211 lines
8.8 KiB
Python
211 lines
8.8 KiB
Python
from migen import *
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from migen.genlib.fifo import *
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from migen.fhdl.specials import Tristate
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from litex.soc.interconnect.csr import *
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import litex
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class MDIOCtrl(Module, AutoCSR):
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def __init__(self, platform):
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div_clk_begin = 39
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div_clk_half = 20
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div_clk_state_change = 2
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sig_mdc = platform.request("sep_mdc");
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sig_mdio = platform.request("sep_mdio");
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mdio_o = Signal()
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mdio_oe = Signal()
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mdio_i = Signal()
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clk_div = Signal(log2_int(div_clk_begin, False))
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int_cnt = Signal(log2_int(32))
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rdata = Signal(32) # DEBUG, should be 16, FIXME
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cmd_recv = Signal()
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self.specials += Tristate(sig_mdio, mdio_o, mdio_oe, mdio_i)
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self.reg_addr = reg_addr = CSRStorage(fields = [CSRField("reg_addr", 5, description = "Reg Addr"),
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CSRField("reserved", 27, description = "Reserved"),])
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self.phy_addr = phy_addr = CSRStorage(fields = [CSRField("phy_addr", 5, description = "Phy Addr"),
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CSRField("reserved", 27, description = "Reserved"),])
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self.mdio_command = mdio_command = CSRStorage(fields = [CSRField("read", 1, description = "Read"),
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CSRField("write", 1, description = "write"),
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CSRField("reserved", 30, description = "Reserved"),])
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self.mdio_status = mdio_status = CSRStatus(fields = [CSRField("access_complete", 1, description = "Phy Addr"),
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CSRField("busy", 1, description = "busy"),
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CSRField("reserved", 30, description = "Reserved"),])
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self.mdio_write = mdio_write = CSRStorage(fields = [CSRField("val", 16, description = "writeval"),
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CSRField("reserved", 16, description = "Reserved"),])
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#self.mdio_read = mdio_read = CSRStatus(fields = [CSRField("val", 16, description = "readval"),
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# CSRField("reserved", 16, description = "Reserved"),])
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self.mdio_read = mdio_read = CSRStatus(fields = [CSRField("val", 32, description = "readval"),]) # DEBUG, should be 16, FIXME
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self.submodules.wishbone_fsm = mdio_fsm = FSM(reset_state = "Reset")
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self.comb += [
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mdio_status.fields.access_complete.eq(mdio_fsm.ongoing("Idle")),
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mdio_status.fields.busy.eq(cmd_recv),
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mdio_read.fields.val.eq(rdata),
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]
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output_data = Signal(32)
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in_preamble = Signal()
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shift_od = Signal()
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self.sync += [
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If(shift_od,
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output_data.eq(Cat(Signal(1, reset = 0), output_data[0:31])),
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),
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]
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self.comb += [
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#If(in_preamble,
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# mdio_o.eq(1),
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#).Else(
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# mdio_o.eq(output_data[31]),
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#),
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mdio_o.eq(in_preamble | output_data[31]),
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]
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shift_rd = Signal()
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shift_rd2 = Signal()
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self.sync += [
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shift_rd2.eq(shift_rd), # delay by one cycle
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If(shift_rd2,
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output_data.eq(Cat(rdata[1:32], Signal(1, reset = 0))), # DEBUG, should be 16, FIXME
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),
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]
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mdc = Signal()
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self.comb += [ sig_mdc.eq(mdc), ]
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self.sync += [
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If(clk_div == 0,
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clk_div.eq(div_clk_begin),
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mdc.eq(1),
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).Else(
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If(clk_div == div_clk_half,
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mdc.eq(0),
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),
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clk_div.eq(clk_div - 1),
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),
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If(mdio_command.re,
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cmd_recv.eq(1),
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),
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]
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write = Signal()
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mdio_fsm.act("Reset",
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NextState("Idle")
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)
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mdio_fsm.act("Idle",
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in_preamble.eq(0),
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mdio_oe.eq(0), # don't drive
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#mdio_oe.eq(1), # drive 0 at idle ?
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If(cmd_recv & (clk_div == div_clk_state_change), # CHECKME
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NextValue(cmd_recv, 0),
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NextValue(write, mdio_command.fields.write),
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NextValue(output_data[0:16], mdio_write.fields.val),
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NextValue(output_data[16:18], 0x2), # TA
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NextValue(output_data[18:23], reg_addr.fields.reg_addr),
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NextValue(output_data[23:28], phy_addr.fields.phy_addr),
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If(mdio_command.fields.write,
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NextValue(output_data[28:30], 0x1), # write
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).Else(
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NextValue(output_data[28:30], 0x2), # read
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NextValue(rdata, 0xFFFFFFFF),
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),
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NextValue(output_data[30:32], 0x1), # start
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in_preamble.eq(1),
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mdio_oe.eq(1),
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NextValue(int_cnt, 31),
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NextState("Preamble"),
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)
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)
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mdio_fsm.act("Preamble",
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in_preamble.eq(1),
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mdio_oe.eq(1),
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If(clk_div == div_clk_state_change, # CHECKME
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If(int_cnt == 0,
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NextValue(int_cnt, 31),
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in_preamble.eq(0), # switch mdio_o to MSb of output_data
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If(write,
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NextState("WData"),
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).Else(
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NextState("RData"),
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),
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).Else(
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NextValue(int_cnt, int_cnt - 1),
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NextState("Preamble"),
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)
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),
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)
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mdio_fsm.act("WData",
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in_preamble.eq(0),
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mdio_oe.eq(1),
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If(clk_div == div_clk_state_change,
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shift_od.eq(1), # so during clk_div == 1, output will move to the next bit
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NextValue(int_cnt, int_cnt - 1),
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If(int_cnt == 0,
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mdio_o.eq(1), # help pull-ups
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# mdio_oe.eq(0), # stop driving
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NextValue(output_data, 0), # make sure it's zero
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NextState("Idle"), ## fixme: delay to idle by one MDC clok cycle?
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)
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),
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)
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mdio_fsm.act("RData",
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in_preamble.eq(0),
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mdio_oe.eq(1),
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If(clk_div == div_clk_state_change,
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shift_od.eq(1), # so during clk_div == div_clk_state_change, output will move to the next bit
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NextValue(int_cnt, int_cnt - 1),
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If(int_cnt == 18,
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mdio_o.eq(1), # help pull-ups
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#mdio_oe.eq(0), # stop driving during TA
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NextState("TA"),
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)
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),
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)
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mdio_fsm.act("TA",
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mdio_oe.eq(0),
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If(clk_div == div_clk_state_change,
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# mdio_oe.eq(0), # stop driving
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NextValue(rdata[15], mdio_i), # DEBUG, will capture on 17 and 16, will be flushed by shifting
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shift_rd.eq(1), # DEBUG, shift in 2 cycles to make room
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NextValue(int_cnt, int_cnt - 1),
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If(int_cnt == 16,
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NextValue(output_data, 0), # make sure it's zero
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NextState("Capture"),
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)
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),
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)
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mdio_fsm.act("Capture",
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mdio_oe.eq(0),
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If(clk_div == div_clk_state_change,
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NextValue(rdata[15], mdio_i),
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NextValue(int_cnt, int_cnt - 1),
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If(int_cnt == 0,
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mdio_oe.eq(0),
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mdio_o.eq(1), # help pull-ups
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NextState("Idle"),
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).Else(
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shift_rd.eq(1), # shift in 2 cycles to make room
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)
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),
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)
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#led0 = platform.request("user_led", 0)
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#led1 = platform.request("user_led", 1)
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#
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#self.comb += [
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# led0.eq(~mdio_fsm.ongoing("Idle")),
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# #led1.eq(clk_div != 0),
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#]
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