187 lines
9.4 KiB
Python
187 lines
9.4 KiB
Python
from migen import *
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from migen.genlib.fifo import *
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import litex
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class NuBus(Module):
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def __init__(self, platform, cd_nubus="nubus", cd_nubus90="nubus90"):
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# unused & unconnected
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# self.nubus_pwf_n = Signal(reset = 1)
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# self.nubus_sp_n = Signal(reset = 1)
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# self.nubus_spv_n = Signal(reset = 1)
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# self.nubus_tm2_n = platform.request("nubus_tm2_n"),
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# memory
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self.mem_valid = Signal()
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self.mem_addr = Signal(32)
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self.mem_wdata = Signal(32)
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self.mem_write = Signal(4)
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self.mem_ready = Signal()
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self.mem_rdata = Signal(32)
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self.mem_error = Signal()
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self.mem_tryagain = Signal()
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# cpu
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self.cpu_valid = Signal(reset = 0)
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self.cpu_addr = Signal(32)
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self.cpu_wdata = Signal(32)
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self.cpu_ready = Signal()
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self.cpu_write = Signal(4)
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self.cpu_rdata = Signal(32)
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self.cpu_lock = Signal()
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self.cpu_eclr = Signal()
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self.cpu_errors = Signal(4)
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# utilities (unused)
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self.mem_stdslot = Signal()
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self.mem_super = Signal()
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self.mem_local = Signal()
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self.add_sources(platform)
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#arbcy_n = platform.request("arbcy_n")
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#grant = platform.request("grant")
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#pad_user_led_0 = platform.request("user_led", 0)
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#pad_user_led_1 = platform.request("user_led", 1)
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#arbcy_n_mem = Signal()
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#grant_mem = Signal()
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#self.sync.nubus += [ arbcy_n_mem.eq(~arbcy_n | arbcy_n_mem) ]
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#self.sync.nubus += [ grant_mem.eq(grant | grant_mem) ]
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#self.comb += pad_user_led_0.eq(arbcy_n_mem)
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#self.comb += pad_user_led_1.eq(grant_mem)
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# FPGA<->CPLD only, now internal signal
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nubus_master_dir = Signal()
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rqst_oe_n = Signal()
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arbcy_n = Signal()
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grant = Signal()
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tmoen = Signal()
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self.nubus_oe = nubus_oe = Signal() # improveme
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# those are needed in both Nubus and cpld integrated part now
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raw_broadcast_id_3v3_n = platform.request("id_3v3_n")
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broadcast_id_3v3_n = Signal(4)
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self.comb += [
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broadcast_id_3v3_n.eq(Cat(raw_broadcast_id_3v3_n, Signal(1, reset = 0))) # add missing ID3 in V1_2
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]
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# those are 'return' signals (O part of IO separated in I and O)
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# the 3v3 signals 'see' the 5V signals from the external drivers
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internal_start_3v3_n = Signal()
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internal_tm0_3v3_n = Signal()
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internal_tm1_3v3_n = Signal()
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internal_tm2_3v3_n = Signal()
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internal_ack_3v3_n = Signal()
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internal_rqst_3v3_n = Signal()
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self.specials += Instance(self.get_netlist_name(),
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# master side
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#p_SIMPLE_MAP = 0x0,
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p_SLOTS_ADDRESS = 0xf,
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p_SUPERSLOTS_ADDRESS = 0x9,
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p_WDT_W = 0x8,
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p_LOCAL_SPACE_EXPOSED_TO_NUBUS = 0,
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i_nub_clkn = ClockSignal(cd_nubus),
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i_nub_resetn = ~ResetSignal(cd_nubus),
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i_nub_idn = broadcast_id_3v3_n, # internal now
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# io_nub_pfwn = self.nubus_pwf_n,
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io_nub_adn = platform.request("ad_3v3_n"),
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i_nub_tm0n = platform.request("tm0_3v3_n"),
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i_nub_tm1n = platform.request("tm1_3v3_n"),
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i_nub_startn = platform.request("start_3v3_n"),
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i_nub_rqstn = platform.request("rqst_3v3_n"),
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i_nub_ackn = platform.request("ack_3v3_n"),
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o_nub_tm0n_o = internal_tm0_3v3_n,
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o_nub_tm1n_o = internal_tm1_3v3_n,
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o_nub_startn_o = internal_start_3v3_n,
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o_nub_rqstn_o = internal_rqst_3v3_n,
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o_nub_ackn_o = internal_ack_3v3_n,
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# io_nub_arbn = platform.request("nubus_arb_n"),
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o_arbcy_n = arbcy_n, # internal now
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i_grant = grant, # internal now
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o_tmoen = tmoen, # internal now
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o_NUBUS_AD_DIR = platform.request("nubus_ad_dir"),
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o_nubus_master_dir = nubus_master_dir, # internal now
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# io_nub_nmrqn = platform.request("nmrq_3v3_n"),
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# io_nub_spn = self.nubus_sp_n,
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# io_nub_spvn = self.nubus_spv_n,
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o_mem_valid = self.mem_valid,
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o_mem_addr = self.mem_addr,
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o_mem_wdata = self.mem_wdata,
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o_mem_write = self.mem_write,
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i_mem_ready = self.mem_ready,
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i_mem_rdata = self.mem_rdata,
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i_mem_error = self.mem_error,
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i_mem_tryagain = self.mem_tryagain,
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i_cpu_valid = self.cpu_valid,
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i_cpu_addr = self.cpu_addr,
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i_cpu_wdata = self.cpu_wdata,
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o_cpu_ready = self.cpu_ready,
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i_cpu_write = self.cpu_write,
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o_cpu_rdata = self.cpu_rdata,
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i_cpu_lock = self.cpu_lock,
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i_cpu_eclr = self.cpu_eclr,
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o_cpu_errors = self.cpu_errors,
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o_mem_stdslot = self.mem_stdslot,
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o_mem_super = self.mem_super,
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o_mem_local = self.mem_local,
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o_fpga_to_cpld_signal = rqst_oe_n, # internal now
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i_nub_clk2xn = ClockSignal(cd_nubus90),
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i_nub_tm2n = platform.request("tm2_3v3_n"),
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o_nub_tm2n_o = internal_tm2_3v3_n,
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)
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self.specials += Instance("nubus_cpldinfpga",
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i_nubus_oe = nubus_oe, # improveme: handled in soc
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i_tmoen = tmoen,
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i_nubus_master_dir = nubus_master_dir,
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i_rqst_oe_n = rqst_oe_n,
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i_id_n_3v3 = broadcast_id_3v3_n, # input only
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i_arbcy_n = arbcy_n,
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i_arb_n_3v3 = platform.request("arb_3v3_n"), # arb only seen by cpld
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o_arb_o_n = platform.request("arb_o_n"),
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o_grant = grant,
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i_tm0_n_3v3 = internal_tm0_3v3_n, # tm0 driving controlled by tmoen
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o_tm0_o_n = platform.request("tm0_o_n"),
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i_tm1_n_3v3 = internal_tm1_3v3_n, # tm1 driving controlled by tmoen
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o_tm1_o_n = platform.request("tm1_o_n"),
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o_tmx_oe_n = platform.request("tmx_oe_n"),
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i_tm2_n_3v3 = internal_tm2_3v3_n, # tm2 currently never driven
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o_tm2_o_n = platform.request("tm2_o_n"),
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o_tm2_oe_n = platform.request("tm2_oe_n"),
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i_start_n_3v3 = internal_start_3v3_n, # start driving enabled by nubus_master_dir
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o_start_o_n = platform.request("start_o_n"),
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o_start_oe_n = platform.request("start_oe_n"),
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i_ack_n_3v3 = internal_ack_3v3_n, # ack driving controlled by tmoen
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o_ack_o_n = platform.request("ack_o_n"),
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o_ack_oe_n = platform.request("ack_oe_n"),
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i_rqst_n_3v3 = internal_rqst_3v3_n, # rqst driving controller by rqst_oe_n
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o_rqst_o_n = platform.request("rqst_o_n")
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)
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def get_netlist_name(self):
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return "nubus"
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def add_sources(self, platform):
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platform.add_source("nubus_V1_2.v", "verilog")
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# XiBus is from my github, branch 'more_fixes'
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platform.add_source("XiBus/nubus.svh", "verilog")
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platform.add_source("nubus_arbiter.v", "verilog") # for CPLDinfpga
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platform.add_source("XiBus/nubus_cpubus.v", "verilog")
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platform.add_source("XiBus/nubus_driver.v", "verilog")
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#platform.add_source("XiBus/nubus_errors.v", "verilog") # unused
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platform.add_source("XiBus/nubus_membus.v", "verilog")
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platform.add_source("XiBus/nubus_master.v", "verilog")
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platform.add_source("XiBus/nubus_slave.v", "verilog")
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platform.add_source("nubus_cpldinfpga.v", "verilog") # internal now
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