326 lines
13 KiB
Verilog
326 lines
13 KiB
Verilog
/*
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* NuBus controller
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*
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* Autor: Valeriya Pudova (hww.github.io)
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* Adapted by Romain Dolbeau <romain@dolbeau.org> for the NuBusFPGA
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* Copyright (c) 2021-2022
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*/
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/* This module is running on the FPGA */
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module nubus
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#(
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// All slots area starts with address $FXXX XXXX
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parameter SLOTS_ADDRESS = 'hF,
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// All superslots starts at $9000 0000
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parameter SUPERSLOTS_ADDRESS = 'h9,
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// Watch dog timer bits. Master controller will terminate transfer
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// after (2 ^ WDT_W) clocks
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parameter WDT_W = 8,
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// Local space of card start and end address. For example 0-5
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// makes local space address $00000000-$50000000
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// UNUSED in NuBusFPGA
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parameter LOCAL_SPACE_EXPOSED_TO_NUBUS = 0,
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parameter LOCAL_SPACE_START = 0,
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parameter LOCAL_SPACE_END = 5
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)
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(
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/* *** NuBus signals *** */
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/* those are connected to the FPGA */
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input nub_clkn, // Clock (rising is driving edge, faling is sampling)
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input nub_resetn, // Reset
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input [ 3:0] nub_idn, // Slot Identification
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// raw input
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input nub_tm0n, // Transfer Mode
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input nub_tm1n, // Transfer Mode
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input nub_startn, // Start
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input nub_rqstn, // Request
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input nub_ackn, // Acknowledge
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// output to other part of the FPGA
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output nub_tm0n_o, // Transfer Mode
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output nub_tm1n_o, // Transfer Mode
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output nub_startn_o, // Start
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output nub_rqstn_o, // Request
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output nub_ackn_o, // Acknowledge
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// NuBus90 (unimplemented)
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input nub_clk2xn,
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input nub_tm2n,
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output nub_tm2n_o,
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/* connected via the 74LVT245 */
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inout [31:0] nub_adn, // Address/Data
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/* those are not used, and not even connected in the board */
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// inout nub_pfwn, // Power Fail Warning
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// inout nub_spn, // System Parity
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// inout nub_spvn, // System Parity Valid
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/* those ared used but handled in directly in the Litex code */
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// output nub_nmrqn, // Non-Master Request, handled in the Litex code
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/* those are used but connected only to the CPLD */
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/* we deal with the CPLD via 'arbcy_n' and 'grant' */
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// inout [ 3:0] nub_arbn, // Arbitration
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/* *** CPLD <-> FPGA signals, not in NuBus */
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output arbcy_n, // request arbitration
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input grant, // arbitration won
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output tmoen, // output enable for tm0/1
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/* *** CPLD <-> FPGA signals, spare, currently unused */
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output fpga_to_cpld_signal, // regular signal
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// inout fpga_to_cpld_signal_2, // regular signal
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// inout fpga_to_cpld_clk, // clk input on CPLD or regular signal
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/* FPGA -> drivers */
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output NUBUS_AD_DIR, // direction for the LS245 (input/output for A/D lines)
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output nubus_master_dir, // are we in master mode (to drive the proper signals)
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/* 'memory bus' signals; those are used to interface with the Wishbone to access the FPGA resources from NuBus */
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output mem_valid,
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output [31:0] mem_addr,
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output [31:0] mem_wdata,
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output [ 3:0] mem_write,
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input mem_ready,
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input [31:0] mem_rdata,
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input mem_error, // ignored
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input mem_tryagain, // ignored
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/* 'processor bus' signals; those are used to interface with the Wishbone to access NuBus resources from the FPGA */
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input cpu_valid,
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input [31:0] cpu_addr,
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input [31:0] cpu_wdata,
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input [ 3:0] cpu_write,
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output cpu_ready,
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output [31:0] cpu_rdata,
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input cpu_lock,
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input cpu_eclr, // ignored
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output [3:0] cpu_errors, // ignored
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/* utilities signal from the NuBus stuff, currently unused */
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// Access to slot area
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output mem_stdslot,
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// Access to superslot area ($sXXXXXXX where <s> is card id)
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output mem_super,
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// Access to local memory on the card
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output mem_local
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);
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`include "nubus.svh"
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// ==========================================================================
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// Colock and reset
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// ==========================================================================
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wire nub_clk = ~nub_clkn;
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wire nub_reset = ~nub_resetn;
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// ==========================================================================
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// Global signals
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// ==========================================================================
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// ===== SLAVE =====
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//wire slv_master;
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wire slv_slave; // output nubus_slave module; input internal ; active during slave cycle
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wire slv_tm1n; // output nubus_slave module; input internal & nubus_membus
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wire slv_tm0n; // output nubus_slave module; input nubus_membus
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wire slv_ackcyn; // output nubus_slave module; input nubus_driver
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wire slv_myslotcy; // output nubus_slave module; input internal & nubus_driver
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wire unsigned [31:0] slv_addr;// output nubus_slave module; input nubus_membus
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// ===== CPU ====
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wire unsigned [31:0] cpu_ad; // output nubus_master; input MUX to A/D lines 'nub_ad' (nub_ad then as an OE and an iverter to reach nub_adn)
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wire cpu_tm1n; // R(h)/W(l); output nubus_cpu; input nubus_driver & internal
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wire cpu_tm0n; // byte size(l); idem
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wire cpu_masterd; // ignored
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// ===== DRIVER =====
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wire drv_tmoen; // output enable for tm0n/tm1n (== tmoen) by nubus_driver
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wire drv_mstdn; // ??? only connected to driver as an output
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// ===== MASTER ===
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wire mst_timeout; // timeout???; output nubus_master; input nubus_driver & nubus_slave
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wire mst_arbcyn; // req. arb; output nubus_master; input internal & to CPLD & nubus_driver
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assign arbcy_n = mst_arbcyn;
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wire mst_adrcyn; // during the address cycle for master; output nubus_master; input nubus_driver & nubus_cpubus
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wire mst_lockedn; // for locked accesses (?); output nubus_master; input nubus_driver
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wire mst_arbdn; // delay during arbitration; output nubus_master; input [NULL] ???
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wire mst_busyn; // busy during transfer; output nubus_master; input [NULL] ???
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wire mst_ownern; // master is bus owner; output nubus_master; input nubus_driver & internal
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wire mst_dtacyn; // during the data cycle for master; output nubus_master; input nubus_driver & internal
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// ==========================================================================
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// Drive NuBus address-data line
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// ==========================================================================
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// Should we be putting the address (instead of data) on the bus [see also nub_adoe]
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// yes during address cycle, or if we're reading (not writing) data
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// actually during write the CPU puts data in cpu_ad so also when writing
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// nub_adoe takes care of the enablement
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wire cpu_adsel = ~mst_adrcyn | ~mst_dtacyn;// & ~cpu_tm1n;
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// Select nubus address or data signals
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wire [31:0] nub_ad = cpu_adsel ? cpu_ad : mem_rdata;
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// Tri-state control for the A/D line
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// nub_adoe is the output enable, when 0 A/D lines are high-impedance
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// Slave: only drive the A/D lines to return data on a read (slave cycle with tm1n high)
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// Master: drives during (a) address cycle
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// (b) data cycle when writing
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wire nub_adoe = slv_slave & slv_tm1n /* SLAVE read of card */
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| cpu_valid & ~mst_adrcyn /* MASTER address cycle*/
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| ~mst_ownern & ~mst_dtacyn & ~cpu_tm1n /* MASTER data cycle, when writing*/
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;
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assign nub_adn = nub_adoe ? ~nub_ad : 'bZ;
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/* for direction */
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assign NUBUS_AD_DIR = ~nub_adoe;
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//assign nubus_master_dir = grant | ~mst_adrcyn | ~mst_arbdn | ~mst_ownern | ~mst_dtacyn;
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assign nubus_master_dir = ~mst_ownern;
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/* for slave access, enable the access during slv_myslotcy*/
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assign mem_valid = slv_myslotcy;
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// ==========================================================================
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// Slave FSM
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// ==========================================================================
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nubus_slave
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#(
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.SLOTS_ADDRESS (SLOTS_ADDRESS),
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.SUPERSLOTS_ADDRESS(SUPERSLOTS_ADDRESS),
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.SIMPLE_MAP(0),
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// UNUSED in NuBusFPGA
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.LOCAL_SPACE_EXPOSED_TO_NUBUS(LOCAL_SPACE_EXPOSED_TO_NUBUS),
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.LOCAL_SPACE_START(LOCAL_SPACE_START),
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.LOCAL_SPACE_END(LOCAL_SPACE_END)
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)
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USlave
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(
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.nub_clkn(nub_clkn), // Clock
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.nub_resetn(nub_resetn), // Reset
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.nub_idn(nub_idn), // Card ID
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.nub_adn(nub_adn), // Address Data
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.nub_startn(nub_startn), // Transfer start
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.nub_ackn(nub_ackn), // Transfer end
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.nub_tm1n(nub_tm1n), // Transition mode 1 (Read/Write)
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.nub_tm0n(nub_tm0n),
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.mem_ready(mem_ready),
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.mst_timeout(mst_timeout),
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.slv_slave_o(slv_slave), // Slave mode
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.slv_tm1n_o(slv_tm1n), // Latched transition mode 1 (Read/Write)
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.slv_tm0n_o(slv_tm0n),
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.slv_ackcyn_o(slv_ackcyn), // Acknowlege
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.slv_addr_o(slv_addr), // Slave address
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.slv_stdslot_o(mem_stdslot), // Starndard slot
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.slv_super_o(mem_super), // Superslot
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.slv_local_o(mem_local), // Local area
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.slv_myslotcy_o(slv_myslotcy) // Any slot
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);
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// ==========================================================================
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// Master FSM
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// ==========================================================================
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nubus_master
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#(
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.WDT_W(WDT_W)
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)
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UMaster
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(
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.nub_clkn(nub_clkn), // Clock
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.nub_resetn(nub_resetn), // Reset
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.nub_rqstn(nub_rqstn), // Bus request
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.nub_startn(nub_startn), // Start transfer
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.nub_ackn(nub_ackn), // End of transfer
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.arb_grant(grant), // Grant access
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.cpu_lock(cpu_lock), // Address line
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.cpu_masterd(cpu_valid), // Master mode (delayed) // FIXME: ignoring cpu_masterd which is always 0 (see below)
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.mst_lockedn_o(mst_lockedn), // Locked or not tranfer
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.mst_arbdn_o(mst_arbdn),
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.mst_busyn_o(mst_busyn),
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.mst_ownern_o(mst_ownern), // Address or data transfer
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.mst_dtacyn_o(mst_dtacyn), // Data strobe
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.mst_adrcyn_o(mst_adrcyn), // Address strobe
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.mst_arbcyn_o(mst_arbcyn), // Arbiter enabled
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.mst_timeout_o(mst_timeout)
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);
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// ==========================================================================
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// Driver Nubus
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// ==========================================================================
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assign tmoen = drv_tmoen;
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nubus_driver UNDriver
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(
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.slv_ackcyn(slv_ackcyn), // Acknowlege
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.mst_arbcyn(mst_arbcyn), // Arbiter enabled
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.mst_adrcyn(mst_adrcyn), // Address strobe
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.mst_dtacyn(mst_dtacyn), // Data strobe
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.mst_ownern(mst_ownern), // Master is owner of the bus
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.mst_lockedn(mst_lockedn), // Locked or not transfer
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.mst_tm1n(cpu_tm1n), // Address lines
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.mst_tm0n(cpu_tm0n), // Address lines
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.mst_timeout(mst_timeout),
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.mis_errorn(TMN_COMPLETE),
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.nub_tm0n_o(nub_tm0n_o), // Transfer mode
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.nub_tm1n_o(nub_tm1n_o), // Transfer mode
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.nub_ackn_o(nub_ackn_o), // Achnowlege
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.nub_startn_o(nub_startn_o), // Transfer start
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.nub_rqstn_o(nub_rqstn_o), // Bus request
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.nub_rqstoen_o(fpga_to_cpld_signal), // Bus request enable
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.drv_tmoen_o(drv_tmoen), // Transfer mode enable
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.drv_mstdn_o(drv_mstdn) // Guess: Slave sends /ACK. Master responds with /MSTDN, which allows slave to clear /ACK and listen for next transaction.
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);
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// ==========================================================================
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// CPU Interface
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// ==========================================================================
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assign cpu_rdata = ~nub_adn;
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assign cpu_ready = ~nub_ackn & nub_startn & ~mst_ownern; // if mst_ownern is inactive (high), then we're seeing the ACK from the previous slave transaction that we were waiting on
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nubus_cpubus UCPUBus
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(
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.nub_clkn(nub_clkn),
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.nub_resetn(nub_resetn),
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.mst_adrcyn(mst_adrcyn),
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.cpu_valid(cpu_valid),
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.cpu_write(cpu_write),
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.cpu_addr(cpu_addr),
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.cpu_wdata(cpu_wdata),
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.cpu_ad_o(cpu_ad),
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.cpu_tm1n_o(cpu_tm1n),
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.cpu_tm0n_o(cpu_tm0n),
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.cpu_error_o(cpu_errors),
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.cpu_masterd_o(cpu_masterd) // FIXME, set to 0 in Xibus nubus_cpubus
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);
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// ==========================================================================
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// Memory Interface
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// ==========================================================================
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nubus_membus UMemBus
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(
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.nub_clkn(nub_clkn), // Clock
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.nub_resetn(nub_resetn), // Reset
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.nub_adn(nub_adn),
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.slv_tm1n(slv_tm1n),
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.slv_tm0n(slv_tm0n),
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.slv_myslotcy(slv_myslotcy),
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.slv_addr(slv_addr),
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.mem_addr_o(mem_addr),
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.mem_write_o(mem_write),
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.mem_wdata_o(mem_wdata)
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);
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endmodule
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