65 lines
1.8 KiB
Verilog
65 lines
1.8 KiB
Verilog
/*
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* Nubus Arbitration logic
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*
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* ARB is responsible for doing the NuBus arbitration logic. Upon
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* detecting any higher priority ARB<3:0> value, it will defer its
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* generation of lower ARB<3:0> bits.
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* The GRANT signal must be timed externally to determine proper
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* NuBus constraints.
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* This version uses a new technique to minimize skews.
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*
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* Modified from the XiBus version to support external drivers in the NuBusFPGA
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*/
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module nubus_arbiter
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(
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input [3:0] idn, // ID of this card
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input [3:0] arbn, // NuBus arbiter's lines (input)
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output [3:0] arbon, // NuBus arbiter's lines (control)
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input arbcyn, // enable arbitter
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output grant // Grant access
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);
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wire arb2oen, arb1oen, arb0oen;
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wire arb3, arb2, arb1, arb0;
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wire grantn;
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assign arbon[3] = ~arb3;
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assign arbon[2] = ~arb2;
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assign arbon[1] = ~arb1;
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assign arbon[0] = ~arb0;
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// ------------------------------------------
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assign arb3 = ~arbcyn & ~idn[3];
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assign arb2oen = idn[3] & ~arbn[3];
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// ------------------------------------------
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assign arb2 = ~arbcyn & ~arb2oen & ~idn[2];
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assign arb1oen = idn[3] & ~arbn[3] |
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idn[2] & ~arbn[2];
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// ------------------------------------------
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assign arb1 = ~arbcyn & ~arb1oen & ~idn[1];
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assign arb0oen = idn[3] & ~arbn[3] |
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idn[2] & ~arbn[2] |
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idn[1] & ~arbn[1];
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// ------------------------------------------
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assign arb0 = ~arbcyn & ~arb0oen & ~idn[0];
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assign grantn = idn[3] & ~arbn[3] |
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idn[2] & ~arbn[2] |
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idn[1] & ~arbn[1] |
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idn[0] & ~arbn[0];
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assign grant = ~arbcyn & ~grantn;
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endmodule
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