119 lines
4.9 KiB
Python
119 lines
4.9 KiB
Python
from migen import *
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from migen.genlib.fifo import *
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import litex
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from litex.soc.interconnect import wishbone
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class PingMaster(Module):
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def __init__(self, nubus, platform):
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self.bus_slv = bus_slv = wishbone.Interface()
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self.bus_mst = bus_mst = wishbone.Interface()
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#led0 = platform.request("user_led", 0)
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#led1 = platform.request("user_led", 1)
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valu_reg = Signal(32)
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waddr_reg = Signal(32)
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raddr_reg = Signal(32)
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writ_del = Signal(6)
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read_del = Signal(6)
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do_write = Signal()
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do_read = Signal()
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#waddr_reg_rev = Signal(32)
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#self.comb += [ waddr_reg_rev[ 0: 8].eq(waddr_reg[24:32]),
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# waddr_reg_rev[ 8:16].eq(waddr_reg[16:24]),
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# waddr_reg_rev[16:24].eq(waddr_reg[ 8:16]),
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# waddr_reg_rev[24:32].eq(waddr_reg[ 0: 8]), ]
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self.sync += [ If(writ_del != 0,
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writ_del.eq(writ_del - 1),),
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If(writ_del == 1,
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do_write.eq(1),
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),
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If(read_del != 0,
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read_del.eq(read_del - 1),),
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If(read_del == 1,
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do_read.eq(1),
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)
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]
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self.submodules.wishbone_fsm = wishbone_fsm = FSM(reset_state = "Reset")
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wishbone_fsm.act("Reset",
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NextValue(bus_slv.ack, 0),
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NextState("Idle"))
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wishbone_fsm.act("Idle",
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If(bus_slv.cyc & bus_slv.stb & bus_slv.we & ~bus_slv.ack, #write
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# FIXME: should check for prefix?
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Case(bus_slv.adr[0:2], {
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0x0: [ NextValue(valu_reg, bus_slv.dat_w[0:32]), ],
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0x1: [ NextValue(waddr_reg, bus_slv.dat_w[0:32]),
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NextValue(writ_del, 3), ],
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0x2: [ NextValue(raddr_reg, bus_slv.dat_w[0:32]),
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NextValue(read_del, 3), ],
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}),
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NextValue(bus_slv.ack, 1),
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).Elif(bus_slv.cyc & bus_slv.stb & ~bus_slv.we & ~bus_slv.ack, #read
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Case(bus_slv.adr[0:2], {
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0x0: [ NextValue(bus_slv.dat_r, valu_reg), ],
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0x1: [ NextValue(bus_slv.dat_r, waddr_reg), ],
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0x2: [ NextValue(bus_slv.dat_r, raddr_reg), ],
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}),
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NextValue(bus_slv.ack, 1),
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).Else(
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NextValue(bus_slv.ack, 0),
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)
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)
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self.submodules.writer_fsm = writer_fsm = FSM(reset_state = "Reset")
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writer_fsm.act("Reset",
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NextState("Idle"),)
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writer_fsm.act("Idle",
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If(do_write,
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NextValue(do_write, 0),
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bus_mst.cyc.eq(1),
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bus_mst.stb.eq(1),
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bus_mst.we.eq(1),
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bus_mst.dat_w.eq(valu_reg),
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bus_mst.adr.eq(waddr_reg[2:32]),
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bus_mst.sel.eq(0xf),
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If(bus_mst.ack,
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NextState("Idle")
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).Else(
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NextState("Write")
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)
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).Elif(do_read,
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NextValue(do_read, 0),
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bus_mst.cyc.eq(1),
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bus_mst.stb.eq(1),
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bus_mst.we.eq(0),
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bus_mst.adr.eq(raddr_reg[2:32]),
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bus_mst.sel.eq(0xf),
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NextState("Read"),
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)
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)
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writer_fsm.act("Write",
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bus_mst.cyc.eq(1),
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bus_mst.stb.eq(1),
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bus_mst.we.eq(1),
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bus_mst.dat_w.eq(valu_reg),
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bus_mst.adr.eq(waddr_reg[2:32]),
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bus_mst.sel.eq(0xf),
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If(bus_mst.ack,
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NextState("Idle")
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),
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)
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writer_fsm.act("Read",
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bus_mst.cyc.eq(1),
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bus_mst.stb.eq(1),
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bus_mst.we.eq(0),
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bus_mst.adr.eq(raddr_reg[2:32]),
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bus_mst.sel.eq(0xf),
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If(bus_mst.ack,
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NextValue(valu_reg, bus_mst.dat_r),
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NextState("Idle")
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),
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)
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#self.comb += [ led0.eq(bus_mst.cyc),
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# led1.eq(writ_del != 0), ]
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