115 lines
4.9 KiB
Python
115 lines
4.9 KiB
Python
from migen import *
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from migen.genlib.fifo import *
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import litex
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from litex.soc.interconnect import wishbone
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from migen.genlib.cdc import BusSynchronizer
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class NuBus2WishboneFIFO(Module):
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def __init__(self, platform, nubus, wb_read, wb_write):
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# memory
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# nubus.mem_valid
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# nubus.mem_addr
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# nubus.mem_wdata
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# nubus.mem_write
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# nubus.mem_ready
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# nubus.mem_rdata
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#nubus.mem_error
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#nubus.mem_tryagain
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assert(len(wb_read.dat_r) == 32)
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assert(len(nubus.mem_wdata) == 32)
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assert(len(nubus.mem_write) == 4)
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write_fifo_layout = [
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("adr", 32),
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("data", 32),
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("sel", 4),
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]
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self.submodules.write_fifo = write_fifo = ClockDomainsRenamer({"read": "sys", "write": "nubus"})(AsyncFIFOBuffered(width=layout_len(write_fifo_layout), depth=8))
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write_fifo_dout = Record(write_fifo_layout)
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self.comb += write_fifo_dout.raw_bits().eq(write_fifo.dout)
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write_fifo_din = Record(write_fifo_layout)
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self.comb += write_fifo.din.eq(write_fifo_din.raw_bits())
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self.comb += wb_read.cyc.eq(nubus.mem_valid & (nubus.mem_write == 0)) # only handle reads
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self.comb += wb_read.stb.eq(nubus.mem_valid & (nubus.mem_write == 0)) # only handle reads
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self.comb += wb_read.we.eq(0) #(nubus.mem_write != 0)
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self.comb += [
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If(~nubus.mem_addr[23], # first 8 MiB of slot space: remap to last 8 Mib of SDRAM
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wb_read.adr.eq(Cat(nubus.mem_addr[2:23], Signal(1, reset=1), Signal(8, reset = 0x8f))), # 0x8f8...
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).Else( # second 8 MiB: direct access
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wb_read.adr.eq(Cat(nubus.mem_addr[2:24], Signal(8, reset = 0xf0)))), # 24 bits, a.k.a 22 bits of words
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]
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#self.comb += If(nubus.mem_write == 0,
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# wb_read.sel.eq(0xF)).Else(
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# wb_read.sel.eq(nubus.mem_write))
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self.comb += [
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#wb_read.dat_w.eq(nubus.mem_wdata),
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wb_read.sel.eq(0xF),
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nubus.mem_rdata.eq(wb_read.dat_r),
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]
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write_ack = Signal()
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self.comb += nubus.mem_ready.eq(wb_read.ack | write_ack)
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self.comb += nubus.mem_error.eq(0) # FIXME: TODO: ???
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self.comb += nubus.mem_tryagain.eq(0) # FIXME: TODO: ???
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#led0 = platform.request("user_led", 0)
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#led1 = platform.request("user_led", 1)
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#self.comb += [ led0.eq(wb_read.ack),
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# led1.eq(write_ack), ]
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#self.submodules.write_fsm = write_fsm = FSM(reset_state = "Reset")
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#write_fsm.act("Reset",
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# NextState("Idle"))
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#write_fsm.act("Idle",)
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# in NuBus
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#self.comb += [ write_fifo.we.eq(write_fifo.writable & nubus.mem_valid & (nubus.mem_write != 0)),
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# write_ack.eq(write_fifo.writable & nubus.mem_valid & (nubus.mem_write != 0))
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#]
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#self.comb += [ write_fifo_din.adr.eq(nubus.mem_addr),
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# write_fifo_din.data.eq(nubus.mem_wdata),
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# write_fifo_din.sel.eq(nubus.mem_write),
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#]
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self.submodules.write_fsm = write_fsm = ClockDomainsRenamer("nubus")(FSM(reset_state = "Reset"))
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write_fsm.act("Reset",
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NextState("Idle"))
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write_fsm.act("Idle",
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If(nubus.mem_valid & (nubus.mem_write != 0), # & write_fifo.writable),
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NextState("WriteFifo"),
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)
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)
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write_fsm.act("WriteFifo",
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write_fifo.we.eq(1),
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write_ack.eq(1), # the one cycle delay is needed for the tmO -> nubus.mem_write -> ack dependency chain
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NextState("WaitForNuBus"),
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)
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write_fsm.act("WaitForNuBus",
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If(~nubus.mem_valid,
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NextState("Idle"),
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)
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)
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self.comb += [ write_fifo_din.adr.eq(nubus.mem_addr),
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write_fifo_din.data.eq(nubus.mem_wdata),
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write_fifo_din.sel.eq(nubus.mem_write),
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]
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self.comb += [ wb_write.cyc.eq(write_fifo.readable),
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wb_write.stb.eq(write_fifo.readable),
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wb_write.we.eq(1),
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If(~write_fifo_dout.adr[23], # first 8 MiB of slot space: remap to last 8 Mib of SDRAM
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wb_write.adr.eq(Cat(write_fifo_dout.adr[2:23], Signal(1, reset=1), Signal(8, reset = 0x8f))), # 0x8f8...
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).Else( # second 8 MiB: direct access
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wb_write.adr.eq(Cat(write_fifo_dout.adr[2:24], Signal(8, reset = 0xf0)))), # 24 bits, a.k.a 22 bits of words
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wb_write.dat_w.eq(write_fifo_dout.data),
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wb_write.sel.eq(write_fifo_dout.sel),
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write_fifo.re.eq(wb_write.ack),
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]
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