113 lines
3.5 KiB
Verilog
113 lines
3.5 KiB
Verilog
/*
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* NuBus sampling
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*
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* Romain Dolbeau <romain@dolbeau.org> for the NuBusFPGA
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* Copyright (c) 2021022
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*/
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/* This module is running on the FPGA */
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module nubus_sampling
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(
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/* *** NuBus signals *** */
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/* those are connected to the FPGA */
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/* connected via the CPLD */
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input nub_clkn, // Clock (rising is driving edge, faling is sampling)
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input nub_resetn, // Reset
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//input [ 3:0] nub_idn, // Slot Identification
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input nub_tm0n, // Transfer Mode
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input nub_tm1n, // Transfer Mode
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input nub_startn, // Start
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input nub_rqstn, // Request
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input nub_ackn, // Acknowledge
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// connected via the CPLD but NuBus90 (unimplemented)
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//input nub_clk2xn,
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//inout nub_tm2n,
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/* connected via the 74LVT245 */
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input [31:0] nub_adn, // Address/Data
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/* those are not used, and not even connected in the board */
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// inout nub_pfwn, // Power Fail Warning
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// inout nub_spn, // System Parity
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// inout nub_spvn, // System Parity Valid
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/* those ared used but handled in directly in the Litex code */
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// output nub_nmrqn, // Non-Master Request, handled in the Litex code
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/* those are used but connected only to the CPLD */
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/* we deal with the CPLD via 'arbcy_n' and 'grant' */
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// inout [ 3:0] nub_arbn, // Arbitration
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output tm0,
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output tm1,
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output start,
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output rqst,
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output ack,
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output [31:0] ad,
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output [3:0] sel,
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output block,
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output busy
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);
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reg reg_tm0n, reg_tm1n;
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reg reg_startn;
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reg reg_rqstn;
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reg reg_ackn;
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reg [31:0] reg_adn;
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reg reg_busy;
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always @(negedge nub_clkn) begin: proc_sampling
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if (~nub_resetn) begin
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reg_tm0n <= 1;
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reg_tm1n <= 1;
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reg_startn <= 1;
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reg_rqstn <= 1;
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reg_ackn <= 1;
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reg_adn <= 0;
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reg_busy <= 0;
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end else begin
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reg_tm0n <= nub_tm0n;
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reg_tm1n <= nub_tm1n;
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reg_startn <= nub_startn;
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reg_rqstn <= nub_rqstn;
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reg_ackn <= nub_ackn;
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reg_adn <= nub_adn;
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reg_busy <= ~reg_busy & nub_ackn & ~nub_startn /* beginning of transaction */
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| reg_busy & nub_ackn & nub_resetn; /* hold during cycle */
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end
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end
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assign tm0 = ~reg_tm0n;
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assign tm1 = ~reg_tm1n;
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assign start = ~reg_startn;
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assign rqst = ~reg_rqstn;
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assign ack = ~reg_ackn;
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assign ad = ~reg_adn;
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assign busy = reg_busy;
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// write selector for Wishbone
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assign sel[3] = ~reg_tm1n & ~reg_adn[1] & ~reg_adn[0] & ~reg_tm0n /* Byte 3 */
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| ~reg_tm1n & ~reg_adn[1] & ~reg_adn[0] & reg_tm0n /* Half 1 */
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| ~reg_tm1n & reg_adn[1] & reg_adn[0] & reg_tm0n /* Word */
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;
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assign sel[2] = ~reg_tm1n & ~reg_adn[1] & reg_adn[0] & ~reg_tm0n /* Byte 2 */
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| ~reg_tm1n & ~reg_adn[1] & ~reg_adn[0] & reg_tm0n /* Half 1 */
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| ~reg_tm1n & reg_adn[1] & reg_adn[0] & reg_tm0n /* Word */
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;
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assign sel[1] = ~reg_tm1n & reg_adn[1] & ~reg_adn[0] & ~reg_tm0n /* Byte 1 */
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| ~reg_tm1n & reg_adn[1] & ~reg_adn[0] & reg_tm0n /* Half 0 */
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| ~reg_tm1n & reg_adn[1] & reg_adn[0] & reg_tm0n /* Word */
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;
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assign sel[0] = ~reg_tm1n & reg_adn[1] & reg_adn[0] & ~reg_tm0n /* Byte 0 */
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| ~reg_tm1n & reg_adn[1] & ~reg_adn[0] & reg_tm0n /* Half 0 */
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| ~reg_tm1n & reg_adn[1] & reg_adn[0] & reg_tm0n /* Word */
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;
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assign block = ~reg_adn[1] & reg_adn[0] & reg_tm0n; // 1x block write or 1x block read
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endmodule
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