510 lines
28 KiB
Python
510 lines
28 KiB
Python
import os
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import argparse
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from migen import *
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from migen.genlib.fifo import *
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from migen.fhdl.specials import Tristate
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import litex
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from litex.build.generic_platform import *
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.integration.soc import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.clock import *
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from litex.soc.cores.led import LedChaser
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import ztex213_nubus
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import nubus_to_fpga_export
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import nubus_full_unified
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import nubus_stat
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from litedram.frontend.dma import *
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from liteeth.phy.rmii import LiteEthPHYRMII
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from migen.genlib.cdc import BusSynchronizer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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# Wishbone stuff
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from VintageBusFPGA_Common.cdc_wb import WishboneDomainCrossingMaster
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from VintageBusFPGA_Common.fpga_blk_dma import *
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from VintageBusFPGA_Common.fpga_sd_dma import *
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from VintageBusFPGA_Common.MacPeriphSoC import *
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from nubus_mem_wb import NuBus2Wishbone
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from nubus_memfifo_wb import NuBus2WishboneFIFO
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from nubus_cpu_wb import Wishbone2NuBus
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module, AutoCSR): # AutoCSR for DRP
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def __init__(self, platform, version, sys_clk_freq,
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goblin=False,
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hdmi=False,
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pix_clk=0,
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ethernet=False):
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self.clock_domains.cd_sys = ClockDomain() # 100 MHz PLL, reset'ed by NuBus (via pll), SoC/Wishbone main clock
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_native = ClockDomain(reset_less=True) # 48MHz native, non-reset'ed (for power-on long delay, never reset, we don't want the delay after a warm reset)
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self.clock_domains.cd_nubus = ClockDomain() # 10 MHz NuBus, reset'ed by NuBus, native NuBus clock domain (25% duty cycle)
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self.clock_domains.cd_nubus90 = ClockDomain() # 20 MHz NuBus90, reset'ed by NuBus, native NuBus90 clock domain (25% duty cycle)
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if (goblin):
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if (not hdmi):
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self.clock_domains.cd_vga = ClockDomain(reset_less=True)
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else:
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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if (ethernet):
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self.clock_domains.cd_eth = ClockDomain()
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# # #
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clk48 = platform.request("clk48")
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###### explanations from betrusted-io/betrusted-soc/betrusted_soc.py
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# Note: below feature cannot be used because Litex appends this *after* platform commands! This causes the generated
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# clock derived constraints immediately below to fail, because .xdc file is parsed in-order, and the main clock needs
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# to be created before the derived clocks. Instead, we use the line afterwards.
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platform.add_platform_command("create_clock -name clk48 -period 20.8333 [get_nets clk48]")
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# The above constraint must strictly proceed the below create_generated_clock constraints in the .XDC file
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# This allows PLLs/MMCMEs to be placed anywhere and reference the input clock
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self.clk48_bufg = Signal()
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self.specials += Instance("BUFG", i_I=clk48, o_O=self.clk48_bufg)
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self.comb += self.cd_native.clk.eq(self.clk48_bufg)
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#self.cd_native.clk = clk48
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##### V1.2 extra clock for B34
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if (version == "V1.2"):
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self.clock_domains.cd_bank34 = ClockDomain()
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clk54 = platform.request("clk54")
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platform.add_platform_command("create_clock -name clk54 -period 18.51851851851851851 [get_nets clk54]")
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self.clk54_bufg = Signal()
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self.specials += Instance("BUFG", i_I=clk54, o_O=self.clk54_bufg)
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self.comb += self.cd_bank34.clk.eq(self.clk54_bufg)
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else:
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clk54 = None
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clk_nubus = platform.request("clk_3v3_n")
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if (clk_nubus is None):
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print(" ***** ERROR ***** Can't find the NuBus Clock !!!!\n");
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assert(false)
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self.cd_nubus.clk = clk_nubus
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rst_nubus_n = platform.request("reset_3v3_n")
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self.comb += self.cd_nubus.rst.eq(~rst_nubus_n)
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platform.add_platform_command("create_clock -name nubus_clk -period 100.0 -waveform {{0.0 75.0}} [get_ports clk_3v3_n]")
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clk2x_nubus = platform.request("clk2x_3v3_n")
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if (clk2x_nubus is None):
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print(" ***** ERROR ***** Can't find the NuBus90 Clock !!!!\n");
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assert(false)
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self.cd_nubus90.clk = clk2x_nubus
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self.comb += self.cd_nubus90.rst.eq(~rst_nubus_n)
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platform.add_platform_command("create_clock -name nubus90_clk -period 50.0 -waveform {{0.0 25}} [get_ports clk2x_3v3_n]")
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num_adv = 0
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num_clk = 0
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self.submodules.pll = pll = S7MMCM(speedgrade=platform.speedgrade)
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#pll.register_clkin(clk48, 48e6)
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pll.register_clkin(self.clk48_bufg, 48e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_platform_command("create_generated_clock -name sysclk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
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num_clk = num_clk + 1
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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platform.add_platform_command("create_generated_clock -name sys4xclk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
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num_clk = num_clk + 1
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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platform.add_platform_command("create_generated_clock -name sys4x90clk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
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num_clk = num_clk + 1
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if (ethernet):
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pll.create_clkout(self.cd_eth, 50e6, phase=90) # fixme: what if sys_clk_feq != 100e6? # why phase ???
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platform.add_platform_command("create_generated_clock -name ethclk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
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num_clk = num_clk + 1
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self.comb += pll.reset.eq(~rst_nubus_n) # | ~por_done
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platform.add_false_path_constraints(clk48, self.cd_nubus.clk) # FIXME?
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platform.add_false_path_constraints(self.cd_nubus.clk, clk48) # FIXME?
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#platform.add_false_path_constraints(self.cd_sys.clk, self.cd_nubus.clk)
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#platform.add_false_path_constraints(self.cd_nubus.clk, self.cd_sys.clk)
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##platform.add_false_path_constraints(self.cd_native.clk, self.cd_sys.clk)
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num_adv = num_adv + 1
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num_clk = 0
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self.submodules.pll_idelay = pll_idelay = S7MMCM(speedgrade=platform.speedgrade)
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#pll_idelay.register_clkin(clk48, 48e6)
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pll_idelay.register_clkin(self.clk48_bufg, 48e6)
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pll_idelay.create_clkout(self.cd_idelay, 200e6, margin = 0)
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platform.add_platform_command("create_generated_clock -name idelayclk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
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num_clk = num_clk + 1
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self.comb += pll_idelay.reset.eq(~rst_nubus_n) # | ~por_done
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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num_adv = num_adv + 1
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num_clk = 0
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if (goblin):
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self.submodules.video_pll = video_pll = S7MMCM(speedgrade=platform.speedgrade)
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if (clk54 is None):
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# no 54 MHz clock, drive hdmi from the main clock
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video_pll.register_clkin(self.clk48_bufg, 48e6)
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else:
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# drive hdmi from the 54 MHz clock, easier to generate e.g. 148.5 MHz
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video_pll.register_clkin(self.clk54_bufg, 54e6)
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platform.add_false_path_constraints(self.cd_bank34.clk, self.cd_nubus.clk) # FIXME?
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platform.add_false_path_constraints(self.cd_bank34.clk, clk48) # FIXME?
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if (not hdmi):
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video_pll.create_clkout(self.cd_vga, pix_clk, margin = 0.0005)
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platform.add_platform_command("create_generated_clock -name vga_clk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
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num_clk = num_clk + 1
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else:
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video_pll.create_clkout(self.cd_hdmi, pix_clk, margin = 0.005)
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video_pll.create_clkout(self.cd_hdmi5x, 5*pix_clk, margin = 0.005)
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platform.add_platform_command("create_generated_clock -name hdmi_clk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
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num_clk = num_clk + 1
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platform.add_platform_command("create_generated_clock -name hdmi5x_clk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
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num_clk = num_clk + 1
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video_pll.expose_drp()
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self.comb += video_pll.reset.eq(~rst_nubus_n)
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#platform.add_false_path_constraints(self.cd_sys.clk, self.cd_vga.clk)
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platform.add_false_path_constraints(self.cd_sys.clk, video_pll.clkin)
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num_adv = num_adv + 1
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num_clk = 0
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class NuBusFPGA(MacPeriphSoC):
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def __init__(self, variant, version, sys_clk_freq, goblin, hdmi, goblin_res, use_goblin_alt, sdcard, flash, config_flash, ethernet, **kwargs):
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print(f"Building NuBusFPGA for board version {version}")
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self.platform = platform = ztex213_nubus.Platform(variant = variant, version = version)
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if (flash and (version == "V1.2")):
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platform.add_extension(ztex213_nubus._flashtemp_pmod_io_v1_2)
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if (ethernet and (version == "V1.2")):
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platform.add_extension(ztex213_nubus._rmii_eth_extpmod_io_v1_2)
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MacPeriphSoC.__init__(self,
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platform=platform,
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sys_clk_freq=sys_clk_freq,
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csr_paging=0x800, # default is 0x800
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bus_interconnect = "crossbar",
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goblin = goblin,
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hdmi = hdmi,
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goblin_res = goblin_res,
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use_goblin_alt = use_goblin_alt,
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**kwargs)
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self.mem_map.update(self.wb_mem_map)
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self.submodules.crg = _CRG(platform=platform, version=version, sys_clk_freq=sys_clk_freq, goblin=goblin, hdmi=hdmi, pix_clk=litex.soc.cores.video.video_timings[goblin_res]["pix_clk"], ethernet=ethernet)
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## add our custom timings after the clocks have been defined
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xdc_timings_filename = None;
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#if (version == "V1.0"):
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# xdc_timings_filename = "/home/dolbeau/nubus-to-ztex-gateware/nubus_fpga_V1_0_timings.xdc"
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if (version == "V1.2"):
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xdc_timings_filename = "nubus_fpga_V1_2_timings.xdc"
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if (xdc_timings_filename != None):
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xdc_timings_file = open(xdc_timings_filename)
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xdc_timings_lines = xdc_timings_file.readlines()
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for line in xdc_timings_lines:
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if (line[0:3] == "set"):
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fix_line = line.strip().replace("{", "{{").replace("}", "}}")
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#print(fix_line)
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platform.add_platform_command(fix_line)
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MacPeriphSoC.mac_add_declrom(self, version = version, flash = flash, config_flash = config_flash)
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MacPeriphSoC.mac_add_sdram(self, hwinit = False)
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if (goblin):
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MacPeriphSoC.mac_add_goblin_prelim(self)
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# don't enable anything on the NuBus side for XX seconds after power up
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# this avoids FPGA initialization messing with the cold boot process
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# requires us to reset the Macintosh afterward so the FPGA board
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# is properly identified
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# This is in the 'native' ClockDomain that is never reset
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# not needed, FPGA initializes fast enough, works on cold boots
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#hold_reset_ctr = Signal(30, reset=960000000)
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hold_reset_ctr = Signal(5, reset=31)
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self.sync.native += If(hold_reset_ctr>0, hold_reset_ctr.eq(hold_reset_ctr - 1))
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self.hold_reset = hold_reset = Signal() # in reset if high, out-of-reset if low
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self.comb += hold_reset.eq(~(hold_reset_ctr == 0))
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pad_nubus_oe = platform.request("nubus_oe")
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self.comb += pad_nubus_oe.eq(hold_reset)
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#pad_user_led_0 = platform.request("user_led", 0)
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#self.comb += pad_user_led_0.eq(~hold_reset)
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# Interface NuBus to wishbone
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# we need to cross clock domains
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# Xibus is the original VErilog implementation I used
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# mostly only for testing now, it doesn't have block mode so doesn't support the DMA mode of the RAM disk
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# Should be set to False unless for testing (usually with notsimul=False)
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xibus=False
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if (xibus):
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wishbone_master_sys = wishbone.Interface(data_width=self.bus.data_width)
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self.submodules.wishbone_master_nubus = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="nubus", cd_slave="sys")
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self.bus.add_master(name="NuBusBridgeToWishbone", master=wishbone_master_sys)
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if (version == "V1.0"):
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from nubus_V1_0 import NuBus
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elif (version == "V1.2"):
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from nubus_V1_2 import NuBus
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self.submodules.nubus = NuBus(platform=platform, cd_nubus="nubus")
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#self.submodules.nubus2wishbone = ClockDomainsRenamer("nubus")(NuBus2Wishbone(nubus=self.nubus,wb=self.wishbone_master_nubus))
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if (version == "V1.2"):
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self.comb += self.nubus.nubus_oe.eq(hold_reset) # improveme
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nubus_writemaster_sys = wishbone.Interface(data_width=self.bus.data_width)
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self.submodules.nubus2wishbone = NuBus2WishboneFIFO(platform=self.platform,nubus=self.nubus,wb_read=self.wishbone_master_nubus,wb_write=nubus_writemaster_sys)
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self.bus.add_master(name="NuBusBridgeToWishboneWrite", master=nubus_writemaster_sys)
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wishbone_slave_nubus = wishbone.Interface(data_width=self.bus.data_width)
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self.submodules.wishbone2nubus = ClockDomainsRenamer("nubus")(Wishbone2NuBus(nubus=self.nubus,wb=wishbone_slave_nubus))
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self.submodules.wishbone_slave_sys = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_slave_nubus, cd_master="sys", cd_slave="nubus")
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self.bus.add_slave("DMA", self.wishbone_slave_sys, SoCRegion(origin=self.mem_map.get("master", None), size=0x40000000, cached=False))
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irq_line = self.platform.request("nmrq_3v3_n") # active low
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fb_irq = Signal() # active low
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#led0 = platform.request("user_led", 0)
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#self.comb += [
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# led0.eq(~fb_irq),
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#]
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self.comb += irq_line.eq(fb_irq) # active low, enable if one is low
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else:
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# details for usesampling in the NuBus python object
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usesampling = False
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wishbone_master_sys = wishbone.Interface(data_width=self.bus.data_width)
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if (not usesampling): # we need an extra CDC
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self.submodules.wishbone_master_nubus = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="nubus", cd_slave="sys") # for non-sampling only
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nubus_writemaster_sys = wishbone.Interface(data_width=self.bus.data_width)
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wishbone_slave_nubus = wishbone.Interface(data_width=self.bus.data_width)
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self.submodules.wishbone_slave_sys = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_slave_nubus, cd_master="sys", cd_slave="nubus", force_delay=9) # force delay needed to avoid back-to-back transaction running into issue https://github.com/alexforencich/verilog-wishbone/issues/4
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#led0 = platform.request("user_led", 0)
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#led1 = platform.request("user_led", 1)
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#self.comb += [ led0.eq(self.wishbone_slave_sys.stb),
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# led1.eq(self.wishbone_slave_sys.cyc), ]
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burst_size=4
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data_width = burst_size * 4
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data_width_bits = burst_size * 32
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blk_addr_width = 32 - log2_int(data_width)
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self.tosbus_layout = [
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("address", 32),
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("data", data_width_bits),
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]
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self.fromsbus_layout = [
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("blkaddress", blk_addr_width),
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("data", data_width_bits),
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]
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self.fromsbus_req_layout = [
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("blkaddress", blk_addr_width),
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("dmaaddress", 32),
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]
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irq_line = self.platform.request("nmrq_3v3_n") # active low
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fb_irq = Signal(reset = 1) # active low
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dma_irq = Signal(reset = 1) # active low
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audio_irq = Signal(reset = 1) # active low
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#led0 = platform.request("user_led", 0)
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#led1 = platform.request("user_led", 1)
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#self.comb += [
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# led0.eq(~fb_irq),
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# led1.eq(~dma_irq),
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#]
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self.comb += irq_line.eq(fb_irq & dma_irq & audio_irq) # active low, enable if one is low
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self.submodules.tosbus_fifo = ClockDomainsRenamer({"read": "nubus", "write": "sys"})(AsyncFIFOBuffered(width=layout_len(self.tosbus_layout), depth=1024//data_width))
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self.submodules.fromsbus_fifo = ClockDomainsRenamer({"write": "nubus", "read": "sys"})(AsyncFIFOBuffered(width=layout_len(self.fromsbus_layout), depth=512//data_width))
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self.submodules.fromsbus_req_fifo = ClockDomainsRenamer({"read": "nubus", "write": "sys"})(AsyncFIFOBuffered(width=layout_len(self.fromsbus_req_layout), depth=512//data_width))
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#if (not sdcard): # fixme: temporay exclusion
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self.submodules.exchange_with_mem = ExchangeWithMem(soc=self,
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platform=platform,
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tosbus_fifo=self.tosbus_fifo,
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fromsbus_fifo=self.fromsbus_fifo,
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fromsbus_req_fifo=self.fromsbus_req_fifo,
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dram_native_r=self.sdram.crossbar.get_port(mode="read", data_width=data_width_bits),
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dram_native_w=self.sdram.crossbar.get_port(mode="write", data_width=data_width_bits),
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mem_size=self.avail_sdram//1048576,
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burst_size=burst_size,
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do_checksum = False,
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clock_domain="nubus")
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self.comb += dma_irq.eq(self.exchange_with_mem.irq)
|
||
#else:
|
||
# self.add_sdcard_custom()
|
||
# self.submodules.exchange_with_sd = ExchangeWithSD(soc=self,
|
||
# platform=platform,
|
||
# tosbus_fifo=self.tosbus_fifo,
|
||
# fromsbus_fifo=self.fromsbus_fifo,
|
||
# fromsbus_req_fifo=self.fromsbus_req_fifo,
|
||
# sd_source=self.sdcore.source,
|
||
# sd_sink=self.sdcore.sink,
|
||
# burst_size=burst_size,
|
||
# clock_domain="nubus")
|
||
# self.comb += dma_irq.eq(self.exchange_with_sd.irq)
|
||
|
||
|
||
self.submodules.nubus = nubus_full_unified.NuBus(soc=self,
|
||
version=version,
|
||
burst_size=burst_size,
|
||
tosbus_fifo=self.tosbus_fifo,
|
||
fromsbus_fifo=self.fromsbus_fifo,
|
||
fromsbus_req_fifo=self.fromsbus_req_fifo,
|
||
wb_read=(wishbone_master_sys if usesampling else self.wishbone_master_nubus), # CDC or not
|
||
wb_write=nubus_writemaster_sys,
|
||
wb_dma=wishbone_slave_nubus,
|
||
usesampling=usesampling,
|
||
cd_nubus="nubus")
|
||
|
||
self.bus.add_master(name="NuBusBridgeToWishbone", master=wishbone_master_sys)
|
||
self.bus.add_slave("DMA", self.wishbone_slave_sys, SoCRegion(origin=self.mem_map.get("master", None), size=0x40000000, cached=False))
|
||
self.bus.add_master(name="NuBusBridgeToWishboneWrite", master=nubus_writemaster_sys)
|
||
|
||
self.submodules.stat = nubus_stat.NuBusStat(nubus=self.nubus, platform=platform)
|
||
self.bus.add_slave("Stat", self.stat.bus_slv, SoCRegion(origin=self.mem_map.get("stat", None), size=0x1000, cached=False))
|
||
|
||
if (goblin):
|
||
MacPeriphSoC.mac_add_goblin(self, use_goblin_alt = use_goblin_alt, hdmi = hdmi, goblin_res = goblin_res, goblin_irq = fb_irq, audio_irq = audio_irq)
|
||
|
||
if (sdcard): ### WIP WIP WIP WIP
|
||
self.add_sdcard()
|
||
# irq?
|
||
|
||
if (ethernet): ### WIP WIP WIP WIP
|
||
# we need the CRG to provide the cd_eth clock: "use refclk_cd as RMII reference clock (provided by user design) (no external clock).
|
||
self.ethphy = LiteEthPHYRMII(
|
||
clock_pads = self.platform.request("eth_clocks"),
|
||
#clock_pads = None,
|
||
pads = self.platform.request("eth"))
|
||
self.add_ethernet(phy=self.ethphy, data_width = 32)
|
||
print(f"%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% {self.ethmac.interface.sram.ev.irq}") # FIXME HANDLEME
|
||
from mdio import MDIOCtrl
|
||
self.submodules.mdio_ctrl = MDIOCtrl(platform=platform)
|
||
|
||
# for testing
|
||
if (False):
|
||
from nubus_master_tst import PingMaster
|
||
self.submodules.pingmaster = PingMaster(nubus=self.nubus, platform=self.platform)
|
||
self.bus.add_slave("pingmaster_slv", self.pingmaster.bus_slv, SoCRegion(origin=self.mem_map.get("pingmaster", None), size=0x010, cached=False))
|
||
self.bus.add_master(name="pingmaster_mst", master=self.pingmaster.bus_mst)
|
||
|
||
def main():
|
||
parser = argparse.ArgumentParser(description="NuBusFPGA")
|
||
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
||
parser.add_argument("--variant", default="ztex2.13a", help="ZTex board variant (default ztex2.13a)")
|
||
parser.add_argument("--version", default="V1.0", help="NuBusFPGA board version (default V1.0)")
|
||
parser.add_argument("--sys-clk-freq", default=100e6, help="NuBusFPGA system clock (default 100e6 = 100 MHz)")
|
||
parser.add_argument("--goblin", action="store_true", help="add a goblin framebuffer")
|
||
parser.add_argument("--hdmi", action="store_true", help="The framebuffer uses HDMI (default to VGA, required for V1.2)")
|
||
parser.add_argument("--goblin-res", default="1920x1080@60Hz", help="Specify the goblin resolution")
|
||
parser.add_argument("--goblin-alt", action="store_true", help="Use alternate HDMI Phy with Audio support (requires Full HD resolution)")
|
||
parser.add_argument("--sdcard", action="store_true", help="add a sdcard controller (V1.2 only)")
|
||
parser.add_argument("--flash", action="store_true", help="add a Flash device [V1.2+FLASHTEMP PMod] and configure the ROM to it")
|
||
parser.add_argument("--config-flash", action="store_true", help="Configure the ROM to the internal Flash used for FPGA config")
|
||
parser.add_argument("--ethernet", action="store_true", help="Add Ethernet (V1.2 w/ custom PMod only)")
|
||
builder_args(parser)
|
||
vivado_build_args(parser)
|
||
args = parser.parse_args()
|
||
|
||
if (args.sdcard and (args.version == "V1.0")):
|
||
print(" ***** ERROR ***** : Ethernet not supported on V1.0\n");
|
||
assert(False)
|
||
|
||
if (args.flash and (args.version == "V1.0")):
|
||
print(" ***** ERROR ***** : Flash not supported on V1.0\n");
|
||
assert(False)
|
||
|
||
if (args.ethernet and (args.version == "V1.0")):
|
||
print(" ***** ERROR ***** : Ethernet not supported on V1.0\n");
|
||
assert(False)
|
||
|
||
if (args.ethernet and args.flash):
|
||
print(" ***** ERROR ***** : Only one PMod usable on V1.2\n");
|
||
assert(False)
|
||
|
||
if ((not args.hdmi) and (args.version == "V1.2")):
|
||
print(" ***** ERROR ***** : VGA not supported on V1.2\n");
|
||
assert(False)
|
||
|
||
if ((not args.hdmi) and args.goblin_alt):
|
||
print(" ***** ERROR ***** : VGA and Goblin Alt PHY don't make sense\n");
|
||
assert(False)
|
||
|
||
if (args.config_flash and args.flash):
|
||
print(" ***** ERROR ***** : ROM-in-Flash can only use config OR PMod, not both\n");
|
||
assert(False)
|
||
|
||
if (args.goblin_alt and (args.goblin_res != "1920x1080@60Hz")):
|
||
print(" ***** ERROR ***** : Goblin Alt PHY currently only supports Full HD\n");
|
||
assert(False)
|
||
|
||
if (True):
|
||
f = open("decl_rom_config.mak","w+")
|
||
hres = int(args.goblin_res.split("@")[0].split("x")[0])
|
||
vres = int(args.goblin_res.split("@")[0].split("x")[1])
|
||
f.write("TARGET=NUBUSFPGA\n")
|
||
f.write("FEATURES+= -DNUBUSFPGA")
|
||
f.write(" -DENABLE_RAMDSK") # only NuBusFPGA for now
|
||
if (args.goblin_alt):
|
||
f.write(" -DENABLE_HDMIAUDIO") # no audio in litex-style not-hdmi phy
|
||
else:
|
||
f.write(" -DENABLE_HDMI_ALT_CHANGE");
|
||
if (args.version == "V1.0"):
|
||
f.write(" -DENABLE_HDMI_ALT_CHANGE_48MHZ");
|
||
elif (args.version == "V1.2"):
|
||
f.write(" -DENABLE_HDMI_ALT_CHANGE_54MHZ");
|
||
|
||
f.write("\n");
|
||
f.write(f"HRES={hres}\n");
|
||
f.write(f"VRES={vres}\n");
|
||
f.close()
|
||
|
||
soc = NuBusFPGA(**soc_core_argdict(args),
|
||
variant=args.variant,
|
||
version=args.version,
|
||
sys_clk_freq=int(float(args.sys_clk_freq)),
|
||
goblin=args.goblin,
|
||
hdmi=args.hdmi,
|
||
goblin_res=args.goblin_res,
|
||
use_goblin_alt=args.goblin_alt,
|
||
sdcard=args.sdcard,
|
||
flash=args.flash,
|
||
config_flash=args.config_flash,
|
||
ethernet=args.ethernet)
|
||
|
||
version_for_filename = args.version.replace(".", "_")
|
||
|
||
soc.platform.name += "_" + version_for_filename
|
||
|
||
builder = Builder(soc, **builder_argdict(args))
|
||
builder.build(**vivado_build_argdict(args), run=args.build)
|
||
|
||
# Generate modified CSR registers definitions/access functions to netbsd_csr.h.
|
||
# should be split per-device (and without base) to still work if we have identical devices in different configurations on multiple boards
|
||
# now it is split
|
||
|
||
csr_contents_dict = nubus_to_fpga_export.get_csr_header_split(
|
||
regions = soc.csr_regions,
|
||
constants = soc.constants,
|
||
csr_base = soc.mem_regions['csr'].origin)
|
||
for name in csr_contents_dict.keys():
|
||
write_to_file(os.path.join("nubusfpga_csr_{}.h".format(name)), csr_contents_dict[name])
|
||
|
||
|
||
if __name__ == "__main__":
|
||
main()
|