476 lines
15 KiB
Systemverilog
476 lines
15 KiB
Systemverilog
`timescale 1 ns / 1 ps
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module nubus_slave_tb ();
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`include "nubus_tb.svh"
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parameter TEST_CARD_ID = 'hc;
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parameter TEST_ADDR = 'hFc000000;
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parameter TEST_DATA = 'h87654321;
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parameter [1:0] MEMORY_WAIT_CLOCKS = 1;
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parameter DEBUG_NUBUS_START = 0;
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parameter ROM_ADDR = 'hFcFFF000;
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parameter PING_ADDR = 'hFcB00000;
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// Clock (rising is driving edge, faling is sampling)
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tri1 bd_clk48;
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// Slot Identification
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tri1 [3:0] nub_idn;
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// Clock (rising is driving edge, faling is sampling)
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tri1 nub_clkn;
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// Clock 90 (rising is driving edge, faling is sampling)
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tri1 nub_clk2xn;
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// Reset [Open Collector]
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tri1 nub_resetn;
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// Power Fail Warning [Control]
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//tri1 nub_pfwn;
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// Address/Data [Address/Data]
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tri1 [31:0] nub_adn;
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// Transfer Mode [Control]
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tri1 nub_tm0n;
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tri1 nub_tm1n;
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tri1 nub_tm2n;
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// Start [Control]
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tri1 nub_startn;
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// Request [Open Collector]
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tri1 nub_rqstn;
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// Acknowledge [Control]
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tri1 nub_ackn;
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// Arbitration [Open Collector]
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tri1 [3:0] nub_arbn;
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// Non-Master Request [Open Collector]
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tri1 nub_nmrqn;
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// System Parity [Address/Data]
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//tri1 nub_spn;
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// System Parity Valid [Address/Data]
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//tri1 nub_spvn;
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tri1 [1:0] leds;
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tri unused0, unused1, unused2;
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tri nubus_oe, nubus_ad_dir;
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tri reset_n_3v3, clk_n_3v3, tm0_n_3v3, tm1_n_3v3, start_n_3v3, ack_n_3v3, rqst_n_3v3;
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tri [3:0] id_n_3v3;
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tri [3:0] arb_n_3v3;
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tri [31:0] ad_n_3v3;
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tri [3:0] arb_o_n;
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tri tm0_o_n, tm1_o_n, tmx_oe_n;
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tri start_o_n, start_oe_n;
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tri ack_o_n, ack_oe_n;
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tri rqst_o_n;
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tri clk2x_n_3v3;
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tri tm2_n_3v3, tm2_o_n, tm2_oe_n;
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assign nub_idn = ~ TEST_CARD_ID;
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//assign nub_arbn = 'b1111;
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// actually 74lvt245, same digital function
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sn74fct245 shifters_b0(.data_5v(nub_adn[ 7: 0]),
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.data_3v3(ad_n_3v3[ 7: 0]),
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.nubus_oe(nubus_oe),
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.nubus_ad_dir(nubus_ad_dir));
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sn74fct245 shifters_b1(.data_5v(nub_adn[15: 8]),
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.data_3v3(ad_n_3v3[15: 8]),
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.nubus_oe(nubus_oe),
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.nubus_ad_dir(nubus_ad_dir));
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sn74fct245 shifters_b2(.data_5v(nub_adn[23:16]),
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.data_3v3(ad_n_3v3[23:16]),
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.nubus_oe(nubus_oe),
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.nubus_ad_dir(nubus_ad_dir));
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sn74fct245 shifters_b3(.data_5v(nub_adn[31:24]),
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.data_3v3(ad_n_3v3[31:24]),
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.nubus_oe(nubus_oe),
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.nubus_ad_dir(nubus_ad_dir));
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tri1 nmrq_n_3v3;
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sn74lvt145_quarter driver_u1a(.oe_n(nmrq_n_3v3),
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.in(0),
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.out(nub_nmrqn));
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sn74lvt145_quarter driver_u1b(.oe_n(rqst_o_n),
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.in(0),
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.out(nub_rqstn));
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sn74lvt145_quarter driver_u1c(.oe_n(start_oe_n),
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.in(start_o_n),
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.out(nub_startn));
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sn74lvt145_quarter driver_u1d(.oe_n(ack_oe_n),
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.in(ack_o_n),
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.out(nub_ackn));
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sn74lvt145_quarter driver_u3a(.oe_n(arb_o_n[0]),
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.in(0),
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.out(nub_arbn[0]));
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sn74lvt145_quarter driver_u3b(.oe_n(arb_o_n[1]),
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.in(0),
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.out(nub_arbn[1]));
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sn74lvt145_quarter driver_u3c(.oe_n(arb_o_n[3]),
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.in(0),
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.out(nub_arbn[3]));
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sn74lvt145_quarter driver_u3d(.oe_n(arb_o_n[2]),
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.in(0),
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.out(nub_arbn[2]));
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sn74lvt145_quarter driver_u2a(.oe_n(tmx_oe_n),
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.in(tm1_o_n),
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.out(nub_tm1n));
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sn74lvt145_quarter driver_u2b(.oe_n(tmx_oe_n),
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.in(tm0_o_n),
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.out(nub_tm0n));
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sn74lvt145_quarter driver_u2c(.oe_n(tm2_oe_n),
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.in(tm2_o_n),
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.out(nub_tm2n));
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tri1 [2:0] u13_throwaway;
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tri1 [2:0] u13_zero;
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sn74cb3t3245 shifters_u13(.oe_n('h0),
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.A({clk2x_n_3v3, clk_n_3v3, start_n_3v3, ack_n_3v3, rqst_n_3v3, u13_throwaway}),
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.B({nub_clk2xn, nub_clkn, nub_startn, nub_ackn, nub_rqstn, u13_zero}));
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sn74cb3t3245 shifters_u14(.oe_n('h0),
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.A({id_n_3v3, arb_n_3v3 }),
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.B({nub_idn, nub_arbn }));
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tri1 [3:0] u15_throwaway;
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tri1 [3:0] u15_zero;
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sn74cb3t3245 shifters_u15(.oe_n('h0),
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.A({ reset_n_3v3, tm2_n_3v3, tm0_n_3v3, tm1_n_3v3, u15_throwaway }),
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.B({ nub_resetn, nub_tm2n, nub_tm0n, nub_tm1n, u15_zero }));
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ztex213_nubus_V1_2 UNuBus (
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// NuBus lines only
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.clk48(bd_clk48),
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.clk_3v3_n(clk_n_3v3),
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.reset_3v3_n(reset_n_3v3),
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.user_led0(leds[0]),
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.user_led1(leds[1]),
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.id_3v3_n(id_n_3v3),
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.ad_3v3_n(ad_n_3v3),
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.tm0_3v3_n(tm0_n_3v3),
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.tm1_3v3_n(tm1_n_3v3),
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.tm0_o_n(tm0_o_n),
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.tm1_o_n(tm1_o_n),
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.tmx_oe_n(tmx_oe_n),
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.start_3v3_n(start_n_3v3),
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.start_o_n(start_o_n),
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.start_oe_n(start_oe_n),
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.rqst_3v3_n(rqst_n_3v3),
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.rqst_o_n(rqst_o_n),
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.nmrq_3v3_n(nmrq_n_3v3), // output only, direct to driver
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.ack_3v3_n(ack_n_3v3),
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.ack_o_n(ack_o_n),
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.ack_oe_n(ack_oe_n),
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.arb_3v3_n(arb_n_3v3),
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.arb_o_n(arb_o_n),
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.nubus_ad_dir(nubus_ad_dir),
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.nubus_oe(nubus_oe),
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.clk2x_3v3_n(clk2x_n_3v3),
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.tm2_3v3_n(tm2_n_3v3),
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.tm2_o_n(tm2_o_n),
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.tm2_oe_n(tm2_oe_n)
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);
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// State machine of test bench
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reg tst_clkn;
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reg tst_clk2xn;
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reg tst_clk48;
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reg tst_resetn;
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reg tst_startn;
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reg tst_ackn; // half clkn delayed ackn
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reg [1:0] tst_tmn;
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reg [1:0] tst_statusn;
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reg [31:0] tst_addrn;
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reg [31:0] tst_wdatan;
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reg [31:0] tst_rdatan;
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reg tst_rqstn;
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reg mastermode_start;
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reg mastermode_tmack;
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assign nub_clkn = tst_clkn;
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assign nub_clk2xn = tst_clk2xn;
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assign bd_clk48 = tst_clk48;
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assign nub_resetn = tst_resetn;
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assign nub_rqstn = tst_rqstn;
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// Drive NuBus signals
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assign nub_startn = mastermode_start ? 'bZ: tst_startn;
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assign nub_tm0n = (tst_startn & ~mastermode_tmack) ? 'bZ : tst_tmn[0];
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assign nub_tm1n = (tst_startn & ~mastermode_tmack) ? 'bZ : tst_tmn[1];
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assign nub_ackn = (tst_startn & ~mastermode_tmack) ? 'bZ : tst_ackn;
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// Drive NuBus address/data lines
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wire [31:0] tst_adn = tst_startn ? tst_wdatan : tst_addrn;
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wire tst_nuboen = (tst_startn & tst_tmn[1]) | mastermode_start;
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assign nub_adn = tst_nuboen ? 'bZ : tst_adn;
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// Inverted verions of registers
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wire [31:0] tst_rdata = ~tst_rdatan;
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wire [31:0] tst_addr = ~tst_addrn;
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initial begin
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$display ("Start virtual master (vm) writes and reads to/from NuBus slave memory module");
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$dumpfile("nubus_slave_tb.vcd");
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$dumpvars;
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#1;
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mastermode_start <= 0;
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mastermode_tmack <= 0;
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tst_clkn <= 1;
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tst_resetn <= 0;
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tst_rqstn <= 'bz;
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tst_addrn <= 'hFFFFFFFF;
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tst_wdatan <= 'hFFFFFFFF;
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tst_rdatan <= 'hFFFFFFFF;
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tst_startn <= 1;
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tst_statusn<= TMN_TRY_AGAIN_LATER;
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tst_tmn <= TMN_NOP;
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@ (posedge nub_clkn);
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@ (posedge nub_clkn);
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tst_resetn <= 1;
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#2000;
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@ (posedge nub_clkn);
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$display ("%g: %b", $time, nub_startn);
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$display ("WORD ---------------------------");
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write_word(TMADN_WR_WORD, TEST_ADDR+0, TEST_DATA);
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read_word (TMADN_RD_WORD, TEST_ADDR+0);
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check_word(TMADN_RD_WORD, TEST_DATA);
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$display ("HALF 0 -------------------------");
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write_word(TMADN_WR_HALF_0, TEST_ADDR+4, TEST_DATA);
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read_word (TMADN_RD_HALF_0, TEST_ADDR+4);
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check_word(TMADN_RD_HALF_0, TEST_DATA);
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$display ("HALF 1 -------------------------");
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write_word(TMADN_WR_HALF_1, TEST_ADDR+8, TEST_DATA);
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read_word (TMADN_RD_HALF_1, TEST_ADDR+8);
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check_word(TMADN_RD_HALF_1, TEST_DATA);
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$display ("BYTE 0 -------------------------");
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write_word(TMADN_WR_BYTE_0, TEST_ADDR+12, TEST_DATA);
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read_word (TMADN_RD_BYTE_0, TEST_ADDR+12);
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check_word(TMADN_RD_BYTE_0, TEST_DATA);
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$display ("BYTE 1 -------------------------");
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write_word(TMADN_WR_BYTE_1, TEST_ADDR+16, TEST_DATA);
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read_word (TMADN_RD_BYTE_1, TEST_ADDR+16);
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check_word(TMADN_RD_BYTE_1, TEST_DATA);
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$display ("BYTE 2 -------------------------");
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write_word(TMADN_WR_BYTE_2, TEST_ADDR+20, TEST_DATA);
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read_word (TMADN_RD_BYTE_2, TEST_ADDR+20);
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check_word(TMADN_RD_BYTE_2, TEST_DATA);
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$display ("BYTE 3 -------------------------");
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write_word(TMADN_WR_BYTE_3, TEST_ADDR+24, TEST_DATA);
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read_word (TMADN_RD_BYTE_3, TEST_ADDR+24);
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check_word(TMADN_RD_BYTE_3, TEST_DATA);
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// $display ("BLOCK2 -------------------------");
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// read_block2 (TMADN_RD_BLOCK, TEST_ADDR);
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#500
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// Check Rom
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$display ("ROM ---------------------------");
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read_word (TMADN_RD_WORD, ROM_ADDR+4092);
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read_word (TMADN_RD_WORD, ROM_ADDR+4088);
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read_word (TMADN_RD_WORD, ROM_ADDR+4084);
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read_word (TMADN_RD_WORD, ROM_ADDR+4080);
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read_word (TMADN_RD_WORD, ROM_ADDR+0);
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read_word (TMADN_RD_WORD, ROM_ADDR+4);
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read_word (TMADN_RD_WORD, ROM_ADDR+8);
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read_word (TMADN_RD_WORD, ROM_ADDR+12);
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#1000;
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// check PingMaster
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$display ("PING ---------------------------");
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write_word(TMADN_WR_WORD, PING_ADDR+0, 'h00C0FFEE);
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read_word (TMADN_RD_WORD, PING_ADDR+0);
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write_word(TMADN_WR_WORD, PING_ADDR+4, 'h00096240);
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//read_word (TMADN_RD_WORD, ROM_ADDR+0);
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mastermode_start <= 1;
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mastermode_tmack <= 0;
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tst_ackn <= 1;
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@ (negedge nub_startn);
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#1
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$display ("GOT START ---------------------------");
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$display ("%g (received ) address: $%h", $time, ~nub_adn);
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@ (negedge nub_clkn);
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#1
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@ (negedge nub_clkn);
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#1
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@ (negedge nub_clkn);
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#1
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$display ("%g (received ) data: $%h", $time, ~nub_adn);
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@ (posedge nub_clkn);
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mastermode_tmack <= 1;
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tst_ackn <= 0;
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tst_tmn <= TMN_COMPLETE;
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@ (posedge nub_clkn);
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mastermode_start <= 0;
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mastermode_tmack <= 0;
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#2000;
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$finish;
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end
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// ======================================================
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// Write task
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// ======================================================
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task write_word;
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input [3:0] tmadn;
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input [31:0] addr;
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input [31:0] data;
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begin
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@ (posedge nub_clkn);
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tst_wdatan <= ~data;
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tst_addrn[31:2] <= ~addr[31:2];
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tst_addrn[ 1:0] <= tmadn[1:0];
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tst_tmn <= tmadn[3:2];
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tst_startn <= 0;
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tst_ackn <= 1;
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//tst_statusn <= TMN_TRY_AGAIN_LATER;
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@ (posedge nub_clkn);
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tst_startn <= 1;
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tst_ackn <= nub_ackn;
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do begin
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@ (negedge nub_clkn);
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tst_ackn <= nub_ackn;
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tst_statusn <= { nub_tm1n, nub_tm0n };
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//@ (posedge nub_clkn);
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end while (tst_ackn) ;
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$display ("%g (write) address: $%h tm: $%h data: $%h stat: %s", $time, addr, tmadn, data, get_status_str(tst_statusn));
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end
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endtask
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// ======================================================
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// Read task
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// ======================================================
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task read_word;
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input [3:0] tmadn;
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input [31:0] addr;
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begin
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@ (posedge nub_clkn);
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tst_tmn <= tmadn[3:2];
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tst_addrn[ 1:0] <= tmadn[1:0];
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tst_addrn[31:2] <= ~addr[31:2];
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tst_startn <= 0;
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tst_ackn <= 1;
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//tst_statusn <= TMN_TRY_AGAIN_LATER;
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@ (posedge nub_clkn);
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tst_startn <= 1;
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tst_ackn <= nub_ackn;
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do begin
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@ (negedge nub_clkn);
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tst_rdatan <= nub_adn;
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tst_ackn <= nub_ackn;
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tst_statusn <= { nub_tm1n, nub_tm0n };
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//@ (posedge nub_clkn);
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end while (tst_ackn) ;
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$display ("%g (read ) address: $%h tm: $%h data: $%h stat: %s", $time, addr, tmadn, tst_rdata, get_status_str(tst_statusn));
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end
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endtask
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// ======================================================
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// Verify data writen to memory with read from
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// asume memory befor write was $00000000
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// ======================================================
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task check_word
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(
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input [3:0] tm,
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input [31:0] data_wr
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);
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reg [31:0] expected;
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begin
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expected = (data_wr & get_mask(tm));
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if (tst_rdata == expected)
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$display (":) PASSED");
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else
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$display (":( FAILED expected: $%h found: $%h", expected, tst_rdata);
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$display(" ");
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end
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endtask // verify
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// ======================================================
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// Read block2 task
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// Currently unsupported (introduced with Q700/Q900, not in the NTC)
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// ======================================================
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task read_block2;
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input [3:0] tmadn;
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input [31:0] addr;
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begin
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@ (posedge nub_clkn);
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tst_tmn <= tmadn[3:2];
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tst_addrn[ 1:0] <= tmadn[1:0];
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tst_addrn[ 2:2] <= 1; // this indicates size 2
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tst_addrn[31:3] <= ~addr[31:3];
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tst_startn <= 0;
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//tst_statusn <= TMN_TRY_AGAIN_LATER;
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@ (posedge nub_clkn);
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tst_startn <= 1;
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tst_ackn <= nub_ackn;
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do begin
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|
@ (negedge nub_clkn);
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tst_rdatan <= nub_adn;
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tst_ackn <= nub_ackn;
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tst_statusn <= { nub_tm1n, nub_tm0n };
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//@ (posedge nub_clkn);
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end while (tst_statusn[0]) ;
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$display ("%g (block0/2) address: $%h tm: $%h data: $%h stat: %s", $time, addr, tmadn, tst_rdata, get_status_str(tst_statusn));
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|
do begin
|
|
@ (negedge nub_clkn);
|
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tst_rdatan <= nub_adn;
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|
tst_ackn <= nub_ackn;
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tst_statusn <= { nub_tm1n, nub_tm0n };
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//@ (posedge nub_clkn);
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end while (tst_ackn) ;
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|
$display ("%g (block1/2) address: $%h tm: $%h data: $%h stat: %s", $time, addr, tmadn, tst_rdata, get_status_str(tst_statusn));
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|
end
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|
endtask // read block2
|
|
|
|
// ======================================================
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|
// Clock generators
|
|
// ======================================================
|
|
|
|
always begin
|
|
tst_clkn <= 1;
|
|
#75.075;
|
|
tst_clkn <= 0;
|
|
if (DEBUG_NUBUS_START) begin
|
|
if (~nub_startn)
|
|
$display ("%g (NuBus Start) /ad: $%h {/tmadn}: %b%b%b%b", $time, nub_adn, nub_tm1n, nub_tm0n, nub_adn[1], nub_adn[0]);
|
|
end
|
|
#25.025;
|
|
end
|
|
always begin
|
|
tst_clk2xn <= 0;
|
|
#25.025;
|
|
tst_clk2xn <= 1;
|
|
#25.025;
|
|
end
|
|
|
|
always begin
|
|
tst_clk48 <= 0;
|
|
#10.41666666;
|
|
tst_clk48 <= 1;
|
|
#10.41666666;
|
|
end
|
|
|
|
endmodule
|