38 lines
1.0 KiB
Verilog
38 lines
1.0 KiB
Verilog
module sn74cb3t3125
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(
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input [3:0] oe_n,
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output [3:0] A,
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input [3:0] B
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);
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/*
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wire [3:0] tA;
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wire [3:0] tB;
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assign A[0] = oe_n[0] ? 'bZ : tA[0];
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assign A[1] = oe_n[1] ? 'bZ : tA[1];
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assign A[2] = oe_n[2] ? 'bZ : tA[2];
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assign A[3] = oe_n[3] ? 'bZ : tA[3];
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assign B[0] = oe_n[0] ? 'bZ : tB[0];
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assign B[1] = oe_n[1] ? 'bZ : tB[1];
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assign B[2] = oe_n[2] ? 'bZ : tB[2];
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assign B[3] = oe_n[3] ? 'bZ : tB[3];
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assign tA[0] = A[0] === 'bZ ? B[0] : 'bZ;
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assign tA[1] = A[1] === 'bZ ? B[1] : 'bZ;
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assign tA[2] = A[2] === 'bZ ? B[2] : 'bZ;
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assign tA[3] = A[3] === 'bZ ? B[3] : 'bZ;
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assign tB[0] = B[0] === 'bZ ? A[0] : 'bZ;
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assign tB[1] = B[1] === 'bZ ? A[1] : 'bZ;
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assign tB[2] = B[2] === 'bZ ? A[2] : 'bZ;
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assign tB[3] = B[3] === 'bZ ? A[3] : 'bZ;
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*/
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assign A[0] = oe_n[0] ? 'bZ : B[0];
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assign A[1] = oe_n[1] ? 'bZ : B[1];
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assign A[2] = oe_n[2] ? 'bZ : B[2];
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assign A[3] = oe_n[3] ? 'bZ : B[3];
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endmodule // sn74cb3t3125
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