158 lines
7.2 KiB
Python
158 lines
7.2 KiB
Python
from migen import *
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from migen.genlib.fifo import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import wishbone
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class GoblinAccel(Module): # AutoCSR ?
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def __init__(self, soc):
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platform = soc.platform
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# reg access
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self.bus = bus = wishbone.Interface()
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self.COORD_BITS = COORD_BITS = 12 #
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reg_status = Signal(32) # 0
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reg_cmd = Signal(32) # 1
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reg_r5_cmd = Signal(32) # 2, to communicate with Vex
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# 3 resv0
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reg_width = Signal(COORD_BITS) # 4
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reg_height = Signal(COORD_BITS) # 5
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reg_fgcolor = Signal(32) # 6
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# 7 resv2
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reg_bitblt_src_x = Signal(COORD_BITS) # 8
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reg_bitblt_src_y = Signal(COORD_BITS) # 9
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reg_bitblt_dst_x = Signal(COORD_BITS) # 10
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reg_bitblt_dst_y = Signal(COORD_BITS) # 11
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# do-some-work flags
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do_blit = Signal()
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do_fill = Signal()
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# cmd register reg_cmd
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DO_BLIT_BIT = 0
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DO_FILL_BIT = 1
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# global status register reg_status
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WORK_IN_PROGRESS_BIT = 0
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self.submodules.wishbone_fsm = wishbone_fsm = FSM(reset_state = "Reset")
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wishbone_fsm.act("Reset",
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NextValue(bus.ack, 0),
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NextState("Idle"))
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wishbone_fsm.act("Idle",
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If(bus.cyc & bus.stb & bus.we & ~bus.ack, #write
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Case(bus.adr[0:10], { #
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"default": [ ],
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# 0: reg_status R/O
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0: [ NextValue(reg_status, bus.dat_w) ], # debug, remove me
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1: [ NextValue(reg_cmd, bus.dat_w),
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NextValue(do_blit, bus.dat_w[DO_BLIT_BIT] & ~reg_status[WORK_IN_PROGRESS_BIT]),
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NextValue(do_fill, bus.dat_w[DO_FILL_BIT] & ~reg_status[WORK_IN_PROGRESS_BIT]),
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],
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2: [ NextValue(reg_r5_cmd, bus.dat_w) ],
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# 3
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4: [ NextValue(reg_width, bus.dat_w) ],
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5: [ NextValue(reg_height, bus.dat_w) ],
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6: [ NextValue(reg_fgcolor, bus.dat_w) ],
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# 7
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8: [ NextValue(reg_bitblt_src_x, bus.dat_w) ],
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9: [ NextValue(reg_bitblt_src_y, bus.dat_w) ],
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10: [ NextValue(reg_bitblt_dst_x, bus.dat_w) ],
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11: [ NextValue(reg_bitblt_dst_y, bus.dat_w) ],
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}),
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NextValue(bus.ack, 1),
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).Elif(bus.cyc & bus.stb & ~bus.we & ~bus.ack, #read
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Case(bus.adr[0:10], {
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"default": [ NextValue(bus.dat_r, 0xDEADBEEF) ],
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0: [ NextValue(bus.dat_r, reg_status) ],
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1: [ NextValue(bus.dat_r, reg_cmd) ],
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2: [ NextValue(bus.dat_r, reg_r5_cmd) ],
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# 3
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4: [ NextValue(bus.dat_r, reg_width) ],
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5: [ NextValue(bus.dat_r, reg_height) ],
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6: [ NextValue(bus.dat_r, reg_fgcolor) ],
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# 7
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8: [ NextValue(bus.dat_r, reg_bitblt_src_x) ],
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9: [ NextValue(bus.dat_r, reg_bitblt_src_y) ],
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10: [ NextValue(bus.dat_r, reg_bitblt_dst_x) ],
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11: [ NextValue(bus.dat_r, reg_bitblt_dst_y) ],
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}),
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NextValue(bus.ack, 1),
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).Else(
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NextValue(bus.ack, 0),
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)
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)
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# also in blit.c, for r5-cmd
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FUN_DONE_BIT = 31
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FUN_BLIT_BIT = 0
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FUN_FILL_BIT = 1
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# to hold the Vex in reset
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local_reset = Signal(reset = 1)
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self.sync += [
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If(reg_r5_cmd[FUN_DONE_BIT],
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reg_r5_cmd.eq(0),
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reg_status[WORK_IN_PROGRESS_BIT].eq(0),
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local_reset.eq(1),
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#timeout.eq(timeout_rst),
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).Elif(do_blit & ~reg_status[WORK_IN_PROGRESS_BIT],
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do_blit.eq(0),
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reg_r5_cmd[FUN_BLIT_BIT].eq(1),
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reg_status[WORK_IN_PROGRESS_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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).Elif(do_fill & ~reg_status[WORK_IN_PROGRESS_BIT],
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do_fill.eq(0),
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reg_r5_cmd[FUN_FILL_BIT].eq(1),
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reg_status[WORK_IN_PROGRESS_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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)
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]
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#led0 = platform.request("user_led", 0)
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#self.comb += led0.eq(~local_reset)
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self.ibus = ibus = wishbone.Interface()
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self.dbus = dbus = wishbone.Interface()
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vex_reset = Signal()
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self.comb += vex_reset.eq(ResetSignal("sys") | local_reset)
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self.specials += Instance(self.get_netlist_name(),
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i_clk = ClockSignal("sys"),
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i_reset = vex_reset,
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o_iBusWishbone_CYC = ibus.cyc,
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o_iBusWishbone_STB = ibus.stb,
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i_iBusWishbone_ACK = ibus.ack,
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o_iBusWishbone_WE = ibus.we,
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o_iBusWishbone_ADR = ibus.adr,
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i_iBusWishbone_DAT_MISO = ibus.dat_r,
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o_iBusWishbone_DAT_MOSI = ibus.dat_w,
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o_iBusWishbone_SEL = ibus.sel,
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i_iBusWishbone_ERR = ibus.err,
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o_iBusWishbone_CTI = ibus.cti,
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o_iBusWishbone_BTE = ibus.bte,
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o_dBusWishbone_CYC = dbus.cyc,
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o_dBusWishbone_STB = dbus.stb,
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i_dBusWishbone_ACK = dbus.ack,
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o_dBusWishbone_WE = dbus.we,
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o_dBusWishbone_ADR = dbus.adr,
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i_dBusWishbone_DAT_MISO = dbus.dat_r,
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o_dBusWishbone_DAT_MOSI = dbus.dat_w,
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o_dBusWishbone_SEL = dbus.sel,
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i_dBusWishbone_ERR = dbus.err,
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o_dBusWishbone_CTI = dbus.cti,
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o_dBusWishbone_BTE = dbus.bte,)
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self.add_sources(platform)
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def get_netlist_name(self):
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return "VexRiscv"
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def add_sources(self, platform):
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platform.add_source("/home/dolbeau/NuBusFPGA/nubus-to-ztex-gateware/VexRiscv_FbAccel.v", "verilog")
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