mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-06-02 03:41:29 +00:00
206 lines
7.6 KiB
C
206 lines
7.6 KiB
C
#include "NuBusFPGARAMDskDrvr.h"
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/* #include <DriverServices.h> */
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__attribute__ ((section (".text.dskdriver"))) static inline void waitSome(unsigned long bound) {
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unsigned long i;
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for (i = 0 ; i < bound ; i++) {
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asm volatile("nop");
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}
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}
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/* Devices 1-34 (p54) */
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#pragma parameter __D0 cNuBusFPGARAMDskPrime(__A0, __A1)
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OSErr cNuBusFPGARAMDskPrime(IOParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
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{
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OSErr ret = noErr;
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struct RAMDrvContext *ctx;
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/* write_reg(dce, GOBOFB_DEBUG, 0xDEAD0003); */
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/* write_reg(dce, GOBOFB_DEBUG, pb->ioTrap); */
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/* write_reg(dce, GOBOFB_DEBUG, pb->ioPosMode); */
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/* write_reg(dce, GOBOFB_DEBUG, pb->ioReqCount); */
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/* write_reg(dce, GOBOFB_DEBUG, pb->ioPosOffset); */
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ctx = *(struct RAMDrvContext**)dce->dCtlStorage;
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if (ctx) {
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unsigned char* superslot = (unsigned char*)(((unsigned long)ctx->slot) << 28ul);
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unsigned long abs_offset = 0;
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/* IOParamPtr: Devices 1-53 (p73) */
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/* **** WHERE **** */
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switch(pb->ioPosMode & 0x000F) { // ignore rdVerify
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case fsAtMark:
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abs_offset = dce->dCtlPosition;
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break;
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case fsFromStart:
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abs_offset = pb->ioPosOffset;
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break;
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case fsFromMark:
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abs_offset = dce->dCtlPosition + pb->ioPosOffset;
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break;
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default:
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break;
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}
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/* **** WHAT **** */
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/* Devices 1-33 (p53) */
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if ((pb->ioTrap & 0x00FF) == aRdCmd) {
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if(!(pb->ioPosMode & 0x40)) { // rdVerify, let's ignore it for now
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#ifdef ENABLE_DMA
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/* write_reg(dce, GOBOFB_DEBUG, 0xD1580000); */
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/* write_reg(dce, GOBOFB_DEBUG, (unsigned long)pb->ioBuffer); */
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/* write_reg(dce, GOBOFB_DEBUG, pb->ioReqCount); */
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if ((((unsigned long)pb->ioBuffer & ctx->dma_blk_size_mask) == 0) &&
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(((unsigned long)pb->ioReqCount & ctx->dma_blk_size_mask) == 0) &&
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(((unsigned long)abs_offset & ctx->dma_blk_size_mask) == 0)) {
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unsigned long blk_todo = (pb->ioReqCount >> ctx->dma_blk_size_shift), blk_doing, blk_done;
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unsigned long count, max_count, delay;
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unsigned long blk_cnt, status;
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blk_cnt = revb(read_reg(dce, DMA_BLK_CNT)) & 0xFFFF;
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status = revb(read_reg(dce, DMA_STATUS)) & DMA_STATUS_CHECK_BITS;
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blk_done = 0;
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while (blk_todo > 0) {
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blk_doing = blk_todo;
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if (blk_doing > 65535) { // fixme: read HW max
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blk_doing = 32768; // nice Po2
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}
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max_count = 32 * blk_doing;
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delay = (blk_doing >> 4);
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if (delay > 65536)
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delay = 65536;
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if ((blk_cnt == 0) && (status == 0)) {
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write_reg(dce, DMA_BLK_ADDR, revb(ctx->dma_blk_base + (abs_offset >> ctx->dma_blk_size_shift) + blk_done));
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write_reg(dce, DMA_DMA_ADDR, revb(pb->ioBuffer + (blk_done << ctx->dma_blk_size_shift)));
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write_reg(dce, DMA_BLK_CNT, revb(0x00000000ul | blk_doing));
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waitSome(delay);
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count = 0;
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blk_cnt = revb(read_reg(dce, DMA_BLK_CNT)) & 0xFFFF;
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status = revb(read_reg(dce, DMA_STATUS)) & DMA_STATUS_CHECK_BITS;
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while (((blk_cnt != 0) ||
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(status != 0)) &&
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(count < max_count)) {
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count ++;
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waitSome(delay);
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if (blk_cnt) blk_cnt = revb(read_reg(dce, DMA_BLK_CNT)) & 0xFFFF;
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if (status) status = revb(read_reg(dce, DMA_STATUS)) & DMA_STATUS_CHECK_BITS;
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}
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}
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blk_done += blk_doing;
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blk_todo -= blk_doing;
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}
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if (blk_cnt || status) {
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return readErr;
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BlockMoveData((superslot + abs_offset), pb->ioBuffer, pb->ioReqCount);
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}
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#ifdef DMA_DEBUG
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else {
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unsigned int k = 0;
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while ((((unsigned long*)(superslot))[5] == 0x12345678) && (((unsigned long*)(superslot))[9] == 0x87654321) && (k < 7)) {
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k++;
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superslot += 64;
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}
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if ((((unsigned long*)(superslot))[5] != 0x12345678) || (((unsigned long*)(superslot))[9] != 0x87654321)) {
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unsigned int i;
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for (i = 0 ; i < pb->ioReqCount ; i+=4 ) {
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if ((*(unsigned long*)(superslot + abs_offset + i)) != (*(unsigned long*)((char*)pb->ioBuffer + i))) {
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((unsigned long*)(superslot))[0] = ctx->dma_blk_size;
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((unsigned long*)(superslot))[1] = ctx->dma_blk_size_mask;
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((unsigned long*)(superslot))[2] = ctx->dma_blk_size_shift;
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((unsigned long*)(superslot))[3] = ctx->dma_blk_base;
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((unsigned long*)(superslot))[4] = ctx->dma_mem_size;
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((unsigned long*)(superslot))[5] = 0x12345678;
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((unsigned long*)(superslot))[6] = pb->ioBuffer;
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((unsigned long*)(superslot))[7] = pb->ioReqCount;
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((unsigned long*)(superslot))[8] = abs_offset;
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((unsigned long*)(superslot))[9] = 0x87654321;
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((unsigned long*)(superslot))[10] = i;
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((unsigned long*)(superslot))[11] = (*(unsigned long*)(superslot + abs_offset + i));
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((unsigned long*)(superslot))[12] = (*(unsigned long*)((char*)pb->ioBuffer + i));
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((unsigned long*)(superslot))[13] = (*(unsigned long*)(superslot + abs_offset + i + 4));
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((unsigned long*)(superslot))[14] = (*(unsigned long*)((char*)pb->ioBuffer + i + 4));
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i += 4;
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}
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}
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}
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}
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#endif
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} else
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#endif
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{
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BlockMoveData((superslot + abs_offset), pb->ioBuffer, pb->ioReqCount);
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}
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}
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pb->ioActCount = pb->ioReqCount;
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dce->dCtlPosition = abs_offset + pb->ioReqCount;
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pb->ioPosOffset = dce->dCtlPosition;
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} else if ((pb->ioTrap & 0x00FF) == aWrCmd) {
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#ifdef ENABLE_DMA
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/* write_reg(dce, GOBOFB_DEBUG, 0xD1580001); */
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/* write_reg(dce, GOBOFB_DEBUG, (unsigned long)pb->ioBuffer); */
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/* write_reg(dce, GOBOFB_DEBUG, pb->ioReqCount); */
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if ((((unsigned long)pb->ioBuffer & ctx->dma_blk_size_mask) == 0) &&
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(((unsigned long)pb->ioReqCount & ctx->dma_blk_size_mask) == 0) &&
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(((unsigned long)abs_offset & ctx->dma_blk_size_mask) == 0)) {
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unsigned long blk_todo = (pb->ioReqCount >> ctx->dma_blk_size_shift), blk_doing, blk_done;
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unsigned long count, max_count, delay;
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unsigned long blk_cnt, status;
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blk_cnt = revb(read_reg(dce, DMA_BLK_CNT)) & 0xFFFF;
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status = revb(read_reg(dce, DMA_STATUS)) & DMA_STATUS_CHECK_BITS;
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blk_done = 0;
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while (blk_todo > 0) {
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blk_doing = blk_todo;
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if (blk_doing > 65535) { // fixme: read HW max
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blk_doing = 32768; // nice Po2
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}
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max_count = 32 * blk_doing;
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delay = (blk_doing >> 4);
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if (delay > 65536)
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delay = 65536;
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if ((blk_cnt == 0) && (status == 0)) {
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write_reg(dce, DMA_BLK_ADDR, revb(ctx->dma_blk_base + (abs_offset >> ctx->dma_blk_size_shift) + blk_done));
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write_reg(dce, DMA_DMA_ADDR, revb(pb->ioBuffer + (blk_done << ctx->dma_blk_size_shift)));
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write_reg(dce, DMA_BLK_CNT, revb(0x80000000ul | blk_doing));
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waitSome(delay);
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count = 0;
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blk_cnt = revb(read_reg(dce, DMA_BLK_CNT)) & 0xFFFF;
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status = revb(read_reg(dce, DMA_STATUS)) & DMA_STATUS_CHECK_BITS;
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while (((blk_cnt != 0) ||
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(status != 0)) &&
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(count < max_count)) {
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count ++;
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waitSome(delay);
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if (blk_cnt) blk_cnt = revb(read_reg(dce, DMA_BLK_CNT)) & 0xFFFF;
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if (status) status = revb(read_reg(dce, DMA_STATUS)) & DMA_STATUS_CHECK_BITS;
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}
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}
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blk_done += blk_doing;
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blk_todo -= blk_doing;
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}
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if (blk_cnt || status) {
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return writErr;
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BlockMoveData(pb->ioBuffer, (superslot + abs_offset), pb->ioReqCount);
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}
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} else
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#endif
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{
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BlockMoveData(pb->ioBuffer, (superslot + abs_offset), pb->ioReqCount);
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}
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pb->ioActCount = pb->ioReqCount;
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dce->dCtlPosition = abs_offset + pb->ioReqCount;
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pb->ioPosOffset = dce->dCtlPosition;
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} else {
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ret = paramErr;
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goto done;
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}
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} else {
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ret = offLinErr; /* r/w requested for an off-line drive */
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goto done;
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}
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done:
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if (!(pb->ioTrap & (1<<noQueueBit)))
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IODone((DCtlPtr)dce, ret);
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return ret;
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}
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