142 lines
4.9 KiB
Scala
142 lines
4.9 KiB
Scala
package vexriscv.demo
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// CG6Plugin is:
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// ./gen_plugin -n CG6 -i data_bitmanip.txt -i data_bitmanip_ZbbOnly.txt -I SH2ADD -I MINU -I MAXU -I REV8 -I CMOV -I CMIX -I FSR -I ZEXTdotH -I SEXTdotB >| CG6.scala
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// Goblin Plugins are:
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// ./gen_plugin -n Goblin -i data_Zpn.txt -I UKADD8 -I UKSUB8 >| Goblin.scala
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// ./gen_plugin -n Goblin -i data_Zxrender_2cycles.txt -I UFMA8VxV >| Goblin2c.scala
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import vexriscv.plugin._
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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import spinal.core._
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import vexriscv.ip.InstructionCacheConfig
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import spinal.lib._
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import spinal.lib.sim.Phase
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import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
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import vexriscv.plugin._
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object GenGoblinAccel { // extends App {
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def main(args: Array[String]) {
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val report = SpinalVerilog{
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val config = VexRiscvConfig(
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plugins = List(
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new IBusCachedPlugin(
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resetVector = 0xF0910000l, // beginning of ROM (NuBus)
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//resetVector = 0x00410000l, // beginning of ROM (SBus)
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relaxedPcCalculation = false,
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prediction = STATIC,
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config = InstructionCacheConfig(
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cacheSize = 256,
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bytePerLine = 16,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = false,
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catchAccessFault = false,
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asyncTagMemory = false,
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twoCycleRam = false,
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twoCycleCache = true
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)
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),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = false,
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// catchAccessFault = false
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// ),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 256,
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bytePerLine = 16,
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wayCount = 2,
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addressWidth = 32,
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cpuDataWidth = 128,
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memDataWidth = 128,
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catchAccessError = false,
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catchIllegal = false,
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catchUnaligned = false,
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pendingMax = 8, // 64 ; irrelevant? only for SMP?
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withWriteAggregation = true // required if memDataWidth > 32
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),
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dBusCmdMasterPipe = false, // prohibited if memDataWidth > 32
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dBusCmdSlavePipe = true,
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dBusRspSlavePipe = true
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),
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new StaticMemoryTranslatorPlugin(
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// only cache the sdram memory
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// NuBus
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ioRange = addr => ((addr(31 downto 28) =/= 0x8) & // SDRAM
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(addr(31 downto 12) =/= 0xF0902) & // SRAM
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(addr(31 downto 16) =/= 0xF091) // ROM
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)
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// SBus
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//ioRange = addr => ((addr(31 downto 28) =/= 0x8) & // SDRAM
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// (addr(31 downto 16) =/= 0x0042) & // SRAM
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// (addr(31 downto 16) =/= 0x0041) // ROM
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// )
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFileOddEvenPlugin(
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regFileReadyKind = plugin.ASYNC, // FIXME why is even-odd failing with SYNC??? (and what's the difference...)
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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//new LightShifterPlugin,
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new MulPlugin,
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new FullBarrelShifterPlugin,
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new CG6Plugin(earlyInjection = false), // full-custom list
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new GoblinPlugin(earlyInjection = false), // full-custom list
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new Goblin2cPlugin(earlyInjection = false), // full-custom list
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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val cpu = new VexRiscv(config)
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cpu.rework {
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for (plugin <- config.plugins) plugin match {
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case plugin: IBusSimplePlugin => {
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plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
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master(plugin.iBus.toWishbone()).setName("iBusWishbone")
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}
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case plugin: IBusCachedPlugin => {
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plugin.iBus.setAsDirectionLess()
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master(plugin.iBus.toWishbone()).setName("iBusWishbone")
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}
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case plugin: DBusSimplePlugin => {
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plugin.dBus.setAsDirectionLess()
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master(plugin.dBus.toWishbone()).setName("dBusWishbone")
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}
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case plugin: DBusCachedPlugin => {
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plugin.dBus.setAsDirectionLess()
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master(plugin.dBus.toWishbone()).setName("dBusWishbone")
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}
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case _ =>
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}
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}
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cpu
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}
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//report.printPruned()
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}
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}
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