33 lines
1.0 KiB
Python
33 lines
1.0 KiB
Python
from migen import *
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from migen.genlib.fifo import *
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import litex
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from litex.soc.interconnect import wishbone
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from migen.genlib.cdc import BusSynchronizer
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class Wishbone2NuBus(Module):
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def __init__(self, nubus, wb):
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# cpu
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# input cpu_valid,
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# input [31:0] cpu_addr,
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# input [31:0] cpu_wdata,
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# input [ 3:0] cpu_write,
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# output cpu_ready,
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# output [31:0] cpu_rdata,
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#input cpu_lock,
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#input cpu_eclr,
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#output [3:0] cpu_errors,
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self.comb += nubus.cpu_valid.eq(wb.cyc & wb.stb)
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self.comb += nubus.cpu_addr.eq(Cat(Signal(2, reset = 0), wb.adr))
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self.comb += nubus.cpu_wdata.eq(wb.dat_w)
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self.comb += If(wb.we == 1,
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nubus.cpu_write.eq(wb.sel)).Else(
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nubus.cpu_write.eq(0))
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self.comb += wb.ack.eq(nubus.cpu_ready)
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self.comb += wb.dat_r.eq(nubus.cpu_rdata)
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self.comb += nubus.cpu_lock.eq(0) # FIXME: TODO: ???
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self.comb += nubus.cpu_eclr.eq(0) # FIXME: TODO: ???
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