mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-06-02 03:41:29 +00:00
334 lines
16 KiB
Python
334 lines
16 KiB
Python
from migen import *
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from migen.genlib.fifo import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import wishbone
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from litedram.common import LiteDRAMNativePort
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from litedram.frontend.wishbone import LiteDRAMWishbone2Native
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class GoblinAccel(Module): # AutoCSR ?
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def __init__(self, soc):
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platform = soc.platform
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# reg access
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self.bus = bus = wishbone.Interface()
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self.COORD_BITS = COORD_BITS = 14 # need enough bytes for 32-bits depth and widest resolution ; should be <= 15 otherwise the INIT code will need to strip the upper bit from some parameters
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reg_status = Signal(32) # 0
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reg_cmd = Signal(32) # 1
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reg_r5_cmd = Signal(32) # 2, to communicate with Vex
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reg_op = Signal(8) # 3, X11 op or (0x80 | Render op)
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reg_width = Signal(COORD_BITS) # 4
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reg_height = Signal(COORD_BITS) # 5
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reg_fgcolor = Signal(32) # 6
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reg_depth = Signal(8) # 7, depth (0 is native)
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reg_bitblt_src_x = Signal(COORD_BITS) # 8
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reg_bitblt_src_y = Signal(COORD_BITS) # 9
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reg_bitblt_dst_x = Signal(COORD_BITS) # 10
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reg_bitblt_dst_y = Signal(COORD_BITS) # 11
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reg_src_stride = Signal(COORD_BITS) # 12
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reg_dst_stride = Signal(COORD_BITS) # 13
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reg_src_ptr = Signal(32) # 14
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reg_dst_ptr = Signal(32) # 15
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reg_bitblt_msk_x = Signal(COORD_BITS) # 16
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reg_bitblt_msk_y = Signal(COORD_BITS) # 17
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reg_msk_stride = Signal(COORD_BITS) # 18
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reg_msk_ptr = Signal(32) # 19
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# do-some-work flags
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do_blit = Signal()
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do_fill = Signal()
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do_patt = Signal()
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do_rsmsk8dst32 = Signal()
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do_rsrc32msk32dst32 = Signal()
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do_rsrc32dst32 = Signal()
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# cmd register reg_cmd
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DO_BLIT_BIT = 0
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DO_FILL_BIT = 1
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DO_PATT_BIT = 2
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DO_RSMSK8DST32_BIT = 3
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DO_RSRC32MSK32DST32_BIT = 4
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DO_RSRC32DST32_BIT = 5
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# global status register reg_status
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WORK_IN_PROGRESS_BIT = 0
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# replicate all registers in both endianess
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# we want to avoid byte-reversal on either the host or the Vex
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bus_dat_w_endian = Signal(32)
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bus_dat_r_endian = Signal(32)
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self.comb += [
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If(bus.adr[9], # 9 on bus is 11 for host
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bus_dat_w_endian[24:32].eq(bus.dat_w[ 0: 8]),
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bus_dat_w_endian[16:24].eq(bus.dat_w[ 8:16]),
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bus_dat_w_endian[ 8:16].eq(bus.dat_w[16:24]),
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bus_dat_w_endian[ 0: 8].eq(bus.dat_w[24:32]),
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bus.dat_r[24:32].eq(bus_dat_r_endian[ 0: 8]),
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bus.dat_r[16:24].eq(bus_dat_r_endian[ 8:16]),
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bus.dat_r[ 8:16].eq(bus_dat_r_endian[16:24]),
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bus.dat_r[ 0: 8].eq(bus_dat_r_endian[24:32]),
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).Else(
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bus_dat_w_endian.eq(bus.dat_w),
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bus.dat_r.eq(bus_dat_r_endian),
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)
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]
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self.submodules.wishbone_fsm = wishbone_fsm = FSM(reset_state = "Reset")
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wishbone_fsm.act("Reset",
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NextValue(bus.ack, 0),
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NextState("Idle"))
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wishbone_fsm.act("Idle",
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If(bus.cyc & bus.stb & bus.we & ~bus.ack, #write
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Case(bus.adr[0:9], { # bit 9 is used for endianess, so not there
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"default": [ ],
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# 0: reg_status R/O
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0: [ NextValue(reg_status, bus_dat_w_endian) ], # debug, remove me
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1: [ NextValue(reg_cmd, bus_dat_w_endian),
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NextValue(do_blit, bus_dat_w_endian[DO_BLIT_BIT] & ~reg_status[WORK_IN_PROGRESS_BIT]),
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NextValue(do_fill, bus_dat_w_endian[DO_FILL_BIT] & ~reg_status[WORK_IN_PROGRESS_BIT]),
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NextValue(do_patt, bus_dat_w_endian[DO_PATT_BIT] & ~reg_status[WORK_IN_PROGRESS_BIT]),
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NextValue(do_rsmsk8dst32, bus_dat_w_endian[DO_RSMSK8DST32_BIT] & ~reg_status[WORK_IN_PROGRESS_BIT]),
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NextValue(do_rsrc32msk32dst32, bus_dat_w_endian[DO_RSRC32MSK32DST32_BIT] & ~reg_status[WORK_IN_PROGRESS_BIT]),
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NextValue(do_rsrc32dst32, bus_dat_w_endian[DO_RSRC32DST32_BIT] & ~reg_status[WORK_IN_PROGRESS_BIT]),
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],
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2: [ NextValue(reg_r5_cmd, bus_dat_w_endian) ],
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3: [ NextValue(reg_op, bus_dat_w_endian) ],
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4: [ NextValue(reg_width, bus_dat_w_endian) ],
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5: [ NextValue(reg_height, bus_dat_w_endian) ],
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6: [ NextValue(reg_fgcolor, bus_dat_w_endian) ],
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7: [ NextValue(reg_depth, bus_dat_w_endian) ],
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8: [ NextValue(reg_bitblt_src_x, bus_dat_w_endian) ],
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9: [ NextValue(reg_bitblt_src_y, bus_dat_w_endian) ],
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10: [ NextValue(reg_bitblt_dst_x, bus_dat_w_endian) ],
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11: [ NextValue(reg_bitblt_dst_y, bus_dat_w_endian) ],
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12: [ NextValue(reg_src_stride, bus_dat_w_endian) ],
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13: [ NextValue(reg_dst_stride, bus_dat_w_endian) ],
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14: [ NextValue(reg_src_ptr, bus_dat_w_endian) ],
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15: [ NextValue(reg_dst_ptr, bus_dat_w_endian) ],
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16: [ NextValue(reg_bitblt_msk_x, bus_dat_w_endian) ],
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17: [ NextValue(reg_bitblt_msk_y, bus_dat_w_endian) ],
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18: [ NextValue(reg_msk_stride, bus_dat_w_endian) ],
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19: [ NextValue(reg_msk_ptr, bus_dat_w_endian) ],
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}),
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NextValue(bus.ack, 1),
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).Elif(bus.cyc & bus.stb & ~bus.we & ~bus.ack, #read
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Case(bus.adr[0:9], { # bit 9 is used for endianess, so not there
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"default": [ NextValue(bus_dat_r_endian, 0xDEADBEEF) ],
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0: [ NextValue(bus_dat_r_endian, reg_status) ],
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1: [ NextValue(bus_dat_r_endian, reg_cmd) ],
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2: [ NextValue(bus_dat_r_endian, reg_r5_cmd) ],
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3: [ NextValue(bus_dat_r_endian, reg_op) ],
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4: [ NextValue(bus_dat_r_endian, reg_width) ],
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5: [ NextValue(bus_dat_r_endian, reg_height) ],
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6: [ NextValue(bus_dat_r_endian, reg_fgcolor) ],
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7: [ NextValue(bus_dat_r_endian, reg_depth) ],
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8: [ NextValue(bus_dat_r_endian, reg_bitblt_src_x) ],
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9: [ NextValue(bus_dat_r_endian, reg_bitblt_src_y) ],
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10: [ NextValue(bus_dat_r_endian, reg_bitblt_dst_x) ],
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11: [ NextValue(bus_dat_r_endian, reg_bitblt_dst_y) ],
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12: [ NextValue(bus_dat_r_endian, reg_src_stride) ],
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13: [ NextValue(bus_dat_r_endian, reg_dst_stride) ],
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14: [ NextValue(bus_dat_r_endian, reg_src_ptr) ],
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15: [ NextValue(bus_dat_r_endian, reg_dst_ptr) ],
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16: [ NextValue(bus_dat_r_endian, reg_bitblt_msk_x) ],
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17: [ NextValue(bus_dat_r_endian, reg_bitblt_msk_y) ],
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18: [ NextValue(bus_dat_r_endian, reg_msk_stride) ],
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19: [ NextValue(bus_dat_r_endian, reg_msk_ptr) ],
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}),
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NextValue(bus.ack, 1),
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).Else(
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NextValue(bus.ack, 0),
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)
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)
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# also in blit.c, for r5-cmd
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FUN_DONE_BIT = 31
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FUN_BLIT_BIT = 0
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FUN_FILL_BIT = 1
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FUN_PATT_BIT = 2
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FUN_RSMSK8DST32_BIT = 3
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FUN_RSRC32MSK32DST32_BIT = 4
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FUN_RSRC32DST32_BIT = 5
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# to hold the Vex in reset
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self.local_reset = local_reset = Signal(reset = 1)
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self.sync += [
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If(reg_r5_cmd[FUN_DONE_BIT],
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reg_r5_cmd.eq(0),
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reg_status[WORK_IN_PROGRESS_BIT].eq(0),
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local_reset.eq(1),
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#timeout.eq(timeout_rst),
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).Elif(do_blit & ~reg_status[WORK_IN_PROGRESS_BIT],
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do_blit.eq(0),
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reg_r5_cmd[FUN_BLIT_BIT].eq(1),
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reg_status[WORK_IN_PROGRESS_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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).Elif(do_fill & ~reg_status[WORK_IN_PROGRESS_BIT],
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do_fill.eq(0),
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reg_r5_cmd[FUN_FILL_BIT].eq(1),
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reg_status[WORK_IN_PROGRESS_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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).Elif(do_patt & ~reg_status[WORK_IN_PROGRESS_BIT],
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do_patt.eq(0),
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reg_r5_cmd[FUN_PATT_BIT].eq(1),
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reg_status[WORK_IN_PROGRESS_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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).Elif(do_rsmsk8dst32 & ~reg_status[WORK_IN_PROGRESS_BIT],
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do_rsmsk8dst32.eq(0),
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reg_r5_cmd[FUN_RSMSK8DST32_BIT].eq(1),
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reg_status[WORK_IN_PROGRESS_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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).Elif(do_rsrc32msk32dst32 & ~reg_status[WORK_IN_PROGRESS_BIT],
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do_rsrc32msk32dst32.eq(0),
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reg_r5_cmd[FUN_RSRC32MSK32DST32_BIT].eq(1),
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reg_status[WORK_IN_PROGRESS_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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).Elif(do_rsrc32dst32 & ~reg_status[WORK_IN_PROGRESS_BIT],
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do_rsrc32dst32.eq(0),
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reg_r5_cmd[FUN_RSRC32DST32_BIT].eq(1),
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reg_status[WORK_IN_PROGRESS_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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)
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]
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self.ibus = ibus = wishbone.Interface()
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#self.dbus = dbus = wishbone.Interface()
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vex_reset = Signal()
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dbus_raw = wishbone.Interface(data_width=128, adr_width=28) # wide interface from the Vex, master
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dbus_sys = wishbone.Interface(data_width=128, adr_width=28) # wide interface to system wishbone
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dbus_mem = wishbone.Interface(data_width=128, adr_width=28) # wide interface for direct memory access
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self.dbus = dbus_sys
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#masters = {}
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#masters["VexRiscv_AccelFB"] = dbus_raw
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##slaves["VexSystemAccess"] = dbus
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##regions["VexSystemAccess"] = SoCRegion(origin=soc.mem_map.get("goblin_bt", None), size=0x00100000, cached=False)
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##slaves["VexMemoryAccess"] = dbus_mem
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##regions["VexSystemAccess"] = SoCRegion(origin=soc.mem_map.get("main_ram", None), size=0x10000000, cached=True)
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#function_VexSystemAccess = lambda x: (x[24:28] != 0x8)
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#function_VexMemoryAccess = lambda x: (x[24:28] == 0x8)
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##function_VexSystemAccess = lambda x: (True)
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##function_VexMemoryAccess = lambda x: (False)
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#slaves = [
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# (function_VexSystemAccess, dbus_sys),
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# (function_VexMemoryAccess, dbus_mem),
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#]
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#self.submodules.crossbar = wishbone.Crossbar(
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# masters = masters.values(),
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# slaves = slaves,
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# register = False,
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# timeout_cycles = None
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#)
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#self.submodules.shared = wishbone.InterconnectShared(
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# masters = masters.values(),
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# slaves = slaves,
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# register = False,
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# timeout_cycles = None
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#)
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self.comb += [
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If((dbus_raw.adr[24:28] == 0x8),
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dbus_sys.cyc.eq(0),
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dbus_sys.stb.eq(0),
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dbus_mem.cyc.eq(dbus_raw.cyc),
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dbus_mem.stb.eq(dbus_raw.stb),
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dbus_raw.ack.eq(dbus_mem.ack),
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dbus_raw.err.eq(dbus_mem.err),
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dbus_raw.dat_r.eq(dbus_mem.dat_r),
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).Else(
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dbus_sys.cyc.eq(dbus_raw.cyc),
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dbus_sys.stb.eq(dbus_raw.stb),
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dbus_mem.cyc.eq(0),
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dbus_mem.stb.eq(0),
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dbus_raw.ack.eq(dbus_sys.ack),
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dbus_raw.err.eq(dbus_sys.err),
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dbus_raw.dat_r.eq(dbus_sys.dat_r),
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),
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dbus_sys.dat_w.eq(dbus_raw.dat_w),
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dbus_mem.dat_w.eq(dbus_raw.dat_w),
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dbus_sys.we.eq(dbus_raw.we),
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dbus_mem.we.eq(dbus_raw.we),
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dbus_sys.adr.eq(dbus_raw.adr),
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dbus_mem.adr.eq(dbus_raw.adr),
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dbus_sys.sel.eq(dbus_raw.sel),
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dbus_mem.sel.eq(dbus_raw.sel),
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dbus_sys.cti.eq(dbus_raw.cti),
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dbus_mem.cti.eq(dbus_raw.cti),
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dbus_sys.bte.eq(dbus_raw.bte),
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dbus_mem.bte.eq(dbus_raw.bte),
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]
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# now connect the memory
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# memory port
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port = soc.sdram.crossbar.get_port()
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assert(port.data_width == 128)
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self.submodules.wb2native = LiteDRAMWishbone2Native(
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wishbone = dbus_mem,
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port = port,
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base_address = soc.bus.regions["main_ram"].origin
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)
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self.comb += vex_reset.eq(ResetSignal("sys") | local_reset)
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self.specials += Instance(self.get_netlist_name(),
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i_clk = ClockSignal("sys"),
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i_reset = vex_reset,
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o_iBusWishbone_CYC = ibus.cyc,
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o_iBusWishbone_STB = ibus.stb,
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i_iBusWishbone_ACK = ibus.ack,
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o_iBusWishbone_WE = ibus.we,
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o_iBusWishbone_ADR = ibus.adr,
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i_iBusWishbone_DAT_MISO = ibus.dat_r,
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o_iBusWishbone_DAT_MOSI = ibus.dat_w,
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o_iBusWishbone_SEL = ibus.sel,
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i_iBusWishbone_ERR = ibus.err,
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o_iBusWishbone_CTI = ibus.cti,
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o_iBusWishbone_BTE = ibus.bte,
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o_dBusWishbone_CYC = dbus_raw.cyc,
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o_dBusWishbone_STB = dbus_raw.stb,
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i_dBusWishbone_ACK = dbus_raw.ack,
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o_dBusWishbone_WE = dbus_raw.we,
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o_dBusWishbone_ADR = dbus_raw.adr,
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i_dBusWishbone_DAT_MISO = dbus_raw.dat_r,
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o_dBusWishbone_DAT_MOSI = dbus_raw.dat_w,
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o_dBusWishbone_SEL = dbus_raw.sel,
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i_dBusWishbone_ERR = dbus_raw.err,
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o_dBusWishbone_CTI = dbus_raw.cti,
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o_dBusWishbone_BTE = dbus_raw.bte,)
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self.add_sources(platform)
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def get_netlist_name(self):
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return "VexRiscv"
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class GoblinAccelNuBus(GoblinAccel):
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def add_sources(self, platform):
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platform.add_source("/home/dolbeau/NuBusFPGA/nubus-to-ztex-gateware/VexRiscv_GoblinAccel_NuBus.v", "verilog")
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class GoblinAccelSBus(GoblinAccel):
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def add_sources(self, platform):
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led0 = platform.request("SBUS_DATA_OE_LED")
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self.comb += [ led0.eq(~self.local_reset), ]
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platform.add_source("/home/dolbeau/NuBusFPGA/nubus-to-ztex-gateware/VexRiscv_GoblinAccel_SBus.v", "verilog")
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