156 lines
4.0 KiB
C
156 lines
4.0 KiB
C
#include "NuBusFPGADrvr.h"
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#include "NuBusFPGARAMDskDrvr.h"
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#include <Traps.h>
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#include <ROMDefs.h>
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#define PRIM_WRITEREG(reg, val) \
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*((volatile UInt32*)(a32+GOBOFB_BASE+reg)) = (UInt32)val
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#define PRIM_READREG(reg) \
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(*((volatile UInt32*)(a32+GOBOFB_BASE+reg)))
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#pragma parameter __D0 Primary(__A0)
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UInt32 Primary(SEBlock* seblock) {
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UInt32 a32 = 0xF0000000 | ((UInt32)seblock->seSlot << 24);
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UInt32 a32_l0, a32_l1;
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UInt32 a32_4p0, a32_4p1;
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SpBlock spblock;
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/* UInt8 pram[8]; */
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OSErr err;
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UInt16 i,j, hres, vres;
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char busMode;
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UniversalProcPtr qd32ptr, unimpptr;
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busMode = 1;
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SwapMMUMode ( &busMode ); // to32 // this likely won't work on older MacII ???
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PRIM_WRITEREG(GOBOFB_VBL_MASK, 0);// disable interrupts on FB
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PRIM_WRITEREG(DMA_IRQ_CTL, revb(0x2));// disable/clear interrupts on DSK
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/* PRIM_WRITEREG(GOBOFB_DEBUG, 0x87654321);// trace */
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/* PRIM_WRITEREG(GOBOFB_DEBUG, busMode);// trace */
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hres = __builtin_bswap32((UInt32)PRIM_READREG(GOBOFB_HRES)); // fixme: endianness
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vres = __builtin_bswap32((UInt32)PRIM_READREG(GOBOFB_VRES)); // fixme: endianness
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/* initialize DRAM controller */
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sdram_init(a32);
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/* grey the screen */
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/* should switch to HW ? */
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a32_l0 = a32;
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a32_l1 = a32 + hres;
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for (j = 0 ; j < vres ; j+= 2) {
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a32_4p0 = a32_l0;
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a32_4p1 = a32_l1;
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for (i = 0 ; i < hres ; i += 4) {
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*((UInt32*)a32_4p0) = 0xAAAAAAAA;
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*((UInt32*)a32_4p1) = 0x55555555;
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a32_4p0 += 4;
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a32_4p1 += 4;
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}
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a32_l0 += 2*hres;
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a32_l1 += 2*hres;
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}
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SwapMMUMode ( &busMode ); // restore
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{ // disable non-default entries
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SpBlock spb;
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err = noErr;
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do {
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spb.spParamData = 1<<foneslot|1<<fnext;
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spb.spCategory = catDisplay;
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spb.spCType = typeVideo;
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spb.spDrvrSW = drSwApple;
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spb.spDrvrHW = 0xBEEF;
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spb.spTBMask = 0; /* match everything above */
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spb.spSlot = seblock->seSlot;
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spb.spID = nativeVidMode; /* skip over the 'good' one; we can reset as SNextTypeSRsrc skips disabled */
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spb.spExtDev = 0;
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err = SNextTypeSRsrc(&spb);
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if ((err == noErr) &&
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(spb.spSlot == seblock->seSlot) &&
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(((UInt8)spb.spID) > (UInt8)nativeVidMode) &&
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(((UInt8)spb.spID) < (UInt8)diskResource)) {
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spb.spParamData = 1; /* disable */
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spb.spSlot = seblock->seSlot;
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spb.spExtDev = 0;
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SetSRsrcState(&spb);
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/* PRIM_WRITEREG(GOBOFB_DEBUG, 0xBEEF000F); */
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/* PRIM_WRITEREG(GOBOFB_DEBUG, spb.spID); */
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}
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} while (err == noErr);
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}
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#if 0
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/* call SVersion to figure out if we have a recent SlotManager */
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//spblock.spSlot = seblock->seSlot;
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//spblock.spExtDev = 0;
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err = SVersion(&spblock);
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busMode = 1;
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SwapMMUMode ( &busMode ); // to32
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if (err) {
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/* DCDMF3 p178: if error, old slot manager*/
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/* PRIM_WRITEREG(GOBOFB_DEBUG, 0xFFFFFFFF);*/
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/* PRIM_WRITEREG(GOBOFB_DEBUG, err);*/
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} else {
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/* DCDMF3 p178: new slot manager */
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/* PRIM_WRITEREG(GOBOFB_DEBUG, 0);*/
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/* PRIM_WRITEREG(GOBOFB_DEBUG, spblock.spResult);*/
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}
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SwapMMUMode ( &busMode ); // restore
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/* check for 32-bits QuickDraw */
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qd32ptr = GetTrapAddress(Check32QDTrap);
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unimpptr = GetTrapAddress(_Unimplemented);
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busMode = 1;
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SwapMMUMode ( &busMode ); // to32
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if (qd32ptr == unimpptr) {
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/* no 32QD */
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PRIM_WRITEREG(GOBOFB_DEBUG, 0xFFFFFFFF);
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PRIM_WRITEREG(GOBOFB_DEBUG, unimpptr);
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} else {
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/* yes 32QD */
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PRIM_WRITEREG(GOBOFB_DEBUG, 0x00C0FFEE);
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}
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SwapMMUMode ( &busMode ); // restore
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/* check the content of the PRAM */
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spblock.spSlot = seblock->seSlot;
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spblock.spResult = (UInt32)pram;
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err = SReadPRAMRec(&spblock);
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#if 0
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PRIM_WRITEREG(GOBOFB_DEBUG, 0x88888888);
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for (j = 0 ; j < 8 ; j++)
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PRIM_WRITEREG(GOBOFB_DEBUG, (uint32_t)pram[j]);
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PRIM_WRITEREG(GOBOFB_DEBUG, 0x88888888);
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#endif
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busMode = 1;
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SwapMMUMode ( &busMode ); // to32
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if (err) {
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/* PRIM_WRITEREG(GOBOFB_DEBUG, 0xFFFFFFFF);*/
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/* PRIM_WRITEREG(GOBOFB_DEBUG, err);*/
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} else {
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/* PRIM_WRITEREG(GOBOFB_DEBUG, 0xC0FFEE00);*/
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/* for (i = 0 ; i < 8 ; i++) */
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/* PRIM_WRITEREG(GOBOFB_DEBUG, pram[i]);*/
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}
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SwapMMUMode ( &busMode ); // restore
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#endif
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seblock->seStatus = 1;
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return 0;
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}
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/* SDRAM INIT */
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