Romain Dolbeau b7a941e61b typo		2022-11-01 14:36:46 +01:00
..
ConsoleTest
DeclROM	DMA + IRQ for RAM Disk	2022-10-08 18:23:01 +02:00
NuBusFPGAInit	track HW changes	2022-09-11 14:36:14 +02:00
VintageBusFPGA_Common@c7d117677e	update submodule	2022-11-01 09:08:20 +01:00
XiBus@e20f6ca7c4	move to submodules XiBus	2022-10-31 15:28:08 +01:00
.gitignore
74fct245.v
CG6.scala
DepVideoEqu.a
do
GenGoblinAccel.scala
Goblin2c.scala	Rounding FMA	2022-08-27 08:30:21 +02:00
Goblin.scala	Rounding FMA	2022-08-27 08:30:21 +02:00
MakeFile
nubus_arbiter.v
nubus_cpld.ucf
nubus_cpld.v	typo	2022-11-01 11:34:06 +01:00
nubus_cpldinfpga.v	typos	2022-11-01 12:41:58 +01:00
nubus_cpu_wb.py
nubus_fpga_V1_0_timings.xdc	missing entries (???)	2022-09-20 23:11:59 +02:00
nubus_full_sampling.py	DMA + IRQ for RAM Disk	2022-10-08 18:23:01 +02:00
nubus_full.py	DMA + IRQ for RAM Disk	2022-10-08 18:23:01 +02:00
nubus_master_tst.py
nubus_mem_wb.py
nubus_memfifo_wb.py
nubus_sampling.v
nubus_stat.py
nubus_to_fpga_export.py
nubus_to_fpga_soc.py	typos	2022-11-01 12:41:58 +01:00
nubus-to-ztex-io-signal.xdc	more stuff thinking about V1.2	2022-11-01 09:29:34 +01:00
nubus-to-ztex-pin-signal.xdc	update xdc	2022-11-01 09:45:57 +01:00
nubus.py	typo	2022-11-01 14:36:46 +01:00
nubus.v	draft integration of CPLD in FPGA - can't have internal tri-state signals...	2022-11-01 11:36:51 +01:00
NuBusFPGADrvr.a
NuBusFPGAPrimaryInit.a
NuBusFPGASecondaryInit.a
post_process_timings.sh
rom.a
sdram_init.py	move wb_master to common	2022-10-31 17:02:21 +01:00
slave_tb.sv
slave_V1.2_tb.sv	typos	2022-11-01 12:41:58 +01:00
sn74cb3t3125.v	more stuff thinking about V1.2	2022-11-01 09:29:34 +01:00
sn74lvt125.v
ztex213_nubus.py	typos	2022-11-01 12:41:58 +01:00