65 lines
1.4 KiB
C
65 lines
1.4 KiB
C
#ifndef __NUBUSFPGA_HW_H__
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#define __NUBUSFPGA_HW_H__
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//#define GOBLIN_FB_BASE 0xFC000000 // FIXME !!!!
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#define GOBLIN_BT_OFFSET 0x00900000
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#define GOBLIN_ACCEL_OFFSET 0x00901000
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#define GOBLIN_ACCEL_OFFSET_LE 0x00901800
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#define GOBLIN_FB_OFFSET 0x00000000
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#define GOBLIN_PATTERN_OFFSET 0x007F0000 // 8 MiB - 64 KiB
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#define u_int32_t volatile unsigned long
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// status
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#define WORK_IN_PROGRESS_BIT 0
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// cmd
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#define DO_BLIT_BIT 0 // all hardwired in goblin_accel.py
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#define DO_FILL_BIT 1
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#define DO_PATT_BIT 2
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#define DO_RSMSK8DST32_BIT 3
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#define DO_RSRC32MSK32DST32_BIT 4
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#define DO_RSRC32DST32_BIT 5
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#define FUN_DONE_BIT 31
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struct goblin_bt_regs {
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u_int32_t mode;
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u_int32_t vblmask;
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u_int32_t videoctrl;
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u_int32_t intrclear;
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u_int32_t reset;
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u_int32_t lutaddr;
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u_int32_t lut;
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u_int32_t debug;
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};
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struct goblin_accel_regs {
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u_int32_t reg_status; // 0
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u_int32_t reg_cmd;
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u_int32_t reg_r5_cmd;
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u_int32_t reg_op;
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u_int32_t reg_width; // 4
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u_int32_t reg_height;
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u_int32_t reg_fgcolor;
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u_int32_t reg_depth;
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u_int32_t reg_bitblt_src_x; // 8
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u_int32_t reg_bitblt_src_y;
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u_int32_t reg_bitblt_dst_x;
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u_int32_t reg_bitblt_dst_y;
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u_int32_t reg_src_stride; // 12
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u_int32_t reg_dst_stride;
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u_int32_t reg_src_ptr; // 14
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u_int32_t reg_dst_ptr;
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u_int32_t reg_msk_x; // 16
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u_int32_t reg_msk_y;
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u_int32_t reg_msk_stride; // 18
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u_int32_t reg_msk_ptr;
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};
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#endif // __NUBUSFPGA_HW_H__
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