62 lines
2.5 KiB
Python
62 lines
2.5 KiB
Python
from migen import *
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from migen.genlib.fifo import *
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import litex
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from litex.soc.interconnect import wishbone
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class PingMaster(Module):
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def __init__(self):
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self.bus_slv = bus_slv = wishbone.Interface()
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self.bus_mst = bus_mst = wishbone.Interface()
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valu_reg = Signal(32)
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addr_reg = Signal(32)
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writ_del = Signal(6)
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addr_reg_rev = Signal(32)
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self.comb += [ addr_reg_rev[ 0: 8].eq(addr_reg[24:32]),
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addr_reg_rev[ 8:16].eq(addr_reg[16:24]),
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addr_reg_rev[16:24].eq(addr_reg[ 8:16]),
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addr_reg_rev[24:32].eq(addr_reg[ 0: 8]), ]
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self.sync += If(writ_del != 0,
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writ_del.eq(writ_del - 1))
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self.submodules.wishbone_fsm = wishbone_fsm = FSM(reset_state = "Reset")
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wishbone_fsm.act("Reset",
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NextValue(bus_slv.ack, 0),
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NextState("Idle"))
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wishbone_fsm.act("Idle",
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If(bus_slv.cyc & bus_slv.stb & bus_slv.we & ~bus_slv.ack, #write
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# FIXME: should check for prefix?
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Case(bus_slv.adr[0:1], {
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0x0: [ NextValue(valu_reg, bus_slv.dat_w[0:32]), ],
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0x1: [ NextValue(addr_reg, bus_slv.dat_w[0:32]),
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NextValue(writ_del, 3), ],
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}),
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NextValue(bus_slv.ack, 1),
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).Elif(bus_slv.cyc & bus_slv.stb & ~bus_slv.we & ~bus_slv.ack, #read
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Case(bus_slv.adr[0:1], {
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0x0: [ NextValue(bus_slv.dat_r, valu_reg), ],
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0x1: [ NextValue(bus_slv.dat_r, addr_reg), ],
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}),
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NextValue(bus_slv.ack, 1),
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).Else(
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NextValue(bus_slv.ack, 0),
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),
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If(writ_del == 1,
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NextState("Write"),),
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)
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wishbone_fsm.act("Write",
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bus_mst.cyc.eq(1),
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bus_mst.stb.eq(1),
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bus_mst.we.eq(1),
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bus_mst.dat_w.eq(valu_reg),
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bus_mst.adr.eq(addr_reg[2:32]),
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bus_mst.sel.eq(0xf),
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If(bus_mst.ack,
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NextState("Idle")),
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)
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