169 lines
8.3 KiB
Python
169 lines
8.3 KiB
Python
from migen import *
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from migen.genlib.fifo import *
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from migen.genlib.cdc import *
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from migen.fhdl.specials import Tristate
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import litex
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from litex.soc.interconnect import wishbone
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class MC68030_SYNC_FSM(Module):
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def __init__(self, platform, wb_read, wb_write, cd_m68k="m68k"):
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# 68030
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A = platform.request("A") # 32 # address, I[O]
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D = platform.request("D") # 32 # data, IO
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RW_n = platform.request("RW_n") # direction of bus transfer with respect to the main processor, I [three-state, high read, write low]
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DS_n = platform.request("DS_n") # data strobe, I[O]
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BERR_n = platform.request("BERR_n") # bus error, [I]O
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HALT_n = platform.request("HALT_n") # Signal indicating that main processor should suspend all bus activity, O
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SIZ_n = platform.request("SIZ") # 2 # in conjunction with processor’s dynamic bus sizing capabilities to indicate number of bytes remaining to be transferred during current bus cycle, I [three-state]
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FC = platform.request("FC") # 3 # Function code used to identify address space of current bus cycle, I[O]
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# RESET_n = platform.request("RESET_n") # Bidirectional signal that initiates system reset.
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# RMC = platform.request("RMC") # identifies current bus cycle as part of indivisible read-modify-write operation, three-state
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# DSACK_n = platform.request("DSACK_n") # 2 # Data transfer acknowledge, I[O]
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# CBREQ_n = platform.request("CBREQ_n") # CPU burst reuqest, I ?
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# CBACK_n = platform.request("CBACK_n") # CPU burst ack, w/ STERM, IO ?
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#STERM_n = platform.request("STERM_n") # indicates termination of a transfer using the MC68030 synchronous cycle, [I]O
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# in this version STERM is negated by the driver
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STERM = platform.request("STERM") # indicates termination of a transfer using the MC68030 synchronous cycle, [I]O
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CPU_AS_n = platform.request("CPU_AS_n") # address strobe, I [three-state]
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# CIOUT_n = platform.request("CIOUT_n") # cache inhibit out (from cpu), I
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# BR_n = platform.request("BR_n") # bus request, I
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# CPU_BG_n = platform.request("CPU_BG_n") # processor bus grant, I ?
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# BGACK_n = platform.request("BGACK_n") # bus grant ack, I
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# IPL = platform.request("IPL") # 3 # Interrupt priority-level lines.
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## DBEN_n not in PDS slot (buffer enable)
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## CIIN_n not in PDS slot (cache in inhibit)
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## OCS_n not in PDS slot (operand cycle start)
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## ECS_n not in PDS slot (external cycle start) # is on IIfx
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# not 68030
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# CACHE = platform.request("CACHE")
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# CLK16M not connected
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# CPU_CLK = platform.request("CPU_CLK") # handled in CRG
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# CPU_DISABLE_n = platform.request("CPU_DISABLE_n") # Disables the MC68030 CPU (and MC68882 FPU, if installed) on the main logic board. This signal is used by a PDS card that replaces the main processor.
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# CPU_TYPE = platform.request("CPU_TYPE") # Defines bus protocol for the PDS; logical one (1) for MC68020 and MC68030, logical zero (0) for MC68040. # not in IIci
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# FC3 not connected # Additional function code bit, used to indicate that the software is running in 32-bit address mode. (As in the Macintosh LC II, the software always runs in 32-bit mode.) # not in IIci
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# FPU_SEL_n = platform.request("FPU_SEL_n") # Select signal for an optional MC68881 or MC68882 FPU on the card. # not in IIci
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# PDS_AS not connected (16 MHz AS)
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# PDS_DSACK not connected (16 MHz DSACK)
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# 16MASTER not connected (grounded on board for 32 bits)
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# SLOT_BG_n = platform.request("SLOT_BG_n") # Bus grant signal to the expansion card. # not in IIci
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SLOTIRQ_E_n = platform.request("SLOTIRQ_n") # IRQ for (pseudo-)slot E # not in IIci
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# SLOTIRQ_C_n # not supported on LCIII/LC520 # IRQ for (pseudo-)slot C # not in IIci
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# SLOTIRQ_D_n # not supported on LCIII/LC520 # IRQ for (pseudo-)slot D # not in IIci
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# SNDOUT not connected (Apple II-style sound) # not in IIci
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# # ROMOE_n only in IIci
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# # BUSLOCK_n only in SE/30, IIsi (nubus bus lock)
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# # NUBUS_n only in SE/30, IIsi (signal nubus access)
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# # BCLK only in SE/30, IIsi (VIA clock)
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# # PFW only in SE/30, IIsi (power failure)
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#card_select = Signal()
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# we don't have 24-bits mode, FC3 is assumed to be 1
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#self.comb += card_select.eq(A[31] & (~FC[0] | ~FC[1] | ~FC[2])) # high-order address bit set & not in CPU space
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A_i = Signal(32)
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#A_o = Signal(32)
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#A_oe = Signal(reset = 0)
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#self.specials += Tristate(A, A_o, A_oe, A_i)
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A_latch = Signal(32)
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self.comb += [ A_I.eq(A) ]
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D_i = Signal(32)
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D_o = Signal(32)
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D_oe = Signal(reset = 0)
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self.specials += Tristate(D, D_o, D_oe, D_i)
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D_latch = Signal(32)
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#DSACK_i_n = Signal(2)
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#DSACK_o_n = Signal(2)
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#DSACK_oe = Signal(reset = 0)
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#self.specials += Tristate(DSACK_n, DSACK_o_n, DSACK_oe, DSACK_i_n)
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SIZ_i_n = Signal(2)
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#SIZ_o_n = Signal(2)
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#SIZ_oe = Signal(reset = 0)
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#self.specials += Tristate(SIZ_n, SIZ_o_n, SIZ_oe, SIZ_i_n)
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self.comb += [ SIZ_i_n.eq(SIZ_n) ]
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AS_i_n = Signal()
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#AS_o_n = Signal()
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#AS_oe = Signal(reset = 0)
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#self.specials += Tristate(CPU_AS_n, AS_o_n, AS_oe, AS_i_n)
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self.comb += [ AS_i_n.eq(AS_n) ]
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DS_i_n = Signal()
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#DS_o_n = Signal()
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#DS_oe = Signal(reset = 0)
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#self.specials += Tristate(DS_n, DS_o_n, DS_oe, DS_i_n)
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self.comb += [ DS_i_n.eq(DS_n) ]
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my_space = Signal()
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self.comb += [ my_space.eq((A_i[24:31] == 0xf9) & (~FC[0] | ~FC[1] | ~FC[2])) ] # checkme
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self.submodules.slave_fsm = slave_fsm = ClockDomainsRenamer(cd_m68k)(FSM(reset_state="Reset"))
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slave_fsm.act("Reset",
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NextState("Idle")
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)
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slave_fsm.act("Idle",
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If((my_space & ~AS_i_n & RW_n), # Read
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wb_read.cyc.eq(1),
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wb_read.stb.eq(1),
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wb_read.we.eq(0),
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wb_read.sel.eq(0xf), # always read 32-bits for cache
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wb_read.adr.eq(A_i[2:32]),
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NextValue(A_latch, A_i[2:32]),
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STERM.eq(0), # insert delay
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NextState("Read"),
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).Elif((my_space & ~AS_i_n & ~RW_n), # Write, data not ready just yet
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NextValue(A_latch, A_i[2:32]),
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STERM.eq(0), # insert delay
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NextState("Write"),
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)
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)
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slave_fsm.act("Read",
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wb_read.cyc.eq(1),
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wb_read.stb.eq(1),
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wb_read.we.eq(0),
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wb_read.sel.eq(0xf),
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wb_read.adr.eq(A_latch[2:32]),
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STERM.eq(0), # insert delay
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If(wb_read.ack,
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NextValue(D_latch, wb_read.dat_r),
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D_oe.eq(1),
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D_o.eq(wb_read.dat_r),
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STERM.eq(1), # ACK 32-bits for 1 cycle
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NextState("FinishRead"),
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)
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)
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slave_fsm.act("FinishRead",
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D_oe.eq(1), # keep data one more cycle
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D_o.eq(D_latch),
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STERM.eq(1), # ACK finished after 1 cycle
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NextState("Idle"),
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)
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slave_fsm.act("Write",
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wb_write.cyc.eq(1),
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wb_write.stb.eq(1),
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wb_write.we.eq(1),
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# assumes SIZ & A_i[0:2] are both 0 (longword, aligned), checkme
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wb_write.sel.eq(0xF),
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wb_write.adr.eq(A_latch[2:32]),
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wb_write.dat_w.eq(D_i), # data available this cycle (and later)
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STERM.eq(0), # wait
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If(wb_write.ack,
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STERM.eq(1),
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NextState("FinishWrite"),
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)
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)
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slave_fsm.act("FinishWrite", # unnecessary ?
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STERM.eq(0), # finish ACK after one cycle
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NextState("Idle"),
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)
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