This commit is contained in:
Zane Kaminski 2024-01-27 17:28:09 -05:00
parent a19f105125
commit 0d06c47184
128 changed files with 264349 additions and 281954 deletions

27
.gitignore vendored
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@ -2,36 +2,17 @@
# Format documentation: http://kicad-pcb.org/help/file-formats/
# Temporary files
*.000
*.bak
*.bck
*.kicad_pcb-bak
*.sch-bak
*~
_autosave-*
*.tmp
*-rescue.lib
*-save.pro
*-save.kicad_pcb
fp-info-cache
# Netlist files (exported from Eeschema)
*.net
# Autorouter files (exported from Pcbnew)
*.dsn
*.ses
*.DS_Store
Documentation/~$MSIMM30SelectionGuide.docx
GW4190-4MB-SOJ/GW4190-SOJ-backups/*
GW4190-4MB-SOP/GW4190-SOP-backups/*
GW4191-4MB-parity-SOJ/GW4191-SOJ-backups/*
GW4191-4MB-parity-SOP/GW4191-SOP-backups/*
GW4192-16MB-SOJ/GW4192-SOJ-backups/*
GW4192-16MB-SOP/GW4192-SOP-backups/*
GW4194-4MB-CBRFIX-SOJ-DC/GW4194-SOJ-DC-backups/*
GW4194-4MB-CBRFIX-SOJ-DP/GW4194-SOJ-DP-backups/*
GW4194-4MB-CBRFIX-SOP/GW4194-SOP-backups/*
GW4194-4MB-CBRFIX-SOJ-DC/GW4194-backups/*
GW4194-4MB-CBRFIX-SOJ-DP/GW4194-backups/*
GW4194-4MB-CBRFIX-SOP-DC/GW4194-backups/*
GW4194-4MB-CBRFIX-SOP-DP/GW4194-backups/*
*.kicad_prl
GW4194-4MB-CBRFIX-SOJ-DC/GW4194-SOJ-backups/GW4194-SOJ-2023-01-20_194304.zip

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@ -4,7 +4,7 @@
"design_settings": {
"defaults": {
"board_outline_line_width": 0.15,
"copper_line_width": 0.19999999999999998,
"copper_line_width": 0.15239999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
@ -64,32 +64,43 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"copper_sliver": "error",
"courtyards_overlap": "warning",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"duplicate_footprints": "error",
"extra_footprint": "error",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "ignore",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"missing_footprint": "error",
"net_conflict": "error",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "warning",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
@ -98,7 +109,6 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
@ -107,29 +117,77 @@
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.25,
"min_clearance": 0.15,
"min_connection": 0.12,
"min_copper_edge_clearance": 0.30479999999999996,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_hole_to_hole": 0.254,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.19999999999999998,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.15,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.508,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.1524,
0.254,
0.15,
0.2,
0.25,
0.3,
0.35,
0.4,
0.45,
0.508,
0.5,
0.6,
0.762,
0.8,
1.0,
1.27,
1.524
],
@ -138,6 +196,10 @@
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.5,
"drill": 0.3
},
{
"diameter": 0.6,
"drill": 0.3
@ -145,6 +207,14 @@
{
"diameter": 0.8,
"drill": 0.4
},
{
"diameter": 1.0,
"drill": 0.5
},
{
"diameter": 1.524,
"drill": 0.762
}
],
"zones_allow_external_fillets": false,
@ -380,7 +450,7 @@
"classes": [
{
"bus_width": 12,
"clearance": 0.1524,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
@ -390,9 +460,9 @@
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1524,
"via_diameter": 0.508,
"via_drill": 0.2,
"track_width": 0.15,
"via_diameter": 0.5,
"via_drill": 0.3,
"wire_width": 6
}
],

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@ -1,12 +1,12 @@
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M02*

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,165 @@
{
"Header": {
"GenerationSoftware": {
"Vendor": "KiCad",
"Application": "Pcbnew",
"Version": "7.0.1-0"
},
"CreationDate": "2023-11-01T19:37:53-04:00"
},
"GeneralSpecs": {
"ProjectId": {
"Name": "GW4194",
"GUID": "47573431-3934-42e6-9b69-6361645f7063",
"Revision": "1.1-SOJ-DC"
},
"Size": {
"X": 89.1,
"Y": 20.52
},
"LayerNumber": 4,
"BoardThickness": 1.6108,
"Finish": "None"
},
"DesignRules": [
{
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"PadToPad": 0.15,
"PadToTrack": 0.15,
"TrackToTrack": 0.15,
"MinLineWidth": 0.1524,
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},
{
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}
],
"FilesAttributes": [
{
"Path": "GW4194-F_Cu.gtl",
"FileFunction": "Copper,L1,Top",
"FilePolarity": "Positive"
},
{
"Path": "GW4194-In1_Cu.g2",
"FileFunction": "Copper,L2,Inr",
"FilePolarity": "Positive"
},
{
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},
{
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},
{
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},
{
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{
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{
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},
{
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},
{
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},
{
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},
{
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"Name": "In1.Cu/In2.Cu",
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View File

@ -1,49 +1,54 @@
M48
; DRILL file {KiCad (7.0.0-0)} date Tuesday, February 28, 2023 at 11:31:54 AM
; DRILL file {KiCad 7.0.1-0} date 2023 November 01, Wednesday 19:37:53
; FORMAT={-:-/ absolute / inch / decimal}
; #@! TF.CreationDate,2023-02-28T11:31:54-05:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,(7.0.0-0)
; #@! TF.CreationDate,2023-11-01T19:37:53-04:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,7.0.1-0
; #@! TF.FileFunction,MixedPlating,1,4
FMAT,2
INCH
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T1C0.0079
T1C0.0118
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T2C0.0118
; #@! TA.AperFunction,Plated,PTH,ViaDrill
T3C0.0157
T2C0.0157
; #@! TA.AperFunction,Plated,PTH,ComponentDrill
T4C0.0157
T3C0.0157
; #@! TA.AperFunction,Plated,PTH,ViaDrill
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T4C0.0197
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G90
G05
T1
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