Done with new layouts?

This commit is contained in:
Zane Kaminski 2021-06-19 02:22:35 -04:00
parent b927ecec6d
commit 7041819469
63 changed files with 34457 additions and 71847 deletions

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G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5-0-10_14)*
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### Module positions - created on Friday, February 26, 2021 at 03:39:55 AM ###
### Printed by Pcbnew version kicad (5.1.5-0-10_14)
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Ref,Val,Package,PosX,PosY,Rot,Side
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### Module positions - created on Friday, February 26, 2021 at 03:39:55 AM ###
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## Unit = mm, Angle = deg.
## Side : top
# Ref Val Package PosX PosY Rot Side
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ENDDRAW
ENDDEF
#
# Device_R_Small
#
DEF Device_R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "Device_R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
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update=Friday, May 15, 2020 at 06:04:31 PM
update=Wednesday, June 09, 2021 at 11:45:00 AM
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last_client=kicad
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Text Label 1950 6450 0 50 ~ 0
2A1
Text Label 1950 6850 0 50 ~ 0
2A2
Text Label 1950 7050 0 50 ~ 0
2A5
Text Label 1950 6650 0 50 ~ 0
2A6
Text Label 1950 7250 0 50 ~ 0
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Text Label 1950 7450 0 50 ~ 0
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Text Label 1750 6000 2 50 ~ 0
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Text Label 1750 5800 2 50 ~ 0
A2
Text Label 1750 5600 2 50 ~ 0
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Text Label 1750 5400 2 50 ~ 0
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Text Label 1750 6400 2 50 ~ 0
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Text Label 1950 5350 0 50 ~ 0
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Text Label 1950 5550 0 50 ~ 0
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Text Label 1950 6750 0 50 ~ 0
1A0
Text Label 1950 6950 0 50 ~ 0
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Text Label 1950 7150 0 50 ~ 0
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Text Label 1950 7350 0 50 ~ 0
1A9
$Comp
L GW_RAM:DRAM-4Mx4-SOP-24 U1
U 1 1 5D38F422
P 3800 6650
F 0 "U1" H 3800 7300 50 0000 C CNN
F 1 "AS4C4M4" H 3800 6000 50 0000 C CNN
F 2 "stdpads:SOJ-24-26-300mil" H 3800 5950 50 0001 C CNN
F 3 "https://www.alliancememory.com/wp-content/uploads/pdf/AS6C8008.pdf" H 3800 6150 50 0001 C CNN
1 3800 6650
1 0 0 -1
$EndComp
Text Label 3400 7050 2 50 ~ 0
1A9
$Comp
L power:GND #PWR0105
U 1 1 5D395DE3
P 4200 7150
F 0 "#PWR0105" H 4200 6900 50 0001 C CNN
F 1 "GND" H 4200 7000 50 0000 C CNN
F 2 "" H 4200 7150 50 0001 C CNN
F 3 "" H 4200 7150 50 0001 C CNN
1 4200 7150
1 0 0 -1
$EndComp
Text Label 4200 6750 0 50 ~ 0
~CAS~
Text Label 4200 6850 0 50 ~ 0
~RAS~
Text Label 4200 6950 0 50 ~ 0
~WE~
Text Label 4200 6250 0 50 ~ 0
D5
Text Label 4200 6550 0 50 ~ 0
D4
Text Label 4200 6350 0 50 ~ 0
D7
Text Label 4200 6450 0 50 ~ 0
D6
$Comp
L power:+5V #PWR0106
U 1 1 5D396692
P 4200 6150
F 0 "#PWR0106" H 4200 6000 50 0001 C CNN
F 1 "+5V" H 4200 6300 50 0000 C CNN
F 2 "" H 4200 6150 50 0001 C CNN
F 3 "" H 4200 6150 50 0001 C CNN
1 4200 6150
1 0 0 -1
$EndComp
Text Label 5800 7100 0 50 ~ 0
~OE~
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2A8
Text Label 5000 6900 2 50 ~ 0
2A7
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2A6
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Text Label 5000 7100 2 50 ~ 0
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$Comp
L power:GND #PWR0108
U 1 1 5D3999DD
P 5800 7200
F 0 "#PWR0108" H 5800 6950 50 0001 C CNN
F 1 "GND" H 5800 7050 50 0000 C CNN
F 2 "" H 5800 7200 50 0001 C CNN
F 3 "" H 5800 7200 50 0001 C CNN
1 5800 7200
1 0 0 -1
$EndComp
Text Label 5800 6800 0 50 ~ 0
~CAS~
Text Label 5800 6900 0 50 ~ 0
~RAS~
Text Label 5800 7000 0 50 ~ 0
~WE~
$Comp
L power:+5V #PWR0109
U 1 1 5D3999EA
P 5800 6200
F 0 "#PWR0109" H 5800 6050 50 0001 C CNN
F 1 "+5V" H 5800 6350 50 0000 C CNN
F 2 "" H 5800 6200 50 0001 C CNN
F 3 "" H 5800 6200 50 0001 C CNN
1 5800 6200
1 0 0 -1
$EndComp
Text Label 5800 6600 0 50 ~ 0
D0
Text Label 5800 6500 0 50 ~ 0
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Text Label 5800 6400 0 50 ~ 0
D3
Text Label 5800 6300 0 50 ~ 0
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$Comp
L power:GND #PWR0110
U 1 1 5D3FC319
P 4000 4300
F 0 "#PWR0110" H 4000 4050 50 0001 C CNN
F 1 "GND" H 4000 4150 50 0000 C CNN
F 2 "" H 4000 4300 50 0001 C CNN
F 3 "" H 4000 4300 50 0001 C CNN
1 4000 4300
1 0 0 -1
$EndComp
Wire Wire Line
3600 4300 4000 4300
Connection ~ 4000 4300
Wire Wire Line
4000 4100 3600 4100
$Comp
L Device:C_Small C5
U 1 1 5D3FC322
P 4000 4200
F 0 "C5" H 4092 4246 50 0000 L CNN
F 1 "100n" H 4092 4155 50 0000 L CNN
F 2 "stdpads:C_0805" H 4000 4200 50 0001 C CNN
F 3 "~" H 4000 4200 50 0001 C CNN
1 4000 4200
1 0 0 -1
$EndComp
$Comp
L GW_RAM:DRAM-4Mx4-SOP-24 U2
U 1 1 5D3999D6
P 5400 6700
F 0 "U2" H 5400 7350 50 0000 C CNN
F 1 "AS4C4M4" H 5400 6050 50 0000 C CNN
F 2 "stdpads:SOJ-24-26-300mil" H 5400 6000 50 0001 C CNN
F 3 "https://www.alliancememory.com/wp-content/uploads/pdf/AS6C8008.pdf" H 5400 6200 50 0001 C CNN
1 5400 6700
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R2
U 1 1 60C54176
P 9100 5900
F 0 "R2" H 9159 5946 50 0000 L CNN
F 1 "FPM" H 9159 5855 50 0000 L CNN
F 2 "stdpads:R_0805" H 9100 5900 50 0001 C CNN
F 3 "~" H 9100 5900 50 0001 C CNN
1 9100 5900
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R1
U 1 1 60C5420A
P 9100 5700
F 0 "R1" H 9159 5746 50 0000 L CNN
F 1 "EDO" H 9159 5655 50 0000 L CNN
F 2 "stdpads:R_0805" H 9100 5700 50 0001 C CNN
F 3 "~" H 9100 5700 50 0001 C CNN
1 9100 5700
1 0 0 -1
$EndComp
Text Label 8900 5800 0 50 ~ 0
~OE~
Wire Wire Line
9100 5800 8900 5800
Connection ~ 9100 5800
Text Label 8900 5600 0 50 ~ 0
~CAS~
Wire Wire Line
8900 5600 9100 5600
$Comp
L power:GND #PWR0115
U 1 1 60C57F90
P 9100 6000
F 0 "#PWR0115" H 9100 5750 50 0001 C CNN
F 1 "GND" H 9100 5850 50 0000 C CNN
F 2 "" H 9100 6000 50 0001 C CNN
F 3 "" H 9100 6000 50 0001 C CNN
1 9100 6000
1 0 0 -1
$EndComp
$EndSCHEMATC

View File

@ -1,3 +1,4 @@
(sym_lib_table
(lib (name GW_RAM)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_RAM.lib")(options "")(descr ""))
(lib (name GW_Logic)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_Logic.lib")(options "")(descr ""))
)

View File

@ -0,0 +1,182 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_01x30
#
DEF Connector_Generic_Conn_01x30 J 0 40 Y N 1 F N
F0 "J" 0 1500 50 H V C CNN
F1 "Connector_Generic_Conn_01x30" 0 -1600 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -1495 0 -1505 1 1 6 N
S -50 -1395 0 -1405 1 1 6 N
S -50 -1295 0 -1305 1 1 6 N
S -50 -1195 0 -1205 1 1 6 N
S -50 -1095 0 -1105 1 1 6 N
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 905 0 895 1 1 6 N
S -50 1005 0 995 1 1 6 N
S -50 1105 0 1095 1 1 6 N
S -50 1205 0 1195 1 1 6 N
S -50 1305 0 1295 1 1 6 N
S -50 1405 0 1395 1 1 6 N
S -50 1450 50 -1550 1 1 10 f
X Pin_1 1 -200 1400 150 R 50 50 1 1 P
X Pin_10 10 -200 500 150 R 50 50 1 1 P
X Pin_11 11 -200 400 150 R 50 50 1 1 P
X Pin_12 12 -200 300 150 R 50 50 1 1 P
X Pin_13 13 -200 200 150 R 50 50 1 1 P
X Pin_14 14 -200 100 150 R 50 50 1 1 P
X Pin_15 15 -200 0 150 R 50 50 1 1 P
X Pin_16 16 -200 -100 150 R 50 50 1 1 P
X Pin_17 17 -200 -200 150 R 50 50 1 1 P
X Pin_18 18 -200 -300 150 R 50 50 1 1 P
X Pin_19 19 -200 -400 150 R 50 50 1 1 P
X Pin_2 2 -200 1300 150 R 50 50 1 1 P
X Pin_20 20 -200 -500 150 R 50 50 1 1 P
X Pin_21 21 -200 -600 150 R 50 50 1 1 P
X Pin_22 22 -200 -700 150 R 50 50 1 1 P
X Pin_23 23 -200 -800 150 R 50 50 1 1 P
X Pin_24 24 -200 -900 150 R 50 50 1 1 P
X Pin_25 25 -200 -1000 150 R 50 50 1 1 P
X Pin_26 26 -200 -1100 150 R 50 50 1 1 P
X Pin_27 27 -200 -1200 150 R 50 50 1 1 P
X Pin_28 28 -200 -1300 150 R 50 50 1 1 P
X Pin_29 29 -200 -1400 150 R 50 50 1 1 P
X Pin_3 3 -200 1200 150 R 50 50 1 1 P
X Pin_30 30 -200 -1500 150 R 50 50 1 1 P
X Pin_4 4 -200 1100 150 R 50 50 1 1 P
X Pin_5 5 -200 1000 150 R 50 50 1 1 P
X Pin_6 6 -200 900 150 R 50 50 1 1 P
X Pin_7 7 -200 800 150 R 50 50 1 1 P
X Pin_8 8 -200 700 150 R 50 50 1 1 P
X Pin_9 9 -200 600 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Small
#
DEF Device_R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "Device_R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -30 70 30 -70 0 1 8 N
X ~ 1 0 100 30 D 50 50 1 1 P
X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GW_RAM_DRAM-4Mx4-SOP-24
#
DEF GW_RAM_DRAM-4Mx4-SOP-24 U 0 20 Y Y 1 F N
F0 "U" 0 650 50 H V C CNN
F1 "GW_RAM_DRAM-4Mx4-SOP-24" 0 0 50 V V C CNN
F2 "stdpads:SOP-24-26-300mil" 0 -650 50 H I C CNN
F3 "" 0 -600 50 H I C CNN
$FPLIST
SOJ*10.16x23.49mm*P1.27mm*
$ENDFPLIST
DRAW
S -300 600 300 -600 0 1 10 f
X VDD 1 400 500 100 L 50 50 1 1 W
X A1 10 -400 400 100 R 50 50 1 1 I
X A2 11 -400 300 100 R 50 50 1 1 I
X A3 12 -400 200 100 R 50 50 1 1 I
X VDD 13 400 500 100 L 50 50 1 1 W N
X GND 14 400 -500 100 L 50 50 1 1 W N
X A4 15 -400 100 100 R 50 50 1 1 I
X A5 16 -400 0 100 R 50 50 1 1 I
X A6 17 -400 -100 100 R 50 50 1 1 I
X A7 18 -400 -200 100 R 50 50 1 1 I
X A8 19 -400 -300 100 R 50 50 1 1 I
X D0 2 400 400 100 L 50 50 1 1 B
X NC 20 400 0 100 L 50 50 1 1 N N
X A9 21 -400 -400 100 R 50 50 1 1 I
X ~OE~ 22 400 -400 100 L 50 50 1 1 I
X ~CAS~ 23 400 -100 100 L 50 50 1 1 I
X D2 24 400 200 100 L 50 50 1 1 B
X D3 25 400 100 100 L 50 50 1 1 B
X GND 26 400 -500 100 L 50 50 1 1 W
X D1 3 400 300 100 L 50 50 1 1 B
X ~WE~ 4 400 -300 100 L 50 50 1 1 I
X ~RAS~ 5 400 -200 100 L 50 50 1 1 I
X NC 7 400 0 100 L 50 50 1 1 N N
X A10 8 -400 -500 100 R 50 50 1 1 I
X A0 9 -400 500 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

View File

@ -0,0 +1,262 @@
update=Wednesday, June 09, 2021 at 11:45:00 AM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=simm-30-4mb.net
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.127
MinViaDiameter=0.508
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1524
TrackWidth2=0.1524
TrackWidth3=0.254
TrackWidth4=0.4
TrackWidth5=0.45
TrackWidth6=0.508
TrackWidth7=0.6
TrackWidth8=0.762
TrackWidth9=0.8
TrackWidth10=1.27
TrackWidth11=1.524
ViaDiameter1=0.508
ViaDrill1=0.2
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.8
ViaDrill3=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.07619999999999999
SolderMaskMinWidth=0.127
SolderPasteClearance=-0.03809999999999999
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
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[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=1
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.508
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

View File

@ -336,19 +336,6 @@ F 3 "~" H 3600 4200 50 0001 C CNN
1 3600 4200
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0116
U 1 1 5D14FA7D
P 4400 7050
F 0 "#PWR0116" H 4400 6800 50 0001 C CNN
F 1 "GND" H 4400 6900 50 0000 C CNN
F 2 "" H 4400 7050 50 0001 C CNN
F 3 "" H 4400 7050 50 0001 C CNN
1 4400 7050
1 0 0 -1
$EndComp
Wire Wire Line
4400 7050 4200 7050
Text Label 1950 5650 0 50 ~ 0
2A10
Text Label 1950 5450 0 50 ~ 0
@ -486,19 +473,6 @@ Text Label 5000 6200 2 50 ~ 0
2A0
Text Label 5000 7200 2 50 ~ 0
2A10
$Comp
L power:GND #PWR0107
U 1 1 5D3999CF
P 6000 7100
F 0 "#PWR0107" H 6000 6850 50 0001 C CNN
F 1 "GND" H 6000 6950 50 0000 C CNN
F 2 "" H 6000 7100 50 0001 C CNN
F 3 "" H 6000 7100 50 0001 C CNN
1 6000 7100
1 0 0 -1
$EndComp
Wire Wire Line
6000 7100 5800 7100
Text Label 5000 7100 2 50 ~ 0
2A9
$Comp
@ -575,4 +549,46 @@ F 3 "https://www.alliancememory.com/wp-content/uploads/pdf/AS6C8008.pdf" H 5400
1 5400 6700
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R2
U 1 1 60C54176
P 9100 5900
F 0 "R2" H 9159 5946 50 0000 L CNN
F 1 "FPM" H 9159 5855 50 0000 L CNN
F 2 "stdpads:R_0805" H 9100 5900 50 0001 C CNN
F 3 "~" H 9100 5900 50 0001 C CNN
1 9100 5900
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R1
U 1 1 60C5420A
P 9100 5700
F 0 "R1" H 9159 5746 50 0000 L CNN
F 1 "EDO" H 9159 5655 50 0000 L CNN
F 2 "stdpads:R_0805" H 9100 5700 50 0001 C CNN
F 3 "~" H 9100 5700 50 0001 C CNN
1 9100 5700
1 0 0 -1
$EndComp
Text Label 8900 5800 0 50 ~ 0
~OE~
Wire Wire Line
9100 5800 8900 5800
Connection ~ 9100 5800
Text Label 8900 5600 0 50 ~ 0
~CAS~
Wire Wire Line
8900 5600 9100 5600
$Comp
L power:GND #PWR0115
U 1 1 60C57F90
P 9100 6000
F 0 "#PWR0115" H 9100 5750 50 0001 C CNN
F 1 "GND" H 9100 5850 50 0000 C CNN
F 2 "" H 9100 6000 50 0001 C CNN
F 3 "" H 9100 6000 50 0001 C CNN
1 9100 6000
1 0 0 -1
$EndComp
$EndSCHEMATC

View File

@ -0,0 +1,4 @@
(sym_lib_table
(lib (name GW_RAM)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_RAM.lib")(options "")(descr ""))
(lib (name GW_Logic)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_Logic.lib")(options "")(descr ""))
)

View File

@ -0,0 +1,217 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_01x30
#
DEF Connector_Generic_Conn_01x30 J 0 40 Y N 1 F N
F0 "J" 0 1500 50 H V C CNN
F1 "Connector_Generic_Conn_01x30" 0 -1600 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -1495 0 -1505 1 1 6 N
S -50 -1395 0 -1405 1 1 6 N
S -50 -1295 0 -1305 1 1 6 N
S -50 -1195 0 -1205 1 1 6 N
S -50 -1095 0 -1105 1 1 6 N
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 905 0 895 1 1 6 N
S -50 1005 0 995 1 1 6 N
S -50 1105 0 1095 1 1 6 N
S -50 1205 0 1195 1 1 6 N
S -50 1305 0 1295 1 1 6 N
S -50 1405 0 1395 1 1 6 N
S -50 1450 50 -1550 1 1 10 f
X Pin_1 1 -200 1400 150 R 50 50 1 1 P
X Pin_10 10 -200 500 150 R 50 50 1 1 P
X Pin_11 11 -200 400 150 R 50 50 1 1 P
X Pin_12 12 -200 300 150 R 50 50 1 1 P
X Pin_13 13 -200 200 150 R 50 50 1 1 P
X Pin_14 14 -200 100 150 R 50 50 1 1 P
X Pin_15 15 -200 0 150 R 50 50 1 1 P
X Pin_16 16 -200 -100 150 R 50 50 1 1 P
X Pin_17 17 -200 -200 150 R 50 50 1 1 P
X Pin_18 18 -200 -300 150 R 50 50 1 1 P
X Pin_19 19 -200 -400 150 R 50 50 1 1 P
X Pin_2 2 -200 1300 150 R 50 50 1 1 P
X Pin_20 20 -200 -500 150 R 50 50 1 1 P
X Pin_21 21 -200 -600 150 R 50 50 1 1 P
X Pin_22 22 -200 -700 150 R 50 50 1 1 P
X Pin_23 23 -200 -800 150 R 50 50 1 1 P
X Pin_24 24 -200 -900 150 R 50 50 1 1 P
X Pin_25 25 -200 -1000 150 R 50 50 1 1 P
X Pin_26 26 -200 -1100 150 R 50 50 1 1 P
X Pin_27 27 -200 -1200 150 R 50 50 1 1 P
X Pin_28 28 -200 -1300 150 R 50 50 1 1 P
X Pin_29 29 -200 -1400 150 R 50 50 1 1 P
X Pin_3 3 -200 1200 150 R 50 50 1 1 P
X Pin_30 30 -200 -1500 150 R 50 50 1 1 P
X Pin_4 4 -200 1100 150 R 50 50 1 1 P
X Pin_5 5 -200 1000 150 R 50 50 1 1 P
X Pin_6 6 -200 900 150 R 50 50 1 1 P
X Pin_7 7 -200 800 150 R 50 50 1 1 P
X Pin_8 8 -200 700 150 R 50 50 1 1 P
X Pin_9 9 -200 600 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Small
#
DEF Device_R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "Device_R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -30 70 30 -70 0 1 8 N
X ~ 1 0 100 30 D 50 50 1 1 P
X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GW_RAM_DRAM-4Mx1-SOP-20
#
DEF GW_RAM_DRAM-4Mx1-SOP-20 U 0 20 Y Y 1 F N
F0 "U" 0 650 50 H V C CNN
F1 "GW_RAM_DRAM-4Mx1-SOP-20" 0 0 50 V V C CNN
F2 "stdpads:SOP-24-26-300mil" 0 -650 50 H I C CNN
F3 "" 0 -600 50 H I C CNN
$FPLIST
SOJ*10.16x23.49mm*P1.27mm*
$ENDFPLIST
DRAW
S -300 600 300 -600 0 1 10 f
X D 1 400 400 100 L 50 50 1 1 I
X A1 10 -400 400 100 R 50 50 1 1 I
X A2 11 -400 300 100 R 50 50 1 1 I
X A3 12 -400 200 100 R 50 50 1 1 I
X VDD 13 400 500 100 L 50 50 1 1 W
X A4 14 -400 100 100 R 50 50 1 1 I
X A5 15 -400 0 100 R 50 50 1 1 I
X A6 16 -400 -100 100 R 50 50 1 1 I
X A7 17 -400 -200 100 R 50 50 1 1 I
X A8 18 -400 -300 100 R 50 50 1 1 I
X ~WE~ 2 400 -300 100 L 50 50 1 1 I
X A9 22 -400 -400 100 R 50 50 1 1 I
X NC 23 400 0 100 L 50 50 1 1 N N
X ~CAS~ 24 400 -100 100 L 50 50 1 1 I
X Q 25 400 300 100 L 50 50 1 1 T
X GND 26 400 -500 100 L 50 50 1 1 W
X ~RAS~ 3 400 -200 100 L 50 50 1 1 I
X NC 4 400 50 100 L 50 50 1 1 N N
X A10 5 -400 -500 100 R 50 50 1 1 I
X A0 9 -400 500 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# GW_RAM_DRAM-4Mx4-SOP-24
#
DEF GW_RAM_DRAM-4Mx4-SOP-24 U 0 20 Y Y 1 F N
F0 "U" 0 650 50 H V C CNN
F1 "GW_RAM_DRAM-4Mx4-SOP-24" 0 0 50 V V C CNN
F2 "stdpads:SOP-24-26-300mil" 0 -650 50 H I C CNN
F3 "" 0 -600 50 H I C CNN
$FPLIST
SOJ*10.16x23.49mm*P1.27mm*
$ENDFPLIST
DRAW
S -300 600 300 -600 0 1 10 f
X VDD 1 400 500 100 L 50 50 1 1 W
X A1 10 -400 400 100 R 50 50 1 1 I
X A2 11 -400 300 100 R 50 50 1 1 I
X A3 12 -400 200 100 R 50 50 1 1 I
X VDD 13 400 500 100 L 50 50 1 1 W N
X GND 14 400 -500 100 L 50 50 1 1 W N
X A4 15 -400 100 100 R 50 50 1 1 I
X A5 16 -400 0 100 R 50 50 1 1 I
X A6 17 -400 -100 100 R 50 50 1 1 I
X A7 18 -400 -200 100 R 50 50 1 1 I
X A8 19 -400 -300 100 R 50 50 1 1 I
X D0 2 400 400 100 L 50 50 1 1 B
X NC 20 400 0 100 L 50 50 1 1 N N
X A9 21 -400 -400 100 R 50 50 1 1 I
X ~OE~ 22 400 -400 100 L 50 50 1 1 I
X ~CAS~ 23 400 -100 100 L 50 50 1 1 I
X D2 24 400 200 100 L 50 50 1 1 B
X D3 25 400 100 100 L 50 50 1 1 B
X GND 26 400 -500 100 L 50 50 1 1 W
X D1 3 400 300 100 L 50 50 1 1 B
X ~WE~ 4 400 -300 100 L 50 50 1 1 I
X ~RAS~ 5 400 -200 100 L 50 50 1 1 I
X NC 7 400 0 100 L 50 50 1 1 N N
X A10 8 -400 -500 100 R 50 50 1 1 I
X A0 9 -400 500 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,262 @@
update=Wednesday, June 09, 2021 at 11:45:00 AM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=simm-30-4mb.net
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.127
MinViaDiameter=0.508
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1524
TrackWidth2=0.1524
TrackWidth3=0.254
TrackWidth4=0.4
TrackWidth5=0.45
TrackWidth6=0.508
TrackWidth7=0.6
TrackWidth8=0.762
TrackWidth9=0.8
TrackWidth10=1.27
TrackWidth11=1.524
ViaDiameter1=0.508
ViaDrill1=0.2
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.8
ViaDrill3=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.07619999999999999
SolderMaskMinWidth=0.127
SolderPasteClearance=-0.03809999999999999
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=1
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.508
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

View File

@ -0,0 +1,703 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr USLetter 11000 8500
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector_Generic:Conn_01x30 J1
U 1 1 5C2E1E12
P 4450 3450
F 0 "J1" V 4574 3396 50 0000 C CNN
F 1 "DRAM-SIMM-30" V 4665 3396 50 0000 C CNN
F 2 "stdpads:SIMM-30_Edge" H 4450 3450 50 0001 C CNN
F 3 "~" H 4450 3450 50 0001 C CNN
1 4450 3450
0 -1 1 0
$EndComp
$Comp
L power:+5V #PWR0101
U 1 1 5C2E1ED2
P 5950 3250
F 0 "#PWR0101" H 5950 3100 50 0001 C CNN
F 1 "+5V" H 5950 3400 50 0000 C CNN
F 2 "" H 5950 3250 50 0001 C CNN
F 3 "" H 5950 3250 50 0001 C CNN
1 5950 3250
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR0102
U 1 1 5C2E1F89
P 3050 3250
F 0 "#PWR0102" H 3050 3100 50 0001 C CNN
F 1 "+5V" H 3050 3400 50 0000 C CNN
F 2 "" H 3050 3250 50 0001 C CNN
F 3 "" H 3050 3250 50 0001 C CNN
1 3050 3250
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0103
U 1 1 5C2E2010
P 5150 3250
F 0 "#PWR0103" H 5150 3000 50 0001 C CNN
F 1 "GND" H 5150 3100 50 0000 C CNN
F 2 "" H 5150 3250 50 0001 C CNN
F 3 "" H 5150 3250 50 0001 C CNN
1 5150 3250
-1 0 0 1
$EndComp
$Comp
L power:GND #PWR0104
U 1 1 5C2E2033
P 3850 3250
F 0 "#PWR0104" H 3850 3000 50 0001 C CNN
F 1 "GND" H 3850 3100 50 0000 C CNN
F 2 "" H 3850 3250 50 0001 C CNN
F 3 "" H 3850 3250 50 0001 C CNN
1 3850 3250
-1 0 0 1
$EndComp
Text Label 3150 3250 1 50 ~ 0
~CAS~
Text Label 3250 3250 1 50 ~ 0
D0
Text Label 3350 3250 1 50 ~ 0
A0
Text Label 3450 3250 1 50 ~ 0
A1
Text Label 3550 3250 1 50 ~ 0
D1
Text Label 3650 3250 1 50 ~ 0
A2
Text Label 3750 3250 1 50 ~ 0
A3
Text Label 3950 3250 1 50 ~ 0
D2
Text Label 4050 3250 1 50 ~ 0
A4
Text Label 4150 3250 1 50 ~ 0
A5
Text Label 4250 3250 1 50 ~ 0
D3
Text Label 4350 3250 1 50 ~ 0
A6
Text Label 4450 3250 1 50 ~ 0
A7
Text Label 4550 3250 1 50 ~ 0
D4
Text Label 4650 3250 1 50 ~ 0
A8
Text Label 4750 3250 1 50 ~ 0
A9
Text Label 4850 3250 1 50 ~ 0
A10
Text Label 4950 3250 1 50 ~ 0
D5
Text Label 5050 3250 1 50 ~ 0
~WE~
Text Label 5250 3250 1 50 ~ 0
D6
Text Label 5350 3250 1 50 ~ 0
A11
Text Label 5450 3250 1 50 ~ 0
D7
Text Label 5550 3250 1 50 ~ 0
QP
Text Label 5650 3250 1 50 ~ 0
~RAS~
Text Label 5750 3250 1 50 ~ 0
~CASP~
Text Label 5850 3250 1 50 ~ 0
DP
Text Label 2700 7050 0 50 ~ 0
~OE~
Text Label 1900 6950 2 50 ~ 0
1A8
Text Label 1900 6850 2 50 ~ 0
1A7
Text Label 1900 6750 2 50 ~ 0
1A6
Text Label 1900 6650 2 50 ~ 0
1A5
Text Label 1900 6550 2 50 ~ 0
1A4
Text Label 1900 6450 2 50 ~ 0
1A3
Text Label 1900 6350 2 50 ~ 0
1A2
Text Label 1900 6250 2 50 ~ 0
1A1
Text Label 1900 6150 2 50 ~ 0
1A0
Text Label 1900 7150 2 50 ~ 0
1A10
Wire Wire Line
1050 7650 1150 7650
Wire Wire Line
1050 7550 1150 7550
Wire Wire Line
950 7650 1050 7650
$Comp
L Device:C_Small C1
U 1 1 5C2E290A
P 2400 4200
F 0 "C1" H 2492 4246 50 0000 L CNN
F 1 "100n" H 2492 4155 50 0000 L CNN
F 2 "stdpads:C_0805" H 2400 4200 50 0001 C CNN
F 3 "~" H 2400 4200 50 0001 C CNN
1 2400 4200
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C2
U 1 1 5C2E296A
P 2800 4200
F 0 "C2" H 2892 4246 50 0000 L CNN
F 1 "100n" H 2892 4155 50 0000 L CNN
F 2 "stdpads:C_0805" H 2800 4200 50 0001 C CNN
F 3 "~" H 2800 4200 50 0001 C CNN
1 2800 4200
1 0 0 -1
$EndComp
Wire Wire Line
2800 4300 2400 4300
$Comp
L power:+5V #PWR0113
U 1 1 5C2E299D
P 2400 4100
F 0 "#PWR0113" H 2400 3950 50 0001 C CNN
F 1 "+5V" H 2400 4250 50 0000 C CNN
F 2 "" H 2400 4100 50 0001 C CNN
F 3 "" H 2400 4100 50 0001 C CNN
1 2400 4100
1 0 0 -1
$EndComp
Connection ~ 2400 4100
Wire Wire Line
2400 4100 2800 4100
$Comp
L Device:C_Small C3
U 1 1 5C2EDC35
P 3200 4200
F 0 "C3" H 3292 4246 50 0000 L CNN
F 1 "100n" H 3292 4155 50 0000 L CNN
F 2 "stdpads:C_0805" H 3200 4200 50 0001 C CNN
F 3 "~" H 3200 4200 50 0001 C CNN
1 3200 4200
1 0 0 -1
$EndComp
Wire Wire Line
3200 4100 2800 4100
Connection ~ 2800 4100
Wire Wire Line
2800 4300 3200 4300
Connection ~ 2800 4300
Connection ~ 3200 4300
Wire Wire Line
3200 4300 3600 4300
Connection ~ 3600 4300
Wire Wire Line
3600 4100 3200 4100
Connection ~ 3200 4100
$Comp
L Device:C_Small C4
U 1 1 5D1301A9
P 3600 4200
F 0 "C4" H 3692 4246 50 0000 L CNN
F 1 "100n" H 3692 4155 50 0000 L CNN
F 2 "stdpads:C_0805" H 3600 4200 50 0001 C CNN
F 3 "~" H 3600 4200 50 0001 C CNN
1 3600 4200
1 0 0 -1
$EndComp
Text Label 1150 7650 0 50 ~ 0
2A4
Text Label 950 7650 2 50 ~ 0
A10
Text Label 1150 7550 0 50 ~ 0
1A9
$Comp
L GW_RAM:DRAM-4Mx4-SOP-24 U1
U 1 1 5D38F422
P 2300 6650
F 0 "U1" H 2300 7300 50 0000 C CNN
F 1 "4C4M4" H 2300 6000 50 0000 C CNN
F 2 "stdpads:SOJ-24-26-300mil" H 2300 5950 50 0001 C CNN
F 3 "https://www.alliancememory.com/wp-content/uploads/pdf/AS6C8008.pdf" H 2300 6150 50 0001 C CNN
1 2300 6650
1 0 0 -1
$EndComp
Text Label 1900 7050 2 50 ~ 0
1A9
$Comp
L power:GND #PWR0105
U 1 1 5D395DE3
P 2700 7150
F 0 "#PWR0105" H 2700 6900 50 0001 C CNN
F 1 "GND" H 2700 7000 50 0000 C CNN
F 2 "" H 2700 7150 50 0001 C CNN
F 3 "" H 2700 7150 50 0001 C CNN
1 2700 7150
1 0 0 -1
$EndComp
Text Label 2700 6750 0 50 ~ 0
~CAS~
Text Label 2700 6850 0 50 ~ 0
~RAS~
Text Label 2700 6950 0 50 ~ 0
~WE~
Text Label 2700 6250 0 50 ~ 0
D5
Text Label 2700 6550 0 50 ~ 0
D4
Text Label 2700 6350 0 50 ~ 0
D7
Text Label 2700 6450 0 50 ~ 0
D6
$Comp
L power:+5V #PWR0106
U 1 1 5D396692
P 2700 6150
F 0 "#PWR0106" H 2700 6000 50 0001 C CNN
F 1 "+5V" H 2700 6300 50 0000 C CNN
F 2 "" H 2700 6150 50 0001 C CNN
F 3 "" H 2700 6150 50 0001 C CNN
1 2700 6150
1 0 0 -1
$EndComp
Text Label 4300 7100 0 50 ~ 0
~OE~
Text Label 3500 7000 2 50 ~ 0
2A8
Text Label 3500 6900 2 50 ~ 0
2A7
Text Label 3500 6800 2 50 ~ 0
2A6
Text Label 3500 6700 2 50 ~ 0
2A5
Text Label 3500 6600 2 50 ~ 0
2A4
Text Label 3500 6500 2 50 ~ 0
2A3
Text Label 3500 6400 2 50 ~ 0
2A2
Text Label 3500 6300 2 50 ~ 0
2A1
Text Label 3500 6200 2 50 ~ 0
2A0
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2A10
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$Comp
L power:GND #PWR0108
U 1 1 5D3999DD
P 4300 7200
F 0 "#PWR0108" H 4300 6950 50 0001 C CNN
F 1 "GND" H 4300 7050 50 0000 C CNN
F 2 "" H 4300 7200 50 0001 C CNN
F 3 "" H 4300 7200 50 0001 C CNN
1 4300 7200
1 0 0 -1
$EndComp
Text Label 4300 6800 0 50 ~ 0
~CAS~
Text Label 4300 6900 0 50 ~ 0
~RAS~
Text Label 4300 7000 0 50 ~ 0
~WE~
$Comp
L power:+5V #PWR0109
U 1 1 5D3999EA
P 4300 6200
F 0 "#PWR0109" H 4300 6050 50 0001 C CNN
F 1 "+5V" H 4300 6350 50 0000 C CNN
F 2 "" H 4300 6200 50 0001 C CNN
F 3 "" H 4300 6200 50 0001 C CNN
1 4300 6200
1 0 0 -1
$EndComp
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D0
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D3
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$Comp
L power:GND #PWR0110
U 1 1 5D3FC319
P 4000 4300
F 0 "#PWR0110" H 4000 4050 50 0001 C CNN
F 1 "GND" H 4000 4150 50 0000 C CNN
F 2 "" H 4000 4300 50 0001 C CNN
F 3 "" H 4000 4300 50 0001 C CNN
1 4000 4300
1 0 0 -1
$EndComp
Wire Wire Line
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Connection ~ 4000 4300
Wire Wire Line
4000 4100 3600 4100
$Comp
L Device:C_Small C5
U 1 1 5D3FC322
P 4000 4200
F 0 "C5" H 4092 4246 50 0000 L CNN
F 1 "100n" H 4092 4155 50 0000 L CNN
F 2 "stdpads:C_0805" H 4000 4200 50 0001 C CNN
F 3 "~" H 4000 4200 50 0001 C CNN
1 4000 4200
1 0 0 -1
$EndComp
$Comp
L GW_RAM:DRAM-4Mx4-SOP-24 U2
U 1 1 5D3999D6
P 3900 6700
F 0 "U2" H 3900 7350 50 0000 C CNN
F 1 "4C4M4" H 3900 6050 50 0000 C CNN
F 2 "stdpads:SOJ-24-26-300mil" H 3900 6000 50 0001 C CNN
F 3 "https://www.alliancememory.com/wp-content/uploads/pdf/AS6C8008.pdf" H 3900 6200 50 0001 C CNN
1 3900 6700
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R2
U 1 1 60C54176
P 9100 5900
F 0 "R2" H 9159 5946 50 0000 L CNN
F 1 "FPM" H 9159 5855 50 0000 L CNN
F 2 "stdpads:R_0805" H 9100 5900 50 0001 C CNN
F 3 "~" H 9100 5900 50 0001 C CNN
1 9100 5900
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R1
U 1 1 60C5420A
P 9100 5700
F 0 "R1" H 9159 5746 50 0000 L CNN
F 1 "EDO" H 9159 5655 50 0000 L CNN
F 2 "stdpads:R_0805" H 9100 5700 50 0001 C CNN
F 3 "~" H 9100 5700 50 0001 C CNN
1 9100 5700
1 0 0 -1
$EndComp
Text Label 8900 5800 0 50 ~ 0
~OE~
Wire Wire Line
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Connection ~ 9100 5800
Text Label 8900 5600 0 50 ~ 0
~CAS~
Wire Wire Line
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$Comp
L power:GND #PWR0115
U 1 1 60C57F90
P 9100 6000
F 0 "#PWR0115" H 9100 5750 50 0001 C CNN
F 1 "GND" H 9100 5850 50 0000 C CNN
F 2 "" H 9100 6000 50 0001 C CNN
F 3 "" H 9100 6000 50 0001 C CNN
1 9100 6000
1 0 0 -1
$EndComp
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$Comp
L power:GND #PWR0107
U 1 1 60C25D3B
P 5900 7200
F 0 "#PWR0107" H 5900 6950 50 0001 C CNN
F 1 "GND" H 5900 7050 50 0000 C CNN
F 2 "" H 5900 7200 50 0001 C CNN
F 3 "" H 5900 7200 50 0001 C CNN
1 5900 7200
1 0 0 -1
$EndComp
Text Label 5900 6900 0 50 ~ 0
~RAS~
Text Label 5900 7000 0 50 ~ 0
~WE~
$Comp
L power:+5V #PWR0111
U 1 1 60C25D44
P 5900 6200
F 0 "#PWR0111" H 5900 6050 50 0001 C CNN
F 1 "+5V" H 5900 6350 50 0000 C CNN
F 2 "" H 5900 6200 50 0001 C CNN
F 3 "" H 5900 6200 50 0001 C CNN
1 5900 6200
1 0 0 -1
$EndComp
$Comp
L GW_RAM:DRAM-4Mx1-SOP-20 U3
U 1 1 60C25D4E
P 5500 6700
F 0 "U3" H 5500 7350 50 0000 C CNN
F 1 "4C4M1" H 5500 6050 50 0000 C CNN
F 2 "stdpads:SOJ-20-26-300mil" H 5500 6000 50 0001 C CNN
F 3 "https://www.alliancememory.com/wp-content/uploads/pdf/AS6C8008.pdf" H 5500 6200 50 0001 C CNN
1 5500 6700
1 0 0 -1
$EndComp
Text Label 5900 6800 0 50 ~ 0
~CASP~
Text Label 5900 6400 0 50 ~ 0
QP
Text Label 5900 6300 0 50 ~ 0
DP
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1A10
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1A8
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Wire Wire Line
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Connection ~ 1050 5850
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$EndSCHEMATC

View File

@ -0,0 +1,4 @@
(sym_lib_table
(lib (name GW_RAM)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_RAM.lib")(options "")(descr ""))
(lib (name GW_Logic)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_Logic.lib")(options "")(descr ""))
)

View File

@ -0,0 +1,3 @@
(fp_lib_table
(lib (name stdpads)(type KiCad)(uri "$(KIPRJMOD)/../../stdpads.pretty")(options "")(descr ""))
)

View File

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View File

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View File

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(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.15))
(fp_text user %R (at 0 0 270) (layer F.SilkS) hide
(effects (font (size 0.254 0.254) (thickness 0.0635)))
)
@ -709,16 +709,16 @@
(fp_text value 100n (at 0 0.35 90) (layer F.Fab)
(effects (font (size 0.254 0.254) (thickness 0.0635)))
)
(fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 270) (layer F.SilkS) hide
(effects (font (size 0.254 0.254) (thickness 0.0635)))
)
@ -746,16 +746,16 @@
(fp_text value 100n (at 0 0.35 90) (layer F.Fab)
(effects (font (size 0.254 0.254) (thickness 0.0635)))
)
(fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 270) (layer F.SilkS) hide
(effects (font (size 0.254 0.254) (thickness 0.0635)))
)
@ -783,16 +783,16 @@
(fp_text value 100n (at 0 0.35 90) (layer F.Fab)
(effects (font (size 0.254 0.254) (thickness 0.0635)))
)
(fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.15))
(fp_text user %R (at 0 0 270) (layer F.SilkS) hide
(effects (font (size 0.254 0.254) (thickness 0.0635)))
)
@ -820,16 +820,16 @@
(fp_text value 100n (at 0 0.35 90) (layer F.Fab)
(effects (font (size 0.254 0.254) (thickness 0.0635)))
)
(fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 270) (layer F.SilkS) hide
(effects (font (size 0.254 0.254) (thickness 0.0635)))
)
@ -857,16 +857,16 @@
(fp_text value EDO (at 0 0.35) (layer F.Fab)
(effects (font (size 0.254 0.254) (thickness 0.0635)))
)
(fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.1))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.1))
(fp_text user %R (at 0 0 180) (layer F.SilkS) hide
(effects (font (size 0.254 0.254) (thickness 0.0635)))
)
@ -894,16 +894,16 @@
(fp_text value FPM (at 0 0.35) (layer F.Fab)
(effects (font (size 0.254 0.254) (thickness 0.0635)))
)
(fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.1))
(fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524))
(fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.SilkS) hide
(effects (font (size 0.254 0.254) (thickness 0.0635)))
)
@ -941,7 +941,7 @@
(gr_text "Garretts Workshop" (at 129.794 93.98) (layer B.SilkS) (tstamp 60BD7F50)
(effects (font (size 1.524 1.524) (thickness 0.225)) (justify mirror))
)
(gr_text 4191A (at 127.889 96.774) (layer B.SilkS) (tstamp 60BD85F9)
(gr_text 4192A (at 127.889 96.774) (layer B.SilkS) (tstamp 60BD85F9)
(effects (font (size 1.5 1.5) (thickness 0.3)) (justify mirror))
)
(gr_text GW (at 133.477 96.774) (layer B.SilkS) (tstamp 60BD7F4D)

View File

@ -0,0 +1,3 @@
(fp_lib_table
(lib (name stdpads)(type KiCad)(uri "$(KIPRJMOD)/../../stdpads.pretty")(options "")(descr ""))
)

View File

@ -0,0 +1,286 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 74xGxx_74AHCT1G04
#
DEF 74xGxx_74AHCT1G04 U 0 40 Y Y 1 F N
F0 "U" -100 150 50 H V C CNN
F1 "74xGxx_74AHCT1G04" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74LVC1GU04 74AHC1G04 74AHCT1G04 74AUC1G04 74AUP1G04 74AHC1GU04 74AHCT1GU04 74AUC1GU04 74AUP1GU04
$FPLIST
SOT*
SG-*
$ENDFPLIST
DRAW
P 4 0 1 10 -150 100 -150 -100 100 0 -150 100 N
X ~ 2 -300 0 150 R 40 40 1 1 I
X GND 3 0 -100 0 D 40 40 1 1 W N
X ~ 4 250 0 150 L 40 40 1 1 O I
X VCC 5 0 100 0 U 40 40 1 1 W N
ENDDRAW
ENDDEF
#
# 74xGxx_74AHCT1G32
#
DEF 74xGxx_74AHCT1G32 U 0 40 Y Y 1 F N
F0 "U" -100 150 50 H V C CNN
F1 "74xGxx_74AHCT1G32" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74AHC1G32 74AHCT1G32 74AUC1G32 74AUP1G32
$FPLIST
SOT*
SG-*
$ENDFPLIST
DRAW
A -275 0 160 386 -386 0 1 10 N -150 100 -150 -100
A -38 -37 142 744 150 0 1 10 N 0 100 100 0
A -38 37 142 -744 -150 0 1 10 N 0 -100 100 0
P 2 0 1 0 -150 -50 -125 -50 N
P 2 0 1 0 -150 50 -125 50 N
P 2 0 1 10 0 -100 -150 -100 f
P 2 0 1 10 0 100 -150 100 f
X ~ 1 -300 50 150 R 40 40 1 1 I
X ~ 2 -300 -50 150 R 40 40 1 1 I
X GND 3 0 -100 0 D 40 40 1 1 W N
X ~ 4 250 0 150 L 40 40 1 1 O
X VCC 5 0 100 0 U 40 40 1 1 W N
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x30
#
DEF Connector_Generic_Conn_01x30 J 0 40 Y N 1 F N
F0 "J" 0 1500 50 H V C CNN
F1 "Connector_Generic_Conn_01x30" 0 -1600 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -1495 0 -1505 1 1 6 N
S -50 -1395 0 -1405 1 1 6 N
S -50 -1295 0 -1305 1 1 6 N
S -50 -1195 0 -1205 1 1 6 N
S -50 -1095 0 -1105 1 1 6 N
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 905 0 895 1 1 6 N
S -50 1005 0 995 1 1 6 N
S -50 1105 0 1095 1 1 6 N
S -50 1205 0 1195 1 1 6 N
S -50 1305 0 1295 1 1 6 N
S -50 1405 0 1395 1 1 6 N
S -50 1450 50 -1550 1 1 10 f
X Pin_1 1 -200 1400 150 R 50 50 1 1 P
X Pin_10 10 -200 500 150 R 50 50 1 1 P
X Pin_11 11 -200 400 150 R 50 50 1 1 P
X Pin_12 12 -200 300 150 R 50 50 1 1 P
X Pin_13 13 -200 200 150 R 50 50 1 1 P
X Pin_14 14 -200 100 150 R 50 50 1 1 P
X Pin_15 15 -200 0 150 R 50 50 1 1 P
X Pin_16 16 -200 -100 150 R 50 50 1 1 P
X Pin_17 17 -200 -200 150 R 50 50 1 1 P
X Pin_18 18 -200 -300 150 R 50 50 1 1 P
X Pin_19 19 -200 -400 150 R 50 50 1 1 P
X Pin_2 2 -200 1300 150 R 50 50 1 1 P
X Pin_20 20 -200 -500 150 R 50 50 1 1 P
X Pin_21 21 -200 -600 150 R 50 50 1 1 P
X Pin_22 22 -200 -700 150 R 50 50 1 1 P
X Pin_23 23 -200 -800 150 R 50 50 1 1 P
X Pin_24 24 -200 -900 150 R 50 50 1 1 P
X Pin_25 25 -200 -1000 150 R 50 50 1 1 P
X Pin_26 26 -200 -1100 150 R 50 50 1 1 P
X Pin_27 27 -200 -1200 150 R 50 50 1 1 P
X Pin_28 28 -200 -1300 150 R 50 50 1 1 P
X Pin_29 29 -200 -1400 150 R 50 50 1 1 P
X Pin_3 3 -200 1200 150 R 50 50 1 1 P
X Pin_30 30 -200 -1500 150 R 50 50 1 1 P
X Pin_4 4 -200 1100 150 R 50 50 1 1 P
X Pin_5 5 -200 1000 150 R 50 50 1 1 P
X Pin_6 6 -200 900 150 R 50 50 1 1 P
X Pin_7 7 -200 800 150 R 50 50 1 1 P
X Pin_8 8 -200 700 150 R 50 50 1 1 P
X Pin_9 9 -200 600 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Small
#
DEF Device_R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "Device_R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -30 70 30 -70 0 1 8 N
X ~ 1 0 100 30 D 50 50 1 1 P
X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GW_Logic_741G74DC
#
DEF GW_Logic_741G74DC U 0 40 Y Y 1 F N
F0 "U" 0 300 50 H V C CNN
F1 "GW_Logic_741G74DC" 0 -300 50 H V C CNN
F2 "stdpads:SOT-353" 0 -350 50 H I C TNN
F3 "" 0 -200 60 H I C CNN
DRAW
S 200 -250 -200 250 0 1 10 f
X CK 1 -400 -150 200 R 50 50 1 1 I
X D 2 -400 150 200 R 50 50 1 1 I
X ~Q~ 3 400 -50 200 L 50 50 1 1 O
X GND 4 400 -150 200 L 50 50 1 1 W
X Q 5 400 50 200 L 50 50 1 1 O
X ~R~ 6 -400 -50 200 R 50 50 1 1 I
X ~S~ 7 -400 50 200 R 50 50 1 1 I
X Vcc 8 400 150 200 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_RAM_DRAM-4Mx4-SOP-24
#
DEF GW_RAM_DRAM-4Mx4-SOP-24 U 0 20 Y Y 1 F N
F0 "U" 0 650 50 H V C CNN
F1 "GW_RAM_DRAM-4Mx4-SOP-24" 0 0 50 V V C CNN
F2 "stdpads:SOP-24-26-300mil" 0 -650 50 H I C CNN
F3 "" 0 -600 50 H I C CNN
$FPLIST
SOJ*10.16x23.49mm*P1.27mm*
$ENDFPLIST
DRAW
S -300 600 300 -600 0 1 10 f
X VDD 1 400 500 100 L 50 50 1 1 W
X A1 10 -400 400 100 R 50 50 1 1 I
X A2 11 -400 300 100 R 50 50 1 1 I
X A3 12 -400 200 100 R 50 50 1 1 I
X VDD 13 400 500 100 L 50 50 1 1 W N
X GND 14 400 -500 100 L 50 50 1 1 W N
X A4 15 -400 100 100 R 50 50 1 1 I
X A5 16 -400 0 100 R 50 50 1 1 I
X A6 17 -400 -100 100 R 50 50 1 1 I
X A7 18 -400 -200 100 R 50 50 1 1 I
X A8 19 -400 -300 100 R 50 50 1 1 I
X D0 2 400 400 100 L 50 50 1 1 B
X NC 20 400 0 100 L 50 50 1 1 N N
X A9 21 -400 -400 100 R 50 50 1 1 I
X ~OE~ 22 400 -400 100 L 50 50 1 1 I
X ~CAS~ 23 400 -100 100 L 50 50 1 1 I
X D2 24 400 200 100 L 50 50 1 1 B
X D3 25 400 100 100 L 50 50 1 1 B
X GND 26 400 -500 100 L 50 50 1 1 W
X D1 3 400 300 100 L 50 50 1 1 B
X ~WE~ 4 400 -300 100 L 50 50 1 1 I
X ~RAS~ 5 400 -200 100 L 50 50 1 1 I
X NC 7 400 0 100 L 50 50 1 1 N N
X A10 8 -400 -500 100 R 50 50 1 1 I
X A0 9 -400 500 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# Regulator_Linear_XC6206PxxxMR
#
DEF Regulator_Linear_XC6206PxxxMR U 0 10 Y Y 1 F N
F0 "U" -150 125 50 H V C CNN
F1 "Regulator_Linear_XC6206PxxxMR" 0 125 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23" 0 225 50 H I C CIN
F3 "" 0 0 50 H I C CNN
ALIAS APE8865N-15-HF-3 APE8865N-16-HF-3 APE8865N-17-HF-3 APE8865N-18-HF-3 APE8865N-19-HF-3 APE8865N-20-HF-3 APE8865N-21-HF-3 APE8865N-22-HF-3 APE8865N-23-HF-3 APE8865N-24-HF-3 APE8865N-25-HF-3 APE8865N-26-HF-3 APE8865N-27-HF-3 APE8865N-28-HF-3 APE8865N-29-HF-3 APE8865N-30-HF-3 APE8865N-31-HF-3 APE8865N-32-HF-3 APE8865N-33-HF-3 AP2127N-1.0 AP2127N-1.2 AP2127N-1.5 AP2127N-1.8 AP2127N-2.5 AP2127N-2.8 AP2127N-3.0 AP2127N-3.3 XC6206PxxxMR
$FPLIST
SOT?23*
$ENDFPLIST
DRAW
S -200 75 200 -200 0 1 10 f
X GND 1 0 -300 100 U 50 50 1 1 W
X VO 2 300 0 100 L 50 50 1 1 w
X VI 3 -300 0 100 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# power_+3V3
#
DEF power_+3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,262 @@
update=Wednesday, June 09, 2021 at 11:45:00 AM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=simm-30-4mb.net
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.127
MinViaDiameter=0.508
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1524
TrackWidth2=0.1524
TrackWidth3=0.254
TrackWidth4=0.4
TrackWidth5=0.45
TrackWidth6=0.508
TrackWidth7=0.6
TrackWidth8=0.762
TrackWidth9=0.8
TrackWidth10=1.27
TrackWidth11=1.524
ViaDiameter1=0.508
ViaDrill1=0.2
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.8
ViaDrill3=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.07619999999999999
SolderMaskMinWidth=0.127
SolderPasteClearance=-0.03809999999999999
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=1
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.508
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

View File

@ -0,0 +1,908 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr USLetter 11000 8500
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector_Generic:Conn_01x30 J1
U 1 1 5C2E1E12
P 4450 3450
F 0 "J1" V 4574 3396 50 0000 C CNN
F 1 "DRAM-SIMM-30" V 4665 3396 50 0000 C CNN
F 2 "stdpads:SIMM-30_Edge" H 4450 3450 50 0001 C CNN
F 3 "~" H 4450 3450 50 0001 C CNN
1 4450 3450
0 -1 1 0
$EndComp
$Comp
L power:+5V #PWR0101
U 1 1 5C2E1ED2
P 5950 3250
F 0 "#PWR0101" H 5950 3100 50 0001 C CNN
F 1 "+5V" H 5950 3400 50 0000 C CNN
F 2 "" H 5950 3250 50 0001 C CNN
F 3 "" H 5950 3250 50 0001 C CNN
1 5950 3250
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR0102
U 1 1 5C2E1F89
P 3050 3250
F 0 "#PWR0102" H 3050 3100 50 0001 C CNN
F 1 "+5V" H 3050 3400 50 0000 C CNN
F 2 "" H 3050 3250 50 0001 C CNN
F 3 "" H 3050 3250 50 0001 C CNN
1 3050 3250
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0103
U 1 1 5C2E2010
P 5150 3250
F 0 "#PWR0103" H 5150 3000 50 0001 C CNN
F 1 "GND" H 5150 3100 50 0000 C CNN
F 2 "" H 5150 3250 50 0001 C CNN
F 3 "" H 5150 3250 50 0001 C CNN
1 5150 3250
-1 0 0 1
$EndComp
$Comp
L power:GND #PWR0104
U 1 1 5C2E2033
P 3850 3250
F 0 "#PWR0104" H 3850 3000 50 0001 C CNN
F 1 "GND" H 3850 3100 50 0000 C CNN
F 2 "" H 3850 3250 50 0001 C CNN
F 3 "" H 3850 3250 50 0001 C CNN
1 3850 3250
-1 0 0 1
$EndComp
Text Label 3150 3250 1 50 ~ 0
~CAS~
Text Label 3250 3250 1 50 ~ 0
D0
Text Label 3350 3250 1 50 ~ 0
A0
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A1
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D1
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D6
Text Label 5350 3250 1 50 ~ 0
A11
Text Label 5450 3250 1 50 ~ 0
D7
Text Label 5550 3250 1 50 ~ 0
QP
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~RAS~
Text Label 5750 3250 1 50 ~ 0
~CASP~
Text Label 5850 3250 1 50 ~ 0
DP
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1A1
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1A0
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1A10
Wire Wire Line
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Wire Wire Line
1850 7400 1850 7450
Connection ~ 1850 7400
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
1850 5550 1950 5550
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Connection ~ 1850 5800
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 1850 6000
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Wire Wire Line
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Wire Wire Line
1750 6000 1850 6000
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Wire Wire Line
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$Comp
L Device:C_Small C1
U 1 1 5C2E290A
P 2400 4200
F 0 "C1" H 2492 4246 50 0000 L CNN
F 1 "100n" H 2492 4155 50 0000 L CNN
F 2 "stdpads:C_0805" H 2400 4200 50 0001 C CNN
F 3 "~" H 2400 4200 50 0001 C CNN
1 2400 4200
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C2
U 1 1 5C2E296A
P 2800 4200
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F 1 "100n" H 2892 4155 50 0000 L CNN
F 2 "stdpads:C_0805" H 2800 4200 50 0001 C CNN
F 3 "~" H 2800 4200 50 0001 C CNN
1 2800 4200
1 0 0 -1
$EndComp
Wire Wire Line
2800 4300 2400 4300
$Comp
L power:+5V #PWR0113
U 1 1 5C2E299D
P 2400 4100
F 0 "#PWR0113" H 2400 3950 50 0001 C CNN
F 1 "+5V" H 2400 4250 50 0000 C CNN
F 2 "" H 2400 4100 50 0001 C CNN
F 3 "" H 2400 4100 50 0001 C CNN
1 2400 4100
1 0 0 -1
$EndComp
Connection ~ 2400 4100
Wire Wire Line
2400 4100 2800 4100
$Comp
L Device:C_Small C3
U 1 1 5C2EDC35
P 3200 4200
F 0 "C3" H 3292 4246 50 0000 L CNN
F 1 "100n" H 3292 4155 50 0000 L CNN
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F 3 "~" H 3200 4200 50 0001 C CNN
1 3200 4200
1 0 0 -1
$EndComp
Wire Wire Line
3200 4100 2800 4100
Connection ~ 2800 4100
Wire Wire Line
2800 4300 3200 4300
Connection ~ 2800 4300
Connection ~ 3200 4300
Wire Wire Line
3200 4300 3600 4300
Connection ~ 3600 4300
Wire Wire Line
3600 4100 3200 4100
Connection ~ 3200 4100
$Comp
L Device:C_Small C4
U 1 1 5D1301A9
P 3600 4200
F 0 "C4" H 3692 4246 50 0000 L CNN
F 1 "100n" H 3692 4155 50 0000 L CNN
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F 3 "~" H 3600 4200 50 0001 C CNN
1 3600 4200
1 0 0 -1
$EndComp
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1A9
$Comp
L GW_RAM:DRAM-4Mx4-SOP-24 U1
U 1 1 5D38F422
P 3800 6650
F 0 "U1" H 3800 7300 50 0000 C CNN
F 1 "AS4C4M4" H 3800 6000 50 0000 C CNN
F 2 "stdpads:SOJ-24-26-300mil" H 3800 5950 50 0001 C CNN
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1 3800 6650
1 0 0 -1
$EndComp
Text Label 3400 7050 2 50 ~ 0
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$Comp
L power:GND #PWR0105
U 1 1 5D395DE3
P 4200 7150
F 0 "#PWR0105" H 4200 6900 50 0001 C CNN
F 1 "GND" H 4200 7000 50 0000 C CNN
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F 3 "" H 4200 7150 50 0001 C CNN
1 4200 7150
1 0 0 -1
$EndComp
Text Label 4200 6750 0 50 ~ 0
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D5
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D4
Text Label 4200 6350 0 50 ~ 0
D7
Text Label 4200 6450 0 50 ~ 0
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$Comp
L power:+5V #PWR0106
U 1 1 5D396692
P 4200 6150
F 0 "#PWR0106" H 4200 6000 50 0001 C CNN
F 1 "+5V" H 4200 6300 50 0000 C CNN
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F 3 "" H 4200 6150 50 0001 C CNN
1 4200 6150
1 0 0 -1
$EndComp
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~OE~
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2A8
Text Label 5000 6900 2 50 ~ 0
2A7
Text Label 5000 6800 2 50 ~ 0
2A6
Text Label 5000 6700 2 50 ~ 0
2A5
Text Label 5000 6600 2 50 ~ 0
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Text Label 5000 6300 2 50 ~ 0
2A1
Text Label 5000 6200 2 50 ~ 0
2A0
Text Label 5000 7200 2 50 ~ 0
2A10
Text Label 5000 7100 2 50 ~ 0
2A9
$Comp
L power:GND #PWR0108
U 1 1 5D3999DD
P 5800 7200
F 0 "#PWR0108" H 5800 6950 50 0001 C CNN
F 1 "GND" H 5800 7050 50 0000 C CNN
F 2 "" H 5800 7200 50 0001 C CNN
F 3 "" H 5800 7200 50 0001 C CNN
1 5800 7200
1 0 0 -1
$EndComp
Text Label 5800 6800 0 50 ~ 0
~CAS~
Text Label 5800 6900 0 50 ~ 0
~RAS~
Text Label 5800 7000 0 50 ~ 0
~RWE~
$Comp
L power:+5V #PWR0109
U 1 1 5D3999EA
P 5800 6200
F 0 "#PWR0109" H 5800 6050 50 0001 C CNN
F 1 "+5V" H 5800 6350 50 0000 C CNN
F 2 "" H 5800 6200 50 0001 C CNN
F 3 "" H 5800 6200 50 0001 C CNN
1 5800 6200
1 0 0 -1
$EndComp
Text Label 5800 6600 0 50 ~ 0
D0
Text Label 5800 6500 0 50 ~ 0
D2
Text Label 5800 6400 0 50 ~ 0
D3
Text Label 5800 6300 0 50 ~ 0
D1
$Comp
L power:GND #PWR0110
U 1 1 5D3FC319
P 4000 4300
F 0 "#PWR0110" H 4000 4050 50 0001 C CNN
F 1 "GND" H 4000 4150 50 0000 C CNN
F 2 "" H 4000 4300 50 0001 C CNN
F 3 "" H 4000 4300 50 0001 C CNN
1 4000 4300
1 0 0 -1
$EndComp
Wire Wire Line
3600 4300 4000 4300
Connection ~ 4000 4300
Wire Wire Line
4000 4100 3600 4100
$Comp
L Device:C_Small C5
U 1 1 5D3FC322
P 4000 4200
F 0 "C5" H 4092 4246 50 0000 L CNN
F 1 "100n" H 4092 4155 50 0000 L CNN
F 2 "stdpads:C_0805" H 4000 4200 50 0001 C CNN
F 3 "~" H 4000 4200 50 0001 C CNN
1 4000 4200
1 0 0 -1
$EndComp
$Comp
L GW_RAM:DRAM-4Mx4-SOP-24 U2
U 1 1 5D3999D6
P 5400 6700
F 0 "U2" H 5400 7350 50 0000 C CNN
F 1 "AS4C4M4" H 5400 6050 50 0000 C CNN
F 2 "stdpads:SOJ-24-26-300mil" H 5400 6000 50 0001 C CNN
F 3 "https://www.alliancememory.com/wp-content/uploads/pdf/AS6C8008.pdf" H 5400 6200 50 0001 C CNN
1 5400 6700
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0107
U 1 1 60C23F6F
P 7550 5200
F 0 "#PWR0107" H 7550 4950 50 0001 C CNN
F 1 "GND" H 7550 5050 50 0000 C CNN
F 2 "" H 7550 5200 50 0001 C CNN
F 3 "" H 7550 5200 50 0001 C CNN
1 7550 5200
1 0 0 -1
$EndComp
NoConn ~ 7550 5000
Text Label 7650 5000 0 50 ~ 0
~WE~
Text Label 7750 5100 2 50 ~ 0
~WEE~
Wire Wire Line
7650 5000 7750 5000
Text Label 8700 5050 2 50 ~ 0
~RWE~
Wire Wire Line
8700 5050 8500 5050
$Comp
L Device:R_Small R2
U 1 1 60C54176
P 7150 3550
F 0 "R2" H 7209 3596 50 0000 L CNN
F 1 "FPM" H 7209 3505 50 0000 L CNN
F 2 "stdpads:R_0805" H 7150 3550 50 0001 C CNN
F 3 "~" H 7150 3550 50 0001 C CNN
1 7150 3550
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R1
U 1 1 60C5420A
P 7150 3350
F 0 "R1" H 7209 3396 50 0000 L CNN
F 1 "EDO" H 7209 3305 50 0000 L CNN
F 2 "stdpads:R_0805" H 7150 3350 50 0001 C CNN
F 3 "~" H 7150 3350 50 0001 C CNN
1 7150 3350
1 0 0 -1
$EndComp
Text Label 6950 3450 0 50 ~ 0
~OE~
Wire Wire Line
7150 3450 6950 3450
Connection ~ 7150 3450
Text Label 6950 3250 0 50 ~ 0
~CAS~
Wire Wire Line
6950 3250 7150 3250
$Comp
L power:GND #PWR0115
U 1 1 60C57F90
P 7150 3650
F 0 "#PWR0115" H 7150 3400 50 0001 C CNN
F 1 "GND" H 7150 3500 50 0000 C CNN
F 2 "" H 7150 3650 50 0001 C CNN
F 3 "" H 7150 3650 50 0001 C CNN
1 7150 3650
1 0 0 -1
$EndComp
$Comp
L 74xGxx:74AHCT1G32 U5
U 1 1 60C701C1
P 8050 5050
F 0 "U5" H 8050 5050 50 0000 C CNN
F 1 "74LVC1G32" H 8150 4950 50 0000 L CNN
F 2 "stdpads:SOT-353" H 8050 5050 50 0001 C CNN
F 3 "http://www.ti.com/lit/sg/scyt129e/scyt129e.pdf" H 8050 5050 50 0001 C CNN
1 8050 5050
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0118
U 1 1 60C72B3C
P 8050 5150
F 0 "#PWR0118" H 8050 4900 50 0001 C CNN
F 1 "GND" H 8050 5000 50 0000 C CNN
F 2 "" H 8050 5150 50 0001 C CNN
F 3 "" H 8050 5150 50 0001 C CNN
1 8050 5150
1 0 0 -1
$EndComp
$Comp
L Regulator_Linear:XC6206PxxxMR U6
U 1 1 60C9B194
P 3250 4950
F 0 "U6" H 3250 5192 50 0000 C CNN
F 1 "XC6206PxxxMR" H 3250 5101 50 0000 C CNN
F 2 "stdpads:SOT-23" H 3250 5175 50 0001 C CIN
F 3 "https://www.torexsemi.com/file/xc6206/XC6206.pdf" H 3250 4950 50 0001 C CNN
1 3250 4950
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0119
U 1 1 60C9CD9C
P 3250 5250
F 0 "#PWR0119" H 3250 5000 50 0001 C CNN
F 1 "GND" H 3250 5100 50 0000 C CNN
F 2 "" H 3250 5250 50 0001 C CNN
F 3 "" H 3250 5250 50 0001 C CNN
1 3250 5250
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C6
U 1 1 60CA3460
P 2400 3800
F 0 "C6" H 2492 3846 50 0000 L CNN
F 1 "100n" H 2492 3755 50 0000 L CNN
F 2 "stdpads:C_0805" H 2400 3800 50 0001 C CNN
F 3 "~" H 2400 3800 50 0001 C CNN
1 2400 3800
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C7
U 1 1 60CA3466
P 2800 3800
F 0 "C7" H 2892 3846 50 0000 L CNN
F 1 "100n" H 2892 3755 50 0000 L CNN
F 2 "stdpads:C_0805" H 2800 3800 50 0001 C CNN
F 3 "~" H 2800 3800 50 0001 C CNN
1 2800 3800
1 0 0 -1
$EndComp
Wire Wire Line
2800 3900 2400 3900
Wire Wire Line
2400 3700 2800 3700
$Comp
L power:+3V3 #PWR0121
U 1 1 60CA59B0
P 2400 3700
F 0 "#PWR0121" H 2400 3550 50 0001 C CNN
F 1 "+3V3" H 2400 3850 50 0000 C CNN
F 2 "" H 2400 3700 50 0001 C CNN
F 3 "" H 2400 3700 50 0001 C CNN
1 2400 3700
1 0 0 -1
$EndComp
Connection ~ 2400 3700
$Comp
L power:+5V #PWR0122
U 1 1 60CA60DC
P 2850 4950
F 0 "#PWR0122" H 2850 4800 50 0001 C CNN
F 1 "+5V" H 2850 5100 50 0000 C CNN
F 2 "" H 2850 4950 50 0001 C CNN
F 3 "" H 2850 4950 50 0001 C CNN
1 2850 4950
1 0 0 -1
$EndComp
Wire Wire Line
2950 4950 2850 4950
$Comp
L power:+3V3 #PWR0123
U 1 1 60CA88AF
P 3650 4950
F 0 "#PWR0123" H 3650 4800 50 0001 C CNN
F 1 "+3V3" H 3650 5100 50 0000 C CNN
F 2 "" H 3650 4950 50 0001 C CNN
F 3 "" H 3650 4950 50 0001 C CNN
1 3650 4950
1 0 0 -1
$EndComp
Wire Wire Line
3550 4950 3650 4950
$Comp
L GW_Logic:741G74DC U4
U 1 1 60C11C86
P 7150 5050
F 0 "U4" H 7150 5050 50 0000 C CNN
F 1 "74LVC1G74DC" H 7150 4750 50 0000 C CNN
F 2 "stdpads:NXP_TSSOP-8_3x3mm_P0.65mm" H 7150 4700 50 0001 C TNN
F 3 "" H 7150 4850 60 0001 C CNN
1 7150 5050
1 0 0 -1
$EndComp
$Comp
L power:+3V3 #PWR0114
U 1 1 60CD2DD4
P 7550 4900
F 0 "#PWR0114" H 7550 4750 50 0001 C CNN
F 1 "+3V3" H 7550 5050 50 0000 C CNN
F 2 "" H 7550 4900 50 0001 C CNN
F 3 "" H 7550 4900 50 0001 C CNN
1 7550 4900
1 0 0 -1
$EndComp
$Comp
L power:+3V3 #PWR0117
U 1 1 60CD3487
P 8050 4950
F 0 "#PWR0117" H 8050 4800 50 0001 C CNN
F 1 "+3V3" H 8050 5100 50 0000 C CNN
F 2 "" H 8050 4950 50 0001 C CNN
F 3 "" H 8050 4950 50 0001 C CNN
1 8050 4950
1 0 0 -1
$EndComp
Connection ~ 2800 3900
Wire Wire Line
6650 5000 6750 5000
Text Label 5450 5200 0 50 ~ 0
~RAS~
$Comp
L Device:C_Small C9
U 1 1 60D6A09F
P 6550 5300
F 0 "C9" H 6642 5346 50 0000 L CNN
F 1 "18p" H 6642 5255 50 0000 L CNN
F 2 "stdpads:C_0805" H 6550 5300 50 0001 C CNN
F 3 "~" H 6550 5300 50 0001 C CNN
1 6550 5300
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R3
U 1 1 60D6B055
P 6400 5200
F 0 "R3" V 6250 5200 50 0000 C CNN
F 1 "180" V 6350 5200 50 0000 C BNN
F 2 "stdpads:R_0805" H 6400 5200 50 0001 C CNN
F 3 "~" H 6400 5200 50 0001 C CNN
1 6400 5200
0 1 1 0
$EndComp
Wire Wire Line
6500 5200 6550 5200
Wire Wire Line
6750 5100 6550 5100
Wire Wire Line
6550 5100 6550 5000
Text Label 5450 4900 0 50 ~ 0
~CAS~
Wire Wire Line
5450 4900 6750 4900
Connection ~ 6550 5200
Wire Wire Line
6550 5200 6750 5200
Wire Wire Line
6300 5200 6250 5200
Wire Wire Line
6250 5200 6250 5000
Wire Wire Line
6250 5000 6550 5000
$Comp
L 74xGxx:74AHCT1G04 U3
U 1 1 60D961A7
P 5950 5200
F 0 "U3" H 5900 5200 50 0000 C CNN
F 1 "74LVC1G04" H 6000 5100 50 0000 L CNN
F 2 "stdpads:SOT-353" H 5950 5200 50 0001 C CNN
F 3 "http://www.ti.com/lit/sg/scyt129e/scyt129e.pdf" H 5950 5200 50 0001 C CNN
1 5950 5200
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0112
U 1 1 60D97767
P 5950 5400
F 0 "#PWR0112" H 5950 5150 50 0001 C CNN
F 1 "GND" H 5950 5250 50 0000 C CNN
F 2 "" H 5950 5400 50 0001 C CNN
F 3 "" H 5950 5400 50 0001 C CNN
1 5950 5400
1 0 0 -1
$EndComp
Wire Wire Line
5450 5200 5650 5200
Wire Wire Line
6200 5200 6250 5200
Connection ~ 6250 5200
Wire Wire Line
7550 5100 7750 5100
Wire Wire Line
5950 5300 5950 5400
Wire Wire Line
5950 5400 6550 5400
Connection ~ 5950 5400
Wire Wire Line
6650 4850 6650 5000
$Comp
L power:+3V3 #PWR0111
U 1 1 60CEEECB
P 6650 4850
F 0 "#PWR0111" H 6650 4700 50 0001 C CNN
F 1 "+3V3" H 6650 5000 50 0000 C CNN
F 2 "" H 6650 4850 50 0001 C CNN
F 3 "" H 6650 4850 50 0001 C CNN
1 6650 4850
1 0 0 -1
$EndComp
$Comp
L power:+3V3 #PWR0116
U 1 1 60D97B61
P 5950 5100
F 0 "#PWR0116" H 5950 4950 50 0001 C CNN
F 1 "+3V3" H 5950 5250 50 0000 C CNN
F 2 "" H 5950 5100 50 0001 C CNN
F 3 "" H 5950 5100 50 0001 C CNN
1 5950 5100
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R4
U 1 1 60E11E8F
P 8400 5050
F 0 "R4" V 8250 5050 50 0000 C CNN
F 1 "33" V 8350 5050 50 0000 C BNN
F 2 "stdpads:R_0805" H 8400 5050 50 0001 C CNN
F 3 "~" H 8400 5050 50 0001 C CNN
1 8400 5050
0 1 1 0
$EndComp
Text Notes 6350 5500 0 50 ~ 0
1-5ns delay
Text Notes 5900 5400 2 50 ~ 0
1-3ns delay
Text Notes 7000 5500 0 50 ~ 0
1-6ns delay
Text Notes 7850 5450 0 50 ~ 0
1-4ns delay
$Comp
L Device:C_Small C8
U 1 1 60CDF1EF
P 3200 3800
F 0 "C8" H 3292 3846 50 0000 L CNN
F 1 "100n" H 3292 3755 50 0000 L CNN
F 2 "stdpads:C_0805" H 3200 3800 50 0001 C CNN
F 3 "~" H 3200 3800 50 0001 C CNN
1 3200 3800
1 0 0 -1
$EndComp
Wire Wire Line
3200 3900 2800 3900
Wire Wire Line
2800 3700 3200 3700
$Comp
L power:GND #PWR0120
U 1 1 60CDF1F7
P 3200 3900
F 0 "#PWR0120" H 3200 3650 50 0001 C CNN
F 1 "GND" H 3200 3750 50 0000 C CNN
F 2 "" H 3200 3900 50 0001 C CNN
F 3 "" H 3200 3900 50 0001 C CNN
1 3200 3900
1 0 0 -1
$EndComp
Connection ~ 3200 3900
Connection ~ 2800 3700
$EndSCHEMATC

View File

@ -0,0 +1,4 @@
(sym_lib_table
(lib (name GW_RAM)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_RAM.lib")(options "")(descr ""))
(lib (name GW_Logic)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_Logic.lib")(options "")(descr ""))
)

View File

@ -0,0 +1,3 @@
(fp_lib_table
(lib (name stdpads)(type KiCad)(uri "$(KIPRJMOD)/../../stdpads.pretty")(options "")(descr ""))
)

View File

@ -0,0 +1,286 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 74xGxx_74AHCT1G04
#
DEF 74xGxx_74AHCT1G04 U 0 40 Y Y 1 F N
F0 "U" -100 150 50 H V C CNN
F1 "74xGxx_74AHCT1G04" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74LVC1GU04 74AHC1G04 74AHCT1G04 74AUC1G04 74AUP1G04 74AHC1GU04 74AHCT1GU04 74AUC1GU04 74AUP1GU04
$FPLIST
SOT*
SG-*
$ENDFPLIST
DRAW
P 4 0 1 10 -150 100 -150 -100 100 0 -150 100 N
X ~ 2 -300 0 150 R 40 40 1 1 I
X GND 3 0 -100 0 D 40 40 1 1 W N
X ~ 4 250 0 150 L 40 40 1 1 O I
X VCC 5 0 100 0 U 40 40 1 1 W N
ENDDRAW
ENDDEF
#
# 74xGxx_74AHCT1G32
#
DEF 74xGxx_74AHCT1G32 U 0 40 Y Y 1 F N
F0 "U" -100 150 50 H V C CNN
F1 "74xGxx_74AHCT1G32" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74AHC1G32 74AHCT1G32 74AUC1G32 74AUP1G32
$FPLIST
SOT*
SG-*
$ENDFPLIST
DRAW
A -275 0 160 386 -386 0 1 10 N -150 100 -150 -100
A -38 -37 142 744 150 0 1 10 N 0 100 100 0
A -38 37 142 -744 -150 0 1 10 N 0 -100 100 0
P 2 0 1 0 -150 -50 -125 -50 N
P 2 0 1 0 -150 50 -125 50 N
P 2 0 1 10 0 -100 -150 -100 f
P 2 0 1 10 0 100 -150 100 f
X ~ 1 -300 50 150 R 40 40 1 1 I
X ~ 2 -300 -50 150 R 40 40 1 1 I
X GND 3 0 -100 0 D 40 40 1 1 W N
X ~ 4 250 0 150 L 40 40 1 1 O
X VCC 5 0 100 0 U 40 40 1 1 W N
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x30
#
DEF Connector_Generic_Conn_01x30 J 0 40 Y N 1 F N
F0 "J" 0 1500 50 H V C CNN
F1 "Connector_Generic_Conn_01x30" 0 -1600 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -1495 0 -1505 1 1 6 N
S -50 -1395 0 -1405 1 1 6 N
S -50 -1295 0 -1305 1 1 6 N
S -50 -1195 0 -1205 1 1 6 N
S -50 -1095 0 -1105 1 1 6 N
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 905 0 895 1 1 6 N
S -50 1005 0 995 1 1 6 N
S -50 1105 0 1095 1 1 6 N
S -50 1205 0 1195 1 1 6 N
S -50 1305 0 1295 1 1 6 N
S -50 1405 0 1395 1 1 6 N
S -50 1450 50 -1550 1 1 10 f
X Pin_1 1 -200 1400 150 R 50 50 1 1 P
X Pin_10 10 -200 500 150 R 50 50 1 1 P
X Pin_11 11 -200 400 150 R 50 50 1 1 P
X Pin_12 12 -200 300 150 R 50 50 1 1 P
X Pin_13 13 -200 200 150 R 50 50 1 1 P
X Pin_14 14 -200 100 150 R 50 50 1 1 P
X Pin_15 15 -200 0 150 R 50 50 1 1 P
X Pin_16 16 -200 -100 150 R 50 50 1 1 P
X Pin_17 17 -200 -200 150 R 50 50 1 1 P
X Pin_18 18 -200 -300 150 R 50 50 1 1 P
X Pin_19 19 -200 -400 150 R 50 50 1 1 P
X Pin_2 2 -200 1300 150 R 50 50 1 1 P
X Pin_20 20 -200 -500 150 R 50 50 1 1 P
X Pin_21 21 -200 -600 150 R 50 50 1 1 P
X Pin_22 22 -200 -700 150 R 50 50 1 1 P
X Pin_23 23 -200 -800 150 R 50 50 1 1 P
X Pin_24 24 -200 -900 150 R 50 50 1 1 P
X Pin_25 25 -200 -1000 150 R 50 50 1 1 P
X Pin_26 26 -200 -1100 150 R 50 50 1 1 P
X Pin_27 27 -200 -1200 150 R 50 50 1 1 P
X Pin_28 28 -200 -1300 150 R 50 50 1 1 P
X Pin_29 29 -200 -1400 150 R 50 50 1 1 P
X Pin_3 3 -200 1200 150 R 50 50 1 1 P
X Pin_30 30 -200 -1500 150 R 50 50 1 1 P
X Pin_4 4 -200 1100 150 R 50 50 1 1 P
X Pin_5 5 -200 1000 150 R 50 50 1 1 P
X Pin_6 6 -200 900 150 R 50 50 1 1 P
X Pin_7 7 -200 800 150 R 50 50 1 1 P
X Pin_8 8 -200 700 150 R 50 50 1 1 P
X Pin_9 9 -200 600 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Small
#
DEF Device_R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "Device_R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -30 70 30 -70 0 1 8 N
X ~ 1 0 100 30 D 50 50 1 1 P
X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GW_Logic_741G74DC
#
DEF GW_Logic_741G74DC U 0 40 Y Y 1 F N
F0 "U" 0 300 50 H V C CNN
F1 "GW_Logic_741G74DC" 0 -300 50 H V C CNN
F2 "stdpads:SOT-353" 0 -350 50 H I C TNN
F3 "" 0 -200 60 H I C CNN
DRAW
S 200 -250 -200 250 0 1 10 f
X CK 1 -400 -150 200 R 50 50 1 1 I
X D 2 -400 150 200 R 50 50 1 1 I
X ~Q~ 3 400 -50 200 L 50 50 1 1 O
X GND 4 400 -150 200 L 50 50 1 1 W
X Q 5 400 50 200 L 50 50 1 1 O
X ~R~ 6 -400 -50 200 R 50 50 1 1 I
X ~S~ 7 -400 50 200 R 50 50 1 1 I
X Vcc 8 400 150 200 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_RAM_DRAM-4Mx4-SOP-24
#
DEF GW_RAM_DRAM-4Mx4-SOP-24 U 0 20 Y Y 1 F N
F0 "U" 0 650 50 H V C CNN
F1 "GW_RAM_DRAM-4Mx4-SOP-24" 0 0 50 V V C CNN
F2 "stdpads:SOP-24-26-300mil" 0 -650 50 H I C CNN
F3 "" 0 -600 50 H I C CNN
$FPLIST
SOJ*10.16x23.49mm*P1.27mm*
$ENDFPLIST
DRAW
S -300 600 300 -600 0 1 10 f
X VDD 1 400 500 100 L 50 50 1 1 W
X A1 10 -400 400 100 R 50 50 1 1 I
X A2 11 -400 300 100 R 50 50 1 1 I
X A3 12 -400 200 100 R 50 50 1 1 I
X VDD 13 400 500 100 L 50 50 1 1 W N
X GND 14 400 -500 100 L 50 50 1 1 W N
X A4 15 -400 100 100 R 50 50 1 1 I
X A5 16 -400 0 100 R 50 50 1 1 I
X A6 17 -400 -100 100 R 50 50 1 1 I
X A7 18 -400 -200 100 R 50 50 1 1 I
X A8 19 -400 -300 100 R 50 50 1 1 I
X D0 2 400 400 100 L 50 50 1 1 B
X NC 20 400 0 100 L 50 50 1 1 N N
X A9 21 -400 -400 100 R 50 50 1 1 I
X ~OE~ 22 400 -400 100 L 50 50 1 1 I
X ~CAS~ 23 400 -100 100 L 50 50 1 1 I
X D2 24 400 200 100 L 50 50 1 1 B
X D3 25 400 100 100 L 50 50 1 1 B
X GND 26 400 -500 100 L 50 50 1 1 W
X D1 3 400 300 100 L 50 50 1 1 B
X ~WE~ 4 400 -300 100 L 50 50 1 1 I
X ~RAS~ 5 400 -200 100 L 50 50 1 1 I
X NC 7 400 0 100 L 50 50 1 1 N N
X A10 8 -400 -500 100 R 50 50 1 1 I
X A0 9 -400 500 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# Regulator_Linear_XC6206PxxxMR
#
DEF Regulator_Linear_XC6206PxxxMR U 0 10 Y Y 1 F N
F0 "U" -150 125 50 H V C CNN
F1 "Regulator_Linear_XC6206PxxxMR" 0 125 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23" 0 225 50 H I C CIN
F3 "" 0 0 50 H I C CNN
ALIAS APE8865N-15-HF-3 APE8865N-16-HF-3 APE8865N-17-HF-3 APE8865N-18-HF-3 APE8865N-19-HF-3 APE8865N-20-HF-3 APE8865N-21-HF-3 APE8865N-22-HF-3 APE8865N-23-HF-3 APE8865N-24-HF-3 APE8865N-25-HF-3 APE8865N-26-HF-3 APE8865N-27-HF-3 APE8865N-28-HF-3 APE8865N-29-HF-3 APE8865N-30-HF-3 APE8865N-31-HF-3 APE8865N-32-HF-3 APE8865N-33-HF-3 AP2127N-1.0 AP2127N-1.2 AP2127N-1.5 AP2127N-1.8 AP2127N-2.5 AP2127N-2.8 AP2127N-3.0 AP2127N-3.3 XC6206PxxxMR
$FPLIST
SOT?23*
$ENDFPLIST
DRAW
S -200 75 200 -200 0 1 10 f
X GND 1 0 -300 100 U 50 50 1 1 W
X VO 2 300 0 100 L 50 50 1 1 w
X VI 3 -300 0 100 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# power_+3V3
#
DEF power_+3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,262 @@
update=Wednesday, June 09, 2021 at 11:45:00 AM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=simm-30-4mb.net
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.127
MinViaDiameter=0.508
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1524
TrackWidth2=0.1524
TrackWidth3=0.254
TrackWidth4=0.4
TrackWidth5=0.45
TrackWidth6=0.508
TrackWidth7=0.6
TrackWidth8=0.762
TrackWidth9=0.8
TrackWidth10=1.27
TrackWidth11=1.524
ViaDiameter1=0.508
ViaDrill1=0.2
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.8
ViaDrill3=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.07619999999999999
SolderMaskMinWidth=0.127
SolderPasteClearance=-0.03809999999999999
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=1
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.508
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

View File

@ -0,0 +1,900 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr USLetter 11000 8500
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector_Generic:Conn_01x30 J1
U 1 1 5C2E1E12
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F 0 "J1" V 4574 3396 50 0000 C CNN
F 1 "DRAM-SIMM-30" V 4665 3396 50 0000 C CNN
F 2 "stdpads:SIMM-30_Edge" H 4450 3450 50 0001 C CNN
F 3 "~" H 4450 3450 50 0001 C CNN
1 4450 3450
0 -1 1 0
$EndComp
$Comp
L power:+5V #PWR0101
U 1 1 5C2E1ED2
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F 0 "#PWR0101" H 5950 3100 50 0001 C CNN
F 1 "+5V" H 5950 3400 50 0000 C CNN
F 2 "" H 5950 3250 50 0001 C CNN
F 3 "" H 5950 3250 50 0001 C CNN
1 5950 3250
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR0102
U 1 1 5C2E1F89
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F 0 "#PWR0102" H 3050 3100 50 0001 C CNN
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F 2 "" H 3050 3250 50 0001 C CNN
F 3 "" H 3050 3250 50 0001 C CNN
1 3050 3250
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0103
U 1 1 5C2E2010
P 5150 3250
F 0 "#PWR0103" H 5150 3000 50 0001 C CNN
F 1 "GND" H 5150 3100 50 0000 C CNN
F 2 "" H 5150 3250 50 0001 C CNN
F 3 "" H 5150 3250 50 0001 C CNN
1 5150 3250
-1 0 0 1
$EndComp
$Comp
L power:GND #PWR0104
U 1 1 5C2E2033
P 3850 3250
F 0 "#PWR0104" H 3850 3000 50 0001 C CNN
F 1 "GND" H 3850 3100 50 0000 C CNN
F 2 "" H 3850 3250 50 0001 C CNN
F 3 "" H 3850 3250 50 0001 C CNN
1 3850 3250
-1 0 0 1
$EndComp
Text Label 3150 3250 1 50 ~ 0
~CAS~
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D0
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D1
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A11
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QP
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DP
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Wire Wire Line
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Wire Wire Line
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Connection ~ 1850 7400
Wire Wire Line
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Wire Wire Line
1850 7350 1950 7350
Wire Wire Line
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Wire Wire Line
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Connection ~ 1850 5400
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
1750 5400 1850 5400
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Wire Wire Line
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Connection ~ 1850 6000
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Wire Wire Line
1850 5950 1950 5950
Wire Wire Line
1750 6000 1850 6000
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Connection ~ 1850 7200
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$Comp
L Device:C_Small C1
U 1 1 5C2E290A
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1 2400 4200
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C2
U 1 1 5C2E296A
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F 3 "~" H 2800 4200 50 0001 C CNN
1 2800 4200
1 0 0 -1
$EndComp
Wire Wire Line
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$Comp
L power:+5V #PWR0113
U 1 1 5C2E299D
P 2400 4100
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F 2 "" H 2400 4100 50 0001 C CNN
F 3 "" H 2400 4100 50 0001 C CNN
1 2400 4100
1 0 0 -1
$EndComp
Connection ~ 2400 4100
Wire Wire Line
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$Comp
L Device:C_Small C3
U 1 1 5C2EDC35
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F 1 "100n" H 3292 4155 50 0000 L CNN
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F 3 "~" H 3200 4200 50 0001 C CNN
1 3200 4200
1 0 0 -1
$EndComp
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Wire Wire Line
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Connection ~ 2800 4300
Connection ~ 3200 4300
Wire Wire Line
3200 4300 3600 4300
Connection ~ 3600 4300
Wire Wire Line
3600 4100 3200 4100
Connection ~ 3200 4100
$Comp
L Device:C_Small C4
U 1 1 5D1301A9
P 3600 4200
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F 1 "100n" H 3692 4155 50 0000 L CNN
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F 3 "~" H 3600 4200 50 0001 C CNN
1 3600 4200
1 0 0 -1
$EndComp
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$Comp
L GW_RAM:DRAM-4Mx4-SOP-24 U1
U 1 1 5D38F422
P 3800 6650
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1 3800 6650
1 0 0 -1
$EndComp
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$Comp
L power:GND #PWR0105
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1 4200 7150
1 0 0 -1
$EndComp
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L power:+5V #PWR0106
U 1 1 5D396692
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1 4200 6150
1 0 0 -1
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$Comp
L power:GND #PWR0108
U 1 1 5D3999DD
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F 1 "GND" H 5800 7050 50 0000 C CNN
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1 0 0 -1
$EndComp
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~CAS~
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$Comp
L power:+5V #PWR0109
U 1 1 5D3999EA
P 5800 6200
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F 1 "+5V" H 5800 6350 50 0000 C CNN
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F 3 "" H 5800 6200 50 0001 C CNN
1 5800 6200
1 0 0 -1
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D0
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D2
Text Label 5800 6400 0 50 ~ 0
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$Comp
L power:GND #PWR0110
U 1 1 5D3FC319
P 4000 4300
F 0 "#PWR0110" H 4000 4050 50 0001 C CNN
F 1 "GND" H 4000 4150 50 0000 C CNN
F 2 "" H 4000 4300 50 0001 C CNN
F 3 "" H 4000 4300 50 0001 C CNN
1 4000 4300
1 0 0 -1
$EndComp
Wire Wire Line
3600 4300 4000 4300
Connection ~ 4000 4300
Wire Wire Line
4000 4100 3600 4100
$Comp
L Device:C_Small C5
U 1 1 5D3FC322
P 4000 4200
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F 1 "100n" H 4092 4155 50 0000 L CNN
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F 3 "~" H 4000 4200 50 0001 C CNN
1 4000 4200
1 0 0 -1
$EndComp
$Comp
L GW_RAM:DRAM-4Mx4-SOP-24 U2
U 1 1 5D3999D6
P 5400 6700
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F 2 "stdpads:SOP-24-26-300mil" H 5400 6000 50 0001 C CNN
F 3 "https://www.alliancememory.com/wp-content/uploads/pdf/AS6C8008.pdf" H 5400 6200 50 0001 C CNN
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$Comp
L power:GND #PWR0107
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L Device:R_Small R2
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L Device:R_Small R1
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L power:GND #PWR0115
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$Comp
L 74xGxx:74AHCT1G32 U5
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$Comp
L power:GND #PWR0118
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$Comp
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$Comp
L power:GND #PWR0119
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$Comp
L Device:C_Small C7
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Wire Wire Line
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Wire Wire Line
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L power:+3V3 #PWR0121
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$Comp
L power:+5V #PWR0122
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Wire Wire Line
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L power:+3V3 #PWR0123
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$EndComp
Wire Wire Line
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$Comp
L power:+3V3 #PWR0114
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1 7550 4900
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$EndComp
$Comp
L power:+3V3 #PWR0117
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Wire Wire Line
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L Device:C_Small C9
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$EndComp
$Comp
L Device:R_Small R3
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$EndComp
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
L 74xGxx:74AHCT1G04 U3
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F 1 "74LVC1G04" H 6000 5100 50 0000 L CNN
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$Comp
L power:GND #PWR0112
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
L power:+3V3 #PWR0111
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$Comp
L power:+3V3 #PWR0116
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$EndComp
$Comp
L Device:R_Small R4
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$EndComp
$Comp
L Device:C_Small C8
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1 3200 3800
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$EndComp
Wire Wire Line
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Wire Wire Line
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$Comp
L power:GND #PWR0120
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F 3 "" H 3200 3900 50 0001 C CNN
1 3200 3900
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$EndSCHEMATC

View File

@ -0,0 +1,4 @@
(sym_lib_table
(lib (name GW_RAM)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_RAM.lib")(options "")(descr ""))
(lib (name GW_Logic)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_Logic.lib")(options "")(descr ""))
)

20
LICENSE Normal file
View File

@ -0,0 +1,20 @@
Copyright (c) Garrett's Workshop
Rationale
----------------------------------------
We at Garrett's Workshop create our products and release their source in
hopes of encouraging others to contribute and build their own "clones,"
even selling them and competing with us. One day, GW will be defunct,
and it would be a shame if our hardware and software die along with GW.
At the same time, however, we seek to protect our trademark and ensure
that clones and derivative products do not masquerade as genuine
Garrett's Workshop products.
License Terms
----------------------------------------
This project may be licensed under one of two licenses:
1. You may elect to license this project under CC BY-NC-SA 4.0.
2. You may elect to license this project under CC BY-SA 4.0 ONLY IF
you remove all "Garrett's Workshop" trademarks from the project.