2024-05-29 01:03:49 +00:00
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// //---------------------------------------------------------------------------
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// //
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2024-06-01 00:28:27 +00:00
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// // SCSI Target Emulator PiSCSI
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// // for Raspberry Pi
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2024-05-29 01:03:49 +00:00
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// //
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2024-06-01 00:28:27 +00:00
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// // Powered by XM6 TypeG Technology.
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// // Copyright (C) 2022-2024 akuker
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// // Copyright (C) 2016-2020 GIMONS
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2024-05-29 01:03:49 +00:00
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// //
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2024-06-01 00:28:27 +00:00
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// // [ GPIO-SCSI bus for SBCs using the Raspberry Pi RP1 chip ]
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2024-05-29 01:03:49 +00:00
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// //
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// //---------------------------------------------------------------------------
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2024-06-01 00:28:27 +00:00
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// #pragma once
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// #include "hal/data_sample_raspberry.h"
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// #include "hal/gpiobus.h"
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// #include "shared/scsi.h"
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// #include <map>
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// // //---------------------------------------------------------------------------
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// // //
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// // // SCSI signal pin assignment setting
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// // // GPIO pin mapping table for SCSI signals.
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// // // PIN_DT0~PIN_SEL
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// // //
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// // //---------------------------------------------------------------------------
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// // #define ALL_SCSI_PINS
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// // ((1 << PIN_DT0) | (1 << PIN_DT1) | (1 << PIN_DT2) | (1 << PIN_DT3) | (1 << PIN_DT4) | (1 << PIN_DT5) |
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// // (1 << PIN_DT6) | (1 << PIN_DT7) | (1 << PIN_DP) | (1 << PIN_ATN) | (1 << PIN_RST) | (1 << PIN_ACK) |
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// // (1 << PIN_REQ) | (1 << PIN_MSG) | (1 << PIN_CD) | (1 << PIN_IO) | (1 << PIN_BSY) | (1 << PIN_SEL))
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// // #define GPIO_INEDGE ((1 << PIN_BSY) | (1 << PIN_SEL) | (1 << PIN_ATN) | (1 << PIN_ACK) | (1 << PIN_RST))
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// // #define GPIO_MCI ((1 << PIN_MSG) | (1 << PIN_CD) | (1 << PIN_IO))
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// #define UNUSED(x) (void)(x)
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// // //---------------------------------------------------------------------------
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// // //
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// // // Constant declarations (GIC)
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// // //
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// // //---------------------------------------------------------------------------
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// // const static uint32_t ARM_GICD_BASE = 0xFF841000;
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// // const static uint32_t ARM_GICC_BASE = 0xFF842000;
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// // const static uint32_t ARM_GIC_END = 0xFF847FFF;
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// // const static int GICD_CTLR = 0x000;
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// // const static int GICD_IGROUPR0 = 0x020;
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// // const static int GICD_ISENABLER0 = 0x040;
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// // const static int GICD_ICENABLER0 = 0x060;
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// // const static int GICD_ISPENDR0 = 0x080;
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// // const static int GICD_ICPENDR0 = 0x0A0;
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// // const static int GICD_ISACTIVER0 = 0x0C0;
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// // const static int GICD_ICACTIVER0 = 0x0E0;
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// // const static int GICD_IPRIORITYR0 = 0x100;
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// // const static int GICD_ITARGETSR0 = 0x200;
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// // const static int GICD_ICFGR0 = 0x300;
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// // const static int GICD_SGIR = 0x3C0;
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// // const static int GICC_CTLR = 0x000;
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// // const static int GICC_PMR = 0x001;
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// // const static int GICC_IAR = 0x003;
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// // const static int GICC_EOIR = 0x004;
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// // //---------------------------------------------------------------------------
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// // //
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// // // Constant declarations (GIC IRQ)
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// // //
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// // //---------------------------------------------------------------------------
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// // const static int GIC_IRQLOCAL0 = (16 + 14);
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// // const static int GIC_GPIO_IRQ = (32 + 116); // GPIO3
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2024-05-29 01:03:49 +00:00
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// //---------------------------------------------------------------------------
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// //
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2024-06-01 00:28:27 +00:00
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// // Class definition
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2024-05-29 01:03:49 +00:00
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// //
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// //---------------------------------------------------------------------------
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2024-06-01 00:28:27 +00:00
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// class GPIOBUS_RPi_rp1 : public GPIOBUS
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// {
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// public:
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// GPIOBUS_RPi_rp1() = default;
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// ~GPIOBUS_RPi_rp1() override = default;
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// bool Init(mode_e mode = mode_e::TARGET) override;
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// void Reset() override;
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// void Cleanup() override;
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// // Bus signal acquisition
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// uint32_t Acquire() override;
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// // Set ENB signal
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// void SetENB(bool ast) override;
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// // Get BSY signal
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// bool GetBSY() const override;
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// // Set BSY signal
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// void SetBSY(bool ast) override;
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// // Get SEL signal
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// bool GetSEL() const override;
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// // Set SEL signal
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// void SetSEL(bool ast) override;
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// // Get ATN signal
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// bool GetATN() const override;
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// // Set ATN signal
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// void SetATN(bool ast) override;
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// // Get ACK signal
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// bool GetACK() const override;
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// // Set ACK signal
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// void SetACK(bool ast) override;
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// // Get ACT signal
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// bool GetACT() const override;
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// // Set ACT signal
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// void SetACT(bool ast) override;
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// // Get RST signal
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// bool GetRST() const override;
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// // Set RST signal
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// void SetRST(bool ast) override;
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// // Get MSG signal
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// bool GetMSG() const override;
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// // Set MSG signal
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// void SetMSG(bool ast) override;
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// // Get CD signal
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// bool GetCD() const override;
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// // Set CD signal
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// void SetCD(bool ast) override;
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// // Get IO signal
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// bool GetIO() override;
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// // Set IO signal
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// void SetIO(bool ast) override;
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// // Get REQ signal
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// bool GetREQ() const override;
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// // Set REQ signal
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// void SetREQ(bool ast) override;
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// // Get DAT signal
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// uint8_t GetDAT() override;
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// // Set DAT signal
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// void SetDAT(uint8_t dat) override;
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// bool WaitREQ(bool ast) override
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// {
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// UNUSED(ast);
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// printf("FIX THIS\n");
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// return false;
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// // return WaitSignal(PIN_REQ, ast);
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// }
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// bool WaitACK(bool ast) override
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// {
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// UNUSED(ast);
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// printf("FIX THIS\n");
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// return false;
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// // return WaitSignal(PIN_ACK, ast);
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// }
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// static uint32_t bcm_host_get_peripheral_address();
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// unique_ptr<DataSample> GetSample(uint64_t timestamp) override
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// {
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// // Acquire();
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// printf("FIX THIS\n");
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// return make_unique<DataSample_Raspberry>(0, timestamp);
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// // return make_unique<DataSample_Raspberry>(signals, timestamp);
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// }
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// // protected:
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// // All bus signals
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// uint32_t signals = 0;
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// // // GPIO input level
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// // volatile uint32_t *level = nullptr;
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// // private:
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// // // SCSI I/O signal control
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// // void MakeTable() override;
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// // // Create work data
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// // void SetControl(int pin, bool ast) override;
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// // // Set Control Signal
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// // void SetMode(int pin, int mode) override;
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// // // Set SCSI I/O mode
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// // bool GetSignal(int pin) const override;
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// // // Get SCSI input signal value
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// // void SetSignal(int pin, bool ast) override;
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// // // Set SCSI output signal value
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// // // Interrupt control
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// // void DisableIRQ() override;
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// // // IRQ Disabled
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// // void EnableIRQ() override;
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// // // IRQ Enabled
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// // // GPIO pin functionality settings
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// // void PinConfig(int pin, int mode) override;
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// // // GPIO pin direction setting
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// // void PullConfig(int pin, int mode) override;
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// // // GPIO pin pull up/down resistor setting
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// // void PinSetSignal(int pin, bool ast) override;
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// // // Set GPIO output signal
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// // void DrvConfig(uint32_t drive) override;
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// // // Set GPIO drive strength
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// // static uint32_t get_dt_ranges(const char *filename, uint32_t offset);
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// // uint32_t baseaddr = 0; // Base address
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// // int rpitype = 0; // Type of Raspberry Pi
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// // // GPIO register
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// // volatile uint32_t *gpio = nullptr; // NOSONAR: volatile needed for register access
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// // // PADS register
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// // volatile uint32_t *pads = nullptr; // NOSONAR: volatile needed for register access
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// // // Interrupt control register
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// // volatile uint32_t *irpctl = nullptr;
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// // // Interrupt enabled state
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// // volatile uint32_t irptenb; // NOSONAR: volatile needed for register access
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// // // QA7 register
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// // volatile uint32_t *qa7regs = nullptr;
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// // // Interupt control target CPU.
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// // volatile int tintcore; // NOSONAR: volatile needed for register access
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// // // Interupt control
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// // volatile uint32_t tintctl; // NOSONAR: volatile needed for register access
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// // // GICC priority setting
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// // volatile uint32_t giccpmr; // NOSONAR: volatile needed for register access
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// // #if !defined(__x86_64__) && !defined(__X86__)
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// // // GIC Interrupt distributor register
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// // volatile uint32_t *gicd = nullptr;
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// // #endif
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// // // GIC CPU interface register
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// // volatile uint32_t *gicc = nullptr;
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// // // RAM copy of GPFSEL0-4 values (GPIO Function Select)
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// // array<uint32_t, 4> gpfsel;
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// // #if SIGNAL_CONTROL_MODE == 0
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// // // Data mask table
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// // array<array<uint32_t, 256>, 3> tblDatMsk;
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// // // Data setting table
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// // array<array<uint32_t, 256>, 3> tblDatSet;
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// // #else
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// // // Data mask table
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// // array<uint32_t, 256> tblDatMsk = {};
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// // // Table setting table
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// // array<uint32_t, 256> tblDatSet = {};
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// // #endif
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// // static const array<int, 19> SignalTable;
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// // const static int GPIO_FSEL_0 = 0;
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// // const static int GPIO_FSEL_1 = 1;
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// // const static int GPIO_FSEL_2 = 2;
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// // const static int GPIO_FSEL_3 = 3;
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// // const static int GPIO_SET_0 = 7;
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// // const static int GPIO_CLR_0 = 10;
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// // const static int GPIO_LEV_0 = 13;
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// // const static int GPIO_EDS_0 = 16;
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// // const static int GPIO_REN_0 = 19;
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// // const static int GPIO_FEN_0 = 22;
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// // const static int GPIO_HEN_0 = 25;
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// // const static int GPIO_LEN_0 = 28;
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// // const static int GPIO_AREN_0 = 31;
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// // const static int GPIO_AFEN_0 = 34;
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// // const static int GPIO_PUD = 37;
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// // const static int GPIO_CLK_0 = 38;
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// // const static int GPIO_GPPINMUXSD = 52;
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// // const static int GPIO_PUPPDN0 = 57;
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// // const static int GPIO_PUPPDN1 = 58;
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// // const static int GPIO_PUPPDN3 = 59;
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// // const static int GPIO_PUPPDN4 = 60;
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// // const static int PAD_0_27 = 11;
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// // const static int IRPT_PND_IRQ_B = 0;
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// // const static int IRPT_PND_IRQ_1 = 1;
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// // const static int IRPT_PND_IRQ_2 = 2;
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// // const static int IRPT_FIQ_CNTL = 3;
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// // const static int IRPT_ENB_IRQ_1 = 4;
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// // const static int IRPT_ENB_IRQ_2 = 5;
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// // const static int IRPT_ENB_IRQ_B = 6;
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// // const static int IRPT_DIS_IRQ_1 = 7;
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// // const static int IRPT_DIS_IRQ_2 = 8;
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// // const static int IRPT_DIS_IRQ_B = 9;
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// // const static int QA7_CORE0_TINTC = 16;
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// // const static int GPIO_IRQ = (32 + 20); // GPIO3
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// // const static uint32_t IRPT_OFFSET = 0x0000B200;
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// // const static uint32_t PADS_OFFSET = 0x00100000;
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// // const static uint32_t GPIO_OFFSET = 0x00200000;
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// // const static uint32_t QA7_OFFSET = 0x01000000;
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// const static uint32_t RP1_NUM_GPIOS = 54;
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// const static uint32_t RP1_IO_BANK0_OFFSET = 0x00000000;
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// const static uint32_t RP1_IO_BANK1_OFFSET = 0x00004000;
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// const static uint32_t RP1_IO_BANK2_OFFSET = 0x00008000;
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// const static uint32_t RP1_SYS_RIO_BANK0_OFFSET = 0x00010000;
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// const static uint32_t RP1_SYS_RIO_BANK1_OFFSET = 0x00014000;
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// const static uint32_t RP1_SYS_RIO_BANK2_OFFSET = 0x00018000;
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// const static uint32_t RP1_PADS_BANK0_OFFSET = 0x00020000;
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// const static uint32_t RP1_PADS_BANK1_OFFSET = 0x00024000;
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// const static uint32_t RP1_PADS_BANK2_OFFSET = 0x00028000;
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// const static uint32_t RP1_RW_OFFSET = 0x0000;
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// const static uint32_t RP1_XOR_OFFSET = 0x1000;
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// const static uint32_t RP1_SET_OFFSET = 0x2000;
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// const static uint32_t RP1_CLR_OFFSET = 0x3000;
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// const static uint32_t RP1_GPIO_CTRL_FSEL_LSB = 0;
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// const static uint32_t RP1_GPIO_CTRL_FSEL_MASK = (0x1f << RP1_GPIO_CTRL_FSEL_LSB);
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// const static uint32_t RP1_GPIO_CTRL_OUTOVER_LSB = 12;
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// const static uint32_t RP1_GPIO_CTRL_OUTOVER_MASK = (0x03 << RP1_GPIO_CTRL_OUTOVER_LSB);
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// const static uint32_t RP1_GPIO_CTRL_OEOVER_LSB = 14;
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// const static uint32_t RP1_GPIO_CTRL_OEOVER_MASK = (0x03 << RP1_GPIO_CTRL_OEOVER_LSB);
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// const static uint32_t RP1_PADS_OD_SET = (1 << 7);
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// const static uint32_t RP1_PADS_IE_SET = (1 << 6);
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// const static uint32_t RP1_PADS_PUE_SET = (1 << 3);
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// const static uint32_t RP1_PADS_PDE_SET = (1 << 2);
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// inline uint32_t RP1_GPIO_IO_REG_STATUS_OFFSET(int offset) { (((offset * 2) + 0) * sizeof(uint32_t)); }
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// inline uint32_t RP1_GPIO_IO_REG_CTRL_OFFSET(int offset) { (((offset * 2) + 1) * sizeof(uint32_t)); }
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// inline uint32_t RP1_GPIO_PADS_REG_OFFSET(int offset) { (sizeof(uint32_t) + (offset * sizeof(uint32_t))); }
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// const static uint32_t RP1_GPIO_SYS_RIO_REG_OUT_OFFSET = 0x0;
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// const static uint32_t RP1_GPIO_SYS_RIO_REG_OE_OFFSET = 0x4;
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// const static uint32_t RP1_GPIO_SYS_RIO_REG_SYNC_IN_OFFSET = 0x8;
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// inline void rp1_gpio_write32(volatile uint32_t *base, int peri_offset, int reg_offset, uint32_t value)
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// {
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// base[(peri_offset + reg_offset) / 4] = value;
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// }
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// inline uint32_t rp1_gpio_read32(volatile uint32_t *base, int peri_offset, int reg_offset)
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// {
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// return base[(peri_offset + reg_offset) / 4];
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// }
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// typedef struct
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// {
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// uint32_t io[3];
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// uint32_t pads[3];
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// uint32_t sys_rio[3];
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// } GPIO_STATE_T;
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// typedef enum
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// {
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// RP1_FSEL_ALT0 = 0x0,
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// RP1_FSEL_ALT1 = 0x1,
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// RP1_FSEL_ALT2 = 0x2,
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// RP1_FSEL_ALT3 = 0x3,
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// RP1_FSEL_ALT4 = 0x4,
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// RP1_FSEL_ALT5 = 0x5,
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// RP1_FSEL_ALT6 = 0x6,
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// RP1_FSEL_ALT7 = 0x7,
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// RP1_FSEL_ALT8 = 0x8,
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// RP1_FSEL_COUNT,
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// RP1_FSEL_SYS_RIO = RP1_FSEL_ALT5,
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// RP1_FSEL_NULL = 0x1f
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// } RP1_FSEL_T;
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// const static GPIO_STATE_T gpio_state;
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// const static int rp1_bank_base[];
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// #define NUM_HDR_PINS 40
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// #define MAX_GPIO_PINS 300
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// #define GPIO_INVALID (~0U)
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// #define GPIO_GND (~1U)
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// #define GPIO_5V (~2U)
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// #define GPIO_3V3 (~3U)
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// #define GPIO_1V8 (~4U)
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// #define GPIO_OTHER (~5U)
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// typedef enum
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// {
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// GPIO_FSEL_FUNC0,
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// GPIO_FSEL_FUNC1,
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// GPIO_FSEL_FUNC2,
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// GPIO_FSEL_FUNC3,
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// GPIO_FSEL_FUNC4,
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// GPIO_FSEL_FUNC5,
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// GPIO_FSEL_FUNC6,
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// GPIO_FSEL_FUNC7,
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// GPIO_FSEL_FUNC8,
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// /* ... */
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// GPIO_FSEL_INPUT = 0x10,
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// GPIO_FSEL_OUTPUT,
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// GPIO_FSEL_GPIO, /* Preserves direction if possible, else input */
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// GPIO_FSEL_NONE, /* If possible, else input */
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// GPIO_FSEL_MAX
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// } GPIO_FSEL_T;
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// typedef enum
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// {
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// PULL_NONE,
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// PULL_DOWN,
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// PULL_UP,
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// PULL_MAX
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// } GPIO_PULL_T;
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// typedef enum
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// {
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// DIR_INPUT,
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// DIR_OUTPUT,
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// DIR_MAX,
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// } GPIO_DIR_T;
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// typedef enum
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// {
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// DRIVE_LOW,
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// DRIVE_HIGH,
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// DRIVE_MAX
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// } GPIO_DRIVE_T;
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// typedef struct GPIO_CHIP_
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// {
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// const char *name;
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// const char *compatible;
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// // const GPIO_CHIP_INTERFACE_T *interface;
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// int size;
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// uintptr_t data;
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// } GPIO_CHIP_T;
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// // const char *GPIOBUS_RPi_rp1::rp1_gpio_fsel_names[GPIOBUS_RPi_rp1::RP1_NUM_GPIOS][GPIOBUS_RPi_rp1::RP1_FSEL_COUNT];
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// void rp1_gpio_get_bank(int num, int *bank, int *offset);
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// uint32_t rp1_gpio_ctrl_read(volatile uint32_t *base, int bank, int offset);
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// void rp1_gpio_ctrl_write(volatile uint32_t *base, int bank, int offset, uint32_t value);
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// uint32_t rp1_gpio_pads_read(volatile uint32_t *base, int bank, int offset);
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// void rp1_gpio_pads_write(volatile uint32_t *base, int bank, int offset, uint32_t value);
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// uint32_t rp1_gpio_sys_rio_out_read(volatile uint32_t *base, int bank, int offset);
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// uint32_t rp1_gpio_sys_rio_sync_in_read(volatile uint32_t *base, int bank, int offset);
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// void rp1_gpio_sys_rio_out_set(volatile uint32_t *base, int bank, int offset);
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// void rp1_gpio_sys_rio_out_clr(volatile uint32_t *base, int bank, int offset);
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// uint32_t rp1_gpio_sys_rio_oe_read(volatile uint32_t *base, int bank);
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// void rp1_gpio_sys_rio_oe_clr(volatile uint32_t *base, int bank, int offset);
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// void rp1_gpio_sys_rio_oe_set(volatile uint32_t *base, int bank, int offset);
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// void rp1_gpio_set_dir(void *priv, uint32_t gpio, GPIO_DIR_T dir);
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// GPIO_DIR_T rp1_gpio_get_dir(void *priv, unsigned gpio);
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// GPIO_FSEL_T rp1_gpio_get_fsel(void *priv, unsigned gpio);
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// void rp1_gpio_set_fsel(void *priv, unsigned gpio, const GPIO_FSEL_T func);
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// int rp1_gpio_get_level(void *priv, unsigned gpio);
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// void rp1_gpio_set_drive(void *priv, unsigned gpio, GPIO_DRIVE_T drv);
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// void rp1_gpio_set_pull(void *priv, unsigned gpio, GPIO_PULL_T pull);
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// GPIO_PULL_T rp1_gpio_get_pull(void *priv, unsigned gpio);
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// GPIO_DRIVE_T rp1_gpio_get_drive(void *priv, unsigned gpio);
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// const char *rp1_gpio_get_name(void *priv, unsigned gpio);
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// const char *rp1_gpio_get_fsel_name(void *priv, unsigned gpio, GPIO_FSEL_T fsel);
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// void *rp1_gpio_create_instance(const GPIO_CHIP_T *chip, const char *dtnode);
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// int rp1_gpio_count(void *priv);
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// void *rp1_gpio_probe_instance(void *priv, volatile uint32_t *base);
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// };
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