RASCSI/hw/rascsi_zero_1p0/rascsi_zero.pro

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Squashed commit of the following: commit 4ae273ccbd3e2b9bfda6426a9c1f71844b48b2d9 Author: akuker <34318535+akuker@users.noreply.github.com> Date: Sun Dec 19 22:30:22 2021 -0600 Loopback tester pcb (#545) commit 46c5c1966f36841419df7c3337990ac941de3c85 Author: akuker <34318535+akuker@users.noreply.github.com> Date: Sun Dec 19 22:29:59 2021 -0600 RaSCSI Zero version 1.0 (#546) commit d09df31d67de3470ef4ed3fc74b40da1b181c0bb Author: Daniel Markstedt <markstedt@gmail.com> Date: Sun Dec 19 20:25:23 2021 -0800 Remove redundant code from OLED script (#547) commit d8828da6909a8b87e54f21aada20758607a2a67a Author: akuker <34318535+akuker@users.noreply.github.com> Date: Sun Dec 19 21:02:50 2021 -0600 Added list of sponsors commit bcd7e8396d945f5a051e01080354d3ac7ba63704 Author: Daniel Markstedt <markstedt@gmail.com> Date: Sun Dec 19 15:51:45 2021 -0800 Second attempt at properly creating the manpage dir (#542) commit c887edfc8c9956aa9dcac3764abe6cef16ffb596 Author: Daniel Markstedt <markstedt@gmail.com> Date: Sun Dec 19 15:50:03 2021 -0800 Remove special elevated privileges for the Web Interface (#536) * Use the pi_shutdown method to restart the rascsi service * Use the pi_shutdown method to restart the rascsi service * Remove modifications to sudoers no longer needed * Introduce sleeps attempting to connect to socket; reduce overall number of retries * Remove systemd helped methods and the functionality that depends on it * Attempts to speed up splash code * Remove unneccessary verbosity * Attempt to optimize service definition commit 801aebfb96e968a3bef1575b0301db4bd7625a35 Author: Daniel Markstedt <markstedt@gmail.com> Date: Sun Dec 19 15:47:22 2021 -0800 More readable message when downloading a file (#531) commit 29cf58288f228fe235b7d6fe2f0dd5852cf9a411 Author: Daniel Markstedt <markstedt@gmail.com> Date: Sun Dec 19 15:47:03 2021 -0800 Add a warning notice when ejecting removable media (#526) commit 7efa89523905a6985bea261f1dcf078ec76faf27 Author: Daniel Markstedt <markstedt@gmail.com> Date: Sun Dec 19 15:46:22 2021 -0800 Unzip zipfiles before storing to iso (#525) * Unzip zipfiles before storing to iso * Add helptext * Skip unzip for MacZip format * Should not be an fstring commit 39bc485671fa5163c6fc87860eed53b2966637ca Author: Daniel Markstedt <markstedt@gmail.com> Date: Sun Dec 19 15:28:22 2021 -0800 Add pip3 to global dependencies; remove duplicates from monitor_rascs… (#523) * Add pip3 to global dependencies; remove duplicates from monitor_rascsi dependencies * Cleanup
2021-12-20 09:25:28 +00:00
update=1/7/2021 8:29:52 AM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=empty.kicad_wks
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=39
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.127
MinViaDiameter=0.45
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.15
TrackWidth3=0.2
TrackWidth4=0.25
TrackWidth5=0.4
TrackWidth6=0.5
ViaDiameter1=0.8
ViaDrill1=0.4
ViaDiameter2=0.5
ViaDrill2=0.25
ViaDiameter3=0.8
ViaDrill3=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
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[pcbnew/Layer.In25.Cu]
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[pcbnew/Layer.B.Cu]
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Type=0
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[pcbnew/Layer.B.Adhes]
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[pcbnew/Layer.B.Paste]
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[pcbnew/Netclasses]
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Clearance=0.127
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dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25