Basic data capture works

This commit is contained in:
akuker 2020-07-18 13:34:29 -05:00
parent 3fb3ee7d7f
commit efa01e1e10
5 changed files with 551 additions and 206 deletions

View File

@ -43,7 +43,14 @@
// Disk
//
//===========================================================================
//#define DISK_LOG
#ifndef DISK_LOG
#define DISK_LOG
#endif // DISK_LOG
#ifndef RASCSI
#define RASCSI
#endif // RASCSI
#ifdef RASCSI
#define BENDER_SIGNATURE "RaSCSI"
@ -6324,9 +6331,7 @@ BUS::phase_t FASTCALL SASIDEV::Process()
// For the monitor tool, we shouldn't need to reset. We're just logging information
// Reset
if (ctrl.bus->GetRST()) {
#if defined(DISK_LOG)
spdlog::info( "RESET signal received");
#endif // DISK_LOG
// Reset the controller
Reset();
@ -6394,19 +6399,17 @@ void FASTCALL SASIDEV::BusFree()
// Phase change
if (ctrl.phase != BUS::busfree) {
#if defined(DISK_LOG)
spdlog::info( "Bus free phase");
#endif // DISK_LOG
// Phase Setting
ctrl.phase = BUS::busfree;
// Set Signal lines
ctrl.bus->SetREQ(FALSE);
ctrl.bus->SetMSG(FALSE);
ctrl.bus->SetCD(FALSE);
ctrl.bus->SetIO(FALSE);
ctrl.bus->SetBSY(FALSE);
////////////// // Set Signal lines
////////////// ctrl.bus->SetREQ(FALSE);
////////////// ctrl.bus->SetMSG(FALSE);
////////////// ctrl.bus->SetCD(FALSE);
////////////// ctrl.bus->SetIO(FALSE);
////////////// ctrl.bus->SetBSY(FALSE);
// Initialize status and message
ctrl.status = 0x00;
@ -6444,16 +6447,16 @@ void FASTCALL SASIDEV::Selection()
return;
}
#if defined(DISK_LOG)
spdlog::info(
"Selection Phase ID=%d (with device)", ctrl.id);
#endif // DISK_LOG
// Wait for this monitor target to assert the selection
// before moving on to the selection phase.
if(ctrl.bus->GetBSY())
{
// Phase change
ctrl.phase = BUS::selection;
spdlog::trace(
"[ID %d] Selection Phase (with device)", ctrl.id);
}
// Phase change
ctrl.phase = BUS::selection;
// Raiase BSY and respond
ctrl.bus->SetBSY(TRUE);
return;
}
@ -6481,16 +6484,24 @@ void FASTCALL SASIDEV::Command()
if (ctrl.phase != BUS::command) {
#if defined(DISK_LOG)
spdlog::info( "Command Phase");
spdlog::trace( "[ID %d] Moving to command Phase", ctrl.id);
#endif // DISK_LOG
// Phase Setting
ctrl.phase = BUS::command;
// Signal line operated by the target
ctrl.bus->SetMSG(FALSE);
ctrl.bus->SetCD(TRUE);
ctrl.bus->SetIO(FALSE);
////////// // Signal line operated by the target
////////// ctrl.bus->SetMSG(FALSE);
////////// ctrl.bus->SetCD(TRUE);
////////// ctrl.bus->SetIO(FALSE);
// Wait until target sets the following condition:
// MSG = FALSE
// CD = TRUE
// IO = FALSE
if (ctrl.bus->GetMSG() || !ctrl.bus->GetCD() || ctrl.bus->GetIO()) {
return;
}
// Data transfer is 6 bytes x 1 block
ctrl.offset = 0;
@ -7903,7 +7914,7 @@ void FASTCALL SASIDEV::FlushUnit()
}
}
#ifdef DISK_LOG
#if 0
//---------------------------------------------------------------------------
//
// Get the current phase as a string
@ -8016,9 +8027,7 @@ BUS::phase_t FASTCALL SCSIDEV::Process()
// Reset
if (ctrl.bus->GetRST()) {
#if defined(DISK_LOG)
spdlog::info( "RESET信号受信");
#endif // DISK_LOG
spdlog::info( "RESET phase");
// Reset the controller
Reset();
@ -8028,6 +8037,7 @@ BUS::phase_t FASTCALL SCSIDEV::Process()
return ctrl.phase;
}
// spdlog::trace("ID {} in phase {}",ctrl.id,ctrl.phase);
// Phase processing
switch (ctrl.phase) {
// Bus free phase
@ -8104,12 +8114,13 @@ void FASTCALL SCSIDEV::BusFree()
// Phase setting
ctrl.phase = BUS::busfree;
// Signal line
ctrl.bus->SetREQ(FALSE);
ctrl.bus->SetMSG(FALSE);
ctrl.bus->SetCD(FALSE);
ctrl.bus->SetIO(FALSE);
ctrl.bus->SetBSY(FALSE);
////////// // Signal line
// We shouldn't be setting ANYTHING
////////// ctrl.bus->SetREQ(FALSE);
////////// ctrl.bus->SetMSG(FALSE);
////////// ctrl.bus->SetCD(FALSE);
////////// ctrl.bus->SetIO(FALSE);
////////// ctrl.bus->SetBSY(FALSE);
// Initialize status and message
ctrl.status = 0x00;
@ -8142,24 +8153,30 @@ void FASTCALL SCSIDEV::Selection()
// invalid if IDs do not match
id = 1 << ctrl.id;
if ((ctrl.bus->GetDAT() & id) == 0) {
spdlog::trace("[ID {}] ID doesn't match {}",ctrl.id,id);
return;
}
// End if there is no valid unit
if (!HasUnit()) {
spdlog::trace("[ID {}] No unit attached",ctrl.id);
return;
}
#if defined(DISK_LOG)
spdlog::info(
"Selection Phase ID=%d (with device)", ctrl.id);
#endif // DISK_LOG
ctrl.phase = BUS::selection;
// Phase setting
ctrl.phase = BUS::selection;
// Wait for this monitor target to assert the selection
// before moving on to the selection phase.
if(ctrl.bus->GetBSY())
{
// Phase change
spdlog::trace(
"[ID {} Selection Phase (with device)", ctrl.id);
}
else{
spdlog::trace("[ID {}] Selection phase", ctrl.id);
}
// Raise BSY and respond
ctrl.bus->SetBSY(TRUE);
return;
}

View File

@ -65,7 +65,7 @@ DWORD bcm_host_get_peripheral_address(void)
char buf[1024];
size_t len = sizeof(buf);
DWORD address;
if (sysctlbyname("hw.model", buf, &len, NULL, 0) ||
strstr(buf, "ARM1176JZ-S") != buf) {
// Failed to get CPU model || Not BCM2835
@ -88,7 +88,7 @@ extern uint32_t RPi_IO_Base_Addr;
// Core frequency
extern uint32_t RPi_Core_Freq;
#ifdef USE_SEL_EVENT_ENABLE
#ifdef USE_SEL_EVENT_ENABLE
//---------------------------------------------------------------------------
//
// Interrupt control function
@ -460,6 +460,7 @@ void FASTCALL GPIOBUS::Reset()
SetMode(PIN_SEL, IN);
SetMode(PIN_ATN, IN);
SetMode(PIN_ACK, IN);
printf("ACK is set to IN\n");
SetMode(PIN_RST, IN);
// Set data bus signals to input
@ -488,6 +489,7 @@ void FASTCALL GPIOBUS::Reset()
SetControl(PIN_IND, IND_OUT);
SetMode(PIN_SEL, OUT);
SetMode(PIN_ATN, OUT);
printf("ACK is set to OUT\n");
SetMode(PIN_ACK, OUT);
SetMode(PIN_RST, OUT);
@ -508,6 +510,8 @@ void FASTCALL GPIOBUS::Reset()
signals = 0;
}
static DWORD high_bits = 0x0;
static DWORD low_bits = 0xFFFFFFFF;
//---------------------------------------------------------------------------
//
// Bus signal acquisition
@ -517,11 +521,22 @@ DWORD FASTCALL GPIOBUS::Aquire()
{
signals = *level;
DWORD prev_high = high_bits;
DWORD prev_low = low_bits;
high_bits |= signals;
low_bits &= signals;
if ((high_bits != prev_high) || (low_bits != prev_low))
{
printf(" %08lX %08lX\n",high_bits, low_bits);
}
#if SIGNAL_CONTROL_MODE < 2
// Invert if negative logic (internal processing is unified to positive logic)
signals = ~signals;
#endif // SIGNAL_CONTROL_MODE
return signals;
}
@ -552,36 +567,36 @@ BOOL FASTCALL GPIOBUS::GetBSY()
//---------------------------------------------------------------------------
void FASTCALL GPIOBUS::SetBSY(BOOL ast)
{
// Set BSY signal
SetSignal(PIN_BSY, ast);
if (actmode == TARGET) {
if (ast) {
// Turn on ACTIVE signal
SetControl(PIN_ACT, ACT_ON);
// Set Target signal to output
SetControl(PIN_TAD, TAD_OUT);
SetMode(PIN_BSY, OUT);
SetMode(PIN_MSG, OUT);
SetMode(PIN_CD, OUT);
SetMode(PIN_REQ, OUT);
SetMode(PIN_IO, OUT);
} else {
// Turn off the ACTIVE signal
SetControl(PIN_ACT, ACT_OFF);
// Set the target signal to input
SetControl(PIN_TAD, TAD_IN);
SetMode(PIN_BSY, IN);
SetMode(PIN_MSG, IN);
SetMode(PIN_CD, IN);
SetMode(PIN_REQ, IN);
SetMode(PIN_IO, IN);
}
}
// // Set BSY signal
// SetSignal(PIN_BSY, ast);
//
// if (actmode == TARGET) {
// if (ast) {
// // Turn on ACTIVE signal
// SetControl(PIN_ACT, ACT_ON);
//
// // Set Target signal to output
// SetControl(PIN_TAD, TAD_OUT);
//
// SetMode(PIN_BSY, OUT);
// SetMode(PIN_MSG, OUT);
// SetMode(PIN_CD, OUT);
// SetMode(PIN_REQ, OUT);
// SetMode(PIN_IO, OUT);
// } else {
// // Turn off the ACTIVE signal
// SetControl(PIN_ACT, ACT_OFF);
//
// // Set the target signal to input
// SetControl(PIN_TAD, TAD_IN);
//
// SetMode(PIN_BSY, IN);
// SetMode(PIN_MSG, IN);
// SetMode(PIN_CD, IN);
// SetMode(PIN_REQ, IN);
// SetMode(PIN_IO, IN);
// }
// }
}
//---------------------------------------------------------------------------
@ -601,13 +616,13 @@ BOOL FASTCALL GPIOBUS::GetSEL()
//---------------------------------------------------------------------------
void FASTCALL GPIOBUS::SetSEL(BOOL ast)
{
if (actmode == INITIATOR && ast) {
// Turn on ACTIVE signal
SetControl(PIN_ACT, ACT_ON);
}
// Set SEL signal
SetSignal(PIN_SEL, ast);
// if (actmode == INITIATOR && ast) {
// // Turn on ACTIVE signal
// SetControl(PIN_ACT, ACT_ON);
// }
//
// // Set SEL signal
// SetSignal(PIN_SEL, ast);
}
//---------------------------------------------------------------------------
@ -627,7 +642,7 @@ BOOL FASTCALL GPIOBUS::GetATN()
//---------------------------------------------------------------------------
void FASTCALL GPIOBUS::SetATN(BOOL ast)
{
SetSignal(PIN_ATN, ast);
// SetSignal(PIN_ATN, ast);
}
//---------------------------------------------------------------------------
@ -647,7 +662,7 @@ BOOL FASTCALL GPIOBUS::GetACK()
//---------------------------------------------------------------------------
void FASTCALL GPIOBUS::SetACK(BOOL ast)
{
SetSignal(PIN_ACK, ast);
//SetSignal(PIN_ACK, ast);
}
//---------------------------------------------------------------------------
@ -667,7 +682,7 @@ BOOL FASTCALL GPIOBUS::GetRST()
//---------------------------------------------------------------------------
void FASTCALL GPIOBUS::SetRST(BOOL ast)
{
SetSignal(PIN_RST, ast);
//SetSignal(PIN_RST, ast);
}
//---------------------------------------------------------------------------
@ -687,7 +702,7 @@ BOOL FASTCALL GPIOBUS::GetMSG()
//---------------------------------------------------------------------------
void FASTCALL GPIOBUS::SetMSG(BOOL ast)
{
SetSignal(PIN_MSG, ast);
//SetSignal(PIN_MSG, ast);
}
//---------------------------------------------------------------------------
@ -707,7 +722,7 @@ BOOL FASTCALL GPIOBUS::GetCD()
//---------------------------------------------------------------------------
void FASTCALL GPIOBUS::SetCD(BOOL ast)
{
SetSignal(PIN_CD, ast);
//SetSignal(PIN_CD, ast);
}
//---------------------------------------------------------------------------
@ -805,7 +820,7 @@ BOOL FASTCALL GPIOBUS::GetREQ()
//---------------------------------------------------------------------------
void FASTCALL GPIOBUS::SetREQ(BOOL ast)
{
SetSignal(PIN_REQ, ast);
// SetSignal(PIN_REQ, ast);
}
//---------------------------------------------------------------------------
@ -839,36 +854,36 @@ BYTE FASTCALL GPIOBUS::GetDAT()
void FASTCALL GPIOBUS::SetDAT(BYTE dat)
{
// Write to port
#if SIGNAL_CONTROL_MODE == 0
DWORD fsel;
fsel = gpfsel[0];
fsel &= tblDatMsk[0][dat];
fsel |= tblDatSet[0][dat];
if (fsel != gpfsel[0]) {
gpfsel[0] = fsel;
gpio[GPIO_FSEL_0] = fsel;
}
fsel = gpfsel[1];
fsel &= tblDatMsk[1][dat];
fsel |= tblDatSet[1][dat];
if (fsel != gpfsel[1]) {
gpfsel[1] = fsel;
gpio[GPIO_FSEL_1] = fsel;
}
fsel = gpfsel[2];
fsel &= tblDatMsk[2][dat];
fsel |= tblDatSet[2][dat];
if (fsel != gpfsel[2]) {
gpfsel[2] = fsel;
gpio[GPIO_FSEL_2] = fsel;
}
#else
gpio[GPIO_CLR_0] = tblDatMsk[dat];
gpio[GPIO_SET_0] = tblDatSet[dat];
#endif // SIGNAL_CONTROL_MODE
//#if SIGNAL_CONTROL_MODE == 0
// DWORD fsel;
//
// fsel = gpfsel[0];
// fsel &= tblDatMsk[0][dat];
// fsel |= tblDatSet[0][dat];
// if (fsel != gpfsel[0]) {
// gpfsel[0] = fsel;
// gpio[GPIO_FSEL_0] = fsel;
// }
//
// fsel = gpfsel[1];
// fsel &= tblDatMsk[1][dat];
// fsel |= tblDatSet[1][dat];
// if (fsel != gpfsel[1]) {
// gpfsel[1] = fsel;
// gpio[GPIO_FSEL_1] = fsel;
// }
//
// fsel = gpfsel[2];
// fsel &= tblDatMsk[2][dat];
// fsel |= tblDatSet[2][dat];
// if (fsel != gpfsel[2]) {
// gpfsel[2] = fsel;
// gpio[GPIO_FSEL_2] = fsel;
// }
//#else
// gpio[GPIO_CLR_0] = tblDatMsk[dat];
// gpio[GPIO_SET_0] = tblDatSet[dat];
//#endif // SIGNAL_CONTROL_MODE
}
//---------------------------------------------------------------------------
@ -1155,7 +1170,7 @@ int FASTCALL GPIOBUS::SendHandShake(BYTE *buf, int count)
}
// Already waiting for REQ assertion
// Assert the ACK signal
SetSignal(PIN_ACK, ON);
@ -1399,7 +1414,7 @@ void FASTCALL GPIOBUS::SetMode(int pin, int mode)
gpio[index] = data;
gpfsel[index] = data;
}
//---------------------------------------------------------------------------
//
// Get input signal value
@ -1409,7 +1424,7 @@ BOOL FASTCALL GPIOBUS::GetSignal(int pin)
{
return (signals >> pin) & 1;
}
//---------------------------------------------------------------------------
//
// Set output signal value

View File

@ -480,6 +480,8 @@ public:
void FASTCALL SetIO(BOOL ast);
// Set IO signal
void FASTCALL SetAct(BOOL ast) { PinSetSignal(PIN_ACT, ast);}
BOOL FASTCALL GetREQ();
// Get REQ signal
void FASTCALL SetREQ(BOOL ast);

View File

@ -12,6 +12,10 @@
#if !defined(log_h)
#define log_h
#define LOGINFO(...) \
do{char buf[256]; snprintf(buf, 256,__VA_ARGS__); spdlog::info(buf);}while(0)
//===========================================================================
//
// ログ

View File

@ -16,6 +16,8 @@
#include "disk.h"
#include "gpiobus.h"
#include "spdlog/spdlog.h"
//#include <sys/timespec_util.h>
#include <sys/time.h>
//---------------------------------------------------------------------------
//
@ -47,6 +49,23 @@ int monsocket; // Monitor Socket
pthread_t monthread; // Monitor Thread
static void *MonThread(void *param);
#endif // BAREMETAL
typedef struct data_capture{
DWORD data;
timeval timestamp;
} data_capture_t;
#define MAX_BUFF_SIZE 1000000
data_capture data_buffer[MAX_BUFF_SIZE];
int data_idx = 0;
#define SECONDS_1 (1000 * 1000)
#define SECONDS_3 (3 * 1000 * 1000)
#define WAIT_FOR_EQUAL(x,y,timeout) { DWORD now = SysTimer::GetTimerLow(); while ((SysTimer::GetTimerLow() - now) < timeout) { bus->Aquire();if (x == y) {break;}}}
#ifndef BAREMETAL
//---------------------------------------------------------------------------
@ -181,6 +200,149 @@ BOOL Init()
return TRUE;
}
#define PIN_ACT 4 // ACTIVE
#define PIN_ENB 5 // ENABLE
#define PIN_IND -1 // INITIATOR CTRL DIRECTION
#define PIN_TAD -1 // TARGET CTRL DIRECTION
#define PIN_DTD -1 // DATA DIRECTION
// Control signal output logic
#define ACT_ON TRUE // ACTIVE SIGNAL ON
#define ENB_ON TRUE // ENABLE SIGNAL ON
#define IND_IN FALSE // INITIATOR SIGNAL INPUT
#define TAD_IN FALSE // TARGET SIGNAL INPUT
#define DTD_IN TRUE // DATA SIGNAL INPUT
// SCSI signal pin assignment
#define PIN_DT0 10 // Data 0
#define PIN_DT1 11 // Data 1
#define PIN_DT2 12 // Data 2
#define PIN_DT3 13 // Data 3
#define PIN_DT4 14 // Data 4
#define PIN_DT5 15 // Data 5
#define PIN_DT6 16 // Data 6
#define PIN_DT7 17 // Data 7
#define PIN_DP 18 // Data parity
#define PIN_ATN 19 // ATN
#define PIN_RST 20 // RST
#define PIN_ACK 21 // ACK
#define PIN_REQ 22 // REQ
#define PIN_MSG 23 // MSG
#define PIN_CD 24 // CD
#define PIN_IO 25 // IO
#define PIN_BSY 26 // BSY
#define PIN_SEL 27 // SEL
BOOL get_pin_value(DWORD data, int pin)
{
return (data >> pin) & 1;
}
BYTE get_data_field(DWORD data)
{
DWORD data_out;
data_out =
((data >> (PIN_DT0 - 0)) & (1 << 0)) |
((data >> (PIN_DT1 - 1)) & (1 << 1)) |
((data >> (PIN_DT2 - 2)) & (1 << 2)) |
((data >> (PIN_DT3 - 3)) & (1 << 3)) |
((data >> (PIN_DT4 - 4)) & (1 << 4)) |
((data >> (PIN_DT5 - 5)) & (1 << 5)) |
((data >> (PIN_DT6 - 6)) & (1 << 6)) |
((data >> (PIN_DT7 - 7)) & (1 << 7));
return (BYTE)data_out;
}
int pin_nums[] = {PIN_BSY,PIN_SEL,PIN_CD,PIN_IO,PIN_MSG,PIN_REQ,PIN_ACK,PIN_ATN,PIN_RST,PIN_DT0};
char* pin_names[] = {"BSY","SEL","CD","IO","MSG","REQ","ACK","ATN","RST","DAT"};
void dump_data()
{
char outstr[1024];
int i = 0;
timeval time_diff;
FILE *fp;
timeval start_time = data_buffer[0].timestamp;
fp = fopen("log.txt","w");
fprintf(fp, "idx\traw\ttimestamp\tBSY\tSEL\tC/D\tI/O\tMSG\tREQ\tACK\tATN\tRST\tData..\n");
while(i < data_idx)
{
timersub(&(data_buffer[i].timestamp), &start_time, &time_diff);
//timediff = difftime(data_buffer[i].timestamp, start_time);
fprintf(fp, "%d\t%08lX\t%d:%d\t",data_idx, data_buffer[i].data, time_diff.tv_sec, time_diff.tv_usec);
fprintf(fp, "%d\t", get_pin_value(data_buffer[i].data, PIN_BSY));
fprintf(fp, "%d\t", get_pin_value(data_buffer[i].data, PIN_SEL));
fprintf(fp, "%d\t", get_pin_value(data_buffer[i].data, PIN_CD));
fprintf(fp, "%d\t", get_pin_value(data_buffer[i].data, PIN_IO));
fprintf(fp, "%d\t", get_pin_value(data_buffer[i].data, PIN_MSG));
fprintf(fp, "%d\t", get_pin_value(data_buffer[i].data, PIN_REQ));
fprintf(fp, "%d\t", get_pin_value(data_buffer[i].data, PIN_ACK));
fprintf(fp, "%d\t", get_pin_value(data_buffer[i].data, PIN_ATN));
fprintf(fp, "%d\t", get_pin_value(data_buffer[i].data, PIN_RST));
fprintf(fp, "%02X\t", get_data_field(data_buffer[i].data));
fprintf(fp, "\n");
i++;
}
fclose(fp);
i=0;
printf("Creating timing_drawer.txt\n");
fp = fopen("timing_drawer.txt","w");
while(i < data_idx)
{
timersub(&(data_buffer[i].timestamp), &start_time, &time_diff);
//timediff = difftime(data_buffer[i].timestamp, start_time);
fprintf(fp, "TIME=%d:%d;", time_diff.tv_sec, time_diff.tv_usec);
fprintf(fp, "BSY=%d;", get_pin_value(data_buffer[i].data, PIN_BSY));
fprintf(fp, "SEL=%d;", get_pin_value(data_buffer[i].data, PIN_SEL));
fprintf(fp, "CD=%d;", get_pin_value(data_buffer[i].data, PIN_CD));
fprintf(fp, "IO=%d;", get_pin_value(data_buffer[i].data, PIN_IO));
fprintf(fp, "MSG=%d;", get_pin_value(data_buffer[i].data, PIN_MSG));
fprintf(fp, "REQ=%d;", get_pin_value(data_buffer[i].data, PIN_REQ));
fprintf(fp, "ACK=%d;", get_pin_value(data_buffer[i].data, PIN_ACK));
fprintf(fp, "ATN=%d;", get_pin_value(data_buffer[i].data, PIN_ATN));
fprintf(fp, "RST=%d;", get_pin_value(data_buffer[i].data, PIN_RST));
fprintf(fp, "DATA=%02X.", get_data_field(data_buffer[i].data));
fprintf(fp, "\n");
i++;
}
fclose(fp);
//
// fp = fopen("log2.txt","w");
//
// for(int pin=0; pin < ARRAY_SIZE(pin_names); pin++)
// {
// i=0;
// while(i < data_idx)
// {
// char this_point = ((get_pin_value(data_buffer[i].data), pin_nums[pin]) == TRUE) ? "-", "_";
// fprintf(fp, this_point)
// }
//
//
//
//
// }
}
//---------------------------------------------------------------------------
//
// Cleanup
@ -190,6 +352,14 @@ void Cleanup()
{
int i;
printf("In cleanup....\n");
dump_data();
// Delete the disks
for (i = 0; i < CtrlMax * UnitNum; i++) {
if (disk[i]) {
@ -971,6 +1141,8 @@ next:
}
#endif // BAREMETAL
//---------------------------------------------------------------------------
//
// Main processing
@ -986,20 +1158,23 @@ int startrascsi(void)
int main(int argc, char* argv[])
{
#endif // BAREMETAL
int i;
DWORD prev_sample = 0xFFFFFFFF;
DWORD this_sample = 0;
//int i;
int ret;
int actid;
DWORD now;
BUS::phase_t phase;
BYTE data;
// int actid;
//DWORD now;
//BUS::phase_t phase;
// BYTE data;
#ifndef BAREMETAL
struct sched_param schparam;
#endif // BAREMETAL
spdlog::set_level(spdlog::level::trace);
spdlog::trace("Entering the function with %d arguments", argc);
spdlog::trace("Entering the function with {0:x}{1:X} arguments", argc,20);
// Output the Banner
Banner(argc, argv);
memset(data_buffer,0,sizeof(data_buffer));
// Initialize
ret = 0;
@ -1040,103 +1215,235 @@ int main(int argc, char* argv[])
// Start execution
running = TRUE;
bus->SetAct(FALSE);
spdlog::trace("Going into running mode {}", 1);
// Main Loop
while (running) {
// Work initialization
actid = -1;
phase = BUS::busfree;
this_sample = bus->Aquire();
#ifdef USE_SEL_EVENT_ENABLE
// SEL signal polling
if (bus->PollSelectEvent() < 0) {
// Stop on interrupt
if (errno == EINTR) {
break;
}
continue;
if(this_sample != prev_sample)
{
//printf("%d Sample %08lX\n", data_idx, this_sample);
data_buffer[data_idx].data = this_sample;
(void)gettimeofday(&(data_buffer[data_idx].timestamp), NULL);
data_idx = (data_idx + 1) % MAX_BUFF_SIZE;
prev_sample = this_sample;
}
// Get the bus
bus->Aquire();
#else
bus->Aquire();
if (!bus->GetSEL()) {
#if !defined(BAREMETAL)
usleep(0);
#endif // !BAREMETAL
continue;
}
#endif // USE_SEL_EVENT_ENABLE
// Wait until BSY is released as there is a possibility for the
// initiator to assert it while setting the ID (for up to 3 seconds)
if (bus->GetBSY()) {
now = SysTimer::GetTimerLow();
while ((SysTimer::GetTimerLow() - now) < 3 * 1000 * 1000) {
bus->Aquire();
if (!bus->GetBSY()) {
break;
}
}
}
// Stop because it the bus is busy or another device responded
if (bus->GetBSY() || !bus->GetSEL()) {
continue;
}
// Notify all controllers
data = bus->GetDAT();
for (i = 0; i < CtrlMax; i++) {
if (!ctrl[i] || (data & (1 << i)) == 0) {
continue;
}
// Find the target that has moved to the selection phase
if (ctrl[i]->Process() == BUS::selection) {
// Get the target ID
actid = i;
// Bus Selection phase
phase = BUS::selection;
break;
}
}
// Return to bus monitoring if the selection phase has not started
if (phase != BUS::selection) {
continue;
}
// Start target device
active = TRUE;
#if !defined(USE_SEL_EVENT_ENABLE) && !defined(BAREMETAL)
// Scheduling policy setting (highest priority)
schparam.sched_priority = sched_get_priority_max(SCHED_FIFO);
sched_setscheduler(0, SCHED_FIFO, &schparam);
#endif // !USE_SEL_EVENT_ENABLE && !BAREMETAL
// Loop until the bus is free
while (running) {
// Target drive
phase = ctrl[actid]->Process();
// End when the bus is free
if (phase == BUS::busfree) {
break;
}
}
#if !defined(USE_SEL_EVENT_ENABLE) && !defined(BAREMETAL)
// Set the scheduling priority back to normal
schparam.sched_priority = 0;
sched_setscheduler(0, SCHED_OTHER, &schparam);
#endif // !USE_SEL_EVENT_ENABLE && !BAREMETAL
// End the target travel
active = FALSE;
continue;
////////
//////// // Target sending data
//////// if(!bus->GetIO() && bus->GetREQ() && bus->GetACK())
//////// {
//////// BYTE data = bus->GetDAT();
//////// printf("+%02X ",data);
////////
////////
////////
//////// DWORD now = SysTimer::GetTimerLow();
//////// while ((SysTimer::GetTimerLow() - now) < SECONDS_1/100)
//////// {
//////// bus->Aquire();
//////// if (bus->GetACK() == FALSE) {
//////// break;
//////// }
//////// }
////////
//////// if(bus->GetACK() != FALSE)
//////// {
//////// spdlog::warn("got an invalid req/ack sequence for target sending data");
//////// }
//////// }
////////
////////
////////
//////// if(bus->GetIO() && bus->GetREQ() && !bus->GetACK())
//////// {
//////// BYTE data = bus->GetDAT();
//////// printf("-%02X ",data);
////////
////////
//////// DWORD now = SysTimer::GetTimerLow();
//////// while ((SysTimer::GetTimerLow() - now) < SECONDS_1/100)
//////// {
//////// bus->Aquire();
//////// if (bus->GetREQ() == FALSE) {
//////// break;
//////// }
//////// }
////////
//////// if(bus->GetREQ() != TRUE)
//////// {
//////// spdlog::warn("REQ didn't de-assert when I wanted it to.");
//////// }
////////
////////
//////// }
////////
//////// continue;
////////
//////// // Wait until BSY is released as there is a possibility for the
//////// // initiator to assert it while setting the ID (for up to 3 seconds)
//////// if (bus->GetSEL() ) {
//////// BYTE data = bus->GetDAT();
//////// printf("SEL is asserted. Data: %02X, BSY: %d, SEL %d\n", data, bus->GetBSY(), bus->GetSEL());
//////// now = SysTimer::GetTimerLow();
//////// while ((SysTimer::GetTimerLow() - now) < 3 * 1000 * 1000) {
//////// bus->Aquire();
//////// if (!bus->GetSEL()) {
//////// printf("SEL is clear. Data: %02X, BSY: %d, SEL %d\n", data, bus->GetBSY(), bus->GetSEL());
//////// break;
//////// }
//////// }
//////// }
//////// else{
////////
//////// continue;
//////// }
////////// spdlog::trace("Busy: {}",bus->GetBSY());
////////
////////
//////// // For monitor mode, we just want to make sure the initiator
//////// // released the BSY signal within 3 seconds. If it hasn't
//////// // the initiator is misbehaving
////////// if (bus->GetBSY()) {
////////// spdlog::warn("The initiator (%d) did not release the BSY signal after 3 seconds", bus->GetDAT());
////////// continue;
////////// }
////////
//////////////////////
////////////////////// // Stop because it the bus is busy or another device responded
////////////////////// if (bus->GetBSY() || !bus->GetSEL()) {
////////////////////// continue;
////////////////////// }
//
// // Notify all controllers
// data = bus->GetDAT();
//// spdlog::trace("Data is {x}",data);
// for (i = 0; i < CtrlMax; i++) {
// if (!ctrl[i] || (data & (1 << i)) == 0) {
// continue;
// }
//// spdlog::trace("Found an active controller! Let's do some selection {}", i);
// // Find the target that has moved to the selection phase
// if (ctrl[i]->Process() == BUS::selection) {
// // Get the target ID
// actid = i;
//
// // Bus Selection phase
// phase = BUS::selection;
// break;
// }
// }
//
// // Return to bus monitoring if the selection phase has not started
// if (phase != BUS::selection) {
// continue;
// }
//
// // Start target device
// active = TRUE;
// spdlog::trace("Found a target device {} ID:{}",actid, ctrl[actid]->GetID());
//
//#if !defined(USE_SEL_EVENT_ENABLE) && !defined(BAREMETAL)
// // Scheduling policy setting (highest priority)
// schparam.sched_priority = sched_get_priority_max(SCHED_FIFO);
// sched_setscheduler(0, SCHED_FIFO, &schparam);
//#endif // !USE_SEL_EVENT_ENABLE && !BAREMETAL
//
// // Loop until the bus is free
// while (running) {
// // Target drive
// phase = ctrl[actid]->Process();
//
// // End when the bus is free
// if (phase == BUS::busfree) {
// break;
// }
// }
//
//#if !defined(USE_SEL_EVENT_ENABLE) && !defined(BAREMETAL)
// // Set the scheduling priority back to normal
// schparam.sched_priority = 0;
// sched_setscheduler(0, SCHED_OTHER, &schparam);
//#endif // !USE_SEL_EVENT_ENABLE && !BAREMETAL
//
// // End the target travel
// active = FALSE;
}
err_exit: