mirror of
https://github.com/akuker/RASCSI.git
synced 2024-11-22 01:31:25 +00:00
08194af424
- Moved C++ code to cpp/ from src/raspberrypi - Related updates to Makefile, easyinstall.sh, and the github build rules - Removed the native X68k C code in src/x68k from the repo
107 lines
3.8 KiB
C++
107 lines
3.8 KiB
C++
//---------------------------------------------------------------------------
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//
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// SCSI Target Emulator RaSCSI Reloaded
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// for Raspberry Pi
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//
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// Copyright (C) 2022 akuker
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//
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// [ High resolution timer ]
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//
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//---------------------------------------------------------------------------
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#pragma once
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#include "systimer.h"
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#include <stdint.h>
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#include <string>
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//===========================================================================
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//
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// System timer
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//
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//===========================================================================
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class SysTimer_AllWinner : public PlatformSpecificTimer
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{
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public:
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// Default constructor
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SysTimer_AllWinner() = default;
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// Default destructor
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~SysTimer_AllWinner() override = default;
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// Initialization
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void Init() override;
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// Get system timer low byte
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uint32_t GetTimerLow() override;
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// Get system timer high byte
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uint32_t GetTimerHigh() override;
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// Sleep for N nanoseconds
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void SleepNsec(uint32_t nsec) override;
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// Sleep for N microseconds
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void SleepUsec(uint32_t usec) override;
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private:
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void enable_hs_timer();
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void disable_hs_timer();
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static const std::string dev_mem_filename;
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/* Reference: Allwinner H3 Datasheet, section 4.9.3 */
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static const uint32_t hs_timer_base_address = 0x01C60000;
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/* Note: Currently the high speed timer is NOT in the armbian
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* device tree. If it is ever added, this should be pulled
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* from there */
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struct sun8i_hsitimer_registers {
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/* 0x00 HS Timer IRQ Enabled Register */
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uint32_t hs_tmr_irq_en_reg;
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/* 0x04 HS Timer Status Register */
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uint32_t hs_tmr_irq_stat_reg;
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/* 0x08 Unused */
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uint32_t unused_08;
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/* 0x0C Unused */
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uint32_t unused_0C;
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/* 0x10 HS Timer Control Register */
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uint32_t hs_tmr_ctrl_reg;
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/* 0x14 HS Timer Interval Value Low Reg */
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uint32_t hs_tmr_intv_lo_reg;
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/* 0x18 HS Timer Interval Value High Register */
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uint32_t hs_tmr_intv_hi_reg;
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/* 0x1C HS Timer Current Value Low Register */
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uint32_t hs_tmr_curnt_lo_reg;
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/* 0x20 HS Timer Current Value High Register */
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uint32_t hs_tmr_curnt_hi_reg;
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};
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/* Constants for the HS Timer IRQ enable Register (section 4.9.4.1) */
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static const uint32_t HS_TMR_INTERUPT_ENB = (1 << 0);
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/* Constants for the HS Timer Control Register (section 4.9.4.3) */
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static const uint32_t HS_TMR_EN = (1 << 0);
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static const uint32_t HS_TMR_RELOAD = (1 << 1);
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static const uint32_t HS_TMR_CLK_PRE_SCALE_1 = (0 << 4);
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static const uint32_t HS_TMR_CLK_PRE_SCALE_2 = (1 << 4);
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static const uint32_t HS_TMR_CLK_PRE_SCALE_4 = (2 << 4);
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static const uint32_t HS_TMR_CLK_PRE_SCALE_8 = (3 << 4);
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static const uint32_t HS_TMR_CLK_PRE_SCALE_16 = (4 << 4); // NOSONAR This matches the datasheet
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static const uint32_t HS_TMR_MODE_SINGLE = (1 << 7);
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static const uint32_t HS_TMR_TEST_MODE = (1 << 31);
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struct sun8i_hsitimer_registers *hsitimer_regs;
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/* Reference: Allwinner H3 Datasheet, section 4.3.4 */
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static const uint32_t system_bus_base_address = 0x01C20000;
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struct sun8i_sysbus_registers {
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uint32_t pad_00_5C[(0x60 / sizeof(uint32_t))]; //NOSONAR c-style array used for padding
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/* 0x0060 Bus Clock Gating Register 0 */
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uint32_t bus_clk_gating_reg0;
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uint32_t pad_64_2C0[((0x2C0 - 0x64) / sizeof(uint32_t))]; //NOSONAR c-style array used for padding
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/* 0x2C0 Bus Software Reset Register 0 */
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uint32_t bus_soft_rst_reg0;
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};
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/* Bit associated with the HS Timer */
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static const uint32_t BUS_CLK_GATING_REG0_HSTMR = 19;
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static const uint32_t BUS_SOFT_RST_REG0_HSTMR = 19;
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struct sun8i_sysbus_registers *sysbus_regs;
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};
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