mirror of
https://github.com/akuker/RASCSI.git
synced 2024-11-22 16:33:17 +00:00
1418 lines
30 KiB
C++
1418 lines
30 KiB
C++
//---------------------------------------------------------------------------
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//
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// SCSI Target Emulator RaSCSI Reloaded
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// for Raspberry Pi
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//
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// Powered by XM6 TypeG Technology.
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// Copyright (C) 2016-2020 GIMONS
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//
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// [ GPIO-SCSI bus ]
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//
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//---------------------------------------------------------------------------
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#include <sys/mman.h>
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#include <sys/ioctl.h>
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#include <sys/time.h>
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#include "hal/gpiobus.h"
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#include "hal/systimer.h"
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#include "shared/config.h"
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#include "shared/log.h"
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#include <array>
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#ifdef __linux__
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#include <sys/epoll.h>
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#endif
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using namespace std;
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#ifdef __linux__
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//---------------------------------------------------------------------------
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//
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// imported from bcm_host.c
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//
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//---------------------------------------------------------------------------
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static uint32_t get_dt_ranges(const char *filename, uint32_t offset)
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{
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uint32_t address = ~0;
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if (FILE *fp = fopen(filename, "rb"); fp) {
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fseek(fp, offset, SEEK_SET);
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if (array<uint8_t, 4> buf; fread(buf.data(), 1, buf.size(), fp) == buf.size()) {
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address = (int)buf[0] << 24 | (int)buf[1] << 16 | (int)buf[2] << 8 | (int)buf[3] << 0;
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}
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fclose(fp);
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}
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return address;
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}
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uint32_t bcm_host_get_peripheral_address()
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{
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uint32_t address = get_dt_ranges("/proc/device-tree/soc/ranges", 4);
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if (address == 0) {
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address = get_dt_ranges("/proc/device-tree/soc/ranges", 8);
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}
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address = (address == (uint32_t)~0) ? 0x20000000 : address;
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return address;
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}
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#endif
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#ifdef __NetBSD__
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// Assume the Raspberry Pi series and estimate the address from CPU
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uint32_t bcm_host_get_peripheral_address()
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{
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array<char, 1024> buf;
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size_t len = buf.size();
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uint32_t address;
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if (sysctlbyname("hw.model", buf.data(), &len, NULL, 0) ||
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strstr(buf, "ARM1176JZ-S") != buf.data()) {
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// Failed to get CPU model || Not BCM2835
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// use the address of BCM283[67]
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address = 0x3f000000;
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} else {
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// Use BCM2835 address
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address = 0x20000000;
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}
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printf("Peripheral address : 0x%lx\n", address);
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return address;
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}
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#endif
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bool GPIOBUS::Init(mode_e mode)
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{
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// Save operation mode
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actmode = mode;
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#if defined(__x86_64__) || defined(__X86__)
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return true;
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#else
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int i;
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#ifdef USE_SEL_EVENT_ENABLE
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epoll_event ev = {};
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#endif
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// Get the base address
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baseaddr = (uint32_t)bcm_host_get_peripheral_address();
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// Open /dev/mem
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int fd = open("/dev/mem", O_RDWR | O_SYNC);
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if (fd == -1) {
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LOGERROR("Error: Unable to open /dev/mem. Are you running as root?")
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return false;
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}
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// Map peripheral region memory
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void *map = mmap(NULL, 0x1000100, PROT_READ | PROT_WRITE, MAP_SHARED, fd, baseaddr);
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if (map == MAP_FAILED) {
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LOGERROR("Error: Unable to map memory")
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close(fd);
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return false;
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}
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// Determine the type of raspberry pi from the base address
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if (baseaddr == 0xfe000000) {
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rpitype = 4;
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} else if (baseaddr == 0x3f000000) {
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rpitype = 2;
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} else {
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rpitype = 1;
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}
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// GPIO
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gpio = (uint32_t *)map;
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gpio += GPIO_OFFSET / sizeof(uint32_t);
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level = &gpio[GPIO_LEV_0];
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// PADS
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pads = (uint32_t *)map;
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pads += PADS_OFFSET / sizeof(uint32_t);
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// System timer
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SysTimer::Init(
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(uint32_t *)map + SYST_OFFSET / sizeof(uint32_t),
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(uint32_t *)map + ARMT_OFFSET / sizeof(uint32_t));
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// Interrupt controller
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irpctl = (uint32_t *)map;
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irpctl += IRPT_OFFSET / sizeof(uint32_t);
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// Quad-A7 control
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qa7regs = (uint32_t *)map;
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qa7regs += QA7_OFFSET / sizeof(uint32_t);
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// Map GIC memory
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if (rpitype == 4) {
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map = mmap(NULL, 8192,
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PROT_READ | PROT_WRITE, MAP_SHARED, fd, ARM_GICD_BASE);
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if (map == MAP_FAILED) {
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close(fd);
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return false;
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}
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gicd = (uint32_t *)map;
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gicc = (uint32_t *)map;
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gicc += (ARM_GICC_BASE - ARM_GICD_BASE) / sizeof(uint32_t);
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} else {
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gicd = NULL;
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gicc = NULL;
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}
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close(fd);
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// Set Drive Strength to 16mA
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DrvConfig(7);
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// Set pull up/pull down
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#if SIGNAL_CONTROL_MODE == 0
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int pullmode = GPIO_PULLNONE;
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#elif SIGNAL_CONTROL_MODE == 1
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int pullmode = GPIO_PULLUP;
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#else
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int pullmode = GPIO_PULLDOWN;
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#endif
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// Initialize all signals
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for (i = 0; SignalTable[i] >= 0; i++) {
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int j = SignalTable[i];
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PinSetSignal(j, OFF);
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PinConfig(j, GPIO_INPUT);
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PullConfig(j, pullmode);
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}
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// Set control signals
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PinSetSignal(PIN_ACT, OFF);
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PinSetSignal(PIN_TAD, OFF);
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PinSetSignal(PIN_IND, OFF);
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PinSetSignal(PIN_DTD, OFF);
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PinConfig(PIN_ACT, GPIO_OUTPUT);
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PinConfig(PIN_TAD, GPIO_OUTPUT);
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PinConfig(PIN_IND, GPIO_OUTPUT);
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PinConfig(PIN_DTD, GPIO_OUTPUT);
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// Set the ENABLE signal
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// This is used to show that the application is running
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PinSetSignal(PIN_ENB, ENB_OFF);
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PinConfig(PIN_ENB, GPIO_OUTPUT);
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// GPFSEL backup
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gpfsel[0] = gpio[GPIO_FSEL_0];
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gpfsel[1] = gpio[GPIO_FSEL_1];
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gpfsel[2] = gpio[GPIO_FSEL_2];
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gpfsel[3] = gpio[GPIO_FSEL_3];
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// Initialize SEL signal interrupt
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#ifdef USE_SEL_EVENT_ENABLE
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// GPIO chip open
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fd = open("/dev/gpiochip0", 0);
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if (fd == -1) {
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LOGERROR("Unable to open /dev/gpiochip0. Is RaSCSI already running?")
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return false;
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}
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// Event request setting
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strcpy(selevreq.consumer_label, "RaSCSI");
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selevreq.lineoffset = PIN_SEL;
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selevreq.handleflags = GPIOHANDLE_REQUEST_INPUT;
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#if SIGNAL_CONTROL_MODE < 2
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selevreq.eventflags = GPIOEVENT_REQUEST_FALLING_EDGE;
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#else
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selevreq.eventflags = GPIOEVENT_REQUEST_RISING_EDGE;
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#endif // SIGNAL_CONTROL_MODE
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//Get event request
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if (ioctl(fd, GPIO_GET_LINEEVENT_IOCTL, &selevreq) == -1) {
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LOGERROR("Unable to register event request. Is RaSCSI already running?")
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close(fd);
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return false;
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}
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// Close GPIO chip file handle
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close(fd);
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// epoll initialization
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epfd = epoll_create(1);
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ev.events = EPOLLIN | EPOLLPRI;
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ev.data.fd = selevreq.fd;
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epoll_ctl(epfd, EPOLL_CTL_ADD, selevreq.fd, &ev);
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#else
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// Edge detection setting
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#if SIGNAL_CONTROL_MODE == 2
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gpio[GPIO_AREN_0] = 1 << PIN_SEL;
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#else
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gpio[GPIO_AFEN_0] = 1 << PIN_SEL;
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#endif // SIGNAL_CONTROL_MODE
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// Clear event
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gpio[GPIO_EDS_0] = 1 << PIN_SEL;
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// Register interrupt handler
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setIrqFuncAddress(IrqHandler);
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// GPIO interrupt setting
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if (rpitype == 4) {
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// GIC Invalid
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gicd[GICD_CTLR] = 0;
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// Route all interupts to core 0
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for (i = 0; i < 8; i++) {
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gicd[GICD_ICENABLER0 + i] = 0xffffffff;
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gicd[GICD_ICPENDR0 + i] = 0xffffffff;
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gicd[GICD_ICACTIVER0 + i] = 0xffffffff;
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}
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for (i = 0; i < 64; i++) {
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gicd[GICD_IPRIORITYR0 + i] = 0xa0a0a0a0;
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gicd[GICD_ITARGETSR0 + i] = 0x01010101;
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}
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// Set all interrupts as level triggers
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for (i = 0; i < 16; i++) {
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gicd[GICD_ICFGR0 + i] = 0;
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}
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// GIC Invalid
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gicd[GICD_CTLR] = 1;
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// Enable CPU interface for core 0
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gicc[GICC_PMR] = 0xf0;
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gicc[GICC_CTLR] = 1;
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// Enable interrupts
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gicd[GICD_ISENABLER0 + (GIC_GPIO_IRQ / 32)] =
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1 << (GIC_GPIO_IRQ % 32);
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} else {
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// Enable interrupts
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irpctl[IRPT_ENB_IRQ_2] = (1 << (GPIO_IRQ % 32));
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}
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#endif // USE_SEL_EVENT_ENABLE
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// Create work table
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MakeTable();
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// Finally, enable ENABLE
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// Show the user that this app is running
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SetControl(PIN_ENB, ENB_ON);
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return true;
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#endif // ifdef __x86_64__ || __X86__
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}
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void GPIOBUS::Cleanup()
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{
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#if defined(__x86_64__) || defined(__X86__)
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return;
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#else
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// Release SEL signal interrupt
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#ifdef USE_SEL_EVENT_ENABLE
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close(selevreq.fd);
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#endif // USE_SEL_EVENT_ENABLE
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// Set control signals
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PinSetSignal(PIN_ENB, OFF);
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PinSetSignal(PIN_ACT, OFF);
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PinSetSignal(PIN_TAD, OFF);
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PinSetSignal(PIN_IND, OFF);
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PinSetSignal(PIN_DTD, OFF);
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PinConfig(PIN_ACT, GPIO_INPUT);
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PinConfig(PIN_TAD, GPIO_INPUT);
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PinConfig(PIN_IND, GPIO_INPUT);
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PinConfig(PIN_DTD, GPIO_INPUT);
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// Initialize all signals
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for (int i = 0; SignalTable[i] >= 0; i++) {
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int pin = SignalTable[i];
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PinSetSignal(pin, OFF);
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PinConfig(pin, GPIO_INPUT);
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PullConfig(pin, GPIO_PULLNONE);
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}
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// Set drive strength back to 8mA
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DrvConfig(3);
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#endif // ifdef __x86_64__ || __X86__
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}
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void GPIOBUS::Reset()
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{
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#if defined(__x86_64__) || defined(__X86__)
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return;
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#else
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int i;
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int j;
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// Turn off active signal
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SetControl(PIN_ACT, ACT_OFF);
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// Set all signals to off
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for (i = 0;; i++) {
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j = SignalTable[i];
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if (j < 0) {
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break;
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}
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SetSignal(j, OFF);
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}
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if (actmode == mode_e::TARGET) {
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// Target mode
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// Set target signal to input
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SetControl(PIN_TAD, TAD_IN);
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SetMode(PIN_BSY, IN);
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SetMode(PIN_MSG, IN);
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SetMode(PIN_CD, IN);
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SetMode(PIN_REQ, IN);
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SetMode(PIN_IO, IN);
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// Set the initiator signal to input
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SetControl(PIN_IND, IND_IN);
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SetMode(PIN_SEL, IN);
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SetMode(PIN_ATN, IN);
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SetMode(PIN_ACK, IN);
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SetMode(PIN_RST, IN);
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// Set data bus signals to input
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SetControl(PIN_DTD, DTD_IN);
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SetMode(PIN_DT0, IN);
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SetMode(PIN_DT1, IN);
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SetMode(PIN_DT2, IN);
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SetMode(PIN_DT3, IN);
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SetMode(PIN_DT4, IN);
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SetMode(PIN_DT5, IN);
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SetMode(PIN_DT6, IN);
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SetMode(PIN_DT7, IN);
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SetMode(PIN_DP, IN);
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} else {
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// Initiator mode
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// Set target signal to input
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SetControl(PIN_TAD, TAD_IN);
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SetMode(PIN_BSY, IN);
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SetMode(PIN_MSG, IN);
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SetMode(PIN_CD, IN);
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SetMode(PIN_REQ, IN);
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SetMode(PIN_IO, IN);
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// Set the initiator signal to output
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SetControl(PIN_IND, IND_OUT);
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SetMode(PIN_SEL, OUT);
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SetMode(PIN_ATN, OUT);
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SetMode(PIN_ACK, OUT);
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SetMode(PIN_RST, OUT);
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// Set the data bus signals to output
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SetControl(PIN_DTD, DTD_OUT);
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SetMode(PIN_DT0, OUT);
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SetMode(PIN_DT1, OUT);
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SetMode(PIN_DT2, OUT);
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SetMode(PIN_DT3, OUT);
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SetMode(PIN_DT4, OUT);
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SetMode(PIN_DT5, OUT);
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SetMode(PIN_DT6, OUT);
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SetMode(PIN_DT7, OUT);
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SetMode(PIN_DP, OUT);
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}
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// Initialize all signals
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signals = 0;
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#endif // ifdef __x86_64__ || __X86__
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}
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void GPIOBUS::SetENB(bool ast)
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{
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PinSetSignal(PIN_ENB, ast ? ENB_ON : ENB_OFF);
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}
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bool GPIOBUS::GetBSY() const
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{
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return GetSignal(PIN_BSY);
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}
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void GPIOBUS::SetBSY(bool ast)
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{
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// Set BSY signal
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SetSignal(PIN_BSY, ast);
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if (actmode == mode_e::TARGET) {
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if (ast) {
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// Turn on ACTIVE signal
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SetControl(PIN_ACT, ACT_ON);
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// Set Target signal to output
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SetControl(PIN_TAD, TAD_OUT);
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SetMode(PIN_BSY, OUT);
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SetMode(PIN_MSG, OUT);
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SetMode(PIN_CD, OUT);
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SetMode(PIN_REQ, OUT);
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SetMode(PIN_IO, OUT);
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} else {
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// Turn off the ACTIVE signal
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SetControl(PIN_ACT, ACT_OFF);
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// Set the target signal to input
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SetControl(PIN_TAD, TAD_IN);
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SetMode(PIN_BSY, IN);
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SetMode(PIN_MSG, IN);
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SetMode(PIN_CD, IN);
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SetMode(PIN_REQ, IN);
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SetMode(PIN_IO, IN);
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}
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}
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}
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bool GPIOBUS::GetSEL() const
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{
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return GetSignal(PIN_SEL);
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}
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void GPIOBUS::SetSEL(bool ast)
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{
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if (actmode == mode_e::INITIATOR && ast) {
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// Turn on ACTIVE signal
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SetControl(PIN_ACT, ACT_ON);
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}
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// Set SEL signal
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SetSignal(PIN_SEL, ast);
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}
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bool GPIOBUS::GetATN() const
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{
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return GetSignal(PIN_ATN);
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}
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void GPIOBUS::SetATN(bool ast)
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{
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SetSignal(PIN_ATN, ast);
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}
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bool GPIOBUS::GetACK() const
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{
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return GetSignal(PIN_ACK);
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}
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void GPIOBUS::SetACK(bool ast)
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{
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SetSignal(PIN_ACK, ast);
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}
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bool GPIOBUS::GetACT() const
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{
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return GetSignal(PIN_ACT);
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}
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void GPIOBUS::SetACT(bool ast)
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{
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SetSignal(PIN_ACT, ast);
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}
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bool GPIOBUS::GetRST() const
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{
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return GetSignal(PIN_RST);
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}
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void GPIOBUS::SetRST(bool ast)
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{
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SetSignal(PIN_RST, ast);
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}
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bool GPIOBUS::GetMSG() const
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{
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return GetSignal(PIN_MSG);
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}
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void GPIOBUS::SetMSG(bool ast)
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{
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SetSignal(PIN_MSG, ast);
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}
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bool GPIOBUS::GetCD() const
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{
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return GetSignal(PIN_CD);
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}
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void GPIOBUS::SetCD(bool ast)
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{
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SetSignal(PIN_CD, ast);
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}
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bool GPIOBUS::GetIO()
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{
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bool ast = GetSignal(PIN_IO);
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if (actmode == mode_e::INITIATOR) {
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// Change the data input/output direction by IO signal
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if (ast) {
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SetControl(PIN_DTD, DTD_IN);
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SetMode(PIN_DT0, IN);
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SetMode(PIN_DT1, IN);
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SetMode(PIN_DT2, IN);
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SetMode(PIN_DT3, IN);
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SetMode(PIN_DT4, IN);
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SetMode(PIN_DT5, IN);
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SetMode(PIN_DT6, IN);
|
|
SetMode(PIN_DT7, IN);
|
|
SetMode(PIN_DP, IN);
|
|
} else {
|
|
SetControl(PIN_DTD, DTD_OUT);
|
|
SetMode(PIN_DT0, OUT);
|
|
SetMode(PIN_DT1, OUT);
|
|
SetMode(PIN_DT2, OUT);
|
|
SetMode(PIN_DT3, OUT);
|
|
SetMode(PIN_DT4, OUT);
|
|
SetMode(PIN_DT5, OUT);
|
|
SetMode(PIN_DT6, OUT);
|
|
SetMode(PIN_DT7, OUT);
|
|
SetMode(PIN_DP, OUT);
|
|
}
|
|
}
|
|
|
|
return ast;
|
|
}
|
|
|
|
void GPIOBUS::SetIO(bool ast)
|
|
{
|
|
SetSignal(PIN_IO, ast);
|
|
|
|
if (actmode == mode_e::TARGET) {
|
|
// Change the data input/output direction by IO signal
|
|
if (ast) {
|
|
SetControl(PIN_DTD, DTD_OUT);
|
|
SetDAT(0);
|
|
SetMode(PIN_DT0, OUT);
|
|
SetMode(PIN_DT1, OUT);
|
|
SetMode(PIN_DT2, OUT);
|
|
SetMode(PIN_DT3, OUT);
|
|
SetMode(PIN_DT4, OUT);
|
|
SetMode(PIN_DT5, OUT);
|
|
SetMode(PIN_DT6, OUT);
|
|
SetMode(PIN_DT7, OUT);
|
|
SetMode(PIN_DP, OUT);
|
|
} else {
|
|
SetControl(PIN_DTD, DTD_IN);
|
|
SetMode(PIN_DT0, IN);
|
|
SetMode(PIN_DT1, IN);
|
|
SetMode(PIN_DT2, IN);
|
|
SetMode(PIN_DT3, IN);
|
|
SetMode(PIN_DT4, IN);
|
|
SetMode(PIN_DT5, IN);
|
|
SetMode(PIN_DT6, IN);
|
|
SetMode(PIN_DT7, IN);
|
|
SetMode(PIN_DP, IN);
|
|
}
|
|
}
|
|
}
|
|
|
|
bool GPIOBUS::GetREQ() const
|
|
{
|
|
return GetSignal(PIN_REQ);
|
|
}
|
|
|
|
void GPIOBUS::SetREQ(bool ast)
|
|
{
|
|
SetSignal(PIN_REQ, ast);
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Get data signals
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
uint8_t GPIOBUS::GetDAT()
|
|
{
|
|
uint32_t data = Acquire();
|
|
data =
|
|
((data >> (PIN_DT0 - 0)) & (1 << 0)) |
|
|
((data >> (PIN_DT1 - 1)) & (1 << 1)) |
|
|
((data >> (PIN_DT2 - 2)) & (1 << 2)) |
|
|
((data >> (PIN_DT3 - 3)) & (1 << 3)) |
|
|
((data >> (PIN_DT4 - 4)) & (1 << 4)) |
|
|
((data >> (PIN_DT5 - 5)) & (1 << 5)) |
|
|
((data >> (PIN_DT6 - 6)) & (1 << 6)) |
|
|
((data >> (PIN_DT7 - 7)) & (1 << 7));
|
|
|
|
return (uint8_t)data;
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Set data signals
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
void GPIOBUS::SetDAT(uint8_t dat)
|
|
{
|
|
// Write to port
|
|
#if SIGNAL_CONTROL_MODE == 0
|
|
uint32_t fsel = gpfsel[0];
|
|
fsel &= tblDatMsk[0][dat];
|
|
fsel |= tblDatSet[0][dat];
|
|
if (fsel != gpfsel[0]) {
|
|
gpfsel[0] = fsel;
|
|
gpio[GPIO_FSEL_0] = fsel;
|
|
}
|
|
|
|
fsel = gpfsel[1];
|
|
fsel &= tblDatMsk[1][dat];
|
|
fsel |= tblDatSet[1][dat];
|
|
if (fsel != gpfsel[1]) {
|
|
gpfsel[1] = fsel;
|
|
gpio[GPIO_FSEL_1] = fsel;
|
|
}
|
|
|
|
fsel = gpfsel[2];
|
|
fsel &= tblDatMsk[2][dat];
|
|
fsel |= tblDatSet[2][dat];
|
|
if (fsel != gpfsel[2]) {
|
|
gpfsel[2] = fsel;
|
|
gpio[GPIO_FSEL_2] = fsel;
|
|
}
|
|
#else
|
|
gpio[GPIO_CLR_0] = tblDatMsk[dat];
|
|
gpio[GPIO_SET_0] = tblDatSet[dat];
|
|
#endif // SIGNAL_CONTROL_MODE
|
|
}
|
|
|
|
bool GPIOBUS::GetDP() const
|
|
{
|
|
return GetSignal(PIN_DP);
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Receive command handshake
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
int GPIOBUS::CommandHandShake(vector<uint8_t>& buf)
|
|
{
|
|
// Only works in TARGET mode
|
|
if (actmode != mode_e::TARGET) {
|
|
return 0;
|
|
}
|
|
|
|
DisableIRQ();
|
|
|
|
// Assert REQ signal
|
|
SetSignal(PIN_REQ, ON);
|
|
|
|
// Wait for ACK signal
|
|
bool ret = WaitSignal(PIN_ACK, ON);
|
|
|
|
// Wait until the signal line stabilizes
|
|
SysTimer::SleepNsec(SCSI_DELAY_BUS_SETTLE_DELAY_NS);
|
|
|
|
// Get data
|
|
buf[0] = GetDAT();
|
|
|
|
// Disable REQ signal
|
|
SetSignal(PIN_REQ, OFF);
|
|
|
|
// Timeout waiting for ACK assertion
|
|
if (!ret) {
|
|
EnableIRQ();
|
|
return 0;
|
|
}
|
|
|
|
// Wait for ACK to clear
|
|
ret = WaitSignal(PIN_ACK, OFF);
|
|
|
|
// Timeout waiting for ACK to clear
|
|
if (!ret) {
|
|
EnableIRQ();
|
|
return 0;
|
|
}
|
|
|
|
// The ICD AdSCSI ST, AdSCSI Plus ST and AdSCSI Micro ST host adapters allow SCSI devices to be connected
|
|
// to the ACSI bus of Atari ST/TT computers and some clones. ICD-aware drivers prepend a $1F byte in front
|
|
// of the CDB (effectively resulting in a custom SCSI command) in order to get access to the full SCSI
|
|
// command set. Native ACSI is limited to the low SCSI command classes with command bytes < $20.
|
|
// Most other host adapters (e.g. LINK96/97 and the one by Inventronik) and also several devices (e.g.
|
|
// UltraSatan or GigaFile) that can directly be connected to the Atari's ACSI port also support ICD
|
|
// semantics. I fact, these semantics have become a standard in the Atari world.
|
|
|
|
// RaSCSI becomes ICD compatible by ignoring the prepended $1F byte before processing the CDB.
|
|
if (buf[0] == 0x1F) {
|
|
SetSignal(PIN_REQ, ON);
|
|
|
|
ret = WaitSignal(PIN_ACK, ON);
|
|
|
|
SysTimer::SleepNsec(SCSI_DELAY_BUS_SETTLE_DELAY_NS);
|
|
|
|
// Get the actual SCSI command
|
|
buf[0] = GetDAT();
|
|
|
|
SetSignal(PIN_REQ, OFF);
|
|
|
|
if (!ret) {
|
|
EnableIRQ();
|
|
return 0;
|
|
}
|
|
|
|
WaitSignal(PIN_ACK, OFF);
|
|
|
|
if (!ret) {
|
|
EnableIRQ();
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
const int command_byte_count = GetCommandByteCount(buf[0]);
|
|
if (command_byte_count == 0) {
|
|
EnableIRQ();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int offset = 0;
|
|
|
|
int bytes_received;
|
|
for (bytes_received = 1; bytes_received < command_byte_count; bytes_received++) {
|
|
++offset;
|
|
|
|
// Assert REQ signal
|
|
SetSignal(PIN_REQ, ON);
|
|
|
|
// Wait for ACK signal
|
|
ret = WaitSignal(PIN_ACK, ON);
|
|
|
|
// Wait until the signal line stabilizes
|
|
SysTimer::SleepNsec(SCSI_DELAY_BUS_SETTLE_DELAY_NS);
|
|
|
|
// Get data
|
|
buf[offset] = GetDAT();
|
|
|
|
// Clear the REQ signal
|
|
SetSignal(PIN_REQ, OFF);
|
|
|
|
// Check for timeout waiting for ACK assertion
|
|
if (!ret) {
|
|
break;
|
|
}
|
|
|
|
// Wait for ACK to clear
|
|
ret = WaitSignal(PIN_ACK, OFF);
|
|
|
|
// Check for timeout waiting for ACK to clear
|
|
if (!ret) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
EnableIRQ();
|
|
|
|
return bytes_received;
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Data reception handshake
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
int GPIOBUS::ReceiveHandShake(uint8_t *buf, int count)
|
|
{
|
|
int i;
|
|
|
|
// Disable IRQs
|
|
DisableIRQ();
|
|
|
|
if (actmode == mode_e::TARGET) {
|
|
for (i = 0; i < count; i++) {
|
|
// Assert the REQ signal
|
|
SetSignal(PIN_REQ, ON);
|
|
|
|
// Wait for ACK
|
|
bool ret = WaitSignal(PIN_ACK, ON);
|
|
|
|
// Wait until the signal line stabilizes
|
|
SysTimer::SleepNsec(SCSI_DELAY_BUS_SETTLE_DELAY_NS);
|
|
|
|
// Get data
|
|
*buf = GetDAT();
|
|
|
|
// Clear the REQ signal
|
|
SetSignal(PIN_REQ, OFF);
|
|
|
|
// Check for timeout waiting for ACK signal
|
|
if (!ret) {
|
|
break;
|
|
}
|
|
|
|
// Wait for ACK to clear
|
|
ret = WaitSignal(PIN_ACK, OFF);
|
|
|
|
// Check for timeout waiting for ACK to clear
|
|
if (!ret) {
|
|
break;
|
|
}
|
|
|
|
// Advance the buffer pointer to receive the next byte
|
|
buf++;
|
|
}
|
|
} else {
|
|
// Get phase
|
|
uint32_t phase = Acquire() & GPIO_MCI;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
// Wait for the REQ signal to be asserted
|
|
bool ret = WaitSignal(PIN_REQ, ON);
|
|
|
|
// Check for timeout waiting for REQ signal
|
|
if (!ret) {
|
|
break;
|
|
}
|
|
|
|
// Phase error
|
|
if ((signals & GPIO_MCI) != phase) {
|
|
break;
|
|
}
|
|
|
|
// Wait until the signal line stabilizes
|
|
SysTimer::SleepNsec(SCSI_DELAY_BUS_SETTLE_DELAY_NS);
|
|
|
|
// Get data
|
|
*buf = GetDAT();
|
|
|
|
// Assert the ACK signal
|
|
SetSignal(PIN_ACK, ON);
|
|
|
|
// Wait for REQ to clear
|
|
ret = WaitSignal(PIN_REQ, OFF);
|
|
|
|
// Clear the ACK signal
|
|
SetSignal(PIN_ACK, OFF);
|
|
|
|
// Check for timeout waiting for REQ to clear
|
|
if (!ret) {
|
|
break;
|
|
}
|
|
|
|
// Phase error
|
|
if ((signals & GPIO_MCI) != phase) {
|
|
break;
|
|
}
|
|
|
|
// Advance the buffer pointer to receive the next byte
|
|
buf++;
|
|
}
|
|
}
|
|
|
|
// Re-enable IRQ
|
|
EnableIRQ();
|
|
|
|
// Return the number of bytes received
|
|
return i;
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Data transmission handshake
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
int GPIOBUS::SendHandShake(uint8_t *buf, int count, int delay_after_bytes)
|
|
{
|
|
int i;
|
|
|
|
// Disable IRQs
|
|
DisableIRQ();
|
|
|
|
if (actmode == mode_e::TARGET) {
|
|
for (i = 0; i < count; i++) {
|
|
if(i==delay_after_bytes){
|
|
LOGTRACE("%s DELAYING for %dus after %d bytes", __PRETTY_FUNCTION__, SCSI_DELAY_SEND_DATA_DAYNAPORT_US, (int)delay_after_bytes)
|
|
SysTimer::SleepUsec(SCSI_DELAY_SEND_DATA_DAYNAPORT_US);
|
|
}
|
|
|
|
// Set the DATA signals
|
|
SetDAT(*buf);
|
|
|
|
// Wait for ACK to clear
|
|
bool ret = WaitSignal(PIN_ACK, OFF);
|
|
|
|
// Check for timeout waiting for ACK to clear
|
|
if (!ret) {
|
|
break;
|
|
}
|
|
|
|
// Already waiting for ACK to clear
|
|
|
|
// Assert the REQ signal
|
|
SetSignal(PIN_REQ, ON);
|
|
|
|
// Wait for ACK
|
|
ret = WaitSignal(PIN_ACK, ON);
|
|
|
|
// Clear REQ signal
|
|
SetSignal(PIN_REQ, OFF);
|
|
|
|
// Check for timeout waiting for ACK to clear
|
|
if (!ret) {
|
|
break;
|
|
}
|
|
|
|
// Advance the data buffer pointer to receive the next byte
|
|
buf++;
|
|
}
|
|
|
|
// Wait for ACK to clear
|
|
WaitSignal(PIN_ACK, OFF);
|
|
} else {
|
|
// Get Phase
|
|
uint32_t phase = Acquire() & GPIO_MCI;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
if(i==delay_after_bytes){
|
|
LOGTRACE("%s DELAYING for %dus after %d bytes", __PRETTY_FUNCTION__, SCSI_DELAY_SEND_DATA_DAYNAPORT_US, (int)delay_after_bytes)
|
|
SysTimer::SleepUsec(SCSI_DELAY_SEND_DATA_DAYNAPORT_US);
|
|
}
|
|
|
|
// Set the DATA signals
|
|
SetDAT(*buf);
|
|
|
|
// Wait for REQ to be asserted
|
|
bool ret = WaitSignal(PIN_REQ, ON);
|
|
|
|
// Check for timeout waiting for REQ to be asserted
|
|
if (!ret) {
|
|
break;
|
|
}
|
|
|
|
// Phase error
|
|
if ((signals & GPIO_MCI) != phase) {
|
|
break;
|
|
}
|
|
|
|
// Already waiting for REQ assertion
|
|
|
|
// Assert the ACK signal
|
|
SetSignal(PIN_ACK, ON);
|
|
|
|
// Wait for REQ to clear
|
|
ret = WaitSignal(PIN_REQ, OFF);
|
|
|
|
// Clear the ACK signal
|
|
SetSignal(PIN_ACK, OFF);
|
|
|
|
// Check for timeout waiting for REQ to clear
|
|
if (!ret) {
|
|
break;
|
|
}
|
|
|
|
// Phase error
|
|
if ((signals & GPIO_MCI) != phase) {
|
|
break;
|
|
}
|
|
|
|
// Advance the data buffer pointer to receive the next byte
|
|
buf++;
|
|
}
|
|
}
|
|
|
|
// Re-enable IRQ
|
|
EnableIRQ();
|
|
|
|
// Return number of transmissions
|
|
return i;
|
|
}
|
|
|
|
#ifdef USE_SEL_EVENT_ENABLE
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// SEL signal event polling
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
bool GPIOBUS::PollSelectEvent()
|
|
{
|
|
errno = 0;
|
|
|
|
if (epoll_event epev; epoll_wait(epfd, &epev, 1, -1) <= 0) {
|
|
LOGWARN("%s epoll_wait failed", __PRETTY_FUNCTION__)
|
|
return false;
|
|
}
|
|
|
|
if (gpioevent_data gpev; read(selevreq.fd, &gpev, sizeof(gpev)) < 0) {
|
|
LOGWARN("%s read failed", __PRETTY_FUNCTION__)
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Cancel SEL signal event
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
void GPIOBUS::ClearSelectEvent()
|
|
{
|
|
}
|
|
#endif // USE_SEL_EVENT_ENABLE
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Signal table
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
const array<int, 19> GPIOBUS::SignalTable = {
|
|
PIN_DT0, PIN_DT1, PIN_DT2, PIN_DT3,
|
|
PIN_DT4, PIN_DT5, PIN_DT6, PIN_DT7, PIN_DP,
|
|
PIN_SEL,PIN_ATN, PIN_RST, PIN_ACK,
|
|
PIN_BSY, PIN_MSG, PIN_CD, PIN_IO, PIN_REQ,
|
|
-1
|
|
};
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Create work table
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
void GPIOBUS::MakeTable(void)
|
|
{
|
|
const array<int, 9> pintbl = {
|
|
PIN_DT0, PIN_DT1, PIN_DT2, PIN_DT3, PIN_DT4,
|
|
PIN_DT5, PIN_DT6, PIN_DT7, PIN_DP
|
|
};
|
|
|
|
array<bool, 256> tblParity;
|
|
|
|
// Create parity table
|
|
for (uint32_t i = 0; i < 0x100; i++) {
|
|
uint32_t bits = i;
|
|
uint32_t parity = 0;
|
|
for (int j = 0; j < 8; j++) {
|
|
parity ^= bits & 1;
|
|
bits >>= 1;
|
|
}
|
|
parity = ~parity;
|
|
tblParity[i] = parity & 1;
|
|
}
|
|
|
|
#if SIGNAL_CONTROL_MODE == 0
|
|
// Mask and setting data generation
|
|
for (auto& tbl : tblDatMsk) {
|
|
tbl.fill(-1);
|
|
}
|
|
for (auto& tbl : tblDatSet) {
|
|
tbl.fill(0);
|
|
}
|
|
|
|
for (uint32_t i = 0; i < 0x100; i++) {
|
|
// Bit string for inspection
|
|
uint32_t bits = i;
|
|
|
|
// Get parity
|
|
if (tblParity[i]) {
|
|
bits |= (1 << 8);
|
|
}
|
|
|
|
// Bit check
|
|
for (int j = 0; j < 9; j++) {
|
|
// Index and shift amount calculation
|
|
int index = pintbl[j] / 10;
|
|
int shift = (pintbl[j] % 10) * 3;
|
|
|
|
// Mask data
|
|
tblDatMsk[index][i] &= ~(0x7 << shift);
|
|
|
|
// Setting data
|
|
if (bits & 1) {
|
|
tblDatSet[index][i] |= (1 << shift);
|
|
}
|
|
|
|
bits >>= 1;
|
|
}
|
|
}
|
|
#else
|
|
for (uint32_t i = 0; i < 0x100; i++) {
|
|
// Bit string for inspection
|
|
uint32_t bits = i;
|
|
|
|
// Get parity
|
|
if (tblParity[i]) {
|
|
bits |= (1 << 8);
|
|
}
|
|
|
|
#if SIGNAL_CONTROL_MODE == 1
|
|
// Negative logic is inverted
|
|
bits = ~bits;
|
|
#endif
|
|
|
|
// Create GPIO register information
|
|
uint32_t gpclr = 0;
|
|
uint32_t gpset = 0;
|
|
for (int j = 0; j < 9; j++) {
|
|
if (bits & 1) {
|
|
gpset |= (1 << pintbl[j]);
|
|
} else {
|
|
gpclr |= (1 << pintbl[j]);
|
|
}
|
|
bits >>= 1;
|
|
}
|
|
|
|
tblDatMsk[i] = gpclr;
|
|
tblDatSet[i] = gpset;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Control signal setting
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
void GPIOBUS::SetControl(int pin, bool ast)
|
|
{
|
|
PinSetSignal(pin, ast);
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Input/output mode setting
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
void GPIOBUS::SetMode(int pin, int mode)
|
|
{
|
|
#if SIGNAL_CONTROL_MODE == 0
|
|
if (mode == OUT) {
|
|
return;
|
|
}
|
|
#endif // SIGNAL_CONTROL_MODE
|
|
|
|
int index = pin / 10;
|
|
int shift = (pin % 10) * 3;
|
|
uint32_t data = gpfsel[index];
|
|
data &= ~(0x7 << shift);
|
|
if (mode == OUT) {
|
|
data |= (1 << shift);
|
|
}
|
|
gpio[index] = data;
|
|
gpfsel[index] = data;
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Get input signal value
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
bool GPIOBUS::GetSignal(int pin) const
|
|
{
|
|
return (signals >> pin) & 1;
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Set output signal value
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
void GPIOBUS::SetSignal(int pin, bool ast)
|
|
{
|
|
#if SIGNAL_CONTROL_MODE == 0
|
|
int index = pin / 10;
|
|
int shift = (pin % 10) * 3;
|
|
uint32_t data = gpfsel[index];
|
|
if (ast) {
|
|
data |= (1 << shift);
|
|
} else {
|
|
data &= ~(0x7 << shift);
|
|
}
|
|
gpio[index] = data;
|
|
gpfsel[index] = data;
|
|
#elif SIGNAL_CONTROL_MODE == 1
|
|
if (ast) {
|
|
gpio[GPIO_CLR_0] = 0x1 << pin;
|
|
} else {
|
|
gpio[GPIO_SET_0] = 0x1 << pin;
|
|
}
|
|
#elif SIGNAL_CONTROL_MODE == 2
|
|
if (ast) {
|
|
gpio[GPIO_SET_0] = 0x1 << pin;
|
|
} else {
|
|
gpio[GPIO_CLR_0] = 0x1 << pin;
|
|
}
|
|
#endif // SIGNAL_CONTROL_MODE
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Wait for signal change
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
bool GPIOBUS::WaitSignal(int pin, int ast)
|
|
{
|
|
// Get current time
|
|
uint32_t now = SysTimer::GetTimerLow();
|
|
|
|
// Calculate timeout (3000ms)
|
|
uint32_t timeout = 3000 * 1000;
|
|
|
|
// end immediately if the signal has changed
|
|
do {
|
|
// Immediately upon receiving a reset
|
|
Acquire();
|
|
if (GetRST()) {
|
|
return false;
|
|
}
|
|
|
|
// Check for the signal edge
|
|
if (((signals >> pin) ^ ~ast) & 1) {
|
|
return true;
|
|
}
|
|
} while ((SysTimer::GetTimerLow() - now) < timeout);
|
|
|
|
// We timed out waiting for the signal
|
|
return false;
|
|
}
|
|
|
|
void GPIOBUS::DisableIRQ()
|
|
{
|
|
#ifdef __linux__
|
|
if (rpitype == 4) {
|
|
// RPI4 is disabled by GICC
|
|
giccpmr = gicc[GICC_PMR];
|
|
gicc[GICC_PMR] = 0;
|
|
} else if (rpitype == 2) {
|
|
// RPI2,3 disable core timer IRQ
|
|
tintcore = sched_getcpu() + QA7_CORE0_TINTC;
|
|
tintctl = qa7regs[tintcore];
|
|
qa7regs[tintcore] = 0;
|
|
} else {
|
|
// Stop system timer interrupt with interrupt controller
|
|
irptenb = irpctl[IRPT_ENB_IRQ_1];
|
|
irpctl[IRPT_DIS_IRQ_1] = irptenb & 0xf;
|
|
}
|
|
#else
|
|
(void)0;
|
|
#endif
|
|
}
|
|
|
|
void GPIOBUS::EnableIRQ()
|
|
{
|
|
if (rpitype == 4) {
|
|
// RPI4 enables interrupts via the GICC
|
|
gicc[GICC_PMR] = giccpmr;
|
|
} else if (rpitype == 2) {
|
|
// RPI2,3 re-enable core timer IRQ
|
|
qa7regs[tintcore] = tintctl;
|
|
} else {
|
|
// Restart the system timer interrupt with the interrupt controller
|
|
irpctl[IRPT_ENB_IRQ_1] = irptenb & 0xf;
|
|
}
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Pin direction setting (input/output)
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
void GPIOBUS::PinConfig(int pin, int mode)
|
|
{
|
|
// Check for invalid pin
|
|
if (pin < 0) {
|
|
return;
|
|
}
|
|
|
|
int index = pin / 10;
|
|
uint32_t mask = ~(0x7 << ((pin % 10) * 3));
|
|
gpio[index] = (gpio[index] & mask) | ((mode & 0x7) << ((pin % 10) * 3));
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Pin pull-up/pull-down setting
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
void GPIOBUS::PullConfig(int pin, int mode)
|
|
{
|
|
uint32_t pull;
|
|
|
|
// Check for invalid pin
|
|
if (pin < 0) {
|
|
return;
|
|
}
|
|
|
|
if (rpitype == 4) {
|
|
switch (mode) {
|
|
case GPIO_PULLNONE:
|
|
pull = 0;
|
|
break;
|
|
case GPIO_PULLUP:
|
|
pull = 1;
|
|
break;
|
|
case GPIO_PULLDOWN:
|
|
pull = 2;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
pin &= 0x1f;
|
|
int shift = (pin & 0xf) << 1;
|
|
uint32_t bits = gpio[GPIO_PUPPDN0 + (pin >> 4)];
|
|
bits &= ~(3 << shift);
|
|
bits |= (pull << shift);
|
|
gpio[GPIO_PUPPDN0 + (pin >> 4)] = bits;
|
|
} else {
|
|
pin &= 0x1f;
|
|
gpio[GPIO_PUD] = mode & 0x3;
|
|
SysTimer::SleepUsec(2);
|
|
gpio[GPIO_CLK_0] = 0x1 << pin;
|
|
SysTimer::SleepUsec(2);
|
|
gpio[GPIO_PUD] = 0;
|
|
gpio[GPIO_CLK_0] = 0;
|
|
}
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Set output pin
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
void GPIOBUS::PinSetSignal(int pin, bool ast)
|
|
{
|
|
// Check for invalid pin
|
|
if (pin < 0) {
|
|
return;
|
|
}
|
|
|
|
if (ast) {
|
|
gpio[GPIO_SET_0] = 0x1 << pin;
|
|
} else {
|
|
gpio[GPIO_CLR_0] = 0x1 << pin;
|
|
}
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Set the signal drive strength
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
void GPIOBUS::DrvConfig(uint32_t drive)
|
|
{
|
|
uint32_t data = pads[PAD_0_27];
|
|
pads[PAD_0_27] = (0xFFFFFFF8 & data) | drive | 0x5a000000;
|
|
}
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Generic Phase Acquisition (Doesn't read GPIO)
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
BUS::phase_t GPIOBUS::GetPhaseRaw(uint32_t raw_data)
|
|
{
|
|
// Selection Phase
|
|
if (GetPinRaw(raw_data, PIN_SEL)) {
|
|
if(GetPinRaw(raw_data, PIN_IO)) {
|
|
return BUS::phase_t::reselection;
|
|
} else{
|
|
return BUS::phase_t::selection;
|
|
}
|
|
}
|
|
|
|
// Bus busy phase
|
|
if (!GetPinRaw(raw_data, PIN_BSY)) {
|
|
return BUS::phase_t::busfree;
|
|
}
|
|
|
|
// Get target phase from bus signal line
|
|
int mci = GetPinRaw(raw_data, PIN_MSG) ? 0x04 : 0x00;
|
|
mci |= GetPinRaw(raw_data, PIN_CD) ? 0x02 : 0x00;
|
|
mci |= GetPinRaw(raw_data, PIN_IO) ? 0x01 : 0x00;
|
|
return GetPhase(mci);
|
|
}
|