mirror of https://github.com/akuker/RASCSI.git
189 lines
7.6 KiB
C++
189 lines
7.6 KiB
C++
//---------------------------------------------------------------------------
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//
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// SCSI Target Emulator PiSCSI
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// for Raspberry Pi
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//
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// Copyright (C) 2022 akuker
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//
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// [ Utility functions for working with Allwinner CPUs ]
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//
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// This should include generic functions that can be applicable to
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// different variants of the SunXI (Allwinner) SoCs
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//
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// Large portions of this functionality were derived from c_gpio.c, which
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// is part of the RPI.GPIO library available here:
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// https://github.com/BPI-SINOVOIP/RPi.GPIO/blob/master/source/c_gpio.c
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of
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// this software and associated documentation files (the "Software"), to deal in
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// the Software without restriction, including without limitation the rights to
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// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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// of the Software, and to permit persons to whom the Software is furnished to do
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// so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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//
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//---------------------------------------------------------------------------
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#pragma once
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#include <cstdint>
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#ifndef __arm__
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#include <time.h>
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#endif
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class SunXI
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{
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public:
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static inline int GPIO_BANK(int pin)
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{
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return (pin >> 5);
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}
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static inline int GPIO_NUM(int pin)
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{
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return (pin & 0x1F);
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}
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static inline int GPIO_CFG_INDEX(int pin)
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{
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return ((pin & 0x1F) >> 3);
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}
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static inline int GPIO_CFG_OFFSET(int pin)
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{
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return (((pin & 0x1F) & 0x7) << 2);
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}
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static inline int GPIO_PUL_INDEX(int pin)
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{
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return ((pin & 0x1F) >> 4);
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}
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static inline int GPIO_PUL_OFFSET(int pin)
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{
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return ((pin & 0x0F) << 1);
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}
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static inline int GPIO_DRV_INDEX(int pin)
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{
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return ((pin & 0x1F) >> 4);
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}
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static inline int GPIO_DRV_OFFSET(int pin)
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{
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return ((pin & 0x0F) << 1);
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}
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static inline void short_wait(void)
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{
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for (int i = 0; i < 150; i++) {
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#ifndef __arm__
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// Timing doesn't really matter if we're not on ARM.
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// The SunXI SoCs are all ARM-based.
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const timespec ts = {.tv_sec = 0, .tv_nsec = 1};
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nanosleep(&ts, nullptr);
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#else
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// wait 150 cycles
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asm volatile("nop");
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#endif
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}
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}
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enum class gpio_configure_values_e : uint8_t {
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gpio_input = 0b000,
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gpio_output = 0b001,
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gpio_alt_func_1 = 0b010,
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gpio_alt_func_2 = 0b011,
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gpio_reserved_1 = 0b100,
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gpio_reserved_2 = 0b101,
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gpio_interupt = 0b110,
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gpio_disable = 0b111
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};
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struct sunxi_gpio {
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unsigned int CFG[4]; // NOSONAR: Intentionally using C style arrays for low level register access
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unsigned int DAT;
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unsigned int DRV[2]; // NOSONAR: Intentionally using C style arrays for low level register access
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unsigned int PULL[2]; // NOSONAR: Intentionally using C style arrays for low level register access
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};
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using sunxi_gpio_t = struct sunxi_gpio;
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/* gpio interrupt control */
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struct sunxi_gpio_int {
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unsigned int CFG[3]; // NOSONAR: Intentionally using C style arrays for low level register access
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unsigned int CTL;
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unsigned int STA;
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unsigned int DEB;
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};
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using sunxi_gpio_int_t = struct sunxi_gpio_int;
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struct sunxi_gpio_reg {
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struct sunxi_gpio gpio_bank[9]; // NOSONAR: Intentionally using C style arrays for low level register access
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unsigned char res[0xbc]; // NOSONAR: Intentionally using C style arrays for low level register access
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struct sunxi_gpio_int gpio_int;
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};
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using sunxi_gpio_reg_t = struct sunxi_gpio_reg;
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static const uint32_t PAGE_SIZE = (4 * 1024);
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static const uint32_t BLOCK_SIZE = (4 * 1024);
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static const int SETUP_DEVMEM_FAIL = 1;
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static const int SETUP_MALLOC_FAIL = 2;
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static const int SETUP_MMAP_FAIL = 3;
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static const int SETUP_CPUINFO_FAIL = 4;
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static const int SETUP_NOT_RPI_FAIL = 5;
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static const int INPUT = 1;
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static const int OUTPUT = 0;
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static const int ALT0 = 4;
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static const int HIGH = 1;
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static const int LOW = 0;
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static const int PUD_OFF = 0;
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static const int PUD_DOWN = 1;
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static const int PUD_UP = 2;
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static const uint32_t SUNXI_R_GPIO_BASE = 0x01F02000;
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static const uint32_t SUNXI_R_GPIO_REG_OFFSET = 0xC00;
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static const uint32_t SUNXI_GPIO_BASE = 0x01C20000;
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static const uint32_t SUNXI_GPIO_REG_OFFSET = 0x800;
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static const uint32_t SUNXI_CFG_OFFSET = 0x00;
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static const uint32_t SUNXI_DATA_OFFSET = 0x10;
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static const uint32_t SUNXI_PUD_OFFSET = 0x1C;
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static const uint32_t SUNXI_BANK_SIZE = 0x24;
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static const uint32_t MAP_SIZE = (4096 * 2);
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static const uint32_t MAP_MASK = (MAP_SIZE - 1);
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static const int FSEL_OFFSET = 0; // 0x0000
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static const int SET_OFFSET = 7; // 0x001c / 4
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static const int CLR_OFFSET = 10; // 0x0028 / 4
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static const int PINLEVEL_OFFSET = 13; // 0x0034 / 4
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static const int EVENT_DETECT_OFFSET = 16; // 0x0040 / 4
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static const int RISING_ED_OFFSET = 19; // 0x004c / 4
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static const int FALLING_ED_OFFSET = 22; // 0x0058 / 4
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static const int HIGH_DETECT_OFFSET = 25; // 0x0064 / 4
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static const int LOW_DETECT_OFFSET = 28; // 0x0070 / 4
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static const int PULLUPDN_OFFSET = 37; // 0x0094 / 4
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static const int PULLUPDNCLK_OFFSET = 38; // 0x0098 / 4
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static const uint32_t TMR_REGISTER_BASE = 0x01C20C00;
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static const uint32_t TMR_IRQ_EN_REG = 0x0; // T imer IRQ Enable Register
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static const uint32_t TMR_IRQ_STA_REG = 0x4; // Timer Status Register
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static const uint32_t TMR0_CTRL_REG = 0x10; // Timer 0 Control Register
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static const uint32_t TMR0_INTV_VALUE_REG = 0x14; // Timer 0 Interval Value Register
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static const uint32_t TMR0_CUR_VALUE_REG = 0x18; // Timer 0 Current Value Register
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static const uint32_t TMR1_CTRL_REG = 0x20; // Timer 1 Control Register
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static const uint32_t TMR1_INTV_VALUE_REG = 0x24; // Timer 1 Interval Value Register
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static const uint32_t TMR1_CUR_VALUE_REG = 0x28; // Timer 1 Current Value Register
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static const uint32_t AVS_CNT_CTL_REG = 0x80; // AVS Control Register
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static const uint32_t AVS_CNT0_REG = 0x84; // AVS Counter 0 Register
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static const uint32_t AVS_CNT1_REG = 0x88; // AVS Counter 1 Register
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static const uint32_t AVS_CNT_DIV_REG = 0x8C; // AVS Divisor Register
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static const uint32_t WDOG0_IRQ_EN_REG = 0xA0; // Watchdog 0 IRQ Enable Register
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static const uint32_t WDOG0_IRQ_STA_REG = 0xA4; // Watchdog 0 Status Register
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static const uint32_t WDOG0_CTRL_REG = 0xB0; // Watchdog 0 Control Register
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static const uint32_t WDOG0_CFG_REG = 0xB4; // Watchdog 0 Configuration Register
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static const uint32_t WDOG0_MODE_REG = 0xB8; // Watchdog 0 Mode Register
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}; |