mirror of https://github.com/akuker/RASCSI.git
699 lines
21 KiB
C++
699 lines
21 KiB
C++
//---------------------------------------------------------------------------
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//
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// SCSI Target Emulator RaSCSI (*^..^*)
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// for Raspberry Pi
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//
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// Powered by XM6 TypeG Technology.
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// Copyright (C) 2016-2020 GIMONS
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// [ GPIO-SCSI bus ]
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//
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//---------------------------------------------------------------------------
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#if !defined(gpiobus_h)
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#define gpiobus_h
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#include "config.h"
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#include "scsi.h"
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//---------------------------------------------------------------------------
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//
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// Connection method definitions
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//
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//---------------------------------------------------------------------------
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//#define CONNECT_TYPE_STANDARD // Standard (SCSI logic, standard pin assignment)
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//#define CONNECT_TYPE_FULLSPEC // Full spec (SCSI logic, standard pin assignment)
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//#define CONNECT_TYPE_AIBOM // AIBOM version (positive logic, unique pin assignment)
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//#define CONNECT_TYPE_GAMERNIUM // GAMERnium.com version (standard logic, unique pin assignment)
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//---------------------------------------------------------------------------
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//
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// Signal control logic and pin assignment customization
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//
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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//
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// SIGNAL_CONTROL_MODE: Signal control mode selection
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// You can customize the signal control logic from Version 1.22
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//
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// 0:SCSI logical specification
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// Conversion board using 74LS641-1 etc. directly connected or published on HP
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// True : 0V
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// False : Open collector output (disconnect from bus)
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//
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// 1:Negative logic specification (when using conversion board for negative logic -> SCSI logic)
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// There is no conversion board with this specification at this time
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// True : 0V -> (CONVERT) -> 0V
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// False : 3.3V -> (CONVERT) -> Open collector output
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//
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// 2:Positive logic specification (when using the conversion board for positive logic -> SCSI logic)
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// RaSCSI Adapter Rev.C @132sync etc.
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//
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// True : 3.3V -> (CONVERT) -> 0V
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// False : 0V -> (CONVERT) -> Open collector output
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//
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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//
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// Control signal pin assignment setting
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// GPIO pin mapping table for control signals.
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//
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// Control signal:
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// PIN_ACT
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// Signal that indicates the status of processing SCSI command.
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// PIN_ENB
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// Signal that indicates the valid signal from start to finish.
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// PIN_TAD
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// Signal that indicates the input/output direction of the target signal (BSY,IO,CD,MSG,REG).
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// PIN_IND
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// Signal that indicates the input/output direction of the initiator signal (SEL, ATN, RST, ACK).
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// PIN_DTD
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// Signal that indicates the input/output direction of the data lines (DT0...DT7,DP).
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//
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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//
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// Control signal output logic
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// 0V:FALSE 3.3V:TRUE
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//
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// ACT_ON
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// PIN_ACT signal
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// ENB_ON
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// PIN_ENB signal
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// TAD_IN
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// PIN_TAD This is the logic when inputting.
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// IND_IN
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// PIN_ENB This is the logic when inputting.
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// DTD_IN
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// PIN_ENB This is the logic when inputting.
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//
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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//
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// SCSI signal pin assignment setting
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// GPIO pin mapping table for SCSI signals.
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// PIN_DT0～PIN_SEL
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//
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//---------------------------------------------------------------------------
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#ifdef CONNECT_TYPE_STANDARD
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//
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// RaSCSI standard (SCSI logic, standard pin assignment)
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//
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#define CONNECT_DESC "STANDARD" // Startup message
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// Select signal control mode
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#define SIGNAL_CONTROL_MODE 0 // SCSI logical specification
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// Control signal pin assignment (-1 means no control)
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#define PIN_ACT 4 // ACTIVE
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#define PIN_ENB 5 // ENABLE
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#define PIN_IND -1 // INITIATOR CTRL DIRECTION
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#define PIN_TAD -1 // TARGET CTRL DIRECTION
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#define PIN_DTD -1 // DATA DIRECTION
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// Control signal output logic
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#define ACT_ON TRUE // ACTIVE SIGNAL ON
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#define ENB_ON TRUE // ENABLE SIGNAL ON
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#define IND_IN FALSE // INITIATOR SIGNAL INPUT
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#define TAD_IN FALSE // TARGET SIGNAL INPUT
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#define DTD_IN TRUE // DATA SIGNAL INPUT
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// SCSI signal pin assignment
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#define PIN_DT0 10 // Data 0
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#define PIN_DT1 11 // Data 1
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#define PIN_DT2 12 // Data 2
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#define PIN_DT3 13 // Data 3
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#define PIN_DT4 14 // Data 4
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#define PIN_DT5 15 // Data 5
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#define PIN_DT6 16 // Data 6
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#define PIN_DT7 17 // Data 7
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#define PIN_DP 18 // Data parity
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#define PIN_ATN 19 // ATN
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#define PIN_RST 20 // RST
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#define PIN_ACK 21 // ACK
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#define PIN_REQ 22 // REQ
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#define PIN_MSG 23 // MSG
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#define PIN_CD 24 // CD
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#define PIN_IO 25 // IO
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#define PIN_BSY 26 // BSY
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#define PIN_SEL 27 // SEL
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#endif
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#ifdef CONNECT_TYPE_FULLSPEC
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//
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// RaSCSI standard (SCSI logic, standard pin assignment)
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//
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#define CONNECT_DESC "FULLSPEC" // Startup message
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// Select signal control mode
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#define SIGNAL_CONTROL_MODE 0 // SCSI logical specification
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// Control signal pin assignment (-1 means no control)
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#define PIN_ACT 4 // ACTIVE
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#define PIN_ENB 5 // ENABLE
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#define PIN_IND 6 // INITIATOR CTRL DIRECTION
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#define PIN_TAD 7 // TARGET CTRL DIRECTION
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#define PIN_DTD 8 // DATA DIRECTION
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// Control signal output logic
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#define ACT_ON TRUE // ACTIVE SIGNAL ON
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#define ENB_ON TRUE // ENABLE SIGNAL ON
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#define IND_IN FALSE // INITIATOR SIGNAL INPUT
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#define TAD_IN FALSE // TARGET SIGNAL INPUT
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#define DTD_IN TRUE // DATA SIGNAL INPUT
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// SCSI signal pin assignment
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#define PIN_DT0 10 // Data 0
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#define PIN_DT1 11 // Data 1
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#define PIN_DT2 12 // Data 2
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#define PIN_DT3 13 // Data 3
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#define PIN_DT4 14 // Data 4
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#define PIN_DT5 15 // Data 5
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#define PIN_DT6 16 // Data 6
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#define PIN_DT7 17 // Data 7
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#define PIN_DP 18 // Data parity
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#define PIN_ATN 19 // ATN
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#define PIN_RST 20 // RST
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#define PIN_ACK 21 // ACK
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#define PIN_REQ 22 // REQ
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#define PIN_MSG 23 // MSG
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#define PIN_CD 24 // CD
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#define PIN_IO 25 // IO
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#define PIN_BSY 26 // BSY
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#define PIN_SEL 27 // SEL
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#endif
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#ifdef CONNECT_TYPE_AIBOM
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//
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// RaSCSI Adapter Aibom version
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//
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#define CONNECT_DESC "AIBOM PRODUCTS version" // Startup message
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// Select signal control mode
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#define SIGNAL_CONTROL_MODE 2 // SCSI positive logic specification
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// Control signal output logic
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#define ACT_ON TRUE // ACTIVE SIGNAL ON
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#define ENB_ON TRUE // ENABLE SIGNAL ON
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#define IND_IN FALSE // INITIATOR SIGNAL INPUT
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#define TAD_IN FALSE // TARGET SIGNAL INPUT
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#define DTD_IN FALSE // DATA SIGNAL INPUT
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// Control signal pin assignment (-1 means no control)
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#define PIN_ACT 4 // ACTIVE
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#define PIN_ENB 17 // ENABLE
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#define PIN_IND 27 // INITIATOR CTRL DIRECTION
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#define PIN_TAD -1 // TARGET CTRL DIRECTION
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#define PIN_DTD 18 // DATA DIRECTION
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// SCSI signal pin assignment
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#define PIN_DT0 6 // Data 0
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#define PIN_DT1 12 // Data 1
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#define PIN_DT2 13 // Data 2
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#define PIN_DT3 16 // Data 3
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#define PIN_DT4 19 // Data 4
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#define PIN_DT5 20 // Data 5
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#define PIN_DT6 26 // Data 6
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#define PIN_DT7 21 // Data 7
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#define PIN_DP 5 // Data parity
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#define PIN_ATN 22 // ATN
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#define PIN_RST 25 // RST
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#define PIN_ACK 10 // ACK
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#define PIN_REQ 7 // REQ
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#define PIN_MSG 9 // MSG
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#define PIN_CD 11 // CD
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#define PIN_IO 23 // IO
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#define PIN_BSY 24 // BSY
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#define PIN_SEL 8 // SEL
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#endif
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#ifdef CONNECT_TYPE_GAMERNIUM
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//
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// RaSCSI Adapter GAMERnium.com version
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//
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#define CONNECT_DESC "GAMERnium.com version"// Startup message
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// Select signal control mode
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#define SIGNAL_CONTROL_MODE 0 // SCSI logical specification
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// Control signal output logic
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#define ACT_ON TRUE // ACTIVE SIGNAL ON
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#define ENB_ON TRUE // ENABLE SIGNAL ON
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#define IND_IN FALSE // INITIATOR SIGNAL INPUT
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#define TAD_IN FALSE // TARGET SIGNAL INPUT
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#define DTD_IN TRUE // DATA SIGNAL INPUT
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// Control signal pin assignment (-1 means no control)
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#define PIN_ACT 14 // ACTIVE
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#define PIN_ENB 6 // ENABLE
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#define PIN_IND 7 // INITIATOR CTRL DIRECTION
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#define PIN_TAD 8 // TARGET CTRL DIRECTION
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#define PIN_DTD 5 // DATA DIRECTION
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// SCSI signal pin assignment
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#define PIN_DT0 21 // Data 0
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#define PIN_DT1 26 // Data 1
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#define PIN_DT2 20 // Data 2
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#define PIN_DT3 19 // Data 3
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#define PIN_DT4 16 // Data 4
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#define PIN_DT5 13 // Data 5
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#define PIN_DT6 12 // Data 6
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#define PIN_DT7 11 // Data 7
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#define PIN_DP 25 // Data parity
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#define PIN_ATN 10 // ATN
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#define PIN_RST 22 // RST
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#define PIN_ACK 24 // ACK
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#define PIN_REQ 15 // REQ
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#define PIN_MSG 17 // MSG
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#define PIN_CD 18 // CD
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#define PIN_IO 4 // IO
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#define PIN_BSY 27 // BSY
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#define PIN_SEL 23 // SEL
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#endif
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#define ALL_SCSI_PINS \
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((1<<PIN_DT0)|\
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(1<<PIN_DT1)|\
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(1<<PIN_DT2)|\
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(1<<PIN_DT3)|\
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(1<<PIN_DT4)|\
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(1<<PIN_DT5)|\
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(1<<PIN_DT6)|\
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(1<<PIN_DT7)|\
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(1<<PIN_DP)|\
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(1<<PIN_ATN)|\
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(1<<PIN_RST)|\
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(1<<PIN_ACK)|\
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(1<<PIN_REQ)|\
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(1<<PIN_MSG)|\
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(1<<PIN_CD)|\
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(1<<PIN_IO)|\
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(1<<PIN_BSY)|\
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(1<<PIN_SEL))
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//---------------------------------------------------------------------------
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//
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// Constant declarations (GPIO)
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//
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//---------------------------------------------------------------------------
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#define SYST_OFFSET 0x00003000
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#define IRPT_OFFSET 0x0000B200
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#define ARMT_OFFSET 0x0000B400
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#define PADS_OFFSET 0x00100000
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#define GPIO_OFFSET 0x00200000
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#define QA7_OFFSET 0x01000000
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#define GPIO_INPUT 0
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#define GPIO_OUTPUT 1
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#define GPIO_PULLNONE 0
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#define GPIO_PULLDOWN 1
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#define GPIO_PULLUP 2
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#define GPIO_FSEL_0 0
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#define GPIO_FSEL_1 1
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#define GPIO_FSEL_2 2
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#define GPIO_FSEL_3 3
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#define GPIO_SET_0 7
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#define GPIO_CLR_0 10
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#define GPIO_LEV_0 13
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#define GPIO_EDS_0 16
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#define GPIO_REN_0 19
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#define GPIO_FEN_0 22
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#define GPIO_HEN_0 25
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#define GPIO_LEN_0 28
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#define GPIO_AREN_0 31
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#define GPIO_AFEN_0 34
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#define GPIO_PUD 37
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#define GPIO_CLK_0 38
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#define GPIO_GPPINMUXSD 52
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#define GPIO_PUPPDN0 57
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#define GPIO_PUPPDN1 58
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#define GPIO_PUPPDN3 59
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#define GPIO_PUPPDN4 60
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#define PAD_0_27 11
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#define SYST_CS 0
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#define SYST_CLO 1
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#define SYST_CHI 2
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#define SYST_C0 3
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#define SYST_C1 4
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#define SYST_C2 5
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#define SYST_C3 6
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#define ARMT_LOAD 0
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#define ARMT_VALUE 1
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#define ARMT_CTRL 2
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#define ARMT_CLRIRQ 3
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#define ARMT_RAWIRQ 4
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#define ARMT_MSKIRQ 5
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#define ARMT_RELOAD 6
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#define ARMT_PREDIV 7
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#define ARMT_FREERUN 8
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#define IRPT_PND_IRQ_B 0
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#define IRPT_PND_IRQ_1 1
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#define IRPT_PND_IRQ_2 2
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#define IRPT_FIQ_CNTL 3
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#define IRPT_ENB_IRQ_1 4
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#define IRPT_ENB_IRQ_2 5
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#define IRPT_ENB_IRQ_B 6
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#define IRPT_DIS_IRQ_1 7
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#define IRPT_DIS_IRQ_2 8
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#define IRPT_DIS_IRQ_B 9
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#define QA7_CORE0_TINTC 16
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#define GPIO_IRQ (32 + 20) // GPIO3
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#define GPIO_INEDGE ((1 << PIN_BSY) | \
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(1 << PIN_SEL) | \
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(1 << PIN_ATN) | \
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(1 << PIN_ACK) | \
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(1 << PIN_RST))
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#define GPIO_MCI ((1 << PIN_MSG) | \
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(1 << PIN_CD) | \
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(1 << PIN_IO))
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//---------------------------------------------------------------------------
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//
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// Constant declarations (GIC)
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//
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//---------------------------------------------------------------------------
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#define ARM_GICD_BASE 0xFF841000
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#define ARM_GICC_BASE 0xFF842000
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#define ARM_GIC_END 0xFF847FFF
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#define GICD_CTLR 0x000
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#define GICD_IGROUPR0 0x020
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#define GICD_ISENABLER0 0x040
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#define GICD_ICENABLER0 0x060
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#define GICD_ISPENDR0 0x080
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#define GICD_ICPENDR0 0x0A0
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#define GICD_ISACTIVER0 0x0C0
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#define GICD_ICACTIVER0 0x0E0
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#define GICD_IPRIORITYR0 0x100
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#define GICD_ITARGETSR0 0x200
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#define GICD_ICFGR0 0x300
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#define GICD_SGIR 0x3C0
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#define GICC_CTLR 0x000
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#define GICC_PMR 0x001
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#define GICC_IAR 0x003
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#define GICC_EOIR 0x004
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//---------------------------------------------------------------------------
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//
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// Constant declarations (GIC IRQ)
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//
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//---------------------------------------------------------------------------
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#define GIC_IRQLOCAL0 (16 + 14)
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#define GIC_GPIO_IRQ (32 + 116) // GPIO3
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//---------------------------------------------------------------------------
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//
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// Constant declarations (Control signals)
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//
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//---------------------------------------------------------------------------
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#define ACT_OFF !ACT_ON
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#define ENB_OFF !ENB_ON
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#define TAD_OUT !TAD_IN
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#define IND_OUT !IND_IN
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#define DTD_OUT !DTD_IN
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//---------------------------------------------------------------------------
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//
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// Constant declarations (SCSI)
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//
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//---------------------------------------------------------------------------
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#define IN GPIO_INPUT
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#define OUT GPIO_OUTPUT
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#define ON TRUE
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#define OFF FALSE
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//---------------------------------------------------------------------------
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//
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// Constant declarations (bus control timing)
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//
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//---------------------------------------------------------------------------
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// SCSI Bus timings taken from:
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// https://www.staff.uni-mainz.de/tacke/scsi/SCSI2-05.html
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#define SCSI_DELAY_ARBITRATION_DELAY_NS 2400
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#define SCSI_DELAY_ASSERTION_PERIOD_NS 90
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#define SCSI_DELAY_BUS_CLEAR_DELAY_NS 800
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#define SCSI_DELAY_BUS_FREE_DELAY_NS 800
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#define SCSI_DELAY_BUS_SET_DELAY_NS 1800
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#define SCSI_DELAY_BUS_SETTLE_DELAY_NS 400
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#define SCSI_DELAY_CABLE_SKEW_DELAY_NS 10
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#define SCSI_DELAY_DATA_RELEASE_DELAY_NS 400
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#define SCSI_DELAY_DESKEW_DELAY_NS 45
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#define SCSI_DELAY_DISCONNECTION_DELAY_US 200
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#define SCSI_DELAY_HOLD_TIME_NS 45
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#define SCSI_DELAY_NEGATION_PERIOD_NS 90
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#define SCSI_DELAY_POWER_ON_TO_SELECTION_TIME_S 10 // (recommended)
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#define SCSI_DELAY_RESET_TO_SELECTION_TIME_US (250*1000) // (recommended)
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#define SCSI_DELAY_RESET_HOLD_TIME_US 25
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#define SCSI_DELAY_SELECTION_ABORT_TIME_US 200
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#define SCSI_DELAY_SELECTION_TIMEOUT_DELAY_NS (250*1000) // (recommended)
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#define SCSI_DELAY_FAST_ASSERTION_PERIOD_NS 30
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#define SCSI_DELAY_FAST_CABLE_SKEW_DELAY_NS 5
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#define SCSI_DELAY_FAST_DESKEW_DELAY_NS 20
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#define SCSI_DELAY_FAST_HOLD_TIME_NS 10
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#define SCSI_DELAY_FAST_NEGATION_PERIOD_NS 30
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// The DaynaPort SCSI Link do a short delay in the middle of transfering
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// a packet. This is the number of uS that will be delayed between the
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// header and the actual data.
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#define SCSI_DELAY_SEND_DATA_DAYNAPORT_US 100
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//---------------------------------------------------------------------------
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//
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// Class definition
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//
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//---------------------------------------------------------------------------
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class GPIOBUS : public BUS
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{
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public:
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// Basic Functions
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GPIOBUS();
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// Constructor
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virtual ~GPIOBUS();
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// Destructor
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BOOL Init(mode_e mode = TARGET);
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// Initialization
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void Reset();
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// Reset
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void Cleanup();
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// Cleanup
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//---------------------------------------------------------------------------
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//
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// Bus signal acquisition
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//
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//---------------------------------------------------------------------------
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inline DWORD Aquire() override
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{
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#if defined(__x86_64__) || defined(__X86__)
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// Only used for development/debugging purposes. Isn't really applicable
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// to any real-world RaSCSI application
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return 0;
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#else
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signals = *level;
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#if SIGNAL_CONTROL_MODE < 2
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// Invert if negative logic (internal processing is unified to positive logic)
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signals = ~signals;
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#endif // SIGNAL_CONTROL_MODE
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return signals;
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#endif // ifdef __x86_64__ || __X86__
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}
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void SetENB(BOOL ast);
|
||
// Set ENB signal
|
||
|
||
bool GetBSY() override;
|
||
// Get BSY signal
|
||
void SetBSY(bool ast) override;
|
||
// Set BSY signal
|
||
|
||
BOOL GetSEL() override;
|
||
// Get SEL signal
|
||
void SetSEL(BOOL ast) override;
|
||
// Set SEL signal
|
||
|
||
BOOL GetATN() override;
|
||
// Get ATN signal
|
||
void SetATN(BOOL ast) override;
|
||
// Set ATN signal
|
||
|
||
BOOL GetACK() override;
|
||
// Get ACK signal
|
||
void SetACK(BOOL ast) override;
|
||
// Set ACK signal
|
||
|
||
BOOL GetACT();
|
||
// Get ACT signal
|
||
void SetACT(BOOL ast);
|
||
// Set ACT signal
|
||
|
||
BOOL GetRST() override;
|
||
// Get RST signal
|
||
void SetRST(BOOL ast) override;
|
||
// Set RST signal
|
||
|
||
BOOL GetMSG() override;
|
||
// Get MSG signal
|
||
void SetMSG(BOOL ast) override;
|
||
// Set MSG signal
|
||
|
||
BOOL GetCD() override;
|
||
// Get CD signal
|
||
void SetCD(BOOL ast) override;
|
||
// Set CD signal
|
||
|
||
BOOL GetIO() override;
|
||
// Get IO signal
|
||
void SetIO(BOOL ast) override;
|
||
// Set IO signal
|
||
|
||
BOOL GetREQ() override;
|
||
// Get REQ signal
|
||
void SetREQ(BOOL ast) override;
|
||
// Set REQ signal
|
||
|
||
BYTE GetDAT() override;
|
||
// Get DAT signal
|
||
void SetDAT(BYTE dat) override;
|
||
// Set DAT signal
|
||
BOOL GetDP() override;
|
||
// Get Data parity signal
|
||
int CommandHandShake(BYTE *buf) override;
|
||
// Command receive handshake
|
||
int ReceiveHandShake(BYTE *buf, int count) override;
|
||
// Data receive handshake
|
||
int SendHandShake(BYTE *buf, int count, int delay_after_bytes) override;
|
||
// Data transmission handshake
|
||
|
||
static BUS::phase_t GetPhaseRaw(DWORD raw_data);
|
||
// Get the phase based on raw data
|
||
|
||
static int GetCommandByteCount(BYTE opcode);
|
||
|
||
#ifdef USE_SEL_EVENT_ENABLE
|
||
// SEL signal interrupt
|
||
int PollSelectEvent();
|
||
// SEL signal event polling
|
||
void ClearSelectEvent();
|
||
// Clear SEL signal event
|
||
#endif // USE_SEL_EVENT_ENABLE
|
||
|
||
private:
|
||
// SCSI I/O signal control
|
||
void MakeTable();
|
||
// Create work data
|
||
void SetControl(int pin, BOOL ast);
|
||
// Set Control Signal
|
||
void SetMode(int pin, int mode);
|
||
// Set SCSI I/O mode
|
||
BOOL GetSignal(int pin);
|
||
// Get SCSI input signal value
|
||
void SetSignal(int pin, BOOL ast);
|
||
// Set SCSI output signal value
|
||
BOOL WaitSignal(int pin, BOOL ast);
|
||
// Wait for a signal to change
|
||
// Interrupt control
|
||
void DisableIRQ();
|
||
// IRQ Disabled
|
||
void EnableIRQ();
|
||
// IRQ Enabled
|
||
|
||
// GPIO pin functionality settings
|
||
void PinConfig(int pin, int mode);
|
||
// GPIO pin direction setting
|
||
void PullConfig(int pin, int mode);
|
||
// GPIO pin pull up/down resistor setting
|
||
void PinSetSignal(int pin, BOOL ast);
|
||
// Set GPIO output signal
|
||
void DrvConfig(DWORD drive);
|
||
// Set GPIO drive strength
|
||
|
||
|
||
mode_e actmode; // Operation mode
|
||
|
||
DWORD baseaddr; // Base address
|
||
|
||
int rpitype; // Type of Raspberry Pi
|
||
|
||
volatile DWORD *gpio; // GPIO register
|
||
|
||
volatile DWORD *pads; // PADS register
|
||
|
||
volatile DWORD *level; // GPIO input level
|
||
|
||
volatile DWORD *irpctl; // Interrupt control register
|
||
|
||
volatile DWORD irptenb; // Interrupt enabled state
|
||
|
||
volatile DWORD *qa7regs; // QA7 register
|
||
|
||
volatile int tintcore; // Interupt control target CPU.
|
||
|
||
volatile DWORD tintctl; // Interupt control
|
||
|
||
volatile DWORD giccpmr; // GICC priority setting
|
||
|
||
volatile DWORD *gicd; // GIC Interrupt distributor register
|
||
|
||
volatile DWORD *gicc; // GIC CPU interface register
|
||
|
||
DWORD gpfsel[4]; // GPFSEL0-4 backup values
|
||
|
||
DWORD signals; // All bus signals
|
||
|
||
#ifdef USE_SEL_EVENT_ENABLE
|
||
struct gpioevent_request selevreq = {}; // SEL signal event request
|
||
|
||
int epfd; // epoll file descriptor
|
||
#endif // USE_SEL_EVENT_ENABLE
|
||
|
||
#if SIGNAL_CONTROL_MODE == 0
|
||
DWORD tblDatMsk[3][256]; // Data mask table
|
||
|
||
DWORD tblDatSet[3][256]; // Data setting table
|
||
#else
|
||
DWORD tblDatMsk[256]; // Data mask table
|
||
|
||
DWORD tblDatSet[256]; // Table setting table
|
||
#endif
|
||
|
||
static const int SignalTable[19]; // signal table
|
||
};
|
||
|
||
//===========================================================================
|
||
//
|
||
// System timer
|
||
//
|
||
//===========================================================================
|
||
class SysTimer
|
||
{
|
||
public:
|
||
static void Init(DWORD *syst, DWORD *armt);
|
||
// Initialization
|
||
static DWORD GetTimerLow();
|
||
// Get system timer low byte
|
||
static DWORD GetTimerHigh();
|
||
// Get system timer high byte
|
||
static void SleepNsec(DWORD nsec);
|
||
// Sleep for N nanoseconds
|
||
static void SleepUsec(DWORD usec);
|
||
// Sleep for N microseconds
|
||
|
||
private:
|
||
static volatile DWORD *systaddr;
|
||
// System timer address
|
||
static volatile DWORD *armtaddr;
|
||
// ARM timer address
|
||
static volatile DWORD corefreq;
|
||
// Core frequency
|
||
};
|
||
|
||
#endif // gpiobus_h
|