mirror of
https://github.com/akuker/RASCSI.git
synced 2025-08-07 15:25:54 +00:00
e64c2f7254
* moved gpiobus * moved gpiobus and systimer into hardware abstraction layer * split up gpiobus by connection type * merge develop changes * revert compiler setting change * registers working * updates * updates * Revert "updates" This reverts commit0134b81061. * Revert "updates" This reverts commit4bf0416ab4. * Revert "registers working" This reverts commitf5ee073eaf. * Address comment in #843. Restore -Wextra Co-authored-by: Tony Kuker <akuker@gmail.com>
502 lines
15 KiB
C++
502 lines
15 KiB
C++
//---------------------------------------------------------------------------
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//
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// SCSI Target Emulator RaSCSI Reloaded
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// for Raspberry Pi
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//
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// Powered by XM6 TypeG Technology.
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// Copyright (C) 2016-2020 GIMONS
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// [ GPIO-SCSI bus ]
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//
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//---------------------------------------------------------------------------
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#pragma once
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#include "config.h"
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#include "scsi.h"
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//---------------------------------------------------------------------------
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//
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// Connection method definitions
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//
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//---------------------------------------------------------------------------
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//#define CONNECT_TYPE_STANDARD // Standard (SCSI logic, standard pin assignment)
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//#define CONNECT_TYPE_FULLSPEC // Full spec (SCSI logic, standard pin assignment)
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//#define CONNECT_TYPE_AIBOM // AIBOM version (positive logic, unique pin assignment)
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//#define CONNECT_TYPE_GAMERNIUM // GAMERnium.com version (standard logic, unique pin assignment)
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#if defined CONNECT_TYPE_STANDARD
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#include "hal/gpiobus_standard.h"
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#elif defined CONNECT_TYPE_FULLSPEC
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#include "hal/gpiobus_fullspec.h"
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#elif defined CONNECT_TYPE_AIBOM
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#include "hal/gpiobus_aibom.h"
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#elif defined CONNECT_TYPE_GAMERNIUM
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#include "hal/gpiobus_gamernium.h"
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#else
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#error Invalid connection type or none specified
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#endif
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//---------------------------------------------------------------------------
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//
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// Signal control logic and pin assignment customization
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//
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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//
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// SIGNAL_CONTROL_MODE: Signal control mode selection
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// You can customize the signal control logic from Version 1.22
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//
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// 0:SCSI logical specification
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// Conversion board using 74LS641-1 etc. directly connected or published on HP
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// True : 0V
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// False : Open collector output (disconnect from bus)
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//
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// 1:Negative logic specification (when using conversion board for negative logic -> SCSI logic)
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// There is no conversion board with this specification at this time
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// True : 0V -> (CONVERT) -> 0V
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// False : 3.3V -> (CONVERT) -> Open collector output
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//
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// 2:Positive logic specification (when using the conversion board for positive logic -> SCSI logic)
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// RaSCSI Adapter Rev.C @132sync etc.
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//
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// True : 3.3V -> (CONVERT) -> 0V
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// False : 0V -> (CONVERT) -> Open collector output
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//
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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//
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// Control signal pin assignment setting
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// GPIO pin mapping table for control signals.
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//
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// Control signal:
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// PIN_ACT
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// Signal that indicates the status of processing SCSI command.
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// PIN_ENB
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// Signal that indicates the valid signal from start to finish.
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// PIN_TAD
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// Signal that indicates the input/output direction of the target signal (BSY,IO,CD,MSG,REG).
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// PIN_IND
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// Signal that indicates the input/output direction of the initiator signal (SEL, ATN, RST, ACK).
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// PIN_DTD
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// Signal that indicates the input/output direction of the data lines (DT0...DT7,DP).
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//
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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//
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// Control signal output logic
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// 0V:FALSE 3.3V:TRUE
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//
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// ACT_ON
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// PIN_ACT signal
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// ENB_ON
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// PIN_ENB signal
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// TAD_IN
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// PIN_TAD This is the logic when inputting.
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// IND_IN
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// PIN_ENB This is the logic when inputting.
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// DTD_IN
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// PIN_ENB This is the logic when inputting.
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//
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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//
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// SCSI signal pin assignment setting
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// GPIO pin mapping table for SCSI signals.
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// PIN_DT0～PIN_SEL
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//
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//---------------------------------------------------------------------------
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#define ALL_SCSI_PINS \
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((1<<PIN_DT0)|\
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(1<<PIN_DT1)|\
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(1<<PIN_DT2)|\
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(1<<PIN_DT3)|\
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(1<<PIN_DT4)|\
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(1<<PIN_DT5)|\
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(1<<PIN_DT6)|\
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(1<<PIN_DT7)|\
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(1<<PIN_DP)|\
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(1<<PIN_ATN)|\
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(1<<PIN_RST)|\
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(1<<PIN_ACK)|\
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(1<<PIN_REQ)|\
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(1<<PIN_MSG)|\
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(1<<PIN_CD)|\
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(1<<PIN_IO)|\
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(1<<PIN_BSY)|\
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(1<<PIN_SEL))
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//---------------------------------------------------------------------------
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//
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// Constant declarations (GPIO)
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//
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//---------------------------------------------------------------------------
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#define SYST_OFFSET 0x00003000
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#define IRPT_OFFSET 0x0000B200
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#define ARMT_OFFSET 0x0000B400
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#define PADS_OFFSET 0x00100000
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#define GPIO_OFFSET 0x00200000
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#define QA7_OFFSET 0x01000000
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#define GPIO_INPUT 0
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#define GPIO_OUTPUT 1
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#define GPIO_PULLNONE 0
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#define GPIO_PULLDOWN 1
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#define GPIO_PULLUP 2
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#define GPIO_FSEL_0 0
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#define GPIO_FSEL_1 1
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#define GPIO_FSEL_2 2
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#define GPIO_FSEL_3 3
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#define GPIO_SET_0 7
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#define GPIO_CLR_0 10
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#define GPIO_LEV_0 13
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#define GPIO_EDS_0 16
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#define GPIO_REN_0 19
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#define GPIO_FEN_0 22
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#define GPIO_HEN_0 25
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#define GPIO_LEN_0 28
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#define GPIO_AREN_0 31
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#define GPIO_AFEN_0 34
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#define GPIO_PUD 37
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#define GPIO_CLK_0 38
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#define GPIO_GPPINMUXSD 52
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#define GPIO_PUPPDN0 57
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#define GPIO_PUPPDN1 58
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#define GPIO_PUPPDN3 59
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#define GPIO_PUPPDN4 60
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#define PAD_0_27 11
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#define SYST_CS 0
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#define SYST_CLO 1
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#define SYST_CHI 2
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#define SYST_C0 3
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#define SYST_C1 4
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#define SYST_C2 5
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#define SYST_C3 6
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#define ARMT_LOAD 0
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#define ARMT_VALUE 1
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#define ARMT_CTRL 2
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#define ARMT_CLRIRQ 3
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#define ARMT_RAWIRQ 4
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#define ARMT_MSKIRQ 5
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#define ARMT_RELOAD 6
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#define ARMT_PREDIV 7
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#define ARMT_FREERUN 8
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#define IRPT_PND_IRQ_B 0
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#define IRPT_PND_IRQ_1 1
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#define IRPT_PND_IRQ_2 2
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#define IRPT_FIQ_CNTL 3
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#define IRPT_ENB_IRQ_1 4
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#define IRPT_ENB_IRQ_2 5
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#define IRPT_ENB_IRQ_B 6
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#define IRPT_DIS_IRQ_1 7
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#define IRPT_DIS_IRQ_2 8
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#define IRPT_DIS_IRQ_B 9
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#define QA7_CORE0_TINTC 16
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#define GPIO_IRQ (32 + 20) // GPIO3
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#define GPIO_INEDGE ((1 << PIN_BSY) | \
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(1 << PIN_SEL) | \
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(1 << PIN_ATN) | \
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(1 << PIN_ACK) | \
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(1 << PIN_RST))
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#define GPIO_MCI ((1 << PIN_MSG) | \
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(1 << PIN_CD) | \
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(1 << PIN_IO))
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//---------------------------------------------------------------------------
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//
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// Constant declarations (GIC)
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//
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//---------------------------------------------------------------------------
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#define ARM_GICD_BASE 0xFF841000
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#define ARM_GICC_BASE 0xFF842000
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#define ARM_GIC_END 0xFF847FFF
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#define GICD_CTLR 0x000
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#define GICD_IGROUPR0 0x020
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#define GICD_ISENABLER0 0x040
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#define GICD_ICENABLER0 0x060
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#define GICD_ISPENDR0 0x080
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#define GICD_ICPENDR0 0x0A0
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#define GICD_ISACTIVER0 0x0C0
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#define GICD_ICACTIVER0 0x0E0
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#define GICD_IPRIORITYR0 0x100
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#define GICD_ITARGETSR0 0x200
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#define GICD_ICFGR0 0x300
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#define GICD_SGIR 0x3C0
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#define GICC_CTLR 0x000
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#define GICC_PMR 0x001
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#define GICC_IAR 0x003
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#define GICC_EOIR 0x004
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//---------------------------------------------------------------------------
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//
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// Constant declarations (GIC IRQ)
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//
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//---------------------------------------------------------------------------
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#define GIC_IRQLOCAL0 (16 + 14)
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#define GIC_GPIO_IRQ (32 + 116) // GPIO3
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//---------------------------------------------------------------------------
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//
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// Constant declarations (Control signals)
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//
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//---------------------------------------------------------------------------
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#define ACT_OFF !ACT_ON
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#define ENB_OFF !ENB_ON
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#define TAD_OUT !TAD_IN
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#define IND_OUT !IND_IN
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#define DTD_OUT !DTD_IN
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//---------------------------------------------------------------------------
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//
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// Constant declarations (SCSI)
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//
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//---------------------------------------------------------------------------
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#define IN GPIO_INPUT
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#define OUT GPIO_OUTPUT
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#define ON TRUE
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#define OFF FALSE
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//---------------------------------------------------------------------------
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//
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// Constant declarations (bus control timing)
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//
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//---------------------------------------------------------------------------
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// SCSI Bus timings taken from:
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// https://www.staff.uni-mainz.de/tacke/scsi/SCSI2-05.html
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const static int SCSI_DELAY_ARBITRATION_DELAY_NS = 2400;
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const static int SCSI_DELAY_ASSERTION_PERIOD_NS = 90;
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const static int SCSI_DELAY_BUS_CLEAR_DELAY_NS = 800;
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const static int SCSI_DELAY_BUS_FREE_DELAY_NS = 800;
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const static int SCSI_DELAY_BUS_SET_DELAY_NS = 1800;
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const static int SCSI_DELAY_BUS_SETTLE_DELAY_NS = 400;
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const static int SCSI_DELAY_CABLE_SKEW_DELAY_NS = 10;
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const static int SCSI_DELAY_DATA_RELEASE_DELAY_NS = 400;
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const static int SCSI_DELAY_DESKEW_DELAY_NS = 45;
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const static int SCSI_DELAY_DISCONNECTION_DELAY_US = 200;
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const static int SCSI_DELAY_HOLD_TIME_NS = 45;
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const static int SCSI_DELAY_NEGATION_PERIOD_NS = 90;
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const static int SCSI_DELAY_POWER_ON_TO_SELECTION_TIME_S = 10; // (recommended)
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const static int SCSI_DELAY_RESET_TO_SELECTION_TIME_US = 250*1000; // (recommended)
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const static int SCSI_DELAY_RESET_HOLD_TIME_US = 25;
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const static int SCSI_DELAY_SELECTION_ABORT_TIME_US = 200;
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const static int SCSI_DELAY_SELECTION_TIMEOUT_DELAY_NS = 250*1000; // (recommended)
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const static int SCSI_DELAY_FAST_ASSERTION_PERIOD_NS = 30;
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const static int SCSI_DELAY_FAST_CABLE_SKEW_DELAY_NS = 5;
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const static int SCSI_DELAY_FAST_DESKEW_DELAY_NS = 20;
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const static int SCSI_DELAY_FAST_HOLD_TIME_NS = 10;
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const static int SCSI_DELAY_FAST_NEGATION_PERIOD_NS = 30;
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// The DaynaPort SCSI Link do a short delay in the middle of transfering
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// a packet. This is the number of uS that will be delayed between the
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// header and the actual data.
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const static int SCSI_DELAY_SEND_DATA_DAYNAPORT_US = 100;
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//---------------------------------------------------------------------------
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//
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// Class definition
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//
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//---------------------------------------------------------------------------
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class GPIOBUS : public BUS
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{
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public:
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// Basic Functions
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GPIOBUS()= default;
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~GPIOBUS() final = default;
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// Destructor
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bool Init(mode_e mode = TARGET) override;
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// Initialization
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void Reset() override;
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// Reset
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void Cleanup() override;
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// Cleanup
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//---------------------------------------------------------------------------
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//
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// Bus signal acquisition
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//
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//---------------------------------------------------------------------------
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inline DWORD Acquire() override
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{
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#if defined(__x86_64__) || defined(__X86__)
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// Only used for development/debugging purposes. Isn't really applicable
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// to any real-world RaSCSI application
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return 0;
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#else
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signals = *level;
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#if SIGNAL_CONTROL_MODE < 2
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// Invert if negative logic (internal processing is unified to positive logic)
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signals = ~signals;
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#endif // SIGNAL_CONTROL_MODE
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return signals;
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#endif // ifdef __x86_64__ || __X86__
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}
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void SetENB(bool ast);
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// Set ENB signal
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bool GetBSY() const override;
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// Get BSY signal
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void SetBSY(bool ast) override;
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// Set BSY signal
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bool GetSEL() const override;
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// Get SEL signal
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void SetSEL(bool ast) override;
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// Set SEL signal
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bool GetATN() const override;
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// Get ATN signal
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void SetATN(bool ast) override;
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// Set ATN signal
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bool GetACK() const override;
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// Get ACK signal
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void SetACK(bool ast) override;
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// Set ACK signal
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bool GetACT() const;
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// Get ACT signal
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void SetACT(bool ast);
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// Set ACT signal
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bool GetRST() const override;
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// Get RST signal
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void SetRST(bool ast) override;
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// Set RST signal
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bool GetMSG() const override;
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// Get MSG signal
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void SetMSG(bool ast) override;
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// Set MSG signal
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bool GetCD() const override;
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// Get CD signal
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void SetCD(bool ast) override;
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// Set CD signal
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bool GetIO() override;
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// Get IO signal
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void SetIO(bool ast) override;
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// Set IO signal
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bool GetREQ() const override;
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// Get REQ signal
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void SetREQ(bool ast) override;
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// Set REQ signal
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BYTE GetDAT() override;
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// Get DAT signal
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void SetDAT(BYTE dat) override;
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// Set DAT signal
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bool GetDP() const override;
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// Get Data parity signal
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int CommandHandShake(BYTE *buf) override;
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// Command receive handshake
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int ReceiveHandShake(BYTE *buf, int count) override;
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// Data receive handshake
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int SendHandShake(BYTE *buf, int count, int delay_after_bytes) override;
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// Data transmission handshake
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static BUS::phase_t GetPhaseRaw(DWORD raw_data);
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// Get the phase based on raw data
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static int GetCommandByteCount(BYTE opcode);
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#ifdef USE_SEL_EVENT_ENABLE
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// SEL signal interrupt
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bool PollSelectEvent();
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// SEL signal event polling
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void ClearSelectEvent();
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// Clear SEL signal event
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#endif // USE_SEL_EVENT_ENABLE
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private:
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// SCSI I/O signal control
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void MakeTable();
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// Create work data
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void SetControl(int pin, bool ast);
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// Set Control Signal
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void SetMode(int pin, int mode);
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// Set SCSI I/O mode
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bool GetSignal(int pin) const override;
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// Get SCSI input signal value
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void SetSignal(int pin, bool ast) override;
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// Set SCSI output signal value
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bool WaitSignal(int pin, BOOL ast);
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// Wait for a signal to change
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// Interrupt control
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void DisableIRQ();
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// IRQ Disabled
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void EnableIRQ();
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// IRQ Enabled
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// GPIO pin functionality settings
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void PinConfig(int pin, int mode);
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// GPIO pin direction setting
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void PullConfig(int pin, int mode);
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// GPIO pin pull up/down resistor setting
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void PinSetSignal(int pin, bool ast);
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// Set GPIO output signal
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void DrvConfig(DWORD drive);
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// Set GPIO drive strength
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mode_e actmode = TARGET; // Operation mode
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uint32_t baseaddr = 0; // Base address
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int rpitype = 0; // Type of Raspberry Pi
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volatile uint32_t *gpio = nullptr; // GPIO register
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volatile uint32_t *pads = nullptr; // PADS register
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volatile uint32_t *level = nullptr; // GPIO input level
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volatile uint32_t *irpctl = nullptr; // Interrupt control register
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volatile uint32_t irptenb; // Interrupt enabled state
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volatile uint32_t *qa7regs = nullptr; // QA7 register
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volatile int tintcore; // Interupt control target CPU.
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volatile uint32_t tintctl; // Interupt control
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volatile uint32_t giccpmr; // GICC priority setting
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volatile uint32_t *gicd = nullptr; // GIC Interrupt distributor register
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volatile uint32_t *gicc = nullptr; // GIC CPU interface register
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DWORD gpfsel[4]; // GPFSEL0-4 backup values
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uint32_t signals = 0; // All bus signals
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#ifdef USE_SEL_EVENT_ENABLE
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struct gpioevent_request selevreq = {}; // SEL signal event request
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int epfd; // epoll file descriptor
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#endif // USE_SEL_EVENT_ENABLE
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#if SIGNAL_CONTROL_MODE == 0
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DWORD tblDatMsk[3][256]; // Data mask table
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DWORD tblDatSet[3][256]; // Data setting table
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#else
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DWORD tblDatMsk[256]; // Data mask table
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DWORD tblDatSet[256]; // Table setting table
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#endif
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static const int SignalTable[19]; // signal table
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};
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