#***************************************************************************

#sjplacer

#Version:            1.1

#Build Date:         Mar 26 2013 14:54:34

#File Generated:     Oct 26 2013 18:55:19

#Purpose:            

#Copyright (C) 2010-2011 by Softjin Technologies Pvt Ltd. All rights reserved.

#***************************************************************************

Executing : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\bin/sjplacer.exe --proj-name USB_Bootloader --netlist-vh2 USB_Bootloader_p.vh2 --arch-file C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\dev/psoc3/placer.ark --rrg-file C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\dev/psoc5/psoc5lp/route_arch-rrg.cydata --irq-file C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\dev/psoc5/psoc5lp/irqconn.cydata --drq-file C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\dev/psoc5/psoc5lp/dmaconn.cydata --dsi-conn-file C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\dev/psoc5/psoc5lp/dsiconn.cydata --pins-file PSoC5_PSoC5LP_100-TQFP.xml --lib-file USB_Bootloader_p.lib --sdc-file USB_Bootloader.sdc --io-pcf USB_Bootloader.pci --outdir .

		Softjin Techologies Placer, Version 1.1

Build Date : Jul 22 2013	11:20:09

D2004: Option and Settings Summary
=============================================================
Netlist vh2 file          - USB_Bootloader_p.vh2
Architecture file         - C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\dev/psoc3/placer.ark
Package                   - 
Defparam file             - 
SDC file                  - USB_Bootloader.sdc
Output directory          - .
Timing library            - USB_Bootloader_p.lib
IO Placement file         - USB_Bootloader.pci

D2050: Starting reading inputs for placer
=============================================================
D2065: Reading netlist file : "USB_Bootloader_p.vh2"
D2065: Reading arch file : "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\dev/psoc3/placer.ark"
D2051: Reading of inputs for placer completed successfully

D2053: Starting placement of the design
=============================================================

Phase 2
Phase 3
I2659: No Constrained paths were found. The placer will run in non-timing driven mode.

Design Statistics after Packing
    Number of Combinational MCs 	:	0
    Number of Sequential MCs    	:	0
    Number of DPs               	:	0
    Number of Controls          	:	0
    Number of Status            	:	0
    Number of SyncCells         	:	0
    Number of count7cells       	:	0

Device Utilization Summary after Packing
    Macrocells                  :	0/192
    UDBS                        :	0/24
    IOs                         :	20/72


D2088: Phase 3, elapsed time : 0.0 (sec)

Phase 4
D2088: Phase 4, elapsed time : 0.0 (sec)

Phase 5
D2088: Phase 5, elapsed time : 0.0 (sec)

Phase 8
D2088: Phase 8, elapsed time : 0.0 (sec)

D2054: Placement of the design completed successfully

I2076: Total run-time: 1.3 sec.

