mirror of
https://github.com/fhgwright/SCSI2SD.git
synced 2024-06-02 06:41:36 +00:00
Fix DMA transfer bug.
This commit is contained in:
Michael McMaster
parent
5bcd0c3a18
commit
092541dd02
11
readme.txt
11
readme.txt
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@ -45,15 +45,20 @@ Performance
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As currently implemented:
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Sequential read: 2.5MB/s Sequential write: 900kb/sec
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Transfer size: 512 2048 8192 65536
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-------------------------------------------------------
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read: 2MB/s 2.1MB/s 2.5MB/s 2.6MB/s
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write: 125kB/s 441kB/s 1.5MB/s 2.3MB/s
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-------------------------------------------------------
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Tested with a 16GB class 10 SD card, via the commands:
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# WRITE TEST
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sudo dd bs=8192 count=100 if=/dev/zero of=/dev/sdX oflag=dsync
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sudo dd bs=${SIZE} count=100 if=/dev/zero of=/dev/sdX oflag=dsync
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# READ TEST
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sudo dd bs=8192 count=100 if=/dev/sdX of=/dev/null
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sudo dd bs=${SIZE} count=100 if=/dev/sdX of=/dev/null
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Compatibility
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@ -84,28 +84,28 @@
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/* SCSI_CTL_PHASE */
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
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/* SCSI_Out_Bits */
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#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
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@ -630,34 +630,34 @@
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#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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/* SDCard_BSPIM */
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#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
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#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
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#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK
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#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
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#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
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#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
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#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
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#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
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#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
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#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
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#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
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#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
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#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
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#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL
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#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
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#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL
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#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
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#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
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#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK
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#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
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#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
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#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
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#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
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#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
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#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK
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#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
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#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
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#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
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#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL
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#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL
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#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
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#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
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#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
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#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
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#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
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#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL
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#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
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#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL
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#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
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#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
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#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK
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#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
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#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
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#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
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#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
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#define SDCard_BSPIM_RxStsReg__4__POS 4
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#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
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#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
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#define SDCard_BSPIM_RxStsReg__6__POS 6
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#define SDCard_BSPIM_RxStsReg__MASK 0x70u
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#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK
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#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
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#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST
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#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK
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#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
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#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
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#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
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#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL
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#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL
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#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST
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#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
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#define SDCard_BSPIM_TxStsReg__0__POS 0
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#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
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#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
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#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
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#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
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#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
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#define SDCard_BSPIM_TxStsReg__1__POS 1
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#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
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#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
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#define SDCard_BSPIM_TxStsReg__4__POS 4
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#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
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#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
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#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
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#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
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#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
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#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL
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#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL
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#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1
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#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1
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#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0
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#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1
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#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1
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#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0
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#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1
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#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL
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#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1
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#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0
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#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1
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#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK
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#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
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#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB05_06_A0
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB05_06_A1
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB05_06_D0
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB05_06_D1
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB05_06_F0
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB05_06_F1
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#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB05_A0_A1
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#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB05_A0
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#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB05_A1
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#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB05_D0_D1
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#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB05_D0
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#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB05_D1
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#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL
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#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB05_F0_F1
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#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB05_F0
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#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB05_F1
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#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
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#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
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/* USBFS_dp_int */
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#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
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#define SD_Data_Clk__PM_STBY_MSK 0x01u
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/* SD_Init_Clk */
|
||||
#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG3_CFG0
|
||||
#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG3_CFG1
|
||||
#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG3_CFG2
|
||||
#define SD_Init_Clk__CFG2_SRC_SEL_MASK 0x07u
|
||||
#define SD_Init_Clk__INDEX 0x03u
|
||||
#define SD_Init_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
|
||||
#define SD_Init_Clk__PM_ACT_MSK 0x08u
|
||||
#define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
|
||||
#define SD_Init_Clk__PM_STBY_MSK 0x08u
|
||||
|
||||
/* timer_clock */
|
||||
#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
|
||||
#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
|
||||
|
|
@ -1208,8 +1199,8 @@
|
|||
/* scsiTarget */
|
||||
#define scsiTarget_StatusReg__0__MASK 0x01u
|
||||
#define scsiTarget_StatusReg__0__POS 0
|
||||
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
|
||||
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
|
||||
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
|
||||
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST
|
||||
#define scsiTarget_StatusReg__1__MASK 0x02u
|
||||
#define scsiTarget_StatusReg__1__POS 1
|
||||
#define scsiTarget_StatusReg__2__MASK 0x04u
|
||||
|
|
@ -1219,9 +1210,9 @@
|
|||
#define scsiTarget_StatusReg__4__MASK 0x10u
|
||||
#define scsiTarget_StatusReg__4__POS 4
|
||||
#define scsiTarget_StatusReg__MASK 0x1Fu
|
||||
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK
|
||||
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
|
||||
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST
|
||||
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB00_MSK
|
||||
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL
|
||||
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB00_ST
|
||||
#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
|
||||
#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
|
||||
#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK
|
||||
|
|
@ -1268,9 +1259,6 @@
|
|||
#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
|
||||
/* SD_Clk_Ctl */
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__REMOVED 1u
|
||||
|
||||
/* USBFS_ep_0 */
|
||||
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
||||
#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -84,28 +84,28 @@
|
|||
/* SCSI_CTL_PHASE */
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
|
||||
|
||||
/* SCSI_Out_Bits */
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
|
||||
|
|
@ -630,34 +630,34 @@
|
|||
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
|
||||
|
||||
/* SDCard_BSPIM */
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK
|
||||
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK
|
||||
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
|
||||
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
|
||||
.set SDCard_BSPIM_RxStsReg__4__POS, 4
|
||||
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
|
||||
|
|
@ -665,13 +665,17 @@
|
|||
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
|
||||
.set SDCard_BSPIM_RxStsReg__6__POS, 6
|
||||
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
|
||||
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
|
||||
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK
|
||||
.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
|
||||
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
|
||||
.set SDCard_BSPIM_TxStsReg__0__POS, 0
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
|
||||
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
|
||||
.set SDCard_BSPIM_TxStsReg__1__POS, 1
|
||||
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
|
||||
|
|
@ -681,30 +685,28 @@
|
|||
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
|
||||
.set SDCard_BSPIM_TxStsReg__4__POS, 4
|
||||
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
|
||||
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
|
||||
.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1
|
||||
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB05_06_A0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB05_06_A1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB05_06_D0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB05_06_D1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB05_06_F0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB05_06_F1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB05_A0_A1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB05_A0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB05_A1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB05_D0_D1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB05_D0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB05_D1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB05_F0_F1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB05_F0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB05_F1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
|
||||
|
||||
/* USBFS_dp_int */
|
||||
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
|
|
@ -1183,17 +1185,6 @@
|
|||
.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
|
||||
.set SD_Data_Clk__PM_STBY_MSK, 0x01
|
||||
|
||||
/* SD_Init_Clk */
|
||||
.set SD_Init_Clk__CFG0, CYREG_CLKDIST_DCFG3_CFG0
|
||||
.set SD_Init_Clk__CFG1, CYREG_CLKDIST_DCFG3_CFG1
|
||||
.set SD_Init_Clk__CFG2, CYREG_CLKDIST_DCFG3_CFG2
|
||||
.set SD_Init_Clk__CFG2_SRC_SEL_MASK, 0x07
|
||||
.set SD_Init_Clk__INDEX, 0x03
|
||||
.set SD_Init_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2
|
||||
.set SD_Init_Clk__PM_ACT_MSK, 0x08
|
||||
.set SD_Init_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
|
||||
.set SD_Init_Clk__PM_STBY_MSK, 0x08
|
||||
|
||||
/* timer_clock */
|
||||
.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0
|
||||
.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1
|
||||
|
|
@ -1208,8 +1199,8 @@
|
|||
/* scsiTarget */
|
||||
.set scsiTarget_StatusReg__0__MASK, 0x01
|
||||
.set scsiTarget_StatusReg__0__POS, 0
|
||||
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
|
||||
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
|
||||
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
|
||||
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST
|
||||
.set scsiTarget_StatusReg__1__MASK, 0x02
|
||||
.set scsiTarget_StatusReg__1__POS, 1
|
||||
.set scsiTarget_StatusReg__2__MASK, 0x04
|
||||
|
|
@ -1219,9 +1210,9 @@
|
|||
.set scsiTarget_StatusReg__4__MASK, 0x10
|
||||
.set scsiTarget_StatusReg__4__POS, 4
|
||||
.set scsiTarget_StatusReg__MASK, 0x1F
|
||||
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK
|
||||
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
|
||||
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST
|
||||
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB00_MSK
|
||||
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
|
||||
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB00_ST
|
||||
.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
|
||||
.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
|
||||
.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK
|
||||
|
|
@ -1268,9 +1259,6 @@
|
|||
.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
|
||||
/* SD_Clk_Ctl */
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__REMOVED, 1
|
||||
|
||||
/* USBFS_ep_0 */
|
||||
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
|
||||
|
|
|
|||
|
|
@ -84,28 +84,28 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
|||
/* SCSI_CTL_PHASE */
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
|
||||
|
||||
/* SCSI_Out_Bits */
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
|
|
@ -630,34 +630,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
|||
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
/* SDCard_BSPIM */
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
|
||||
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_RxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
|
||||
|
|
@ -665,13 +665,17 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
|
|||
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
|
||||
SDCard_BSPIM_RxStsReg__6__POS EQU 6
|
||||
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
|
||||
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
|
||||
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
|
||||
SDCard_BSPIM_TxStsReg__0__POS EQU 0
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
|
||||
SDCard_BSPIM_TxStsReg__1__POS EQU 1
|
||||
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
|
||||
|
|
@ -681,30 +685,28 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
|
|||
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_TxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
|
||||
SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
|
||||
SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
|
||||
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0
|
||||
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1
|
||||
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0
|
||||
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB05_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB05_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1
|
||||
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB05_D0
|
||||
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB05_D1
|
||||
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB05_F0
|
||||
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB05_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
|
||||
|
||||
/* USBFS_dp_int */
|
||||
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
|
|
@ -1183,17 +1185,6 @@ SD_Data_Clk__PM_ACT_MSK EQU 0x01
|
|||
SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
|
||||
SD_Data_Clk__PM_STBY_MSK EQU 0x01
|
||||
|
||||
/* SD_Init_Clk */
|
||||
SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0
|
||||
SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1
|
||||
SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2
|
||||
SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07
|
||||
SD_Init_Clk__INDEX EQU 0x03
|
||||
SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
|
||||
SD_Init_Clk__PM_ACT_MSK EQU 0x08
|
||||
SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
|
||||
SD_Init_Clk__PM_STBY_MSK EQU 0x08
|
||||
|
||||
/* timer_clock */
|
||||
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
|
||||
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
|
||||
|
|
@ -1208,8 +1199,8 @@ timer_clock__PM_STBY_MSK EQU 0x04
|
|||
/* scsiTarget */
|
||||
scsiTarget_StatusReg__0__MASK EQU 0x01
|
||||
scsiTarget_StatusReg__0__POS EQU 0
|
||||
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
|
||||
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
|
||||
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
|
||||
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
|
||||
scsiTarget_StatusReg__1__MASK EQU 0x02
|
||||
scsiTarget_StatusReg__1__POS EQU 1
|
||||
scsiTarget_StatusReg__2__MASK EQU 0x04
|
||||
|
|
@ -1219,9 +1210,9 @@ scsiTarget_StatusReg__3__POS EQU 3
|
|||
scsiTarget_StatusReg__4__MASK EQU 0x10
|
||||
scsiTarget_StatusReg__4__POS EQU 4
|
||||
scsiTarget_StatusReg__MASK EQU 0x1F
|
||||
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
|
||||
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
|
||||
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
|
||||
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK
|
||||
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
|
||||
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST
|
||||
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
|
||||
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK
|
||||
|
|
@ -1268,9 +1259,6 @@ scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1
|
|||
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
|
||||
/* SD_Clk_Ctl */
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__REMOVED EQU 1
|
||||
|
||||
/* USBFS_ep_0 */
|
||||
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
|
|
|
|||
|
|
@ -84,28 +84,28 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
|||
; SCSI_CTL_PHASE
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
|
||||
|
||||
; SCSI_Out_Bits
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
|
|
@ -630,34 +630,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
|||
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
; SDCard_BSPIM
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
|
||||
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_RxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
|
||||
|
|
@ -665,13 +665,17 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
|
|||
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
|
||||
SDCard_BSPIM_RxStsReg__6__POS EQU 6
|
||||
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
|
||||
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
|
||||
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
|
||||
SDCard_BSPIM_TxStsReg__0__POS EQU 0
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
|
||||
SDCard_BSPIM_TxStsReg__1__POS EQU 1
|
||||
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
|
||||
|
|
@ -681,30 +685,28 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
|
|||
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_TxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
|
||||
SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
|
||||
SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
|
||||
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0
|
||||
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1
|
||||
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0
|
||||
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB05_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB05_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1
|
||||
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB05_D0
|
||||
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB05_D1
|
||||
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB05_F0
|
||||
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB05_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
|
||||
|
||||
; USBFS_dp_int
|
||||
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
|
|
@ -1183,17 +1185,6 @@ SD_Data_Clk__PM_ACT_MSK EQU 0x01
|
|||
SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
|
||||
SD_Data_Clk__PM_STBY_MSK EQU 0x01
|
||||
|
||||
; SD_Init_Clk
|
||||
SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0
|
||||
SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1
|
||||
SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2
|
||||
SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07
|
||||
SD_Init_Clk__INDEX EQU 0x03
|
||||
SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
|
||||
SD_Init_Clk__PM_ACT_MSK EQU 0x08
|
||||
SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
|
||||
SD_Init_Clk__PM_STBY_MSK EQU 0x08
|
||||
|
||||
; timer_clock
|
||||
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
|
||||
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
|
||||
|
|
@ -1208,8 +1199,8 @@ timer_clock__PM_STBY_MSK EQU 0x04
|
|||
; scsiTarget
|
||||
scsiTarget_StatusReg__0__MASK EQU 0x01
|
||||
scsiTarget_StatusReg__0__POS EQU 0
|
||||
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
|
||||
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
|
||||
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
|
||||
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
|
||||
scsiTarget_StatusReg__1__MASK EQU 0x02
|
||||
scsiTarget_StatusReg__1__POS EQU 1
|
||||
scsiTarget_StatusReg__2__MASK EQU 0x04
|
||||
|
|
@ -1219,9 +1210,9 @@ scsiTarget_StatusReg__3__POS EQU 3
|
|||
scsiTarget_StatusReg__4__MASK EQU 0x10
|
||||
scsiTarget_StatusReg__4__POS EQU 4
|
||||
scsiTarget_StatusReg__MASK EQU 0x1F
|
||||
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
|
||||
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
|
||||
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
|
||||
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK
|
||||
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
|
||||
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST
|
||||
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
|
||||
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK
|
||||
|
|
@ -1268,9 +1259,6 @@ scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1
|
|||
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
|
||||
; SD_Clk_Ctl
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__REMOVED EQU 1
|
||||
|
||||
; USBFS_ep_0
|
||||
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
|
|
|
|||
|
|
@ -21,9 +21,7 @@
|
|||
#include <cydisabledsheets.h>
|
||||
#include <SCSI_In_DBx_aliases.h>
|
||||
#include <SCSI_Out_DBx_aliases.h>
|
||||
#include <SD_Clk_Ctl.h>
|
||||
#include <SD_Data_Clk.h>
|
||||
#include <SD_Init_Clk.h>
|
||||
#include <SD_CD_aliases.h>
|
||||
#include <SD_CD.h>
|
||||
#include <SD_DAT2_aliases.h>
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
|
||||
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006577" bitWidth="8" desc="" />
|
||||
</block>
|
||||
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />
|
||||
</block>
|
||||
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
|
|
@ -62,11 +64,8 @@
|
|||
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
|
||||
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
|
||||
</block>
|
||||
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006577" bitWidth="8" desc="" />
|
||||
</block>
|
||||
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
|
|
@ -74,6 +73,7 @@
|
|||
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
</block>
|
||||
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
|
||||
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
|
|
@ -154,39 +154,36 @@
|
|||
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
|
||||
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
|
||||
</block>
|
||||
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_Init_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />
|
||||
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" />
|
||||
</block>
|
||||
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
</blockRegMap>
|
||||
Binary file not shown.
|
|
@ -1244,14 +1244,14 @@
|
|||
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
|
||||
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SD_Init_Clk" persistent="">
|
||||
<Hidden v="False" />
|
||||
<Hidden v="True" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
|
||||
<dependencies>
|
||||
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SD_Init_Clk.c" persistent=".\Generated_Source\PSoC5\SD_Init_Clk.c">
|
||||
<Hidden v="False" />
|
||||
<Hidden v="True" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="ARM_C_FILE" />
|
||||
<PropertyDeltas />
|
||||
|
|
@ -1260,7 +1260,7 @@
|
|||
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SD_Init_Clk.h" persistent=".\Generated_Source\PSoC5\SD_Init_Clk.h">
|
||||
<Hidden v="False" />
|
||||
<Hidden v="True" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="NONE" />
|
||||
<PropertyDeltas />
|
||||
|
|
@ -1304,14 +1304,14 @@
|
|||
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
|
||||
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SD_Clk_Ctl" persistent="">
|
||||
<Hidden v="False" />
|
||||
<Hidden v="True" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
|
||||
<dependencies>
|
||||
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SD_Clk_Ctl.c" persistent=".\Generated_Source\PSoC5\SD_Clk_Ctl.c">
|
||||
<Hidden v="False" />
|
||||
<Hidden v="True" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="ARM_C_FILE" />
|
||||
<PropertyDeltas />
|
||||
|
|
@ -1320,7 +1320,7 @@
|
|||
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SD_Clk_Ctl.h" persistent=".\Generated_Source\PSoC5\SD_Clk_Ctl.h">
|
||||
<Hidden v="False" />
|
||||
<Hidden v="True" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="NONE" />
|
||||
<PropertyDeltas />
|
||||
|
|
|
|||
|
|
@ -6,6 +6,27 @@
|
|||
<addressUnitBits>8</addressUnitBits>
|
||||
<width>32</width>
|
||||
<peripherals>
|
||||
<peripheral>
|
||||
<name>SCSI_Out_Ctl</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x40006577</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x1</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>SCSI_Out_Ctl_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_Out_Bits</name>
|
||||
<description>No description available</description>
|
||||
|
|
@ -319,27 +340,6 @@
|
|||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_Out_Ctl</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x40006577</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x1</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>SCSI_Out_Ctl_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>USBFS</name>
|
||||
<description>USBFS</description>
|
||||
|
|
@ -827,7 +827,7 @@
|
|||
<peripheral>
|
||||
<name>SCSI_CTL_PHASE</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x40006472</baseAddress>
|
||||
<baseAddress>0x40006475</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x1</size>
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -238,6 +238,7 @@ void configPoll()
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef MM_DEBUG
|
||||
void debugPoll()
|
||||
{
|
||||
if (!usbReady)
|
||||
|
|
@ -286,6 +287,7 @@ CY_ISR(debugTimerISR)
|
|||
debugPoll();
|
||||
CyExitCriticalSection(savedIntrStatus);
|
||||
}
|
||||
#endif
|
||||
|
||||
void debugInit()
|
||||
{
|
||||
|
|
|
|||
|
|
@ -463,6 +463,8 @@ void scsiDiskPoll()
|
|||
if (scsiDev.phase == DATA_IN &&
|
||||
transfer.currentBlock != transfer.blocks)
|
||||
{
|
||||
scsiEnterPhase(DATA_IN);
|
||||
|
||||
int totalSDSectors = transfer.blocks * SDSectorsPerSCSISector();
|
||||
uint32_t sdLBA = SCSISector2SD(transfer.lba);
|
||||
int buffers = sizeof(scsiDev.data) / SD_SECTOR_SIZE;
|
||||
|
|
@ -519,6 +521,8 @@ void scsiDiskPoll()
|
|||
else if (scsiDev.phase == DATA_OUT &&
|
||||
transfer.currentBlock != transfer.blocks)
|
||||
{
|
||||
scsiEnterPhase(DATA_OUT);
|
||||
|
||||
int totalSDSectors = transfer.blocks * SDSectorsPerSCSISector();
|
||||
int buffers = sizeof(scsiDev.data) / SD_SECTOR_SIZE;
|
||||
int prep = 0;
|
||||
|
|
|
|||
|
|
@ -20,7 +20,8 @@
|
|||
// Set this to true to log SCSI commands and status information via
|
||||
// USB HID packets. The can be captured and viewed in wireshark.
|
||||
// For windows users, capture using USBPcap http://desowin.org/usbpcap/
|
||||
#define MM_DEBUG 0
|
||||
//#define MM_DEBUG 1
|
||||
#undef MM_DEBUG
|
||||
|
||||
#include "geometry.h"
|
||||
#include "sense.h"
|
||||
|
|
|
|||
|
|
@ -647,8 +647,9 @@ int sdInit()
|
|||
|
||||
// Set the SPI clock for 400kHz transfers
|
||||
// 25MHz / 400kHz approx factor of 63.
|
||||
// The register contains (divider - 1)
|
||||
uint16_t clkDiv25MHz = SD_Data_Clk_GetDividerRegister();
|
||||
SD_Data_Clk_SetDivider(clkDiv25MHz * 63);
|
||||
SD_Data_Clk_SetDivider(((clkDiv25MHz + 1) * 63) - 1);
|
||||
// Wait for the clock to settle.
|
||||
CyDelayUs(1);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user