diff --git a/software/SCSI2SD/src/config.c b/software/SCSI2SD/src/config.c index 1a19dfb..5b4195c 100755 --- a/software/SCSI2SD/src/config.c +++ b/software/SCSI2SD/src/config.c @@ -195,6 +195,33 @@ scsiTestCommand() hidPacket_send(response, sizeof(response)); } +static void +deviceListCommand() +{ + int deviceCount; + S2S_Device** devices = s2s_GetDevices(&deviceCount); + + uint8_t response[16] = // Make larger if there can be more than 2 devices + { + deviceCount + }; + + int pos = 1; + + for (int i = 0; i < deviceCount; ++i) + { + response[pos++] = devices[i]->deviceType; + + uint32_t capacity = devices[i]->getCapacity(devices[i]); + response[pos++] = capacity >> 24; + response[pos++] = capacity >> 16; + response[pos++] = capacity >> 8; + response[pos++] = capacity; + } + + hidPacket_send(response, pos); +} + static void processCommand(const uint8_t* cmd, size_t cmdSize) { @@ -224,6 +251,10 @@ processCommand(const uint8_t* cmd, size_t cmdSize) scsiTestCommand(); break; + case S2S_CMD_DEV_LIST: + deviceListCommand(); + break; + case CONFIG_NONE: // invalid default: break; diff --git a/software/SCSI2SD/src/flash.c b/software/SCSI2SD/src/flash.c new file mode 100644 index 0000000..39affaa --- /dev/null +++ b/software/SCSI2SD/src/flash.c @@ -0,0 +1,160 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#include "device.h" +#include "flash.h" + +#include "config.h" +#include "led.h" +#include "time.h" + +typedef struct +{ + S2S_Device dev; + + S2S_Target targets[MAX_SCSI_TARGETS]; + + uint32_t capacity; // in 512 byte blocks + + // CFI info + uint8_t manufacturerID; + uint8_t deviceID[2]; + + +} SpiFlash; + +static void spiFlash_earlyInit(S2S_Device* dev); +static void spiFlash_init(S2S_Device* dev); +static S2S_Target* spiFlash_getTargets(S2S_Device* dev, int* count); +static uint32_t spiFlash_getCapacity(S2S_Device* dev); +static int spiFlash_pollMediaChange(S2S_Device* dev); +static void spiFlash_pollMediaBusy(S2S_Device* dev); + +SpiFlash spiFlash = { + { + spiFlash_earlyInit, + spiFlash_init, + spiFlash_getTargets, + spiFlash_getCapacity, + spiFlash_pollMediaChange, + spiFlash_pollMediaBusy, + 0, // initial mediaState + CONFIG_STOREDEVICE_FLASH + } +}; + +S2S_Device* spiFlashDevice = &(spiFlash.dev); + +// Read and write 1 byte. +static uint8_t spiFlashByte(uint8_t value) +{ + NOR_SPI_WriteTxData(value); + while (!(NOR_SPI_ReadRxStatus() & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) {} + return NOR_SPI_ReadRxData(); +} + +static void spiFlash_earlyInit(S2S_Device* dev) +{ + SpiFlash* spiFlash = (SpiFlash*)dev; + + for (int i = 0; i < MAX_SCSI_TARGETS; ++i) + { + spiFlash->targets[i].device = dev; + + const S2S_TargetCfg* cfg = getConfigByIndex(i); + if (cfg->storageDevice == CONFIG_STOREDEVICE_FLASH) + { + spiFlash->targets[i].cfg = (S2S_TargetCfg*)cfg; + } + else + { + spiFlash->targets[i].cfg = NULL; + } + } + + // Don't require the host to send us a START STOP UNIT command + spiFlash->dev.mediaState = MEDIA_STARTED; +} + +static void spiFlash_init(S2S_Device* dev) +{ + SpiFlash* spiFlash = (SpiFlash*)dev; + spiFlash->capacity = 0; + + nNOR_WP_Write(0); // Enable Write Protect + nNOR_CS_Write(1); // Deselect + + NOR_SPI_Start(); + CyDelayUs(1); + + nNOR_CS_Write(0); // Select + + // JEDEC standard "Read Identification" command + // returns CFI information + spiFlashByte(0x9F); + + // 1 byte manufacturer ID + spiFlash->manufacturerID = spiFlashByte(0xFF); + + // 2 bytes device ID + spiFlash->deviceID[0] = spiFlashByte(0xFF); + spiFlash->deviceID[1] = spiFlashByte(0xFF); + + uint8_t bytesFollowing = spiFlashByte(0xFF); + + // Chances are this says 0, which means up to 512 bytes. + // But ignore it for now and just get the capacity. + for (int i = 0; i < 0x23; ++i) + { + spiFlashByte(0xFF); + } + + // Capacity is 2^n at offset 0x27 + //spiFlash->capacity = (1 << spiFlashByte(0xFF)) / 512; + // Record value in 512-byte sectors. + spiFlash->capacity = 1 << (spiFlashByte(0xFF) - 9); + + // Don't bother reading the rest. Deselecting will cancel the command. + + nNOR_CS_Write(1); // Deselect + +} + +static S2S_Target* spiFlash_getTargets(S2S_Device* dev, int* count) +{ + SpiFlash* spiFlash = (SpiFlash*)dev; + *count = MAX_SCSI_TARGETS; + return spiFlash->targets; +} + +static uint32_t spiFlash_getCapacity(S2S_Device* dev) +{ + SpiFlash* spiFlash = (SpiFlash*)dev; + return spiFlash->capacity; +} + +static int spiFlash_pollMediaChange(S2S_Device* dev) +{ + // Non-removable + return 0; +} + +static void spiFlash_pollMediaBusy(S2S_Device* dev) +{ + // Non-removable +} + diff --git a/software/SCSI2SD/src/flash.h b/software/SCSI2SD/src/flash.h new file mode 100644 index 0000000..5daf3ba --- /dev/null +++ b/software/SCSI2SD/src/flash.h @@ -0,0 +1,25 @@ +// Copyright (C) 2020 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#ifndef S2S_FLASH_H +#define S2S_FLASH_H + +#include "storedevice.h" + +extern S2S_Device* spiFlashDevice; + + +#endif diff --git a/software/SCSI2SD/src/main.c b/software/SCSI2SD/src/main.c index 0349c77..5e93e70 100755 --- a/software/SCSI2SD/src/main.c +++ b/software/SCSI2SD/src/main.c @@ -61,7 +61,7 @@ int main() ++delaySeconds; } - sdCheckPresent(); + s2s_deviceInit(); while (1) { diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c index edf4cb6..b25bf13 100755 --- a/software/SCSI2SD/src/scsi.c +++ b/software/SCSI2SD/src/scsi.c @@ -665,11 +665,14 @@ static void process_SelectionPhase() S2S_Target* target = NULL; for (int testIdx = 0; testIdx < 8; ++testIdx) { - target = s2s_DeviceFindByScsiId(testIdx); - if (target) - { - break; - } + if (mask & (1 << testIdx)) + { + target = s2s_DeviceFindByScsiId(testIdx); + if (target) + { + break; + } + } } sel &= (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL); @@ -1052,11 +1055,11 @@ void scsiInit() scsiDev.compatMode = COMPAT_UNKNOWN; int deviceCount; - S2S_Device* allDevices = s2s_GetDevices(&deviceCount); + S2S_Device** allDevices = s2s_GetDevices(&deviceCount); for (int devIdx = 0; devIdx < deviceCount; ++devIdx) { int targetCount; - S2S_Target* targets = allDevices[devIdx].getTargets(allDevices + devIdx, &targetCount); + S2S_Target* targets = allDevices[devIdx]->getTargets(allDevices[devIdx], &targetCount); for (int i = 0; i < targetCount; ++i) { @@ -1068,7 +1071,10 @@ void scsiInit() state->sense.code = NO_SENSE; state->sense.asc = NO_ADDITIONAL_SENSE_INFORMATION; - state->bytesPerSector = targets[i].cfg->bytesPerSector; + if (targets[i].cfg) + { + state->bytesPerSector = targets[i].cfg->bytesPerSector; + } } } } diff --git a/software/SCSI2SD/src/sd.c b/software/SCSI2SD/src/sd.c index a16ad50..abeac8e 100755 --- a/software/SCSI2SD/src/sd.c +++ b/software/SCSI2SD/src/sd.c @@ -29,6 +29,7 @@ #include static void sd_earlyInit(S2S_Device* dev); +static void sd_deviceInit(S2S_Device* dev); static S2S_Target* sd_getTargets(S2S_Device* dev, int* count); static uint32_t sd_getCapacity(S2S_Device* dev); static int sd_pollMediaChange(S2S_Device* dev); @@ -38,10 +39,13 @@ static void sd_pollMediaBusy(S2S_Device* dev); SdCard sdCard = { { sd_earlyInit, + sd_deviceInit, sd_getTargets, sd_getCapacity, sd_pollMediaChange, - sd_pollMediaBusy + sd_pollMediaBusy, + 0, // initial mediaState + CONFIG_STOREDEVICE_SD } }; S2S_Device* sdDevice = &(sdCard.dev); @@ -1038,13 +1042,26 @@ static void sd_earlyInit(S2S_Device* dev) for (int i = 0; i < MAX_SCSI_TARGETS; ++i) { sdCardDevice->targets[i].device = dev; - sdCardDevice->targets[i].cfg = getConfigByIndex(i); + + const S2S_TargetCfg* cfg = getConfigByIndex(i); + if (cfg->storageDevice == CONFIG_STOREDEVICE_SD) + { + sdCardDevice->targets[i].cfg = (S2S_TargetCfg*)cfg; + } + else + { + sdCardDevice->targets[i].cfg = NULL; + } } sdCardDevice->lastPollMediaTime = getTime_ms(); // Don't require the host to send us a START STOP UNIT command sdCardDevice->dev.mediaState = MEDIA_STARTED; +} +static void sd_deviceInit(S2S_Device* dev) +{ + sdCheckPresent(); } static S2S_Target* sd_getTargets(S2S_Device* dev, int* count) diff --git a/software/SCSI2SD/src/storedevice.c b/software/SCSI2SD/src/storedevice.c index a6b0173..3b93d36 100644 --- a/software/SCSI2SD/src/storedevice.c +++ b/software/SCSI2SD/src/storedevice.c @@ -16,6 +16,12 @@ // along with SCSI2SD. If not, see . #include "storedevice.h" +#include "device.h" + +#ifdef NOR_SPI_DATA_WIDTH +#include "flash.h" +#endif + #include "sd.h" #include @@ -24,15 +30,16 @@ S2S_Target* s2s_DeviceFindByScsiId(int scsiId) { int deviceCount; - S2S_Device* devices = s2s_GetDevices(&deviceCount); + S2S_Device** devices = s2s_GetDevices(&deviceCount); for (int deviceIdx = 0; deviceIdx < deviceCount; ++deviceIdx) { int targetCount; - S2S_Target* targets = devices[deviceIdx].getTargets(devices + deviceIdx, &targetCount); + S2S_Target* targets = devices[deviceIdx]->getTargets(devices[deviceIdx], &targetCount); for (int targetIdx = 0; targetIdx < targetCount; ++targetIdx) { S2S_Target* target = targets + targetIdx; if (target && + target->cfg && (target->cfg->scsiId & CONFIG_TARGET_ENABLED) && ((target->cfg->scsiId & CONFIG_TARGET_ID_BITS) == scsiId)) { @@ -44,19 +51,38 @@ S2S_Target* s2s_DeviceFindByScsiId(int scsiId) return NULL; } -S2S_Device* s2s_GetDevices(int* count) +S2S_Device** s2s_GetDevices(int* count) { - *count = 1; - return sdDevice; + static S2S_Device* allDevices[2]; + + *count = 1; + allDevices[0] = sdDevice; + + #ifdef NOR_SPI_DATA_WIDTH + *count = 2; + allDevices[0] = spiFlashDevice; + #endif + + return &allDevices; } void s2s_deviceEarlyInit() { int count; - S2S_Device* devices = s2s_GetDevices(&count); + S2S_Device** devices = s2s_GetDevices(&count); for (int i = 0; i < count; ++i) { - devices[i].earlyInit(&(devices[i])); + devices[i]->earlyInit(devices[i]); + } +} + +void s2s_deviceInit() +{ + int count; + S2S_Device** devices = s2s_GetDevices(&count); + for (int i = 0; i < count; ++i) + { + devices[i]->init(devices[i]); } } @@ -64,10 +90,10 @@ int s2s_pollMediaChange() { int result = 0; int count; - S2S_Device* devices = s2s_GetDevices(&count); + S2S_Device** devices = s2s_GetDevices(&count); for (int i = 0; i < count; ++i) { - int devResult = devices[i].pollMediaChange(&(devices[i])); + int devResult = devices[i]->pollMediaChange(devices[i]); result = result || devResult; } return result; diff --git a/software/SCSI2SD/src/storedevice.h b/software/SCSI2SD/src/storedevice.h index 8d39cbd..a394ef6 100644 --- a/software/SCSI2SD/src/storedevice.h +++ b/software/SCSI2SD/src/storedevice.h @@ -66,6 +66,7 @@ struct S2S_TargetStruct struct S2S_DeviceStruct { void (*earlyInit)(S2S_Device* dev); + void (*init)(S2S_Device* dev); S2S_Target* (*getTargets)(S2S_Device* dev, int* count); @@ -76,13 +77,15 @@ struct S2S_DeviceStruct void (*pollMediaBusy)(S2S_Device* dev); MEDIA_STATE mediaState; + CONFIG_STOREDEVICE deviceType; }; S2S_Target* s2s_DeviceFindByScsiId(int scsiId); -S2S_Device* s2s_GetDevices(int* count); +S2S_Device** s2s_GetDevices(int* count); void s2s_deviceEarlyInit(); +void s2s_deviceInit(); int s2s_pollMediaChange(); #endif diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 6704c4a..601f1b7 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -424,34 +424,34 @@ #define NOR_SO__SLW CYREG_PRT15_SLW /* SDCard */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -459,13 +459,9 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB04_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB04_ST #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 @@ -483,12 +479,14 @@ #define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 #define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 #define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 +#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u #define SDCard_BSPIM_TxStsReg__2__POS 2 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u @@ -496,9 +494,9 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB06_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB06_ST +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST /* SD_SCK */ #define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE1 @@ -534,30 +532,6 @@ #define SD_SCK__SHIFT 1u #define SD_SCK__SLW CYREG_PRT3_SLW -/* NOR_CTL */ -#define NOR_CTL_Sync_ctrl_reg__0__MASK 0x01u -#define NOR_CTL_Sync_ctrl_reg__0__POS 0 -#define NOR_CTL_Sync_ctrl_reg__1__MASK 0x02u -#define NOR_CTL_Sync_ctrl_reg__1__POS 1 -#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL -#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL -#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL -#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL -#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK -#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK -#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK -#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK -#define NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define NOR_CTL_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB06_CTL -#define NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL -#define NOR_CTL_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB06_CTL -#define NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL -#define NOR_CTL_Sync_ctrl_reg__MASK 0x03u -#define NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define NOR_CTL_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB06_MSK - /* NOR_SCK */ #define NOR_SCK__0__INTTYPE CYREG_PICU3_INTTYPE7 #define NOR_SCK__0__MASK 0x80u @@ -593,34 +567,34 @@ #define NOR_SCK__SLW CYREG_PRT3_SLW /* NOR_SPI */ -#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK -#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK -#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK -#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK -#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL -#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB08_CTL -#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL -#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB08_CTL -#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL -#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB08_MSK -#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST -#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB08_MSK -#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB08_ST -#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL -#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK +#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL +#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL +#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL +#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL +#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK +#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST +#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK +#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST +#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST #define NOR_SPI_BSPIM_RxStsReg__4__MASK 0x10u #define NOR_SPI_BSPIM_RxStsReg__4__POS 4 #define NOR_SPI_BSPIM_RxStsReg__5__MASK 0x20u @@ -628,32 +602,34 @@ #define NOR_SPI_BSPIM_RxStsReg__6__MASK 0x40u #define NOR_SPI_BSPIM_RxStsReg__6__POS 6 #define NOR_SPI_BSPIM_RxStsReg__MASK 0x70u -#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK -#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL -#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0 -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0 -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0 -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0 -#define NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0 -#define NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0 -#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1 +#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK +#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL #define NOR_SPI_BSPIM_TxStsReg__0__MASK 0x01u #define NOR_SPI_BSPIM_TxStsReg__0__POS 0 #define NOR_SPI_BSPIM_TxStsReg__1__MASK 0x02u #define NOR_SPI_BSPIM_TxStsReg__1__POS 1 -#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST +#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST #define NOR_SPI_BSPIM_TxStsReg__2__MASK 0x04u #define NOR_SPI_BSPIM_TxStsReg__2__POS 2 #define NOR_SPI_BSPIM_TxStsReg__3__MASK 0x08u @@ -661,9 +637,9 @@ #define NOR_SPI_BSPIM_TxStsReg__4__MASK 0x10u #define NOR_SPI_BSPIM_TxStsReg__4__POS 4 #define NOR_SPI_BSPIM_TxStsReg__MASK 0x1Fu -#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK -#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST +#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK +#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST /* SCSI_In */ #define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1 @@ -1784,15 +1760,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u @@ -1805,35 +1781,35 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB09_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB09_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB09_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG #define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX #define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE @@ -2843,58 +2819,58 @@ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK /* SCSI_Glitch_Ctl */ #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL #define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB08_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB08_ST /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index b9cd1c4..da9035b 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -369,7 +369,7 @@ void cyfitter_cfg(void) /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */ static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { - 0x08u, 0x00u, 0x01u, 0xFEu, 0xFEu, 0x02u, 0xF6u, 0x00u, 0x00u, 0x01u}; + 0x08u, 0x00u, 0x01u, 0xFEu, 0xFEu, 0x02u, 0xC6u, 0x00u, 0x00u, 0x01u}; /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { @@ -410,44 +410,44 @@ void cyfitter_cfg(void) static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004501u, /* Base address: 0x40004500 Count: 1 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x4000520Eu, /* Base address: 0x40005200 Count: 14 */ + 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */ 0x40006402u, /* Base address: 0x40006400 Count: 2 */ - 0x40006502u, /* Base address: 0x40006500 Count: 2 */ - 0x40010045u, /* Base address: 0x40010000 Count: 69 */ - 0x4001013Au, /* Base address: 0x40010100 Count: 58 */ - 0x4001024Eu, /* Base address: 0x40010200 Count: 78 */ - 0x4001035Bu, /* Base address: 0x40010300 Count: 91 */ - 0x4001041Bu, /* Base address: 0x40010400 Count: 27 */ - 0x40010545u, /* Base address: 0x40010500 Count: 69 */ - 0x40010651u, /* Base address: 0x40010600 Count: 81 */ - 0x40010751u, /* Base address: 0x40010700 Count: 81 */ - 0x4001084Eu, /* Base address: 0x40010800 Count: 78 */ - 0x4001095Fu, /* Base address: 0x40010900 Count: 95 */ - 0x40010A5Cu, /* Base address: 0x40010A00 Count: 92 */ - 0x40010B60u, /* Base address: 0x40010B00 Count: 96 */ - 0x40010C49u, /* Base address: 0x40010C00 Count: 73 */ - 0x40010D54u, /* Base address: 0x40010D00 Count: 84 */ - 0x40010E51u, /* Base address: 0x40010E00 Count: 81 */ - 0x40010F43u, /* Base address: 0x40010F00 Count: 67 */ - 0x40011462u, /* Base address: 0x40011400 Count: 98 */ - 0x40011540u, /* Base address: 0x40011500 Count: 64 */ - 0x40011651u, /* Base address: 0x40011600 Count: 81 */ - 0x4001174Cu, /* Base address: 0x40011700 Count: 76 */ - 0x40011855u, /* Base address: 0x40011800 Count: 85 */ - 0x40011948u, /* Base address: 0x40011900 Count: 72 */ - 0x40011B06u, /* Base address: 0x40011B00 Count: 6 */ + 0x40006501u, /* Base address: 0x40006500 Count: 1 */ + 0x4001003Eu, /* Base address: 0x40010000 Count: 62 */ + 0x40010147u, /* Base address: 0x40010100 Count: 71 */ + 0x40010245u, /* Base address: 0x40010200 Count: 69 */ + 0x40010350u, /* Base address: 0x40010300 Count: 80 */ + 0x40010455u, /* Base address: 0x40010400 Count: 85 */ + 0x4001054Eu, /* Base address: 0x40010500 Count: 78 */ + 0x4001066Bu, /* Base address: 0x40010600 Count: 107 */ + 0x40010757u, /* Base address: 0x40010700 Count: 87 */ + 0x4001084Au, /* Base address: 0x40010800 Count: 74 */ + 0x40010952u, /* Base address: 0x40010900 Count: 82 */ + 0x40010A52u, /* Base address: 0x40010A00 Count: 82 */ + 0x40010B56u, /* Base address: 0x40010B00 Count: 86 */ + 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */ + 0x40010D57u, /* Base address: 0x40010D00 Count: 87 */ + 0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */ + 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */ + 0x4001141Cu, /* Base address: 0x40011400 Count: 28 */ + 0x4001155Cu, /* Base address: 0x40011500 Count: 92 */ + 0x40011653u, /* Base address: 0x40011600 Count: 83 */ + 0x40011755u, /* Base address: 0x40011700 Count: 85 */ + 0x40011857u, /* Base address: 0x40011800 Count: 87 */ + 0x4001194Cu, /* Base address: 0x40011900 Count: 76 */ + 0x40011B09u, /* Base address: 0x40011B00 Count: 9 */ 0x4001401Du, /* Base address: 0x40014000 Count: 29 */ - 0x40014120u, /* Base address: 0x40014100 Count: 32 */ - 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */ - 0x4001430Au, /* Base address: 0x40014300 Count: 10 */ - 0x40014411u, /* Base address: 0x40014400 Count: 17 */ - 0x40014517u, /* Base address: 0x40014500 Count: 23 */ - 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */ - 0x4001470Cu, /* Base address: 0x40014700 Count: 12 */ + 0x40014121u, /* Base address: 0x40014100 Count: 33 */ + 0x40014215u, /* Base address: 0x40014200 Count: 21 */ + 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */ + 0x40014410u, /* Base address: 0x40014400 Count: 16 */ + 0x40014519u, /* Base address: 0x40014500 Count: 25 */ + 0x40014614u, /* Base address: 0x40014600 Count: 20 */ + 0x40014715u, /* Base address: 0x40014700 Count: 21 */ 0x4001480Du, /* Base address: 0x40014800 Count: 13 */ - 0x4001491Au, /* Base address: 0x40014900 Count: 26 */ - 0x40014C0Cu, /* Base address: 0x40014C00 Count: 12 */ - 0x40014D07u, /* Base address: 0x40014D00 Count: 7 */ + 0x40014913u, /* Base address: 0x40014900 Count: 19 */ + 0x40014C08u, /* Base address: 0x40014C00 Count: 8 */ + 0x40014D03u, /* Base address: 0x40014D00 Count: 3 */ 0x40015005u, /* Base address: 0x40015000 Count: 5 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; @@ -455,44 +455,51 @@ void cyfitter_cfg(void) static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x7Eu, 0x02u}, {0x01u, 0x30u}, - {0x0Au, 0x4Bu}, - {0x00u, 0x02u}, - {0x01u, 0x20u}, - {0x10u, 0xA8u}, - {0x11u, 0x2Au}, - {0x18u, 0x62u}, - {0x19u, 0x38u}, + {0x0Au, 0x27u}, + {0x01u, 0x22u}, + {0x10u, 0x0Au}, + {0x11u, 0x88u}, + {0x18u, 0x8Au}, + {0x19u, 0x82u}, {0x1Cu, 0x08u}, {0x20u, 0x01u}, - {0x30u, 0x84u}, - {0x31u, 0x20u}, - {0x61u, 0x20u}, + {0x21u, 0x03u}, + {0x31u, 0x80u}, {0x78u, 0x20u}, - {0x79u, 0x20u}, {0x7Cu, 0x40u}, {0x20u, 0x01u}, - {0x88u, 0x0Fu}, - {0x76u, 0x01u}, - {0x85u, 0x0Fu}, - {0x00u, 0x0Au}, - {0x02u, 0x55u}, - {0x06u, 0x7Fu}, - {0x0Cu, 0x8Bu}, - {0x0Eu, 0x74u}, - {0x14u, 0x91u}, - {0x16u, 0x6Cu}, - {0x18u, 0x01u}, - {0x1Cu, 0x40u}, - {0x1Eu, 0x80u}, - {0x22u, 0x10u}, - {0x24u, 0x06u}, - {0x28u, 0x20u}, - {0x2Au, 0x40u}, - {0x30u, 0x3Fu}, - {0x36u, 0xC0u}, - {0x3Au, 0x80u}, - {0x40u, 0x62u}, - {0x41u, 0x04u}, + {0x86u, 0x0Fu}, + {0x84u, 0x0Fu}, + {0x01u, 0x08u}, + {0x03u, 0x10u}, + {0x06u, 0x24u}, + {0x07u, 0x03u}, + {0x0Bu, 0x84u}, + {0x0Cu, 0x24u}, + {0x0Eu, 0x12u}, + {0x0Fu, 0x80u}, + {0x12u, 0x18u}, + {0x14u, 0x24u}, + {0x16u, 0x09u}, + {0x19u, 0x08u}, + {0x1Au, 0x03u}, + {0x1Bu, 0x60u}, + {0x1Fu, 0x04u}, + {0x21u, 0x10u}, + {0x22u, 0x20u}, + {0x29u, 0x84u}, + {0x2Au, 0x04u}, + {0x2Bu, 0x21u}, + {0x2Du, 0x84u}, + {0x2Fu, 0x42u}, + {0x30u, 0x38u}, + {0x33u, 0x07u}, + {0x34u, 0x07u}, + {0x35u, 0xE0u}, + {0x37u, 0x18u}, + {0x3Fu, 0x40u}, + {0x40u, 0x63u}, + {0x41u, 0x02u}, {0x42u, 0x10u}, {0x45u, 0xECu}, {0x46u, 0x2Du}, @@ -504,9 +511,10 @@ void cyfitter_cfg(void) {0x4Fu, 0x2Cu}, {0x56u, 0x01u}, {0x58u, 0x04u}, + {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x02u}, + {0x5Cu, 0x22u}, {0x5Du, 0x02u}, {0x5Fu, 0x01u}, {0x60u, 0x08u}, @@ -515,1206 +523,429 @@ void cyfitter_cfg(void) {0x68u, 0x40u}, {0x69u, 0x40u}, {0x6Eu, 0x08u}, - {0x81u, 0x04u}, - {0x84u, 0x02u}, - {0x86u, 0x01u}, - {0x89u, 0x02u}, - {0x8Du, 0x01u}, - {0x94u, 0x02u}, - {0x96u, 0x01u}, - {0x98u, 0x02u}, - {0x9Au, 0x05u}, - {0x9Cu, 0x01u}, - {0x9Eu, 0x02u}, - {0xA0u, 0x02u}, - {0xA2u, 0x09u}, - {0xB1u, 0x04u}, - {0xB2u, 0x08u}, - {0xB4u, 0x04u}, - {0xB5u, 0x02u}, - {0xB6u, 0x03u}, - {0xB7u, 0x01u}, - {0xBAu, 0x80u}, - {0xBFu, 0x50u}, - {0xD6u, 0x08u}, + {0x88u, 0x02u}, + {0xA4u, 0x01u}, + {0xB0u, 0x01u}, + {0xB4u, 0x02u}, + {0xBEu, 0x01u}, {0xD8u, 0x04u}, - {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x92u}, - {0xDDu, 0x90u}, + {0xDCu, 0x09u}, {0xDFu, 0x01u}, - {0x01u, 0x02u}, - {0x03u, 0x12u}, - {0x04u, 0x04u}, - {0x0Au, 0x01u}, - {0x0Bu, 0x28u}, - {0x0Eu, 0x2Au}, - {0x10u, 0xA4u}, - {0x16u, 0x80u}, - {0x19u, 0x02u}, - {0x1Au, 0x01u}, + {0x00u, 0x08u}, + {0x01u, 0x80u}, + {0x05u, 0x10u}, + {0x07u, 0x04u}, + {0x08u, 0x08u}, + {0x0Au, 0x44u}, + {0x10u, 0x80u}, + {0x11u, 0x10u}, + {0x16u, 0x10u}, + {0x1Au, 0xC4u}, {0x1Cu, 0x04u}, - {0x1Eu, 0x22u}, - {0x1Fu, 0x80u}, - {0x24u, 0x02u}, - {0x25u, 0x02u}, - {0x27u, 0x04u}, - {0x3Du, 0xA2u}, - {0x3Fu, 0x02u}, + {0x1Fu, 0x01u}, + {0x21u, 0x44u}, + {0x22u, 0x10u}, + {0x28u, 0x08u}, + {0x29u, 0x80u}, + {0x2Au, 0x01u}, + {0x32u, 0x10u}, + {0x33u, 0x40u}, + {0x35u, 0x40u}, + {0x36u, 0x40u}, + {0x38u, 0x02u}, + {0x39u, 0x48u}, + {0x3Bu, 0x10u}, {0x40u, 0x08u}, - {0x42u, 0x01u}, - {0x43u, 0x02u}, - {0x48u, 0x20u}, - {0x49u, 0x14u}, - {0x4Bu, 0x22u}, - {0x50u, 0x80u}, - {0x51u, 0x60u}, - {0x52u, 0x10u}, - {0x53u, 0x08u}, - {0x59u, 0xA0u}, - {0x5Bu, 0x0Au}, - {0x5Cu, 0x80u}, - {0x60u, 0x60u}, - {0x62u, 0xA0u}, - {0x66u, 0x80u}, - {0x68u, 0x04u}, - {0x69u, 0x44u}, + {0x41u, 0x10u}, + {0x42u, 0x21u}, + {0x48u, 0x14u}, + {0x49u, 0x04u}, + {0x4Au, 0x40u}, + {0x4Bu, 0x10u}, + {0x50u, 0x20u}, + {0x51u, 0xA0u}, + {0x52u, 0x80u}, + {0x53u, 0x04u}, + {0x58u, 0x42u}, + {0x5Bu, 0x28u}, + {0x60u, 0x20u}, + {0x62u, 0x20u}, + {0x63u, 0x81u}, + {0x65u, 0x20u}, + {0x67u, 0x08u}, + {0x69u, 0x50u}, + {0x6Au, 0x08u}, {0x6Bu, 0x40u}, - {0x70u, 0x50u}, - {0x72u, 0x40u}, - {0x73u, 0x10u}, - {0x81u, 0x60u}, - {0x83u, 0x01u}, - {0x84u, 0x08u}, - {0x85u, 0x46u}, - {0x87u, 0x10u}, - {0x88u, 0xA0u}, - {0x8Cu, 0x41u}, - {0xC0u, 0x2Du}, - {0xC2u, 0xE7u}, - {0xC4u, 0x1Eu}, - {0xCEu, 0xB0u}, - {0xD0u, 0x0Du}, + {0x6Cu, 0x01u}, + {0x6Fu, 0x02u}, + {0x70u, 0x80u}, + {0x71u, 0x08u}, + {0x72u, 0x08u}, + {0x73u, 0x40u}, + {0x80u, 0x04u}, + {0x81u, 0x18u}, + {0x84u, 0x60u}, + {0x87u, 0x40u}, + {0x88u, 0x20u}, + {0x8Au, 0x08u}, + {0x8Bu, 0x20u}, + {0xC0u, 0x45u}, + {0xC2u, 0x0Eu}, + {0xC4u, 0x2Au}, + {0xCAu, 0x0Du}, + {0xCCu, 0x0Cu}, + {0xCEu, 0x0Fu}, + {0xD0u, 0x0Eu}, {0xD2u, 0x04u}, - {0xD6u, 0x1Fu}, - {0xD8u, 0x1Fu}, - {0xE0u, 0x2Du}, - {0xE2u, 0x42u}, - {0xE4u, 0x0Au}, - {0x01u, 0x02u}, - {0x03u, 0x11u}, - {0x05u, 0x02u}, - {0x07u, 0x05u}, - {0x0Cu, 0x02u}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, + {0xE0u, 0x03u}, + {0xE4u, 0x06u}, + {0xE6u, 0x08u}, + {0x08u, 0x02u}, {0x0Du, 0x02u}, - {0x0Eu, 0x01u}, {0x0Fu, 0x01u}, - {0x11u, 0x01u}, - {0x13u, 0x02u}, - {0x14u, 0x02u}, - {0x15u, 0x02u}, - {0x16u, 0x11u}, - {0x17u, 0x09u}, - {0x18u, 0x02u}, - {0x1Au, 0x05u}, - {0x1Cu, 0x01u}, - {0x1Eu, 0x02u}, - {0x24u, 0x02u}, - {0x26u, 0x09u}, - {0x30u, 0x04u}, - {0x31u, 0x03u}, - {0x32u, 0x08u}, + {0x10u, 0x01u}, + {0x11u, 0x02u}, + {0x13u, 0x11u}, + {0x15u, 0x01u}, + {0x17u, 0x02u}, + {0x19u, 0x02u}, + {0x1Bu, 0x05u}, + {0x20u, 0x02u}, + {0x2Du, 0x02u}, + {0x2Fu, 0x09u}, + {0x31u, 0x10u}, {0x33u, 0x08u}, - {0x34u, 0x10u}, - {0x35u, 0x10u}, - {0x36u, 0x03u}, + {0x34u, 0x01u}, + {0x35u, 0x03u}, + {0x36u, 0x02u}, {0x37u, 0x04u}, - {0x3Au, 0x80u}, - {0x3Bu, 0x02u}, + {0x38u, 0x80u}, + {0x3Bu, 0x20u}, + {0x3Eu, 0x10u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x22u}, + {0x5Cu, 0x20u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x78u}, - {0x82u, 0x03u}, - {0x86u, 0x7Fu}, - {0x87u, 0x06u}, - {0x8Cu, 0x20u}, - {0x8Eu, 0x40u}, + {0x80u, 0x04u}, + {0x81u, 0x28u}, + {0x82u, 0x10u}, + {0x83u, 0x04u}, + {0x84u, 0x2Bu}, + {0x85u, 0x12u}, + {0x86u, 0x14u}, + {0x87u, 0x01u}, + {0x88u, 0x43u}, + {0x8Au, 0x0Cu}, + {0x8Cu, 0x28u}, + {0x8Du, 0x04u}, + {0x8Eu, 0x17u}, {0x8Fu, 0x08u}, - {0x90u, 0x01u}, - {0x92u, 0x6Eu}, - {0x94u, 0x20u}, - {0x96u, 0x40u}, - {0x97u, 0x30u}, - {0x98u, 0x80u}, + {0x91u, 0x13u}, + {0x93u, 0x2Cu}, + {0x94u, 0x0Du}, + {0x96u, 0x12u}, {0x9Au, 0x01u}, - {0x9Bu, 0x01u}, - {0x9Cu, 0x03u}, - {0x9Eu, 0x74u}, - {0x9Fu, 0x40u}, + {0x9Bu, 0x40u}, + {0x9Cu, 0x10u}, + {0x9Du, 0x01u}, + {0x9Eu, 0x20u}, + {0x9Fu, 0x02u}, {0xA0u, 0x02u}, - {0xA1u, 0x49u}, - {0xA3u, 0x24u}, - {0xA6u, 0x08u}, - {0xA8u, 0x64u}, - {0xA9u, 0x01u}, - {0xABu, 0x48u}, - {0xADu, 0x49u}, - {0xAFu, 0x12u}, - {0xB2u, 0x80u}, - {0xB3u, 0x70u}, - {0xB4u, 0x1Fu}, - {0xB5u, 0x0Eu}, - {0xB6u, 0x60u}, - {0xB7u, 0x01u}, - {0xBAu, 0x80u}, - {0xBEu, 0x04u}, - {0xBFu, 0x40u}, + {0xAAu, 0x17u}, + {0xB0u, 0x40u}, + {0xB1u, 0x0Fu}, + {0xB2u, 0x0Fu}, + {0xB3u, 0x30u}, + {0xB5u, 0x40u}, + {0xB6u, 0x30u}, + {0xBAu, 0x88u}, + {0xBEu, 0x01u}, + {0xBFu, 0x05u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDCu, 0x22u}, {0xDFu, 0x01u}, - {0x01u, 0x82u}, - {0x03u, 0x10u}, - {0x04u, 0x40u}, - {0x08u, 0x89u}, - {0x0Bu, 0x08u}, - {0x0Du, 0x20u}, - {0x0Eu, 0x12u}, - {0x10u, 0x84u}, - {0x12u, 0x10u}, - {0x13u, 0x02u}, - {0x16u, 0x20u}, - {0x18u, 0x28u}, - {0x19u, 0x90u}, - {0x1Cu, 0x42u}, - {0x1Du, 0x20u}, - {0x1Eu, 0x12u}, - {0x20u, 0x24u}, - {0x21u, 0x88u}, - {0x25u, 0x45u}, - {0x26u, 0x02u}, - {0x27u, 0x04u}, - {0x28u, 0x01u}, - {0x29u, 0x12u}, - {0x2Bu, 0x02u}, - {0x2Eu, 0x40u}, + {0x00u, 0x89u}, + {0x03u, 0x08u}, + {0x04u, 0x20u}, + {0x09u, 0x24u}, + {0x0Au, 0x01u}, + {0x0Fu, 0x40u}, + {0x12u, 0x88u}, + {0x15u, 0x40u}, + {0x16u, 0x01u}, + {0x17u, 0x02u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x09u}, + {0x1Cu, 0x02u}, + {0x1Fu, 0x20u}, + {0x20u, 0x14u}, + {0x21u, 0x01u}, + {0x24u, 0x40u}, + {0x27u, 0x15u}, {0x2Fu, 0x01u}, - {0x30u, 0x20u}, - {0x31u, 0x08u}, - {0x33u, 0x40u}, - {0x36u, 0x02u}, - {0x37u, 0x04u}, - {0x38u, 0x04u}, - {0x39u, 0x40u}, - {0x3Du, 0x88u}, - {0x3Fu, 0x01u}, - {0x40u, 0x20u}, - {0x43u, 0x08u}, - {0x58u, 0x20u}, - {0x59u, 0x04u}, - {0x5Au, 0x40u}, - {0x5Bu, 0x02u}, - {0x5Fu, 0x50u}, - {0x61u, 0x80u}, - {0x66u, 0x20u}, - {0x67u, 0x01u}, - {0x6Bu, 0x01u}, - {0x80u, 0x10u}, - {0x81u, 0x10u}, - {0x84u, 0x54u}, - {0x87u, 0x04u}, - {0x8Bu, 0x50u}, - {0x91u, 0x40u}, - {0x93u, 0x02u}, - {0x97u, 0x08u}, - {0x99u, 0x06u}, - {0x9Au, 0x10u}, - {0x9Bu, 0x40u}, - {0x9Cu, 0x04u}, - {0x9Du, 0x90u}, - {0x9Fu, 0x18u}, - {0xA0u, 0xA4u}, - {0xA2u, 0x10u}, - {0xA3u, 0x08u}, - {0xA4u, 0x01u}, - {0xA5u, 0x11u}, - {0xA6u, 0xA4u}, - {0xA7u, 0x02u}, - {0xA8u, 0x10u}, - {0xABu, 0x82u}, - {0xACu, 0x01u}, - {0xADu, 0x22u}, - {0xB3u, 0x01u}, - {0xB4u, 0x40u}, - {0xB6u, 0x40u}, - {0xB7u, 0x0Cu}, - {0xC0u, 0x8Du}, - {0xC2u, 0xEFu}, - {0xC4u, 0x2Eu}, - {0xCAu, 0x0Du}, - {0xCCu, 0xCEu}, - {0xCEu, 0xDAu}, + {0x30u, 0x80u}, + {0x32u, 0x50u}, + {0x33u, 0x02u}, + {0x37u, 0x15u}, + {0x38u, 0x80u}, + {0x39u, 0x09u}, + {0x3Cu, 0x40u}, + {0x59u, 0x64u}, + {0x5Au, 0x02u}, + {0x5Du, 0x80u}, + {0x5Fu, 0x10u}, + {0x62u, 0x40u}, + {0x64u, 0x04u}, + {0x67u, 0x02u}, + {0x68u, 0x10u}, + {0x69u, 0x51u}, + {0x70u, 0x40u}, + {0x71u, 0x10u}, + {0x72u, 0x62u}, + {0x82u, 0x20u}, + {0x84u, 0x10u}, + {0x86u, 0x04u}, + {0x8Au, 0x40u}, + {0x8Du, 0x10u}, + {0x8Eu, 0x40u}, + {0x90u, 0x02u}, + {0x91u, 0x88u}, + {0x92u, 0x86u}, + {0x95u, 0x20u}, + {0x96u, 0x01u}, + {0x97u, 0x01u}, + {0x99u, 0x64u}, + {0x9Cu, 0x02u}, + {0x9Eu, 0x01u}, + {0x9Fu, 0x0Cu}, + {0xA1u, 0x24u}, + {0xA2u, 0x80u}, + {0xA3u, 0x02u}, + {0xA4u, 0x04u}, + {0xA6u, 0x20u}, + {0xA7u, 0x40u}, + {0xA9u, 0xA4u}, + {0xAAu, 0x20u}, + {0xACu, 0x10u}, + {0xAEu, 0x40u}, + {0xB1u, 0x80u}, + {0xB2u, 0x15u}, + {0xB5u, 0x40u}, + {0xB7u, 0x01u}, + {0xC0u, 0x4Fu}, + {0xC2u, 0x17u}, + {0xC4u, 0x1Au}, + {0xCAu, 0x10u}, + {0xCCu, 0xEDu}, + {0xCEu, 0x1Bu}, {0xD6u, 0x3Fu}, {0xD8u, 0x38u}, - {0xE0u, 0x28u}, - {0xE2u, 0x01u}, - {0xE4u, 0x82u}, - {0xE6u, 0x08u}, - {0xE8u, 0x04u}, - {0xEAu, 0x10u}, - {0xECu, 0x0Cu}, - {0xEEu, 0x13u}, - {0x88u, 0x02u}, - {0x8Du, 0x02u}, - {0x8Fu, 0x01u}, - {0x91u, 0x02u}, - {0x93u, 0x05u}, - {0x95u, 0x02u}, - {0x96u, 0x01u}, - {0x97u, 0x09u}, - {0x99u, 0x01u}, - {0x9Bu, 0x02u}, - {0xADu, 0x02u}, - {0xAFu, 0x11u}, - {0xB0u, 0x02u}, - {0xB1u, 0x04u}, - {0xB3u, 0x03u}, - {0xB4u, 0x01u}, - {0xB5u, 0x10u}, - {0xB7u, 0x08u}, - {0xBBu, 0x08u}, - {0xBEu, 0x01u}, - {0xD6u, 0x08u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x22u}, - {0xDDu, 0x90u}, - {0xDFu, 0x01u}, - {0x00u, 0x18u}, - {0x01u, 0x80u}, - {0x05u, 0x10u}, - {0x08u, 0xA0u}, - {0x09u, 0x88u}, - {0x0Bu, 0x80u}, - {0x0Eu, 0x20u}, - {0x11u, 0xAAu}, - {0x19u, 0x01u}, - {0x1Au, 0x02u}, - {0x1Cu, 0x80u}, - {0x1Eu, 0x08u}, - {0x20u, 0x08u}, - {0x21u, 0x24u}, - {0x23u, 0x01u}, - {0x24u, 0x40u}, - {0x27u, 0x36u}, - {0x28u, 0x20u}, - {0x29u, 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0x40u}, - {0xB4u, 0x80u}, - {0xB5u, 0x44u}, - {0xB7u, 0x40u}, - {0xC0u, 0xFCu}, - {0xC2u, 0xFFu}, - {0xC4u, 0x2Du}, - {0xCAu, 0x6Fu}, - {0xCCu, 0xE5u}, - {0xCEu, 0xFEu}, - {0xD8u, 0x80u}, - {0xE0u, 0x10u}, - {0xE2u, 0x80u}, - {0xE4u, 0x40u}, - {0xE8u, 0x10u}, - {0xEAu, 0x41u}, - {0xEEu, 0x43u}, - {0x05u, 0x50u}, - {0x06u, 0x04u}, - {0x07u, 0xA0u}, - {0x09u, 0x05u}, - {0x0Au, 0x03u}, - {0x0Bu, 0x0Au}, - {0x0Cu, 0x40u}, - {0x0Du, 0x30u}, - {0x0Fu, 0xC0u}, - {0x11u, 0x06u}, - {0x12u, 0x24u}, - {0x13u, 0x09u}, - {0x14u, 0x24u}, - {0x15u, 0x03u}, - {0x16u, 0x09u}, - {0x17u, 0x0Cu}, - {0x18u, 0x24u}, - {0x19u, 0x60u}, - {0x1Au, 0x12u}, - {0x1Bu, 0x90u}, - {0x1Cu, 0x40u}, - {0x22u, 0x18u}, - {0x24u, 0x40u}, - {0x28u, 0x40u}, - {0x2Du, 0x0Fu}, - {0x2Eu, 0x20u}, - {0x2Fu, 0xF0u}, - {0x30u, 0x40u}, - {0x32u, 0x07u}, - {0x34u, 0x38u}, - {0x37u, 0xFFu}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x40u}, - {0x56u, 0x08u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x02u}, - {0x5Du, 0x90u}, - {0x5Fu, 0x01u}, - {0x81u, 0x01u}, - {0x83u, 0x02u}, - {0x84u, 0x04u}, - {0x85u, 0x04u}, - {0x86u, 0x08u}, - {0x87u, 0x08u}, - {0x89u, 0x01u}, - {0x8Au, 0x3Fu}, - {0x8Bu, 0x02u}, - {0x8Cu, 0x3Fu}, - {0x8Du, 0x50u}, - {0x8Fu, 0x8Fu}, - {0x91u, 0x10u}, - {0x92u, 0x3Fu}, - {0x93u, 0x8Fu}, - {0x94u, 0x3Fu}, - {0x95u, 0x20u}, - {0x97u, 0x0Fu}, - {0x98u, 0x01u}, - {0x99u, 0x0Fu}, - {0x9Au, 0x02u}, - {0x9Bu, 0x80u}, - {0x9Cu, 0x10u}, - {0x9Du, 0x04u}, - {0x9Eu, 0x20u}, - {0x9Fu, 0x08u}, - {0xA0u, 0x10u}, - {0xA1u, 0x4Fu}, - {0xA2u, 0x20u}, - {0xA3u, 0x80u}, - {0xA4u, 0x04u}, - {0xA6u, 0x08u}, - {0xA7u, 0x10u}, - {0xA8u, 0x01u}, - {0xAAu, 0x02u}, - {0xAEu, 0x3Fu}, - {0xB1u, 0x03u}, - {0xB2u, 0x0Cu}, - {0xB3u, 0xF0u}, - {0xB4u, 0x03u}, - {0xB6u, 0x30u}, - {0xB7u, 0x0Cu}, - {0xB9u, 0x08u}, - {0xBAu, 0xA8u}, - {0xBBu, 0x82u}, - {0xD4u, 0x01u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x22u}, - {0xDDu, 0x20u}, - {0xDFu, 0x01u}, - {0x00u, 0x40u}, - {0x01u, 0x04u}, - {0x03u, 0x08u}, - {0x05u, 0x04u}, - {0x06u, 0x02u}, - {0x07u, 0x04u}, - {0x08u, 0x02u}, - {0x09u, 0x04u}, - {0x0Bu, 0x0Au}, - {0x0Eu, 0x28u}, - {0x0Fu, 0x82u}, - {0x10u, 0x42u}, - {0x12u, 0x08u}, - {0x13u, 0x08u}, - {0x14u, 0x02u}, - {0x15u, 0x02u}, - {0x16u, 0x20u}, - {0x17u, 0x10u}, - {0x1Au, 0x48u}, - {0x1Bu, 0x08u}, - {0x1Cu, 0x04u}, - {0x1Du, 0x04u}, - {0x1Eu, 0x08u}, - {0x1Fu, 0x80u}, - {0x23u, 0x02u}, - {0x25u, 0x05u}, - {0x26u, 0x80u}, - {0x28u, 0x01u}, - {0x29u, 0x40u}, - {0x2Du, 0x08u}, - {0x2Eu, 0x02u}, - {0x2Fu, 0x20u}, - {0x31u, 0x20u}, - {0x32u, 0x05u}, - {0x34u, 0x02u}, - {0x36u, 0xA0u}, - {0x37u, 0x04u}, - {0x38u, 0x28u}, - {0x3Bu, 0x40u}, - {0x3Du, 0x02u}, - {0x3Fu, 0xA8u}, - {0x58u, 0x10u}, - {0x5Bu, 0x40u}, - {0x5Du, 0x80u}, - {0x60u, 0x08u}, - {0x62u, 0x40u}, - {0x63u, 0x08u}, - {0x79u, 0x02u}, - {0x7Bu, 0x80u}, - {0x81u, 0x01u}, - {0x85u, 0x30u}, - {0x87u, 0x80u}, - {0x88u, 0x40u}, - {0x8Au, 0x04u}, - {0x8Cu, 0x20u}, - {0x8Du, 0x08u}, - {0x8Eu, 0x42u}, - {0x8Fu, 0x04u}, - {0x91u, 0x44u}, - {0x92u, 0x22u}, - {0x93u, 0xA8u}, - {0x95u, 0x01u}, - {0x96u, 0x01u}, - {0x98u, 0x06u}, - {0x99u, 0x80u}, - {0x9Au, 0x22u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x80u}, - {0x9Du, 0x46u}, - {0x9Eu, 0x4Cu}, - {0xA0u, 0x12u}, - {0xA2u, 0x30u}, - {0xA3u, 0x31u}, - {0xA4u, 0x24u}, - {0xA5u, 0x2Cu}, - {0xA6u, 0x80u}, - {0xA7u, 0x48u}, - {0xA8u, 0x40u}, - {0xABu, 0x04u}, - {0xADu, 0x20u}, - {0xAFu, 0x88u}, - {0xB2u, 0x04u}, - {0xB4u, 0x42u}, - {0xC0u, 0xE7u}, - {0xC2u, 0xFFu}, - {0xC4u, 0xFFu}, - {0xCAu, 0xC8u}, - {0xCCu, 0xF7u}, - {0xCEu, 0xFEu}, - {0xD6u, 0x1Cu}, - {0xD8u, 0x0Cu}, - {0xE4u, 0x10u}, - {0xE6u, 0x80u}, - {0xE8u, 0x51u}, - {0xECu, 0x08u}, - {0xEEu, 0x02u}, - {0x01u, 0x02u}, - {0x03u, 0x01u}, - {0x08u, 0x01u}, - {0x0Au, 0x06u}, - {0x0Du, 0x02u}, - {0x0Fu, 0x01u}, - {0x11u, 0x10u}, - {0x13u, 0x20u}, - {0x15u, 0x01u}, - {0x17u, 0x12u}, - {0x1Cu, 0x04u}, - {0x1Eu, 0x03u}, - {0x20u, 0x03u}, - {0x22u, 0x04u}, - {0x25u, 0x02u}, - {0x27u, 0x09u}, - {0x28u, 0x05u}, - {0x2Au, 0x02u}, - {0x2Du, 0x02u}, - {0x2Fu, 0x25u}, - {0x31u, 0x08u}, - {0x33u, 0x03u}, - {0x35u, 0x30u}, - {0x36u, 0x07u}, - {0x37u, 0x04u}, - {0x3Au, 0x80u}, - {0x3Bu, 0x08u}, - {0x3Fu, 0x10u}, - {0x56u, 0x08u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x20u}, - {0x5Du, 0x90u}, - {0x5Fu, 0x01u}, - {0x81u, 0x24u}, - {0x83u, 0x12u}, - {0x84u, 0x40u}, - {0x88u, 0x20u}, - {0x8Bu, 0x18u}, - {0x8Fu, 0x20u}, - {0x90u, 0x29u}, - {0x91u, 0x40u}, - {0x92u, 0x52u}, - {0x93u, 0x03u}, - {0x94u, 0x08u}, - {0x97u, 0x04u}, - {0x99u, 0x80u}, - {0x9Cu, 0x10u}, - {0x9Du, 0x40u}, - {0x9Fu, 0x80u}, - {0xA0u, 0x02u}, - {0xA1u, 0x24u}, - {0xA3u, 0x09u}, - {0xA8u, 0x01u}, - {0xAEu, 0x04u}, - {0xAFu, 0x24u}, - {0xB0u, 0x03u}, - {0xB1u, 0x07u}, - {0xB2u, 0x04u}, - {0xB3u, 0xC0u}, - {0xB4u, 0x60u}, - {0xB5u, 0x38u}, - {0xB6u, 0x18u}, - {0xBEu, 0x51u}, - {0xBFu, 0x04u}, - {0xD6u, 0x08u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x22u}, - {0xDDu, 0x90u}, - {0xDFu, 0x01u}, - {0x00u, 0x08u}, - {0x03u, 0x08u}, - {0x06u, 0x08u}, - {0x0Au, 0xA1u}, - {0x0Eu, 0x02u}, - {0x10u, 0x04u}, - {0x11u, 0x81u}, - {0x14u, 0x80u}, - {0x16u, 0x04u}, - {0x18u, 0x80u}, - {0x19u, 0x18u}, - {0x1Bu, 0x80u}, - {0x1Eu, 0x02u}, - {0x1Fu, 0x40u}, - {0x21u, 0x10u}, - {0x22u, 0x15u}, - {0x25u, 0x41u}, - {0x26u, 0x34u}, - {0x27u, 0x0Cu}, - {0x28u, 0x02u}, - {0x2Bu, 0x40u}, - {0x2Du, 0x08u}, - {0x2Fu, 0x01u}, - {0x31u, 0x60u}, - {0x32u, 0x49u}, - {0x36u, 0x04u}, - {0x37u, 0x01u}, - {0x39u, 0xA0u}, - {0x3Au, 0x02u}, - {0x3Du, 0x82u}, - {0x59u, 0x20u}, - {0x5Au, 0x44u}, - {0x5Cu, 0x50u}, - {0x63u, 0x2Au}, - {0x66u, 0x20u}, - {0x67u, 0x02u}, - {0x6Bu, 0x01u}, - {0x6Du, 0x40u}, - {0x6Eu, 0x10u}, - {0x6Fu, 0x20u}, - {0x80u, 0x10u}, - {0x81u, 0x10u}, - {0x82u, 0x50u}, - {0x84u, 0x04u}, - {0x85u, 0x04u}, - {0x87u, 0x20u}, - {0x8Au, 0x04u}, - {0x91u, 0x80u}, - {0x93u, 0x28u}, - {0x99u, 0x80u}, - {0x9Au, 0x02u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x06u}, - {0x9Eu, 0x60u}, - {0x9Fu, 0x04u}, - {0xA0u, 0x12u}, - {0xA2u, 0x08u}, - {0xA4u, 0x20u}, - {0xA5u, 0x0Cu}, - {0xA6u, 0xA4u}, - {0xA7u, 0x75u}, - {0xA8u, 0x61u}, - {0xA9u, 0x04u}, - {0xAAu, 0x08u}, - {0xADu, 0x10u}, - {0xAFu, 0x08u}, - {0xB1u, 0x08u}, - {0xB4u, 0x02u}, - {0xB7u, 0x80u}, - {0xC0u, 0x46u}, - {0xC2u, 0x8Du}, - {0xC4u, 0x5Bu}, - {0xCAu, 0x59u}, - {0xCCu, 0xCFu}, - {0xCEu, 0x9Du}, - {0xD6u, 0x3Eu}, - {0xD8u, 0x3Eu}, - {0xE2u, 0x04u}, - {0xE4u, 0x04u}, - {0xE6u, 0x01u}, - {0xE8u, 0x80u}, - {0xEAu, 0x40u}, - {0xECu, 0x40u}, - {0x00u, 0x06u}, - {0x01u, 0x55u}, - {0x02u, 0x09u}, - {0x03u, 0xAAu}, - {0x04u, 0x0Fu}, - {0x05u, 0xFFu}, - {0x09u, 0x69u}, - {0x0Bu, 0x96u}, - {0x10u, 0x40u}, - {0x11u, 0x0Fu}, - {0x12u, 0x1Fu}, - {0x13u, 0xF0u}, - {0x14u, 0x10u}, - {0x16u, 0x2Fu}, - {0x17u, 0xFFu}, - {0x19u, 0xFFu}, - {0x1Eu, 0x70u}, - {0x23u, 0xFFu}, - {0x24u, 0x05u}, - {0x26u, 0x0Au}, - {0x28u, 0x20u}, - {0x29u, 0x33u}, - {0x2Au, 0x4Fu}, - {0x2Bu, 0xCCu}, - {0x2Cu, 0x03u}, - {0x2Eu, 0x0Cu}, - {0x2Fu, 0xFFu}, - {0x31u, 0xFFu}, - {0x36u, 0x7Fu}, - {0x3Bu, 0x02u}, - {0x56u, 0x08u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x22u}, - {0x5Du, 0x90u}, - {0x5Fu, 0x01u}, - {0x80u, 0x0Bu}, - {0x81u, 0x55u}, - {0x82u, 0xF4u}, - {0x83u, 0xAAu}, - {0x84u, 0x02u}, - {0x88u, 0x10u}, - {0x89u, 0x69u}, - {0x8Au, 0x20u}, - {0x8Bu, 0x96u}, - {0x8Cu, 0x40u}, - {0x8Eu, 0x80u}, - {0x8Fu, 0xFFu}, - {0x90u, 0x08u}, - {0x92u, 0xF7u}, - {0x93u, 0xFFu}, - {0x95u, 0x0Fu}, - {0x96u, 0xF7u}, - {0x97u, 0xF0u}, - {0x98u, 0x03u}, - {0x99u, 0xFFu}, - {0x9Au, 0x0Cu}, - {0x9Cu, 0x10u}, - {0x9Eu, 0x20u}, - {0xA0u, 0x40u}, - {0xA1u, 0xFFu}, - {0xA2u, 0x80u}, - {0xA4u, 0xF4u}, - {0xA7u, 0xFFu}, - {0xA8u, 0xFDu}, - {0xA9u, 0x33u}, - {0xAAu, 0x02u}, - {0xABu, 0xCCu}, - {0xAEu, 0x01u}, - {0xB2u, 0x30u}, - {0xB4u, 0x0Fu}, - {0xB5u, 0xFFu}, - {0xB6u, 0xC0u}, - {0xBAu, 0xA8u}, - {0xBBu, 0x20u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x22u}, - {0xDFu, 0x01u}, - {0x01u, 0x02u}, - {0x03u, 0x20u}, + {0x00u, 0x22u}, + {0x01u, 0x80u}, + {0x03u, 0x10u}, {0x04u, 0x10u}, - {0x05u, 0x41u}, - {0x07u, 0x20u}, - {0x08u, 0x02u}, - {0x09u, 0x04u}, - {0x0Au, 0x01u}, + {0x06u, 0x80u}, + {0x07u, 0x10u}, + {0x08u, 0x08u}, + {0x09u, 0x28u}, + {0x0Au, 0x40u}, {0x0Du, 0x08u}, - {0x0Eu, 0x04u}, - {0x0Fu, 0x81u}, - {0x12u, 0x06u}, - {0x13u, 0x08u}, - {0x16u, 0x45u}, - {0x17u, 0x04u}, - {0x19u, 0x80u}, - {0x1Au, 0x01u}, - {0x1Cu, 0x10u}, - {0x1Du, 0x40u}, - {0x1Eu, 0x04u}, - {0x1Fu, 0x88u}, - {0x22u, 0x02u}, - {0x27u, 0x08u}, - {0x28u, 0x02u}, - {0x2Bu, 0x44u}, - {0x2Cu, 0x20u}, - {0x2Eu, 0x22u}, - {0x31u, 0x08u}, - {0x32u, 0x22u}, - {0x34u, 0x02u}, - {0x35u, 0x01u}, - {0x36u, 0x20u}, - {0x37u, 0x08u}, - {0x3Au, 0x14u}, - {0x3Bu, 0x09u}, - {0x3Fu, 0xA2u}, - {0x41u, 0x20u}, - {0x43u, 0x10u}, - {0x58u, 0x10u}, - {0x5Au, 0x80u}, - {0x5Cu, 0x41u}, - {0x5Du, 0x18u}, - {0x61u, 0x20u}, - {0x62u, 0x10u}, - {0x63u, 0x01u}, - {0x67u, 0x02u}, - {0x82u, 0x41u}, - {0x83u, 0x20u}, - {0x84u, 0x10u}, - {0x86u, 0x06u}, - {0x87u, 0x14u}, - {0x88u, 0x10u}, - {0x8Au, 0x80u}, - {0x8Du, 0x40u}, - {0x8Eu, 0x04u}, - {0x8Fu, 0x01u}, - {0xC0u, 0xFCu}, - {0xC2u, 0xFDu}, - {0xC4u, 0xF7u}, - {0xCAu, 0xEDu}, - {0xCCu, 0xE7u}, - {0xCEu, 0xB7u}, - {0xD6u, 0xFCu}, - {0xD8u, 0x1Cu}, - {0xE2u, 0x80u}, - {0xE4u, 0x10u}, - {0xE6u, 0x01u}, - {0x01u, 0x88u}, - {0x03u, 0x03u}, - {0x09u, 0x04u}, - {0x0Bu, 0x43u}, - {0x11u, 0xE0u}, - {0x17u, 0xECu}, - {0x19u, 0x21u}, - {0x1Bu, 0x02u}, - {0x1Fu, 0x01u}, - {0x23u, 0x12u}, - {0x33u, 0x0Fu}, - {0x35u, 0xE0u}, + {0x0Eu, 0x49u}, + {0x11u, 0x89u}, + {0x12u, 0x08u}, + {0x16u, 0x01u}, + {0x17u, 0x05u}, + {0x18u, 0x28u}, + {0x1Cu, 0x40u}, + {0x1Du, 0x6Cu}, + {0x1Eu, 0x08u}, + {0x1Fu, 0x10u}, + {0x22u, 0x58u}, + {0x27u, 0x02u}, + {0x28u, 0x04u}, + {0x2Du, 0x01u}, + {0x2Fu, 0x14u}, + {0x32u, 0x58u}, + {0x35u, 0x85u}, {0x37u, 0x10u}, - {0x3Fu, 0x10u}, - {0x40u, 0x34u}, - {0x41u, 0x06u}, - {0x42u, 0x10u}, + {0x38u, 0x04u}, + {0x3Cu, 0x02u}, + {0x3Du, 0xA0u}, + {0x3Eu, 0x08u}, + {0x5Cu, 0x40u}, + {0x5Eu, 0x02u}, + {0x5Fu, 0x24u}, + {0x62u, 0x92u}, + {0x63u, 0x20u}, + {0x65u, 0x40u}, + {0x82u, 0x20u}, + {0x85u, 0x10u}, + {0x89u, 0x01u}, + {0x8Fu, 0x41u}, + {0x90u, 0x06u}, + {0x91u, 0x92u}, + {0x94u, 0x28u}, + {0x95u, 0x20u}, + {0x96u, 0x20u}, + {0x97u, 0x01u}, + {0x98u, 0x04u}, + {0x9Au, 0x02u}, + {0x9Cu, 0x02u}, + {0x9Fu, 0x0Au}, + {0xA0u, 0x81u}, + {0xA4u, 0x44u}, + {0xA6u, 0x2Au}, + {0xA7u, 0x40u}, + {0xA8u, 0x11u}, + {0xAAu, 0x08u}, + {0xABu, 0x20u}, + {0xAEu, 0x02u}, + {0xAFu, 0x51u}, + {0xB1u, 0x80u}, + {0xB4u, 0x05u}, + {0xC0u, 0x7Fu}, + {0xC2u, 0xFEu}, + {0xC4u, 0xBFu}, + {0xCAu, 0xE4u}, + {0xCCu, 0xFEu}, + {0xCEu, 0xF2u}, + {0xD6u, 0xF0u}, + {0xD8u, 0x1Fu}, + {0xE2u, 0x06u}, + {0xE4u, 0x08u}, + {0xE6u, 0x01u}, + {0xE8u, 0x04u}, + {0xEAu, 0x11u}, + {0xECu, 0x81u}, + {0xEEu, 0x02u}, + {0x02u, 0x40u}, + {0x04u, 0x04u}, + {0x06u, 0x03u}, + {0x08u, 0x1Du}, + {0x0Au, 0xA2u}, + {0x0Cu, 0x80u}, + {0x0Eu, 0x08u}, + {0x10u, 0x90u}, + {0x12u, 0x08u}, + {0x14u, 0xE9u}, + {0x16u, 0x16u}, + {0x18u, 0x73u}, + {0x1Au, 0x0Cu}, + {0x1Cu, 0x88u}, + {0x20u, 0x88u}, + {0x24u, 0x08u}, + {0x26u, 0x80u}, + {0x28u, 0x88u}, + {0x30u, 0x18u}, + {0x32u, 0xE0u}, + {0x34u, 0x07u}, + {0x39u, 0x02u}, + {0x3Au, 0x2Eu}, + {0x3Fu, 0x01u}, + {0x40u, 0x26u}, + {0x41u, 0x03u}, + {0x42u, 0x40u}, {0x44u, 0x05u}, - {0x45u, 0xBEu}, + {0x45u, 0xDEu}, {0x46u, 0xFCu}, - {0x47u, 0x0Du}, + {0x47u, 0x0Bu}, {0x48u, 0x1Fu}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, @@ -1723,10 +954,12 @@ void cyfitter_cfg(void) {0x4Eu, 0xF0u}, {0x4Fu, 0x08u}, {0x50u, 0x04u}, + {0x56u, 0x02u}, + {0x57u, 0x28u}, + {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Au, 0x04u}, - {0x5Cu, 0x10u}, - {0x5Du, 0x01u}, + {0x5Bu, 0x04u}, {0x5Fu, 0x01u}, {0x62u, 0xC0u}, {0x64u, 0x40u}, @@ -1740,657 +973,1451 @@ void cyfitter_cfg(void) {0x6Du, 0x01u}, {0x6Eu, 0x40u}, {0x6Fu, 0x01u}, - {0x80u, 0xC0u}, - {0x84u, 0x24u}, - {0x85u, 0x40u}, - {0x86u, 0x10u}, - {0x87u, 0x30u}, - {0x88u, 0x11u}, - {0x89u, 0x32u}, - {0x8Au, 0x62u}, - {0x8Bu, 0x44u}, - {0x8Cu, 0x1Cu}, - {0x8Du, 0x0Du}, - {0x8Fu, 0x80u}, - {0x90u, 0x70u}, - {0x91u, 0x8Du}, - {0x92u, 0x0Fu}, - {0x94u, 0x21u}, - {0x95u, 0x8Du}, - {0x96u, 0x9Eu}, - {0x98u, 0x14u}, - {0x99u, 0x02u}, - {0x9Au, 0x08u}, - {0x9Bu, 0x0Du}, - {0x9Cu, 0x1Cu}, - {0xA0u, 0x08u}, - {0xA1u, 0x8Du}, - {0xA5u, 0x11u}, - {0xA7u, 0x62u}, - {0xA8u, 0x10u}, - {0xA9u, 0x8Du}, - {0xAAu, 0x0Cu}, - {0xACu, 0x0Cu}, - {0xADu, 0x52u}, - {0xAEu, 0x10u}, - {0xAFu, 0x28u}, - {0xB0u, 0xC1u}, - {0xB2u, 0x30u}, - {0xB3u, 0x70u}, - {0xB4u, 0x0Fu}, - {0xB5u, 0x0Fu}, - {0xB7u, 0x80u}, - {0xB8u, 0x02u}, - {0xBAu, 0x08u}, - {0xBBu, 0x28u}, - {0xBFu, 0x40u}, - {0xD6u, 0x02u}, - {0xD7u, 0x28u}, + {0x81u, 0xC0u}, + {0x82u, 0x80u}, + {0x84u, 0x8Du}, + {0x88u, 0x32u}, + {0x89u, 0x10u}, + {0x8Au, 0x44u}, + {0x8Bu, 0x0Cu}, + {0x8Cu, 0x8Du}, + {0x8Du, 0x0Cu}, + {0x8Fu, 0x10u}, + {0x90u, 0x40u}, + {0x91u, 0x24u}, + {0x92u, 0x30u}, + {0x93u, 0x10u}, + {0x95u, 0x21u}, + {0x97u, 0x9Eu}, + {0x98u, 0x52u}, + {0x99u, 0x14u}, + {0x9Au, 0x28u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x1Cu}, + {0x9Eu, 0x0Du}, + {0xA0u, 0x8Du}, + {0xA1u, 0x1Cu}, + {0xA4u, 0x8Du}, + {0xA5u, 0x08u}, + {0xA8u, 0x11u}, + {0xA9u, 0x70u}, + {0xAAu, 0x62u}, + {0xABu, 0x0Fu}, + {0xACu, 0x0Du}, + {0xADu, 0x11u}, + {0xAEu, 0x80u}, + {0xAFu, 0x62u}, + {0xB0u, 0x70u}, + {0xB1u, 0xC1u}, + {0xB3u, 0x0Fu}, + {0xB4u, 0x80u}, + {0xB6u, 0x0Fu}, + {0xB7u, 0x30u}, + {0xB9u, 0x02u}, + {0xBAu, 0x82u}, + {0xBBu, 0x80u}, + {0xBEu, 0x10u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDCu, 0x11u}, + {0xDFu, 0x01u}, + {0x00u, 0x88u}, + {0x02u, 0x80u}, + {0x03u, 0x08u}, + {0x04u, 0x14u}, + {0x06u, 0x80u}, + {0x07u, 0x09u}, + {0x0Au, 0x86u}, + {0x0Du, 0x08u}, + {0x0Eu, 0x49u}, + {0x10u, 0x20u}, + {0x11u, 0x40u}, + {0x12u, 0x08u}, + {0x13u, 0x01u}, + {0x17u, 0x16u}, + {0x1Au, 0x82u}, + {0x1Bu, 0x11u}, + {0x1Cu, 0x34u}, + {0x1Du, 0x01u}, + {0x1Eu, 0x60u}, + {0x1Fu, 0x14u}, + {0x20u, 0x03u}, + {0x21u, 0x01u}, + {0x22u, 0x0Cu}, + {0x23u, 0x40u}, + {0x27u, 0x80u}, + {0x28u, 0x40u}, + {0x29u, 0x10u}, + {0x2Au, 0x44u}, + {0x30u, 0x22u}, + {0x33u, 0x48u}, + {0x39u, 0x52u}, + {0x3Cu, 0x20u}, + {0x3Fu, 0x10u}, + {0x45u, 0x2Au}, + {0x48u, 0x03u}, + {0x4Du, 0x02u}, + {0x4Eu, 0x02u}, + {0x4Fu, 0x14u}, + {0x55u, 0x04u}, + {0x56u, 0xA8u}, + {0x67u, 0x20u}, + {0x6Du, 0xA1u}, + {0x6Eu, 0x01u}, + {0x6Fu, 0x15u}, + {0x75u, 0x80u}, + {0x76u, 0x01u}, + {0x77u, 0x02u}, + {0x8Du, 0x40u}, + {0x90u, 0x02u}, + {0x91u, 0x80u}, + {0x94u, 0x10u}, + {0x95u, 0x01u}, + {0x96u, 0x41u}, + {0x97u, 0x0Cu}, + {0x98u, 0x08u}, + {0x9Au, 0x02u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x81u}, + {0x9Eu, 0x99u}, + {0x9Fu, 0x15u}, + {0xA0u, 0x80u}, + {0xA1u, 0x28u}, + {0xA2u, 0x04u}, + {0xA4u, 0x10u}, + {0xA5u, 0x54u}, + {0xA6u, 0x81u}, + {0xA7u, 0x10u}, + {0xAAu, 0x80u}, + {0xABu, 0x20u}, + {0xACu, 0x44u}, + {0xADu, 0x10u}, + {0xAFu, 0x08u}, + {0xB2u, 0x08u}, + {0xC0u, 0xFFu}, + {0xC2u, 0xFBu}, + {0xC4u, 0x7Fu}, + {0xCAu, 0x0Fu}, + {0xCCu, 0x0Fu}, + {0xCEu, 0x0Du}, + {0xD0u, 0xE0u}, + {0xD2u, 0x30u}, + {0xD8u, 0x40u}, + {0xE0u, 0x02u}, + {0xE2u, 0x08u}, + {0xE8u, 0x80u}, + {0xEAu, 0x0Au}, + {0xEEu, 0x02u}, + {0x00u, 0x02u}, + {0x02u, 0x01u}, + {0x05u, 0xFFu}, + {0x09u, 0x55u}, + {0x0Bu, 0xAAu}, + {0x0Cu, 0x02u}, + {0x0Eu, 0x11u}, + {0x0Fu, 0xFFu}, + {0x11u, 0x69u}, + {0x13u, 0x96u}, + {0x14u, 0x02u}, + {0x16u, 0x09u}, + {0x18u, 0x02u}, + {0x1Au, 0x05u}, + {0x1Cu, 0x01u}, + {0x1Du, 0x0Fu}, + {0x1Eu, 0x02u}, + {0x1Fu, 0xF0u}, + {0x23u, 0xFFu}, + {0x25u, 0xFFu}, + {0x2Bu, 0xFFu}, + {0x2Du, 0x33u}, + {0x2Fu, 0xCCu}, + {0x30u, 0x04u}, + {0x31u, 0xFFu}, + {0x32u, 0x10u}, + {0x34u, 0x08u}, + {0x36u, 0x03u}, + {0x3Au, 0x80u}, + {0x3Bu, 0x02u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x22u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x80u, 0x0Fu}, + {0x81u, 0x96u}, + {0x82u, 0xF0u}, + {0x83u, 0x69u}, + {0x84u, 0xFFu}, + {0x85u, 0xFFu}, + {0x89u, 0xFFu}, + {0x8Au, 0xFFu}, + {0x8Fu, 0xFFu}, + {0x92u, 0xFFu}, + {0x93u, 0xFFu}, + {0x94u, 0x55u}, + {0x96u, 0xAAu}, + {0x97u, 0xFFu}, + {0x98u, 0x33u}, + {0x99u, 0x55u}, + {0x9Au, 0xCCu}, + {0x9Bu, 0xAAu}, + {0x9Du, 0x0Fu}, + {0x9Eu, 0xFFu}, + {0x9Fu, 0xF0u}, + {0xA4u, 0xFFu}, + {0xACu, 0x69u}, + {0xADu, 0x33u}, + {0xAEu, 0x96u}, + {0xAFu, 0xCCu}, + {0xB6u, 0xFFu}, + {0xB7u, 0xFFu}, + {0xBAu, 0x80u}, + {0xBBu, 0x80u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x11u}, - {0xDDu, 0x10u}, + {0xDCu, 0x22u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x05u, 0x15u}, - {0x06u, 0x02u}, - {0x0Eu, 0x5Au}, - {0x15u, 0x50u}, - {0x16u, 0x40u}, - {0x1Du, 0x15u}, - {0x1Fu, 0x20u}, - {0x21u, 0x88u}, - {0x23u, 0x08u}, - {0x24u, 0x01u}, - {0x26u, 0x20u}, - {0x27u, 0x10u}, - {0x29u, 0x02u}, - {0x2Du, 0x10u}, - {0x2Eu, 0x42u}, - {0x2Fu, 0x20u}, - {0x31u, 0x99u}, - {0x36u, 0x25u}, - {0x38u, 0x10u}, - {0x39u, 0x02u}, - {0x3Du, 0x40u}, - {0x3Eu, 0x18u}, - {0x40u, 0x13u}, - {0x41u, 0x01u}, - {0x42u, 0x50u}, - {0x46u, 0x08u}, - {0x47u, 0x10u}, - {0x48u, 0x01u}, - {0x49u, 0x12u}, - {0x4Bu, 0x04u}, - {0x51u, 0x04u}, - {0x52u, 0x50u}, - {0x66u, 0x08u}, - {0x6Du, 0x50u}, - {0x6Eu, 0x0Eu}, - {0x76u, 0x02u}, - {0x84u, 0x01u}, - {0x87u, 0x08u}, - {0x89u, 0x40u}, - {0x92u, 0x50u}, - {0x95u, 0x58u}, - {0x96u, 0x04u}, - {0x97u, 0x04u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x16u}, - {0x9Eu, 0x52u}, - {0xA1u, 0x40u}, - {0xA6u, 0x01u}, - {0xA7u, 0x20u}, - {0xABu, 0x20u}, - {0xADu, 0x84u}, - {0xB4u, 0x10u}, - {0xB5u, 0x01u}, - {0xC0u, 0xF0u}, - {0xC2u, 0xF0u}, - {0xC4u, 0xD0u}, - {0xCAu, 0xF1u}, - {0xCCu, 0xEFu}, - {0xCEu, 0x75u}, - {0xD0u, 0x0Bu}, - {0xD2u, 0x0Cu}, - {0xD8u, 0x40u}, - {0xE6u, 0x20u}, - {0xEEu, 0x40u}, - {0x04u, 0x42u}, - {0x08u, 0x77u}, - {0x0Au, 0x08u}, - {0x0Bu, 0x05u}, - {0x0Cu, 0xC6u}, - {0x10u, 0x01u}, - {0x12u, 0x5Eu}, - {0x14u, 0x39u}, - {0x15u, 0x08u}, - {0x16u, 0x06u}, - {0x18u, 0xC2u}, - {0x1Au, 0x04u}, - {0x1Bu, 0x01u}, - {0x1Cu, 0xC6u}, - {0x20u, 0x04u}, - {0x22u, 0x20u}, - {0x26u, 0x80u}, - {0x27u, 0x03u}, - {0x28u, 0x80u}, - {0x29u, 0x08u}, - {0x2Au, 0x46u}, - {0x2Cu, 0x46u}, - {0x2Du, 0x06u}, + {0x00u, 0x04u}, + {0x01u, 0x08u}, + {0x03u, 0x88u}, + {0x05u, 0x81u}, + {0x09u, 0x60u}, + {0x0Bu, 0x90u}, + {0x0Eu, 0x29u}, + {0x11u, 0x08u}, + {0x12u, 0x02u}, + {0x18u, 0x02u}, + {0x1Bu, 0x80u}, + {0x1Du, 0x01u}, + {0x1Eu, 0x29u}, + {0x21u, 0x40u}, + {0x22u, 0x40u}, + {0x26u, 0x01u}, + {0x27u, 0x40u}, + {0x2Bu, 0x01u}, + {0x2Du, 0x08u}, {0x2Eu, 0x80u}, - {0x30u, 0x70u}, - {0x32u, 0x0Fu}, - {0x33u, 0x07u}, - {0x34u, 0x80u}, + {0x2Fu, 0x48u}, + {0x30u, 0x01u}, + {0x32u, 0x60u}, + {0x33u, 0x08u}, + {0x34u, 0x02u}, + {0x37u, 0x40u}, + {0x38u, 0x24u}, + {0x3Bu, 0x81u}, + {0x3Du, 0x88u}, + {0x3Eu, 0x20u}, + {0x58u, 0x50u}, + {0x5Bu, 0x09u}, + {0x5Fu, 0x80u}, + {0x62u, 0x2Au}, + {0x63u, 0x11u}, + {0x65u, 0x80u}, + {0x84u, 0x10u}, + {0x87u, 0x80u}, + {0x8Bu, 0x01u}, + {0x8Du, 0x02u}, + {0x90u, 0x64u}, + {0x91u, 0x41u}, + {0x92u, 0x02u}, + {0x93u, 0xC8u}, + {0x94u, 0x02u}, + {0x95u, 0x80u}, + {0x96u, 0x01u}, + {0x97u, 0x02u}, + {0x98u, 0x01u}, + {0x99u, 0x30u}, + {0x9Au, 0xB0u}, + {0x9Eu, 0x40u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x21u}, + {0xA1u, 0x64u}, + {0xA3u, 0x09u}, + {0xA4u, 0x40u}, + {0xA5u, 0x08u}, + {0xA6u, 0xA3u}, + {0xA7u, 0x20u}, + {0xA8u, 0x04u}, + {0xAAu, 0x40u}, + {0xACu, 0x81u}, + {0xADu, 0x40u}, + {0xAFu, 0x0Au}, + {0xB1u, 0x40u}, + {0xB3u, 0x48u}, + {0xB5u, 0x80u}, + {0xB7u, 0x10u}, + {0xC0u, 0x9Eu}, + {0xC2u, 0xEFu}, + {0xC4u, 0x05u}, + {0xCAu, 0xF8u}, + {0xCCu, 0x9Fu}, + {0xCEu, 0x7Fu}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x1Fu}, + {0xE2u, 0x08u}, + {0xE4u, 0x10u}, + {0xE6u, 0x02u}, + {0xE8u, 0x80u}, + {0xECu, 0x80u}, + {0x04u, 0x02u}, + {0x08u, 0x02u}, + {0x0Cu, 0x02u}, + {0x12u, 0x04u}, + {0x15u, 0x01u}, + {0x17u, 0x02u}, + {0x19u, 0x02u}, + {0x1Bu, 0x01u}, + {0x1Cu, 0x02u}, + {0x1Du, 0x02u}, + {0x1Fu, 0x01u}, + {0x25u, 0x02u}, + {0x27u, 0x05u}, + {0x2Cu, 0x01u}, + {0x2Du, 0x02u}, + {0x2Fu, 0x09u}, + {0x32u, 0x04u}, + {0x33u, 0x03u}, + {0x34u, 0x02u}, + {0x35u, 0x04u}, + {0x36u, 0x01u}, {0x37u, 0x08u}, - {0x38u, 0x08u}, - {0x39u, 0x80u}, - {0x3Au, 0x03u}, - {0x3Eu, 0x10u}, - {0x54u, 0x40u}, - {0x56u, 0x04u}, + {0x3Bu, 0x08u}, + {0x3Eu, 0x50u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, - {0x5Du, 0x10u}, + {0x5Cu, 0x22u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x04u}, - {0x86u, 0xECu}, - {0x89u, 0x86u}, - {0x8Au, 0x01u}, - {0x8Du, 0x02u}, - {0x91u, 0x06u}, - {0x92u, 0x12u}, - {0x93u, 0x80u}, - {0x94u, 0x88u}, - {0x95u, 0x61u}, - {0x96u, 0x03u}, - {0x97u, 0x0Eu}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x21u}, - {0x9Du, 0x07u}, - {0x9Eu, 0x02u}, - {0x9Fu, 0x38u}, - {0xA0u, 0xE0u}, - {0xA1u, 0x86u}, - {0xA5u, 0x82u}, - {0xA7u, 0x04u}, - {0xA8u, 0x04u}, - {0xA9u, 0x09u}, - {0xAAu, 0x43u}, - {0xABu, 0x56u}, - {0xADu, 0x80u}, - {0xAFu, 0x06u}, - {0xB0u, 0xE0u}, - {0xB1u, 0x08u}, - {0xB2u, 0x0Fu}, - {0xB3u, 0x0Fu}, - {0xB4u, 0x10u}, - {0xB5u, 0x70u}, - {0xB7u, 0x80u}, - {0xB9u, 0x08u}, - {0xBEu, 0x01u}, - {0xBFu, 0x41u}, + {0x82u, 0x20u}, + {0x84u, 0xD8u}, + {0x85u, 0x0Fu}, + {0x86u, 0x03u}, + {0x87u, 0x80u}, + {0x88u, 0xC4u}, + {0x89u, 0x04u}, + {0x8Bu, 0x08u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x50u}, + {0x8Eu, 0xCEu}, + {0x8Fu, 0x8Fu}, + {0x90u, 0x02u}, + {0x91u, 0x04u}, + {0x93u, 0x08u}, + {0x94u, 0x03u}, + {0x95u, 0x01u}, + {0x96u, 0xD4u}, + {0x97u, 0x02u}, + {0x99u, 0x01u}, + {0x9Au, 0x01u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0x40u}, + {0x9Eu, 0x80u}, + {0xA0u, 0x40u}, + {0xA1u, 0x20u}, + {0xA2u, 0x80u}, + {0xA3u, 0x0Fu}, + {0xA6u, 0xDFu}, + {0xA7u, 0x10u}, + {0xA9u, 0x10u}, + {0xAAu, 0x08u}, + {0xABu, 0x8Fu}, + {0xADu, 0x4Fu}, + {0xAFu, 0x80u}, + {0xB0u, 0xC0u}, + {0xB2u, 0x1Fu}, + {0xB3u, 0x03u}, + {0xB5u, 0x0Cu}, + {0xB6u, 0x20u}, + {0xB7u, 0xF0u}, + {0xB9u, 0x80u}, + {0xBAu, 0x02u}, + {0xBBu, 0x28u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x22u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x28u}, - {0x05u, 0x14u}, - {0x06u, 0x02u}, - {0x09u, 0x88u}, - {0x0Bu, 0x80u}, - {0x0Eu, 0x56u}, - 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{0xA8u, 0x80u}, - {0xA9u, 0x08u}, - {0xAAu, 0x04u}, - {0xABu, 0x10u}, - {0xAEu, 0x40u}, - {0xAFu, 0x10u}, - {0xC0u, 0xE6u}, - {0xC2u, 0xFDu}, - {0xC4u, 0xFAu}, - {0xCAu, 0x7Fu}, - {0xCCu, 0x6Fu}, - {0xCEu, 0x2Du}, - {0xD8u, 0xF0u}, - {0xE2u, 0xD0u}, - {0xE8u, 0x01u}, - {0xEAu, 0x10u}, + {0xA1u, 0x04u}, + {0xA3u, 0x01u}, + {0xA4u, 0x01u}, + {0xA6u, 0x81u}, + {0xA7u, 0x04u}, + {0xABu, 0x68u}, + {0xACu, 0x04u}, + {0xADu, 0x82u}, + {0xAEu, 0x11u}, + {0xB0u, 0x50u}, + {0xB1u, 0x20u}, + {0xB7u, 0x20u}, + {0xC0u, 0xF7u}, + {0xC2u, 0xF9u}, + {0xC4u, 0x71u}, + {0xCAu, 0xFAu}, + {0xCCu, 0xEEu}, + {0xCEu, 0x70u}, + {0xD6u, 0x1Cu}, + {0xD8u, 0x1Cu}, + {0xE0u, 0x20u}, + {0xE2u, 0x02u}, + {0xE6u, 0x50u}, + {0xE8u, 0x42u}, + {0xECu, 0x01u}, {0xEEu, 0x08u}, - {0x00u, 0x0Du}, - {0x01u, 0x11u}, - {0x02u, 0x10u}, - {0x03u, 0x22u}, - {0x04u, 0x02u}, - {0x05u, 0x44u}, - {0x06u, 0x0Du}, - {0x07u, 0x88u}, - {0x08u, 0x1Du}, - {0x09u, 0x48u}, - {0x0Bu, 0x84u}, - {0x0Cu, 0x1Du}, - {0x0Du, 0x33u}, - {0x0Fu, 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{0x33u, 0x0Cu}, + {0x35u, 0x03u}, + {0x36u, 0x80u}, + {0x3Bu, 0x20u}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x04u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, + {0x5Cu, 0x22u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x0Fu}, - {0x82u, 0xF0u}, - {0x84u, 0x84u}, - {0x85u, 0x20u}, - {0x86u, 0x48u}, - {0x88u, 0x21u}, - {0x89u, 0x10u}, - {0x8Au, 0x12u}, - {0x8Du, 0x80u}, - {0x90u, 0x11u}, - {0x91u, 0x08u}, - {0x92u, 0x22u}, - {0x93u, 0x04u}, - {0x95u, 0x40u}, - {0x96u, 0xFFu}, - {0x99u, 0x01u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x33u}, - {0x9Du, 0x04u}, - {0x9Eu, 0xCCu}, - {0x9Fu, 0x08u}, - {0xA1u, 0x53u}, - {0xA3u, 0xACu}, - {0xA4u, 0x44u}, - {0xA6u, 0x88u}, - {0xA9u, 0x02u}, - {0xAAu, 0xFFu}, - {0xABu, 0x01u}, - {0xACu, 0xFFu}, - {0xB0u, 0xFFu}, - {0xB1u, 0xC0u}, - {0xB3u, 0x0Fu}, - {0xB7u, 0x30u}, - {0xBEu, 0x01u}, - {0xBFu, 0x45u}, + {0x80u, 0x06u}, + {0x82u, 0x09u}, + {0x84u, 0x0Fu}, + {0x86u, 0xF0u}, + {0x88u, 0x05u}, + {0x89u, 0x04u}, + {0x8Au, 0x0Au}, + {0x8Cu, 0x30u}, + {0x8Du, 0x40u}, + {0x8Eu, 0xC0u}, + {0x91u, 0x10u}, + {0x94u, 0x60u}, + {0x95u, 0x08u}, + {0x96u, 0x90u}, + {0x99u, 0x02u}, + {0x9Du, 0x01u}, + {0xA0u, 0x50u}, + {0xA1u, 0x20u}, + {0xA2u, 0xA0u}, + {0xA4u, 0x03u}, + {0xA5u, 0x55u}, + {0xA6u, 0x0Cu}, + {0xA7u, 0xAAu}, + {0xADu, 0x80u}, + {0xB1u, 0x30u}, + {0xB3u, 0x03u}, + {0xB4u, 0xFFu}, + {0xB5u, 0x0Cu}, + {0xB7u, 0xC0u}, + {0xBEu, 0x10u}, + {0xBFu, 0x55u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x08u}, - {0x01u, 0x02u}, - {0x03u, 0x08u}, - {0x04u, 0x06u}, - {0x06u, 0x01u}, - {0x07u, 0x04u}, - {0x09u, 0x41u}, - {0x0Bu, 0x20u}, - {0x0Du, 0x02u}, - {0x0Eu, 0x06u}, + {0x00u, 0x20u}, + {0x01u, 0x14u}, + {0x02u, 0x81u}, + {0x03u, 0x20u}, + {0x04u, 0x42u}, + {0x06u, 0x08u}, + {0x0Au, 0x20u}, + {0x0Eu, 0x16u}, + {0x10u, 0xA0u}, + {0x14u, 0x04u}, + {0x15u, 0x80u}, + {0x17u, 0x01u}, + {0x19u, 0x20u}, + {0x1Cu, 0x40u}, + {0x1Fu, 0x40u}, + {0x21u, 0x22u}, + {0x22u, 0x44u}, + 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{0x82u, 0x08u}, + {0x84u, 0x20u}, + {0x85u, 0xCAu}, + {0x86u, 0x40u}, + {0x87u, 0x15u}, + {0x88u, 0x63u}, + {0x89u, 0x40u}, + {0x8Bu, 0x80u}, + {0x8Fu, 0xFFu}, + {0x90u, 0x10u}, + {0x91u, 0x40u}, + {0x92u, 0x67u}, + {0x93u, 0x80u}, + {0x95u, 0xE0u}, + {0x96u, 0x10u}, + {0x99u, 0x11u}, + {0x9Au, 0x73u}, + {0x9Bu, 0xECu}, + {0x9Eu, 0x0Cu}, + {0x9Fu, 0x10u}, + {0xA0u, 0x20u}, + {0xA1u, 0x06u}, + {0xA2u, 0x40u}, + {0xA5u, 0x01u}, + {0xA6u, 0x63u}, + {0xA8u, 0x01u}, + {0xAAu, 0x02u}, + {0xACu, 0x01u}, + {0xADu, 0x0Bu}, + {0xAEu, 0x02u}, + {0xAFu, 0xF4u}, + {0xB2u, 0x60u}, + {0xB3u, 0xC0u}, + {0xB4u, 0x03u}, + {0xB5u, 0x3Fu}, + {0xB6u, 0x1Cu}, + {0xBAu, 0x28u}, + {0xBBu, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x22u}, + {0xDFu, 0x01u}, + {0x01u, 0x60u}, + {0x02u, 0x10u}, + {0x04u, 0x20u}, + {0x05u, 0x05u}, + {0x09u, 0x02u}, + {0x0Au, 0x06u}, + {0x0Cu, 0x11u}, + {0x0Eu, 0x22u}, + {0x0Fu, 0x08u}, + {0x11u, 0x24u}, + {0x12u, 0x40u}, + {0x14u, 0x02u}, + {0x15u, 0x10u}, + {0x16u, 0x80u}, + {0x17u, 0x08u}, + {0x18u, 0x10u}, {0x1Du, 0x04u}, {0x1Eu, 0x02u}, - {0x20u, 0x02u}, - {0x23u, 0xA0u}, - {0x27u, 0x08u}, - {0x28u, 0x04u}, - {0x2Bu, 0x40u}, - {0x2Cu, 0x02u}, - {0x2Du, 0x08u}, - {0x2Fu, 0x18u}, - {0x31u, 0x80u}, - {0x32u, 0x15u}, - {0x35u, 0x02u}, - {0x37u, 0x22u}, - {0x38u, 0x28u}, - {0x3Bu, 0x40u}, - {0x3Du, 0x86u}, - {0x3Eu, 0x10u}, + {0x1Fu, 0x24u}, + {0x20u, 0x20u}, + {0x22u, 0x14u}, + {0x24u, 0x04u}, + {0x25u, 0x08u}, + {0x28u, 0x01u}, + {0x29u, 0x02u}, + {0x2Bu, 0x44u}, + {0x2Cu, 0x81u}, + {0x2Eu, 0x04u}, + {0x30u, 0x20u}, + {0x32u, 0x14u}, + {0x34u, 0x90u}, + {0x36u, 0x06u}, + {0x38u, 0x84u}, + {0x3Bu, 0x20u}, + {0x3Cu, 0x04u}, + {0x3Eu, 0x20u}, {0x3Fu, 0x80u}, - {0x59u, 0x80u}, - {0x63u, 0x01u}, - {0x65u, 0x24u}, - {0x66u, 0x80u}, - {0x8Bu, 0x80u}, - {0x8Eu, 0x01u}, - {0x90u, 0x2Au}, - {0x91u, 0x24u}, - {0x92u, 0x3Eu}, - {0x93u, 0x40u}, - {0x94u, 0x40u}, - {0x97u, 0x01u}, - {0x98u, 0x84u}, - {0x99u, 0x28u}, - {0x9Au, 0x01u}, - {0x9Bu, 0x46u}, - {0x9Fu, 0x28u}, - {0xA0u, 0x06u}, - {0xA1u, 0xC3u}, - {0xA3u, 0x08u}, - {0xA9u, 0x02u}, - {0xAAu, 0x04u}, - {0xB6u, 0x80u}, - {0xC0u, 0xFEu}, - {0xC2u, 0xFDu}, - {0xC4u, 0xD7u}, - {0xCAu, 0x75u}, - {0xCCu, 0xAFu}, - {0xCEu, 0xFEu}, - {0xD6u, 0x08u}, - {0xD8u, 0x78u}, - {0xE2u, 0x10u}, - {0xEAu, 0x10u}, - {0xEEu, 0x08u}, - {0xB0u, 0x01u}, + {0x5Du, 0x8Au}, + {0x5Fu, 0x10u}, + {0x67u, 0x02u}, + {0x79u, 0x40u}, + {0x7Au, 0x01u}, + {0x80u, 0x40u}, + {0x81u, 0x08u}, + {0x85u, 0x10u}, + {0x87u, 0x14u}, + {0x89u, 0x18u}, + {0x8Au, 0x02u}, + {0x8Bu, 0x60u}, + {0xC0u, 0x77u}, + {0xC2u, 0xFBu}, + {0xC4u, 0xFEu}, + {0xCAu, 0xDCu}, + {0xCCu, 0xF6u}, + {0xCEu, 0x7Eu}, + {0xD6u, 0xF0u}, + {0xD8u, 0x10u}, + {0xE0u, 0x20u}, + {0xE2u, 0x80u}, + {0xE6u, 0x20u}, + {0x83u, 0x01u}, + {0x87u, 0x12u}, + {0x88u, 0x06u}, + {0x89u, 0xE0u}, + {0x93u, 0xECu}, + {0x94u, 0x32u}, + {0x95u, 0x04u}, + {0x96u, 0x01u}, + {0x97u, 0x43u}, + {0x98u, 0x01u}, + {0x99u, 0x88u}, + {0x9Au, 0x2Cu}, + {0x9Bu, 0x03u}, + {0x9Eu, 0x08u}, + {0xA8u, 0x01u}, + {0xA9u, 0x21u}, + {0xAAu, 0x1Au}, + {0xABu, 0x02u}, {0xB1u, 0x10u}, - {0xB2u, 0x80u}, - {0xB5u, 0x80u}, - {0xB7u, 0x10u}, - {0xE8u, 0x10u}, - {0x04u, 0x40u}, - {0x0Cu, 0x10u}, - {0x0Du, 0x04u}, - {0x12u, 0x01u}, + {0xB2u, 0x07u}, + {0xB5u, 0xE0u}, + {0xB6u, 0x38u}, + {0xB7u, 0x0Fu}, + {0xB8u, 0x08u}, + {0xBFu, 0x10u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDFu, 0x01u}, + {0x00u, 0x80u}, + {0x01u, 0x01u}, + {0x02u, 0x04u}, + {0x03u, 0x20u}, + {0x04u, 0x10u}, + {0x08u, 0x02u}, + {0x0Au, 0x04u}, + {0x0Bu, 0x01u}, + {0x0Cu, 0x40u}, + {0x0Eu, 0x2Au}, + {0x10u, 0x20u}, + {0x11u, 0x50u}, + {0x14u, 0x0Cu}, + {0x18u, 0x04u}, + {0x19u, 0x15u}, + {0x1Au, 0x04u}, + {0x1Bu, 0x0Au}, + {0x1Cu, 0x10u}, + {0x1Eu, 0x02u}, + {0x20u, 0x40u}, + {0x25u, 0x01u}, + {0x26u, 0x20u}, + {0x27u, 0x02u}, + {0x29u, 0x14u}, + {0x2Au, 0x02u}, + {0x2Bu, 0x20u}, + {0x2Cu, 0x04u}, + {0x30u, 0x20u}, + {0x32u, 0x04u}, + {0x33u, 0x41u}, + {0x36u, 0x14u}, + {0x37u, 0x02u}, + {0x38u, 0x81u}, + {0x39u, 0x18u}, + {0x3Cu, 0x10u}, + {0x3Du, 0x02u}, + {0x3Eu, 0x08u}, + {0x40u, 0x04u}, + {0x43u, 0x0Au}, + {0x48u, 0x01u}, + {0x49u, 0x08u}, + {0x4Au, 0x88u}, + {0x50u, 0x40u}, + {0x52u, 0x54u}, + {0x53u, 0x80u}, + {0x5Cu, 0x03u}, + {0x63u, 0x02u}, + {0x68u, 0x64u}, + {0x69u, 0x50u}, + {0x6Bu, 0x41u}, + {0x72u, 0x02u}, + {0x73u, 0x01u}, + {0x81u, 0x10u}, + {0x84u, 0x01u}, + {0x88u, 0x40u}, + {0x8Au, 0x20u}, + {0x8Cu, 0x10u}, + {0x90u, 0x01u}, + {0x91u, 0x09u}, + {0x92u, 0x08u}, + {0x94u, 0x44u}, + {0x95u, 0x50u}, + {0x96u, 0x04u}, + {0x97u, 0x01u}, + {0x98u, 0x08u}, + {0x9Au, 0x08u}, + {0x9Du, 0x19u}, + {0x9Eu, 0x54u}, + {0x9Fu, 0x40u}, + {0xA1u, 0x10u}, + {0xA2u, 0x1Cu}, + {0xA3u, 0x01u}, + {0xA4u, 0x64u}, + {0xA6u, 0x80u}, + {0xA7u, 0x88u}, + {0xA8u, 0x01u}, + {0xABu, 0x04u}, + {0xACu, 0x08u}, + {0xB2u, 0x20u}, + {0xB3u, 0x20u}, + {0xC0u, 0x4Fu}, + {0xC2u, 0xEBu}, + {0xC4u, 0x47u}, + {0xCAu, 0x27u}, + {0xCCu, 0xEFu}, + {0xCEu, 0xEFu}, + {0xD0u, 0x07u}, + {0xD2u, 0x0Cu}, + {0xD8u, 0x08u}, + {0xE2u, 0xB0u}, + {0xEAu, 0x02u}, + {0xECu, 0x04u}, + {0x02u, 0x10u}, + {0x04u, 0x02u}, + {0x06u, 0x0Du}, + {0x08u, 0x3Du}, + {0x0Cu, 0x0Du}, + {0x0Du, 0xE0u}, + {0x0Eu, 0x30u}, + {0x13u, 0x01u}, + {0x14u, 0x01u}, + {0x15u, 0x31u}, + {0x16u, 0x02u}, + {0x17u, 0x02u}, + {0x18u, 0x02u}, + {0x19u, 0x98u}, + {0x1Au, 0x04u}, + {0x1Bu, 0x03u}, + {0x1Cu, 0x3Du}, + {0x1Fu, 0xECu}, + {0x20u, 0x3Du}, + {0x23u, 0x02u}, + {0x24u, 0x02u}, + {0x26u, 0x08u}, + {0x28u, 0x3Du}, + {0x29u, 0x14u}, + {0x2Bu, 0x43u}, + {0x30u, 0x20u}, + {0x31u, 0x0Fu}, + {0x32u, 0x0Fu}, + {0x34u, 0x10u}, + {0x35u, 0xE0u}, + {0x36u, 0x20u}, + {0x37u, 0x10u}, + {0x3Au, 0x08u}, + {0x3Eu, 0x51u}, + {0x3Fu, 0x50u}, + {0x54u, 0x40u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x10u}, + {0x5Fu, 0x01u}, + {0x80u, 0x01u}, + {0x84u, 0xA2u}, + {0x86u, 0x08u}, + {0x88u, 0x08u}, + {0x8Au, 0x61u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x08u}, + {0x92u, 0x40u}, + {0x95u, 0x01u}, + {0x98u, 0x07u}, + {0x99u, 0x02u}, + {0x9Au, 0xD8u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x10u}, + {0xA0u, 0x10u}, + {0xA1u, 0x20u}, + {0xA4u, 0x01u}, + {0xA5u, 0x08u}, + {0xA8u, 0x04u}, + {0xA9u, 0x11u}, + {0xABu, 0x22u}, + {0xACu, 0x01u}, + {0xAFu, 0x04u}, + {0xB0u, 0xE0u}, + {0xB1u, 0x04u}, + {0xB3u, 0x08u}, + {0xB4u, 0x3Fu}, + {0xB5u, 0x03u}, + {0xB6u, 0x08u}, + {0xB7u, 0x30u}, + {0xB8u, 0x20u}, + {0xB9u, 0x08u}, + {0xBEu, 0x50u}, + {0xBFu, 0x50u}, + {0xD4u, 0x09u}, + {0xD6u, 0x04u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, + {0xDDu, 0x10u}, + {0xDFu, 0x01u}, + {0x00u, 0x85u}, + {0x03u, 0x08u}, + {0x05u, 0x06u}, + {0x06u, 0x80u}, + {0x07u, 0x05u}, + {0x08u, 0x40u}, + {0x0Au, 0x48u}, + {0x0Bu, 0x01u}, + {0x0Du, 0x08u}, + {0x0Eu, 0x09u}, + {0x10u, 0x20u}, + {0x11u, 0x40u}, + {0x12u, 0x40u}, + {0x13u, 0x10u}, + {0x17u, 0x1Au}, + {0x19u, 0x80u}, + {0x1Au, 0x40u}, + {0x1Bu, 0x10u}, + {0x1Du, 0x06u}, + {0x1Eu, 0x02u}, + {0x1Fu, 0x10u}, + {0x21u, 0x44u}, + {0x22u, 0x22u}, + {0x23u, 0x10u}, + {0x25u, 0x90u}, + {0x27u, 0x80u}, + {0x2Au, 0x42u}, + {0x2Bu, 0x14u}, + {0x2Fu, 0x88u}, + {0x30u, 0x88u}, + {0x33u, 0x20u}, + {0x35u, 0x10u}, + {0x36u, 0x0Au}, + {0x37u, 0x80u}, + {0x38u, 0x40u}, + {0x3Fu, 0x40u}, + {0x58u, 0x20u}, + {0x59u, 0x89u}, + {0x60u, 0x20u}, + {0x61u, 0x80u}, + {0x62u, 0x05u}, + {0x66u, 0xA0u}, + {0x67u, 0x20u}, + {0x80u, 0x02u}, + {0x81u, 0x40u}, + {0x82u, 0x40u}, + {0x85u, 0x01u}, + {0x86u, 0x08u}, + {0x8Eu, 0x01u}, + {0x90u, 0x03u}, + {0x92u, 0x09u}, + {0x93u, 0x40u}, + {0x95u, 0x50u}, + {0x96u, 0x04u}, + {0x97u, 0x01u}, + {0x98u, 0x08u}, + {0x99u, 0x02u}, + {0x9Au, 0x2Au}, + {0x9Bu, 0x1Fu}, + {0x9Cu, 0x42u}, + {0x9Du, 0x10u}, + {0x9Eu, 0x14u}, + {0x9Fu, 0x40u}, + {0xA0u, 0x80u}, + {0xA1u, 0x08u}, + {0xA2u, 0x1Cu}, + {0xA3u, 0x01u}, + {0xA4u, 0x64u}, + {0xA5u, 0x02u}, + {0xA6u, 0x81u}, + {0xA7u, 0x08u}, + {0xAAu, 0x02u}, + {0xAEu, 0x48u}, + {0xAFu, 0x80u}, + {0xC0u, 0xFFu}, + {0xC2u, 0xEBu}, + {0xC4u, 0x7Fu}, + {0xCAu, 0xAFu}, + {0xCCu, 0xFEu}, + {0xCEu, 0x18u}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x79u}, + {0xE0u, 0x01u}, + {0xE6u, 0x41u}, + {0xEEu, 0x08u}, + {0x00u, 0x33u}, + {0x02u, 0xCCu}, + {0x03u, 0x80u}, + {0x04u, 0x12u}, + {0x05u, 0x0Fu}, + {0x06u, 0x21u}, + {0x08u, 0x0Fu}, + {0x09u, 0x01u}, + {0x0Au, 0xF0u}, + {0x0Bu, 0x02u}, + {0x0Cu, 0x48u}, + {0x0Eu, 0x84u}, + {0x0Fu, 0x40u}, + {0x10u, 0xFFu}, + {0x11u, 0x04u}, + {0x13u, 0x08u}, + {0x15u, 0x01u}, + {0x17u, 0x02u}, + {0x19u, 0x04u}, + {0x1Au, 0xFFu}, + {0x1Bu, 0x08u}, + {0x1Cu, 0xFFu}, + {0x1Fu, 0x30u}, + {0x20u, 0x44u}, + {0x22u, 0x88u}, + {0x23u, 0x0Fu}, + {0x25u, 0x4Fu}, + {0x27u, 0x20u}, + {0x2Bu, 0x4Fu}, + {0x2Cu, 0x11u}, + {0x2Du, 0x40u}, + {0x2Eu, 0x22u}, + {0x2Fu, 0x1Fu}, + {0x30u, 0xFFu}, + {0x31u, 0x0Cu}, + {0x33u, 0x03u}, + {0x35u, 0x80u}, + {0x37u, 0x70u}, + {0x3Bu, 0x0Au}, + {0x3Eu, 0x01u}, + {0x54u, 0x01u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x20u}, + {0x5Du, 0x20u}, + {0x5Fu, 0x01u}, + {0x80u, 0x44u}, + {0x82u, 0x88u}, + {0x84u, 0x12u}, + {0x86u, 0x21u}, + {0x88u, 0x0Fu}, + {0x89u, 0x0Fu}, + {0x8Au, 0xF0u}, + {0x8Bu, 0xF0u}, + {0x8Cu, 0x11u}, + {0x8Du, 0x11u}, + {0x8Eu, 0x22u}, + {0x8Fu, 0x22u}, + {0x91u, 0x33u}, + {0x92u, 0xFFu}, + {0x93u, 0xCCu}, + {0x94u, 0x33u}, + {0x96u, 0xCCu}, + {0x98u, 0x48u}, + {0x9Au, 0x84u}, + {0x9Bu, 0xFFu}, + {0x9Du, 0xFFu}, + {0x9Eu, 0xFFu}, + {0xA1u, 0x44u}, + {0xA3u, 0x88u}, + {0xA5u, 0x84u}, + {0xA6u, 0xFFu}, + {0xA7u, 0x48u}, + {0xA9u, 0x21u}, + {0xABu, 0x12u}, + {0xAFu, 0xFFu}, + {0xB1u, 0xFFu}, + {0xB4u, 0xFFu}, + {0xBEu, 0x10u}, + {0xBFu, 0x01u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x01u, 0x71u}, + {0x02u, 0x10u}, + {0x05u, 0x23u}, + {0x06u, 0x12u}, + {0x08u, 0x18u}, + {0x09u, 0x02u}, + {0x0Au, 0x83u}, + {0x0Bu, 0x08u}, + {0x0Cu, 0x20u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x01u}, + {0x0Fu, 0x02u}, + {0x10u, 0x20u}, + {0x14u, 0x40u}, + {0x15u, 0x41u}, + {0x1Bu, 0x20u}, + {0x1Fu, 0x01u}, + {0x20u, 0x80u}, + {0x25u, 0x09u}, + {0x26u, 0x82u}, + {0x27u, 0x04u}, + {0x28u, 0x50u}, + {0x2Au, 0x10u}, + {0x2Bu, 0x01u}, + {0x2Cu, 0x01u}, + {0x2Du, 0x08u}, + {0x2Fu, 0x48u}, + {0x30u, 0x20u}, + {0x31u, 0x01u}, + {0x32u, 0x40u}, + {0x35u, 0x10u}, + {0x36u, 0x8Au}, + {0x39u, 0x50u}, + {0x3Cu, 0x02u}, + {0x3Du, 0x08u}, + {0x3Eu, 0x20u}, + {0x3Fu, 0x40u}, + {0x41u, 0x08u}, + {0x42u, 0x20u}, + {0x5Bu, 0x40u}, + {0x5Cu, 0x40u}, + {0x60u, 0x02u}, + {0x62u, 0x40u}, + {0x81u, 0x01u}, + {0x90u, 0x40u}, + {0x91u, 0x41u}, + {0x92u, 0x02u}, + {0x93u, 0xC8u}, + {0x97u, 0x02u}, + {0x98u, 0x01u}, + {0x99u, 0x38u}, + {0x9Au, 0x10u}, + {0x9Cu, 0x02u}, + {0x9Eu, 0x40u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x21u}, + {0xA1u, 0x06u}, + {0xA2u, 0x08u}, + {0xA3u, 0x08u}, + {0xA4u, 0x40u}, + {0xA5u, 0x08u}, + {0xA6u, 0x80u}, + {0xA7u, 0x20u}, + {0xAFu, 0x08u}, + {0xB0u, 0x40u}, + {0xC0u, 0xFFu}, + {0xC2u, 0xDFu}, + {0xC4u, 0x94u}, + {0xCAu, 0xFFu}, + {0xCCu, 0xFDu}, + {0xCEu, 0xFCu}, + {0xD6u, 0x18u}, + {0xD8u, 0x08u}, + {0xE0u, 0x01u}, + {0xEAu, 0x08u}, + {0xEEu, 0x08u}, + {0xA8u, 0x08u}, + {0xA9u, 0x02u}, + {0xABu, 0x40u}, + {0xAEu, 0x10u}, + {0xB2u, 0x02u}, + {0xB3u, 0x04u}, + {0xE8u, 0x20u}, + {0xEAu, 0x80u}, + {0xEEu, 0x01u}, + {0x05u, 0x20u}, + {0x0Eu, 0x20u}, + {0x0Fu, 0x04u}, + {0x12u, 0x08u}, {0x13u, 0x02u}, {0x16u, 0x80u}, - {0x17u, 0x40u}, - {0x30u, 0x40u}, + {0x17u, 0x80u}, + {0x30u, 0x10u}, {0x33u, 0x01u}, - {0x34u, 0x20u}, - {0x36u, 0x02u}, - {0x3Au, 0x82u}, - {0x3Cu, 0x02u}, - {0x3Fu, 0x20u}, - {0x42u, 0x08u}, - {0x53u, 0x20u}, - {0x54u, 0x80u}, + {0x36u, 0x20u}, + {0x37u, 0x08u}, + {0x39u, 0x04u}, + {0x3Au, 0x80u}, + {0x3Cu, 0x10u}, + {0x3Eu, 0x04u}, + {0x40u, 0x04u}, + {0x56u, 0x02u}, + {0x59u, 0x40u}, {0x6Bu, 0x03u}, - {0x82u, 0x02u}, - {0x88u, 0x10u}, - {0x8Fu, 0x20u}, + {0x83u, 0x08u}, {0xC0u, 0x80u}, {0xC2u, 0xA0u}, {0xC4u, 0xF0u}, {0xCCu, 0xF0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, - {0xD4u, 0x60u}, - {0xE6u, 0x20u}, - {0x01u, 0x20u}, - {0x0Bu, 0x02u}, - {0x30u, 0x10u}, - {0x32u, 0x08u}, - {0x36u, 0x01u}, - {0x37u, 0x40u}, - {0x39u, 0x80u}, - {0x56u, 0x04u}, - {0x62u, 0x02u}, - {0x64u, 0x10u}, - {0x66u, 0x01u}, - {0x80u, 0x80u}, - {0x86u, 0x02u}, - {0x89u, 0x24u}, - {0x90u, 0x40u}, - {0x91u, 0x08u}, - {0x9Au, 0x05u}, - {0x9Bu, 0x40u}, - {0x9Cu, 0x60u}, - {0x9Eu, 0x08u}, - {0xA4u, 0x81u}, - {0xAEu, 0x02u}, - {0xB6u, 0x04u}, - {0xB7u, 0x10u}, + {0xD4u, 0x80u}, + {0xD6u, 0x20u}, + {0xE2u, 0x20u}, + {0x03u, 0x02u}, + {0x0Au, 0x01u}, + {0x30u, 0x04u}, + {0x33u, 0x10u}, + {0x34u, 0x02u}, + {0x37u, 0x80u}, + {0x3Au, 0x80u}, + {0x5Au, 0x20u}, + {0x63u, 0x80u}, + {0x84u, 0x02u}, + {0x89u, 0x20u}, + {0x93u, 0x04u}, + {0x94u, 0x04u}, + {0x96u, 0x04u}, + {0x99u, 0x20u}, + {0x9Bu, 0x90u}, + {0x9Cu, 0x10u}, + {0x9Du, 0x40u}, + {0xA2u, 0x10u}, + {0xA6u, 0x20u}, + {0xA8u, 0x10u}, + {0xAAu, 0x08u}, + {0xABu, 0x10u}, + {0xADu, 0x04u}, + {0xB6u, 0x02u}, {0xC0u, 0x40u}, {0xC2u, 0x40u}, {0xCCu, 0xF0u}, {0xCEu, 0x10u}, - {0xD4u, 0x40u}, + {0xD4u, 0x80u}, {0xD8u, 0x40u}, - {0xE2u, 0x60u}, - {0xEAu, 0x40u}, - {0x10u, 0x40u}, + {0xE6u, 0x40u}, + {0xEEu, 0xC0u}, + {0x10u, 0x10u}, {0x33u, 0x80u}, - {0x5Bu, 0x02u}, - {0x8Au, 0x08u}, - {0x8Fu, 0x01u}, - {0x93u, 0x02u}, - {0x95u, 0x80u}, - {0x9Cu, 0x60u}, - {0x9Eu, 0x08u}, - {0xA4u, 0x01u}, - {0xA6u, 0x09u}, - {0xB4u, 0x40u}, + {0x83u, 0x40u}, + {0x86u, 0x80u}, + {0x93u, 0x04u}, + {0x94u, 0x04u}, + {0x9Cu, 0x14u}, + {0x9Eu, 0x80u}, + {0xA2u, 0x10u}, + {0xA7u, 0x40u}, + {0xAAu, 0x10u}, + {0xADu, 0x40u}, + {0xAEu, 0x05u}, + {0xB3u, 0x02u}, + {0xB6u, 0x20u}, {0xC4u, 0x10u}, {0xCCu, 0x10u}, - {0xD6u, 0x40u}, - {0x8Au, 0x08u}, - {0x8Eu, 0x04u}, - {0x9Cu, 0x20u}, - {0x9Eu, 0x08u}, - {0xA4u, 0x01u}, - {0xA6u, 0x01u}, + {0xE2u, 0x60u}, + {0xE8u, 0x10u}, + {0xEAu, 0x40u}, + {0xEEu, 0x30u}, + {0x68u, 0x40u}, + {0x84u, 0x04u}, + {0x87u, 0x04u}, + {0x93u, 0x04u}, + {0x94u, 0x04u}, + {0x9Cu, 0x04u}, {0xA7u, 0x80u}, - {0xA9u, 0x40u}, - {0xB3u, 0x02u}, - {0xEAu, 0x80u}, + {0xB2u, 0x10u}, + {0xDCu, 0x20u}, + {0xE0u, 0x40u}, + {0xE2u, 0x10u}, + {0x05u, 0x08u}, {0x06u, 0x08u}, - {0x07u, 0x10u}, - {0x08u, 0x02u}, - {0x0Au, 0x02u}, + {0x08u, 0x08u}, + {0x09u, 0x20u}, {0x13u, 0x02u}, - {0x56u, 0x20u}, - {0x5Cu, 0x04u}, - {0x60u, 0x20u}, - {0x80u, 0x02u}, - {0x8Bu, 0x02u}, + {0x52u, 0x20u}, + {0x58u, 0x02u}, + {0x62u, 0x02u}, + {0x71u, 0x04u}, {0xC0u, 0x05u}, {0xC2u, 0x0Au}, {0xC4u, 0x08u}, - {0xD4u, 0x02u}, - {0xD6u, 0x01u}, + {0xD4u, 0x04u}, + {0xD6u, 0x02u}, {0xD8u, 0x02u}, - {0xE2u, 0x04u}, - {0x00u, 0x08u}, + {0xDCu, 0x01u}, + {0x00u, 0x02u}, {0x02u, 0x02u}, - {0x08u, 0x80u}, - {0x09u, 0x04u}, - {0x56u, 0x02u}, - {0x58u, 0x40u}, - {0x5Cu, 0x01u}, - {0x64u, 0x08u}, - {0x80u, 0xA0u}, - {0x81u, 0x04u}, - {0x8Au, 0x02u}, - {0x92u, 0x02u}, - {0x94u, 0x04u}, + {0x08u, 0x84u}, + {0x56u, 0x22u}, + {0x5Bu, 0x04u}, + {0x60u, 0x10u}, + {0x85u, 0x01u}, + {0x86u, 0x02u}, + {0x8Du, 0x04u}, + {0x98u, 0x08u}, + {0x99u, 0x08u}, {0x9Au, 0x08u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x20u}, - {0x9Eu, 0x20u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x04u}, + {0xA1u, 0x20u}, + {0xA6u, 0x20u}, + {0xB6u, 0x02u}, {0xC0u, 0x0Au}, {0xC2u, 0x0Au}, - {0xD4u, 0x01u}, - {0xD6u, 0x05u}, - {0xD8u, 0x01u}, - {0xE6u, 0x04u}, - {0x8Bu, 0x40u}, - {0x8Eu, 0x20u}, - {0x94u, 0x04u}, + {0xD4u, 0x02u}, + {0xD6u, 0x06u}, + {0xD8u, 0x02u}, + {0xE0u, 0x08u}, + {0xECu, 0x08u}, + {0x54u, 0x20u}, + {0x87u, 0x04u}, + {0x95u, 0x02u}, + {0x98u, 0x04u}, + {0x99u, 0x08u}, {0x9Au, 0x08u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x40u}, - {0x9Eu, 0x20u}, - {0xA0u, 0x04u}, - {0xA8u, 0x01u}, - {0xACu, 0x08u}, - {0xAEu, 0x01u}, - {0xB2u, 0x02u}, - {0xE4u, 0x02u}, - {0xE6u, 0x01u}, - {0xE8u, 0x01u}, - {0x0Bu, 0x81u}, - {0x0Fu, 0x22u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0x02u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x20u}, + {0xA1u, 0x20u}, + {0xA2u, 0x02u}, + {0xA6u, 0x20u}, + {0xA8u, 0x10u}, + {0xACu, 0x28u}, + {0xB0u, 0x81u}, + {0xB2u, 0x20u}, + {0xD4u, 0x02u}, + {0xEAu, 0x05u}, + {0xECu, 0x01u}, + {0x0Bu, 0x84u}, + {0x0Du, 0x01u}, + {0x0Fu, 0x02u}, + {0x86u, 0x08u}, + {0x87u, 0x40u}, + {0x8Au, 0x02u}, + {0x95u, 0x02u}, + {0x97u, 0x04u}, + {0x98u, 0x04u}, + {0x99u, 0x08u}, + {0x9Au, 0x08u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0x02u}, + {0x9Fu, 0x04u}, + {0xA2u, 0x02u}, + {0xB5u, 0x20u}, + {0xB6u, 0x20u}, + {0xC2u, 0x0Fu}, + {0xE6u, 0x04u}, + {0xE8u, 0x08u}, + {0xEEu, 0x02u}, + {0x02u, 0x04u}, + {0x80u, 0x02u}, {0x8Cu, 0x04u}, {0x94u, 0x04u}, - {0x97u, 0x81u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x40u}, - {0xAAu, 0x08u}, - {0xABu, 0x01u}, - {0xACu, 0x04u}, - {0xC2u, 0x0Fu}, - {0xE4u, 0x02u}, - {0x02u, 0x04u}, - {0x84u, 0x01u}, - {0x89u, 0x02u}, - {0x8Cu, 0x08u}, - {0x8Eu, 0x01u}, {0x9Eu, 0x04u}, - {0xA4u, 0x01u}, - {0xA8u, 0x20u}, + {0xAAu, 0x04u}, + {0xACu, 0x40u}, {0xAFu, 0x80u}, - {0xB6u, 0x01u}, {0xC0u, 0x40u}, - {0xE6u, 0x10u}, - {0xEEu, 0x30u}, - {0x03u, 0x20u}, - {0x51u, 0x20u}, - {0x55u, 0x08u}, - {0x58u, 0x08u}, - {0x5Fu, 0x08u}, - {0x61u, 0x02u}, - {0x65u, 0x02u}, - {0x7Au, 0x01u}, - {0x85u, 0x20u}, - {0x87u, 0x20u}, - {0x89u, 0x02u}, - {0x98u, 0x08u}, - {0x99u, 0x02u}, - {0x9Bu, 0x08u}, - {0xA1u, 0x08u}, - {0xA2u, 0x01u}, - {0xA9u, 0x08u}, - {0xB7u, 0x08u}, + {0xE2u, 0x20u}, + {0xE8u, 0x80u}, + {0xEAu, 0x40u}, + {0xEEu, 0x10u}, + {0x01u, 0x02u}, + {0x50u, 0x20u}, + {0x54u, 0x02u}, + {0x5Bu, 0x02u}, + {0x66u, 0x02u}, + {0x70u, 0x04u}, + {0x80u, 0x20u}, + {0x85u, 0x02u}, + {0x8Au, 0x02u}, + {0x8Bu, 0x02u}, + {0x8Cu, 0x04u}, + {0xA0u, 0x02u}, {0xC0u, 0x10u}, - {0xD4u, 0x60u}, - {0xD6u, 0xC0u}, - {0xD8u, 0xC0u}, + {0xD4u, 0x20u}, + {0xD6u, 0x60u}, + {0xD8u, 0x80u}, {0xDCu, 0x80u}, - {0xE2u, 0x10u}, + {0xE2u, 0x80u}, {0xE4u, 0x10u}, - {0xEAu, 0x80u}, - {0x74u, 0x08u}, - {0x88u, 0x08u}, - {0x90u, 0x02u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x40u}, + {0x83u, 0x04u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0x02u}, + {0x9Fu, 0x04u}, + {0xACu, 0x04u}, {0xAFu, 0x01u}, - {0xB4u, 0x01u}, - {0xB7u, 0x10u}, - {0xDEu, 0x04u}, - {0xE4u, 0x04u}, - {0xE8u, 0x02u}, - {0xEAu, 0x08u}, - {0x70u, 0x01u}, - {0x90u, 0x02u}, - {0xB0u, 0x40u}, - {0xB7u, 0x10u}, - {0xDCu, 0x01u}, - {0xE8u, 0x01u}, - {0xEEu, 0x02u}, - {0x10u, 0x03u}, + {0xB1u, 0x08u}, + {0xEAu, 0x01u}, + {0xABu, 0x02u}, + {0xB0u, 0x02u}, + {0xE8u, 0x04u}, + {0x10u, 0x07u}, {0x11u, 0x01u}, {0x1Au, 0x03u}, - {0x1Cu, 0x01u}, + {0x1Cu, 0x04u}, {0x1Du, 0x01u}, {0x00u, 0xFFu}, {0x01u, 0xBFu}, @@ -2416,32 +2443,31 @@ void cyfitter_cfg(void) /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT5_DR), 16u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1024u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P2_U1_BASE), 2944u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; - /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */ - static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = { - 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x40u, 0x60u, 0x00u, 0x00u, 0x88u, 0xFFu, 0x21u, 0x90u, 0x01u, 0x40u, 0x00u, - 0x00u, 0x01u, 0x9Fu, 0x00u, 0x7Fu, 0xA2u, 0x80u, 0x08u, 0xC0u, 0x04u, 0x04u, 0x00u, 0x1Fu, 0x87u, 0x20u, 0x18u, - 0xC0u, 0x40u, 0x02u, 0x00u, 0xC0u, 0x01u, 0x01u, 0x00u, 0xC0u, 0x01u, 0x08u, 0x00u, 0x80u, 0x10u, 0x00u, 0x00u, - 0xFFu, 0x00u, 0x00u, 0x3Fu, 0x00u, 0x40u, 0x00u, 0x80u, 0x80u, 0x28u, 0x00u, 0x00u, 0x00u, 0x00u, 0x41u, 0x44u, - 0x63u, 0x04u, 0x10u, 0x00u, 0x05u, 0xCEu, 0xDBu, 0x0Fu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, + /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { + 0x77u, 0x80u, 0x08u, 0x00u, 0x39u, 0x00u, 0x06u, 0x60u, 0x04u, 0xC0u, 0x20u, 0x08u, 0xC6u, 0x00u, 0x00u, 0x9Fu, + 0x42u, 0x90u, 0x00u, 0x40u, 0x00u, 0x1Fu, 0x00u, 0x20u, 0x01u, 0xC0u, 0x5Eu, 0x04u, 0xC6u, 0xC0u, 0x00u, 0x02u, + 0x00u, 0xC0u, 0x00u, 0x01u, 0xC2u, 0x00u, 0x04u, 0xFFu, 0x80u, 0x7Fu, 0x46u, 0x80u, 0x46u, 0x00u, 0x80u, 0x00u, + 0x80u, 0xFFu, 0x0Fu, 0x00u, 0x70u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x30u, 0x00u, 0x00u, 0x00u, 0x01u, 0x01u, + 0x32u, 0x06u, 0x40u, 0x00u, 0x05u, 0xDEu, 0xFBu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x01u, 0x11u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x01u, 0x07u, 0x01u, 0x05u, 0x01u, 0x05u, 0x01u}; + 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x05u, 0x01u, 0x07u, 0x01u, 0x04u, 0x01u, 0x04u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ - {(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 043d4f7..e1a9a82 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -424,34 +424,34 @@ .set NOR_SO__SLW, CYREG_PRT15_SLW /* SDCard */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -459,13 +459,9 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB04_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB04_ST .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 @@ -483,12 +479,14 @@ .set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 .set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 .set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 +.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 .set SDCard_BSPIM_TxStsReg__2__POS, 2 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 @@ -496,9 +494,9 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB06_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB06_ST +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST /* SD_SCK */ .set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE1 @@ -534,30 +532,6 @@ .set SD_SCK__SHIFT, 1 .set SD_SCK__SLW, CYREG_PRT3_SLW -/* NOR_CTL */ -.set NOR_CTL_Sync_ctrl_reg__0__MASK, 0x01 -.set NOR_CTL_Sync_ctrl_reg__0__POS, 0 -.set NOR_CTL_Sync_ctrl_reg__1__MASK, 0x02 -.set NOR_CTL_Sync_ctrl_reg__1__POS, 1 -.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL -.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL -.set NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL -.set NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL -.set NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK -.set NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK -.set NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK -.set NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK -.set NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set NOR_CTL_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB06_CTL -.set NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL -.set NOR_CTL_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB06_CTL -.set NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL -.set NOR_CTL_Sync_ctrl_reg__MASK, 0x03 -.set NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set NOR_CTL_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB06_MSK - /* NOR_SCK */ .set NOR_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE7 .set NOR_SCK__0__MASK, 0x80 @@ -593,34 +567,34 @@ .set NOR_SCK__SLW, CYREG_PRT3_SLW /* NOR_SPI */ -.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK -.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK -.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK -.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK -.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL -.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB08_CTL -.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL -.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB08_CTL -.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL -.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB08_MSK -.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST -.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB08_MSK -.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB08_ST -.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL -.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK +.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL +.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL +.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL +.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL +.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK +.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST +.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK +.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST +.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST .set NOR_SPI_BSPIM_RxStsReg__4__MASK, 0x10 .set NOR_SPI_BSPIM_RxStsReg__4__POS, 4 .set NOR_SPI_BSPIM_RxStsReg__5__MASK, 0x20 @@ -628,32 +602,34 @@ .set NOR_SPI_BSPIM_RxStsReg__6__MASK, 0x40 .set NOR_SPI_BSPIM_RxStsReg__6__POS, 6 .set NOR_SPI_BSPIM_RxStsReg__MASK, 0x70 -.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK -.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL -.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0 -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0 -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0 -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0 -.set NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0 -.set NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0 -.set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1 +.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK +.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL .set NOR_SPI_BSPIM_TxStsReg__0__MASK, 0x01 .set NOR_SPI_BSPIM_TxStsReg__0__POS, 0 .set NOR_SPI_BSPIM_TxStsReg__1__MASK, 0x02 .set NOR_SPI_BSPIM_TxStsReg__1__POS, 1 -.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST +.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST .set NOR_SPI_BSPIM_TxStsReg__2__MASK, 0x04 .set NOR_SPI_BSPIM_TxStsReg__2__POS, 2 .set NOR_SPI_BSPIM_TxStsReg__3__MASK, 0x08 @@ -661,9 +637,9 @@ .set NOR_SPI_BSPIM_TxStsReg__4__MASK, 0x10 .set NOR_SPI_BSPIM_TxStsReg__4__POS, 4 .set NOR_SPI_BSPIM_TxStsReg__MASK, 0x1F -.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK -.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST +.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK +.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST /* SCSI_In */ .set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1 @@ -1784,15 +1760,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08 @@ -1805,35 +1781,35 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB09_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB09_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB09_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG .set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX .set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE @@ -2843,58 +2819,58 @@ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK /* SCSI_Glitch_Ctl */ .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL .set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB08_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB08_ST /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 5442ef3..6f16a1b 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -423,34 +423,34 @@ NOR_SO__SHIFT EQU 2 NOR_SO__SLW EQU CYREG_PRT15_SLW /* SDCard */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -458,13 +458,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -482,12 +478,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -495,9 +493,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST /* SD_SCK */ SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 @@ -533,30 +531,6 @@ SD_SCK__PS EQU CYREG_PRT3_PS SD_SCK__SHIFT EQU 1 SD_SCK__SLW EQU CYREG_PRT3_SLW -/* NOR_CTL */ -NOR_CTL_Sync_ctrl_reg__0__MASK EQU 0x01 -NOR_CTL_Sync_ctrl_reg__0__POS EQU 0 -NOR_CTL_Sync_ctrl_reg__1__MASK EQU 0x02 -NOR_CTL_Sync_ctrl_reg__1__POS EQU 1 -NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -NOR_CTL_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB06_CTL -NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL -NOR_CTL_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB06_CTL -NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL -NOR_CTL_Sync_ctrl_reg__MASK EQU 0x03 -NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -NOR_CTL_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB06_MSK - /* NOR_SCK */ NOR_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE7 NOR_SCK__0__MASK EQU 0x80 @@ -592,34 +566,34 @@ NOR_SCK__SHIFT EQU 7 NOR_SCK__SLW EQU CYREG_PRT3_SLW /* NOR_SPI */ -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL -NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST -NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK -NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL +NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK +NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -627,32 +601,34 @@ NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5 NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40 NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6 NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70 -NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK -NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 -NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 -NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0 -NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1 -NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 -NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0 -NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1 -NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 -NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0 -NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1 +NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0 +NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0 +NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0 +NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01 NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0 NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02 NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1 -NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04 NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2 NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -660,9 +636,9 @@ NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3 NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F -NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST /* SCSI_In */ SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1 @@ -1783,15 +1759,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1804,35 +1780,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -2842,58 +2818,58 @@ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK /* SCSI_Glitch_Ctl */ SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 5ddb795..a8e4fa9 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -423,34 +423,34 @@ NOR_SO__SHIFT EQU 2 NOR_SO__SLW EQU CYREG_PRT15_SLW ; SDCard -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -458,13 +458,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -482,12 +478,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -495,9 +493,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST ; SD_SCK SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 @@ -533,30 +531,6 @@ SD_SCK__PS EQU CYREG_PRT3_PS SD_SCK__SHIFT EQU 1 SD_SCK__SLW EQU CYREG_PRT3_SLW -; NOR_CTL -NOR_CTL_Sync_ctrl_reg__0__MASK EQU 0x01 -NOR_CTL_Sync_ctrl_reg__0__POS EQU 0 -NOR_CTL_Sync_ctrl_reg__1__MASK EQU 0x02 -NOR_CTL_Sync_ctrl_reg__1__POS EQU 1 -NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -NOR_CTL_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB06_CTL -NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL -NOR_CTL_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB06_CTL -NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL -NOR_CTL_Sync_ctrl_reg__MASK EQU 0x03 -NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -NOR_CTL_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB06_MSK - ; NOR_SCK NOR_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE7 NOR_SCK__0__MASK EQU 0x80 @@ -592,34 +566,34 @@ NOR_SCK__SHIFT EQU 7 NOR_SCK__SLW EQU CYREG_PRT3_SLW ; NOR_SPI -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL -NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST -NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK -NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL +NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK +NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -627,32 +601,34 @@ NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5 NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40 NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6 NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70 -NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK -NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 -NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 -NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0 -NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1 -NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 -NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0 -NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1 -NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 -NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0 -NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1 +NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0 +NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0 +NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0 +NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01 NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0 NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02 NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1 -NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04 NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2 NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -660,9 +636,9 @@ NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3 NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F -NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST ; SCSI_In SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1 @@ -1783,15 +1759,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1804,35 +1780,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -2842,58 +2818,58 @@ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK ; SCSI_Glitch_Ctl SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index fde38ec..5516993 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -81,7 +81,6 @@ #include "nNOR_HOLD.h" #include "NOR_SI_aliases.h" #include "NOR_SI.h" -#include "NOR_CTL.h" #include "nNOR_CS_aliases.h" #include "nNOR_CS.h" #include "nNOR_WP_aliases.h" diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx index d68d1f5..f3c0f70 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -5,16 +5,16 @@