mirror of
https://github.com/fhgwright/SCSI2SD.git
synced 2025-04-10 01:37:07 +00:00
SWV tracing for diagnosing hangs.
Patch provided by James Laird-Wah <james@laird-wah.net>
This commit is contained in:
parent
35d88b4d1f
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@ -24,6 +24,7 @@
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#include "disk.h"
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#include "led.h"
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#include "time.h"
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#include "trace.h"
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const char* Notice = "Copyright (C) 2014 Michael McMaster <michael@codesrc.com>";
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@ -33,6 +34,7 @@ int main()
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{
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timeInit();
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ledInit();
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traceInit();
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// Enable global interrupts.
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// Needed for RST and ATN interrupt handlers.
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@ -21,6 +21,7 @@
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#include "scsi.h"
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#include "scsiPhy.h"
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#include "bits.h"
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#include "trace.h"
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#define scsiTarget_AUX_CTL (* (reg8 *) scsiTarget_datapath__DP_AUX_CTL_REG)
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@ -50,18 +51,21 @@ volatile uint8_t scsiTxDMAComplete;
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CY_ISR_PROTO(scsiRxCompleteISR);
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CY_ISR(scsiRxCompleteISR)
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{
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traceIrq(trace_scsiRxCompleteISR);
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scsiRxDMAComplete = 1;
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}
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CY_ISR_PROTO(scsiTxCompleteISR);
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CY_ISR(scsiTxCompleteISR)
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{
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traceIrq(trace_scsiTxCompleteISR);
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scsiTxDMAComplete = 1;
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}
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CY_ISR_PROTO(scsiResetISR);
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CY_ISR(scsiResetISR)
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{
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traceIrq(trace_scsiResetISR);
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scsiDev.resetFlag = 1;
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}
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@ -82,13 +86,16 @@ scsiReadDBxPins()
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uint8_t
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scsiReadByte(void)
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{
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trace(trace_spinPhyTxFifo);
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while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}
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scsiPhyTx(0);
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trace(trace_spinPhyRxFifo);
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while (scsiPhyRxFifoEmpty() && likely(!scsiDev.resetFlag)) {}
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uint8_t val = scsiPhyRx();
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scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
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trace(trace_spinTxComplete);
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while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}
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return val;
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@ -124,6 +131,7 @@ doRxSingleDMA(uint8* data, uint32 count)
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{
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// Prepare DMA transfer
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dmaInProgress = 1;
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trace(trace_doRxSingleDMA);
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CyDmaTdSetConfiguration(
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scsiDmaTxTd[0],
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@ -184,6 +192,7 @@ scsiReadDMAPoll()
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{
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// Wait until our scsi signals are consistent. This should only be
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// a few cycles.
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trace(trace_spinTxComplete);
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while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}
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if (likely(dmaSentCount == dmaTotalCount))
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@ -219,12 +228,13 @@ scsiRead(uint8_t* data, uint32_t count)
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else
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{
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scsiReadDMA(data, count);
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// Wait for the next DMA interrupt (or the 1ms systick)
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// It's beneficial to halt the processor to
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// give the DMA controller more memory bandwidth to work with.
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__WFI();
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trace(trace_spinReadDMAPoll);
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while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag)) {};
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}
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}
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@ -232,9 +242,11 @@ scsiRead(uint8_t* data, uint32_t count)
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void
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scsiWriteByte(uint8 value)
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{
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trace(trace_spinPhyTxFifo);
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while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}
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scsiPhyTx(value);
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trace(trace_spinTxComplete);
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while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}
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scsiPhyRxFifoClear();
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}
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@ -253,6 +265,7 @@ scsiWritePIO(const uint8_t* data, uint32_t count)
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}
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}
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trace(trace_spinTxComplete);
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while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}
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scsiPhyRxFifoClear();
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}
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@ -262,6 +275,7 @@ doTxSingleDMA(const uint8* data, uint32 count)
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{
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// Prepare DMA transfer
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dmaInProgress = 1;
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trace(trace_doTxSingleDMA);
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CyDmaTdSetConfiguration(
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scsiDmaTxTd[0],
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@ -306,6 +320,7 @@ scsiWriteDMAPoll()
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{
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// Wait until our scsi signals are consistent. This should only be
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// a few cycles.
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trace(trace_spinTxComplete);
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while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}
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if (likely(dmaSentCount == dmaTotalCount))
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@ -341,12 +356,13 @@ scsiWrite(const uint8_t* data, uint32_t count)
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else
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{
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scsiWriteDMA(data, count);
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// Wait for the next DMA interrupt (or the 1ms systick)
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// It's beneficial to halt the processor to
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// give the DMA controller more memory bandwidth to work with.
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__WFI();
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trace(trace_spinWriteDMAPoll);
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while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag)) {};
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}
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}
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@ -370,6 +386,7 @@ void scsiEnterPhase(int phase)
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void scsiPhyReset()
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{
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trace(trace_scsiPhyReset);
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if (dmaInProgress)
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{
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dmaInProgress = 0;
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@ -378,6 +395,7 @@ void scsiPhyReset()
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dmaTotalCount = 0;
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CyDmaChSetRequest(scsiDmaTxChan, CY_DMA_CPU_TERM_CHAIN);
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CyDmaChSetRequest(scsiDmaRxChan, CY_DMA_CPU_TERM_CHAIN);
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trace(trace_spinDMAReset);
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while (!(scsiTxDMAComplete && scsiRxDMAComplete)) {}
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CyDmaChDisable(scsiDmaTxChan);
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@ -24,6 +24,7 @@
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#include "sd.h"
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#include "led.h"
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#include "time.h"
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#include "trace.h"
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#include "scsiPhy.h"
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@ -86,7 +87,9 @@ static uint8 sdCrc7(uint8* chr, uint8 cnt, uint8 crc)
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static uint8_t sdSpiByte(uint8_t value)
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{
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SDCard_WriteTxData(value);
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trace(trace_spinSpiByte);
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while (!(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)) {}
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trace(trace_sdSpiByte);
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return SDCard_ReadRxData();
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}
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@ -145,10 +148,12 @@ static uint16_t sdDoCommand(
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// reads.
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if (waitWhileBusy)
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{
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trace(trace_spinSDRxFIFO);
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while (!(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)) {}
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int busy = SDCard_ReadRxData() != 0xFF;
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if (unlikely(busy))
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{
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trace(trace_spinSDBusy);
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while (sdSpiByte(0xFF) != 0xFF) {}
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}
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}
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@ -164,6 +169,7 @@ static uint16_t sdDoCommand(
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CyDmaChEnable(sdDMARxChan, 1);
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CyDmaChEnable(sdDMATxChan, 1);
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trace(trace_spinSDDMA);
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while (!(sdTxDMAComplete && sdRxDMAComplete)) { __WFI(); }
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uint16_t response = discardBuffer;
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@ -177,6 +183,8 @@ static uint16_t sdDoCommand(
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}
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uint32_t start = getTime_ms();
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trace(trace_spinSDBusy);
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while ((response & 0x80) && likely(elapsedTime_ms(start) <= 200))
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{
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response = sdSpiByte(0xFF);
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@ -246,6 +254,7 @@ dmaReadSector(uint8_t* outputBuffer)
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// Don't wait more than 200ms. The standard recommends 100ms.
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uint32_t start = getTime_ms();
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uint8_t token = sdSpiByte(0xFF);
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trace(trace_spinSDBusy);
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while (token != 0xFE && likely(elapsedTime_ms(start) <= 200))
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{
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if (unlikely(token && ((token & 0xE0) == 0)))
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@ -367,6 +376,7 @@ void sdCompleteRead()
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// Not much choice but to wait until we've completed the transfer.
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// Cancelling the transfer can't be done as we have no way to reset
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// the SD card.
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trace(trace_spinSDCompleteRead);
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while (!sdReadSectorDMAPoll()) { /* spin */ }
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}
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@ -536,6 +546,7 @@ void sdCompleteWrite()
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// Not much choice but to wait until we've completed the transfer.
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// Cancelling the transfer can't be done as we have no way to reset
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// the SD card.
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trace(trace_spinSDCompleteWrite);
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while (!sdWriteSectorDMAPoll(1)) { /* spin */ }
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}
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51
tools/trace2name.pl
Normal file
51
tools/trace2name.pl
Normal file
@ -0,0 +1,51 @@
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# Author James Laird-Wah <james@laird-wah.net>
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# This is free and unencumbered software released into the public domain.
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#
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# Anyone is free to copy, modify, publish, use, compile, sell, or
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# distribute this software, either in source code form or as a compiled
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# binary, for any purpose, commercial or non-commercial, and by any
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# means.
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#
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# In jurisdictions that recognize copyright laws, the author or authors
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# of this software dedicate any and all copyright interest in the
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# software to the public domain. We make this dedication for the benefit
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# of the public at large and to the detriment of our heirs and
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# successors. We intend this dedication to be an overt act of
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# relinquishment in perpetuity of all present and future rights to this
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# software under copyright law.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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# IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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# OTHER DEALINGS IN THE SOFTWARE.
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# For more information, please refer to <http://unlicense.org/>
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open HDR, '<trace.h';
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$next = 0;
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$enum = 0;
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for (<HDR>) {
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chomp;
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/^enum trace_event/ || $enum or next;
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$enum++;
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/}/ && break;
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/trace_(\S+)(\s*=\s*(\S+))?\s*,\s*$/ or next;
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($name, $valmatch, $val) = ($1, $2, $3);
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$next = hex $val if defined $val;
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$names{$next} = $name;
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$next++;
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}
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while (!eof STDIN) {
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$ch = ord getc;
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if ($ch==1 || $ch==9) {
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$data = ord getc;
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print "ISR: " if $ch==9;
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$name = $names{$data} // sprintf "unk: 0x%X", $data;
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print $names{$data}, "\n"
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} else {
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print "<dropped>\n";
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}
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}
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