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SCSI2SD
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Added V5.1 support, XEBEC support, and fixed some bugs.

This commit is contained in:
Michael McMaster 2018-04-15 22:10:01 +10:00
parent 0b49f5de9c
commit 258da24a7a
338 changed files with 254348 additions and 4467 deletions
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10
CHANGELOG
View File

@ -1,3 +1,13 @@
2018XXXX 4.8
- Fix Unit Serial Number inquiry page to use return configured serial number
- Apple mode pages now only sent when in Apple mode.
- Added quirks selection to scsi2sd-util. Apple users should manually fix
their settings to use the Apple mode.
- Added specific support for XEBEC controllers.
- Added a speed selection to scsi2sd-util. Users with older SASI or SCSI1
controllers should select the lower speed for stability.
- Support for v5.1 hardware boards.
20170501 4.7.1
- Fix scsi2sd-util size and sector-size inputs
- Fix crash when configured scsi disk starting sector is less than

3
software/SCSI2SD/src/bits.c
View File

@ -14,8 +14,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "bits.h"
@ -49,4 +47,3 @@ uint8 countBits(uint8 value)
return i;
}
#pragma GCC pop_options

3
software/SCSI2SD/src/cdrom.c
View File

@ -14,8 +14,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
@ -323,4 +321,3 @@ int scsiCDRomCommand()
return commandHandled;
}
#pragma GCC pop_options

17
software/SCSI2SD/src/config.c
View File

@ -14,8 +14,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "device.h"
#include "config.h"
@ -33,7 +31,7 @@
#include <string.h>
static const uint16_t FIRMWARE_VERSION = 0x0471;
static const uint16_t FIRMWARE_VERSION = 0x0480;
// 1 flash row
static const uint8_t DEFAULT_CONFIG[256] =
@ -142,6 +140,17 @@ writeFlashCommand(const uint8_t* cmd, size_t cmdSize)
uint8_t flashArray = cmd[257];
uint8_t flashRow = cmd[258];
// Be very careful not to overwrite the bootloader or other\r
// code. Bootloader updates no longer supported. Use v5.1 board
// instead.
if ((flashArray != SCSI_CONFIG_ARRAY) ||
(flashRow < SCSI_CONFIG_4_ROW) ||
(flashRow >= SCSI_CONFIG_3_ROW + SCSI_CONFIG_ROWS))
{
uint8_t response[] = { CONFIG_STATUS_ERR };
hidPacket_send(response, sizeof(response));
}
CySetTemp();
int status = CyWriteRowData(flashArray, flashRow, cmd + 1);
@ -452,5 +461,3 @@ const TargetConfig* getConfigById(int scsiId)
return NULL;
}
#pragma GCC pop_options

4
software/SCSI2SD/src/diagnostic.c
View File

@ -14,9 +14,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
#include "diagnostic.h"
@ -218,4 +215,3 @@ void scsiWriteBuffer()
}
#pragma GCC pop_options

5
software/SCSI2SD/src/disk.c
View File

@ -15,9 +15,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
#include "scsiPhy.h"
@ -837,4 +834,4 @@ void scsiDiskInit()
#endif
}
#pragma GCC pop_options

5
software/SCSI2SD/src/inquiry.c
View File

@ -14,9 +14,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
#include "config.h"
@ -181,6 +178,7 @@ void scsiInquiry()
{
memcpy(scsiDev.data, UnitSerialNumber, sizeof(UnitSerialNumber));
scsiDev.dataLen = sizeof(UnitSerialNumber);
const TargetConfig* config = scsiDev.target->cfg;
memcpy(&scsiDev.data[4], config->serial, sizeof(config->serial));
scsiDev.phase = DATA_IN;
}
@ -265,4 +263,3 @@ void scsiInquiry()
}
}
#pragma GCC pop_options

5
software/SCSI2SD/src/led.c
View File

@ -14,8 +14,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "led.h"
@ -70,11 +68,10 @@ void ledOn()
void ledOff()
{
LED1_Write(1);
LED1_Write(0xff);
#ifdef HAVE_EXTLED
EXTLED_Write(0);
#endif
}
#pragma GCC pop_options

6
software/SCSI2SD/src/main.c
View File

@ -14,9 +14,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
#include "scsiPhy.h"
@ -26,7 +23,7 @@
#include "time.h"
#include "trace.h"
const char* Notice = "Copyright (C) 2015 Michael McMaster <michael@codesrc.com>";
const char* Notice = "Copyright (C) 2015-2018 Michael McMaster <michael@codesrc.com>";
int main()
{
@ -104,4 +101,3 @@ int main()
return 0;
}
#pragma GCC pop_options

3
software/SCSI2SD/src/mo.c Normal file → Executable file
View File

@ -14,8 +14,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
@ -40,4 +38,3 @@ int scsiMOCommand()
return commandHandled;
}
#pragma GCC pop_options

8
software/SCSI2SD/src/mode.c
View File

@ -15,9 +15,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
#include "mode.h"
@ -476,8 +473,7 @@ static void doModeSense(
}
if ((
(scsiDev.target->cfg->quirks == CONFIG_QUIRKS_APPLE) ||
(idx + sizeof(AppleVendorPage) <= allocLength)
(scsiDev.target->cfg->quirks == CONFIG_QUIRKS_APPLE)
) &&
(pageCode == 0x30 || pageCode == 0x3F))
{
@ -688,5 +684,3 @@ int scsiModeCommand()
return commandHandled;
}
#pragma GCC pop_options

89
software/SCSI2SD/src/scsi.c
View File

@ -14,8 +14,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
@ -145,11 +143,13 @@ void process_Status()
// OMTI non-standard LINK control
if (control & 0x01)
{
scsiDev.phase = COMMAND; return;
scsiDev.phase = COMMAND;
return;
}
}
if ((scsiDev.status == GOOD) && (control & 0x01))
if ((scsiDev.status == GOOD) && (control & 0x01) &&
scsiDev.target->cfg->quirks != CONFIG_QUIRKS_XEBEC)
{
// Linked command.
scsiDev.status = INTERMEDIATE;
@ -168,12 +168,31 @@ void process_Status()
}
if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_OMTI)
if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_XEBEC)
{
// More non-standardness. Expects 2 status bytes (really status + msg)
// 00 d 000 err 0
// d == disk number
// ERR = 1 if error.
if (scsiDev.status == GOOD)
{
scsiWriteByte(scsiDev.cdb[1] & 0x20);
}
else
{
scsiWriteByte((scsiDev.cdb[1] & 0x20) | 0x2);
}
CyDelayUs(10); // Seems to need a delay before changing phase bits.
}
else if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_OMTI)
{
scsiDev.status |= (scsiDev.target->targetId & 0x03) << 5;
scsiWriteByte(scsiDev.status);
}
else
{
scsiWriteByte(scsiDev.status);
}
scsiWriteByte(scsiDev.status);
scsiDev.lastStatus = scsiDev.status;
scsiDev.lastSense = scsiDev.target->sense.code;
@ -279,7 +298,14 @@ static void process_Command()
// Prefer LUN's set by IDENTIFY messages for newer hosts.
if (scsiDev.lun < 0)
{
scsiDev.lun = scsiDev.cdb[1] >> 5;
if (command == 0xE0 || command == 0xE4) // XEBEC s1410
{
scsiDev.lun = 0;
}
else
{
scsiDev.lun = scsiDev.cdb[1] >> 5;
}
}
// For Philips P2000C with Xebec S1410 SASI/MFM adapter
@ -319,7 +345,9 @@ static void process_Command()
scsiDev.target->sense.asc = SCSI_PARITY_ERROR;
enter_Status(CHECK_CONDITION);
}
else if ((control & 0x02) && ((control & 0x01) == 0))
else if ((control & 0x02) && ((control & 0x01) == 0) &&
// used for head step options on xebec.
likely(scsiDev.target->cfg->quirks != CONFIG_QUIRKS_XEBEC))
{
// FLAG set without LINK flag.
scsiDev.target->sense.code = ILLEGAL_REQUEST;
@ -335,6 +363,26 @@ static void process_Command()
// REQUEST SENSE
uint32 allocLength = scsiDev.cdb[4];
if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_XEBEC)
{
// Completely non-standard
allocLength = 4;
if (scsiDev.target->sense.code == NO_SENSE)
scsiDev.data[0] = 0;
else if (scsiDev.target->sense.code == ILLEGAL_REQUEST)
scsiDev.data[0] = 0x20; // Illegal command
else if (scsiDev.target->sense.code == NOT_READY)
scsiDev.data[0] = 0x04; // Drive not ready
else
scsiDev.data[0] = 0x11; // Uncorrectable data error
scsiDev.data[1] = (scsiDev.cdb[1] & 0x20) | ((transfer.lba >> 16) & 0x1F);
scsiDev.data[2] = transfer.lba >> 8;
scsiDev.data[3] = transfer.lba;
}
else
{
// As specified by the SASI and SCSI1 standard.
// Newer initiators won't be specifying 0 anyway.
if (allocLength == 0) allocLength = 4;
@ -352,6 +400,7 @@ static void process_Command()
scsiDev.data[7] = 10; // additional length
scsiDev.data[12] = scsiDev.target->sense.asc >> 8;
scsiDev.data[13] = scsiDev.target->sense.asc;
}
// Silently truncate results. SCSI-2 spec 8.2.14.
enter_DataIn(allocLength);
@ -564,7 +613,11 @@ static void process_SelectionPhase()
// The Mac Plus boot-time (ie. rom code) selection abort time
// is < 1ms and must have no delay (standard suggests 250ms abort time)
// Most newer SCSI2 hosts don't care either way.
if (scsiDev.boardCfg.selectionDelay == 255) // auto
if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_XEBEC)
{
CyDelay(1); // Simply won't work if set to 0.
}
else if (scsiDev.boardCfg.selectionDelay == 255) // auto
{
if (scsiDev.compatMode < COMPAT_SCSI2)
{
@ -580,7 +633,11 @@ static void process_SelectionPhase()
int sel = (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL);
int bsy = SCSI_ReadFilt(SCSI_Filt_BSY);
#ifdef SCSI_In_IO
int io = SCSI_ReadPin(SCSI_In_IO);
#else
int io = 0;
#endif
// Only read these pins AFTER SEL and BSY - we don't want to catch them
// during a transition period.
@ -601,7 +658,9 @@ static void process_SelectionPhase()
}
sel &= (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL);
bsy |= SCSI_ReadFilt(SCSI_Filt_BSY);
#ifdef SCSI_In_IO
io |= SCSI_ReadPin(SCSI_In_IO);
#endif
if (!bsy && !io && sel &&
target &&
(goodParity || !(scsiDev.boardCfg.flags & CONFIG_ENABLE_PARITY) || !atnFlag) &&
@ -663,12 +722,19 @@ static void process_SelectionPhase()
}
// Wait until the end of the selection phase.
uint32_t selTimerBegin = getTime_ms();
while (likely(!scsiDev.resetFlag))
{
if (!SCSI_ReadFilt(SCSI_Filt_SEL))
{
break;
}
else if (elapsedTime_ms(selTimerBegin) >= 250)
{
SCSI_ClearPin(SCSI_Out_BSY);
scsiDev.resetFlag = 1;
break;
}
}
scsiDev.phase = COMMAND;
@ -677,7 +743,7 @@ static void process_SelectionPhase()
{
scsiDev.phase = BUS_BUSY;
}
scsiDev.selFlag = 0;
}
@ -1089,4 +1155,3 @@ int scsiReconnect()
return reconnected;
}
#pragma GCC pop_options

53
software/SCSI2SD/src/scsiPhy.c
View File

@ -14,9 +14,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
#include "scsiPhy.h"
@ -391,9 +388,8 @@ void scsiEnterPhase(int phase)
{
// ANSI INCITS 362-2002 SPI-3 10.7.1:
// Phase changes are not allowed while REQ or ACK is asserted.
while (likely(!scsiDev.resetFlag) &&
(SCSI_ReadPin(SCSI_In_REQ) || SCSI_ReadFilt(SCSI_Filt_ACK))
) {}
while (likely(!scsiDev.resetFlag) && SCSI_ReadFilt(SCSI_Filt_ACK))
{}
int newPhase = phase > 0 ? phase : 0;
if (newPhase != SCSI_CTL_PHASE_Read())
@ -403,7 +399,9 @@ void scsiEnterPhase(int phase)
if (scsiDev.compatMode < COMPAT_SCSI2)
{
CyDelayUs(100);
// XEBEC S1410 manual (old SASI controller) gives 10uSec delay
// between phase bits and REQ.
CyDelayUs(10);
}
}
}
@ -452,9 +450,13 @@ void scsiPhyReset()
SCSI_SetPin(SCSI_Out_RST);
SCSI_CTL_PHASE_Write(0);
#ifdef SCSI_Out_ATN
SCSI_ClearPin(SCSI_Out_ATN);
#endif
SCSI_ClearPin(SCSI_Out_BSY);
#ifdef SCSI_Out_ACK
SCSI_ClearPin(SCSI_Out_ACK);
#endif
SCSI_ClearPin(SCSI_Out_RST);
SCSI_ClearPin(SCSI_Out_SEL);
SCSI_ClearPin(SCSI_Out_REQ);
@ -512,8 +514,34 @@ void scsiPhyInit()
if (scsiDev.boardCfg.flags & CONFIG_DISABLE_GLITCH)
{
SCSI_Glitch_Ctl_Write(1);
// Reduce deskew time to 1. (deskew init + 0)
CY_SET_REG8(scsiTarget_datapath__D0_REG, 0);
}
if ((scsiDev.target->cfg->quirks == CONFIG_QUIRKS_XEBEC) ||
(scsiDev.boardCfg.scsiSpeed == CONFIG_SPEED_ASYNC_15))
{
// 125ns to 250ns deskew time = 3.125 clocks
// - 1 (valid during DESKEW INIT)
// = 2.125. Default is 1.
// Round down because it's going to be doubled anyway due to clock
// divider change below.
CY_SET_REG8(scsiTarget_datapath__D0_REG, 2);
// Half the SCSI clock as a way to extend the glitch filter.
// This also helps meet the 250ns delays between ACK and reading
// data, or release ack and reassert req.
// The register contains (divider - 1)
uint16_t clkDiv25MHz = SCSI_CLK_GetDividerRegister();
SCSI_CLK_SetDivider(((clkDiv25MHz + 1) * 2) - 1);
// Wait for the clock to settle.
CyDelayUs(1);
}
#ifdef TERM_EN_0
TERM_EN_Write((scsiDev.boardCfg.flags6 & S2S_CFG_ENABLE_TERMINATOR) ? 0 : 1);
#endif
}
// 1 = DBx error
@ -546,6 +574,7 @@ int scsiSelfTest()
SCSI_Out_Ctl_Write(0); // Write bits normally.
// TEST MSG, CD, IO
#ifdef SCSI_In_MSG
for (i = 0; i < 8; ++i)
{
SCSI_CTL_PHASE_Write(i);
@ -564,18 +593,19 @@ int scsiSelfTest()
result |= 16;
}
}
#endif
SCSI_CTL_PHASE_Write(0);
uint32_t signalsOut[] = { SCSI_Out_ATN, SCSI_Out_BSY, SCSI_Out_RST, SCSI_Out_SEL };
uint32_t signalsIn[] = { SCSI_Filt_ATN, SCSI_Filt_BSY, SCSI_Filt_RST, SCSI_Filt_SEL };
uint32_t signalsOut[] = { SCSI_Out_BSY, SCSI_Out_RST, SCSI_Out_SEL };
uint32_t signalsIn[] = { SCSI_Filt_BSY, SCSI_Filt_RST, SCSI_Filt_SEL };
for (i = 0; i < 4; ++i)
for (i = 0; i < 3; ++i)
{
SCSI_SetPin(signalsOut[i]);
scsiDeskewDelay();
int j;
for (j = 0; j < 4; ++j)
for (j = 0; j < 3; ++j)
{
if (i == j)
{
@ -598,4 +628,3 @@ int scsiSelfTest()
}
#pragma GCC pop_options

12
software/SCSI2SD/src/scsiPhy.h
View File

@ -37,11 +37,21 @@ typedef enum
#define scsiPhyTx(val) CY_SET_REG8(scsiTarget_datapath__F0_REG, (val))
#define scsiPhyRx() CY_GET_REG8(scsiTarget_datapath__F1_REG)
#ifdef TERM_EN_0
// V5.1 is active-low
#define SCSI_SetPin(pin) \
CyPins_ClearPin((pin));
#define SCSI_ClearPin(pin) \
CyPins_SetPin((pin));
#else
// <= V5.0 is active-high
#define SCSI_SetPin(pin) \
CyPins_SetPin((pin));
#define SCSI_ClearPin(pin) \
CyPins_ClearPin((pin));
CyPins_ClearPin((pin));
#endif
// Active low: we interpret a 0 as "true", and non-zero as "false"
#define SCSI_ReadPin(pin) \

3
software/SCSI2SD/src/sd.c
View File

@ -14,8 +14,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
@ -1018,4 +1016,3 @@ void sdCheckPresent()
firstCheck = 0;
}
#pragma GCC pop_options

4
software/SCSI2SD/src/tape.c Normal file → Executable file
View File

@ -14,8 +14,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "device.h"
#include "scsi.h"
@ -29,5 +27,3 @@ int scsiTapeCommand()
return 0;
}
#pragma GCC pop_options

3
software/SCSI2SD/src/time.c
View File

@ -14,8 +14,6 @@
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#pragma GCC push_options
#pragma GCC optimize("-flto")
#include "time.h"
#include "limits.h"
@ -70,4 +68,3 @@ uint32_t elapsedTime_ms(uint32_t since)
}
}
#pragma GCC pop_options

21
software/SCSI2SD/src/vendor.c
View File

@ -49,6 +49,27 @@ int scsiVendorCommand()
scsiDev.phase = DATA_OUT;
scsiDev.postDataOutHook = doAssignDiskParameters;
}
else if (command == 0x0C)
{
// Initialize Drive Characteristics
// XEBEC S1410 controller
// http://bitsavers.informatik.uni-stuttgart.de/pdf/xebec/104524C_S1410Man_Aug83.pdf
scsiDev.dataLen = 8;
scsiDev.phase = DATA_OUT;
}
else if (command == 0xE0)
{
// RAM Diagnostic
// XEBEC S1410 controller
// http://bitsavers.informatik.uni-stuttgart.de/pdf/xebec/104524C_S1410Man_Aug83.pdf
// Stub, return success
}
else if (command == 0xE4)
{
// Drive Diagnostic
// XEBEC S1410 controller
// Stub, return success
}
else
{
commandHandled = 0;

216
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
View File

@ -391,34 +391,34 @@
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
/* SDCard_BSPIM */
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@ -426,13 +426,13 @@
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK
#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL
#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK
#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL
#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
@ -450,12 +450,14 @@
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
@ -463,9 +465,9 @@
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
/* SD_SCK */
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2
@ -1945,15 +1947,15 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB08_09_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB08_09_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB08_09_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB08_09_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB08_09_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB08_09_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB08_09_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB08_09_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@ -1966,37 +1968,37 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB08_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB08_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB08_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB08_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB08_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB08_MSK
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
@ -2822,6 +2824,8 @@
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
@ -2829,9 +2833,13 @@
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB07_MSK
#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL
#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB07_ST
/* Debug_Timer_Interrupt */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -2952,8 +2960,8 @@
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@ -2961,9 +2969,9 @@
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
@ -2994,34 +3002,34 @@
/* SCSI_Glitch_Ctl */
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB07_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB07_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U

3291
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
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File diff suppressed because it is too large Load Diff

216
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
View File

@ -391,34 +391,34 @@
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
/* SDCard_BSPIM */
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@ -426,13 +426,13 @@
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK
.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL
.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK
.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB08_ST_CTL
.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB08_ST_CTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
@ -450,12 +450,14 @@
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
@ -463,9 +465,9 @@
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB05_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB05_ST
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
/* SD_SCK */
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2
@ -1945,15 +1947,15 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB08_09_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB08_09_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB08_09_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB08_09_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB08_09_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB08_09_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB08_09_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB08_09_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@ -1966,37 +1968,37 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB08_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB08_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB08_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB08_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB08_MSK
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
@ -2822,6 +2824,8 @@
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
@ -2829,9 +2833,13 @@
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB07_MSK
.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL
.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB07_ST
/* Debug_Timer_Interrupt */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -2952,8 +2960,8 @@
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@ -2961,9 +2969,9 @@
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB12_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB12_ST
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
@ -2994,34 +3002,34 @@
/* SCSI_Glitch_Ctl */
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB07_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB07_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000

216
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
View File

@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
/* SDCard_BSPIM */
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -426,13 +426,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -450,12 +450,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -463,9 +465,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
/* SD_SCK */
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@ -1945,15 +1947,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1966,37 +1968,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@ -2822,6 +2824,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2829,9 +2833,13 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST
/* Debug_Timer_Interrupt */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2952,8 +2960,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2961,9 +2969,9 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
@ -2994,34 +3002,34 @@ SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
/* SCSI_Glitch_Ctl */
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB07_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB07_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000

216
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
View File

@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
; SDCard_BSPIM
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -426,13 +426,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -450,12 +450,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -463,9 +465,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
; SD_SCK
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@ -1945,15 +1947,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1966,37 +1968,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@ -2822,6 +2824,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2829,9 +2833,13 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST
; Debug_Timer_Interrupt
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2952,8 +2960,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2961,9 +2969,9 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
@ -2994,34 +3002,34 @@ SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
; SCSI_Glitch_Ctl
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB07_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB07_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000

18
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx
View File

@ -66,7 +66,7 @@
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
</block>
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006579" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -76,15 +76,15 @@
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006477" bitWidth="8" desc="" hidden="false" />
</block>
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x4000646C" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x4000648C" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649C" bitWidth="8" desc="" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x40006462" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x40006482" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006492" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
@ -112,9 +112,9 @@
</register>
</block>
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006567" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006587" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006597" bitWidth="8" desc="" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006461" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006481" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006491" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
@ -1026,7 +1026,7 @@
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
</block>
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006578" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />

BIN
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit
View File

Binary file not shown.

10
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd
View File

@ -301,7 +301,7 @@
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
<baseAddress>0x40006579</baseAddress>
<baseAddress>0x40006478</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -322,7 +322,7 @@
<peripheral>
<name>SCSI_Glitch_Ctl</name>
<description>No description available</description>
<baseAddress>0x40006474</baseAddress>
<baseAddress>0x40006477</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -343,7 +343,7 @@
<peripheral>
<name>SCSI_Filtered</name>
<description>No description available</description>
<baseAddress>0x4000646C</baseAddress>
<baseAddress>0x40006462</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -498,7 +498,7 @@
<peripheral>
<name>SCSI_Parity_Error</name>
<description>No description available</description>
<baseAddress>0x40006567</baseAddress>
<baseAddress>0x40006461</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -2912,7 +2912,7 @@
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
<baseAddress>0x4000647B</baseAddress>
<baseAddress>0x40006578</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>

2
software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v
View File

@ -276,9 +276,7 @@ always @(posedge op_clk) begin
else
state <= STATE_RX;
REQReg <= 1'b0;
parityErrReg <= 1'b0;
data <= 8'b0;
if (IO == IO_READ) begin
parityErrReg <= ^genParity[2:0];
end

242
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
View File

@ -426,34 +426,34 @@
#define EXTLED__SLW CYREG_PRT0_SLW
/* SDCard_BSPIM */
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@ -461,9 +461,9 @@
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB04_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB04_ST
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
@ -485,8 +485,8 @@
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
@ -494,9 +494,9 @@
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB06_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB06_ST
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST
/* SD_SCK */
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2
@ -1906,15 +1906,15 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@ -1927,37 +1927,37 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
@ -2785,8 +2785,8 @@
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
@ -2794,9 +2794,9 @@
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB02_MSK
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB02_ST
/* Debug_Timer_Interrupt */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -2917,8 +2917,8 @@
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@ -2926,71 +2926,67 @@
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK
/* SCSI_Glitch_Ctl */
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB03_MSK
#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB03_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U

3228
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
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File diff suppressed because it is too large Load Diff

242
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
View File

@ -426,34 +426,34 @@
.set EXTLED__SLW, CYREG_PRT0_SLW
/* SDCard_BSPIM */
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@ -461,9 +461,9 @@
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB04_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB04_ST
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
@ -485,8 +485,8 @@
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
@ -494,9 +494,9 @@
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB06_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB06_ST
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
/* SD_SCK */
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2
@ -1906,15 +1906,15 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@ -1927,37 +1927,37 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
@ -2785,8 +2785,8 @@
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
@ -2794,9 +2794,9 @@
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB02_MSK
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB02_ST
/* Debug_Timer_Interrupt */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -2917,8 +2917,8 @@
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@ -2926,71 +2926,67 @@
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK
/* SCSI_Glitch_Ctl */
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB03_MSK
.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB03_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000

242
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
View File

@ -426,34 +426,34 @@ EXTLED__SHIFT EQU 0
EXTLED__SLW EQU CYREG_PRT0_SLW
/* SDCard_BSPIM */
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -461,9 +461,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -485,8 +485,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -494,9 +494,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
/* SD_SCK */
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@ -1906,15 +1906,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1927,37 +1927,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
@ -2785,8 +2785,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2794,9 +2794,9 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST
/* Debug_Timer_Interrupt */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2917,8 +2917,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2926,71 +2926,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK
/* SCSI_Glitch_Ctl */
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB03_MSK
SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB03_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000

242
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
View File

@ -426,34 +426,34 @@ EXTLED__SHIFT EQU 0
EXTLED__SLW EQU CYREG_PRT0_SLW
; SDCard_BSPIM
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -461,9 +461,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -485,8 +485,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -494,9 +494,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
; SD_SCK
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@ -1906,15 +1906,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1927,37 +1927,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
@ -2785,8 +2785,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2794,9 +2794,9 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST
; Debug_Timer_Interrupt
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2917,8 +2917,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2926,71 +2926,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK
; SCSI_Glitch_Ctl
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB03_MSK
SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB03_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000

20
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx
View File

@ -4,9 +4,9 @@
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006463" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006483" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006493" bitWidth="8" desc="" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
@ -42,9 +42,9 @@
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x4000648B" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
@ -76,7 +76,7 @@
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />
</block>
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -153,7 +153,7 @@
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006476" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -1018,10 +1018,10 @@
</block>
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />

BIN
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit
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Binary file not shown.

12
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd
View File

@ -9,7 +9,7 @@
<peripheral>
<name>SCSI_Parity_Error</name>
<description>No description available</description>
<baseAddress>0x40006463</baseAddress>
<baseAddress>0x40006465</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -164,7 +164,7 @@
<peripheral>
<name>SCSI_Filtered</name>
<description>No description available</description>
<baseAddress>0x40006468</baseAddress>
<baseAddress>0x4000646B</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -319,7 +319,7 @@
<peripheral>
<name>SCSI_Glitch_Ctl</name>
<description>No description available</description>
<baseAddress>0x4000647A</baseAddress>
<baseAddress>0x40006474</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -632,7 +632,7 @@
<peripheral>
<name>SCSI_CTL_PHASE</name>
<description>No description available</description>
<baseAddress>0x40006472</baseAddress>
<baseAddress>0x40006476</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -2891,7 +2891,7 @@
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
<baseAddress>0x40006473</baseAddress>
<baseAddress>0x4000647C</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -2912,7 +2912,7 @@
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
<baseAddress>0x4000647C</baseAddress>
<baseAddress>0x4000647E</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>

BIN
software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
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7
software/SCSI2SD/v5.1/SCSI2SD.cydsn/.gitignore vendored Normal file
View File

@ -0,0 +1,7 @@
codegentemp
CortexM3
*.Micha_000
*.rpt
*.pdf
*.html

BIN
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/.USBFS_boot.c.swp Normal file
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270
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c Executable file
View File

@ -0,0 +1,270 @@
/****************************************************************************//**
* \file Bootloadable_1.c
* \version 1.50
*
* \brief
* Provides an API for the Bootloadable application.
*
********************************************************************************
* \copyright
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "Bootloadable_1.h"
/**
\defgroup functions_group Functions
@{
*/
#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \
;
#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/
/*******************************************************************************
* Function Name: Bootloadable_1_Load
****************************************************************************//**
*
* \brief
* Schedules the Bootloader/Launcher to be launched and then performs
* a software reset to launch it
*
* \return
* This method will never return. It will load a new application and reset
* the device.
*
*******************************************************************************/
void Bootloadable_1_Load(void)
{
/* Schedule Bootloader to start after reset */
Bootloadable_1_SET_RUN_TYPE(Bootloadable_1_SCHEDULE_BTLDR);
CySoftwareReset();
}
#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
/*******************************************************************************
* Function Name: Bootloadable_1_GetActiveApplication
****************************************************************************//**
*
* \brief
* Gets the application which will be loaded after a next reset event.
* NOTE Intended for the combination project type ONLY!
*
* \return
* A number of the current active application set in the metadata section.
* \n 0 - app#0 is set as active.
* \n 1 - app#1 is set as active.
*
* \note If neither of the applications is set active, then the API returns 0x02.
*
*******************************************************************************/
uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \
{
uint8 result = Bootloadable_1_MD_BTLDB_ACTIVE_NONE;
if (0u != Bootloadable_1_GET_CODE_DATA( \
Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_0)))
{
result = Bootloadable_1_MD_BTLDB_ACTIVE_0;
}
else if (0u != Bootloadable_1_GET_CODE_DATA( \
Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_1)))
{
result = Bootloadable_1_MD_BTLDB_ACTIVE_1;
}
else
{
/*Do nothing, result is none*/
}
return (result);
}
/*******************************************************************************
* Function Name: Bootloadable_1_SetActiveApplication
****************************************************************************//**
*
* \brief
* Sets the application which will be loaded after a next reset event.
*
* \details
* Theory:
* This API sets in the Flash (metadata section) the given active application
* number.
*
* NOTE The active application number is not set directly, but the boolean
* mark instead means that the application is active or not for the relative
* metadata. Both metadata sections are updated. For example, if the second
* application is to be set active, then in the metadata section for the first
* application there will be a "0" written, which means that it is not active, and
* for the second metadata section there will be a "1" written, which means that it is
* active.
*
* NOTE Intended for the combination project type ONLY!
*
* \param appId
* The active application number to be written to flash (metadata section)
* NOTE Possible values are:
* 0 - for the first application
* 1 - for the second application.
* Any other number is considered invalid.
*
* \return
* A status of writing to flash operation.
* \n CYRET_SUCCESS - Returned if appId was successfully changed.
* \n CYRET_BAD_PARAM - Returned if the parameter appID passed to the function has the
* same value as the active application ID.
* \note - The other non-zero value is considered as a failure during writing to flash.
*
* \note - This API does not update Bootloader_activeApp variable.
*
*******************************************************************************/
cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \
{
cystatus result = CYRET_SUCCESS;
uint8 CYDATA idx;
/* If invalid application number */
if (appId > Bootloadable_1_MD_BTLDB_ACTIVE_1)
{
result = CYRET_BAD_PARAM;
}
else
{
/* If appID has same value as active application ID */
if (1u == Bootloadable_1_GET_CODE_DATA(Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId)))
{
result = CYRET_BAD_PARAM;
}
else
{
/* Updating metadata section */
for(idx = 0u; idx < Bootloadable_1_MAX_NUM_OF_BTLDB; idx++)
{
result |= Bootloadable_1_WriteFlashByte((uint32) Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(idx), \
(uint8)(idx == appId));
}
}
}
return (result);
}
/*******************************************************************************
* Function Name: Bootloadable_1_WriteFlashByte
****************************************************************************//**
*
* \brief
* This API writes to flash the specified data.
*
* \param address
* The address in flash.
*
* \param inputValue
* One-byte data.
*
* \return
* A status of the writing to flash procedure.
*
*******************************************************************************/
static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \
{
cystatus result = CYRET_SUCCESS;
uint32 flsAddr = address - CYDEV_FLASH_BASE;
uint8 rowData[CYDEV_FLS_ROW_SIZE];
#if !(CY_PSOC4)
uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);
#endif /* !(CY_PSOC4) */
#if (CY_PSOC4)
uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);
#else
uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
#endif /* (CY_PSOC4) */
uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);
uint16 idx;
for(idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++)
{
rowData[idx] = (uint8)Bootloadable_1_GET_CODE_DATA(baseAddr + idx);
}
rowData[address % CYDEV_FLS_ROW_SIZE] = inputValue;
#if(CY_PSOC4)
result = CySysFlashWriteRow((uint32) rowNum, rowData);
#else
result = CyWriteRowData(arrayId, rowNum, rowData);
#endif /* (CY_PSOC4) */
#if(CY_PSOC5)
/***************************************************************************
* When writing to flash, data in the instruction cache can become stale.
* Therefore, the cache data does not correlate to the data just written to
* flash. A call to CyFlushCache() is required to invalidate the data in the
* cache and force fresh information to be loaded from flash.
***************************************************************************/
CyFlushCache();
#endif /* (CY_PSOC5) */
return (result);
}
#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/
/** @} functions_group */
/*******************************************************************************
* The following code is OBSOLETE and must not be used.
*******************************************************************************/
void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType)
{
uint32 flsAddr = address - CYDEV_FLASH_BASE;
uint8 rowData[CYDEV_FLS_ROW_SIZE];
#if !(CY_PSOC4)
uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);
#endif /* !(CY_PSOC4) */
#if (CY_PSOC4)
uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);
#else
uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
#endif /* (CY_PSOC4) */
uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);
uint16 idx;
for (idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++)
{
rowData[idx] = Bootloadable_1_GET_CODE_DATA(baseAddr + idx);
}
rowData[address % CYDEV_FLS_ROW_SIZE] = runType;
#if(CY_PSOC4)
(void) CySysFlashWriteRow((uint32) rowNum, rowData);
#else
(void) CyWriteRowData(arrayId, rowNum, rowData);
#endif /* (CY_PSOC4) */
#if(CY_PSOC5)
/***************************************************************************
* When writing to flash, data in the instruction cache can become obsolete.
* Therefore, the cache data does not correlate to the data just written to
* flash. A call to CyFlushCache() is required to invalidate the data in the
* cache and force fresh information to be loaded from flash.
***************************************************************************/
CyFlushCache();
#endif /* (CY_PSOC5) */
}
/* [] END OF FILE */

200
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h Executable file
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/****************************************************************************//**
* \file Bootloadable_1.c
* \version 1.50
*
* \brief
* Provides an API for the Bootloadable application. The API includes a
* single function for starting the Bootloader.
*
********************************************************************************
* \copyright
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#ifndef CY_BOOTLOADABLE_Bootloadable_1_H
#define CY_BOOTLOADABLE_Bootloadable_1_H
#include "cydevice_trm.h"
#include "CyFlash.h"
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
#error Component Bootloadable_v1_50 requires cy_boot v3.0 or later
#endif /* !defined (CY_PSOC5LP) */
#ifndef CYDEV_FLASH_BASE
#define CYDEV_FLASH_BASE CYDEV_FLS_BASE
#define CYDEV_FLASH_SIZE CYDEV_FLS_SIZE
#endif /* CYDEV_FLASH_BASE */
#if(CY_PSOC3)
#define Bootloadable_1_GET_CODE_DATA(idx) (*((uint8 CYCODE *) (idx)))
#else
#define Bootloadable_1_GET_CODE_DATA(idx) (*((uint8 *)(CYDEV_FLASH_BASE + (idx))))
#endif /* (CY_PSOC3) */
/*******************************************************************************
* This variable is used by the Bootloader/Bootloadable components to schedule which
* application will be started after a software reset.
*******************************************************************************/
#if (CY_PSOC4)
#if defined(__ARMCC_VERSION)
__attribute__ ((section(".bootloaderruntype"), zero_init))
#elif defined (__GNUC__)
__attribute__ ((section(".bootloaderruntype")))
#elif defined (__ICCARM__)
#pragma location=".bootloaderruntype"
#endif /* defined(__ARMCC_VERSION) */
extern volatile uint32 cyBtldrRunType;
#endif /* (CY_PSOC4) */
/*******************************************************************************
* Gets the reason for a device reset
*******************************************************************************/
#if(CY_PSOC4)
#define Bootloadable_1_RES_CAUSE_RESET_SOFT (0x10u)
#define Bootloadable_1_GET_RUN_TYPE \
(((CY_GET_REG32(CYREG_RES_CAUSE) & Bootloadable_1_RES_CAUSE_RESET_SOFT) > 0u) \
? (cyBtldrRunType) \
: 0u)
#else
#define Bootloadable_1_GET_RUN_TYPE (CY_GET_REG8(CYREG_RESET_SR0) & \
(Bootloadable_1_START_BTLDR | Bootloadable_1_START_APP))
#endif /* (CY_PSOC4) */
/*******************************************************************************
* Schedule the Bootloader/Bootloadable to be run after a software reset.
*******************************************************************************/
#if(CY_PSOC4)
#define Bootloadable_1_SET_RUN_TYPE(x) (cyBtldrRunType = (x))
#else
#define Bootloadable_1_SET_RUN_TYPE(x) CY_SET_REG8(CYREG_RESET_SR0, (x))
#endif /* (CY_PSOC4) */
/***************************************
* Function Prototypes
***************************************/
extern void Bootloadable_1_Load(void) ;
/*******************************************************************************
* The following code is OBSOLETE and must not be used starting from version 1.10.
*******************************************************************************/
#define CYBTDLR_SET_RUN_TYPE(x) Bootloadable_1_SET_RUN_TYPE(x)
/*******************************************************************************
* Bootloadable's declarations for in-app bootloading.
*******************************************************************************/
#define Bootloadable_1_MD_BTLDB_ACTIVE_0 (0x00u)
#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
#define Bootloadable_1_MAX_NUM_OF_BTLDB (0x02u)
#define Bootloadable_1_MD_BTLDB_ACTIVE_1 (0x01u)
#define Bootloadable_1_MD_BTLDB_ACTIVE_NONE (0x02u)
#define Bootloadable_1_MD_SIZEOF (64u)
#define Bootloadable_1_MD_BASE_ADDR(appId) (CYDEV_FLASH_BASE + (CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \
Bootloadable_1_MD_SIZEOF))
#define Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId) (Bootloadable_1_MD_BASE_ADDR(appId) + 16u)
#else
#define Bootloadable_1_MAX_NUM_OF_BTLDB (0x01u)
#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/
/* Mask used to indicate starting application */
#define Bootloadable_1_SCHEDULE_BTLDB (0x80u)
#define Bootloadable_1_SCHEDULE_BTLDR (0x40u)
#define Bootloadable_1_SCHEDULE_MASK (0xC0u)
/*******************************************************************************
* API prototypes
*******************************************************************************/
#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \
;
cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \
;
#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/
/*******************************************************************************
* The following code is OBSOLETE and must not be used starting from version 1.20
*******************************************************************************/
#define Bootloadable_1_START_APP (0x80u)
#define Bootloadable_1_START_BTLDR (0x40u)
#define Bootloadable_1_META_DATA_SIZE (64u)
#define Bootloadable_1_META_APP_CHECKSUM_OFFSET (0u)
#if(CY_PSOC3)
#define Bootloadable_1_APP_ADDRESS uint16
#define Bootloadable_1_GET_CODE_WORD(idx) (*((uint32 CYCODE *) (idx)))
/* Offset by 2 from 32 bit start because only 16 bits are needed */
#define Bootloadable_1_META_APP_ADDR_OFFSET (3u)
#define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET (7u)
#define Bootloadable_1_META_APP_BYTE_LEN_OFFSET (11u)
#define Bootloadable_1_META_APP_RUN_TYPE_OFFSET (15u)
#else
#define Bootloadable_1_APP_ADDRESS uint32
#define Bootloadable_1_GET_CODE_WORD(idx) (*((uint32 *)(CYDEV_FLASH_BASE + (idx))))
#define Bootloadable_1_META_APP_ADDR_OFFSET (1u)
#define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET (5u)
#define Bootloadable_1_META_APP_BYTE_LEN_OFFSET (9u)
#define Bootloadable_1_META_APP_RUN_TYPE_OFFSET (13u)
#endif /* (CY_PSOC3) */
#define Bootloadable_1_META_APP_ACTIVE_OFFSET (16u)
#define Bootloadable_1_META_APP_VERIFIED_OFFSET (17u)
#define Bootloadable_1_META_APP_BL_BUILD_VER_OFFSET (18u)
#define Bootloadable_1_META_APP_ID_OFFSET (20u)
#define Bootloadable_1_META_APP_VER_OFFSET (22u)
#define Bootloadable_1_META_APP_CUST_ID_OFFSET (24u)
#define Bootloadable_1_SetFlashRunType(runType) \
Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType))
/*******************************************************************************
* The following code is OBSOLETE and must not be used.
*
* If the obsoleted macro definitions are intended for the application, use the
* following scheme, redefine your own versions of these definitions:
* #ifdef <OBSOLETED_DEFINE>
* #undef <OBSOLETED_DEFINE>
* #define <OBSOLETED_DEFINE> (<New Value>)
* #endif
*
* NOTE Redefine obsoleted macro definitions with caution. They might still be
* used in the application and their modification might lead to unexpected
* consequences.
*******************************************************************************/
void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;
#if(CY_PSOC4)
#define Bootloadable_1_SOFTWARE_RESET CySoftwareReset()
#else
#define Bootloadable_1_SOFTWARE_RESET CySoftwareReset()
#endif /* (CY_PSOC4) */
#if(CY_PSOC4)
extern uint8 appRunType;
#endif /* (CY_PSOC4) */
#endif /* CY_BOOTLOADABLE_Bootloadable_1_H */
/* [] END OF FILE */

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software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c Executable file
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/*******************************************************************************
* File Name: CFG_EEPROM.c
* Version 3.0
*
* Description:
* Provides the source code to the API for the EEPROM component.
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "CFG_EEPROM.h"
/*******************************************************************************
* Function Name: CFG_EEPROM_Enable
********************************************************************************
*
* Summary:
* Enable the EEPROM block. Also reads the temperature and stores it for
* future writes.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CFG_EEPROM_Enable(void)
{
/* Read temperature value */
(void)CySetTemp();
/* Start EEPROM block */
CyEEPROM_Start();
}
/*******************************************************************************
* Function Name: CFG_EEPROM_Start
********************************************************************************
*
* Summary:
* Starts EEPROM.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CFG_EEPROM_Start(void)
{
CFG_EEPROM_Enable();
}
/*******************************************************************************
* Function Name: CFG_EEPROM_Stop
********************************************************************************
*
* Summary:
* Stops and powers down EEPROM.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CFG_EEPROM_Stop (void)
{
/* Stop and power down EEPROM block */
CyEEPROM_Stop();
}
/*******************************************************************************
* Function Name: CFG_EEPROM_WriteByte
********************************************************************************
*
* Summary:
* Writes a byte of data to the EEPROM. This function blocks until
* the function is complete. For a reliable write procedure to occur you should
* call CFG_EEPROM_UpdateTemperature() function if the temperature of the
* silicon has been changed for more than 10C since the component was started.
*
* Parameters:
* dataByte: The byte of data to write to the EEPROM
* address: The address of data to be written. The maximum address is dependent
* on the EEPROM size.
*
* Return:
* CYRET_SUCCESS, if the operation was successful.
* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
* CYRET_LOCKED, if the SPC is being used.
* CYRET_UNKNOWN, if there was an SPC error.
*
*******************************************************************************/
cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address)
{
cystatus status;
uint16 rowNumber;
uint16 byteNumber;
CySpcStart();
if (address < CY_EEPROM_SIZE)
{
rowNumber = address/(uint16)CY_EEPROM_SIZEOF_ROW;
byteNumber = address - (rowNumber * ((uint16)CY_EEPROM_SIZEOF_ROW));
if(CYRET_SUCCESS == CySpcLock())
{
status = CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, byteNumber, &dataByte, \
CFG_EEPROM_SPC_BYTE_WRITE_SIZE);
if (CYRET_STARTED == status)
{
/* Plan for failure */
status = CYRET_UNKNOWN;
while(CY_SPC_BUSY)
{
/* Wait until SPC becomes idle */
}
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
/* Command to erase and program the row. */
if(CYRET_SUCCESS == status)
{
if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
dieTemperature[1u]) == CYRET_STARTED)
{
/* Plan for failure */
status = CYRET_UNKNOWN;
while(CY_SPC_BUSY)
{
/* Wait until SPC becomes idle */
}
/* SPC is idle now */
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
}
else
{
status = CYRET_UNKNOWN;
}
}
else
{
status = CYRET_UNKNOWN;
}
}
else
{
if (CYRET_BAD_PARAM != status)
{
status = CYRET_UNKNOWN;
}
}
CySpcUnlock();
}
else
{
status = CYRET_LOCKED;
}
}
else
{
status = CYRET_BAD_PARAM;
}
return (status);
}
/*******************************************************************************
* Function Name: CFG_EEPROM_ReadByte
********************************************************************************
*
* Summary:
* Reads and returns a byte of data from the on-chip EEPROM memory. Although
* the data is present in the CPU memory space, this function provides an
* intuitive user interface, addressing the EEPROM memory as a separate block with
* the first EERPOM byte address equal to 0x0000.
*
* Parameters:
* address: The address of data to be read. The maximum address is limited by the
* size of the EEPROM array on a specific device.
*
* Return:
* Data located at an address.
*
*******************************************************************************/
uint8 CFG_EEPROM_ReadByte(uint16 address)
{
uint8 retByte;
uint8 interruptState;
interruptState = CyEnterCriticalSection();
/* Request access to EEPROM for reading.
This is needed to reserve PHUB for read operation from EEPROM */
CyEEPROM_ReadReserve();
retByte = *((reg8 *) (CYDEV_EE_BASE + address));
/* Release EEPROM array */
CyEEPROM_ReadRelease();
CyExitCriticalSection(interruptState);
return (retByte);
}
/*******************************************************************************
* Function Name: CFG_EEPROM_UpdateTemperature
********************************************************************************
*
* Summary:
* Updates and stores the temperature value. This function should be called
* before EEPROM writes if the temperature may have been changed by more than
* 10 degrees Celsius.
*
* Parameters:
* None
*
* Return:
* Status of operation, 0 if operation complete, non-zero value if error
* was detected.
*
*******************************************************************************/
uint8 CFG_EEPROM_UpdateTemperature(void)
{
return ((uint8)CySetTemp());
}
/*******************************************************************************
* Function Name: CFG_EEPROM_EraseSector
********************************************************************************
*
* Summary:
* Erase an EEPROM sector (64 rows). This function blocks until the erase
* operation is complete. Using this API helps to erase the EEPROM sector at
* a time. This is faster than using individual writes but affects a cycle
* recourse of the whole EEPROM row.
*
* Parameters:
* sectorNumber: The sector number to erase.
*
* Return:
* CYRET_SUCCESS, if the operation was successful.
* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
* CYRET_LOCKED, if the SPC is being used.
* CYRET_UNKNOWN, if there was an SPC error.
*
*******************************************************************************/
cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber)
{
cystatus status;
CySpcStart();
if(sectorNumber < (uint8) CFG_EEPROM_SECTORS_NUMBER)
{
/* See if we can get SPC. */
if(CySpcLock() == CYRET_SUCCESS)
{
if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
{
/* Plan for failure */
status = CYRET_UNKNOWN;
while(CY_SPC_BUSY)
{
/* Wait until SPC becomes idle */
}
/* SPC is idle now */
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
}
else
{
status = CYRET_UNKNOWN;
}
/* Unlock SPC so that someone else can use it. */
CySpcUnlock();
}
else
{
status = CYRET_LOCKED;
}
}
else
{
status = CYRET_BAD_PARAM;
}
return(status);
}
/*******************************************************************************
* Function Name: CFG_EEPROM_Write
********************************************************************************
*
* Summary:
* Writes a row (16 bytes) of data to the EEPROM. This function blocks until
* the write operation is complete. Compared to functions that write one byte,
* this function allows writing a whole row (16 bytes) at a time. For
* a reliable write procedure to occur you should call the
* CFG_EEPROM_UpdateTemperature() function if the temperature of the
* silicon has changed for more than 10C since component was started.
*
* Parameters:
* rowData: The address of the data to write to the EEPROM.
* rowNumber: The row number to write.
*
* Return:
* CYRET_SUCCESS, if the operation was successful.
* CYRET_BAD_PARAM, if the parameter rowNumber is out of range.
* CYRET_LOCKED, if the SPC is being used.
* CYRET_UNKNOWN, if there was an SPC error.
*
*******************************************************************************/
cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber)
{
cystatus status;
CySpcStart();
if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
{
/* See if we can get SPC. */
if(CySpcLock() == CYRET_SUCCESS)
{
/* Plan for failure */
status = CYRET_UNKNOWN;
/* Command to load a row of data */
if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)
{
while(CY_SPC_BUSY)
{
/* Wait until SPC becomes idle */
}
/* SPC is idle now */
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
/* Command to erase and program the row. */
if(status == CYRET_SUCCESS)
{
if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
dieTemperature[1u]) == CYRET_STARTED)
{
/* Plan for failure */
status = CYRET_UNKNOWN;
while(CY_SPC_BUSY)
{
/* Wait until SPC becomes idle */
}
/* SPC is idle now */
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
}
else
{
status = CYRET_UNKNOWN;
}
}
else
{
status = CYRET_UNKNOWN;
}
}
/* Unlock SPC so that someone else can use it. */
CySpcUnlock();
}
else
{
status = CYRET_LOCKED;
}
}
else
{
status = CYRET_BAD_PARAM;
}
return(status);
}
/*******************************************************************************
* Function Name: CFG_EEPROM_StartWrite
********************************************************************************
*
* Summary:
* Starts a write of a row (16 bytes) of data to the EEPROM.
* This function does not block. The function returns once the SPC has begun
* writing the data. This function must be used in combination with
* CFG_EEPROM_Query(). CFG_EEPROM_Query() must be called
* until it returns a status other than CYRET_STARTED. That indicates that the
* write has completed. Until CFG_EEPROM_Query() detects that
* the write is complete, the SPC is marked as locked to prevent another
* SPC operation from being performed. For a reliable write procedure to occur
* you should call CFG_EEPROM_UpdateTemperature() API if the temperature
* of the silicon has changed for more than 10C since component was started.
*
* Parameters:
* rowData: The address of the data to write to the EEPROM.
* rowNumber: The row number to write.
*
* Return:
* CYRET_STARTED, if the SPC command to write was successfully started.
* CYRET_BAD_PARAM, if the parameter rowNumber is out of range.
* CYRET_LOCKED, if the SPC is being used.
* CYRET_UNKNOWN, if there was an SPC error.
*
* Side effects:
* After calling this API, the device should not be powered down, reset or switched
* to low power modes until EEPROM operation is complete.
* Ignoring this recommendation may lead to data corruption or silicon
* unexpected behavior.
*
*******************************************************************************/
cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
{
cystatus status;
CySpcStart();
if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
{
/* See if we can get SPC. */
if(CySpcLock() == CYRET_SUCCESS)
{
/* Plan for failure */
status = CYRET_UNKNOWN;
/* Command to load a row of data */
if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)
{
while(CY_SPC_BUSY)
{
/* Wait until SPC becomes idle */
}
/* SPC is idle now */
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
/* Command to erase and program the row. */
if(status == CYRET_SUCCESS)
{
if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
dieTemperature[1u]) == CYRET_STARTED)
{
status = CYRET_STARTED;
}
else
{
status = CYRET_UNKNOWN;
}
}
else
{
status = CYRET_UNKNOWN;
}
}
}
else
{
status = CYRET_LOCKED;
}
}
else
{
status = CYRET_BAD_PARAM;
}
return(status);
}
/*******************************************************************************
* Function Name: CFG_EEPROM_StartErase
********************************************************************************
*
* Summary:
* Starts the EEPROM sector erase. This function does not block.
* The function returns once the SPC has begun writing the data. This function
* must be used in combination with CFG_EEPROM_Query().
* CFG_EEPROM_Query() must be called until it returns a status
* other than CYRET_STARTED. That indicates the erase has been completed.
* Until CFG_EEPROM_Query() detects that the erase is
* complete, the SPC is marked as locked to prevent another SPC operation
* from being performed.
*
* Parameters:
* sectorNumber: The sector number to erase.
*
* Return:
* CYRET_STARTED, if the SPC command to erase was successfully started.
* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
* CYRET_LOCKED, if the SPC is being used.
* CYRET_UNKNOWN, if there was an SPC error.
*
* Side effects:
* After calling this API, the device should not be powered down, reset or switched
* to low power modes until EEPROM operation is complete.
* Ignoring this recommendation may lead to data corruption or silicon
* unexpected behavior.
*
*******************************************************************************/
cystatus CFG_EEPROM_StartErase(uint8 sectorNumber)
{
cystatus status;
CySpcStart();
if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS)
{
/* See if we can get SPC. */
if(CySpcLock() == CYRET_SUCCESS)
{
/* Plan for failure */
status = CYRET_UNKNOWN;
/* Command to load a row of data */
if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
{
status = CYRET_SUCCESS;
}
}
else
{
status = CYRET_LOCKED;
}
}
else
{
status = CYRET_BAD_PARAM;
}
return(status);
}
/*******************************************************************************
* Function Name: CFG_EEPROM_Query
********************************************************************************
*
* Summary:
* Checks the status of an earlier call to CFG_EEPROM_StartWrite() or
* CFG_EEPROM_StartErase().
* This function must be called until it returns a value other than
* CYRET_STARTED. Once that occurs, the write or erase has been completed and
* the SPC is unlocked.
*
* Parameters:
* None
*
* Return:
* CYRET_STARTED, if the SPC command is still processing.
* CYRET_SUCCESS, if the operation was completed successfully.
* CYRET_UNKNOWN, if there was an SPC error.
*
*******************************************************************************/
cystatus CFG_EEPROM_Query(void)
{
cystatus status;
CySpcStart();
/* Check if SPC is idle */
if(CY_SPC_IDLE)
{
/* SPC is idle now */
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
else
{
status = CYRET_UNKNOWN;
}
/* Unlock SPC so that someone else can use it. */
CySpcUnlock();
}
else
{
status = CYRET_STARTED;
}
return(status);
}
/*******************************************************************************
* Function Name: CFG_EEPROM_ByteWritePos
********************************************************************************
*
* Summary:
* Writes a byte of data to the EEPROM. This is a blocking call. It will not
* return until the write operation succeeds or fails.
*
* Parameters:
* dataByte: The byte of data to write to the EEPROM.
* rowNumber: The EEPROM row number to program.
* byteNumber: The byte number within the row to program.
*
* Return:
* CYRET_SUCCESS, if the operation was successful.
* CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber is out of range.
* CYRET_LOCKED, if the SPC is being used.
* CYRET_UNKNOWN, if there was an SPC error.
*
*******************************************************************************/
cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
{
cystatus status;
/* Start SPC */
CySpcStart();
if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW))
{
/* See if we can get SPC. */
if(CySpcLock() == CYRET_SUCCESS)
{
/* Plan for failure */
status = CYRET_UNKNOWN;
/* Command to load byte of data */
if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\
CFG_EEPROM_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED)
{
while(CY_SPC_BUSY)
{
/* Wait until SPC becomes idle */
}
/* SPC is idle now */
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
/* Command to erase and program the row. */
if(status == CYRET_SUCCESS)
{
if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
dieTemperature[1u]) == CYRET_STARTED)
{
/* Plan for failure */
status = CYRET_UNKNOWN;
while(CY_SPC_BUSY)
{
/* Wait until SPC becomes idle */
}
/* SPC is idle now */
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
}
else
{
status = CYRET_UNKNOWN;
}
}
else
{
status = CYRET_UNKNOWN;
}
}
/* Unlock SPC so that someone else can use it. */
CySpcUnlock();
}
else
{
status = CYRET_LOCKED;
}
}
else
{
status = CYRET_BAD_PARAM;
}
return(status);
}
/* [] END OF FILE */

79
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h Executable file
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/*******************************************************************************
* File Name: CFG_EEPROM.h
* Version 3.0
*
* Description:
* Provides the function definitions for the EEPROM APIs.
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_EEPROM_CFG_EEPROM_H)
#define CY_EEPROM_CFG_EEPROM_H
#include "cydevice_trm.h"
#include "CyFlash.h"
#if !defined(CY_PSOC5LP)
#error Component EEPROM_v3_0 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
/***************************************
* Function Prototypes
***************************************/
void CFG_EEPROM_Enable(void) ;
void CFG_EEPROM_Start(void) ;
void CFG_EEPROM_Stop (void) ;
cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) \
;
uint8 CFG_EEPROM_ReadByte(uint16 address) ;
uint8 CFG_EEPROM_UpdateTemperature(void) ;
cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ;
cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ;
cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
;
cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) ;
cystatus CFG_EEPROM_Query(void) ;
cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
;
/****************************************
* API Constants
****************************************/
#define CFG_EEPROM_EEPROM_SIZE CYDEV_EE_SIZE
#define CFG_EEPROM_SPC_BYTE_WRITE_SIZE (0x01u)
#define CFG_EEPROM_SECTORS_NUMBER (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
#define CFG_EEPROM_AHB_REQ_SHIFT (0x00u)
#define CFG_EEPROM_AHB_REQ ((uint8)(0x01u << CFG_EEPROM_AHB_REQ_SHIFT))
#define CFG_EEPROM_AHB_ACK_SHIFT (0x01u)
#define CFG_EEPROM_AHB_ACK_MASK ((uint8)(0x01u << CFG_EEPROM_AHB_ACK_SHIFT))
/***************************************
* Registers
***************************************/
#define CFG_EEPROM_SPC_EE_SCR_REG (*(reg8 *) CYREG_SPC_EE_SCR)
#define CFG_EEPROM_SPC_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR)
/***************************************
* The following code is DEPRECATED and
* should not be used in new projects.
***************************************/
#define CFG_EEPROM_ByteWrite CFG_EEPROM_ByteWritePos
#define CFG_EEPROM_QueryWrite CFG_EEPROM_Query
#endif /* CY_EEPROM_CFG_EEPROM_H */
/* [] END OF FILE */

160
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf Executable file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x0;
define symbol __ICFEDIT_region_ROM_end__ = 131072 - 1;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2);
define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + (32768 / 2) - 1;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x0400;
/**** End of ICF editor section. ###ICF###*/
/******** Definitions ********/
define symbol CY_APPL_LOADABLE = 1;
define symbol CY_APPL_LOADER = 0;
define symbol CY_APPL_NUM = 1;
define symbol CY_APPL_MAX = 1;
define symbol CY_METADATA_SIZE = 64;
define symbol CY_CHECKSUM_EXCLUDE_SIZE = 0;
define symbol CY_EE_IN_BTLDR = 0x00;
define symbol CY_EE_SIZE = 2048;
include "cybootloader.icf";
if (!CY_APPL_LOADABLE) {
define symbol CYDEV_BTLDR_SIZE = 0;
}
define symbol CY_FLASH_SIZE = 131072;
define symbol CY_APPL_ORIGIN = 0;
define symbol CY_FLASH_ROW_SIZE = 256;
define symbol CY_ECC_ROW_SIZE = 32;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, last block CSTACK};
if (CY_APPL_LOADABLE)
{
define block LOADER { readonly section .cybootloader };
}
define block APPL with fixed order {readonly section .romvectors, readonly};
/* The address of the Flash row next after the Bootloader image */
define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE +
((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ?
(CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0);
/* The start address of Standard/Loader/Loadable#1 image */
define symbol CY_APPL1_START = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END;
/* The number of metadata records located at the end of Flash */
define symbol CY_METADATA_CNT = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0);
/* The application area size measured in rows */
define symbol CY_APPL_ROW_CNT = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT;
/* The start address of Loadable#2 image if any */
define symbol CY_APPL2_START = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE;
/* The current image (Standard/Loader/Loadable) start address */
define symbol CY_APPL_START = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START;
/* The ECC data placement address */
define exported symbol CY_ECC_OFFSET = (CY_APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;
/* The EEPROM offset and size that can be used by current application (Standard/Loader/Loadable) */
define symbol CY_EE_OFFSET = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;
define symbol CY_EE_IN_USE = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;
/* Define EEPROM region */
define region EEPROM_region = mem:[from (0x90200000 + CY_EE_OFFSET) size CY_EE_IN_USE];
/* Define APPL region that will limit application size */
define region APPL_region = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE];
/****** Initializations ******/
initialize by copy { readwrite };
do not initialize { section .noinit };
do not initialize { readwrite section .ramvectors };
/******** Placements *********/
if (CY_APPL_LOADABLE)
{
".cybootloader" : place at start of ROM_region {block LOADER};
}
"APPL" : place at start of APPL_region {block APPL};
"RAMVEC" : place at start of RAM_region { readwrite section .ramvectors };
"readwrite" : place in RAM_region { readwrite };
"HSTACK" : place at end of RAM_region { block HSTACK};
keep { section .cybootloader,
section .cyloadermeta,
section .cyloadablemeta,
section .cyconfigecc,
section .cy_checksum_exclude,
section .cycustnvl,
section .cywolatch,
section .cyeeprom,
section .cyflashprotect,
section .cymeta };
".cyloadermeta" : place at address mem : ((CY_APPL_LOADER && !CY_APPL_LOADABLE) ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };
if (CY_APPL_LOADABLE)
{
".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };
}
/*******************************************************************************
* Checksum Exclude Section. See cm0gcc.ld on placement details.
*******************************************************************************/
if (CY_APPL_LOADABLE)
{
/* Align size to the flash row size */
define symbol CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED = CY_CHECKSUM_EXCLUDE_SIZE + ((CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE)) : 0);
if (CY_CHECKSUM_EXCLUDE_SIZE != 0)
{
/* General case */
if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2))
{
define symbol CY_CHECKSUM_EXCLUDE_START = CY_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED;
}
else
{
define symbol CY_CHECKSUM_EXCLUDE_START = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED;
}
define symbol CY_CHECKSUM_EXCLUDE_START_ALIGNED = CY_CHECKSUM_EXCLUDE_START + ((CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE)) : 0);
".cy_checksum_exclude" : place at address mem : (CY_CHECKSUM_EXCLUDE_START_ALIGNED) { readonly section .cy_checksum_exclude };
} /* (CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED != 0) */
}
else
{
".cy_checksum_exclude" : place in ROM_region { readonly section .cy_checksum_exclude };
}
".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };
".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl };
".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch };
".cyeeprom" : place in EEPROM_region { readonly section .cyeeprom };
".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect };
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
/* EOF */

228
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat Executable file
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#! armcc -E
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;********************************************************************************
;* \file Cm3RealView.scat
;* \version 5.50
;*
;* \brief
;* This Linker Descriptor file describes the memory layout of the PSoC5
;* device. The memory layout of the final binary and hex images as well as
;* the placement in PSoC5 memory is described.
;*
;* romvectors: Cypress default Interrupt service routine vector table.
;* This is the ISR vector table at bootup. Used only for the reset vector.
;*
;* ramvectors: Cypress ram interrupt service routine vector table.
;* This is the ISR vector table used by the application.
;*
;********************************************************************************
;* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.
;* You may use this file only in accordance with the license, terms, conditions,
;* disclaimers, and limitations in the end user license agreement accompanying
;* the software package with which this file was provided.
;********************************************************************************/
#include "cyfitter.h"
#define CY_FLASH_SIZE 131072
#define CY_APPL_ORIGIN 0
#define CY_FLASH_ROW_SIZE 256
#define CY_ECC_ROW_SIZE 32
#define CY_EE_SIZE 2048
#define CY_METADATA_SIZE 64
#define CY_CHECKSUM_EXCLUDE_SIZE AlignExpr(0, CY_FLASH_ROW_SIZE)
#define CY_APPL_NUM 1
#define CY_APPL_MAX 1
; Define application base address
#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \
CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
#define CY_EE_IN_BTLDR 0
#if CY_APPL_ORIGIN
#define APPL1_START CY_APPL_ORIGIN
#else
#define APPL1_START AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE)
#endif
#define APPL_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE))
#define ECC_OFFSET ((APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE)
#define EE_OFFSET (CY_EE_IN_BTLDR ? 0 : (CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1))
#define EE_SIZE (CY_EE_IN_BTLDR ? CY_EE_SIZE : (CY_EE_SIZE / CY_APPL_MAX))
#else
#define APPL_START 0
#define ECC_OFFSET 0
#define EE_OFFSET 0
#define EE_SIZE CY_EE_SIZE
#endif
; Place Bootloader at the beginning of Flash
#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \
CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
CYBOOTLOADER 0
{
.cybootloader +0
{
* (.cybootloader)
}
}
#if CY_APPL_ORIGIN
ScatterAssert(APPL_START >= LoadLimit(CYBOOTLOADER))
#endif
#endif
APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START)
{
VECTORS +0
{
* (.romvectors)
}
CODE +0
{
* (+RO)
}
ISRVECTORS (0x20000000 - (32768 / 2)) UNINIT
{
* (.ramvectors)
}
NOINIT_DATA +0 UNINIT
{
* (.noinit)
}
DATA +0
{
.ANY (+RW, +ZI)
}
ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x1000) EMPTY 0x0400
{
}
ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x1000
{
}
}
/*******************************************************************************
* Bootloader Metadata Section. See cm0gcc.ld on placement details.
*******************************************************************************/
#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || \
CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER || \
CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LAUNCHER)
CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE)
{
.cyloadermeta +0 { * (.cyloadermeta) }
}
#endif
/*******************************************************************************
* Bootloadable Metadata Section. See cm0gcc.ld on placement details.
*******************************************************************************/
#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \
CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE)
{
.cyloadablemeta +0 { * (.cyloadablemeta) }
}
#endif
/*******************************************************************************
* Checksum Exclude Section. See cm0gcc.ld on placement details.
*******************************************************************************/
#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))
#if (0 != 0)
#if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2))
#define CY_CHECKSUM_APPL2_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ), CY_FLASH_ROW_SIZE))
#define CY_CHECKSUM_EXCLUDE_START AlignExpr(CY_CHECKSUM_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE)
#else
#define CY_CHECKSUM_EXCLUDE_START AlignExpr((CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE)
#endif
CY_CHECKSUM_EXCLUDE (CY_CHECKSUM_EXCLUDE_START)
{
.cy_checksum_exclude +0
{
* (.cy_checksum_exclude)
}
}
#endif /* (0 != 0) */
#endif
#if (CYDEV_ECC_ENABLE == 0)
CYCONFIGECC (0x80000000 + ECC_OFFSET)
{
.cyconfigecc +0 { * (.cyconfigecc) }
}
#endif
CYCUSTNVL 0x90000000
{
.cycustnvl +0 { * (.cycustnvl) }
}
CYWOLATCH 0x90100000
{
.cywolatch +0 { * (.cywolatch) }
}
#if defined(CYDEV_ALLOCATE_EEPROM)
CYEEPROM 0x90200000 + EE_OFFSET (EE_SIZE)
{
.cyeeprom +0 { * (.cyeeprom) }
}
#endif
CYFLASHPROTECT 0x90400000
{
.cyflashprotect +0 { * (.cyflashprotect) }
}
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/*******************************************************************************
* Bootloader Metadata Section. Must be part of the image, but beyond rom memory.
*******************************************************************************/
#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))
CYLOADERMETA +0
{
.cyloadermeta +0 { * (.cyloadermeta) }
}
#endif

503
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c Executable file
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/***************************************************************************//**
* \file Cm3Start.c
* \version 5.50
*
* \brief
* Startup code for the ARM CM3.
*
********************************************************************************
* \copyright
* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <limits.h>
#include "cydevice_trm.h"
#include "cytypes.h"
#include "cyfitter_cfg.h"
#include "CyLib.h"
#include "CyDmac.h"
#include "cyfitter.h"
#define CY_NUM_INTERRUPTS (32u)
#define CY_NUM_VECTORS (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS)
#define CY_NUM_ROM_VECTORS (4u)
#define CY_NVIC_APINT_PTR ((reg32 *) CYREG_NVIC_APPLN_INTR)
#define CY_NVIC_CFG_CTRL_PTR ((reg32 *) CYREG_NVIC_CFG_CONTROL)
#define CY_NVIC_APINT_PRIGROUP_3_5 (0x00000400u) /* Priority group 3.5 split */
#define CY_NVIC_APINT_VECTKEY (0x05FA0000u) /* This key is required in order to write the NVIC_APINT register */
#define CY_NVIC_CFG_STACKALIGN (0x00000200u) /* This specifies that the exception stack must be 8 byte aligned */
#if defined(__ARMCC_VERSION)
#define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit)
#elif defined (__GNUC__)
#define INITIAL_STACK_POINTER (&__cy_stack)
#elif defined (__ICCARM__)
#pragma language=extended
#pragma segment="CSTACK"
#define INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) }
extern void __iar_program_start( void );
extern void __iar_data_init3 (void);
#endif /* (__ARMCC_VERSION) */
#if defined(__GNUC__)
#include <errno.h>
extern int errno;
extern int end;
#endif /* defined(__GNUC__) */
/* Extern functions */
extern void CyBtldr_CheckLaunch(void);
/* Function prototypes */
void initialize_psoc(void);
CY_ISR(IntDefaultHandler);
void Reset(void);
/* Global variables */
#if !defined (__ICCARM__)
CY_NOINIT static uint32 cySysNoInitDataValid;
#endif /* !defined (__ICCARM__) */
/*******************************************************************************
* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned.
*******************************************************************************/
#if defined (__ICCARM__)
#pragma location=".ramvectors"
#pragma data_alignment=256
#else
CY_SECTION(".ramvectors")
CY_ALIGN(256)
#endif /* defined (__ICCARM__) */
cyisraddress CyRamVectors[CY_NUM_VECTORS];
/*******************************************************************************
* Function Name: IntDefaultHandler
****************************************************************************//**
*
* This function is called for all interrupts, other than a reset that gets
* called before the system is setup.
*
* Theory:
* Any value other than zero is acceptable.
*
*******************************************************************************/
CY_ISR(IntDefaultHandler)
{
/***************************************************************************
* We must not get here. If we do, a serious problem occurs, so go into
* an infinite loop.
***************************************************************************/
#if defined(__GNUC__)
if (errno == ENOMEM)
{
#ifdef CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK
CyBoot_IntDefaultHandler_Enomem_Exception_Callback();
#endif /* CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK */
while(1)
{
/* Out Of Heap Space
* This can be increased in the System tab of the Design Wide Resources.
*/
}
}
else
#endif
{
#ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK
CyBoot_IntDefaultHandler_Exception_EntryCallback();
#endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */
while(1)
{
}
}
}
#if defined(__ARMCC_VERSION)
/* Local function for device reset. */
extern void Reset(void);
/* Application entry point. */
extern void $Super$$main(void);
/* Linker-generated Stack Base addresses, Two Region and One Region */
extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit;
/* RealView C Library initialization. */
extern int __main(void);
/*******************************************************************************
* Function Name: Reset
****************************************************************************//**
*
* This function handles the reset interrupt for the RVDS/MDK toolchains.
* This is the first bit of code that is executed at startup.
*
*******************************************************************************/
void Reset(void)
{
#if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
/* For PSoC 5LP, debugging is enabled by default */
#if(CYDEV_DEBUGGING_ENABLE == 0)
*(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
#endif /* (CYDEV_DEBUGGING_ENABLE) */
/* Reset Status Register has Read-to-clear SW access mode.
* Preserve current RESET_SR0 state to make it available for next reading.
*/
*(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */
#if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))
CyBtldr_CheckLaunch();
#endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */
__main();
}
/*******************************************************************************
* Function Name: $Sub$$main
****************************************************************************//**
*
* This function is called immediately before the users main
*
*******************************************************************************/
void $Sub$$main(void)
{
initialize_psoc();
/* Call original main */
$Super$$main();
while (1)
{
/* If main returns, it is undefined what we should do. */
}
}
#elif defined(__GNUC__)
void Start_c(void);
/* Stack Base address */
extern void __cy_stack(void);
/* Application entry point. */
extern int main(void);
/* Static objects constructors initializer */
extern void __libc_init_array(void);
typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));
struct __cy_region
{
__cy_byte_align8 *init; /* Initial contents of this region. */
__cy_byte_align8 *data; /* Start address of region. */
size_t init_size; /* Size of initial data. */
size_t zero_size; /* Additional size to be zeroed. */
};
extern const struct __cy_region __cy_regions[];
extern const char __cy_region_num __attribute__((weak));
#define __cy_region_num ((size_t)&__cy_region_num)
/*******************************************************************************
* System Calls of the Red Hat newlib C Library
*******************************************************************************/
/*******************************************************************************
* Function Name: _exit
****************************************************************************//**
*
* Exit a program without cleaning up files. If your system doesn't provide
* this, it is best to avoid linking with subroutines that require it (exit,
* system).
*
* \param status: Status caused program exit.
*
*******************************************************************************/
__attribute__((weak))
void _exit(int status)
{
CyHalt((uint8) status);
while(1)
{
}
}
/*******************************************************************************
* Function Name: _sbrk
****************************************************************************//**
*
* Increase program data space. As malloc and related functions depend on this,
* it is useful to have a working implementation. The following suffices for a
* standalone system; it exploits the symbol end automatically defined by the
* GNU linker.
*
* \param nbytes: The number of bytes requested (if the parameter value is positive)
* from the heap or returned back to the heap (if the parameter value is
* negative).
*
*******************************************************************************/
__attribute__((weak))
void * _sbrk (int nbytes)
{
extern int end; /* Symbol defined by linker map. Start of free memory (as symbol). */
void * returnValue;
/* The statically held previous end of the heap, with its initialization. */
static void *heapPointer = (void *) &end; /* Previous end */
if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE)
{
returnValue = heapPointer;
heapPointer += nbytes;
}
else
{
errno = ENOMEM;
returnValue = (void *) -1;
}
return (returnValue);
}
/*******************************************************************************
* Function Name: Reset
****************************************************************************//**
*
* This function handles the reset interrupt for the GCC toolchain. This is the
* first bit of code that is executed at startup.
*
*******************************************************************************/
void Reset(void)
{
#if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
/* For PSoC 5LP, debugging is enabled by default */
#if(CYDEV_DEBUGGING_ENABLE == 0)
*(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
#endif /* (CYDEV_DEBUGGING_ENABLE) */
/* Reset Status Register has Read-to-clear SW access mode.
* Preserve current RESET_SR0 state to make it available for next reading.
*/
*(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */
#if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))
CyBtldr_CheckLaunch();
#endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */
Start_c();
}
/*******************************************************************************
* Function Name: Start_c
****************************************************************************//**
*
* This function handles initializing the .data and .bss sections in
* preparation for running the standard C code. Once initialization is complete
* it will call main(). This function will never return.
*
*******************************************************************************/
void Start_c(void) __attribute__ ((noreturn));
void Start_c(void)
{
unsigned regions = __cy_region_num;
const struct __cy_region *rptr = __cy_regions;
/* Initialize memory */
for (regions = __cy_region_num; regions != 0u; regions--)
{
uint32 *src = (uint32 *)rptr->init;
uint32 *dst = (uint32 *)rptr->data;
unsigned limit = rptr->init_size;
unsigned count;
for (count = 0u; count != limit; count += sizeof (uint32))
{
*dst = *src;
dst++;
src++;
}
limit = rptr->zero_size;
for (count = 0u; count != limit; count += sizeof (uint32))
{
*dst = 0u;
dst++;
}
rptr++;
}
/* Invoke static objects constructors */
__libc_init_array();
(void) main();
while (1)
{
/* If main returns, make sure we don't return. */
}
}
#elif defined (__ICCARM__)
/*******************************************************************************
* Function Name: __low_level_init
****************************************************************************//**
*
* This function performs early initializations for the IAR Embedded
* Workbench IDE. It is executed in the context of a reset interrupt handler
* before the data sections are initialized.
*
* \return
* The value that determines whether or not data sections should be initialized
* by the system startup code:
* 0 - skip data sections initialization;
* 1 - initialize data sections;
*
*******************************************************************************/
int __low_level_init(void)
{
#if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)
/* For PSoC 5LP, debugging is enabled by default */
#if(CYDEV_DEBUGGING_ENABLE == 0)
*(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
#endif /* (CYDEV_DEBUGGING_ENABLE) */
/* Reset Status Register has Read-to-clear SW access mode.
* Preserve current RESET_SR0 state to make it available for next reading.
*/
*(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */
#if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))
CyBtldr_CheckLaunch();
#endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */
/* Initialize data sections */
__iar_data_init3();
initialize_psoc();
return 0;
}
#endif /* __GNUC__ */
/*******************************************************************************
*
* Default Rom Interrupt Vector table.
*
*******************************************************************************/
#if defined(__ARMCC_VERSION)
/* Suppress diagnostic message 1296-D: extended constant initialiser used */
#pragma diag_suppress 1296
#endif /* defined(__ARMCC_VERSION) */
#if defined (__ICCARM__)
#pragma location=".romvectors"
const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] =
#else
CY_SECTION(".romvectors")
const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
#endif /* defined (__ICCARM__) */
{
INITIAL_STACK_POINTER, /* Initial stack pointer 0 */
#if defined (__ICCARM__) /* Reset handler 1 */
__iar_program_start,
#else
(cyisraddress)&Reset,
#endif /* defined (__ICCARM__) */
&IntDefaultHandler, /* NMI handler 2 */
&IntDefaultHandler, /* Hard fault handler 3 */
};
#if defined(__ARMCC_VERSION)
#pragma diag_default 1296
#endif /* defined(__ARMCC_VERSION) */
/*******************************************************************************
* Function Name: initialize_psoc
****************************************************************************//**
*
* This function used to initialize the PSoC chip before calling main.
*
*******************************************************************************/
#if (defined(__GNUC__) && !defined(__ARMCC_VERSION))
__attribute__ ((constructor(101)))
#endif
void initialize_psoc(void)
{
uint32 i;
/* Set Priority group 5. */
/* Writes to NVIC_APINT register require the VECTKEY in the upper half */
*CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5;
*CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN;
/* Set Ram interrupt vectors to default functions. */
for (i = 0u; i < CY_NUM_VECTORS; i++)
{
#if defined (__ICCARM__)
CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandler;
#else
CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler;
#endif /* defined (__ICCARM__) */
}
/* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */
CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);
/* Point NVIC at RAM vector table. */
*CYINT_VECT_TABLE = CyRamVectors;
/* Initialize the configuration registers. */
cyfitter_cfg();
#if(0u != DMA_CHANNELS_USED__MASK0)
/* Setup DMA - only necessary if design contains DMA component. */
CyDmacConfigure();
#endif /* (0u != DMA_CHANNELS_USED__MASK0) */
#if !defined (__ICCARM__)
/* Actually, no need to clean this variable, just to make compiler happy. */
cySysNoInitDataValid = 0u;
#endif /* !defined (__ICCARM__) */
}
/* [] END OF FILE */

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software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s Executable file
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/***************************************************************************//**
* \file CyBootAsmGnu.s
* \version 5.50
*
* \brief
* Assembly routines for GNU as.
*
********************************************************************************
* \copyright
* Copyright 2010-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
.include "cyfittergnu.inc"
.syntax unified
.text
.thumb
/*******************************************************************************
* Function Name: CyDelayCycles
****************************************************************************//**
*
* Delays for the specified number of cycles.
*
* \param uint32 cycles: number of cycles to delay.
*
*******************************************************************************/
/* void CyDelayCycles(uint32 cycles) */
.align 3 /* Align to 8 byte boundary (2^n) */
.global CyDelayCycles
.func CyDelayCycles, CyDelayCycles
.type CyDelayCycles, %function
.thumb_func
CyDelayCycles: /* cycles bytes */
/* If ICache is enabled */
.ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1
ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */
LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */
BEQ CyDelayCycles_done /* 2 2 Skip if 0 */
NOP /* 1 2 Loop alignment padding */
CyDelayCycles_loop:
SUBS r0, r0, #1 /* 1 2 */
MOV r0, r0 /* 1 2 Pad loop to power of two cycles */
BNE CyDelayCycles_loop /* 2 2 */
CyDelayCycles_done:
BX lr /* 3 2 */
.else
CMP r0, #20 /* 1 2 If delay is short - jump to cycle */
BLS CyDelayCycles_short /* 1 2 */
PUSH {r1} /* 2 2 PUSH r1 to stack */
MOVS r1, #1 /* 1 2 */
SUBS r0, r0, #20 /* 1 2 Subtract overhead */
LDR r1,=CYREG_CACHE_CC_CTL/* 2 2 Load flash wait cycles value */
LDRB r1, [r1, #0] /* 2 2 */
ANDS r1, #0xC0 /* 1 2 */
LSRS r1, r1, #6 /* 1 2 */
PUSH {r2} /* 1 2 PUSH r2 to stack */
LDR r2, =cy_flash_cycles /* 2 2 */
LDRB r1, [r2, r1] /* 2 2 */
POP {r2} /* 2 2 POP r2 from stack */
NOP /* 1 2 Alignment padding */
NOP /* 1 2 Alignment padding */
NOP /* 1 2 Alignment padding */
CyDelayCycles_loop:
SBCS r0, r0, r1 /* 1 2 */
BPL CyDelayCycles_loop /* 3 2 */
NOP /* 1 2 Loop alignment padding */
NOP /* 1 2 Loop alignment padding */
POP {r1} /* 2 2 POP r1 from stack */
CyDelayCycles_done:
BX lr /* 3 2 */
NOP /* 1 2 Alignment padding */
NOP /* 1 2 Alignment padding */
CyDelayCycles_short:
SBCS r0, r0, #4 /* 1 2 */
BPL CyDelayCycles_short /* 3 2 */
BX lr /* 3 2 */
cy_flash_cycles:
.byte 0x0B
.byte 0x05
.byte 0x07
.byte 0x09
.endif
.endfunc
/*******************************************************************************
* Function Name: CyEnterCriticalSection
****************************************************************************//**
*
* CyEnterCriticalSection disables interrupts and returns a value indicating
* whether interrupts were previously enabled (the actual value depends on
* whether the device is PSoC 3 or PSoC 5).
*
* Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
* with interrupts still enabled. The test and set of the interrupt bits is not
* atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid
* corrupting processor state, it must be the policy that all interrupt routines
* restore the interrupt enable bits as they were found on entry.
*
* \return
* uint8
* Returns 0 if interrupts were previously enabled or 1 if interrupts
* were previously disabled.
*
*******************************************************************************/
/* uint8 CyEnterCriticalSection(void) */
.global CyEnterCriticalSection
.func CyEnterCriticalSection, CyEnterCriticalSection
.type CyEnterCriticalSection, %function
.thumb_func
CyEnterCriticalSection:
MRS r0, PRIMASK /* Save and return interrupt state */
CPSID I /* Disable interrupts */
BX lr
.endfunc
/*******************************************************************************
* Function Name: CyExitCriticalSection
****************************************************************************//**
*
* CyExitCriticalSection re-enables interrupts if they were enabled before
* CyEnterCriticalSection was called. The argument should be the value returned
* from CyEnterCriticalSection.
*
* \param uint8 savedIntrStatus:
* Saved interrupt status returned by the CyEnterCriticalSection function.
*
*******************************************************************************/
/* void CyExitCriticalSection(uint8 savedIntrStatus) */
.global CyExitCriticalSection
.func CyExitCriticalSection, CyExitCriticalSection
.type CyExitCriticalSection, %function
.thumb_func
CyExitCriticalSection:
MSR PRIMASK, r0 /* Restore interrupt state */
BX lr
.endfunc
.end
/* [] END OF FILE */

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software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s Executable file
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;-------------------------------------------------------------------------------
; FILENAME: CyBootAsmIar.s
; Version 5.50
;
; DESCRIPTION:
; Assembly routines for IAR Embedded Workbench IDE.
;
;-------------------------------------------------------------------------------
; Copyright 2013-2015, Cypress Semiconductor Corporation. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;-------------------------------------------------------------------------------
SECTION .text:CODE:ROOT(4)
PUBLIC CyDelayCycles
PUBLIC CyEnterCriticalSection
PUBLIC CyExitCriticalSection
INCLUDE cyfitteriar.inc
THUMB
;-------------------------------------------------------------------------------
; Function Name: CyEnterCriticalSection
;-------------------------------------------------------------------------------
;
; Summary:
; CyEnterCriticalSection disables interrupts and returns a value indicating
; whether interrupts were previously enabled.
;
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
; with interrupts still enabled. The test and set of the interrupt bits is not
; atomic. Therefore, to avoid a corrupting processor state, it must be the policy
; that all interrupt routines restore the interrupt enable bits as they were
; found on entry.
;
; Parameters:
; None
;
; Return:
; uint8
; Returns 0 if interrupts were previously enabled or 1 if interrupts
; were previously disabled.
;
;-------------------------------------------------------------------------------
; uint8 CyEnterCriticalSection(void)
CyEnterCriticalSection:
MRS r0, PRIMASK ; Save and return interrupt state
CPSID I ; Disable interrupts
BX lr
;-------------------------------------------------------------------------------
; Function Name: CyExitCriticalSection
;-------------------------------------------------------------------------------
;
; Summary:
; CyExitCriticalSection re-enables interrupts if they were enabled before
; CyEnterCriticalSection was called. The argument should be the value returned
; from CyEnterCriticalSection.
;
; Parameters:
; uint8 savedIntrStatus:
; Saved interrupt status returned by the CyEnterCriticalSection function.
;
; Return:
; None
;
;-------------------------------------------------------------------------------
; void CyExitCriticalSection(uint8 savedIntrStatus)
CyExitCriticalSection:
MSR PRIMASK, r0 ; Restore interrupt state
BX lr
;-------------------------------------------------------------------------------
; Function Name: CyDelayCycles
;-------------------------------------------------------------------------------
;
; Summary:
; Delays for the specified number of cycles.
;
; Parameters:
; uint32 cycles: number of cycles to delay.
;
; Return:
; None
;
;-------------------------------------------------------------------------------
; void CyDelayCycles(uint32 cycles)
CyDelayCycles:
IF CYDEV_INSTRUCT_CACHE_ENABLED == 1
; cycles bytes
ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4
LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags
BEQ CyDelayCycles_done ; 2 2 Skip if 0
NOP ; 1 2 Loop alignment padding
CyDelayCycles_loop:
SUBS r0, r0, #1 ; 1 2
MOV r0, r0 ; 1 2 Pad loop to power of two cycles
BNE CyDelayCycles_loop ; 2 2
CyDelayCycles_done:
BX lr ; 3 2
ELSE
CMP r0, #20 ; 1 2 If delay is short - jump to cycle
BLS CyDelayCycles_short ; 1 2
PUSH {r1} ; 2 2 PUSH r1 to stack
MOVS r1, #1 ; 1 2
SUBS r0, r0, #20 ; 1 2 Subtract overhead
LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value
LDRB r1, [r1, #0] ; 2 2
ANDS r1, r1, #0xC0 ; 1 2
LSRS r1, r1, #6 ; 1 2
PUSH {r2} ; 1 2 PUSH r2 to stack
LDR r2, =cy_flash_cycles ; 2 2
LDRB r1, [r2, r1] ; 2 2
POP {r2} ; 2 2 POP r2 from stack
NOP ; 1 2 Alignment padding
NOP ; 1 2 Alignment padding
NOP ; 1 2 Alignment padding
CyDelayCycles_loop:
SBCS r0, r0, r1 ; 1 2
BPL CyDelayCycles_loop ; 3 2
NOP ; 1 2 Loop alignment padding
NOP ; 1 2 Loop alignment padding
POP {r1} ; 2 2 POP r1 from stack
CyDelayCycles_done:
BX lr ; 3 2
NOP ; 1 2 Alignment padding
NOP ; 1 2 Alignment padding
CyDelayCycles_short:
SBCS r0, r0, #4 ; 1 2
BPL CyDelayCycles_short ; 3 2
BX lr ; 3 2
NOP ; 1 2 Loop alignment padding
DATA
cy_flash_cycles:
byte_1 DCB 0x0B
byte_2 DCB 0x05
byte_3 DCB 0x07
byte_4 DCB 0x09
ENDIF
END

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;-------------------------------------------------------------------------------
; FILENAME: CyBootAsmRv.s
; Version 5.50
;
; DESCRIPTION:
; Assembly routines for RealView.
;
;-------------------------------------------------------------------------------
; Copyright 2010-2015, Cypress Semiconductor Corporation. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;-------------------------------------------------------------------------------
AREA |.text|,CODE,ALIGN=3
THUMB
EXTERN Reset
GET cyfitterrv.inc
;-------------------------------------------------------------------------------
; Function Name: CyDelayCycles
;-------------------------------------------------------------------------------
;
; Summary:
; Delays for the specified number of cycles.
;
; Parameters:
; uint32 cycles: number of cycles to delay.
;
; Return:
; None
;
;-------------------------------------------------------------------------------
; void CyDelayCycles(uint32 cycles)
ALIGN 8
CyDelayCycles FUNCTION
EXPORT CyDelayCycles
IF CYDEV_INSTRUCT_CACHE_ENABLED == 1
; cycles bytes
ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4
LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags
BEQ CyDelayCycles_done ; 2 2 Skip if 0
NOP ; 1 2 Loop alignment padding
CyDelayCycles_loop
SUBS r0, r0, #1 ; 1 2
MOV r0, r0 ; 1 2 Pad loop to power of two cycles
BNE CyDelayCycles_loop ; 2 2
NOP ; 1 2 Loop alignment padding
CyDelayCycles_done
BX lr ; 3 2
ELSE
CMP r0, #20 ; 1 2 If delay is short - jump to cycle
BLS CyDelayCycles_short ; 1 2
PUSH {r1} ; 2 2 PUSH r1 to stack
MOVS r1, #1 ; 1 2
SUBS r0, r0, #20 ; 1 2 Subtract overhead
LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value
LDRB r1, [r1, #0] ; 2 2
ANDS r1, #0xC0 ; 1 2
LSRS r1, r1, #6 ; 1 2
PUSH {r2} ; 1 2 PUSH r2 to stack
LDR r2, =cy_flash_cycles ; 2 2
LDRB r1, [r2, r1] ; 2 2
POP {r2} ; 2 2 POP r2 from stack
NOP ; 1 2 Alignment padding
NOP ; 1 2 Alignment padding
NOP ; 1 2 Alignment padding
CyDelayCycles_loop
SBCS r0, r0, r1 ; 1 2
BPL CyDelayCycles_loop ; 3 2
NOP ; 1 2 Loop alignment padding
NOP ; 1 2 Loop alignment padding
POP {r1} ; 2 2 POP r1 from stack
CyDelayCycles_done
BX lr ; 3 2
NOP ; 1 2 Alignment padding
NOP ; 1 2 Alignment padding
CyDelayCycles_short
SBCS r0, r0, #4 ; 1 2
BPL CyDelayCycles_short ; 3 2
BX lr ; 3 2
cy_flash_cycles
byte_1 DCB 0x0B
byte_2 DCB 0x05
byte_3 DCB 0x07
byte_4 DCB 0x09
ENDIF
ENDFUNC
;-------------------------------------------------------------------------------
; Function Name: CyEnterCriticalSection
;-------------------------------------------------------------------------------
;
; Summary:
; CyEnterCriticalSection disables interrupts and returns a value indicating
; whether interrupts were previously enabled (the actual value depends on
; whether the device is PSoC 3 or PSoC 5).
;
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
; with interrupts still enabled. The test and set of the interrupt bits is not
; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a
; corrupting processor state, it must be the policy that all interrupt routines
; restore the interrupt enable bits as they were found on entry.
;
; Parameters:
; None
;
; Return:
; uint8
; Returns 0 if interrupts were previously enabled or 1 if interrupts
; were previously disabled.
;
;-------------------------------------------------------------------------------
; uint8 CyEnterCriticalSection(void)
CyEnterCriticalSection FUNCTION
EXPORT CyEnterCriticalSection
MRS r0, PRIMASK ; Save and return interrupt state
CPSID I ; Disable interrupts
BX lr
ENDFUNC
;-------------------------------------------------------------------------------
; Function Name: CyExitCriticalSection
;-------------------------------------------------------------------------------
;
; Summary:
; CyExitCriticalSection re-enables interrupts if they were enabled before
; CyEnterCriticalSection was called. The argument should be the value returned
; from CyEnterCriticalSection.
;
; Parameters:
; uint8 savedIntrStatus:
; Saved interrupt status returned by the CyEnterCriticalSection function.
;
; Return:
; None
;
;-------------------------------------------------------------------------------
; void CyExitCriticalSection(uint8 savedIntrStatus)
CyExitCriticalSection FUNCTION
EXPORT CyExitCriticalSection
MSR PRIMASK, r0 ; Restore interrupt state
BX lr
ENDFUNC
END
; [] END OF FILE

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software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c Executable file
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software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h Executable file
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/***************************************************************************//**
* \file CyDmac.h
* \version 5.50
*
* \brief Provides the function definitions for the DMA Controller.
*
* \note Documentation of the API's in this file is located in the System
* Reference Guide provided with PSoC Creator.
*
********************************************************************************
* \copyright
* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_BOOT_CYDMAC_H)
#define CY_BOOT_CYDMAC_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cydevice_trm.h"
#include "CyLib.h"
/***************************************
* Function Prototypes
***************************************/
/* DMA Controller functions. */
void CyDmacConfigure(void) ;
uint8 CyDmacError(void) ;
void CyDmacClearError(uint8 error) ;
uint32 CyDmacErrorAddress(void) ;
/* Channel specific functions. */
uint8 CyDmaChAlloc(void) ;
cystatus CyDmaChFree(uint8 chHandle) ;
cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ;
cystatus CyDmaChDisable(uint8 chHandle) ;
cystatus CyDmaClearPendingDrq(uint8 chHandle) ;
cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ;
cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination)\
;
cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ;
cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ;
cystatus CyDmaChGetRequest(uint8 chHandle) ;
cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ;
cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0,
uint8 tdDone1, uint8 tdStop) ;
cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ;
/* Transfer Descriptor functions. */
uint8 CyDmaTdAllocate(void) ;
void CyDmaTdFree(uint8 tdHandle) ;
uint8 CyDmaTdFreeCount(void) ;
cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration)\
;
cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration)\
;
cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ;
cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ;
/***************************************
* Data Struct Definitions
***************************************/
typedef struct dmac_ch_struct
{
volatile uint8 basic_cfg[4];
volatile uint8 action[4];
volatile uint8 basic_status[4];
volatile uint8 reserved[4];
} dmac_ch;
typedef struct dmac_cfgmem_struct
{
volatile uint8 CFG0[4];
volatile uint8 CFG1[4];
} dmac_cfgmem;
typedef struct dmac_tdmem_struct
{
volatile uint8 TD0[4];
volatile uint8 TD1[4];
} dmac_tdmem;
typedef struct dmac_tdmem2_struct
{
volatile uint16 xfercnt;
volatile uint8 next_td_ptr;
volatile uint8 flags;
volatile uint16 src_adr;
volatile uint16 dst_adr;
} dmac_tdmem2;
/***************************************
* API Constants
***************************************/
#define CY_DMA_INVALID_CHANNEL 0xFFu /* Invalid Channel ID */
#define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */
#define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */
#define CY_DMA_DISABLE_TD 0xFEu
#define CY_DMA_TD_SIZE 0x08u
/* "u" was removed as workaround for Keil compiler bug */
#define CY_DMA_TD_SWAP_EN 0x80
#define CY_DMA_TD_SWAP_SIZE4 0x40
#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20
#define CY_DMA_TD_TERMIN_EN 0x10
#define CY_DMA_TD_TERMOUT1_EN 0x08
#define CY_DMA_TD_TERMOUT0_EN 0x04
#define CY_DMA_TD_INC_DST_ADR 0x02
#define CY_DMA_TD_INC_SRC_ADR 0x01
#define CY_DMA_NUMBEROF_TDS 128u
#define CY_DMA_NUMBEROF_CHANNELS ((uint8)(CYDEV_DMA_CHANNELS_AVAILABLE))
/* Action register bits */
#define CY_DMA_CPU_REQ ((uint8)(1u << 0u))
#define CY_DMA_CPU_TERM_TD ((uint8)(1u << 1u))
#define CY_DMA_CPU_TERM_CHAIN ((uint8)(1u << 2u))
/* Basic Status register bits */
#define CY_DMA_STATUS_CHAIN_ACTIVE ((uint8)(1u << 0u))
#define CY_DMA_STATUS_TD_ACTIVE ((uint8)(1u << 1u))
/* DMA controller register error bits */
#define CY_DMA_BUS_TIMEOUT (1u << 1u)
#define CY_DMA_UNPOP_ACC (1u << 2u)
#define CY_DMA_PERIPH_ERR (1u << 3u)
/* Round robin bits */
#define CY_DMA_ROUND_ROBIN_ENABLE ((uint8)(1u << 4u))
/*******************************************************************************
* CyDmaChEnable() / CyDmaChDisable() API constants
*******************************************************************************/
#define CY_DMA_CH_BASIC_CFG_EN (0x01u)
#define CY_DMA_CH_BASIC_CFG_WORK_SEP (0x20u)
/***************************************
* Registers
***************************************/
#define CY_DMA_CFG_REG (*(reg32 *) CYREG_PHUB_CFG)
#define CY_DMA_CFG_PTR ( (reg32 *) CYREG_PHUB_CFG)
#define CY_DMA_ERR_REG (*(reg32 *) CYREG_PHUB_ERR)
#define CY_DMA_ERR_PTR ( (reg32 *) CYREG_PHUB_ERR)
#define CY_DMA_ERR_ADR_REG (*(reg32 *) CYREG_PHUB_ERR_ADR)
#define CY_DMA_ERR_ADR_PTR ( (reg32 *) CYREG_PHUB_ERR_ADR)
#define CY_DMA_CH_STRUCT_REG (*(dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE)
#define CY_DMA_CH_STRUCT_PTR ( (dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE)
#define CY_DMA_CFGMEM_STRUCT_REG (*(dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE)
#define CY_DMA_CFGMEM_STRUCT_PTR ( (dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE)
#define CY_DMA_TDMEM_STRUCT_REG (*(dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE)
#define CY_DMA_TDMEM_STRUCT_PTR ( (dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE)
/*******************************************************************************
* The following code is OBSOLETE and must not be used.
*
* If the obsoleted macro definitions intended for use in the application use the
* following scheme, redefine your own versions of these definitions:
* #ifdef <OBSOLETED_DEFINE>
* #undef <OBSOLETED_DEFINE>
* #define <OBSOLETED_DEFINE> (<New Value>)
* #endif
*
* Note: Redefine obsoleted macro definitions with caution. They might still be
* used in the application and their modification might lead to unexpected
* consequences.
*******************************************************************************/
#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL)
#define DMA_INVALID_TD (CY_DMA_INVALID_TD)
#define DMA_END_CHAIN_TD (CY_DMA_END_CHAIN_TD)
#define DMAC_TD_SIZE (CY_DMA_TD_SIZE)
#define TD_SWAP_EN (CY_DMA_TD_SWAP_EN)
#define TD_SWAP_SIZE4 (CY_DMA_TD_SWAP_SIZE4)
#define TD_AUTO_EXEC_NEXT (CY_DMA_TD_AUTO_EXEC_NEXT)
#define TD_TERMIN_EN (CY_DMA_TD_TERMIN_EN)
#define TD_TERMOUT1_EN (CY_DMA_TD_TERMOUT1_EN)
#define TD_TERMOUT0_EN (CY_DMA_TD_TERMOUT0_EN)
#define TD_INC_DST_ADR (CY_DMA_TD_INC_DST_ADR)
#define TD_INC_SRC_ADR (CY_DMA_TD_INC_SRC_ADR)
#define NUMBEROF_TDS (CY_DMA_NUMBEROF_TDS)
#define NUMBEROF_CHANNELS (CY_DMA_NUMBEROF_CHANNELS)
#define CPU_REQ (CY_DMA_CPU_REQ)
#define CPU_TERM_TD (CY_DMA_CPU_TERM_TD)
#define CPU_TERM_CHAIN (CY_DMA_CPU_TERM_CHAIN)
#define STATUS_CHAIN_ACTIVE (CY_DMA_STATUS_CHAIN_ACTIVE)
#define STATUS_TD_ACTIVE (CY_DMA_STATUS_TD_ACTIVE)
#define DMAC_BUS_TIMEOUT (CY_DMA_BUS_TIMEOUT)
#define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC)
#define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR)
#define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE)
#define DMA_DISABLE_TD (CY_DMA_DISABLE_TD)
#define DMAC_CFG (CY_DMA_CFG_PTR)
#define DMAC_ERR (CY_DMA_ERR_PTR)
#define DMAC_ERR_ADR (CY_DMA_ERR_ADR_PTR)
#define DMAC_CH (CY_DMA_CH_STRUCT_PTR)
#define DMAC_CFGMEM (CY_DMA_CFGMEM_STRUCT_PTR)
#define DMAC_TDMEM (CY_DMA_TDMEM_STRUCT_PTR)
#endif /* (CY_BOOT_CYDMAC_H) */
/* [] END OF FILE */

684
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c Executable file
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@ -0,0 +1,684 @@
/***************************************************************************//**
* \file CyFlash.c
* \version 5.50
*
* \brief Provides an API for the FLASH/EEPROM.
*
* \note This code is endian agnostic.
*
* \note Documentation of the API's in this file is located in the System
* Reference Guide provided with PSoC Creator.
*
********************************************************************************
* \copyright
* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "CyFlash.h"
/* The number of EEPROM arrays */
#define CY_FLASH_EEPROM_NUMBER_ARRAYS (1u)
/*******************************************************************************
* Holds the die temperature, updated by CySetTemp(). Used for flash writing.
* The first byte is the sign of the temperature (0 = negative, 1 = positive).
* The second byte is the magnitude.
*******************************************************************************/
uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
#if(CYDEV_ECC_ENABLE == 0)
static uint8 * rowBuffer = 0;
#endif /* (CYDEV_ECC_ENABLE == 0) */
static cystatus CySetTempInt(void);
static cystatus CyFlashGetSpcAlgorithm(void);
/*******************************************************************************
* Function Name: CyFlash_Start
****************************************************************************//**
*
* Enable the Flash.
*
*******************************************************************************/
void CyFlash_Start(void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
/***************************************************************************
* Enable SPC clock. This also internally enables the 36MHz IMO, since this
* is required for the SPC to function.
***************************************************************************/
CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
/***************************************************************************
* The wake count defines the number of Bus Clock cycles it takes for the
* flash or eeprom to wake up from a low power mode independent of the chip
* power mode. Wake up time for these blocks is 5 us.
* The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
* (30d) defines the wake up time as 60 cycles of the Bus Clock.
* This register needs to be written with a value dependent on the Bus Clock
* frequency so that the duration of the cycles is equal to or greater than
* the 5 us delay required.
***************************************************************************/
CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
/***************************************************************************
* Enable flash. Active flash macros consume current, but re-enabling a
* disabled flash macro takes 5us. If the CPU attempts to fetch out of the
* macro during that time, it will be stalled. This bit allows the flash to
* be enabled even if the CPU is disabled, which allows a quicker return to
* code execution.
***************************************************************************/
CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_FM;
CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM;
while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
{
/* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
}
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: CyFlash_Stop
****************************************************************************//**
*
* Disable the Flash.
*
* \sideeffect
* This setting is ignored as long as the CPU is currently running. This will
* only take effect when the CPU is later disabled.
*
*******************************************************************************/
void CyFlash_Stop(void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM));
CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM));
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: CySetTempInt
****************************************************************************//**
*
* Sends a command to the SPC to read the die temperature. Sets a global value
* used by the Write function. This function must be called once before
* executing a series of Flash writing functions.
*
* \return
* status:
* CYRET_SUCCESS - if successful
* CYRET_LOCKED - if Flash writing already in use
* CYRET_UNKNOWN - if there was an SPC error
*
*******************************************************************************/
static cystatus CySetTempInt(void)
{
cystatus status;
/* Make sure SPC is powered */
CySpcStart();
/* Plan for failure. */
status = CYRET_UNKNOWN;
if(CySpcLock() == CYRET_SUCCESS)
{
/* Write the command. */
if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES))
{
do
{
if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE)
{
status = CYRET_SUCCESS;
while(CY_SPC_BUSY)
{
/* Spin until idle. */
CyDelayUs(1u);
}
break;
}
} while(CY_SPC_BUSY);
}
CySpcUnlock();
}
else
{
status = CYRET_LOCKED;
}
return (status);
}
/*******************************************************************************
* Function Name: CyFlashGetSpcAlgorithm
****************************************************************************//**
*
* Sends a command to the SPC to download code into RAM.
*
* \return
* status:
* CYRET_SUCCESS - if successful
* CYRET_LOCKED - if Flash writing already in use
* CYRET_UNKNOWN - if there was an SPC error
*
*******************************************************************************/
static cystatus CyFlashGetSpcAlgorithm(void)
{
cystatus status;
/* Make sure SPC is powered */
CySpcStart();
if(CySpcLock() == CYRET_SUCCESS)
{
status = CySpcGetAlgorithm();
if(CYRET_STARTED == status)
{
while(CY_SPC_BUSY)
{
/* Spin until idle. */
CyDelayUs(1u);
}
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
}
CySpcUnlock();
}
else
{
status = CYRET_LOCKED;
}
return (status);
}
/*******************************************************************************
* Function Name: CySetTemp
****************************************************************************//**
*
* This is a wraparound for CySetTempInt(). It is used to return the second
* successful read of the temperature value.
*
* \return
* status:
* CYRET_SUCCESS if successful.
* CYRET_LOCKED if Flash writing already in use
* CYRET_UNKNOWN if there was an SPC error.
*
* uint8 dieTemperature[2]:
* Holds the die temperature for the flash writing algorithm. The first byte is
* the sign of the temperature (0 = negative, 1 = positive). The second byte is
* the magnitude.
*
*******************************************************************************/
cystatus CySetTemp(void)
{
cystatus status = CyFlashGetSpcAlgorithm();
if(status == CYRET_SUCCESS)
{
status = CySetTempInt();
}
return (status);
}
/*******************************************************************************
* Function Name: CySetFlashEEBuffer
****************************************************************************//**
*
* Sets the user supplied temporary buffer to store SPC data while performing
* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC
* is disabled.
*
* \param buffer:
* The address of a block of memory to store temporary memory. The size of the
* block of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.
*
* \return
* status:
* CYRET_SUCCESS if successful.
* CYRET_BAD_PARAM if the buffer is NULL
*
*******************************************************************************/
cystatus CySetFlashEEBuffer(uint8 * buffer)
{
cystatus status = CYRET_SUCCESS;
CySpcStart();
#if(CYDEV_ECC_ENABLE == 0)
if(NULL == buffer)
{
rowBuffer = rowBuffer;
status = CYRET_BAD_PARAM;
}
else if(CySpcLock() != CYRET_SUCCESS)
{
rowBuffer = rowBuffer;
status = CYRET_LOCKED;
}
else
{
rowBuffer = buffer;
CySpcUnlock();
}
#else
/* To suppress warning */
buffer = buffer;
#endif /* (CYDEV_ECC_ENABLE == 0u) */
return(status);
}
/*******************************************************************************
* Function Name: CyWriteRowData
****************************************************************************//**
*
* Sends a command to the SPC to load and program a row of data in
* Flash or EEPROM.
*
* \param arrayID: ID of the array to write.
* The type of write, Flash or EEPROM, is determined from the array ID.
* The arrays in the part are sequential starting at the first ID for the
* specific memory type. The array ID for the Flash memory lasts from 0x00 to
* 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
* \param rowAddress: rowAddress of flash row to program.
* \param rowData: Array of bytes to write.
*
* \return
* status:
* CYRET_SUCCESS if successful.
* CYRET_LOCKED if the SPC is already in use.
* CYRET_CANCELED if command not accepted
* CYRET_UNKNOWN if there was an SPC error.
*
*******************************************************************************/
cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData)
{
uint16 rowSize;
cystatus status;
rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
return(status);
}
/*******************************************************************
* If "Enable Error Correcting Code (ECC)" and "Store Configuration
* Data in ECC" DWR options are disabled, ECC section is available
* for user data.
*******************************************************************/
#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
/*******************************************************************************
* Function Name: CyWriteRowConfig
****************************************************************************//**
*
* Sends a command to the SPC to load and program a row of config data in the
* Flash. This function is only valid for Flash array IDs (not for EEPROM).
*
* \param arrayId: ID of the array to write
* The arrays in the part are sequential starting at the first ID for the
* specific memory type. The array ID for the Flash memory lasts
* from 0x00 to 0x3F.
* \param rowAddress: The address of the sector to erase.
* \param rowECC: The array of bytes to write.
*
* \return
* status:
* CYRET_SUCCESS if successful.
* CYRET_LOCKED if the SPC is already in use.
* CYRET_CANCELED if command not accepted
* CYRET_UNKNOWN if there was an SPC error.
*
*******************************************************************************/
cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\
{
cystatus status;
status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE);
return (status);
}
#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
/*******************************************************************************
* Function Name: CyWriteRowFull
****************************************************************************//**
* Sends a command to the SPC to load and program a row of data in the Flash.
* rowData array is expected to contain Flash and ECC data if needed.
*
* \param arrayId: FLASH or EEPROM array id.
* \param rowData: Pointer to a row of data to write.
* \param rowNumber: Zero based number of the row.
* \param rowSize: Size of the row.
*
* \return
* CYRET_SUCCESS if successful.
* CYRET_LOCKED if the SPC is already in use.
* CYRET_CANCELED if command not accepted
* CYRET_UNKNOWN if there was an SPC error.
*
*******************************************************************************/
cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \
{
cystatus status = CYRET_SUCCESS;
if((arrayId <= CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS + CY_SPC_FIRST_FLASH_ARRAYID)))
{
status = CYRET_BAD_PARAM;
}
if(arrayId > CY_SPC_LAST_EE_ARRAYID)
{
status = CYRET_BAD_PARAM;
}
if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID)))
{
status = CYRET_BAD_PARAM;
}
if(arrayId <= CY_SPC_LAST_FLASH_ARRAYID)
{
/* Flash */
if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS))
{
status = CYRET_BAD_PARAM;
}
}
else
{
/* EEPROM */
if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS))
{
status = CYRET_BAD_PARAM;
}
if(CY_EEPROM_SIZEOF_ROW != rowSize)
{
status = CYRET_BAD_PARAM;
}
}
if(rowData == NULL)
{
status = CYRET_BAD_PARAM;
}
if(status == CYRET_SUCCESS)
{
if(CySpcLock() == CYRET_SUCCESS)
{
/* Load row data into SPC internal latch */
status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize);
if(CYRET_STARTED == status)
{
while(CY_SPC_BUSY)
{
/* Wait for SPC to finish and get SPC status */
CyDelayUs(1u);
}
/* Hide SPC status */
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
else
{
status = CYRET_UNKNOWN;
}
if(CYRET_SUCCESS == status)
{
/* Erase and program flash with data from SPC interval latch */
status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
if(CYRET_STARTED == status)
{
while(CY_SPC_BUSY)
{
/* Wait for SPC to finish and get SPC status */
CyDelayUs(1u);
}
/* Hide SPC status */
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
else
{
status = CYRET_UNKNOWN;
}
}
}
}
CySpcUnlock();
} /* if(CySpcLock() == CYRET_SUCCESS) */
else
{
status = CYRET_LOCKED;
}
}
return(status);
}
/*******************************************************************************
* Function Name: CyFlash_SetWaitCycles
****************************************************************************//**
*
* Sets the number of clock cycles the cache will wait before it samples data
* coming back from the Flash. This function must be called before increasing
* the CPU clock frequency. It can optionally be called after lowering the CPU
* clock frequency in order to improve the CPU performance.
*
* \param uint8 freq:
* Frequency of operation in Megahertz.
*
*******************************************************************************/
void CyFlash_SetWaitCycles(uint8 freq)
{
uint8 interruptState;
/* Save current global interrupt enable and disable it */
interruptState = CyEnterCriticalSection();
/***************************************************************************
* The number of clock cycles the cache will wait before it samples data
* coming back from the Flash must be equal or greater to to the CPU frequency
* outlined in clock cycles.
***************************************************************************/
if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX)
{
CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
CY_FLASH_CACHE_WS_1_VALUE_MASK;
}
else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX)
{
CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
CY_FLASH_CACHE_WS_2_VALUE_MASK;
}
else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX)
{
CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
CY_FLASH_CACHE_WS_3_VALUE_MASK;
}
#if (CY_PSOC5)
else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX)
{
CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
CY_FLASH_CACHE_WS_4_VALUE_MASK;
}
else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX)
{
CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
CY_FLASH_CACHE_WS_5_VALUE_MASK;
}
#endif /* (CY_PSOC5) */
else
{
/* Halt CPU in debug mode if frequency is invalid */
CYASSERT(0u != 0u);
}
/* Restore global interrupt enable state */
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: CyEEPROM_Start
****************************************************************************//**
*
* Enable the EEPROM.
*
*******************************************************************************/
void CyEEPROM_Start(void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
/***************************************************************************
* Enable SPC clock. This also internally enables the 36MHz IMO, since this
* is required for the SPC to function.
***************************************************************************/
CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
/***************************************************************************
* The wake count defines the number of Bus Clock cycles it takes for the
* flash or EEPROM to wake up from a low power mode independent of the chip
* power mode. Wake up time for these blocks is 5 us.
* The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
* (30d) defines the wake up time as 60 cycles of the Bus Clock.
* This register needs to be written with a value dependent on the Bus Clock
* frequency so that the duration of the cycles is equal to or greater than
* the 5 us delay required.
***************************************************************************/
CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
/***************************************************************************
* Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time,
* the EE will not acknowledge a PHUB request.
***************************************************************************/
CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_EE;
CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE;
while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
{
/* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
}
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: CyEEPROM_Stop
****************************************************************************//**
*
* Disable the EEPROM.
*
*******************************************************************************/
void CyEEPROM_Stop (void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE));
CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE));
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: CyEEPROM_ReadReserve
****************************************************************************//**
*
* Request access to the EEPROM for reading and wait until access is available.
*
*******************************************************************************/
void CyEEPROM_ReadReserve(void)
{
/* Make request for PHUB to have access */
CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ;
while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK))
{
/* Wait for acknowledgment from PHUB */
}
}
/*******************************************************************************
* Function Name: CyEEPROM_ReadRelease
****************************************************************************//**
*
* Release the read reservation of the EEPROM.
*
*******************************************************************************/
void CyEEPROM_ReadRelease(void)
{
CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ);
}
/* [] END OF FILE */

322
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/***************************************************************************//**
* \file CyFlash.h
* \version 5.50
*
* \brief Provides the function definitions for the FLASH/EEPROM.
*
* \note Documentation of the API's in this file is located in the System
* Reference Guide provided with PSoC Creator.
*
********************************************************************************
* \copyright
* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_BOOT_CYFLASH_H)
#define CY_BOOT_CYFLASH_H
#include "cydevice_trm.h"
#include "cytypes.h"
#include "CyLib.h"
#include "CySpc.h"
#define CY_FLASH_DIE_TEMP_DATA_SIZE (2u) /* Die temperature data size */
extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
/***************************************
* API Constants
***************************************/
#define CY_FLASH_BASE (CYDEV_FLASH_BASE)
#define CY_FLASH_SIZE (CYDEV_FLS_SIZE)
#define CY_FLASH_SIZEOF_ARRAY (CYDEV_FLS_SECTOR_SIZE)
#define CY_FLASH_SIZEOF_ROW (CYDEV_FLS_ROW_SIZE)
#define CY_FLASH_SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE)
#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)
#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)
#if(CYDEV_ECC_ENABLE == 0)
#define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW)
#else
#define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW)
#endif /* (CYDEV_ECC_ENABLE == 0) */
#define CY_EEPROM_BASE (CYDEV_EE_BASE)
#define CY_EEPROM_SIZE (CYDEV_EE_SIZE)
#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EE_SIZE) /* EEPROM has one array */
#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE)
#define CY_EEPROM_NUMBER_ROWS (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)
#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)
#define CY_EEPROM_NUMBER_SECTORS (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
#define CY_EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE)
#if !defined(CYDEV_FLS_BASE)
#define CYDEV_FLS_BASE CYDEV_FLASH_BASE
#endif /* !defined(CYDEV_FLS_BASE) */
/***************************************
* Function Prototypes
***************************************/
/* Flash Functions */
void CyFlash_Start(void);
void CyFlash_Stop(void);
cystatus CySetTemp(void);
cystatus CySetFlashEEBuffer(uint8 * buffer);
cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, uint16 rowSize) \
;
cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData);
#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \
;
#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
void CyFlash_SetWaitCycles(uint8 freq) ;
/* EEPROM Functions */
void CyEEPROM_Start(void) ;
void CyEEPROM_Stop(void) ;
void CyEEPROM_ReadReserve(void) ;
void CyEEPROM_ReadRelease(void) ;
/***************************************
* Registers
***************************************/
/* Active Power Mode Configuration Register 0 */
#define CY_FLASH_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0)
#define CY_FLASH_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)
/* Alternate Active Power Mode Configuration Register 0 */
#define CY_FLASH_PM_ALTACT_CFG0_REG (* (reg8 *) CYREG_PM_STBY_CFG0)
#define CY_FLASH_PM_ALTACT_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)
/* Active Power Mode Configuration Register 12 */
#define CY_FLASH_PM_ACT_CFG12_REG (* (reg8 *) CYREG_PM_ACT_CFG12)
#define CY_FLASH_PM_ACT_CFG12_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)
/* Alternate Active Power Mode Configuration Register 12 */
#define CY_FLASH_PM_ALTACT_CFG12_REG (* (reg8 *) CYREG_PM_STBY_CFG12)
#define CY_FLASH_PM_ALTACT_CFG12_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)
/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */
#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR ( (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
/* Flash macro control register */
#define CY_FLASH_SPC_FM_EE_CR_REG (* (reg8 *) CYREG_SPC_FM_EE_CR)
#define CY_FLASH_SPC_FM_EE_CR_PTR ( (reg8 *) CYREG_SPC_FM_EE_CR)
/* Cache Control Register */
#if (CY_PSOC3)
#define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CR )
#define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CR )
#else
#define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CC_CTL )
#define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CC_CTL )
#endif /* (CY_PSOC3) */
/* EEPROM Status & Control Register */
#define CY_FLASH_EE_SCR_REG (* (reg8 *) CYREG_SPC_EE_SCR)
#define CY_FLASH_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR)
/***************************************
* Register Constants
***************************************/
/* Power Mode Masks */
/* Enable EEPROM */
#define CY_FLASH_PM_ACT_CFG12_EN_EE (0x10u)
#define CY_FLASH_PM_ALTACT_CFG12_EN_EE (0x10u)
/* Enable Flash */
#if (CY_PSOC3)
#define CY_FLASH_PM_ACT_CFG12_EN_FM (0x01u)
#define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x01u)
#else
#define CY_FLASH_PM_ACT_CFG12_EN_FM (0x0Fu)
#define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x0Fu)
#endif /* (CY_PSOC3) */
/* Frequency Constants */
#if (CY_PSOC3)
#define CY_FLASH_CACHE_WS_VALUE_MASK (0xC0u)
#define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u)
#define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u)
#define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u)
#define CY_FLASH_CACHE_WS_1_FREQ_MAX (22u)
#define CY_FLASH_CACHE_WS_2_FREQ_MAX (44u)
#define CY_FLASH_CACHE_WS_3_FREQ_MAX (67u)
#endif /* (CY_PSOC3) */
#if (CY_PSOC5)
#define CY_FLASH_CACHE_WS_VALUE_MASK (0xE0u)
#define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u)
#define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u)
#define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u)
#define CY_FLASH_CACHE_WS_4_VALUE_MASK (0x00u)
#define CY_FLASH_CACHE_WS_5_VALUE_MASK (0x20u)
#define CY_FLASH_CACHE_WS_1_FREQ_MAX (16u)
#define CY_FLASH_CACHE_WS_2_FREQ_MAX (33u)
#define CY_FLASH_CACHE_WS_3_FREQ_MAX (50u)
#define CY_FLASH_CACHE_WS_4_FREQ_MAX (67u)
#define CY_FLASH_CACHE_WS_5_FREQ_MAX (83u)
#endif /* (CY_PSOC5) */
#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u)
#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))
#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u)
#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u)
#define CY_FLASH_EE_EE_AWAKE (0x20u)
/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */
#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ (0xC8u)
/* Enable clk_spc. This also internally enables the 36MHz IMO. */
#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC (0x08u)
#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC (0x08u)
/* Default values for getting temperature. */
#define CY_TEMP_NUMBER_OF_SAMPLES (0x1u)
#define CY_TEMP_TIMER_PERIOD (0xFFFu)
#define CY_TEMP_CLK_DIV_SELECT (0x4u)
#define CY_TEMP_NUM_SAMPLES (1 << (CY_TEMP_NUMBER_OF_SAMPLES))
#define CY_SPC_CLK_PERIOD (120u) /* nS */
#define CY_SYS_ns_PER_TICK (1000u)
#define CY_FRM_EXEC_TIME (1000u) /* nS */
#define CY_GET_TEMP_TIME ((1 << (CY_TEMP_NUM_SAMPLES + 1)) * \
(CY_SPC_CLK_PERIOD * CY_TEMP_CLK_DIV_SELECT) * \
CY_TEMP_TIMER_PERIOD + CY_FRM_EXEC_TIME)
#define CY_TEMP_MAX_WAIT ((CY_GET_TEMP_TIME) / CY_SYS_ns_PER_TICK) /* In system ticks. */
/*******************************************************************************
* Thne following code is OBSOLETE and must not be used starting with cy_boot
* 4.20.
*
* If the obsoleted macro definitions intended for use in the application use the
* following scheme, redefine your own versions of these definitions:
* #ifdef <OBSOLETED_DEFINE>
* #undef <OBSOLETED_DEFINE>
* #define <OBSOLETED_DEFINE> (<New Value>)
* #endif
*
* Note: Redefine obsoleted macro definitions with caution. They might still be
* used in the application and their modification might lead to unexpected
* consequences.
*******************************************************************************/
#if (CY_PSOC5)
#define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)
#define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)
#define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)
#define CY_FLASH_GREATER_51MHz (0x00u)
#endif /* (CY_PSOC5) */
#if (CY_PSOC3)
#define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u)
#define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u)
#define CY_FLASH_GREATER_44MHz (0x03u)
#endif /* (CY_PSOC3) */
#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)
#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)
#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)
#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)
#define CY_FLASH_PM_EE_MASK (0x10u)
#define CY_FLASH_PM_FLASH_MASK (0x01u)
/*******************************************************************************
* The following code is OBSOLETE and must not be used starting with cy_boot 3.0
*******************************************************************************/
#define FLASH_SIZE (CY_FLASH_SIZE)
#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY)
#define FLASH_NUMBER_ROWS (CY_FLASH_NUMBER_ROWS)
#define FLASH_NUMBER_SECTORS (CY_FLASH_NUMBER_ARRAYS)
#define EEPROM_SIZE (CY_EEPROM_SIZE)
#define EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE)
#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS)
#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_SECTORS)
/*******************************************************************************
* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
*******************************************************************************/
#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR)
#define TEMP_NUMBER_OF_SAMPLES (CY_TEMP_NUMBER_OF_SAMPLES)
#define TEMP_TIMER_PERIOD (CY_TEMP_TIMER_PERIOD)
#define TEMP_CLK_DIV_SELECT (CY_TEMP_CLK_DIV_SELECT)
#define NUM_SAMPLES (CY_TEMP_NUM_SAMPLES)
#define SPC_CLK_PERIOD (CY_SPC_CLK_PERIOD)
#define FRM_EXEC_TIME (CY_FRM_EXEC_TIME)
#define GET_TEMP_TIME (CY_GET_TEMP_TIME)
#define TEMP_MAX_WAIT (CY_TEMP_MAX_WAIT)
#define ECC_ADDR (0x80u)
#define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)
#define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)
#define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
#define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
#define PM_EE_MASK (CY_FLASH_PM_EE_MASK)
#define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK)
#define FLASH_CYCLES_MASK_SHIFT (CY_FLASH_CYCLES_MASK_SHIFT)
#define FLASH_CYCLES_MASK (CY_FLASH_CYCLES_MASK)
#if (CY_PSOC3)
#define LESSER_OR_EQUAL_22MHz (CY_FLASH_LESSER_OR_EQUAL_22MHz)
#define LESSER_OR_EQUAL_44MHz (CY_FLASH_LESSER_OR_EQUAL_44MHz)
#define GREATER_44MHz (CY_FLASH_GREATER_44MHz)
#endif /* (CY_PSOC3) */
#if (CY_PSOC5)
#define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz)
#define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz)
#define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz)
#define LESSER_OR_EQUAL_67MHz (CY_FLASH_LESSER_OR_EQUAL_67MHz)
#define GREATER_67MHz (CY_FLASH_GREATER_67MHz)
#define GREATER_51MHz (CY_FLASH_GREATER_51MHz)
#endif /* (CY_PSOC5) */
#define AHUB_EE_REQ_ACK_PTR (CY_FLASH_EE_SCR_PTR)
#endif /* (CY_BOOT_CYFLASH_H) */
/* [] END OF FILE */

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software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c Executable file
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/***************************************************************************//**
* \file CySpc.c
* \version 5.50
*
* \brief Provides an API for the System Performance Component.
* The SPC functions are not meant to be called directly by the user
* application.
*
********************************************************************************
* \copyright
* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "CySpc.h"
#define CY_SPC_KEY_ONE (0xB6u)
#define CY_SPC_KEY_TWO(x) ((uint8) (((uint16) 0xD3u) + ((uint16) (x))))
/* Command Codes */
#define CY_SPC_CMD_LD_BYTE (0x00u)
#define CY_SPC_CMD_LD_MULTI_BYTE (0x01u)
#define CY_SPC_CMD_LD_ROW (0x02u)
#define CY_SPC_CMD_RD_BYTE (0x03u)
#define CY_SPC_CMD_RD_MULTI_BYTE (0x04u)
#define CY_SPC_CMD_WR_ROW (0x05u)
#define CY_SPC_CMD_WR_USER_NVL (0x06u)
#define CY_SPC_CMD_PRG_ROW (0x07u)
#define CY_SPC_CMD_ER_SECTOR (0x08u)
#define CY_SPC_CMD_ER_ALL (0x09u)
#define CY_SPC_CMD_RD_HIDDEN (0x0Au)
#define CY_SPC_CMD_PRG_PROTECT (0x0Bu)
#define CY_SPC_CMD_CHECKSUM (0x0Cu)
#define CY_SPC_CMD_DWNLD_ALGORITHM (0x0Du)
#define CY_SPC_CMD_GET_TEMP (0x0Eu)
#define CY_SPC_CMD_GET_ADC (0x0Fu)
#define CY_SPC_CMD_RD_NVL_VOLATILE (0x10u)
#define CY_SPC_CMD_SETUP_TS (0x11u)
#define CY_SPC_CMD_DISABLE_TS (0x12u)
#define CY_SPC_CMD_ER_ROW (0x13u)
/* Enable bit in Active and Alternate Active mode templates */
#define PM_SPC_PM_EN (0x08u)
/* Gate calls to the SPC. */
uint8 SpcLockState = CY_SPC_UNLOCKED;
#if(CY_PSOC5)
/***************************************************************************
* The wait-state pipeline must be enabled prior to accessing the SPC
* register interface regardless of CPU frequency. The CySpcLock() saves
* current wait-state pipeline state and enables it. The CySpcUnlock()
* function, which must be called after SPC transaction, restores original
* state.
***************************************************************************/
static uint32 spcWaitPipeBypass = 0u;
#endif /* (CY_PSOC5) */
/*******************************************************************************
* Function Name: CySpcStart
****************************************************************************//**
* Starts the SPC.
*
*******************************************************************************/
void CySpcStart(void)
{
/* Save current global interrupt enable and disable it */
uint8 interruptState = CyEnterCriticalSection();
CY_SPC_PM_ACT_REG |= PM_SPC_PM_EN;
CY_SPC_PM_STBY_REG |= PM_SPC_PM_EN;
/* Restore global interrupt enable state */
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: CySpcStop
****************************************************************************//**
* Stops the SPC.
*
*******************************************************************************/
void CySpcStop(void)
{
/* Save current global interrupt enable and disable it */
uint8 interruptState = CyEnterCriticalSection();
CY_SPC_PM_ACT_REG &= ((uint8)(~PM_SPC_PM_EN));
CY_SPC_PM_STBY_REG &= ((uint8)(~PM_SPC_PM_EN));
/* Restore global interrupt enable state */
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: CySpcReadData
****************************************************************************//**
* Reads data from the SPC.
*
* \param uint8 buffer:
* Address to store data read.
*
* \param uint8 size:
* Number of bytes to read from the SPC.
*
* \return
* uint8:
* The number of bytes read from the SPC.
*
*******************************************************************************/
uint8 CySpcReadData(uint8 buffer[], uint8 size)
{
uint8 i;
for(i = 0u; i < size; i++)
{
while(!CY_SPC_DATA_READY)
{
CyDelayUs(1u);
}
buffer[i] = CY_SPC_CPU_DATA_REG;
}
return(i);
}
/*******************************************************************************
* Function Name: CySpcLoadMultiByte
****************************************************************************//**
* Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array.
*
* \param uint8 array:
* Id of the array.
*
* \param uint16 address:
* Flash/eeprom addrress
*
* \param uint8* buffer:
* Data to load to the row latch
*
* \param uint16 number:
* Number bytes to load.
*
* \return
* CYRET_STARTED
* CYRET_CANCELED
* CYRET_LOCKED
* CYRET_BAD_PARAM
*
*******************************************************************************/
cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
{
cystatus status = CYRET_STARTED;
uint8 i;
/***************************************************************************
* Check if number is correct for array. Number must be less than
* 32 for Flash or less than 16 for EEPROM.
***************************************************************************/
if(((array < CY_SPC_LAST_FLASH_ARRAYID) && (size < 32u)) ||
((array > CY_SPC_LAST_FLASH_ARRAYID) && (size < 16u)))
{
if(CY_SPC_IDLE)
{
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_MULTI_BYTE);
CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_MULTI_BYTE;
if(CY_SPC_BUSY)
{
CY_SPC_CPU_DATA_REG = array;
CY_SPC_CPU_DATA_REG = 1u & HI8(address);
CY_SPC_CPU_DATA_REG = LO8(address);
CY_SPC_CPU_DATA_REG = ((uint8)(size - 1u));
for(i = 0u; i < size; i++)
{
CY_SPC_CPU_DATA_REG = buffer[i];
}
}
else
{
status = CYRET_CANCELED;
}
}
else
{
status = CYRET_LOCKED;
}
}
else
{
status = CYRET_BAD_PARAM;
}
return(status);
}
/*******************************************************************************
* Function Name: CySpcLoadRow
****************************************************************************//**
* Loads a row of data into the row latch of a Flash/EEPROM array.
*
* The buffer pointer should point to the data that should be written to the
* flash row directly (no data in ECC/flash will be preserved). It is Flash API
* responsibility to prepare data: the preserved data are copied from flash into
* array with the modified data.
*
* \param uint8 array:
* Id of the array.
*
* \param uint8* buffer:
* Data to be loaded to the row latch
*
* \param uint8 size:
* The number of data bytes that the SPC expects to be written. Depends on the
* type of the array and, if the array is Flash, whether ECC is being enabled
* or not. There are following values: flash row latch size with ECC enabled,
* flash row latch size with ECC disabled and EEPROM row latch size.
*
* \return
* CYRET_STARTED
* CYRET_CANCELED
* CYRET_LOCKED
*
*******************************************************************************/
cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size)
{
cystatus status = CYRET_STARTED;
uint16 i;
/* Make sure the SPC is ready to accept command */
if(CY_SPC_IDLE)
{
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);
CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;
/* Make sure the command was accepted */
if(CY_SPC_BUSY)
{
CY_SPC_CPU_DATA_REG = array;
for(i = 0u; i < size; i++)
{
CY_SPC_CPU_DATA_REG = buffer[i];
}
}
else
{
status = CYRET_CANCELED;
}
}
else
{
status = CYRET_LOCKED;
}
return(status);
}
/*******************************************************************************
* Function Name: CySpcLoadRowFull
****************************************************************************//**
* Loads a row of data into the row latch of a Flash/EEPROM array.
*
* The only data that are going to be changed should be passed. The function
* will handle unmodified data preservation based on DWR settings and input
* parameters.
*
* \param uint8 array:
* Id of the array.
*
* \param uint16 row:
* Flash row number to be loaded.
*
* \param uint8* buffer:
* Data to be loaded to the row latch
*
* \param uint8 size:
* The number of data bytes that the SPC expects to be written. Depends on the
* type of the array and, if the array is Flash, whether ECC is being enabled
* or not. There are following values: flash row latch size with ECC enabled,
* flash row latch size with ECC disabled and EEPROM row latch size.
*
* \return
* CYRET_STARTED
* CYRET_CANCELED
* CYRET_LOCKED
*
*******************************************************************************/
cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
{
cystatus status = CYRET_STARTED;
uint16 i;
#if (CYDEV_ECC_ENABLE == 0)
uint32 offset;
#endif /* (CYDEV_ECC_ENABLE == 0) */
/* Make sure the SPC is ready to accept command */
if(CY_SPC_IDLE)
{
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);
CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;
/* Make sure the command was accepted */
if(CY_SPC_BUSY)
{
CY_SPC_CPU_DATA_REG = array;
/*******************************************************************
* If "Enable Error Correcting Code (ECC)" and "Store Configuration
* Data in ECC" DWR options are disabled, ECC section is available
* for user data.
*******************************************************************/
#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
/*******************************************************************
* If size parameter equals size of the ECC row and selected array
* identification corresponds to the flash array (but not to EEPROM
* array) then data are going to be written to the ECC section.
* In this case flash data must be preserved. The flash data copied
* from flash data section to the SPC data register.
*******************************************************************/
if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
{
offset = CYDEV_FLS_BASE +
((uint32) array * CYDEV_FLS_SECTOR_SIZE) +
((uint32) row * CYDEV_FLS_ROW_SIZE );
for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
{
CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
}
}
#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
for(i = 0u; i < size; i++)
{
CY_SPC_CPU_DATA_REG = buffer[i];
}
/*******************************************************************
* If "Enable Error Correcting Code (ECC)" DWR option is disabled,
* ECC section can be used for storing device configuration data
* ("Store Configuration Data in ECC" DWR option is enabled) or for
* storing user data in the ECC section ("Store Configuration Data in
* ECC" DWR option is enabled). In both cases, the data in the ECC
* section must be preserved if flash data is written.
*******************************************************************/
#if (CYDEV_ECC_ENABLE == 0)
/*******************************************************************
* If size parameter equals size of the flash row and selected array
* identification corresponds to the flash array (but not to EEPROM
* array) then data are going to be written to the flash data
* section. In this case, ECC section data must be preserved.
* The ECC section data copied from ECC section to the SPC data
* register.
*******************************************************************/
if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
{
offset = CYDEV_ECC_BASE +
((uint32) array * CYDEV_ECC_SECTOR_SIZE) +
((uint32) row * CYDEV_ECC_ROW_SIZE );
for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
{
CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
}
}
#else
if(0u != row)
{
/* To remove unreferenced local variable warning */
}
#endif /* (CYDEV_ECC_ENABLE == 0) */
}
else
{
status = CYRET_CANCELED;
}
}
else
{
status = CYRET_LOCKED;
}
return(status);
}
/*******************************************************************************
* Function Name: CySpcWriteRow
****************************************************************************//**
* Erases then programs a row in Flash/EEPROM with data in row latch.
*
* \param uint8 array:
* Id of the array.
*
* \param uint16 address:
* flash/eeprom addrress
*
* \param uint8 tempPolarity:
* temperature polarity.
* \param 1: the Temp Magnitude is interpreted as a positive value
* \param 0: the Temp Magnitude is interpreted as a negative value
*
* \param uint8 tempMagnitude:
* temperature magnitude.
*
* \return
* CYRET_STARTED
* CYRET_CANCELED
* CYRET_LOCKED
*
*******************************************************************************/
cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
{
cystatus status = CYRET_STARTED;
/* Make sure the SPC is ready to accept command */
if(CY_SPC_IDLE)
{
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_WR_ROW);
CY_SPC_CPU_DATA_REG = CY_SPC_CMD_WR_ROW;
/* Make sure the command was accepted */
if(CY_SPC_BUSY)
{
CY_SPC_CPU_DATA_REG = array;
CY_SPC_CPU_DATA_REG = HI8(address);
CY_SPC_CPU_DATA_REG = LO8(address);
CY_SPC_CPU_DATA_REG = tempPolarity;
CY_SPC_CPU_DATA_REG = tempMagnitude;
}
else
{
status = CYRET_CANCELED;
}
}
else
{
status = CYRET_LOCKED;
}
return(status);
}
/*******************************************************************************
* Function Name: CySpcEraseSector
****************************************************************************//**
* Erases all data in the addressed sector (block of 64 rows).
*
* \param uint8 array:
* Id of the array.
*
* \param uint8 sectorNumber:
* Zero based sector number within Flash/EEPROM array
*
* \return
* CYRET_STARTED
* CYRET_CANCELED
* CYRET_LOCKED
*
*******************************************************************************/
cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber)
{
cystatus status = CYRET_STARTED;
/* Make sure the SPC is ready to accept command */
if(CY_SPC_IDLE)
{
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_SECTOR);
CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_SECTOR;
/* Make sure the command was accepted */
if(CY_SPC_BUSY)
{
CY_SPC_CPU_DATA_REG = array;
CY_SPC_CPU_DATA_REG = sectorNumber;
}
else
{
status = CYRET_CANCELED;
}
}
else
{
status = CYRET_LOCKED;
}
return(status);
}
/*******************************************************************************
* Function Name: CySpcGetTemp
****************************************************************************//**
* Returns the internal die temperature
*
* \param uint8 numSamples:
* Number of samples. Valid values are 1-5, resulting in 2 - 32 samples
* respectively.
*
* \param uint16 timerPeriod:
* Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits
* of 16 bit values are ignored.
*
* \param uint8 clkDivSelect:
* ADC ACLK clock divide value. Valid values are 2 - 225.
*
* \return
* CYRET_STARTED
* CYRET_CANCELED
* CYRET_LOCKED
*
*******************************************************************************/
cystatus CySpcGetTemp(uint8 numSamples)
{
cystatus status = CYRET_STARTED;
/* Make sure the SPC is ready to accept command */
if(CY_SPC_IDLE)
{
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_GET_TEMP);
CY_SPC_CPU_DATA_REG = CY_SPC_CMD_GET_TEMP;
/* Make sure the command was accepted */
if(CY_SPC_BUSY)
{
CY_SPC_CPU_DATA_REG = numSamples;
}
else
{
status = CYRET_CANCELED;
}
}
else
{
status = CYRET_LOCKED;
}
return(status);
}
/*******************************************************************************
* Function Name: CySpcLock
****************************************************************************//**
* Locks the SPC so it can not be used by someone else:
* - Saves wait-pipeline enable state and enable pipeline (PSoC5)
*
* \return
* CYRET_SUCCESS - if the resource was free.
* CYRET_LOCKED - if the SPC is in use.
*
*******************************************************************************/
cystatus CySpcLock(void)
{
cystatus status = CYRET_LOCKED;
uint8 interruptState;
/* Enter critical section */
interruptState = CyEnterCriticalSection();
if(CY_SPC_UNLOCKED == SpcLockState)
{
SpcLockState = CY_SPC_LOCKED;
status = CYRET_SUCCESS;
#if(CY_PSOC5)
if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS))
{
/* Enable pipeline registers */
CY_SPC_CPU_WAITPIPE_REG &= ((uint32)(~CY_SPC_CPU_WAITPIPE_BYPASS));
/* At least 2 NOP instructions are recommended */
CY_NOP;
CY_NOP;
CY_NOP;
spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS;
}
#endif /* (CY_PSOC5) */
}
/* Exit critical section */
CyExitCriticalSection(interruptState);
return(status);
}
/*******************************************************************************
* Function Name: CySpcUnlock
****************************************************************************//**
* Unlocks the SPC so it can be used by someone else:
* - Restores wait-pipeline enable state (PSoC5)
*
*******************************************************************************/
void CySpcUnlock(void)
{
uint8 interruptState;
/* Enter critical section */
interruptState = CyEnterCriticalSection();
/* Release the SPC object */
SpcLockState = CY_SPC_UNLOCKED;
#if(CY_PSOC5)
if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass)
{
/* Force to bypass pipeline registers */
CY_SPC_CPU_WAITPIPE_REG |= CY_SPC_CPU_WAITPIPE_BYPASS;
/* At least 2 NOP instructions are recommended */
CY_NOP;
CY_NOP;
CY_NOP;
spcWaitPipeBypass = 0u;
}
#endif /* (CY_PSOC5) */
/* Exit critical section */
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: CySpcGetAlgorithm
****************************************************************************//**
* Downloads SPC algorithm from SPC SROM into SRAM.
*
* \return
* CYRET_STARTED
* CYRET_LOCKED
*
*******************************************************************************/
cystatus CySpcGetAlgorithm(void)
{
cystatus status = CYRET_STARTED;
/* Make sure the SPC is ready to accept command */
if(CY_SPC_IDLE)
{
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM);
CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM;
}
else
{
status = CYRET_LOCKED;
}
return(status);
}
/* [] END OF FILE */

168
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h Executable file
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/***************************************************************************//**
* \file CySpc.c
* \version 5.50
*
* \brief Provides definitions for the System Performance Component API.
* The SPC functions are not meant to be called directly by the user
* application.
*
********************************************************************************
* \copyright
* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_BOOT_CYSPC_H)
#define CY_BOOT_CYSPC_H
#include "cytypes.h"
#include "CyLib.h"
#include "cydevice_trm.h"
/***************************************
* Global Variables
***************************************/
extern uint8 SpcLockState;
/***************************************
* Function Prototypes
***************************************/
void CySpcStart(void);
void CySpcStop(void);
uint8 CySpcReadData(uint8 buffer[], uint8 size);
cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
;
cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);
cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
;
cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
;
cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);
cystatus CySpcGetTemp(uint8 numSamples);
cystatus CySpcGetAlgorithm(void);
cystatus CySpcLock(void);
void CySpcUnlock(void);
/***************************************
* API Constants
***************************************/
#define CY_SPC_LOCKED (0x01u)
#define CY_SPC_UNLOCKED (0x00u)
/*******************************************************************************
* The Array ID indicates the unique ID of the SONOS array being accessed:
* - 0x00-0x3E : Flash Arrays
* - 0x3F : Selects all Flash arrays simultaneously
* - 0x40-0x7F : Embedded EEPROM Arrays
*******************************************************************************/
#define CY_SPC_FIRST_FLASH_ARRAYID (0x00u)
#define CY_SPC_LAST_FLASH_ARRAYID (0x3Fu)
#define CY_SPC_FIRST_EE_ARRAYID (0x40u)
#define CY_SPC_LAST_EE_ARRAYID (0x7Fu)
#define CY_SPC_STATUS_DATA_READY_MASK (0x01u)
#define CY_SPC_STATUS_IDLE_MASK (0x02u)
#define CY_SPC_STATUS_CODE_MASK (0xFCu)
#define CY_SPC_STATUS_CODE_SHIFT (0x02u)
/* Status codes for SPC. */
#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */
#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */
#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */
#define CY_SPC_STATUS_ARRAY_ASLEEP (0x03u) /* Addressed Array is Asleep */
#define CY_SPC_STATUS_EXTERN_ACCESS (0x04u) /* External Access Failure (SPC is not in external access mode) */
#define CY_SPC_STATUS_INVALID_NUMBER (0x05u) /* Invalid 'N' Value for given command */
#define CY_SPC_STATUS_TEST_MODE (0x06u) /* Test Mode Failure (SPC is not in test mode) */
#define CY_SPC_STATUS_ALG_CSUM (0x07u) /* Smart Write Algorithm Checksum Failure */
#define CY_SPC_STATUS_PARAM_CSUM (0x08u) /* Smart Write Parameter Checksum Failure */
#define CY_SPC_STATUS_PROTECTION (0x09u) /* Protection Check Failure */
#define CY_SPC_STATUS_ADDRESS_PARAM (0x0Au) /* Invalid Address parameter for the given command */
#define CY_SPC_STATUS_COMMAND_CODE (0x0Bu) /* Invalid Command Code */
#define CY_SPC_STATUS_ROW_ID (0x0Cu) /* Invalid Row ID parameter for given command */
#define CY_SPC_STATUS_TADC_INPUT (0x0Du) /* Invalid input value for Get Temp & Get ADC commands */
#define CY_SPC_STATUS_BUSY (0xFFu) /* SPC is busy */
#if(CY_PSOC5)
/* Wait-state pipeline */
#define CY_SPC_CPU_WAITPIPE_BYPASS ((uint32)0x01u)
#endif /* (CY_PSOC5) */
/***************************************
* Registers
***************************************/
/* SPC CPU Data Register */
#define CY_SPC_CPU_DATA_REG (* (reg8 *) CYREG_SPC_CPU_DATA )
#define CY_SPC_CPU_DATA_PTR ( (reg8 *) CYREG_SPC_CPU_DATA )
/* SPC Status Register */
#define CY_SPC_STATUS_REG (* (reg8 *) CYREG_SPC_SR )
#define CY_SPC_STATUS_PTR ( (reg8 *) CYREG_SPC_SR )
/* Active Power Mode Configuration Register 0 */
#define CY_SPC_PM_ACT_REG (* (reg8 *) CYREG_PM_ACT_CFG0 )
#define CY_SPC_PM_ACT_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 )
/* Standby Power Mode Configuration Register 0 */
#define CY_SPC_PM_STBY_REG (* (reg8 *) CYREG_PM_STBY_CFG0 )
#define CY_SPC_PM_STBY_PTR ( (reg8 *) CYREG_PM_STBY_CFG0 )
#if(CY_PSOC5)
/* Wait State Pipeline */
#define CY_SPC_CPU_WAITPIPE_REG (* (reg32 *) CYREG_PANTHER_WAITPIPE )
#define CY_SPC_CPU_WAITPIPE_PTR ( (reg32 *) CYREG_PANTHER_WAITPIPE )
#endif /* (CY_PSOC5) */
/***************************************
* Macros
***************************************/
#define CY_SPC_IDLE (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK))
#define CY_SPC_BUSY (0u == (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK))
#define CY_SPC_DATA_READY (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_DATA_READY_MASK))
/* SPC must be in idle state in order to obtain correct status */
#define CY_SPC_READ_STATUS (CY_SPC_IDLE ? \
((uint8)(CY_SPC_STATUS_REG >> CY_SPC_STATUS_CODE_SHIFT)) : \
((uint8) CY_SPC_STATUS_BUSY))
/*******************************************************************************
* The following code is OBSOLETE and must not be used.
*
* If the obsoleted macro definitions intended for use in the application use the
* following scheme, redefine your own versions of these definitions:
* #ifdef <OBSOLETED_DEFINE>
* #undef <OBSOLETED_DEFINE>
* #define <OBSOLETED_DEFINE> (<New Value>)
* #endif
*
* Note: Redefine obsoleted macro definitions with caution. They might still be
* used in the application and their modification might lead to unexpected
* consequences.
*******************************************************************************/
#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID)
#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID)
#define FIRST_EE_ARRAYID (CY_SPC_FIRST_EE_ARRAYID)
#define LAST_EE_ARRAYID (CY_SPC_LAST_EE_ARRAYID)
#define SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE)
#define SIZEOF_FLASH_ROW (CYDEV_FLS_ROW_SIZE)
#define SIZEOF_EEPROM_ROW (CYDEV_EEPROM_ROW_SIZE)
#endif /* (CY_BOOT_CYSPC_H) */
/* [] END OF FILE */

774
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c Executable file
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/*******************************************************************************
* File Name: Debug_Timer.c
* Version 2.70
*
* Description:
* The Timer component consists of a 8, 16, 24 or 32-bit timer with
* a selectable period between 2 and 2^Width - 1. The timer may free run
* or be used as a capture timer as well. The capture can be initiated
* by a positive or negative edge signal as well as via software.
* A trigger input can be programmed to enable the timer on rising edge
* falling edge, either edge or continous run.
* Interrupts may be generated due to a terminal count condition
* or a capture event.
*
* Note:
*
********************************************************************************
* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include "Debug_Timer.h"
uint8 Debug_Timer_initVar = 0u;
/*******************************************************************************
* Function Name: Debug_Timer_Init
********************************************************************************
*
* Summary:
* Initialize to the schematic state
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_Init(void)
{
#if(!Debug_Timer_UsingFixedFunction)
/* Interrupt State Backup for Critical Region*/
uint8 Debug_Timer_interruptState;
#endif /* Interrupt state back up for Fixed Function only */
#if (Debug_Timer_UsingFixedFunction)
/* Clear all bits but the enable bit (if it's already set) for Timer operation */
Debug_Timer_CONTROL &= Debug_Timer_CTRL_ENABLE;
/* Clear the mode bits for continuous run mode */
#if (CY_PSOC5A)
Debug_Timer_CONTROL2 &= ((uint8)(~Debug_Timer_CTRL_MODE_MASK));
#endif /* Clear bits in CONTROL2 only in PSOC5A */
#if (CY_PSOC3 || CY_PSOC5LP)
Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_MODE_MASK));
#endif /* CONTROL3 register exists only in PSoC3 OR PSoC5LP */
/* Check if One Shot mode is enabled i.e. RunMode !=0*/
#if (Debug_Timer_RunModeUsed != 0x0u)
/* Set 3rd bit of Control register to enable one shot mode */
Debug_Timer_CONTROL |= 0x04u;
#endif /* One Shot enabled only when RunModeUsed is not Continuous*/
#if (Debug_Timer_RunModeUsed == 2)
#if (CY_PSOC5A)
/* Set last 2 bits of control2 register if one shot(halt on
interrupt) is enabled*/
Debug_Timer_CONTROL2 |= 0x03u;
#endif /* Set One-Shot Halt on Interrupt bit in CONTROL2 for PSoC5A */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Set last 2 bits of control3 register if one shot(halt on
interrupt) is enabled*/
Debug_Timer_CONTROL3 |= 0x03u;
#endif /* Set One-Shot Halt on Interrupt bit in CONTROL3 for PSoC3 or PSoC5LP */
#endif /* Remove section if One Shot Halt on Interrupt is not enabled */
#if (Debug_Timer_UsingHWEnable != 0)
#if (CY_PSOC5A)
/* Set the default Run Mode of the Timer to Continuous */
Debug_Timer_CONTROL2 |= Debug_Timer_CTRL_MODE_PULSEWIDTH;
#endif /* Set Continuous Run Mode in CONTROL2 for PSoC5A */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Clear and Set ROD and COD bits of CFG2 register */
Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_RCOD_MASK));
Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_RCOD;
/* Clear and Enable the HW enable bit in CFG2 register */
Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_ENBL_MASK));
Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_ENBL;
/* Set the default Run Mode of the Timer to Continuous */
Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_MODE_CONTINUOUS;
#endif /* Set Continuous Run Mode in CONTROL3 for PSoC3ES3 or PSoC5A */
#endif /* Configure Run Mode with hardware enable */
/* Clear and Set SYNCTC and SYNCCMP bits of RT1 register */
Debug_Timer_RT1 &= ((uint8)(~Debug_Timer_RT1_MASK));
Debug_Timer_RT1 |= Debug_Timer_SYNC;
/*Enable DSI Sync all all inputs of the Timer*/
Debug_Timer_RT1 &= ((uint8)(~Debug_Timer_SYNCDSI_MASK));
Debug_Timer_RT1 |= Debug_Timer_SYNCDSI_EN;
/* Set the IRQ to use the status register interrupts */
Debug_Timer_CONTROL2 |= Debug_Timer_CTRL2_IRQ_SEL;
#endif /* Configuring registers of fixed function implementation */
/* Set Initial values from Configuration */
Debug_Timer_WritePeriod(Debug_Timer_INIT_PERIOD);
Debug_Timer_WriteCounter(Debug_Timer_INIT_PERIOD);
#if (Debug_Timer_UsingHWCaptureCounter)/* Capture counter is enabled */
Debug_Timer_CAPTURE_COUNT_CTRL |= Debug_Timer_CNTR_ENABLE;
Debug_Timer_SetCaptureCount(Debug_Timer_INIT_CAPTURE_COUNT);
#endif /* Configure capture counter value */
#if (!Debug_Timer_UsingFixedFunction)
#if (Debug_Timer_SoftwareCaptureMode)
Debug_Timer_SetCaptureMode(Debug_Timer_INIT_CAPTURE_MODE);
#endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */
#if (Debug_Timer_SoftwareTriggerMode)
#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE))
{
Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE);
}
#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
#endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */
/* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
/* Enter Critical Region*/
Debug_Timer_interruptState = CyEnterCriticalSection();
/* Use the interrupt output of the status register for IRQ output */
Debug_Timer_STATUS_AUX_CTRL |= Debug_Timer_STATUS_ACTL_INT_EN_MASK;
/* Exit Critical Region*/
CyExitCriticalSection(Debug_Timer_interruptState);
#if (Debug_Timer_EnableTriggerMode)
Debug_Timer_EnableTrigger();
#endif /* Set Trigger enable bit for UDB implementation in the control register*/
#if (Debug_Timer_InterruptOnCaptureCount && !Debug_Timer_UDB_CONTROL_REG_REMOVED)
Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT);
#endif /* Set interrupt count in UDB implementation if interrupt count feature is checked.*/
Debug_Timer_ClearFIFO();
#endif /* Configure additional features of UDB implementation */
Debug_Timer_SetInterruptMode(Debug_Timer_INIT_INTERRUPT_MODE);
}
/*******************************************************************************
* Function Name: Debug_Timer_Enable
********************************************************************************
*
* Summary:
* Enable the Timer
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_Enable(void)
{
/* Globally Enable the Fixed Function Block chosen */
#if (Debug_Timer_UsingFixedFunction)
Debug_Timer_GLOBAL_ENABLE |= Debug_Timer_BLOCK_EN_MASK;
Debug_Timer_GLOBAL_STBY_ENABLE |= Debug_Timer_BLOCK_STBY_EN_MASK;
#endif /* Set Enable bit for enabling Fixed function timer*/
/* Remove assignment if control register is removed */
#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
Debug_Timer_CONTROL |= Debug_Timer_CTRL_ENABLE;
#endif /* Remove assignment if control register is removed */
}
/*******************************************************************************
* Function Name: Debug_Timer_Start
********************************************************************************
*
* Summary:
* The start function initializes the timer with the default values, the
* enables the timerto begin counting. It does not enable interrupts,
* the EnableInt command should be called if interrupt generation is required.
*
* Parameters:
* void
*
* Return:
* void
*
* Global variables:
* Debug_Timer_initVar: Is modified when this function is called for the
* first time. Is used to ensure that initialization happens only once.
*
*******************************************************************************/
void Debug_Timer_Start(void)
{
if(Debug_Timer_initVar == 0u)
{
Debug_Timer_Init();
Debug_Timer_initVar = 1u; /* Clear this bit for Initialization */
}
/* Enable the Timer */
Debug_Timer_Enable();
}
/*******************************************************************************
* Function Name: Debug_Timer_Stop
********************************************************************************
*
* Summary:
* The stop function halts the timer, but does not change any modes or disable
* interrupts.
*
* Parameters:
* void
*
* Return:
* void
*
* Side Effects: If the Enable mode is set to Hardware only then this function
* has no effect on the operation of the timer.
*
*******************************************************************************/
void Debug_Timer_Stop(void)
{
/* Disable Timer */
#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_ENABLE));
#endif /* Remove assignment if control register is removed */
/* Globally disable the Fixed Function Block chosen */
#if (Debug_Timer_UsingFixedFunction)
Debug_Timer_GLOBAL_ENABLE &= ((uint8)(~Debug_Timer_BLOCK_EN_MASK));
Debug_Timer_GLOBAL_STBY_ENABLE &= ((uint8)(~Debug_Timer_BLOCK_STBY_EN_MASK));
#endif /* Disable global enable for the Timer Fixed function block to stop the Timer*/
}
/*******************************************************************************
* Function Name: Debug_Timer_SetInterruptMode
********************************************************************************
*
* Summary:
* This function selects which of the interrupt inputs may cause an interrupt.
* The twosources are caputure and terminal. One, both or neither may
* be selected.
*
* Parameters:
* interruptMode: This parameter is used to enable interrups on either/or
* terminal count or capture.
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_SetInterruptMode(uint8 interruptMode)
{
Debug_Timer_STATUS_MASK = interruptMode;
}
/*******************************************************************************
* Function Name: Debug_Timer_SoftwareCapture
********************************************************************************
*
* Summary:
* This function forces a capture independent of the capture signal.
*
* Parameters:
* void
*
* Return:
* void
*
* Side Effects:
* An existing hardware capture could be overwritten.
*
*******************************************************************************/
void Debug_Timer_SoftwareCapture(void)
{
/* Generate a software capture by reading the counter register */
#if(Debug_Timer_UsingFixedFunction)
(void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
#else
(void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
#endif/* (Debug_Timer_UsingFixedFunction) */
/* Capture Data is now in the FIFO */
}
/*******************************************************************************
* Function Name: Debug_Timer_ReadStatusRegister
********************************************************************************
*
* Summary:
* Reads the status register and returns it's state. This function should use
* defined types for the bit-field information as the bits in this register may
* be permuteable.
*
* Parameters:
* void
*
* Return:
* The contents of the status register
*
* Side Effects:
* Status register bits may be clear on read.
*
*******************************************************************************/
uint8 Debug_Timer_ReadStatusRegister(void)
{
return (Debug_Timer_STATUS);
}
#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove API if control register is unused */
/*******************************************************************************
* Function Name: Debug_Timer_ReadControlRegister
********************************************************************************
*
* Summary:
* Reads the control register and returns it's value.
*
* Parameters:
* void
*
* Return:
* The contents of the control register
*
*******************************************************************************/
uint8 Debug_Timer_ReadControlRegister(void)
{
#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
return ((uint8)Debug_Timer_CONTROL);
#else
return (0);
#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
}
/*******************************************************************************
* Function Name: Debug_Timer_WriteControlRegister
********************************************************************************
*
* Summary:
* Sets the bit-field of the control register.
*
* Parameters:
* control: The contents of the control register
*
* Return:
*
*******************************************************************************/
void Debug_Timer_WriteControlRegister(uint8 control)
{
#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
Debug_Timer_CONTROL = control;
#else
control = 0u;
#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
}
#endif /* Remove API if control register is unused */
/*******************************************************************************
* Function Name: Debug_Timer_ReadPeriod
********************************************************************************
*
* Summary:
* This function returns the current value of the Period.
*
* Parameters:
* void
*
* Return:
* The present value of the counter.
*
*******************************************************************************/
uint16 Debug_Timer_ReadPeriod(void)
{
#if(Debug_Timer_UsingFixedFunction)
return ((uint16)CY_GET_REG16(Debug_Timer_PERIOD_LSB_PTR));
#else
return (CY_GET_REG16(Debug_Timer_PERIOD_LSB_PTR));
#endif /* (Debug_Timer_UsingFixedFunction) */
}
/*******************************************************************************
* Function Name: Debug_Timer_WritePeriod
********************************************************************************
*
* Summary:
* This function is used to change the period of the counter. The new period
* will be loaded the next time terminal count is detected.
*
* Parameters:
* period: This value may be between 1 and (2^Resolution)-1. A value of 0 will
* result in the counter remaining at zero.
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_WritePeriod(uint16 period)
{
#if(Debug_Timer_UsingFixedFunction)
uint16 period_temp = (uint16)period;
CY_SET_REG16(Debug_Timer_PERIOD_LSB_PTR, period_temp);
#else
CY_SET_REG16(Debug_Timer_PERIOD_LSB_PTR, period);
#endif /*Write Period value with appropriate resolution suffix depending on UDB or fixed function implementation */
}
/*******************************************************************************
* Function Name: Debug_Timer_ReadCapture
********************************************************************************
*
* Summary:
* This function returns the last value captured.
*
* Parameters:
* void
*
* Return:
* Present Capture value.
*
*******************************************************************************/
uint16 Debug_Timer_ReadCapture(void)
{
#if(Debug_Timer_UsingFixedFunction)
return ((uint16)CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
#else
return (CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
#endif /* (Debug_Timer_UsingFixedFunction) */
}
/*******************************************************************************
* Function Name: Debug_Timer_WriteCounter
********************************************************************************
*
* Summary:
* This funtion is used to set the counter to a specific value
*
* Parameters:
* counter: New counter value.
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_WriteCounter(uint16 counter)
{
#if(Debug_Timer_UsingFixedFunction)
/* This functionality is removed until a FixedFunction HW update to
* allow this register to be written
*/
CY_SET_REG16(Debug_Timer_COUNTER_LSB_PTR, (uint16)counter);
#else
CY_SET_REG16(Debug_Timer_COUNTER_LSB_PTR, counter);
#endif /* Set Write Counter only for the UDB implementation (Write Counter not available in fixed function Timer */
}
/*******************************************************************************
* Function Name: Debug_Timer_ReadCounter
********************************************************************************
*
* Summary:
* This function returns the current counter value.
*
* Parameters:
* void
*
* Return:
* Present compare value.
*
*******************************************************************************/
uint16 Debug_Timer_ReadCounter(void)
{
/* Force capture by reading Accumulator */
/* Must first do a software capture to be able to read the counter */
/* It is up to the user code to make sure there isn't already captured data in the FIFO */
#if(Debug_Timer_UsingFixedFunction)
(void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
#else
(void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
#endif/* (Debug_Timer_UsingFixedFunction) */
/* Read the data from the FIFO (or capture register for Fixed Function)*/
#if(Debug_Timer_UsingFixedFunction)
return ((uint16)CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
#else
return (CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
#endif /* (Debug_Timer_UsingFixedFunction) */
}
#if(!Debug_Timer_UsingFixedFunction) /* UDB Specific Functions */
/*******************************************************************************
* The functions below this point are only available using the UDB
* implementation. If a feature is selected, then the API is enabled.
******************************************************************************/
#if (Debug_Timer_SoftwareCaptureMode)
/*******************************************************************************
* Function Name: Debug_Timer_SetCaptureMode
********************************************************************************
*
* Summary:
* This function sets the capture mode to either rising or falling edge.
*
* Parameters:
* captureMode: This parameter sets the capture mode of the UDB capture feature
* The parameter values are defined using the
* #define Debug_Timer__B_TIMER__CM_NONE 0
#define Debug_Timer__B_TIMER__CM_RISINGEDGE 1
#define Debug_Timer__B_TIMER__CM_FALLINGEDGE 2
#define Debug_Timer__B_TIMER__CM_EITHEREDGE 3
#define Debug_Timer__B_TIMER__CM_SOFTWARE 4
identifiers
* The following are the possible values of the parameter
* Debug_Timer__B_TIMER__CM_NONE - Set Capture mode to None
* Debug_Timer__B_TIMER__CM_RISINGEDGE - Rising edge of Capture input
* Debug_Timer__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input
* Debug_Timer__B_TIMER__CM_EITHEREDGE - Either edge of Capture input
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_SetCaptureMode(uint8 captureMode)
{
/* This must only set to two bits of the control register associated */
captureMode = ((uint8)((uint8)captureMode << Debug_Timer_CTRL_CAP_MODE_SHIFT));
captureMode &= (Debug_Timer_CTRL_CAP_MODE_MASK);
#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
/* Clear the Current Setting */
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK));
/* Write The New Setting */
Debug_Timer_CONTROL |= captureMode;
#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
}
#endif /* Remove API if Capture Mode is not Software Controlled */
#if (Debug_Timer_SoftwareTriggerMode)
/*******************************************************************************
* Function Name: Debug_Timer_SetTriggerMode
********************************************************************************
*
* Summary:
* This function sets the trigger input mode
*
* Parameters:
* triggerMode: Pass one of the pre-defined Trigger Modes (except Software)
#define Debug_Timer__B_TIMER__TM_NONE 0x00u
#define Debug_Timer__B_TIMER__TM_RISINGEDGE 0x04u
#define Debug_Timer__B_TIMER__TM_FALLINGEDGE 0x08u
#define Debug_Timer__B_TIMER__TM_EITHEREDGE 0x0Cu
#define Debug_Timer__B_TIMER__TM_SOFTWARE 0x10u
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_SetTriggerMode(uint8 triggerMode)
{
/* This must only set to two bits of the control register associated */
triggerMode &= Debug_Timer_CTRL_TRIG_MODE_MASK;
#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove assignment if control register is removed */
/* Clear the Current Setting */
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK));
/* Write The New Setting */
Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE);
#endif /* Remove code section if control register is not used */
}
#endif /* Remove API if Trigger Mode is not Software Controlled */
#if (Debug_Timer_EnableTriggerMode)
/*******************************************************************************
* Function Name: Debug_Timer_EnableTrigger
********************************************************************************
*
* Summary:
* Sets the control bit enabling Hardware Trigger mode
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_EnableTrigger(void)
{
#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove assignment if control register is removed */
Debug_Timer_CONTROL |= Debug_Timer_CTRL_TRIG_EN;
#endif /* Remove code section if control register is not used */
}
/*******************************************************************************
* Function Name: Debug_Timer_DisableTrigger
********************************************************************************
*
* Summary:
* Clears the control bit enabling Hardware Trigger mode
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_DisableTrigger(void)
{
#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED ) /* Remove assignment if control register is removed */
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_EN));
#endif /* Remove code section if control register is not used */
}
#endif /* Remove API is Trigger Mode is set to None */
#if(Debug_Timer_InterruptOnCaptureCount)
/*******************************************************************************
* Function Name: Debug_Timer_SetInterruptCount
********************************************************************************
*
* Summary:
* This function sets the capture count before an interrupt is triggered.
*
* Parameters:
* interruptCount: A value between 0 and 3 is valid. If the value is 0, then
* an interrupt will occur each time a capture occurs.
* A value of 1 to 3 will cause the interrupt
* to delay by the same number of captures.
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_SetInterruptCount(uint8 interruptCount)
{
/* This must only set to two bits of the control register associated */
interruptCount &= Debug_Timer_CTRL_INTCNT_MASK;
#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
/* Clear the Current Setting */
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK));
/* Write The New Setting */
Debug_Timer_CONTROL |= interruptCount;
#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
}
#endif /* Debug_Timer_InterruptOnCaptureCount */
#if (Debug_Timer_UsingHWCaptureCounter)
/*******************************************************************************
* Function Name: Debug_Timer_SetCaptureCount
********************************************************************************
*
* Summary:
* This function sets the capture count
*
* Parameters:
* captureCount: A value between 2 and 127 inclusive is valid. A value of 1
* to 127 will cause the interrupt to delay by the same number of
* captures.
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_SetCaptureCount(uint8 captureCount)
{
Debug_Timer_CAP_COUNT = captureCount;
}
/*******************************************************************************
* Function Name: Debug_Timer_ReadCaptureCount
********************************************************************************
*
* Summary:
* This function reads the capture count setting
*
* Parameters:
* void
*
* Return:
* Returns the Capture Count Setting
*
*******************************************************************************/
uint8 Debug_Timer_ReadCaptureCount(void)
{
return ((uint8)Debug_Timer_CAP_COUNT);
}
#endif /* Debug_Timer_UsingHWCaptureCounter */
/*******************************************************************************
* Function Name: Debug_Timer_ClearFIFO
********************************************************************************
*
* Summary:
* This function clears all capture data from the capture FIFO
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void Debug_Timer_ClearFIFO(void)
{
while(0u != (Debug_Timer_ReadStatusRegister() & Debug_Timer_STATUS_FIFONEMP))
{
(void)Debug_Timer_ReadCapture();
}
}
#endif /* UDB Specific Functions */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: Debug_Timer.h
* Version 2.70
*
* Description:
* Contains the function prototypes and constants available to the timer
* user module.
*
* Note:
* None
*
********************************************************************************
* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#if !defined(CY_Timer_v2_60_Debug_Timer_H)
#define CY_Timer_v2_60_Debug_Timer_H
#include "cytypes.h"
#include "cyfitter.h"
#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */
extern uint8 Debug_Timer_initVar;
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
#error Component Timer_v2_70 requires cy_boot v3.0 or later
#endif /* (CY_ PSOC5LP) */
/**************************************
* Parameter Defaults
**************************************/
#define Debug_Timer_Resolution 16u
#define Debug_Timer_UsingFixedFunction 1u
#define Debug_Timer_UsingHWCaptureCounter 0u
#define Debug_Timer_SoftwareCaptureMode 0u
#define Debug_Timer_SoftwareTriggerMode 0u
#define Debug_Timer_UsingHWEnable 0u
#define Debug_Timer_EnableTriggerMode 0u
#define Debug_Timer_InterruptOnCaptureCount 0u
#define Debug_Timer_RunModeUsed 0u
#define Debug_Timer_ControlRegRemoved 0u
#if defined(Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG)
#define Debug_Timer_UDB_CONTROL_REG_REMOVED (0u)
#elif (Debug_Timer_UsingFixedFunction)
#define Debug_Timer_UDB_CONTROL_REG_REMOVED (0u)
#else
#define Debug_Timer_UDB_CONTROL_REG_REMOVED (1u)
#endif /* End Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG */
/***************************************
* Type defines
***************************************/
/**************************************************************************
* Sleep Wakeup Backup structure for Timer Component
*************************************************************************/
typedef struct
{
uint8 TimerEnableState;
#if(!Debug_Timer_UsingFixedFunction)
uint16 TimerUdb;
uint8 InterruptMaskValue;
#if (Debug_Timer_UsingHWCaptureCounter)
uint8 TimerCaptureCounter;
#endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
uint8 TimerControlRegister;
#endif /* variable declaration for backing up enable state of the Timer */
#endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */
}Debug_Timer_backupStruct;
/***************************************
* Function Prototypes
***************************************/
void Debug_Timer_Start(void) ;
void Debug_Timer_Stop(void) ;
void Debug_Timer_SetInterruptMode(uint8 interruptMode) ;
uint8 Debug_Timer_ReadStatusRegister(void) ;
/* Deprecated function. Do not use this in future. Retained for backward compatibility */
#define Debug_Timer_GetInterruptSource() Debug_Timer_ReadStatusRegister()
#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
uint8 Debug_Timer_ReadControlRegister(void) ;
void Debug_Timer_WriteControlRegister(uint8 control) ;
#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
uint16 Debug_Timer_ReadPeriod(void) ;
void Debug_Timer_WritePeriod(uint16 period) ;
uint16 Debug_Timer_ReadCounter(void) ;
void Debug_Timer_WriteCounter(uint16 counter) ;
uint16 Debug_Timer_ReadCapture(void) ;
void Debug_Timer_SoftwareCapture(void) ;
#if(!Debug_Timer_UsingFixedFunction) /* UDB Prototypes */
#if (Debug_Timer_SoftwareCaptureMode)
void Debug_Timer_SetCaptureMode(uint8 captureMode) ;
#endif /* (!Debug_Timer_UsingFixedFunction) */
#if (Debug_Timer_SoftwareTriggerMode)
void Debug_Timer_SetTriggerMode(uint8 triggerMode) ;
#endif /* (Debug_Timer_SoftwareTriggerMode) */
#if (Debug_Timer_EnableTriggerMode)
void Debug_Timer_EnableTrigger(void) ;
void Debug_Timer_DisableTrigger(void) ;
#endif /* (Debug_Timer_EnableTriggerMode) */
#if(Debug_Timer_InterruptOnCaptureCount)
void Debug_Timer_SetInterruptCount(uint8 interruptCount) ;
#endif /* (Debug_Timer_InterruptOnCaptureCount) */
#if (Debug_Timer_UsingHWCaptureCounter)
void Debug_Timer_SetCaptureCount(uint8 captureCount) ;
uint8 Debug_Timer_ReadCaptureCount(void) ;
#endif /* (Debug_Timer_UsingHWCaptureCounter) */
void Debug_Timer_ClearFIFO(void) ;
#endif /* UDB Prototypes */
/* Sleep Retention APIs */
void Debug_Timer_Init(void) ;
void Debug_Timer_Enable(void) ;
void Debug_Timer_SaveConfig(void) ;
void Debug_Timer_RestoreConfig(void) ;
void Debug_Timer_Sleep(void) ;
void Debug_Timer_Wakeup(void) ;
/***************************************
* Enumerated Types and Parameters
***************************************/
/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */
#define Debug_Timer__B_TIMER__CM_NONE 0
#define Debug_Timer__B_TIMER__CM_RISINGEDGE 1
#define Debug_Timer__B_TIMER__CM_FALLINGEDGE 2
#define Debug_Timer__B_TIMER__CM_EITHEREDGE 3
#define Debug_Timer__B_TIMER__CM_SOFTWARE 4
/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */
#define Debug_Timer__B_TIMER__TM_NONE 0x00u
#define Debug_Timer__B_TIMER__TM_RISINGEDGE 0x04u
#define Debug_Timer__B_TIMER__TM_FALLINGEDGE 0x08u
#define Debug_Timer__B_TIMER__TM_EITHEREDGE 0x0Cu
#define Debug_Timer__B_TIMER__TM_SOFTWARE 0x10u
/***************************************
* Initialial Parameter Constants
***************************************/
#define Debug_Timer_INIT_PERIOD 31999u
#define Debug_Timer_INIT_CAPTURE_MODE ((uint8)((uint8)0u << Debug_Timer_CTRL_CAP_MODE_SHIFT))
#define Debug_Timer_INIT_TRIGGER_MODE ((uint8)((uint8)0u << Debug_Timer_CTRL_TRIG_MODE_SHIFT))
#if (Debug_Timer_UsingFixedFunction)
#define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \
((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)))
#else
#define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \
((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)) | \
((uint8)((uint8)0 << Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT)))
#endif /* (Debug_Timer_UsingFixedFunction) */
#define Debug_Timer_INIT_CAPTURE_COUNT (2u)
#define Debug_Timer_INIT_INT_CAPTURE_COUNT ((uint8)((uint8)(1u - 1u) << Debug_Timer_CTRL_INTCNT_SHIFT))
/***************************************
* Registers
***************************************/
#if (Debug_Timer_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */
/***************************************
* Fixed Function Registers
***************************************/
#define Debug_Timer_STATUS (*(reg8 *) Debug_Timer_TimerHW__SR0 )
/* In Fixed Function Block Status and Mask are the same register */
#define Debug_Timer_STATUS_MASK (*(reg8 *) Debug_Timer_TimerHW__SR0 )
#define Debug_Timer_CONTROL (*(reg8 *) Debug_Timer_TimerHW__CFG0)
#define Debug_Timer_CONTROL2 (*(reg8 *) Debug_Timer_TimerHW__CFG1)
#define Debug_Timer_CONTROL2_PTR ( (reg8 *) Debug_Timer_TimerHW__CFG1)
#define Debug_Timer_RT1 (*(reg8 *) Debug_Timer_TimerHW__RT1)
#define Debug_Timer_RT1_PTR ( (reg8 *) Debug_Timer_TimerHW__RT1)
#if (CY_PSOC3 || CY_PSOC5LP)
#define Debug_Timer_CONTROL3 (*(reg8 *) Debug_Timer_TimerHW__CFG2)
#define Debug_Timer_CONTROL3_PTR ( (reg8 *) Debug_Timer_TimerHW__CFG2)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#define Debug_Timer_GLOBAL_ENABLE (*(reg8 *) Debug_Timer_TimerHW__PM_ACT_CFG)
#define Debug_Timer_GLOBAL_STBY_ENABLE (*(reg8 *) Debug_Timer_TimerHW__PM_STBY_CFG)
#define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerHW__CAP0 )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__CAP0 )
#define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerHW__PER0 )
#define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__PER0 )
#define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerHW__CNT_CMP0 )
#define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__CNT_CMP0 )
/***************************************
* Register Constants
***************************************/
/* Fixed Function Block Chosen */
#define Debug_Timer_BLOCK_EN_MASK Debug_Timer_TimerHW__PM_ACT_MSK
#define Debug_Timer_BLOCK_STBY_EN_MASK Debug_Timer_TimerHW__PM_STBY_MSK
/* Control Register Bit Locations */
/* Interrupt Count - Not valid for Fixed Function Block */
#define Debug_Timer_CTRL_INTCNT_SHIFT 0x00u
/* Trigger Polarity - Not valid for Fixed Function Block */
#define Debug_Timer_CTRL_TRIG_MODE_SHIFT 0x00u
/* Trigger Enable - Not valid for Fixed Function Block */
#define Debug_Timer_CTRL_TRIG_EN_SHIFT 0x00u
/* Capture Polarity - Not valid for Fixed Function Block */
#define Debug_Timer_CTRL_CAP_MODE_SHIFT 0x00u
/* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */
#define Debug_Timer_CTRL_ENABLE_SHIFT 0x00u
/* Control Register Bit Masks */
#define Debug_Timer_CTRL_ENABLE ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT))
/* Control2 Register Bit Masks */
/* As defined in Register Map, Part of the TMRX_CFG1 register */
#define Debug_Timer_CTRL2_IRQ_SEL_SHIFT 0x00u
#define Debug_Timer_CTRL2_IRQ_SEL ((uint8)((uint8)0x01u << Debug_Timer_CTRL2_IRQ_SEL_SHIFT))
#if (CY_PSOC5A)
/* Use CFG1 Mode bits to set run mode */
/* As defined by Verilog Implementation */
#define Debug_Timer_CTRL_MODE_SHIFT 0x01u
#define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Control3 Register Bit Locations */
#define Debug_Timer_CTRL_RCOD_SHIFT 0x02u
#define Debug_Timer_CTRL_ENBL_SHIFT 0x00u
#define Debug_Timer_CTRL_MODE_SHIFT 0x00u
/* Control3 Register Bit Masks */
#define Debug_Timer_CTRL_RCOD_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */
#define Debug_Timer_CTRL_ENBL_MASK ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */
#define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_MODE_SHIFT)) /* Run mode bit mask */
#define Debug_Timer_CTRL_RCOD ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT))
#define Debug_Timer_CTRL_ENBL ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT))
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */
#define Debug_Timer_RT1_SHIFT 0x04u
/* Sync TC and CMP bit masks */
#define Debug_Timer_RT1_MASK ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT))
#define Debug_Timer_SYNC ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT))
#define Debug_Timer_SYNCDSI_SHIFT 0x00u
/* Sync all DSI inputs with Mask */
#define Debug_Timer_SYNCDSI_MASK ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT))
/* Sync all DSI inputs */
#define Debug_Timer_SYNCDSI_EN ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT))
#define Debug_Timer_CTRL_MODE_PULSEWIDTH ((uint8)((uint8)0x01u << Debug_Timer_CTRL_MODE_SHIFT))
#define Debug_Timer_CTRL_MODE_PERIOD ((uint8)((uint8)0x02u << Debug_Timer_CTRL_MODE_SHIFT))
#define Debug_Timer_CTRL_MODE_CONTINUOUS ((uint8)((uint8)0x00u << Debug_Timer_CTRL_MODE_SHIFT))
/* Status Register Bit Locations */
/* As defined in Register Map, part of TMRX_SR0 register */
#define Debug_Timer_STATUS_TC_SHIFT 0x07u
/* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
#define Debug_Timer_STATUS_CAPTURE_SHIFT 0x06u
/* As defined in Register Map, part of TMRX_SR0 register */
#define Debug_Timer_STATUS_TC_INT_MASK_SHIFT (Debug_Timer_STATUS_TC_SHIFT - 0x04u)
/* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
#define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT (Debug_Timer_STATUS_CAPTURE_SHIFT - 0x04u)
/* Status Register Bit Masks */
#define Debug_Timer_STATUS_TC ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
#define Debug_Timer_STATUS_CAPTURE ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
/* Interrupt Enable Bit-Mask for interrupt on TC */
#define Debug_Timer_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT))
/* Interrupt Enable Bit-Mask for interrupt on Capture */
#define Debug_Timer_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT))
#else /* UDB Registers and Register Constants */
/***************************************
* UDB Registers
***************************************/
#define Debug_Timer_STATUS (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_REG )
#define Debug_Timer_STATUS_MASK (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__MASK_REG)
#define Debug_Timer_STATUS_AUX_CTRL (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG)
#define Debug_Timer_CONTROL (* (reg8 *) Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG )
#if(Debug_Timer_Resolution <= 8u) /* 8-bit Timer */
#define Debug_Timer_CAPTURE_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_PERIOD_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_PERIOD_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_COUNTER_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#define Debug_Timer_COUNTER_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#elif(Debug_Timer_Resolution <= 16u) /* 8-bit Timer */
#if(CY_PSOC3) /* 8-bit addres space */
#define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#else /* 16-bit address space */
#define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
#define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
#define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
#define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
#define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
#endif /* CY_PSOC3 */
#elif(Debug_Timer_Resolution <= 24u)/* 24-bit Timer */
#define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#else /* 32-bit Timer */
#if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */
#define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
#define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
#define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#else /* 32-bit address space */
#define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
#define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
#define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
#define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
#define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
#define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
#endif /* CY_PSOC3 || CY_PSOC5 */
#endif
#define Debug_Timer_COUNTER_LSB_PTR_8BIT ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
#if (Debug_Timer_UsingHWCaptureCounter)
#define Debug_Timer_CAP_COUNT (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
#define Debug_Timer_CAP_COUNT_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
#define Debug_Timer_CAPTURE_COUNT_CTRL (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
#define Debug_Timer_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
#endif /* (Debug_Timer_UsingHWCaptureCounter) */
/***************************************
* Register Constants
***************************************/
/* Control Register Bit Locations */
#define Debug_Timer_CTRL_INTCNT_SHIFT 0x00u /* As defined by Verilog Implementation */
#define Debug_Timer_CTRL_TRIG_MODE_SHIFT 0x02u /* As defined by Verilog Implementation */
#define Debug_Timer_CTRL_TRIG_EN_SHIFT 0x04u /* As defined by Verilog Implementation */
#define Debug_Timer_CTRL_CAP_MODE_SHIFT 0x05u /* As defined by Verilog Implementation */
#define Debug_Timer_CTRL_ENABLE_SHIFT 0x07u /* As defined by Verilog Implementation */
/* Control Register Bit Masks */
#define Debug_Timer_CTRL_INTCNT_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_INTCNT_SHIFT))
#define Debug_Timer_CTRL_TRIG_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_TRIG_MODE_SHIFT))
#define Debug_Timer_CTRL_TRIG_EN ((uint8)((uint8)0x01u << Debug_Timer_CTRL_TRIG_EN_SHIFT))
#define Debug_Timer_CTRL_CAP_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_CAP_MODE_SHIFT))
#define Debug_Timer_CTRL_ENABLE ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT))
/* Bit Counter (7-bit) Control Register Bit Definitions */
/* As defined by the Register map for the AUX Control Register */
#define Debug_Timer_CNTR_ENABLE 0x20u
/* Status Register Bit Locations */
#define Debug_Timer_STATUS_TC_SHIFT 0x00u /* As defined by Verilog Implementation */
#define Debug_Timer_STATUS_CAPTURE_SHIFT 0x01u /* As defined by Verilog Implementation */
#define Debug_Timer_STATUS_TC_INT_MASK_SHIFT Debug_Timer_STATUS_TC_SHIFT
#define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT Debug_Timer_STATUS_CAPTURE_SHIFT
#define Debug_Timer_STATUS_FIFOFULL_SHIFT 0x02u /* As defined by Verilog Implementation */
#define Debug_Timer_STATUS_FIFONEMP_SHIFT 0x03u /* As defined by Verilog Implementation */
#define Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT Debug_Timer_STATUS_FIFOFULL_SHIFT
/* Status Register Bit Masks */
/* Sticky TC Event Bit-Mask */
#define Debug_Timer_STATUS_TC ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
/* Sticky Capture Event Bit-Mask */
#define Debug_Timer_STATUS_CAPTURE ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
/* Interrupt Enable Bit-Mask */
#define Debug_Timer_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
/* Interrupt Enable Bit-Mask */
#define Debug_Timer_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
/* NOT-Sticky FIFO Full Bit-Mask */
#define Debug_Timer_STATUS_FIFOFULL ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT))
/* NOT-Sticky FIFO Not Empty Bit-Mask */
#define Debug_Timer_STATUS_FIFONEMP ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFONEMP_SHIFT))
/* Interrupt Enable Bit-Mask */
#define Debug_Timer_STATUS_FIFOFULL_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT))
#define Debug_Timer_STATUS_ACTL_INT_EN 0x10u /* As defined for the ACTL Register */
/* Datapath Auxillary Control Register definitions */
#define Debug_Timer_AUX_CTRL_FIFO0_CLR 0x01u /* As defined by Register map */
#define Debug_Timer_AUX_CTRL_FIFO1_CLR 0x02u /* As defined by Register map */
#define Debug_Timer_AUX_CTRL_FIFO0_LVL 0x04u /* As defined by Register map */
#define Debug_Timer_AUX_CTRL_FIFO1_LVL 0x08u /* As defined by Register map */
#define Debug_Timer_STATUS_ACTL_INT_EN_MASK 0x10u /* As defined for the ACTL Register */
#endif /* Implementation Specific Registers and Register Constants */
#endif /* CY_Timer_v2_30_Debug_Timer_H */
/* [] END OF FILE */

409
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.c Executable file
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/*******************************************************************************
* File Name: Debug_Timer_Interrupt.c
* Version 1.70
*
* Description:
* API for controlling the state of an interrupt.
*
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include <CyLib.h>
#include <Debug_Timer_Interrupt.h>
#if !defined(Debug_Timer_Interrupt__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Place your includes, defines and code here
********************************************************************************/
/* `#START Debug_Timer_Interrupt_intc` */
/* `#END` */
#ifndef CYINT_IRQ_BASE
#define CYINT_IRQ_BASE 16
#endif /* CYINT_IRQ_BASE */
#ifndef CYINT_VECT_TABLE
#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
#endif /* CYINT_VECT_TABLE */
/* Declared in startup, used to set unused interrupts to. */
CY_ISR_PROTO(IntDefaultHandler);
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_Start
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it. This function disables the interrupt,
* sets the default interrupt vector, sets the priority from the value in the
* Design Wide Resources Interrupt Editor, then enables the interrupt to the
* interrupt controller.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_Start(void)
{
/* For all we know the interrupt is active. */
Debug_Timer_Interrupt_Disable();
/* Set the ISR to point to the Debug_Timer_Interrupt Interrupt. */
Debug_Timer_Interrupt_SetVector(&Debug_Timer_Interrupt_Interrupt);
/* Set the priority. */
Debug_Timer_Interrupt_SetPriority((uint8)Debug_Timer_Interrupt_INTC_PRIOR_NUMBER);
/* Enable it. */
Debug_Timer_Interrupt_Enable();
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_StartEx
********************************************************************************
*
* Summary:
* Sets up the interrupt and enables it. This function disables the interrupt,
* sets the interrupt vector based on the address passed in, sets the priority
* from the value in the Design Wide Resources Interrupt Editor, then enables
* the interrupt to the interrupt controller.
*
* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
* used to provide consistent definition across compilers:
*
* Function definition example:
* CY_ISR(MyISR)
* {
* }
* Function prototype example:
* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_StartEx(cyisraddress address)
{
/* For all we know the interrupt is active. */
Debug_Timer_Interrupt_Disable();
/* Set the ISR to point to the Debug_Timer_Interrupt Interrupt. */
Debug_Timer_Interrupt_SetVector(address);
/* Set the priority. */
Debug_Timer_Interrupt_SetPriority((uint8)Debug_Timer_Interrupt_INTC_PRIOR_NUMBER);
/* Enable it. */
Debug_Timer_Interrupt_Enable();
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_Stop
********************************************************************************
*
* Summary:
* Disables and removes the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_Stop(void)
{
/* Disable this interrupt. */
Debug_Timer_Interrupt_Disable();
/* Set the ISR to point to the passive one. */
Debug_Timer_Interrupt_SetVector(&IntDefaultHandler);
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_Interrupt
********************************************************************************
*
* Summary:
* The default Interrupt Service Routine for Debug_Timer_Interrupt.
*
* Add custom code between the coments to keep the next version of this file
* from over writting your code.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
CY_ISR(Debug_Timer_Interrupt_Interrupt)
{
#ifdef Debug_Timer_Interrupt_INTERRUPT_INTERRUPT_CALLBACK
Debug_Timer_Interrupt_Interrupt_InterruptCallback();
#endif /* Debug_Timer_Interrupt_INTERRUPT_INTERRUPT_CALLBACK */
/* Place your Interrupt code here. */
/* `#START Debug_Timer_Interrupt_Interrupt` */
/* `#END` */
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_SetVector
********************************************************************************
*
* Summary:
* Change the ISR vector for the Interrupt. Note calling Debug_Timer_Interrupt_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use Debug_Timer_Interrupt_StartEx instead.
*
* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
* used to provide consistent definition across compilers:
*
* Function definition example:
* CY_ISR(MyISR)
* {
* }
*
* Function prototype example:
* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_SetVector(cyisraddress address)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
ramVectorTable[CYINT_IRQ_BASE + (uint32)Debug_Timer_Interrupt__INTC_NUMBER] = address;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_GetVector
********************************************************************************
*
* Summary:
* Gets the "address" of the current ISR vector for the Interrupt.
*
* Parameters:
* None
*
* Return:
* Address of the ISR in the interrupt vector table.
*
*******************************************************************************/
cyisraddress Debug_Timer_Interrupt_GetVector(void)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
return ramVectorTable[CYINT_IRQ_BASE + (uint32)Debug_Timer_Interrupt__INTC_NUMBER];
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_SetPriority
********************************************************************************
*
* Summary:
* Sets the Priority of the Interrupt.
*
* Note calling Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx will
* override any effect this API would have had. This API should only be called
* after Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called.
* To set the initial priority for the component, use the Design-Wide Resources
* Interrupt Editor.
*
* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
* priority: Priority of the interrupt, 0 being the highest priority
* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_SetPriority(uint8 priority)
{
*Debug_Timer_Interrupt_INTC_PRIOR = priority << 5;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_GetPriority
********************************************************************************
*
* Summary:
* Gets the Priority of the Interrupt.
*
* Parameters:
* None
*
* Return:
* Priority of the interrupt, 0 being the highest priority
* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 Debug_Timer_Interrupt_GetPriority(void)
{
uint8 priority;
priority = *Debug_Timer_Interrupt_INTC_PRIOR >> 5;
return priority;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_Enable
********************************************************************************
*
* Summary:
* Enables the interrupt to the interrupt controller. Do not call this function
* unless ISR_Start() has been called or the functionality of the ISR_Start()
* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_Enable(void)
{
/* Enable the general interrupt. */
*Debug_Timer_Interrupt_INTC_SET_EN = Debug_Timer_Interrupt__INTC_MASK;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_GetState
********************************************************************************
*
* Summary:
* Gets the state (enabled, disabled) of the Interrupt.
*
* Parameters:
* None
*
* Return:
* 1 if enabled, 0 if disabled.
*
*******************************************************************************/
uint8 Debug_Timer_Interrupt_GetState(void)
{
/* Get the state of the general interrupt. */
return ((*Debug_Timer_Interrupt_INTC_SET_EN & (uint32)Debug_Timer_Interrupt__INTC_MASK) != 0u) ? 1u:0u;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_Disable
********************************************************************************
*
* Summary:
* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_Disable(void)
{
/* Disable the general interrupt. */
*Debug_Timer_Interrupt_INTC_CLR_EN = Debug_Timer_Interrupt__INTC_MASK;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_SetPending
********************************************************************************
*
* Summary:
* Causes the Interrupt to enter the pending state, a software method of
* generating the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
* Side Effects:
* If interrupts are enabled and the interrupt is set up properly, the ISR is
* entered (depending on the priority of this interrupt and other pending
* interrupts).
*
*******************************************************************************/
void Debug_Timer_Interrupt_SetPending(void)
{
*Debug_Timer_Interrupt_INTC_SET_PD = Debug_Timer_Interrupt__INTC_MASK;
}
/*******************************************************************************
* Function Name: Debug_Timer_Interrupt_ClearPending
********************************************************************************
*
* Summary:
* Clears a pending interrupt in the interrupt controller.
*
* Note Some interrupt sources are clear-on-read and require the block
* interrupt/status register to be read/cleared with the appropriate block API
* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void Debug_Timer_Interrupt_ClearPending(void)
{
*Debug_Timer_Interrupt_INTC_CLR_PD = Debug_Timer_Interrupt__INTC_MASK;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

70
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.h Executable file
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/*******************************************************************************
* File Name: Debug_Timer_Interrupt.h
* Version 1.70
*
* Description:
* Provides the function definitions for the Interrupt Controller.
*
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_ISR_Debug_Timer_Interrupt_H)
#define CY_ISR_Debug_Timer_Interrupt_H
#include <cytypes.h>
#include <cyfitter.h>
/* Interrupt Controller API. */
void Debug_Timer_Interrupt_Start(void);
void Debug_Timer_Interrupt_StartEx(cyisraddress address);
void Debug_Timer_Interrupt_Stop(void);
CY_ISR_PROTO(Debug_Timer_Interrupt_Interrupt);
void Debug_Timer_Interrupt_SetVector(cyisraddress address);
cyisraddress Debug_Timer_Interrupt_GetVector(void);
void Debug_Timer_Interrupt_SetPriority(uint8 priority);
uint8 Debug_Timer_Interrupt_GetPriority(void);
void Debug_Timer_Interrupt_Enable(void);
uint8 Debug_Timer_Interrupt_GetState(void);
void Debug_Timer_Interrupt_Disable(void);
void Debug_Timer_Interrupt_SetPending(void);
void Debug_Timer_Interrupt_ClearPending(void);
/* Interrupt Controller Constants */
/* Address of the INTC.VECT[x] register that contains the Address of the Debug_Timer_Interrupt ISR. */
#define Debug_Timer_Interrupt_INTC_VECTOR ((reg32 *) Debug_Timer_Interrupt__INTC_VECT)
/* Address of the Debug_Timer_Interrupt ISR priority. */
#define Debug_Timer_Interrupt_INTC_PRIOR ((reg8 *) Debug_Timer_Interrupt__INTC_PRIOR_REG)
/* Priority of the Debug_Timer_Interrupt interrupt. */
#define Debug_Timer_Interrupt_INTC_PRIOR_NUMBER Debug_Timer_Interrupt__INTC_PRIOR_NUM
/* Address of the INTC.SET_EN[x] byte to bit enable Debug_Timer_Interrupt interrupt. */
#define Debug_Timer_Interrupt_INTC_SET_EN ((reg32 *) Debug_Timer_Interrupt__INTC_SET_EN_REG)
/* Address of the INTC.CLR_EN[x] register to bit clear the Debug_Timer_Interrupt interrupt. */
#define Debug_Timer_Interrupt_INTC_CLR_EN ((reg32 *) Debug_Timer_Interrupt__INTC_CLR_EN_REG)
/* Address of the INTC.SET_PD[x] register to set the Debug_Timer_Interrupt interrupt state to pending. */
#define Debug_Timer_Interrupt_INTC_SET_PD ((reg32 *) Debug_Timer_Interrupt__INTC_SET_PD_REG)
/* Address of the INTC.CLR_PD[x] register to clear the Debug_Timer_Interrupt interrupt. */
#define Debug_Timer_Interrupt_INTC_CLR_PD ((reg32 *) Debug_Timer_Interrupt__INTC_CLR_PD_REG)
#endif /* CY_ISR_Debug_Timer_Interrupt_H */
/* [] END OF FILE */

162
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c Executable file
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/*******************************************************************************
* File Name: Debug_Timer_PM.c
* Version 2.70
*
* Description:
* This file provides the power management source code to API for the
* Timer.
*
* Note:
* None
*
*******************************************************************************
* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include "Debug_Timer.h"
static Debug_Timer_backupStruct Debug_Timer_backup;
/*******************************************************************************
* Function Name: Debug_Timer_SaveConfig
********************************************************************************
*
* Summary:
* Save the current user configuration
*
* Parameters:
* void
*
* Return:
* void
*
* Global variables:
* Debug_Timer_backup: Variables of this global structure are modified to
* store the values of non retention configuration registers when Sleep() API is
* called.
*
*******************************************************************************/
void Debug_Timer_SaveConfig(void)
{
#if (!Debug_Timer_UsingFixedFunction)
Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
#if (Debug_Timer_UsingHWCaptureCounter)
Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
#endif /* Back Up capture counter register */
#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
Debug_Timer_backup.TimerControlRegister = Debug_Timer_ReadControlRegister();
#endif /* Backup the enable state of the Timer component */
#endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */
}
/*******************************************************************************
* Function Name: Debug_Timer_RestoreConfig
********************************************************************************
*
* Summary:
* Restores the current user configuration.
*
* Parameters:
* void
*
* Return:
* void
*
* Global variables:
* Debug_Timer_backup: Variables of this global structure are used to
* restore the values of non retention registers on wakeup from sleep mode.
*
*******************************************************************************/
void Debug_Timer_RestoreConfig(void)
{
#if (!Debug_Timer_UsingFixedFunction)
Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
#if (Debug_Timer_UsingHWCaptureCounter)
Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
#endif /* Restore Capture counter register*/
#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
Debug_Timer_WriteControlRegister(Debug_Timer_backup.TimerControlRegister);
#endif /* Restore the enable state of the Timer component */
#endif /* Restore non retention registers in the UDB implementation only */
}
/*******************************************************************************
* Function Name: Debug_Timer_Sleep
********************************************************************************
*
* Summary:
* Stop and Save the user configuration
*
* Parameters:
* void
*
* Return:
* void
*
* Global variables:
* Debug_Timer_backup.TimerEnableState: Is modified depending on the
* enable state of the block before entering sleep mode.
*
*******************************************************************************/
void Debug_Timer_Sleep(void)
{
#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
/* Save Counter's enable state */
if(Debug_Timer_CTRL_ENABLE == (Debug_Timer_CONTROL & Debug_Timer_CTRL_ENABLE))
{
/* Timer is enabled */
Debug_Timer_backup.TimerEnableState = 1u;
}
else
{
/* Timer is disabled */
Debug_Timer_backup.TimerEnableState = 0u;
}
#endif /* Back up enable state from the Timer control register */
Debug_Timer_Stop();
Debug_Timer_SaveConfig();
}
/*******************************************************************************
* Function Name: Debug_Timer_Wakeup
********************************************************************************
*
* Summary:
* Restores and enables the user configuration
*
* Parameters:
* void
*
* Return:
* void
*
* Global variables:
* Debug_Timer_backup.enableState: Is used to restore the enable state of
* block on wakeup from sleep mode.
*
*******************************************************************************/
void Debug_Timer_Wakeup(void)
{
Debug_Timer_RestoreConfig();
#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
if(Debug_Timer_backup.TimerEnableState == 1u)
{ /* Enable Timer's operation */
Debug_Timer_Enable();
} /* Do nothing if Timer was disabled before */
#endif /* Remove this code section if Control register is removed */
}
/* [] END OF FILE */

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/*******************************************************************************
* File Name: EXTLED.c
* Version 2.20
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "EXTLED.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
EXTLED__PORT == 15 && ((EXTLED__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: EXTLED_Write
****************************************************************************//**
*
* \brief Writes the value to the physical port (data output register), masking
* and shifting the bits appropriately.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This function avoids changing
* other bits in the port by using the appropriate method (read-modify-write or
* bit banding).
*
* <b>Note</b> This function should not be used on a hardware digital output pin
* as it is driven by the hardware signal attached to it.
*
* \param value
* Value to write to the component instance.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic; the Interrupt
* Service Routines (ISR) can cause corruption of this function. An ISR that
* interrupts this function and performs writes to the Pins component data
* register can cause corrupted port data. To avoid this issue, you should
* either use the Per-Pin APIs (primary method) or disable interrupts around
* this function.
*
* \funcusage
* \snippet EXTLED_SUT.c usage_EXTLED_Write
*******************************************************************************/
void EXTLED_Write(uint8 value)
{
uint8 staticBits = (EXTLED_DR & (uint8)(~EXTLED_MASK));
EXTLED_DR = staticBits | ((uint8)(value << EXTLED_SHIFT) & EXTLED_MASK);
}
/*******************************************************************************
* Function Name: EXTLED_SetDriveMode
****************************************************************************//**
*
* \brief Sets the drive mode for each of the Pins component's pins.
*
* <b>Note</b> This affects all pins in the Pins component instance. Use the
* Per-Pin APIs if you wish to control individual pin's drive modes.
*
* \param mode
* Mode for the selected signals. Valid options are documented in
* \ref driveMode.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic, the ISR can
* cause corruption of this function. An ISR that interrupts this function
* and performs writes to the Pins component Drive Mode registers can cause
* corrupted port data. To avoid this issue, you should either use the Per-Pin
* APIs (primary method) or disable interrupts around this function.
*
* \funcusage
* \snippet EXTLED_SUT.c usage_EXTLED_SetDriveMode
*******************************************************************************/
void EXTLED_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(EXTLED_0, mode);
}
/*******************************************************************************
* Function Name: EXTLED_Read
****************************************************************************//**
*
* \brief Reads the associated physical port (pin status register) and masks
* the required bits according to the width and bit position of the component
* instance.
*
* The pin's status register returns the current logic level present on the
* physical pin.
*
* \return
* The current value for the pins in the component as a right justified number.
*
* \funcusage
* \snippet EXTLED_SUT.c usage_EXTLED_Read
*******************************************************************************/
uint8 EXTLED_Read(void)
{
return (EXTLED_PS & EXTLED_MASK) >> EXTLED_SHIFT;
}
/*******************************************************************************
* Function Name: EXTLED_ReadDataReg
****************************************************************************//**
*
* \brief Reads the associated physical port's data output register and masks
* the correct bits according to the width and bit position of the component
* instance.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This is not the same as the
* preferred EXTLED_Read() API because the
* EXTLED_ReadDataReg() reads the data register instead of the status
* register. For output pins this is a useful function to determine the value
* just written to the pin.
*
* \return
* The current value of the data register masked and shifted into a right
* justified number for the component instance.
*
* \funcusage
* \snippet EXTLED_SUT.c usage_EXTLED_ReadDataReg
*******************************************************************************/
uint8 EXTLED_ReadDataReg(void)
{
return (EXTLED_DR & EXTLED_MASK) >> EXTLED_SHIFT;
}
/* If interrupt is connected for this Pins component */
#if defined(EXTLED_INTSTAT)
/*******************************************************************************
* Function Name: EXTLED_SetInterruptMode
****************************************************************************//**
*
* \brief Configures the interrupt mode for each of the Pins component's
* pins. Alternatively you may set the interrupt mode for all the pins
* specified in the Pins component.
*
* <b>Note</b> The interrupt is port-wide and therefore any enabled pin
* interrupt may trigger it.
*
* \param position
* The pin position as listed in the Pins component. You may OR these to be
* able to configure the interrupt mode of multiple pins within a Pins
* component. Or you may use EXTLED_INTR_ALL to configure the
* interrupt mode of all the pins in the Pins component.
* - EXTLED_0_INTR (First pin in the list)
* - EXTLED_1_INTR (Second pin in the list)
* - ...
* - EXTLED_INTR_ALL (All pins in Pins component)
*
* \param mode
* Interrupt mode for the selected pins. Valid options are documented in
* \ref intrMode.
*
* \return
* None
*
* \sideeffect
* It is recommended that the interrupt be disabled before calling this
* function to avoid unintended interrupt requests. Note that the interrupt
* type is port wide, and therefore will trigger for any enabled pin on the
* port.
*
* \funcusage
* \snippet EXTLED_SUT.c usage_EXTLED_SetInterruptMode
*******************************************************************************/
void EXTLED_SetInterruptMode(uint16 position, uint16 mode)
{
if((position & EXTLED_0_INTR) != 0u)
{
EXTLED_0_INTTYPE_REG = (uint8)mode;
}
}
/*******************************************************************************
* Function Name: EXTLED_ClearInterrupt
****************************************************************************//**
*
* \brief Clears any active interrupts attached with the component and returns
* the value of the interrupt status register allowing determination of which
* pins generated an interrupt event.
*
* \return
* The right-shifted current value of the interrupt status register. Each pin
* has one bit set if it generated an interrupt event. For example, bit 0 is
* for pin 0 and bit 1 is for pin 1 of the Pins component.
*
* \sideeffect
* Clears all bits of the physical port's interrupt status register, not just
* those associated with the Pins component.
*
* \funcusage
* \snippet EXTLED_SUT.c usage_EXTLED_ClearInterrupt
*******************************************************************************/
uint8 EXTLED_ClearInterrupt(void)
{
return (EXTLED_INTSTAT & EXTLED_MASK) >> EXTLED_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: EXTLED.h
* Version 2.20
*
* Description:
* This file contains Pin function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_EXTLED_H) /* Pins EXTLED_H */
#define CY_PINS_EXTLED_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "EXTLED_aliases.h"
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
EXTLED__PORT == 15 && ((EXTLED__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
/**
* \addtogroup group_general
* @{
*/
void EXTLED_Write(uint8 value);
void EXTLED_SetDriveMode(uint8 mode);
uint8 EXTLED_ReadDataReg(void);
uint8 EXTLED_Read(void);
void EXTLED_SetInterruptMode(uint16 position, uint16 mode);
uint8 EXTLED_ClearInterrupt(void);
/** @} general */
/***************************************
* API Constants
***************************************/
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup driveMode Drive mode constants
* \brief Constants to be passed as "mode" parameter in the EXTLED_SetDriveMode() function.
* @{
*/
#define EXTLED_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define EXTLED_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define EXTLED_DM_RES_UP PIN_DM_RES_UP
#define EXTLED_DM_RES_DWN PIN_DM_RES_DWN
#define EXTLED_DM_OD_LO PIN_DM_OD_LO
#define EXTLED_DM_OD_HI PIN_DM_OD_HI
#define EXTLED_DM_STRONG PIN_DM_STRONG
#define EXTLED_DM_RES_UPDWN PIN_DM_RES_UPDWN
/** @} driveMode */
/** @} group_constants */
/* Digital Port Constants */
#define EXTLED_MASK EXTLED__MASK
#define EXTLED_SHIFT EXTLED__SHIFT
#define EXTLED_WIDTH 1u
/* Interrupt constants */
#if defined(EXTLED__INTSTAT)
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup intrMode Interrupt constants
* \brief Constants to be passed as "mode" parameter in EXTLED_SetInterruptMode() function.
* @{
*/
#define EXTLED_INTR_NONE (uint16)(0x0000u)
#define EXTLED_INTR_RISING (uint16)(0x0001u)
#define EXTLED_INTR_FALLING (uint16)(0x0002u)
#define EXTLED_INTR_BOTH (uint16)(0x0003u)
/** @} intrMode */
/** @} group_constants */
#define EXTLED_INTR_MASK (0x01u)
#endif /* (EXTLED__INTSTAT) */
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define EXTLED_PS (* (reg8 *) EXTLED__PS)
/* Data Register */
#define EXTLED_DR (* (reg8 *) EXTLED__DR)
/* Port Number */
#define EXTLED_PRT_NUM (* (reg8 *) EXTLED__PRT)
/* Connect to Analog Globals */
#define EXTLED_AG (* (reg8 *) EXTLED__AG)
/* Analog MUX bux enable */
#define EXTLED_AMUX (* (reg8 *) EXTLED__AMUX)
/* Bidirectional Enable */
#define EXTLED_BIE (* (reg8 *) EXTLED__BIE)
/* Bit-mask for Aliased Register Access */
#define EXTLED_BIT_MASK (* (reg8 *) EXTLED__BIT_MASK)
/* Bypass Enable */
#define EXTLED_BYP (* (reg8 *) EXTLED__BYP)
/* Port wide control signals */
#define EXTLED_CTL (* (reg8 *) EXTLED__CTL)
/* Drive Modes */
#define EXTLED_DM0 (* (reg8 *) EXTLED__DM0)
#define EXTLED_DM1 (* (reg8 *) EXTLED__DM1)
#define EXTLED_DM2 (* (reg8 *) EXTLED__DM2)
/* Input Buffer Disable Override */
#define EXTLED_INP_DIS (* (reg8 *) EXTLED__INP_DIS)
/* LCD Common or Segment Drive */
#define EXTLED_LCD_COM_SEG (* (reg8 *) EXTLED__LCD_COM_SEG)
/* Enable Segment LCD */
#define EXTLED_LCD_EN (* (reg8 *) EXTLED__LCD_EN)
/* Slew Rate Control */
#define EXTLED_SLW (* (reg8 *) EXTLED__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define EXTLED_PRTDSI__CAPS_SEL (* (reg8 *) EXTLED__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define EXTLED_PRTDSI__DBL_SYNC_IN (* (reg8 *) EXTLED__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define EXTLED_PRTDSI__OE_SEL0 (* (reg8 *) EXTLED__PRTDSI__OE_SEL0)
#define EXTLED_PRTDSI__OE_SEL1 (* (reg8 *) EXTLED__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define EXTLED_PRTDSI__OUT_SEL0 (* (reg8 *) EXTLED__PRTDSI__OUT_SEL0)
#define EXTLED_PRTDSI__OUT_SEL1 (* (reg8 *) EXTLED__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define EXTLED_PRTDSI__SYNC_OUT (* (reg8 *) EXTLED__PRTDSI__SYNC_OUT)
/* SIO registers */
#if defined(EXTLED__SIO_CFG)
#define EXTLED_SIO_HYST_EN (* (reg8 *) EXTLED__SIO_HYST_EN)
#define EXTLED_SIO_REG_HIFREQ (* (reg8 *) EXTLED__SIO_REG_HIFREQ)
#define EXTLED_SIO_CFG (* (reg8 *) EXTLED__SIO_CFG)
#define EXTLED_SIO_DIFF (* (reg8 *) EXTLED__SIO_DIFF)
#endif /* (EXTLED__SIO_CFG) */
/* Interrupt Registers */
#if defined(EXTLED__INTSTAT)
#define EXTLED_INTSTAT (* (reg8 *) EXTLED__INTSTAT)
#define EXTLED_SNAP (* (reg8 *) EXTLED__SNAP)
#define EXTLED_0_INTTYPE_REG (* (reg8 *) EXTLED__0__INTTYPE)
#endif /* (EXTLED__INTSTAT) */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_EXTLED_H */
/* [] END OF FILE */

36
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/*******************************************************************************
* File Name: EXTLED.h
* Version 2.20
*
* Description:
* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_EXTLED_ALIASES_H) /* Pins EXTLED_ALIASES_H */
#define CY_PINS_EXTLED_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define EXTLED_0 (EXTLED__0__PC)
#define EXTLED_0_INTR ((uint16)((uint16)0x0001u << EXTLED__0__SHIFT))
#define EXTLED_INTR_ALL ((uint16)(EXTLED_0_INTR))
#endif /* End Pins EXTLED_ALIASES_H */
/* [] END OF FILE */

231
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c Executable file
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/*******************************************************************************
* File Name: LED1.c
* Version 2.20
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "LED1.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: LED1_Write
****************************************************************************//**
*
* \brief Writes the value to the physical port (data output register), masking
* and shifting the bits appropriately.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This function avoids changing
* other bits in the port by using the appropriate method (read-modify-write or
* bit banding).
*
* <b>Note</b> This function should not be used on a hardware digital output pin
* as it is driven by the hardware signal attached to it.
*
* \param value
* Value to write to the component instance.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic; the Interrupt
* Service Routines (ISR) can cause corruption of this function. An ISR that
* interrupts this function and performs writes to the Pins component data
* register can cause corrupted port data. To avoid this issue, you should
* either use the Per-Pin APIs (primary method) or disable interrupts around
* this function.
*
* \funcusage
* \snippet LED1_SUT.c usage_LED1_Write
*******************************************************************************/
void LED1_Write(uint8 value)
{
uint8 staticBits = (LED1_DR & (uint8)(~LED1_MASK));
LED1_DR = staticBits | ((uint8)(value << LED1_SHIFT) & LED1_MASK);
}
/*******************************************************************************
* Function Name: LED1_SetDriveMode
****************************************************************************//**
*
* \brief Sets the drive mode for each of the Pins component's pins.
*
* <b>Note</b> This affects all pins in the Pins component instance. Use the
* Per-Pin APIs if you wish to control individual pin's drive modes.
*
* \param mode
* Mode for the selected signals. Valid options are documented in
* \ref driveMode.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic, the ISR can
* cause corruption of this function. An ISR that interrupts this function
* and performs writes to the Pins component Drive Mode registers can cause
* corrupted port data. To avoid this issue, you should either use the Per-Pin
* APIs (primary method) or disable interrupts around this function.
*
* \funcusage
* \snippet LED1_SUT.c usage_LED1_SetDriveMode
*******************************************************************************/
void LED1_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(LED1_0, mode);
CyPins_SetPinDriveMode(LED1_1, mode);
}
/*******************************************************************************
* Function Name: LED1_Read
****************************************************************************//**
*
* \brief Reads the associated physical port (pin status register) and masks
* the required bits according to the width and bit position of the component
* instance.
*
* The pin's status register returns the current logic level present on the
* physical pin.
*
* \return
* The current value for the pins in the component as a right justified number.
*
* \funcusage
* \snippet LED1_SUT.c usage_LED1_Read
*******************************************************************************/
uint8 LED1_Read(void)
{
return (LED1_PS & LED1_MASK) >> LED1_SHIFT;
}
/*******************************************************************************
* Function Name: LED1_ReadDataReg
****************************************************************************//**
*
* \brief Reads the associated physical port's data output register and masks
* the correct bits according to the width and bit position of the component
* instance.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This is not the same as the
* preferred LED1_Read() API because the
* LED1_ReadDataReg() reads the data register instead of the status
* register. For output pins this is a useful function to determine the value
* just written to the pin.
*
* \return
* The current value of the data register masked and shifted into a right
* justified number for the component instance.
*
* \funcusage
* \snippet LED1_SUT.c usage_LED1_ReadDataReg
*******************************************************************************/
uint8 LED1_ReadDataReg(void)
{
return (LED1_DR & LED1_MASK) >> LED1_SHIFT;
}
/* If interrupt is connected for this Pins component */
#if defined(LED1_INTSTAT)
/*******************************************************************************
* Function Name: LED1_SetInterruptMode
****************************************************************************//**
*
* \brief Configures the interrupt mode for each of the Pins component's
* pins. Alternatively you may set the interrupt mode for all the pins
* specified in the Pins component.
*
* <b>Note</b> The interrupt is port-wide and therefore any enabled pin
* interrupt may trigger it.
*
* \param position
* The pin position as listed in the Pins component. You may OR these to be
* able to configure the interrupt mode of multiple pins within a Pins
* component. Or you may use LED1_INTR_ALL to configure the
* interrupt mode of all the pins in the Pins component.
* - LED1_0_INTR (First pin in the list)
* - LED1_1_INTR (Second pin in the list)
* - ...
* - LED1_INTR_ALL (All pins in Pins component)
*
* \param mode
* Interrupt mode for the selected pins. Valid options are documented in
* \ref intrMode.
*
* \return
* None
*
* \sideeffect
* It is recommended that the interrupt be disabled before calling this
* function to avoid unintended interrupt requests. Note that the interrupt
* type is port wide, and therefore will trigger for any enabled pin on the
* port.
*
* \funcusage
* \snippet LED1_SUT.c usage_LED1_SetInterruptMode
*******************************************************************************/
void LED1_SetInterruptMode(uint16 position, uint16 mode)
{
if((position & LED1_0_INTR) != 0u)
{
LED1_0_INTTYPE_REG = (uint8)mode;
}
if((position & LED1_1_INTR) != 0u)
{
LED1_1_INTTYPE_REG = (uint8)mode;
}
}
/*******************************************************************************
* Function Name: LED1_ClearInterrupt
****************************************************************************//**
*
* \brief Clears any active interrupts attached with the component and returns
* the value of the interrupt status register allowing determination of which
* pins generated an interrupt event.
*
* \return
* The right-shifted current value of the interrupt status register. Each pin
* has one bit set if it generated an interrupt event. For example, bit 0 is
* for pin 0 and bit 1 is for pin 1 of the Pins component.
*
* \sideeffect
* Clears all bits of the physical port's interrupt status register, not just
* those associated with the Pins component.
*
* \funcusage
* \snippet LED1_SUT.c usage_LED1_ClearInterrupt
*******************************************************************************/
uint8 LED1_ClearInterrupt(void)
{
return (LED1_INTSTAT & LED1_MASK) >> LED1_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: LED1.h
* Version 2.20
*
* Description:
* This file contains Pin function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_LED1_H) /* Pins LED1_H */
#define CY_PINS_LED1_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "LED1_aliases.h"
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
/**
* \addtogroup group_general
* @{
*/
void LED1_Write(uint8 value);
void LED1_SetDriveMode(uint8 mode);
uint8 LED1_ReadDataReg(void);
uint8 LED1_Read(void);
void LED1_SetInterruptMode(uint16 position, uint16 mode);
uint8 LED1_ClearInterrupt(void);
/** @} general */
/***************************************
* API Constants
***************************************/
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup driveMode Drive mode constants
* \brief Constants to be passed as "mode" parameter in the LED1_SetDriveMode() function.
* @{
*/
#define LED1_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define LED1_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define LED1_DM_RES_UP PIN_DM_RES_UP
#define LED1_DM_RES_DWN PIN_DM_RES_DWN
#define LED1_DM_OD_LO PIN_DM_OD_LO
#define LED1_DM_OD_HI PIN_DM_OD_HI
#define LED1_DM_STRONG PIN_DM_STRONG
#define LED1_DM_RES_UPDWN PIN_DM_RES_UPDWN
/** @} driveMode */
/** @} group_constants */
/* Digital Port Constants */
#define LED1_MASK LED1__MASK
#define LED1_SHIFT LED1__SHIFT
#define LED1_WIDTH 2u
/* Interrupt constants */
#if defined(LED1__INTSTAT)
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup intrMode Interrupt constants
* \brief Constants to be passed as "mode" parameter in LED1_SetInterruptMode() function.
* @{
*/
#define LED1_INTR_NONE (uint16)(0x0000u)
#define LED1_INTR_RISING (uint16)(0x0001u)
#define LED1_INTR_FALLING (uint16)(0x0002u)
#define LED1_INTR_BOTH (uint16)(0x0003u)
/** @} intrMode */
/** @} group_constants */
#define LED1_INTR_MASK (0x01u)
#endif /* (LED1__INTSTAT) */
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define LED1_PS (* (reg8 *) LED1__PS)
/* Data Register */
#define LED1_DR (* (reg8 *) LED1__DR)
/* Port Number */
#define LED1_PRT_NUM (* (reg8 *) LED1__PRT)
/* Connect to Analog Globals */
#define LED1_AG (* (reg8 *) LED1__AG)
/* Analog MUX bux enable */
#define LED1_AMUX (* (reg8 *) LED1__AMUX)
/* Bidirectional Enable */
#define LED1_BIE (* (reg8 *) LED1__BIE)
/* Bit-mask for Aliased Register Access */
#define LED1_BIT_MASK (* (reg8 *) LED1__BIT_MASK)
/* Bypass Enable */
#define LED1_BYP (* (reg8 *) LED1__BYP)
/* Port wide control signals */
#define LED1_CTL (* (reg8 *) LED1__CTL)
/* Drive Modes */
#define LED1_DM0 (* (reg8 *) LED1__DM0)
#define LED1_DM1 (* (reg8 *) LED1__DM1)
#define LED1_DM2 (* (reg8 *) LED1__DM2)
/* Input Buffer Disable Override */
#define LED1_INP_DIS (* (reg8 *) LED1__INP_DIS)
/* LCD Common or Segment Drive */
#define LED1_LCD_COM_SEG (* (reg8 *) LED1__LCD_COM_SEG)
/* Enable Segment LCD */
#define LED1_LCD_EN (* (reg8 *) LED1__LCD_EN)
/* Slew Rate Control */
#define LED1_SLW (* (reg8 *) LED1__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define LED1_PRTDSI__CAPS_SEL (* (reg8 *) LED1__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define LED1_PRTDSI__DBL_SYNC_IN (* (reg8 *) LED1__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define LED1_PRTDSI__OE_SEL0 (* (reg8 *) LED1__PRTDSI__OE_SEL0)
#define LED1_PRTDSI__OE_SEL1 (* (reg8 *) LED1__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define LED1_PRTDSI__OUT_SEL0 (* (reg8 *) LED1__PRTDSI__OUT_SEL0)
#define LED1_PRTDSI__OUT_SEL1 (* (reg8 *) LED1__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define LED1_PRTDSI__SYNC_OUT (* (reg8 *) LED1__PRTDSI__SYNC_OUT)
/* SIO registers */
#if defined(LED1__SIO_CFG)
#define LED1_SIO_HYST_EN (* (reg8 *) LED1__SIO_HYST_EN)
#define LED1_SIO_REG_HIFREQ (* (reg8 *) LED1__SIO_REG_HIFREQ)
#define LED1_SIO_CFG (* (reg8 *) LED1__SIO_CFG)
#define LED1_SIO_DIFF (* (reg8 *) LED1__SIO_DIFF)
#endif /* (LED1__SIO_CFG) */
/* Interrupt Registers */
#if defined(LED1__INTSTAT)
#define LED1_INTSTAT (* (reg8 *) LED1__INTSTAT)
#define LED1_SNAP (* (reg8 *) LED1__SNAP)
#define LED1_0_INTTYPE_REG (* (reg8 *) LED1__0__INTTYPE)
#define LED1_1_INTTYPE_REG (* (reg8 *) LED1__1__INTTYPE)
#endif /* (LED1__INTSTAT) */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_LED1_H */
/* [] END OF FILE */

39
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h Executable file
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/*******************************************************************************
* File Name: LED1.h
* Version 2.20
*
* Description:
* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_LED1_ALIASES_H) /* Pins LED1_ALIASES_H */
#define CY_PINS_LED1_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define LED1_0 (LED1__0__PC)
#define LED1_0_INTR ((uint16)((uint16)0x0001u << LED1__0__SHIFT))
#define LED1_1 (LED1__1__PC)
#define LED1_1_INTR ((uint16)((uint16)0x0001u << LED1__1__SHIFT))
#define LED1_INTR_ALL ((uint16)(LED1_0_INTR| LED1_1_INTR))
#endif /* End Pins LED1_ALIASES_H */
/* [] END OF FILE */

137
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.c Normal file
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/*******************************************************************************
* File Name: SCSI_ATN.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "SCSI_ATN.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
SCSI_ATN__PORT == 15 && ((SCSI_ATN__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: SCSI_ATN_Write
********************************************************************************
*
* Summary:
* Assign a new value to the digital port's data output register.
*
* Parameters:
* prtValue: The value to be assigned to the Digital Port.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_ATN_Write(uint8 value)
{
uint8 staticBits = (SCSI_ATN_DR & (uint8)(~SCSI_ATN_MASK));
SCSI_ATN_DR = staticBits | ((uint8)(value << SCSI_ATN_SHIFT) & SCSI_ATN_MASK);
}
/*******************************************************************************
* Function Name: SCSI_ATN_SetDriveMode
********************************************************************************
*
* Summary:
* Change the drive mode on the pins of the port.
*
* Parameters:
* mode: Change the pins to this drive mode.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_ATN_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(SCSI_ATN_0, mode);
}
/*******************************************************************************
* Function Name: SCSI_ATN_Read
********************************************************************************
*
* Summary:
* Read the current value on the pins of the Digital Port in right justified
* form.
*
* Parameters:
* None
*
* Return:
* Returns the current value of the Digital Port as a right justified number
*
* Note:
* Macro SCSI_ATN_ReadPS calls this function.
*
*******************************************************************************/
uint8 SCSI_ATN_Read(void)
{
return (SCSI_ATN_PS & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT;
}
/*******************************************************************************
* Function Name: SCSI_ATN_ReadDataReg
********************************************************************************
*
* Summary:
* Read the current value assigned to a Digital Port's data output register
*
* Parameters:
* None
*
* Return:
* Returns the current value assigned to the Digital Port's data output register
*
*******************************************************************************/
uint8 SCSI_ATN_ReadDataReg(void)
{
return (SCSI_ATN_DR & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT;
}
/* If Interrupts Are Enabled for this Pins component */
#if defined(SCSI_ATN_INTSTAT)
/*******************************************************************************
* Function Name: SCSI_ATN_ClearInterrupt
********************************************************************************
* Summary:
* Clears any active interrupts attached to port and returns the value of the
* interrupt status register.
*
* Parameters:
* None
*
* Return:
* Returns the value of the interrupt status register
*
*******************************************************************************/
uint8 SCSI_ATN_ClearInterrupt(void)
{
return (SCSI_ATN_INTSTAT & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_ATN.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_ATN_H) /* Pins SCSI_ATN_H */
#define CY_PINS_SCSI_ATN_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "SCSI_ATN_aliases.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component cy_pins_v1_90 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
SCSI_ATN__PORT == 15 && ((SCSI_ATN__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
void SCSI_ATN_Write(uint8 value) ;
void SCSI_ATN_SetDriveMode(uint8 mode) ;
uint8 SCSI_ATN_ReadDataReg(void) ;
uint8 SCSI_ATN_Read(void) ;
uint8 SCSI_ATN_ClearInterrupt(void) ;
/***************************************
* API Constants
***************************************/
/* Drive Modes */
#define SCSI_ATN_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define SCSI_ATN_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define SCSI_ATN_DM_RES_UP PIN_DM_RES_UP
#define SCSI_ATN_DM_RES_DWN PIN_DM_RES_DWN
#define SCSI_ATN_DM_OD_LO PIN_DM_OD_LO
#define SCSI_ATN_DM_OD_HI PIN_DM_OD_HI
#define SCSI_ATN_DM_STRONG PIN_DM_STRONG
#define SCSI_ATN_DM_RES_UPDWN PIN_DM_RES_UPDWN
/* Digital Port Constants */
#define SCSI_ATN_MASK SCSI_ATN__MASK
#define SCSI_ATN_SHIFT SCSI_ATN__SHIFT
#define SCSI_ATN_WIDTH 1u
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define SCSI_ATN_PS (* (reg8 *) SCSI_ATN__PS)
/* Data Register */
#define SCSI_ATN_DR (* (reg8 *) SCSI_ATN__DR)
/* Port Number */
#define SCSI_ATN_PRT_NUM (* (reg8 *) SCSI_ATN__PRT)
/* Connect to Analog Globals */
#define SCSI_ATN_AG (* (reg8 *) SCSI_ATN__AG)
/* Analog MUX bux enable */
#define SCSI_ATN_AMUX (* (reg8 *) SCSI_ATN__AMUX)
/* Bidirectional Enable */
#define SCSI_ATN_BIE (* (reg8 *) SCSI_ATN__BIE)
/* Bit-mask for Aliased Register Access */
#define SCSI_ATN_BIT_MASK (* (reg8 *) SCSI_ATN__BIT_MASK)
/* Bypass Enable */
#define SCSI_ATN_BYP (* (reg8 *) SCSI_ATN__BYP)
/* Port wide control signals */
#define SCSI_ATN_CTL (* (reg8 *) SCSI_ATN__CTL)
/* Drive Modes */
#define SCSI_ATN_DM0 (* (reg8 *) SCSI_ATN__DM0)
#define SCSI_ATN_DM1 (* (reg8 *) SCSI_ATN__DM1)
#define SCSI_ATN_DM2 (* (reg8 *) SCSI_ATN__DM2)
/* Input Buffer Disable Override */
#define SCSI_ATN_INP_DIS (* (reg8 *) SCSI_ATN__INP_DIS)
/* LCD Common or Segment Drive */
#define SCSI_ATN_LCD_COM_SEG (* (reg8 *) SCSI_ATN__LCD_COM_SEG)
/* Enable Segment LCD */
#define SCSI_ATN_LCD_EN (* (reg8 *) SCSI_ATN__LCD_EN)
/* Slew Rate Control */
#define SCSI_ATN_SLW (* (reg8 *) SCSI_ATN__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define SCSI_ATN_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_ATN__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define SCSI_ATN_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_ATN__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define SCSI_ATN_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_ATN__PRTDSI__OE_SEL0)
#define SCSI_ATN_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_ATN__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define SCSI_ATN_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_ATN__PRTDSI__OUT_SEL0)
#define SCSI_ATN_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_ATN__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define SCSI_ATN_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_ATN__PRTDSI__SYNC_OUT)
#if defined(SCSI_ATN__INTSTAT) /* Interrupt Registers */
#define SCSI_ATN_INTSTAT (* (reg8 *) SCSI_ATN__INTSTAT)
#define SCSI_ATN_SNAP (* (reg8 *) SCSI_ATN__SNAP)
#endif /* Interrupt Registers */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_SCSI_ATN_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_ATN.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_ATN_ALIASES_H) /* Pins SCSI_ATN_ALIASES_H */
#define CY_PINS_SCSI_ATN_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SCSI_ATN_0 SCSI_ATN__0__PC
#define SCSI_ATN_INT SCSI_ATN__INT__PC
#endif /* End Pins SCSI_ATN_ALIASES_H */
/* [] END OF FILE */

521
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c Executable file
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/*******************************************************************************
* File Name: SCSI_CLK.c
* Version 2.20
*
* Description:
* This file provides the source code to the API for the clock component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include "SCSI_CLK.h"
/* Clock Distribution registers. */
#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD)
#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2)
#define BCFG2_MASK (0x80u)
#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK)
#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK)
#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP)
/*******************************************************************************
* Function Name: SCSI_CLK_Start
********************************************************************************
*
* Summary:
* Starts the clock. Note that on startup, clocks may be already running if the
* "Start on Reset" option is enabled in the DWR.
*
* Parameters:
* None
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_Start(void)
{
/* Set the bit to enable the clock. */
SCSI_CLK_CLKEN |= SCSI_CLK_CLKEN_MASK;
SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
}
/*******************************************************************************
* Function Name: SCSI_CLK_Stop
********************************************************************************
*
* Summary:
* Stops the clock and returns immediately. This API does not require the
* source clock to be running but may return before the hardware is actually
* disabled. If the settings of the clock are changed after calling this
* function, the clock may glitch when it is started. To avoid the clock
* glitch, use the StopBlock function.
*
* Parameters:
* None
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_Stop(void)
{
/* Clear the bit to disable the clock. */
SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
}
#if(CY_PSOC3 || CY_PSOC5LP)
/*******************************************************************************
* Function Name: SCSI_CLK_StopBlock
********************************************************************************
*
* Summary:
* Stops the clock and waits for the hardware to actually be disabled before
* returning. This ensures that the clock is never truncated (high part of the
* cycle will terminate before the clock is disabled and the API returns).
* Note that the source clock must be running or this API will never return as
* a stopped clock cannot be disabled.
*
* Parameters:
* None
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_StopBlock(void)
{
if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
{
#if HAS_CLKDIST_LD_DISABLE
uint16 oldDivider;
CLK_DIST_LD = 0u;
/* Clear all the mask bits except ours. */
#if defined(SCSI_CLK__CFG3)
CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
CLK_DIST_DMASK = 0x00u;
#else
CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
CLK_DIST_AMASK = 0x00u;
#endif /* SCSI_CLK__CFG3 */
/* Clear mask of bus clock. */
CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
oldDivider = CY_GET_REG16(SCSI_CLK_DIV_PTR);
CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
/* Wait for clock to be disabled */
while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
#endif /* HAS_CLKDIST_LD_DISABLE */
/* Clear the bit to disable the clock. */
SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
#if HAS_CLKDIST_LD_DISABLE
/* Clear the disable bit */
CLK_DIST_LD = 0x00u;
CY_SET_REG16(SCSI_CLK_DIV_PTR, oldDivider);
#endif /* HAS_CLKDIST_LD_DISABLE */
}
}
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/*******************************************************************************
* Function Name: SCSI_CLK_StandbyPower
********************************************************************************
*
* Summary:
* Sets whether the clock is active in standby mode.
*
* Parameters:
* state: 0 to disable clock during standby, nonzero to enable.
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_StandbyPower(uint8 state)
{
if(state == 0u)
{
SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
}
else
{
SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
}
}
/*******************************************************************************
* Function Name: SCSI_CLK_SetDividerRegister
********************************************************************************
*
* Summary:
* Modifies the clock divider and, thus, the frequency. When the clock divider
* register is set to zero or changed from zero, the clock will be temporarily
* disabled in order to change the SSS mode bit. If the clock is enabled when
* SetDividerRegister is called, then the source clock must be running.
*
* Parameters:
* clkDivider: Divider register value (0-65,535). This value is NOT the
* divider; the clock hardware divides by clkDivider plus one. For example,
* to divide the clock by 2, this parameter should be set to 1.
* restart: If nonzero, restarts the clock divider: the current clock cycle
* will be truncated and the new divide value will take effect immediately. If
* zero, the new divide value will take effect at the end of the current clock
* cycle.
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart)
{
uint8 enabled;
uint8 currSrc = SCSI_CLK_GetSourceRegister();
uint16 oldDivider = SCSI_CLK_GetDividerRegister();
if (clkDivider != oldDivider)
{
enabled = SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK;
if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
{
/* Moving to/from SSS requires correct ordering to prevent halting the clock */
if (oldDivider == 0u)
{
/* Moving away from SSS, set the divider first so when SSS is cleared we */
/* don't halt the clock. Using the shadow load isn't required as the */
/* divider is ignored while SSS is set. */
CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
}
else
{
/* Moving to SSS, set SSS which then ignores the divider and we can set */
/* it without bothering with the shadow load. */
SCSI_CLK_MOD_SRC |= CYCLK_SSS;
CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
}
}
else
{
if (enabled != 0u)
{
CLK_DIST_LD = 0x00u;
/* Clear all the mask bits except ours. */
#if defined(SCSI_CLK__CFG3)
CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
CLK_DIST_DMASK = 0x00u;
#else
CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
CLK_DIST_AMASK = 0x00u;
#endif /* SCSI_CLK__CFG3 */
/* Clear mask of bus clock. */
CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
/* If clock is currently enabled, disable it if async or going from N-to-1*/
if (((SCSI_CLK_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
{
#if HAS_CLKDIST_LD_DISABLE
CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
/* Wait for clock to be disabled */
while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
#endif /* HAS_CLKDIST_LD_DISABLE */
SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
#if HAS_CLKDIST_LD_DISABLE
/* Clear the disable bit */
CLK_DIST_LD = 0x00u;
#endif /* HAS_CLKDIST_LD_DISABLE */
}
}
/* Load divide value. */
if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
{
/* If the clock is still enabled, use the shadow registers */
CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
}
else
{
/* If the clock is disabled, set the divider directly */
CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
SCSI_CLK_CLKEN |= enabled;
}
}
}
}
/*******************************************************************************
* Function Name: SCSI_CLK_GetDividerRegister
********************************************************************************
*
* Summary:
* Gets the clock divider register value.
*
* Parameters:
* None
*
* Returns:
* Divide value of the clock minus 1. For example, if the clock is set to
* divide by 2, the return value will be 1.
*
*******************************************************************************/
uint16 SCSI_CLK_GetDividerRegister(void)
{
return CY_GET_REG16(SCSI_CLK_DIV_PTR);
}
/*******************************************************************************
* Function Name: SCSI_CLK_SetModeRegister
********************************************************************************
*
* Summary:
* Sets flags that control the operating mode of the clock. This function only
* changes flags from 0 to 1; flags that are already 1 will remain unchanged.
* To clear flags, use the ClearModeRegister function. The clock must be
* disabled before changing the mode.
*
* Parameters:
* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
* clkMode should be a set of the following optional bits or'ed together.
* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
* occur when the divider count reaches half of the divide
* value.
* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
* is asserted for approximately half of its period. When
* disabled, the output clock is asserted for one period of the
* source clock.
* - CYCLK_SYNC Enable output synchronization to master clock. This should
* be enabled for all synchronous clocks.
* See the Technical Reference Manual for details about setting the mode of
* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_SetModeRegister(uint8 modeBitMask)
{
SCSI_CLK_MOD_SRC |= modeBitMask & (uint8)SCSI_CLK_MODE_MASK;
}
/*******************************************************************************
* Function Name: SCSI_CLK_ClearModeRegister
********************************************************************************
*
* Summary:
* Clears flags that control the operating mode of the clock. This function
* only changes flags from 1 to 0; flags that are already 0 will remain
* unchanged. To set flags, use the SetModeRegister function. The clock must be
* disabled before changing the mode.
*
* Parameters:
* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
* clkMode should be a set of the following optional bits or'ed together.
* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
* occur when the divider count reaches half of the divide
* value.
* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
* is asserted for approximately half of its period. When
* disabled, the output clock is asserted for one period of the
* source clock.
* - CYCLK_SYNC Enable output synchronization to master clock. This should
* be enabled for all synchronous clocks.
* See the Technical Reference Manual for details about setting the mode of
* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_ClearModeRegister(uint8 modeBitMask)
{
SCSI_CLK_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SCSI_CLK_MODE_MASK));
}
/*******************************************************************************
* Function Name: SCSI_CLK_GetModeRegister
********************************************************************************
*
* Summary:
* Gets the clock mode register value.
*
* Parameters:
* None
*
* Returns:
* Bit mask representing the enabled mode bits. See the SetModeRegister and
* ClearModeRegister descriptions for details about the mode bits.
*
*******************************************************************************/
uint8 SCSI_CLK_GetModeRegister(void)
{
return SCSI_CLK_MOD_SRC & (uint8)(SCSI_CLK_MODE_MASK);
}
/*******************************************************************************
* Function Name: SCSI_CLK_SetSourceRegister
********************************************************************************
*
* Summary:
* Sets the input source of the clock. The clock must be disabled before
* changing the source. The old and new clock sources must be running.
*
* Parameters:
* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the
* following input sources:
* - CYCLK_SRC_SEL_SYNC_DIG
* - CYCLK_SRC_SEL_IMO
* - CYCLK_SRC_SEL_XTALM
* - CYCLK_SRC_SEL_ILO
* - CYCLK_SRC_SEL_PLL
* - CYCLK_SRC_SEL_XTALK
* - CYCLK_SRC_SEL_DSI_G
* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
* See the Technical Reference Manual for details on clock sources.
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_SetSourceRegister(uint8 clkSource)
{
uint16 currDiv = SCSI_CLK_GetDividerRegister();
uint8 oldSrc = SCSI_CLK_GetSourceRegister();
if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
(clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
{
/* Switching to Master and divider is 1, set SSS, which will output master, */
/* then set the source so we are consistent. */
SCSI_CLK_MOD_SRC |= CYCLK_SSS;
SCSI_CLK_MOD_SRC =
(SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
}
else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
(clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
{
/* Switching from Master to not and divider is 1, set source, so we don't */
/* lock when we clear SSS. */
SCSI_CLK_MOD_SRC =
(SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
}
else
{
SCSI_CLK_MOD_SRC =
(SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
}
}
/*******************************************************************************
* Function Name: SCSI_CLK_GetSourceRegister
********************************************************************************
*
* Summary:
* Gets the input source of the clock.
*
* Parameters:
* None
*
* Returns:
* The input source of the clock. See SetSourceRegister for details.
*
*******************************************************************************/
uint8 SCSI_CLK_GetSourceRegister(void)
{
return SCSI_CLK_MOD_SRC & SCSI_CLK_SRC_SEL_MSK;
}
#if defined(SCSI_CLK__CFG3)
/*******************************************************************************
* Function Name: SCSI_CLK_SetPhaseRegister
********************************************************************************
*
* Summary:
* Sets the phase delay of the analog clock. This function is only available
* for analog clocks. The clock must be disabled before changing the phase
* delay to avoid glitches.
*
* Parameters:
* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
* clkPhase must be from 1 to 11 inclusive. Other values, including 0,
* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11
* produces a 10ns delay.
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_SetPhaseRegister(uint8 clkPhase)
{
SCSI_CLK_PHASE = clkPhase & SCSI_CLK_PHASE_MASK;
}
/*******************************************************************************
* Function Name: SCSI_CLK_GetPhase
********************************************************************************
*
* Summary:
* Gets the phase delay of the analog clock. This function is only available
* for analog clocks.
*
* Parameters:
* None
*
* Returns:
* Phase of the analog clock. See SetPhaseRegister for details.
*
*******************************************************************************/
uint8 SCSI_CLK_GetPhaseRegister(void)
{
return SCSI_CLK_PHASE & SCSI_CLK_PHASE_MASK;
}
#endif /* SCSI_CLK__CFG3 */
/* [] END OF FILE */

124
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h Normal file
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/*******************************************************************************
* File Name: SCSI_CLK.h
* Version 2.20
*
* Description:
* Provides the function and constant definitions for the clock component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CLOCK_SCSI_CLK_H)
#define CY_CLOCK_SCSI_CLK_H
#include <cytypes.h>
#include <cyfitter.h>
/***************************************
* Conditional Compilation Parameters
***************************************/
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
#error Component cy_clock_v2_20 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
/***************************************
* Function Prototypes
***************************************/
void SCSI_CLK_Start(void) ;
void SCSI_CLK_Stop(void) ;
#if(CY_PSOC3 || CY_PSOC5LP)
void SCSI_CLK_StopBlock(void) ;
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
void SCSI_CLK_StandbyPower(uint8 state) ;
void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart)
;
uint16 SCSI_CLK_GetDividerRegister(void) ;
void SCSI_CLK_SetModeRegister(uint8 modeBitMask) ;
void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) ;
uint8 SCSI_CLK_GetModeRegister(void) ;
void SCSI_CLK_SetSourceRegister(uint8 clkSource) ;
uint8 SCSI_CLK_GetSourceRegister(void) ;
#if defined(SCSI_CLK__CFG3)
void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) ;
uint8 SCSI_CLK_GetPhaseRegister(void) ;
#endif /* defined(SCSI_CLK__CFG3) */
#define SCSI_CLK_Enable() SCSI_CLK_Start()
#define SCSI_CLK_Disable() SCSI_CLK_Stop()
#define SCSI_CLK_SetDivider(clkDivider) SCSI_CLK_SetDividerRegister(clkDivider, 1u)
#define SCSI_CLK_SetDividerValue(clkDivider) SCSI_CLK_SetDividerRegister((clkDivider) - 1u, 1u)
#define SCSI_CLK_SetMode(clkMode) SCSI_CLK_SetModeRegister(clkMode)
#define SCSI_CLK_SetSource(clkSource) SCSI_CLK_SetSourceRegister(clkSource)
#if defined(SCSI_CLK__CFG3)
#define SCSI_CLK_SetPhase(clkPhase) SCSI_CLK_SetPhaseRegister(clkPhase)
#define SCSI_CLK_SetPhaseValue(clkPhase) SCSI_CLK_SetPhaseRegister((clkPhase) + 1u)
#endif /* defined(SCSI_CLK__CFG3) */
/***************************************
* Registers
***************************************/
/* Register to enable or disable the clock */
#define SCSI_CLK_CLKEN (* (reg8 *) SCSI_CLK__PM_ACT_CFG)
#define SCSI_CLK_CLKEN_PTR ((reg8 *) SCSI_CLK__PM_ACT_CFG)
/* Register to enable or disable the clock */
#define SCSI_CLK_CLKSTBY (* (reg8 *) SCSI_CLK__PM_STBY_CFG)
#define SCSI_CLK_CLKSTBY_PTR ((reg8 *) SCSI_CLK__PM_STBY_CFG)
/* Clock LSB divider configuration register. */
#define SCSI_CLK_DIV_LSB (* (reg8 *) SCSI_CLK__CFG0)
#define SCSI_CLK_DIV_LSB_PTR ((reg8 *) SCSI_CLK__CFG0)
#define SCSI_CLK_DIV_PTR ((reg16 *) SCSI_CLK__CFG0)
/* Clock MSB divider configuration register. */
#define SCSI_CLK_DIV_MSB (* (reg8 *) SCSI_CLK__CFG1)
#define SCSI_CLK_DIV_MSB_PTR ((reg8 *) SCSI_CLK__CFG1)
/* Mode and source configuration register */
#define SCSI_CLK_MOD_SRC (* (reg8 *) SCSI_CLK__CFG2)
#define SCSI_CLK_MOD_SRC_PTR ((reg8 *) SCSI_CLK__CFG2)
#if defined(SCSI_CLK__CFG3)
/* Analog clock phase configuration register */
#define SCSI_CLK_PHASE (* (reg8 *) SCSI_CLK__CFG3)
#define SCSI_CLK_PHASE_PTR ((reg8 *) SCSI_CLK__CFG3)
#endif /* defined(SCSI_CLK__CFG3) */
/**************************************
* Register Constants
**************************************/
/* Power manager register masks */
#define SCSI_CLK_CLKEN_MASK SCSI_CLK__PM_ACT_MSK
#define SCSI_CLK_CLKSTBY_MASK SCSI_CLK__PM_STBY_MSK
/* CFG2 field masks */
#define SCSI_CLK_SRC_SEL_MSK SCSI_CLK__CFG2_SRC_SEL_MASK
#define SCSI_CLK_MODE_MASK (~(SCSI_CLK_SRC_SEL_MSK))
#if defined(SCSI_CLK__CFG3)
/* CFG3 phase mask */
#define SCSI_CLK_PHASE_MASK SCSI_CLK__CFG3_PHASE_DLY_MASK
#endif /* defined(SCSI_CLK__CFG3) */
#endif /* CY_CLOCK_SCSI_CLK_H */
/* [] END OF FILE */

63
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c Executable file
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/*******************************************************************************
* File Name: SCSI_CTL_IO.c
* Version 1.70
*
* Description:
* This file contains API to enable firmware control of a Control Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_CTL_IO.h"
#if !defined(SCSI_CTL_IO_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Function Name: SCSI_CTL_IO_Write
********************************************************************************
*
* Summary:
* Write a byte to the Control Register.
*
* Parameters:
* control: The value to be assigned to the Control Register.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_CTL_IO_Write(uint8 control)
{
SCSI_CTL_IO_Control = control;
}
/*******************************************************************************
* Function Name: SCSI_CTL_IO_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Control Register.
*
* Parameters:
* None.
*
* Return:
* Returns the current value in the Control Register.
*
*******************************************************************************/
uint8 SCSI_CTL_IO_Read(void)
{
return SCSI_CTL_IO_Control;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

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software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h Executable file
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/*******************************************************************************
* File Name: SCSI_CTL_IO.h
* Version 1.70
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CONTROL_REG_SCSI_CTL_IO_H) /* CY_CONTROL_REG_SCSI_CTL_IO_H */
#define CY_CONTROL_REG_SCSI_CTL_IO_H
#include "cytypes.h"
/***************************************
* Function Prototypes
***************************************/
void SCSI_CTL_IO_Write(uint8 control) ;
uint8 SCSI_CTL_IO_Read(void) ;
/***************************************
* Registers
***************************************/
/* Control Register */
#define SCSI_CTL_IO_Control (* (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )
#define SCSI_CTL_IO_Control_PTR ( (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )
#endif /* End CY_CONTROL_REG_SCSI_CTL_IO_H */
/* [] END OF FILE */

65
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c Executable file
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/*******************************************************************************
* File Name: SCSI_CTL_PHASE.c
* Version 1.80
*
* Description:
* This file contains API to enable firmware control of a Control Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_CTL_PHASE.h"
/* Check for removal by optimization */
#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED)
/*******************************************************************************
* Function Name: SCSI_CTL_PHASE_Write
********************************************************************************
*
* Summary:
* Write a byte to the Control Register.
*
* Parameters:
* control: The value to be assigned to the Control Register.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_CTL_PHASE_Write(uint8 control)
{
SCSI_CTL_PHASE_Control = control;
}
/*******************************************************************************
* Function Name: SCSI_CTL_PHASE_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Control Register.
*
* Parameters:
* None.
*
* Return:
* Returns the current value in the Control Register.
*
*******************************************************************************/
uint8 SCSI_CTL_PHASE_Read(void)
{
return SCSI_CTL_PHASE_Control;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

59
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h Executable file
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/*******************************************************************************
* File Name: SCSI_CTL_PHASE.h
* Version 1.80
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */
#define CY_CONTROL_REG_SCSI_CTL_PHASE_H
#include "cytypes.h"
/***************************************
* Data Struct Definitions
***************************************/
/* Sleep Mode API Support */
typedef struct
{
uint8 controlState;
} SCSI_CTL_PHASE_BACKUP_STRUCT;
/***************************************
* Function Prototypes
***************************************/
void SCSI_CTL_PHASE_Write(uint8 control) ;
uint8 SCSI_CTL_PHASE_Read(void) ;
void SCSI_CTL_PHASE_SaveConfig(void) ;
void SCSI_CTL_PHASE_RestoreConfig(void) ;
void SCSI_CTL_PHASE_Sleep(void) ;
void SCSI_CTL_PHASE_Wakeup(void) ;
/***************************************
* Registers
***************************************/
/* Control Register */
#define SCSI_CTL_PHASE_Control (* (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
#define SCSI_CTL_PHASE_Control_PTR ( (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
#endif /* End CY_CONTROL_REG_SCSI_CTL_PHASE_H */
/* [] END OF FILE */

109
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE_PM.c Executable file
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/*******************************************************************************
* File Name: SCSI_CTL_PHASE_PM.c
* Version 1.80
*
* Description:
* This file contains the setup, control, and status commands to support
* the component operation in the low power mode.
*
* Note:
*
********************************************************************************
* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_CTL_PHASE.h"
/* Check for removal by optimization */
#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED)
static SCSI_CTL_PHASE_BACKUP_STRUCT SCSI_CTL_PHASE_backup = {0u};
/*******************************************************************************
* Function Name: SCSI_CTL_PHASE_SaveConfig
********************************************************************************
*
* Summary:
* Saves the control register value.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_CTL_PHASE_SaveConfig(void)
{
SCSI_CTL_PHASE_backup.controlState = SCSI_CTL_PHASE_Control;
}
/*******************************************************************************
* Function Name: SCSI_CTL_PHASE_RestoreConfig
********************************************************************************
*
* Summary:
* Restores the control register value.
*
* Parameters:
* None
*
* Return:
* None
*
*
*******************************************************************************/
void SCSI_CTL_PHASE_RestoreConfig(void)
{
SCSI_CTL_PHASE_Control = SCSI_CTL_PHASE_backup.controlState;
}
/*******************************************************************************
* Function Name: SCSI_CTL_PHASE_Sleep
********************************************************************************
*
* Summary:
* Prepares the component for entering the low power mode.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_CTL_PHASE_Sleep(void)
{
SCSI_CTL_PHASE_SaveConfig();
}
/*******************************************************************************
* Function Name: SCSI_CTL_PHASE_Wakeup
********************************************************************************
*
* Summary:
* Restores the component after waking up from the low power mode.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_CTL_PHASE_Wakeup(void)
{
SCSI_CTL_PHASE_RestoreConfig();
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

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software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c Executable file
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/*******************************************************************************
* File Name: SCSI_Filtered.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware to read the value of a Status
* Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_Filtered.h"
#if !defined(SCSI_Filtered_sts_sts_reg__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Function Name: SCSI_Filtered_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Status Register.
*
* Parameters:
* None.
*
* Return:
* The current value in the Status Register.
*
*******************************************************************************/
uint8 SCSI_Filtered_Read(void)
{
return SCSI_Filtered_Status;
}
/*******************************************************************************
* Function Name: SCSI_Filtered_InterruptEnable
********************************************************************************
*
* Summary:
* Enables the Status Register interrupt.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Filtered_InterruptEnable(void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
SCSI_Filtered_Status_Aux_Ctrl |= SCSI_Filtered_STATUS_INTR_ENBL;
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: SCSI_Filtered_InterruptDisable
********************************************************************************
*
* Summary:
* Disables the Status Register interrupt.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Filtered_InterruptDisable(void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
SCSI_Filtered_Status_Aux_Ctrl &= (uint8)(~SCSI_Filtered_STATUS_INTR_ENBL);
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: SCSI_Filtered_WriteMask
********************************************************************************
*
* Summary:
* Writes the current mask value assigned to the Status Register.
*
* Parameters:
* mask: Value to write into the mask register.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Filtered_WriteMask(uint8 mask)
{
#if(SCSI_Filtered_INPUTS < 8u)
mask &= ((uint8)(1u << SCSI_Filtered_INPUTS) - 1u);
#endif /* End SCSI_Filtered_INPUTS < 8u */
SCSI_Filtered_Status_Mask = mask;
}
/*******************************************************************************
* Function Name: SCSI_Filtered_ReadMask
********************************************************************************
*
* Summary:
* Reads the current interrupt mask assigned to the Status Register.
*
* Parameters:
* None.
*
* Return:
* The value of the interrupt mask of the Status Register.
*
*******************************************************************************/
uint8 SCSI_Filtered_ReadMask(void)
{
return SCSI_Filtered_Status_Mask;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

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software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h Executable file
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/*******************************************************************************
* File Name: SCSI_Filtered.h
* Version 1.90
*
* Description:
* This file containts Status Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */
#define CY_STATUS_REG_SCSI_Filtered_H
#include "cytypes.h"
#include "CyLib.h"
/***************************************
* Data Struct Definitions
***************************************/
/* Sleep Mode API Support */
typedef struct
{
uint8 statusState;
} SCSI_Filtered_BACKUP_STRUCT;
/***************************************
* Function Prototypes
***************************************/
uint8 SCSI_Filtered_Read(void) ;
void SCSI_Filtered_InterruptEnable(void) ;
void SCSI_Filtered_InterruptDisable(void) ;
void SCSI_Filtered_WriteMask(uint8 mask) ;
uint8 SCSI_Filtered_ReadMask(void) ;
/***************************************
* API Constants
***************************************/
#define SCSI_Filtered_STATUS_INTR_ENBL 0x10u
/***************************************
* Parameter Constants
***************************************/
/* Status Register Inputs */
#define SCSI_Filtered_INPUTS 5
/***************************************
* Registers
***************************************/
/* Status Register */
#define SCSI_Filtered_Status (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG )
#define SCSI_Filtered_Status_PTR ( (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG )
#define SCSI_Filtered_Status_Mask (* (reg8 *) SCSI_Filtered_sts_sts_reg__MASK_REG )
#define SCSI_Filtered_Status_Aux_Ctrl (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG )
#endif /* End CY_STATUS_REG_SCSI_Filtered_H */
/* [] END OF FILE */

65
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c Executable file
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/*******************************************************************************
* File Name: SCSI_Glitch_Ctl.c
* Version 1.80
*
* Description:
* This file contains API to enable firmware control of a Control Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_Glitch_Ctl.h"
/* Check for removal by optimization */
#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED)
/*******************************************************************************
* Function Name: SCSI_Glitch_Ctl_Write
********************************************************************************
*
* Summary:
* Write a byte to the Control Register.
*
* Parameters:
* control: The value to be assigned to the Control Register.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Glitch_Ctl_Write(uint8 control)
{
SCSI_Glitch_Ctl_Control = control;
}
/*******************************************************************************
* Function Name: SCSI_Glitch_Ctl_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Control Register.
*
* Parameters:
* None.
*
* Return:
* Returns the current value in the Control Register.
*
*******************************************************************************/
uint8 SCSI_Glitch_Ctl_Read(void)
{
return SCSI_Glitch_Ctl_Control;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

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software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h Executable file
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/*******************************************************************************
* File Name: SCSI_Glitch_Ctl.h
* Version 1.80
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
#define CY_CONTROL_REG_SCSI_Glitch_Ctl_H
#include "cytypes.h"
/***************************************
* Data Struct Definitions
***************************************/
/* Sleep Mode API Support */
typedef struct
{
uint8 controlState;
} SCSI_Glitch_Ctl_BACKUP_STRUCT;
/***************************************
* Function Prototypes
***************************************/
void SCSI_Glitch_Ctl_Write(uint8 control) ;
uint8 SCSI_Glitch_Ctl_Read(void) ;
void SCSI_Glitch_Ctl_SaveConfig(void) ;
void SCSI_Glitch_Ctl_RestoreConfig(void) ;
void SCSI_Glitch_Ctl_Sleep(void) ;
void SCSI_Glitch_Ctl_Wakeup(void) ;
/***************************************
* Registers
***************************************/
/* Control Register */
#define SCSI_Glitch_Ctl_Control (* (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
#define SCSI_Glitch_Ctl_Control_PTR ( (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
#endif /* End CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
/* [] END OF FILE */

109
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl_PM.c Executable file
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/*******************************************************************************
* File Name: SCSI_Glitch_Ctl_PM.c
* Version 1.80
*
* Description:
* This file contains the setup, control, and status commands to support
* the component operation in the low power mode.
*
* Note:
*
********************************************************************************
* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_Glitch_Ctl.h"
/* Check for removal by optimization */
#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED)
static SCSI_Glitch_Ctl_BACKUP_STRUCT SCSI_Glitch_Ctl_backup = {0u};
/*******************************************************************************
* Function Name: SCSI_Glitch_Ctl_SaveConfig
********************************************************************************
*
* Summary:
* Saves the control register value.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_Glitch_Ctl_SaveConfig(void)
{
SCSI_Glitch_Ctl_backup.controlState = SCSI_Glitch_Ctl_Control;
}
/*******************************************************************************
* Function Name: SCSI_Glitch_Ctl_RestoreConfig
********************************************************************************
*
* Summary:
* Restores the control register value.
*
* Parameters:
* None
*
* Return:
* None
*
*
*******************************************************************************/
void SCSI_Glitch_Ctl_RestoreConfig(void)
{
SCSI_Glitch_Ctl_Control = SCSI_Glitch_Ctl_backup.controlState;
}
/*******************************************************************************
* Function Name: SCSI_Glitch_Ctl_Sleep
********************************************************************************
*
* Summary:
* Prepares the component for entering the low power mode.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_Glitch_Ctl_Sleep(void)
{
SCSI_Glitch_Ctl_SaveConfig();
}
/*******************************************************************************
* Function Name: SCSI_Glitch_Ctl_Wakeup
********************************************************************************
*
* Summary:
* Restores the component after waking up from the low power mode.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_Glitch_Ctl_Wakeup(void)
{
SCSI_Glitch_Ctl_RestoreConfig();
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

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software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In.c Executable file
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/*******************************************************************************
* File Name: SCSI_In.c
* Version 2.20
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "SCSI_In.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
SCSI_In__PORT == 15 && ((SCSI_In__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: SCSI_In_Write
****************************************************************************//**
*
* \brief Writes the value to the physical port (data output register), masking
* and shifting the bits appropriately.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This function avoids changing
* other bits in the port by using the appropriate method (read-modify-write or
* bit banding).
*
* <b>Note</b> This function should not be used on a hardware digital output pin
* as it is driven by the hardware signal attached to it.
*
* \param value
* Value to write to the component instance.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic; the Interrupt
* Service Routines (ISR) can cause corruption of this function. An ISR that
* interrupts this function and performs writes to the Pins component data
* register can cause corrupted port data. To avoid this issue, you should
* either use the Per-Pin APIs (primary method) or disable interrupts around
* this function.
*
* \funcusage
* \snippet SCSI_In_SUT.c usage_SCSI_In_Write
*******************************************************************************/
void SCSI_In_Write(uint8 value)
{
uint8 staticBits = (SCSI_In_DR & (uint8)(~SCSI_In_MASK));
SCSI_In_DR = staticBits | ((uint8)(value << SCSI_In_SHIFT) & SCSI_In_MASK);
}
/*******************************************************************************
* Function Name: SCSI_In_SetDriveMode
****************************************************************************//**
*
* \brief Sets the drive mode for each of the Pins component's pins.
*
* <b>Note</b> This affects all pins in the Pins component instance. Use the
* Per-Pin APIs if you wish to control individual pin's drive modes.
*
* \param mode
* Mode for the selected signals. Valid options are documented in
* \ref driveMode.
*
* \return
* None
*
* \sideeffect
* If you use read-modify-write operations that are not atomic, the ISR can
* cause corruption of this function. An ISR that interrupts this function
* and performs writes to the Pins component Drive Mode registers can cause
* corrupted port data. To avoid this issue, you should either use the Per-Pin
* APIs (primary method) or disable interrupts around this function.
*
* \funcusage
* \snippet SCSI_In_SUT.c usage_SCSI_In_SetDriveMode
*******************************************************************************/
void SCSI_In_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(SCSI_In_0, mode);
}
/*******************************************************************************
* Function Name: SCSI_In_Read
****************************************************************************//**
*
* \brief Reads the associated physical port (pin status register) and masks
* the required bits according to the width and bit position of the component
* instance.
*
* The pin's status register returns the current logic level present on the
* physical pin.
*
* \return
* The current value for the pins in the component as a right justified number.
*
* \funcusage
* \snippet SCSI_In_SUT.c usage_SCSI_In_Read
*******************************************************************************/
uint8 SCSI_In_Read(void)
{
return (SCSI_In_PS & SCSI_In_MASK) >> SCSI_In_SHIFT;
}
/*******************************************************************************
* Function Name: SCSI_In_ReadDataReg
****************************************************************************//**
*
* \brief Reads the associated physical port's data output register and masks
* the correct bits according to the width and bit position of the component
* instance.
*
* The data output register controls the signal applied to the physical pin in
* conjunction with the drive mode parameter. This is not the same as the
* preferred SCSI_In_Read() API because the
* SCSI_In_ReadDataReg() reads the data register instead of the status
* register. For output pins this is a useful function to determine the value
* just written to the pin.
*
* \return
* The current value of the data register masked and shifted into a right
* justified number for the component instance.
*
* \funcusage
* \snippet SCSI_In_SUT.c usage_SCSI_In_ReadDataReg
*******************************************************************************/
uint8 SCSI_In_ReadDataReg(void)
{
return (SCSI_In_DR & SCSI_In_MASK) >> SCSI_In_SHIFT;
}
/* If interrupt is connected for this Pins component */
#if defined(SCSI_In_INTSTAT)
/*******************************************************************************
* Function Name: SCSI_In_SetInterruptMode
****************************************************************************//**
*
* \brief Configures the interrupt mode for each of the Pins component's
* pins. Alternatively you may set the interrupt mode for all the pins
* specified in the Pins component.
*
* <b>Note</b> The interrupt is port-wide and therefore any enabled pin
* interrupt may trigger it.
*
* \param position
* The pin position as listed in the Pins component. You may OR these to be
* able to configure the interrupt mode of multiple pins within a Pins
* component. Or you may use SCSI_In_INTR_ALL to configure the
* interrupt mode of all the pins in the Pins component.
* - SCSI_In_0_INTR (First pin in the list)
* - SCSI_In_1_INTR (Second pin in the list)
* - ...
* - SCSI_In_INTR_ALL (All pins in Pins component)
*
* \param mode
* Interrupt mode for the selected pins. Valid options are documented in
* \ref intrMode.
*
* \return
* None
*
* \sideeffect
* It is recommended that the interrupt be disabled before calling this
* function to avoid unintended interrupt requests. Note that the interrupt
* type is port wide, and therefore will trigger for any enabled pin on the
* port.
*
* \funcusage
* \snippet SCSI_In_SUT.c usage_SCSI_In_SetInterruptMode
*******************************************************************************/
void SCSI_In_SetInterruptMode(uint16 position, uint16 mode)
{
if((position & SCSI_In_0_INTR) != 0u)
{
SCSI_In_0_INTTYPE_REG = (uint8)mode;
}
}
/*******************************************************************************
* Function Name: SCSI_In_ClearInterrupt
****************************************************************************//**
*
* \brief Clears any active interrupts attached with the component and returns
* the value of the interrupt status register allowing determination of which
* pins generated an interrupt event.
*
* \return
* The right-shifted current value of the interrupt status register. Each pin
* has one bit set if it generated an interrupt event. For example, bit 0 is
* for pin 0 and bit 1 is for pin 1 of the Pins component.
*
* \sideeffect
* Clears all bits of the physical port's interrupt status register, not just
* those associated with the Pins component.
*
* \funcusage
* \snippet SCSI_In_SUT.c usage_SCSI_In_ClearInterrupt
*******************************************************************************/
uint8 SCSI_In_ClearInterrupt(void)
{
return (SCSI_In_INTSTAT & SCSI_In_MASK) >> SCSI_In_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In.h Executable file
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/*******************************************************************************
* File Name: SCSI_In.h
* Version 2.20
*
* Description:
* This file contains Pin function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_In_H) /* Pins SCSI_In_H */
#define CY_PINS_SCSI_In_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "SCSI_In_aliases.h"
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
SCSI_In__PORT == 15 && ((SCSI_In__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
/**
* \addtogroup group_general
* @{
*/
void SCSI_In_Write(uint8 value);
void SCSI_In_SetDriveMode(uint8 mode);
uint8 SCSI_In_ReadDataReg(void);
uint8 SCSI_In_Read(void);
void SCSI_In_SetInterruptMode(uint16 position, uint16 mode);
uint8 SCSI_In_ClearInterrupt(void);
/** @} general */
/***************************************
* API Constants
***************************************/
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup driveMode Drive mode constants
* \brief Constants to be passed as "mode" parameter in the SCSI_In_SetDriveMode() function.
* @{
*/
#define SCSI_In_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define SCSI_In_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define SCSI_In_DM_RES_UP PIN_DM_RES_UP
#define SCSI_In_DM_RES_DWN PIN_DM_RES_DWN
#define SCSI_In_DM_OD_LO PIN_DM_OD_LO
#define SCSI_In_DM_OD_HI PIN_DM_OD_HI
#define SCSI_In_DM_STRONG PIN_DM_STRONG
#define SCSI_In_DM_RES_UPDWN PIN_DM_RES_UPDWN
/** @} driveMode */
/** @} group_constants */
/* Digital Port Constants */
#define SCSI_In_MASK SCSI_In__MASK
#define SCSI_In_SHIFT SCSI_In__SHIFT
#define SCSI_In_WIDTH 1u
/* Interrupt constants */
#if defined(SCSI_In__INTSTAT)
/**
* \addtogroup group_constants
* @{
*/
/** \addtogroup intrMode Interrupt constants
* \brief Constants to be passed as "mode" parameter in SCSI_In_SetInterruptMode() function.
* @{
*/
#define SCSI_In_INTR_NONE (uint16)(0x0000u)
#define SCSI_In_INTR_RISING (uint16)(0x0001u)
#define SCSI_In_INTR_FALLING (uint16)(0x0002u)
#define SCSI_In_INTR_BOTH (uint16)(0x0003u)
/** @} intrMode */
/** @} group_constants */
#define SCSI_In_INTR_MASK (0x01u)
#endif /* (SCSI_In__INTSTAT) */
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define SCSI_In_PS (* (reg8 *) SCSI_In__PS)
/* Data Register */
#define SCSI_In_DR (* (reg8 *) SCSI_In__DR)
/* Port Number */
#define SCSI_In_PRT_NUM (* (reg8 *) SCSI_In__PRT)
/* Connect to Analog Globals */
#define SCSI_In_AG (* (reg8 *) SCSI_In__AG)
/* Analog MUX bux enable */
#define SCSI_In_AMUX (* (reg8 *) SCSI_In__AMUX)
/* Bidirectional Enable */
#define SCSI_In_BIE (* (reg8 *) SCSI_In__BIE)
/* Bit-mask for Aliased Register Access */
#define SCSI_In_BIT_MASK (* (reg8 *) SCSI_In__BIT_MASK)
/* Bypass Enable */
#define SCSI_In_BYP (* (reg8 *) SCSI_In__BYP)
/* Port wide control signals */
#define SCSI_In_CTL (* (reg8 *) SCSI_In__CTL)
/* Drive Modes */
#define SCSI_In_DM0 (* (reg8 *) SCSI_In__DM0)
#define SCSI_In_DM1 (* (reg8 *) SCSI_In__DM1)
#define SCSI_In_DM2 (* (reg8 *) SCSI_In__DM2)
/* Input Buffer Disable Override */
#define SCSI_In_INP_DIS (* (reg8 *) SCSI_In__INP_DIS)
/* LCD Common or Segment Drive */
#define SCSI_In_LCD_COM_SEG (* (reg8 *) SCSI_In__LCD_COM_SEG)
/* Enable Segment LCD */
#define SCSI_In_LCD_EN (* (reg8 *) SCSI_In__LCD_EN)
/* Slew Rate Control */
#define SCSI_In_SLW (* (reg8 *) SCSI_In__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define SCSI_In_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_In__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define SCSI_In_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_In__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define SCSI_In_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_In__PRTDSI__OE_SEL0)
#define SCSI_In_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_In__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define SCSI_In_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_In__PRTDSI__OUT_SEL0)
#define SCSI_In_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_In__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define SCSI_In_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_In__PRTDSI__SYNC_OUT)
/* SIO registers */
#if defined(SCSI_In__SIO_CFG)
#define SCSI_In_SIO_HYST_EN (* (reg8 *) SCSI_In__SIO_HYST_EN)
#define SCSI_In_SIO_REG_HIFREQ (* (reg8 *) SCSI_In__SIO_REG_HIFREQ)
#define SCSI_In_SIO_CFG (* (reg8 *) SCSI_In__SIO_CFG)
#define SCSI_In_SIO_DIFF (* (reg8 *) SCSI_In__SIO_DIFF)
#endif /* (SCSI_In__SIO_CFG) */
/* Interrupt Registers */
#if defined(SCSI_In__INTSTAT)
#define SCSI_In_INTSTAT (* (reg8 *) SCSI_In__INTSTAT)
#define SCSI_In_SNAP (* (reg8 *) SCSI_In__SNAP)
#define SCSI_In_0_INTTYPE_REG (* (reg8 *) SCSI_In__0__INTTYPE)
#endif /* (SCSI_In__INTSTAT) */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_SCSI_In_H */
/* [] END OF FILE */

80
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h Executable file
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/*******************************************************************************
* File Name: SCSI_In_DBx.h
* Version 2.20
*
* Description:
* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_In_DBx_ALIASES_H) /* Pins SCSI_In_DBx_ALIASES_H */
#define CY_PINS_SCSI_In_DBx_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SCSI_In_DBx_0 (SCSI_In_DBx__0__PC)
#define SCSI_In_DBx_0_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__0__SHIFT))
#define SCSI_In_DBx_1 (SCSI_In_DBx__1__PC)
#define SCSI_In_DBx_1_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__1__SHIFT))
#define SCSI_In_DBx_2 (SCSI_In_DBx__2__PC)
#define SCSI_In_DBx_2_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__2__SHIFT))
#define SCSI_In_DBx_3 (SCSI_In_DBx__3__PC)
#define SCSI_In_DBx_3_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__3__SHIFT))
#define SCSI_In_DBx_4 (SCSI_In_DBx__4__PC)
#define SCSI_In_DBx_4_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__4__SHIFT))
#define SCSI_In_DBx_5 (SCSI_In_DBx__5__PC)
#define SCSI_In_DBx_5_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__5__SHIFT))
#define SCSI_In_DBx_6 (SCSI_In_DBx__6__PC)
#define SCSI_In_DBx_6_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__6__SHIFT))
#define SCSI_In_DBx_7 (SCSI_In_DBx__7__PC)
#define SCSI_In_DBx_7_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__7__SHIFT))
#define SCSI_In_DBx_INTR_ALL ((uint16)(SCSI_In_DBx_0_INTR| SCSI_In_DBx_1_INTR| SCSI_In_DBx_2_INTR| SCSI_In_DBx_3_INTR| SCSI_In_DBx_4_INTR| SCSI_In_DBx_5_INTR| SCSI_In_DBx_6_INTR| SCSI_In_DBx_7_INTR))
#define SCSI_In_DBx_DB0 (SCSI_In_DBx__DB0__PC)
#define SCSI_In_DBx_DB0_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__0__SHIFT))
#define SCSI_In_DBx_DB1 (SCSI_In_DBx__DB1__PC)
#define SCSI_In_DBx_DB1_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__1__SHIFT))
#define SCSI_In_DBx_DB2 (SCSI_In_DBx__DB2__PC)
#define SCSI_In_DBx_DB2_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__2__SHIFT))
#define SCSI_In_DBx_DB3 (SCSI_In_DBx__DB3__PC)
#define SCSI_In_DBx_DB3_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__3__SHIFT))
#define SCSI_In_DBx_DB4 (SCSI_In_DBx__DB4__PC)
#define SCSI_In_DBx_DB4_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__4__SHIFT))
#define SCSI_In_DBx_DB5 (SCSI_In_DBx__DB5__PC)
#define SCSI_In_DBx_DB5_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__5__SHIFT))
#define SCSI_In_DBx_DB6 (SCSI_In_DBx__DB6__PC)
#define SCSI_In_DBx_DB6_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__6__SHIFT))
#define SCSI_In_DBx_DB7 (SCSI_In_DBx__DB7__PC)
#define SCSI_In_DBx_DB7_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__7__SHIFT))
#endif /* End Pins SCSI_In_DBx_ALIASES_H */
/* [] END OF FILE */

38
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h Executable file
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/*******************************************************************************
* File Name: SCSI_In.h
* Version 2.20
*
* Description:
* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_In_ALIASES_H) /* Pins SCSI_In_ALIASES_H */
#define CY_PINS_SCSI_In_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SCSI_In_0 (SCSI_In__0__PC)
#define SCSI_In_0_INTR ((uint16)((uint16)0x0001u << SCSI_In__0__SHIFT))
#define SCSI_In_INTR_ALL ((uint16)(SCSI_In_0_INTR))
#define SCSI_In_DBP (SCSI_In__DBP__PC)
#define SCSI_In_DBP_INTR ((uint16)((uint16)0x0001u << SCSI_In__0__SHIFT))
#endif /* End Pins SCSI_In_ALIASES_H */
/* [] END OF FILE */

62
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h Executable file
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/*******************************************************************************
* File Name: SCSI_Noise.h
* Version 2.20
*
* Description:
* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_Noise_ALIASES_H) /* Pins SCSI_Noise_ALIASES_H */
#define CY_PINS_SCSI_Noise_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SCSI_Noise_0 (SCSI_Noise__0__PC)
#define SCSI_Noise_0_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__0__SHIFT))
#define SCSI_Noise_1 (SCSI_Noise__1__PC)
#define SCSI_Noise_1_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__1__SHIFT))
#define SCSI_Noise_2 (SCSI_Noise__2__PC)
#define SCSI_Noise_2_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__2__SHIFT))
#define SCSI_Noise_3 (SCSI_Noise__3__PC)
#define SCSI_Noise_3_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__3__SHIFT))
#define SCSI_Noise_4 (SCSI_Noise__4__PC)
#define SCSI_Noise_4_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__4__SHIFT))
#define SCSI_Noise_INTR_ALL ((uint16)(SCSI_Noise_0_INTR| SCSI_Noise_1_INTR| SCSI_Noise_2_INTR| SCSI_Noise_3_INTR| SCSI_Noise_4_INTR))
#define SCSI_Noise_ATN (SCSI_Noise__ATN__PC)
#define SCSI_Noise_ATN_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__0__SHIFT))
#define SCSI_Noise_BSY (SCSI_Noise__BSY__PC)
#define SCSI_Noise_BSY_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__1__SHIFT))
#define SCSI_Noise_SEL (SCSI_Noise__SEL__PC)
#define SCSI_Noise_SEL_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__2__SHIFT))
#define SCSI_Noise_RST (SCSI_Noise__RST__PC)
#define SCSI_Noise_RST_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__3__SHIFT))
#define SCSI_Noise_ACK (SCSI_Noise__ACK__PC)
#define SCSI_Noise_ACK_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__4__SHIFT))
#endif /* End Pins SCSI_Noise_ALIASES_H */
/* [] END OF FILE */

65
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.c Executable file
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/*******************************************************************************
* File Name: SCSI_Out_Bits.c
* Version 1.80
*
* Description:
* This file contains API to enable firmware control of a Control Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_Out_Bits.h"
/* Check for removal by optimization */
#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED)
/*******************************************************************************
* Function Name: SCSI_Out_Bits_Write
********************************************************************************
*
* Summary:
* Write a byte to the Control Register.
*
* Parameters:
* control: The value to be assigned to the Control Register.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Out_Bits_Write(uint8 control)
{
SCSI_Out_Bits_Control = control;
}
/*******************************************************************************
* Function Name: SCSI_Out_Bits_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Control Register.
*
* Parameters:
* None.
*
* Return:
* Returns the current value in the Control Register.
*
*******************************************************************************/
uint8 SCSI_Out_Bits_Read(void)
{
return SCSI_Out_Bits_Control;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

59
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h Executable file
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/*******************************************************************************
* File Name: SCSI_Out_Bits.h
* Version 1.80
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CONTROL_REG_SCSI_Out_Bits_H) /* CY_CONTROL_REG_SCSI_Out_Bits_H */
#define CY_CONTROL_REG_SCSI_Out_Bits_H
#include "cytypes.h"
/***************************************
* Data Struct Definitions
***************************************/
/* Sleep Mode API Support */
typedef struct
{
uint8 controlState;
} SCSI_Out_Bits_BACKUP_STRUCT;
/***************************************
* Function Prototypes
***************************************/
void SCSI_Out_Bits_Write(uint8 control) ;
uint8 SCSI_Out_Bits_Read(void) ;
void SCSI_Out_Bits_SaveConfig(void) ;
void SCSI_Out_Bits_RestoreConfig(void) ;
void SCSI_Out_Bits_Sleep(void) ;
void SCSI_Out_Bits_Wakeup(void) ;
/***************************************
* Registers
***************************************/
/* Control Register */
#define SCSI_Out_Bits_Control (* (reg8 *) SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG )
#define SCSI_Out_Bits_Control_PTR ( (reg8 *) SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG )
#endif /* End CY_CONTROL_REG_SCSI_Out_Bits_H */
/* [] END OF FILE */

109
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits_PM.c Executable file
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/*******************************************************************************
* File Name: SCSI_Out_Bits_PM.c
* Version 1.80
*
* Description:
* This file contains the setup, control, and status commands to support
* the component operation in the low power mode.
*
* Note:
*
********************************************************************************
* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_Out_Bits.h"
/* Check for removal by optimization */
#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED)
static SCSI_Out_Bits_BACKUP_STRUCT SCSI_Out_Bits_backup = {0u};
/*******************************************************************************
* Function Name: SCSI_Out_Bits_SaveConfig
********************************************************************************
*
* Summary:
* Saves the control register value.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_Out_Bits_SaveConfig(void)
{
SCSI_Out_Bits_backup.controlState = SCSI_Out_Bits_Control;
}
/*******************************************************************************
* Function Name: SCSI_Out_Bits_RestoreConfig
********************************************************************************
*
* Summary:
* Restores the control register value.
*
* Parameters:
* None
*
* Return:
* None
*
*
*******************************************************************************/
void SCSI_Out_Bits_RestoreConfig(void)
{
SCSI_Out_Bits_Control = SCSI_Out_Bits_backup.controlState;
}
/*******************************************************************************
* Function Name: SCSI_Out_Bits_Sleep
********************************************************************************
*
* Summary:
* Prepares the component for entering the low power mode.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_Out_Bits_Sleep(void)
{
SCSI_Out_Bits_SaveConfig();
}
/*******************************************************************************
* Function Name: SCSI_Out_Bits_Wakeup
********************************************************************************
*
* Summary:
* Restores the component after waking up from the low power mode.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_Out_Bits_Wakeup(void)
{
SCSI_Out_Bits_RestoreConfig();
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

65
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.c Executable file
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/*******************************************************************************
* File Name: SCSI_Out_Ctl.c
* Version 1.80
*
* Description:
* This file contains API to enable firmware control of a Control Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_Out_Ctl.h"
/* Check for removal by optimization */
#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED)
/*******************************************************************************
* Function Name: SCSI_Out_Ctl_Write
********************************************************************************
*
* Summary:
* Write a byte to the Control Register.
*
* Parameters:
* control: The value to be assigned to the Control Register.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Out_Ctl_Write(uint8 control)
{
SCSI_Out_Ctl_Control = control;
}
/*******************************************************************************
* Function Name: SCSI_Out_Ctl_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Control Register.
*
* Parameters:
* None.
*
* Return:
* Returns the current value in the Control Register.
*
*******************************************************************************/
uint8 SCSI_Out_Ctl_Read(void)
{
return SCSI_Out_Ctl_Control;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

59
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h Executable file
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/*******************************************************************************
* File Name: SCSI_Out_Ctl.h
* Version 1.80
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CONTROL_REG_SCSI_Out_Ctl_H) /* CY_CONTROL_REG_SCSI_Out_Ctl_H */
#define CY_CONTROL_REG_SCSI_Out_Ctl_H
#include "cytypes.h"
/***************************************
* Data Struct Definitions
***************************************/
/* Sleep Mode API Support */
typedef struct
{
uint8 controlState;
} SCSI_Out_Ctl_BACKUP_STRUCT;
/***************************************
* Function Prototypes
***************************************/
void SCSI_Out_Ctl_Write(uint8 control) ;
uint8 SCSI_Out_Ctl_Read(void) ;
void SCSI_Out_Ctl_SaveConfig(void) ;
void SCSI_Out_Ctl_RestoreConfig(void) ;
void SCSI_Out_Ctl_Sleep(void) ;
void SCSI_Out_Ctl_Wakeup(void) ;
/***************************************
* Registers
***************************************/
/* Control Register */
#define SCSI_Out_Ctl_Control (* (reg8 *) SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG )
#define SCSI_Out_Ctl_Control_PTR ( (reg8 *) SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG )
#endif /* End CY_CONTROL_REG_SCSI_Out_Ctl_H */
/* [] END OF FILE */

109
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl_PM.c Executable file
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/*******************************************************************************
* File Name: SCSI_Out_Ctl_PM.c
* Version 1.80
*
* Description:
* This file contains the setup, control, and status commands to support
* the component operation in the low power mode.
*
* Note:
*
********************************************************************************
* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_Out_Ctl.h"
/* Check for removal by optimization */
#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED)
static SCSI_Out_Ctl_BACKUP_STRUCT SCSI_Out_Ctl_backup = {0u};
/*******************************************************************************
* Function Name: SCSI_Out_Ctl_SaveConfig
********************************************************************************
*
* Summary:
* Saves the control register value.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_Out_Ctl_SaveConfig(void)
{
SCSI_Out_Ctl_backup.controlState = SCSI_Out_Ctl_Control;
}
/*******************************************************************************
* Function Name: SCSI_Out_Ctl_RestoreConfig
********************************************************************************
*
* Summary:
* Restores the control register value.
*
* Parameters:
* None
*
* Return:
* None
*
*
*******************************************************************************/
void SCSI_Out_Ctl_RestoreConfig(void)
{
SCSI_Out_Ctl_Control = SCSI_Out_Ctl_backup.controlState;
}
/*******************************************************************************
* Function Name: SCSI_Out_Ctl_Sleep
********************************************************************************
*
* Summary:
* Prepares the component for entering the low power mode.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_Out_Ctl_Sleep(void)
{
SCSI_Out_Ctl_SaveConfig();
}
/*******************************************************************************
* Function Name: SCSI_Out_Ctl_Wakeup
********************************************************************************
*
* Summary:
* Restores the component after waking up from the low power mode.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_Out_Ctl_Wakeup(void)
{
SCSI_Out_Ctl_RestoreConfig();
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

80
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h Executable file
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/*******************************************************************************
* File Name: SCSI_Out_DBx.h
* Version 2.20
*
* Description:
* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_Out_DBx_ALIASES_H) /* Pins SCSI_Out_DBx_ALIASES_H */
#define CY_PINS_SCSI_Out_DBx_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC)
#define SCSI_Out_DBx_0_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__0__SHIFT))
#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC)
#define SCSI_Out_DBx_1_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__1__SHIFT))
#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC)
#define SCSI_Out_DBx_2_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__2__SHIFT))
#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC)
#define SCSI_Out_DBx_3_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__3__SHIFT))
#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC)
#define SCSI_Out_DBx_4_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__4__SHIFT))
#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC)
#define SCSI_Out_DBx_5_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__5__SHIFT))
#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC)
#define SCSI_Out_DBx_6_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__6__SHIFT))
#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC)
#define SCSI_Out_DBx_7_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__7__SHIFT))
#define SCSI_Out_DBx_INTR_ALL ((uint16)(SCSI_Out_DBx_0_INTR| SCSI_Out_DBx_1_INTR| SCSI_Out_DBx_2_INTR| SCSI_Out_DBx_3_INTR| SCSI_Out_DBx_4_INTR| SCSI_Out_DBx_5_INTR| SCSI_Out_DBx_6_INTR| SCSI_Out_DBx_7_INTR))
#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC)
#define SCSI_Out_DBx_DB0_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__0__SHIFT))
#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC)
#define SCSI_Out_DBx_DB1_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__1__SHIFT))
#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC)
#define SCSI_Out_DBx_DB2_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__2__SHIFT))
#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC)
#define SCSI_Out_DBx_DB3_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__3__SHIFT))
#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC)
#define SCSI_Out_DBx_DB4_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__4__SHIFT))
#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC)
#define SCSI_Out_DBx_DB5_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__5__SHIFT))
#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC)
#define SCSI_Out_DBx_DB6_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__6__SHIFT))
#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC)
#define SCSI_Out_DBx_DB7_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__7__SHIFT))
#endif /* End Pins SCSI_Out_DBx_ALIASES_H */
/* [] END OF FILE */

80
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h Executable file
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/*******************************************************************************
* File Name: SCSI_Out.h
* Version 2.20
*
* Description:
* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_Out_ALIASES_H) /* Pins SCSI_Out_ALIASES_H */
#define CY_PINS_SCSI_Out_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SCSI_Out_0 (SCSI_Out__0__PC)
#define SCSI_Out_0_INTR ((uint16)((uint16)0x0001u << SCSI_Out__0__SHIFT))
#define SCSI_Out_1 (SCSI_Out__1__PC)
#define SCSI_Out_1_INTR ((uint16)((uint16)0x0001u << SCSI_Out__1__SHIFT))
#define SCSI_Out_2 (SCSI_Out__2__PC)
#define SCSI_Out_2_INTR ((uint16)((uint16)0x0001u << SCSI_Out__2__SHIFT))
#define SCSI_Out_3 (SCSI_Out__3__PC)
#define SCSI_Out_3_INTR ((uint16)((uint16)0x0001u << SCSI_Out__3__SHIFT))
#define SCSI_Out_4 (SCSI_Out__4__PC)
#define SCSI_Out_4_INTR ((uint16)((uint16)0x0001u << SCSI_Out__4__SHIFT))
#define SCSI_Out_5 (SCSI_Out__5__PC)
#define SCSI_Out_5_INTR ((uint16)((uint16)0x0001u << SCSI_Out__5__SHIFT))
#define SCSI_Out_6 (SCSI_Out__6__PC)
#define SCSI_Out_6_INTR ((uint16)((uint16)0x0001u << SCSI_Out__6__SHIFT))
#define SCSI_Out_7 (SCSI_Out__7__PC)
#define SCSI_Out_7_INTR ((uint16)((uint16)0x0001u << SCSI_Out__7__SHIFT))
#define SCSI_Out_INTR_ALL ((uint16)(SCSI_Out_0_INTR| SCSI_Out_1_INTR| SCSI_Out_2_INTR| SCSI_Out_3_INTR| SCSI_Out_4_INTR| SCSI_Out_5_INTR| SCSI_Out_6_INTR| SCSI_Out_7_INTR))
#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC)
#define SCSI_Out_DBP_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__0__SHIFT))
#define SCSI_Out_BSY (SCSI_Out__BSY__PC)
#define SCSI_Out_BSY_INTR ((uint16)((uint16)0x0001u << SCSI_Out__1__SHIFT))
#define SCSI_Out_RST (SCSI_Out__RST__PC)
#define SCSI_Out_RST_INTR ((uint16)((uint16)0x0001u << SCSI_Out__2__SHIFT))
#define SCSI_Out_MSG_raw (SCSI_Out__MSG_raw__PC)
#define SCSI_Out_MSG_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__3__SHIFT))
#define SCSI_Out_SEL (SCSI_Out__SEL__PC)
#define SCSI_Out_SEL_INTR ((uint16)((uint16)0x0001u << SCSI_Out__4__SHIFT))
#define SCSI_Out_CD_raw (SCSI_Out__CD_raw__PC)
#define SCSI_Out_CD_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__5__SHIFT))
#define SCSI_Out_REQ (SCSI_Out__REQ__PC)
#define SCSI_Out_REQ_INTR ((uint16)((uint16)0x0001u << SCSI_Out__6__SHIFT))
#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC)
#define SCSI_Out_IO_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__7__SHIFT))
#endif /* End Pins SCSI_Out_ALIASES_H */
/* [] END OF FILE */

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software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c Executable file
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/*******************************************************************************
* File Name: SCSI_Parity_Error.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware to read the value of a Status
* Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_Parity_Error.h"
#if !defined(SCSI_Parity_Error_sts_sts_reg__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Function Name: SCSI_Parity_Error_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Status Register.
*
* Parameters:
* None.
*
* Return:
* The current value in the Status Register.
*
*******************************************************************************/
uint8 SCSI_Parity_Error_Read(void)
{
return SCSI_Parity_Error_Status;
}
/*******************************************************************************
* Function Name: SCSI_Parity_Error_InterruptEnable
********************************************************************************
*
* Summary:
* Enables the Status Register interrupt.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Parity_Error_InterruptEnable(void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
SCSI_Parity_Error_Status_Aux_Ctrl |= SCSI_Parity_Error_STATUS_INTR_ENBL;
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: SCSI_Parity_Error_InterruptDisable
********************************************************************************
*
* Summary:
* Disables the Status Register interrupt.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Parity_Error_InterruptDisable(void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
SCSI_Parity_Error_Status_Aux_Ctrl &= (uint8)(~SCSI_Parity_Error_STATUS_INTR_ENBL);
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: SCSI_Parity_Error_WriteMask
********************************************************************************
*
* Summary:
* Writes the current mask value assigned to the Status Register.
*
* Parameters:
* mask: Value to write into the mask register.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Parity_Error_WriteMask(uint8 mask)
{
#if(SCSI_Parity_Error_INPUTS < 8u)
mask &= ((uint8)(1u << SCSI_Parity_Error_INPUTS) - 1u);
#endif /* End SCSI_Parity_Error_INPUTS < 8u */
SCSI_Parity_Error_Status_Mask = mask;
}
/*******************************************************************************
* Function Name: SCSI_Parity_Error_ReadMask
********************************************************************************
*
* Summary:
* Reads the current interrupt mask assigned to the Status Register.
*
* Parameters:
* None.
*
* Return:
* The value of the interrupt mask of the Status Register.
*
*******************************************************************************/
uint8 SCSI_Parity_Error_ReadMask(void)
{
return SCSI_Parity_Error_Status_Mask;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

75
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h Executable file
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/*******************************************************************************
* File Name: SCSI_Parity_Error.h
* Version 1.90
*
* Description:
* This file containts Status Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */
#define CY_STATUS_REG_SCSI_Parity_Error_H
#include "cytypes.h"
#include "CyLib.h"
/***************************************
* Data Struct Definitions
***************************************/
/* Sleep Mode API Support */
typedef struct
{
uint8 statusState;
} SCSI_Parity_Error_BACKUP_STRUCT;
/***************************************
* Function Prototypes
***************************************/
uint8 SCSI_Parity_Error_Read(void) ;
void SCSI_Parity_Error_InterruptEnable(void) ;
void SCSI_Parity_Error_InterruptDisable(void) ;
void SCSI_Parity_Error_WriteMask(uint8 mask) ;
uint8 SCSI_Parity_Error_ReadMask(void) ;
/***************************************
* API Constants
***************************************/
#define SCSI_Parity_Error_STATUS_INTR_ENBL 0x10u
/***************************************
* Parameter Constants
***************************************/
/* Status Register Inputs */
#define SCSI_Parity_Error_INPUTS 1
/***************************************
* Registers
***************************************/
/* Status Register */
#define SCSI_Parity_Error_Status (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
#define SCSI_Parity_Error_Status_PTR ( (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
#define SCSI_Parity_Error_Status_Mask (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__MASK_REG )
#define SCSI_Parity_Error_Status_Aux_Ctrl (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG )
#endif /* End CY_STATUS_REG_SCSI_Parity_Error_H */
/* [] END OF FILE */

137
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST.c Normal file
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/*******************************************************************************
* File Name: SCSI_RST.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "SCSI_RST.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
SCSI_RST__PORT == 15 && ((SCSI_RST__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: SCSI_RST_Write
********************************************************************************
*
* Summary:
* Assign a new value to the digital port's data output register.
*
* Parameters:
* prtValue: The value to be assigned to the Digital Port.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_Write(uint8 value)
{
uint8 staticBits = (SCSI_RST_DR & (uint8)(~SCSI_RST_MASK));
SCSI_RST_DR = staticBits | ((uint8)(value << SCSI_RST_SHIFT) & SCSI_RST_MASK);
}
/*******************************************************************************
* Function Name: SCSI_RST_SetDriveMode
********************************************************************************
*
* Summary:
* Change the drive mode on the pins of the port.
*
* Parameters:
* mode: Change the pins to this drive mode.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(SCSI_RST_0, mode);
}
/*******************************************************************************
* Function Name: SCSI_RST_Read
********************************************************************************
*
* Summary:
* Read the current value on the pins of the Digital Port in right justified
* form.
*
* Parameters:
* None
*
* Return:
* Returns the current value of the Digital Port as a right justified number
*
* Note:
* Macro SCSI_RST_ReadPS calls this function.
*
*******************************************************************************/
uint8 SCSI_RST_Read(void)
{
return (SCSI_RST_PS & SCSI_RST_MASK) >> SCSI_RST_SHIFT;
}
/*******************************************************************************
* Function Name: SCSI_RST_ReadDataReg
********************************************************************************
*
* Summary:
* Read the current value assigned to a Digital Port's data output register
*
* Parameters:
* None
*
* Return:
* Returns the current value assigned to the Digital Port's data output register
*
*******************************************************************************/
uint8 SCSI_RST_ReadDataReg(void)
{
return (SCSI_RST_DR & SCSI_RST_MASK) >> SCSI_RST_SHIFT;
}
/* If Interrupts Are Enabled for this Pins component */
#if defined(SCSI_RST_INTSTAT)
/*******************************************************************************
* Function Name: SCSI_RST_ClearInterrupt
********************************************************************************
* Summary:
* Clears any active interrupts attached to port and returns the value of the
* interrupt status register.
*
* Parameters:
* None
*
* Return:
* Returns the value of the interrupt status register
*
*******************************************************************************/
uint8 SCSI_RST_ClearInterrupt(void)
{
return (SCSI_RST_INTSTAT & SCSI_RST_MASK) >> SCSI_RST_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

130
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/*******************************************************************************
* File Name: SCSI_RST.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_RST_H) /* Pins SCSI_RST_H */
#define CY_PINS_SCSI_RST_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "SCSI_RST_aliases.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component cy_pins_v1_90 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
SCSI_RST__PORT == 15 && ((SCSI_RST__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
void SCSI_RST_Write(uint8 value) ;
void SCSI_RST_SetDriveMode(uint8 mode) ;
uint8 SCSI_RST_ReadDataReg(void) ;
uint8 SCSI_RST_Read(void) ;
uint8 SCSI_RST_ClearInterrupt(void) ;
/***************************************
* API Constants
***************************************/
/* Drive Modes */
#define SCSI_RST_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define SCSI_RST_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define SCSI_RST_DM_RES_UP PIN_DM_RES_UP
#define SCSI_RST_DM_RES_DWN PIN_DM_RES_DWN
#define SCSI_RST_DM_OD_LO PIN_DM_OD_LO
#define SCSI_RST_DM_OD_HI PIN_DM_OD_HI
#define SCSI_RST_DM_STRONG PIN_DM_STRONG
#define SCSI_RST_DM_RES_UPDWN PIN_DM_RES_UPDWN
/* Digital Port Constants */
#define SCSI_RST_MASK SCSI_RST__MASK
#define SCSI_RST_SHIFT SCSI_RST__SHIFT
#define SCSI_RST_WIDTH 1u
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define SCSI_RST_PS (* (reg8 *) SCSI_RST__PS)
/* Data Register */
#define SCSI_RST_DR (* (reg8 *) SCSI_RST__DR)
/* Port Number */
#define SCSI_RST_PRT_NUM (* (reg8 *) SCSI_RST__PRT)
/* Connect to Analog Globals */
#define SCSI_RST_AG (* (reg8 *) SCSI_RST__AG)
/* Analog MUX bux enable */
#define SCSI_RST_AMUX (* (reg8 *) SCSI_RST__AMUX)
/* Bidirectional Enable */
#define SCSI_RST_BIE (* (reg8 *) SCSI_RST__BIE)
/* Bit-mask for Aliased Register Access */
#define SCSI_RST_BIT_MASK (* (reg8 *) SCSI_RST__BIT_MASK)
/* Bypass Enable */
#define SCSI_RST_BYP (* (reg8 *) SCSI_RST__BYP)
/* Port wide control signals */
#define SCSI_RST_CTL (* (reg8 *) SCSI_RST__CTL)
/* Drive Modes */
#define SCSI_RST_DM0 (* (reg8 *) SCSI_RST__DM0)
#define SCSI_RST_DM1 (* (reg8 *) SCSI_RST__DM1)
#define SCSI_RST_DM2 (* (reg8 *) SCSI_RST__DM2)
/* Input Buffer Disable Override */
#define SCSI_RST_INP_DIS (* (reg8 *) SCSI_RST__INP_DIS)
/* LCD Common or Segment Drive */
#define SCSI_RST_LCD_COM_SEG (* (reg8 *) SCSI_RST__LCD_COM_SEG)
/* Enable Segment LCD */
#define SCSI_RST_LCD_EN (* (reg8 *) SCSI_RST__LCD_EN)
/* Slew Rate Control */
#define SCSI_RST_SLW (* (reg8 *) SCSI_RST__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define SCSI_RST_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_RST__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define SCSI_RST_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_RST__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define SCSI_RST_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_RST__PRTDSI__OE_SEL0)
#define SCSI_RST_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_RST__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define SCSI_RST_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_RST__PRTDSI__OUT_SEL0)
#define SCSI_RST_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_RST__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define SCSI_RST_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_RST__PRTDSI__SYNC_OUT)
#if defined(SCSI_RST__INTSTAT) /* Interrupt Registers */
#define SCSI_RST_INTSTAT (* (reg8 *) SCSI_RST__INTSTAT)
#define SCSI_RST_SNAP (* (reg8 *) SCSI_RST__SNAP)
#endif /* Interrupt Registers */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_SCSI_RST_H */
/* [] END OF FILE */

409
software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c Executable file
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/*******************************************************************************
* File Name: SCSI_RST_ISR.c
* Version 1.70
*
* Description:
* API for controlling the state of an interrupt.
*
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include <CyLib.h>
#include <SCSI_RST_ISR.h>
#if !defined(SCSI_RST_ISR__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Place your includes, defines and code here
********************************************************************************/
/* `#START SCSI_RST_ISR_intc` */
/* `#END` */
#ifndef CYINT_IRQ_BASE
#define CYINT_IRQ_BASE 16
#endif /* CYINT_IRQ_BASE */
#ifndef CYINT_VECT_TABLE
#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
#endif /* CYINT_VECT_TABLE */
/* Declared in startup, used to set unused interrupts to. */
CY_ISR_PROTO(IntDefaultHandler);
/*******************************************************************************
* Function Name: SCSI_RST_ISR_Start
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it. This function disables the interrupt,
* sets the default interrupt vector, sets the priority from the value in the
* Design Wide Resources Interrupt Editor, then enables the interrupt to the
* interrupt controller.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_Start(void)
{
/* For all we know the interrupt is active. */
SCSI_RST_ISR_Disable();
/* Set the ISR to point to the SCSI_RST_ISR Interrupt. */
SCSI_RST_ISR_SetVector(&SCSI_RST_ISR_Interrupt);
/* Set the priority. */
SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER);
/* Enable it. */
SCSI_RST_ISR_Enable();
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_StartEx
********************************************************************************
*
* Summary:
* Sets up the interrupt and enables it. This function disables the interrupt,
* sets the interrupt vector based on the address passed in, sets the priority
* from the value in the Design Wide Resources Interrupt Editor, then enables
* the interrupt to the interrupt controller.
*
* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
* used to provide consistent definition across compilers:
*
* Function definition example:
* CY_ISR(MyISR)
* {
* }
* Function prototype example:
* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_StartEx(cyisraddress address)
{
/* For all we know the interrupt is active. */
SCSI_RST_ISR_Disable();
/* Set the ISR to point to the SCSI_RST_ISR Interrupt. */
SCSI_RST_ISR_SetVector(address);
/* Set the priority. */
SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER);
/* Enable it. */
SCSI_RST_ISR_Enable();
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_Stop
********************************************************************************
*
* Summary:
* Disables and removes the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_Stop(void)
{
/* Disable this interrupt. */
SCSI_RST_ISR_Disable();
/* Set the ISR to point to the passive one. */
SCSI_RST_ISR_SetVector(&IntDefaultHandler);
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_Interrupt
********************************************************************************
*
* Summary:
* The default Interrupt Service Routine for SCSI_RST_ISR.
*
* Add custom code between the coments to keep the next version of this file
* from over writting your code.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
CY_ISR(SCSI_RST_ISR_Interrupt)
{
#ifdef SCSI_RST_ISR_INTERRUPT_INTERRUPT_CALLBACK
SCSI_RST_ISR_Interrupt_InterruptCallback();
#endif /* SCSI_RST_ISR_INTERRUPT_INTERRUPT_CALLBACK */
/* Place your Interrupt code here. */
/* `#START SCSI_RST_ISR_Interrupt` */
/* `#END` */
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_SetVector
********************************************************************************
*
* Summary:
* Change the ISR vector for the Interrupt. Note calling SCSI_RST_ISR_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_RST_ISR_StartEx instead.
*
* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
* used to provide consistent definition across compilers:
*
* Function definition example:
* CY_ISR(MyISR)
* {
* }
*
* Function prototype example:
* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_SetVector(cyisraddress address)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER] = address;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_GetVector
********************************************************************************
*
* Summary:
* Gets the "address" of the current ISR vector for the Interrupt.
*
* Parameters:
* None
*
* Return:
* Address of the ISR in the interrupt vector table.
*
*******************************************************************************/
cyisraddress SCSI_RST_ISR_GetVector(void)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER];
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_SetPriority
********************************************************************************
*
* Summary:
* Sets the Priority of the Interrupt.
*
* Note calling SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx will
* override any effect this API would have had. This API should only be called
* after SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called.
* To set the initial priority for the component, use the Design-Wide Resources
* Interrupt Editor.
*
* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
* priority: Priority of the interrupt, 0 being the highest priority
* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_SetPriority(uint8 priority)
{
*SCSI_RST_ISR_INTC_PRIOR = priority << 5;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_GetPriority
********************************************************************************
*
* Summary:
* Gets the Priority of the Interrupt.
*
* Parameters:
* None
*
* Return:
* Priority of the interrupt, 0 being the highest priority
* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SCSI_RST_ISR_GetPriority(void)
{
uint8 priority;
priority = *SCSI_RST_ISR_INTC_PRIOR >> 5;
return priority;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_Enable
********************************************************************************
*
* Summary:
* Enables the interrupt to the interrupt controller. Do not call this function
* unless ISR_Start() has been called or the functionality of the ISR_Start()
* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_Enable(void)
{
/* Enable the general interrupt. */
*SCSI_RST_ISR_INTC_SET_EN = SCSI_RST_ISR__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_GetState
********************************************************************************
*
* Summary:
* Gets the state (enabled, disabled) of the Interrupt.
*
* Parameters:
* None
*
* Return:
* 1 if enabled, 0 if disabled.
*
*******************************************************************************/
uint8 SCSI_RST_ISR_GetState(void)
{
/* Get the state of the general interrupt. */
return ((*SCSI_RST_ISR_INTC_SET_EN & (uint32)SCSI_RST_ISR__INTC_MASK) != 0u) ? 1u:0u;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_Disable
********************************************************************************
*
* Summary:
* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_Disable(void)
{
/* Disable the general interrupt. */
*SCSI_RST_ISR_INTC_CLR_EN = SCSI_RST_ISR__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_SetPending
********************************************************************************
*
* Summary:
* Causes the Interrupt to enter the pending state, a software method of
* generating the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
* Side Effects:
* If interrupts are enabled and the interrupt is set up properly, the ISR is
* entered (depending on the priority of this interrupt and other pending
* interrupts).
*
*******************************************************************************/
void SCSI_RST_ISR_SetPending(void)
{
*SCSI_RST_ISR_INTC_SET_PD = SCSI_RST_ISR__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_ClearPending
********************************************************************************
*
* Summary:
* Clears a pending interrupt in the interrupt controller.
*
* Note Some interrupt sources are clear-on-read and require the block
* interrupt/status register to be read/cleared with the appropriate block API
* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_ClearPending(void)
{
*SCSI_RST_ISR_INTC_CLR_PD = SCSI_RST_ISR__INTC_MASK;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

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