From 381a4f7d673352746da343662bd2ddf5f381fc87 Mon Sep 17 00:00:00 2001 From: Michael McMaster Date: Wed, 19 Sep 2018 22:10:24 +1000 Subject: [PATCH] Fix for multiple devices on the scsi bus. --- CHANGELOG | 3 + software/SCSI2SD/src/config.c | 2 +- software/SCSI2SD/src/disk.c | 10 +- software/SCSI2SD/src/scsi.c | 16 +- software/SCSI2SD/src/scsi.h | 3 +- .../Generated_Source/PSoC5/SCSI_CTL_PHASE.h | 10 +- .../Generated_Source/PSoC5/SCSI_Filtered.h | 12 +- .../Generated_Source/PSoC5/SCSI_Glitch_Ctl.h | 10 +- .../Generated_Source/PSoC5/SCSI_Out_Bits.h | 10 +- .../Generated_Source/PSoC5/SCSI_Out_Ctl.h | 10 +- .../PSoC5/SCSI_Parity_Error.h | 12 +- .../Generated_Source/PSoC5/SDCard.h | 10 +- .../Generated_Source/PSoC5/cydevice.h | 4 +- .../Generated_Source/PSoC5/cydevice_trm.h | 4 +- .../Generated_Source/PSoC5/cydevicegnu.inc | 4 +- .../PSoC5/cydevicegnu_trm.inc | 4 +- .../Generated_Source/PSoC5/cydeviceiar.inc | 4 +- .../PSoC5/cydeviceiar_trm.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv_trm.inc | 4 +- .../Generated_Source/PSoC5/cyfitter.h | 2210 ++++++++--------- .../Generated_Source/PSoC5/cyfitter_cfg.c | 1655 ++++++------ .../Generated_Source/PSoC5/cyfitter_cfg.h | 6 +- .../Generated_Source/PSoC5/cyfittergnu.inc | 2208 ++++++++-------- .../Generated_Source/PSoC5/cyfitteriar.inc | 2207 ++++++++-------- .../Generated_Source/PSoC5/cyfitterrv.inc | 2207 ++++++++-------- .../Generated_Source/PSoC5/cymetadata.c | 10 +- .../Generated_Source/PSoC5/project.h | 4 +- .../SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 241920 -> 254155 bytes .../SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj | 298 ++- .../Generated_Source/PSoC5/SCSI_CTL_PHASE.h | 10 +- .../Generated_Source/PSoC5/SCSI_Filtered.h | 12 +- .../Generated_Source/PSoC5/SCSI_Glitch_Ctl.h | 10 +- .../Generated_Source/PSoC5/SCSI_Out_Bits.h | 10 +- .../Generated_Source/PSoC5/SCSI_Out_Ctl.h | 10 +- .../PSoC5/SCSI_Parity_Error.h | 12 +- .../Generated_Source/PSoC5/SDCard.h | 10 +- .../Generated_Source/PSoC5/cydevice.h | 4 +- .../Generated_Source/PSoC5/cydevice_trm.h | 4 +- .../Generated_Source/PSoC5/cydevicegnu.inc | 4 +- .../PSoC5/cydevicegnu_trm.inc | 4 +- .../Generated_Source/PSoC5/cydeviceiar.inc | 4 +- .../PSoC5/cydeviceiar_trm.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv_trm.inc | 4 +- .../Generated_Source/PSoC5/cyfitter.h | 2134 ++++++++-------- .../Generated_Source/PSoC5/cyfitter_cfg.c | 1360 +++++----- .../Generated_Source/PSoC5/cyfitter_cfg.h | 6 +- .../Generated_Source/PSoC5/cyfittergnu.inc | 2132 ++++++++-------- .../Generated_Source/PSoC5/cyfitteriar.inc | 2131 ++++++++-------- .../Generated_Source/PSoC5/cyfitterrv.inc | 2131 ++++++++-------- .../Generated_Source/PSoC5/cymetadata.c | 10 +- .../Generated_Source/PSoC5/project.h | 4 +- .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 238287 -> 251892 bytes .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj | 262 +- .../Generated_Source/PSoC5/SCSI_CTL_PHASE.h | 10 +- .../Generated_Source/PSoC5/SCSI_Filtered.h | 12 +- .../Generated_Source/PSoC5/SCSI_Glitch_Ctl.h | 10 +- .../Generated_Source/PSoC5/SCSI_Out_Bits.h | 10 +- .../Generated_Source/PSoC5/SCSI_Out_Ctl.h | 10 +- .../PSoC5/SCSI_Parity_Error.h | 12 +- .../Generated_Source/PSoC5/SDCard.h | 10 +- .../Generated_Source/PSoC5/cydevice.h | 4 +- .../Generated_Source/PSoC5/cydevice_trm.h | 4 +- .../Generated_Source/PSoC5/cydevicegnu.inc | 4 +- .../PSoC5/cydevicegnu_trm.inc | 4 +- .../Generated_Source/PSoC5/cydeviceiar.inc | 4 +- .../PSoC5/cydeviceiar_trm.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv_trm.inc | 4 +- .../Generated_Source/PSoC5/cyfitter.h | 2094 ++++++++-------- .../Generated_Source/PSoC5/cyfitter_cfg.c | 1519 +++++------ .../Generated_Source/PSoC5/cyfitter_cfg.h | 6 +- .../Generated_Source/PSoC5/cyfittergnu.inc | 2092 ++++++++-------- .../Generated_Source/PSoC5/cyfitteriar.inc | 2091 ++++++++-------- .../Generated_Source/PSoC5/cyfitterrv.inc | 2091 ++++++++-------- .../Generated_Source/PSoC5/cymetadata.c | 10 +- .../Generated_Source/PSoC5/project.h | 4 +- .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 242777 -> 255983 bytes .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyprj | 264 +- 80 files changed, 15896 insertions(+), 15602 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 02c01c5..3bd0152 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,6 @@ +2018XXXX 4.8.1 + - Fix bug when writing with multiple SCSI devices on the chain + 20180416 4.8 - Fix Unit Serial Number inquiry page to use return configured serial number - Apple mode pages now only sent when in Apple mode. diff --git a/software/SCSI2SD/src/config.c b/software/SCSI2SD/src/config.c index 70948f7..ce84013 100755 --- a/software/SCSI2SD/src/config.c +++ b/software/SCSI2SD/src/config.c @@ -31,7 +31,7 @@ #include -static const uint16_t FIRMWARE_VERSION = 0x0480; +static const uint16_t FIRMWARE_VERSION = 0x0481; // 1 flash row static const uint8_t DEFAULT_CONFIG[256] = diff --git a/software/SCSI2SD/src/disk.c b/software/SCSI2SD/src/disk.c index b825164..b8f6c88 100755 --- a/software/SCSI2SD/src/disk.c +++ b/software/SCSI2SD/src/disk.c @@ -637,6 +637,7 @@ void scsiDiskPoll() int i = 0; int scsiDisconnected = 0; int scsiComplete = 0; + int clearBSY = 0; uint32_t lastActivityTime = getTime_ms(); int scsiActive = 0; int sdActive = 0; @@ -757,16 +758,13 @@ void scsiDiskPoll() scsiComplete = 1; process_Status(); - process_MessageIn(); // Will go to BUS_FREE state - - // Try and prevent anyone else using the SCSI bus while we're not ready. - SCSI_SetPin(SCSI_Out_BSY); + clearBSY = process_MessageIn(0); // Will go to BUS_FREE state but keeps BSY asserted } } - if (scsiComplete) + if (clearBSY) { - SCSI_ClearPin(SCSI_Out_BSY); + enter_BusFree(); } while ( !scsiDev.resetFlag && diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c index 657868d..db37854 100755 --- a/software/SCSI2SD/src/scsi.c +++ b/software/SCSI2SD/src/scsi.c @@ -40,7 +40,6 @@ ScsiDevice scsiDev; static void enter_SelectionPhase(void); static void process_SelectionPhase(void); -static void enter_BusFree(void); static void enter_MessageIn(uint8 message); static void enter_Status(uint8 status); static void enter_DataIn(int len); @@ -50,7 +49,7 @@ static void process_Command(void); static void doReserveRelease(void); -static void enter_BusFree() +void enter_BusFree() { // This delay probably isn't needed for most SCSI hosts, but it won't // hurt either. It's possible some of the samplers needed this delay. @@ -84,7 +83,7 @@ static void enter_MessageIn(uint8 message) scsiDev.phase = MESSAGE_IN; } -void process_MessageIn() +int process_MessageIn(int releaseBusFree) { scsiEnterPhase(MESSAGE_IN); scsiWriteByte(scsiDev.msgIn); @@ -94,6 +93,7 @@ void process_MessageIn() // If there was a parity error, we go // back to MESSAGE_OUT first, get out parity error message, then come // back here. + return 0; } else if ((scsiDev.msgIn == MSG_LINKED_COMMAND_COMPLETE) || (scsiDev.msgIn == MSG_LINKED_COMMAND_COMPLETE_WITH_FLAG)) @@ -107,10 +107,16 @@ void process_MessageIn() scsiDev.status = GOOD; transfer.blocks = 0; transfer.currentBlock = 0; + return 0; } - else /*if (scsiDev.msgIn == MSG_COMMAND_COMPLETE)*/ + else if (releaseBusFree) /*if (scsiDev.msgIn == MSG_COMMAND_COMPLETE)*/ { enter_BusFree(); + return 1; + } + else + { + return 1; } } @@ -1008,7 +1014,7 @@ void scsiPoll(void) } else { - process_MessageIn(); + process_MessageIn(1); } break; diff --git a/software/SCSI2SD/src/scsi.h b/software/SCSI2SD/src/scsi.h index 63cc83f..d1a9f54 100755 --- a/software/SCSI2SD/src/scsi.h +++ b/software/SCSI2SD/src/scsi.h @@ -159,7 +159,8 @@ typedef struct extern ScsiDevice scsiDev; void process_Status(void); -void process_MessageIn(void); +int process_MessageIn(int releaseBusFree); +void enter_BusFree(void); void scsiInit(void); void scsiPoll(void); diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h index f974855..4db2bae 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h @@ -17,7 +17,15 @@ #if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */ #define CY_CONTROL_REG_SCSI_CTL_PHASE_H -#include "cytypes.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h index 87326f5..c64ec62 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h @@ -17,8 +17,16 @@ #if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */ #define CY_STATUS_REG_SCSI_Filtered_H -#include "cytypes.h" -#include "CyLib.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" + #include "CyLib.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h index d6c0d24..88e1557 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h @@ -17,7 +17,15 @@ #if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */ #define CY_CONTROL_REG_SCSI_Glitch_Ctl_H -#include "cytypes.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h index 94ea62a..1ada4ee 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h @@ -17,7 +17,15 @@ #if !defined(CY_CONTROL_REG_SCSI_Out_Bits_H) /* CY_CONTROL_REG_SCSI_Out_Bits_H */ #define CY_CONTROL_REG_SCSI_Out_Bits_H -#include "cytypes.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h index e473a95..725873f 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h @@ -17,7 +17,15 @@ #if !defined(CY_CONTROL_REG_SCSI_Out_Ctl_H) /* CY_CONTROL_REG_SCSI_Out_Ctl_H */ #define CY_CONTROL_REG_SCSI_Out_Ctl_H -#include "cytypes.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h index 532aff3..de1ddc8 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h @@ -17,8 +17,16 @@ #if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */ #define CY_STATUS_REG_SCSI_Parity_Error_H -#include "cytypes.h" -#include "CyLib.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" + #include "CyLib.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h index 6d566df..6a8ae5d 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h @@ -19,15 +19,9 @@ #if !defined(CY_SPIM_SDCard_H) #define CY_SPIM_SDCard_H -#include "cytypes.h" #include "cyfitter.h" -#include "CyLib.h" - -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component SPI_Master_v2_50 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ +#include "cytypes.h" +#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */ /*************************************** diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h index e9a0eaf..160bd6a 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice.h * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h index b7f270a..bff26ed 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice_trm.h * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc index bacd4b7..5db8be3 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu.inc * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc index 22e5061..e0ed758 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu_trm.inc * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc index 019dd7c..6b49c48 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.0 Update 1 +; PSoC Creator 4.1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc index 0e2c8a3..c7c07d0 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar_trm.inc ; -; PSoC Creator 4.0 Update 1 +; PSoC Creator 4.1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc index 228aba9..e9f2b78 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.0 Update 1 +; PSoC Creator 4.1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc index 473b655..4a32cab 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv_trm.inc ; -; PSoC Creator 4.0 Update 1 +; PSoC Creator 4.1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 81204e3..e5a6d7b 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -1,8 +1,52 @@ +/******************************************************************************* +* File Name: cyfitter.h +* +* PSoC Creator 4.1 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + #ifndef INCLUDED_CYFITTER_H #define INCLUDED_CYFITTER_H #include "cydevice.h" #include "cydevice_trm.h" +/* Debug_Timer_Interrupt */ +#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define Debug_Timer_Interrupt__INTC_MASK 0x01u +#define Debug_Timer_Interrupt__INTC_NUMBER 0u +#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u +#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* Debug_Timer_TimerHW */ +#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0 +#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1 +#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0 +#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1 +#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2 +#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 +#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 +#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0 +#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1 +#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 +#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u +#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 +#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u +#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0 +#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1 +#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0 + /* LED1 */ #define LED1__0__INTTYPE CYREG_PICU12_INTTYPE3 #define LED1__0__MASK 0x08u @@ -36,472 +80,82 @@ #define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ #define LED1__SLW CYREG_PRT12_SLW -/* SD_CD */ -#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE6 -#define SD_CD__0__MASK 0x40u -#define SD_CD__0__PC CYREG_PRT3_PC6 -#define SD_CD__0__PORT 3u -#define SD_CD__0__SHIFT 6u -#define SD_CD__AG CYREG_PRT3_AG -#define SD_CD__AMUX CYREG_PRT3_AMUX -#define SD_CD__BIE CYREG_PRT3_BIE -#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_CD__BYP CYREG_PRT3_BYP -#define SD_CD__CTL CYREG_PRT3_CTL -#define SD_CD__DM0 CYREG_PRT3_DM0 -#define SD_CD__DM1 CYREG_PRT3_DM1 -#define SD_CD__DM2 CYREG_PRT3_DM2 -#define SD_CD__DR CYREG_PRT3_DR -#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS -#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN -#define SD_CD__MASK 0x40u -#define SD_CD__PORT 3u -#define SD_CD__PRT CYREG_PRT3_PRT -#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_CD__PS CYREG_PRT3_PS -#define SD_CD__SHIFT 6u -#define SD_CD__SLW CYREG_PRT3_SLW +/* SCSI_CLK */ +#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 +#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 +#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2 +#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u +#define SCSI_CLK__INDEX 0x01u +#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SCSI_CLK__PM_ACT_MSK 0x02u +#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SCSI_CLK__PM_STBY_MSK 0x02u -/* SD_CS */ -#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4 -#define SD_CS__0__MASK 0x10u -#define SD_CS__0__PC CYREG_PRT3_PC4 -#define SD_CS__0__PORT 3u -#define SD_CS__0__SHIFT 4u -#define SD_CS__AG CYREG_PRT3_AG -#define SD_CS__AMUX CYREG_PRT3_AMUX -#define SD_CS__BIE CYREG_PRT3_BIE -#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_CS__BYP CYREG_PRT3_BYP -#define SD_CS__CTL CYREG_PRT3_CTL -#define SD_CS__DM0 CYREG_PRT3_DM0 -#define SD_CS__DM1 CYREG_PRT3_DM1 -#define SD_CS__DM2 CYREG_PRT3_DM2 -#define SD_CS__DR CYREG_PRT3_DR -#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS -#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN -#define SD_CS__MASK 0x10u -#define SD_CS__PORT 3u -#define SD_CS__PRT CYREG_PRT3_PRT -#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_CS__PS CYREG_PRT3_PS -#define SD_CS__SHIFT 4u -#define SD_CS__SLW CYREG_PRT3_SLW +/* SCSI_CTL_PHASE */ +#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK -/* USBFS_arb_int */ -#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_arb_int__INTC_MASK 0x400000u -#define USBFS_arb_int__INTC_NUMBER 22u -#define USBFS_arb_int__INTC_PRIOR_NUM 6u -#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 -#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* SCSI_Filtered */ +#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u +#define SCSI_Filtered_sts_sts_reg__0__POS 0 +#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u +#define SCSI_Filtered_sts_sts_reg__1__POS 1 +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST +#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u +#define SCSI_Filtered_sts_sts_reg__2__POS 2 +#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u +#define SCSI_Filtered_sts_sts_reg__3__POS 3 +#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u +#define SCSI_Filtered_sts_sts_reg__4__POS 4 +#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST -/* USBFS_bus_reset */ -#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_bus_reset__INTC_MASK 0x800000u -#define USBFS_bus_reset__INTC_NUMBER 23u -#define USBFS_bus_reset__INTC_PRIOR_NUM 7u -#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 -#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_Dm */ -#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7 -#define USBFS_Dm__0__MASK 0x80u -#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 -#define USBFS_Dm__0__PORT 15u -#define USBFS_Dm__0__SHIFT 7u -#define USBFS_Dm__AG CYREG_PRT15_AG -#define USBFS_Dm__AMUX CYREG_PRT15_AMUX -#define USBFS_Dm__BIE CYREG_PRT15_BIE -#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK -#define USBFS_Dm__BYP CYREG_PRT15_BYP -#define USBFS_Dm__CTL CYREG_PRT15_CTL -#define USBFS_Dm__DM0 CYREG_PRT15_DM0 -#define USBFS_Dm__DM1 CYREG_PRT15_DM1 -#define USBFS_Dm__DM2 CYREG_PRT15_DM2 -#define USBFS_Dm__DR CYREG_PRT15_DR -#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS -#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE -#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG -#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN -#define USBFS_Dm__MASK 0x80u -#define USBFS_Dm__PORT 15u -#define USBFS_Dm__PRT CYREG_PRT15_PRT -#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL -#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN -#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 -#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 -#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 -#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 -#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT -#define USBFS_Dm__PS CYREG_PRT15_PS -#define USBFS_Dm__SHIFT 7u -#define USBFS_Dm__SLW CYREG_PRT15_SLW - -/* USBFS_Dp */ -#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6 -#define USBFS_Dp__0__MASK 0x40u -#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 -#define USBFS_Dp__0__PORT 15u -#define USBFS_Dp__0__SHIFT 6u -#define USBFS_Dp__AG CYREG_PRT15_AG -#define USBFS_Dp__AMUX CYREG_PRT15_AMUX -#define USBFS_Dp__BIE CYREG_PRT15_BIE -#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK -#define USBFS_Dp__BYP CYREG_PRT15_BYP -#define USBFS_Dp__CTL CYREG_PRT15_CTL -#define USBFS_Dp__DM0 CYREG_PRT15_DM0 -#define USBFS_Dp__DM1 CYREG_PRT15_DM1 -#define USBFS_Dp__DM2 CYREG_PRT15_DM2 -#define USBFS_Dp__DR CYREG_PRT15_DR -#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS -#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT -#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE -#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG -#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN -#define USBFS_Dp__MASK 0x40u -#define USBFS_Dp__PORT 15u -#define USBFS_Dp__PRT CYREG_PRT15_PRT -#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL -#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN -#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 -#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 -#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 -#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 -#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT -#define USBFS_Dp__PS CYREG_PRT15_PS -#define USBFS_Dp__SHIFT 6u -#define USBFS_Dp__SLW CYREG_PRT15_SLW -#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 - -/* USBFS_dp_int */ -#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_dp_int__INTC_MASK 0x1000u -#define USBFS_dp_int__INTC_NUMBER 12u -#define USBFS_dp_int__INTC_PRIOR_NUM 7u -#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 -#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_0 */ -#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_0__INTC_MASK 0x1000000u -#define USBFS_ep_0__INTC_NUMBER 24u -#define USBFS_ep_0__INTC_PRIOR_NUM 7u -#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 -#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_1 */ -#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x80u -#define USBFS_ep_1__INTC_NUMBER 7u -#define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 -#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_2 */ -#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x100u -#define USBFS_ep_2__INTC_NUMBER 8u -#define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 -#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_3 */ -#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_3__INTC_MASK 0x200u -#define USBFS_ep_3__INTC_NUMBER 9u -#define USBFS_ep_3__INTC_PRIOR_NUM 7u -#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 -#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_4 */ -#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_4__INTC_MASK 0x400u -#define USBFS_ep_4__INTC_NUMBER 10u -#define USBFS_ep_4__INTC_PRIOR_NUM 7u -#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 -#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_sof_int */ -#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_sof_int__INTC_MASK 0x200000u -#define USBFS_sof_int__INTC_NUMBER 21u -#define USBFS_sof_int__INTC_PRIOR_NUM 7u -#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 -#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_USB */ -#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG -#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG -#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN -#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR -#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG -#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN -#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR -#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG -#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN -#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR -#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG -#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN -#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR -#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG -#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN -#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR -#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG -#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN -#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR -#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG -#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN -#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR -#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG -#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN -#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR -#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN -#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR -#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR -#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA -#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB -#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA -#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB -#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR -#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA -#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB -#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA -#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB -#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR -#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA -#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB -#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA -#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB -#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR -#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA -#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB -#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA -#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB -#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR -#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA -#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB -#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA -#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB -#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR -#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA -#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB -#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA -#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB -#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR -#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA -#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB -#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA -#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB -#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR -#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA -#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB -#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA -#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB -#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE -#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT -#define USBFS_USB__CR0 CYREG_USB_CR0 -#define USBFS_USB__CR1 CYREG_USB_CR1 -#define USBFS_USB__CWA CYREG_USB_CWA -#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB -#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES -#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB -#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG -#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE -#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE -#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT -#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR -#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 -#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 -#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 -#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 -#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 -#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 -#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 -#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 -#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE -#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 -#define USBFS_USB__PM_ACT_MSK 0x01u -#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 -#define USBFS_USB__PM_STBY_MSK 0x01u -#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN -#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR -#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 -#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 -#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 -#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 -#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 -#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 -#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 -#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 -#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 -#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 -#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 -#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 -#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 -#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 -#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 -#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 -#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 -#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 -#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 -#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 -#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 -#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 -#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 -#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 -#define USBFS_USB__SOF0 CYREG_USB_SOF0 -#define USBFS_USB__SOF1 CYREG_USB_SOF1 -#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN -#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 -#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 - -/* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST -#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u -#define SDCard_BSPIM_RxStsReg__4__POS 4 -#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u -#define SDCard_BSPIM_RxStsReg__5__POS 5 -#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u -#define SDCard_BSPIM_RxStsReg__6__POS 6 -#define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK -#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 -#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u -#define SDCard_BSPIM_TxStsReg__0__POS 0 -#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u -#define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST -#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u -#define SDCard_BSPIM_TxStsReg__2__POS 2 -#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u -#define SDCard_BSPIM_TxStsReg__3__POS 3 -#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u -#define SDCard_BSPIM_TxStsReg__4__POS 4 -#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST - -/* SD_SCK */ -#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2 -#define SD_SCK__0__MASK 0x04u -#define SD_SCK__0__PC CYREG_PRT3_PC2 -#define SD_SCK__0__PORT 3u -#define SD_SCK__0__SHIFT 2u -#define SD_SCK__AG CYREG_PRT3_AG -#define SD_SCK__AMUX CYREG_PRT3_AMUX -#define SD_SCK__BIE CYREG_PRT3_BIE -#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_SCK__BYP CYREG_PRT3_BYP -#define SD_SCK__CTL CYREG_PRT3_CTL -#define SD_SCK__DM0 CYREG_PRT3_DM0 -#define SD_SCK__DM1 CYREG_PRT3_DM1 -#define SD_SCK__DM2 CYREG_PRT3_DM2 -#define SD_SCK__DR CYREG_PRT3_DR -#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS -#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN -#define SD_SCK__MASK 0x04u -#define SD_SCK__PORT 3u -#define SD_SCK__PRT CYREG_PRT3_PRT -#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_SCK__PS CYREG_PRT3_PS -#define SD_SCK__SHIFT 2u -#define SD_SCK__SLW CYREG_PRT3_SLW +/* SCSI_Glitch_Ctl */ +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK /* SCSI_In */ #define SCSI_In__0__AG CYREG_PRT2_AG @@ -784,8 +438,6 @@ #define SCSI_In__REQ__PS CYREG_PRT5_PS #define SCSI_In__REQ__SHIFT 2u #define SCSI_In__REQ__SLW CYREG_PRT5_SLW - -/* SCSI_In_DBx */ #define SCSI_In_DBx__0__AG CYREG_PRT12_AG #define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE #define SCSI_In_DBx__0__BIT_MASK CYREG_PRT12_BIT_MASK @@ -1233,152 +885,285 @@ #define SCSI_In_DBx__DB7__SHIFT 1u #define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW -/* SD_DAT1 */ -#define SD_DAT1__0__INTTYPE CYREG_PICU3_INTTYPE0 -#define SD_DAT1__0__MASK 0x01u -#define SD_DAT1__0__PC CYREG_PRT3_PC0 -#define SD_DAT1__0__PORT 3u -#define SD_DAT1__0__SHIFT 0u -#define SD_DAT1__AG CYREG_PRT3_AG -#define SD_DAT1__AMUX CYREG_PRT3_AMUX -#define SD_DAT1__BIE CYREG_PRT3_BIE -#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_DAT1__BYP CYREG_PRT3_BYP -#define SD_DAT1__CTL CYREG_PRT3_CTL -#define SD_DAT1__DM0 CYREG_PRT3_DM0 -#define SD_DAT1__DM1 CYREG_PRT3_DM1 -#define SD_DAT1__DM2 CYREG_PRT3_DM2 -#define SD_DAT1__DR CYREG_PRT3_DR -#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS -#define SD_DAT1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN -#define SD_DAT1__MASK 0x01u -#define SD_DAT1__PORT 3u -#define SD_DAT1__PRT CYREG_PRT3_PRT -#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_DAT1__PS CYREG_PRT3_PS -#define SD_DAT1__SHIFT 0u -#define SD_DAT1__SLW CYREG_PRT3_SLW - -/* SD_DAT2 */ -#define SD_DAT2__0__INTTYPE CYREG_PICU3_INTTYPE5 -#define SD_DAT2__0__MASK 0x20u -#define SD_DAT2__0__PC CYREG_PRT3_PC5 -#define SD_DAT2__0__PORT 3u -#define SD_DAT2__0__SHIFT 5u -#define SD_DAT2__AG CYREG_PRT3_AG -#define SD_DAT2__AMUX CYREG_PRT3_AMUX -#define SD_DAT2__BIE CYREG_PRT3_BIE -#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_DAT2__BYP CYREG_PRT3_BYP -#define SD_DAT2__CTL CYREG_PRT3_CTL -#define SD_DAT2__DM0 CYREG_PRT3_DM0 -#define SD_DAT2__DM1 CYREG_PRT3_DM1 -#define SD_DAT2__DM2 CYREG_PRT3_DM2 -#define SD_DAT2__DR CYREG_PRT3_DR -#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS -#define SD_DAT2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN -#define SD_DAT2__MASK 0x20u -#define SD_DAT2__PORT 3u -#define SD_DAT2__PRT CYREG_PRT3_PRT -#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_DAT2__PS CYREG_PRT3_PS -#define SD_DAT2__SHIFT 5u -#define SD_DAT2__SLW CYREG_PRT3_SLW - -/* SD_MISO */ -#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1 -#define SD_MISO__0__MASK 0x02u -#define SD_MISO__0__PC CYREG_PRT3_PC1 -#define SD_MISO__0__PORT 3u -#define SD_MISO__0__SHIFT 1u -#define SD_MISO__AG CYREG_PRT3_AG -#define SD_MISO__AMUX CYREG_PRT3_AMUX -#define SD_MISO__BIE CYREG_PRT3_BIE -#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_MISO__BYP CYREG_PRT3_BYP -#define SD_MISO__CTL CYREG_PRT3_CTL -#define SD_MISO__DM0 CYREG_PRT3_DM0 -#define SD_MISO__DM1 CYREG_PRT3_DM1 -#define SD_MISO__DM2 CYREG_PRT3_DM2 -#define SD_MISO__DR CYREG_PRT3_DR -#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS -#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN -#define SD_MISO__MASK 0x02u -#define SD_MISO__PORT 3u -#define SD_MISO__PRT CYREG_PRT3_PRT -#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_MISO__PS CYREG_PRT3_PS -#define SD_MISO__SHIFT 1u -#define SD_MISO__SLW CYREG_PRT3_SLW - -/* SD_MOSI */ -#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3 -#define SD_MOSI__0__MASK 0x08u -#define SD_MOSI__0__PC CYREG_PRT3_PC3 -#define SD_MOSI__0__PORT 3u -#define SD_MOSI__0__SHIFT 3u -#define SD_MOSI__AG CYREG_PRT3_AG -#define SD_MOSI__AMUX CYREG_PRT3_AMUX -#define SD_MOSI__BIE CYREG_PRT3_BIE -#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_MOSI__BYP CYREG_PRT3_BYP -#define SD_MOSI__CTL CYREG_PRT3_CTL -#define SD_MOSI__DM0 CYREG_PRT3_DM0 -#define SD_MOSI__DM1 CYREG_PRT3_DM1 -#define SD_MOSI__DM2 CYREG_PRT3_DM2 -#define SD_MOSI__DR CYREG_PRT3_DR -#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS -#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN -#define SD_MOSI__MASK 0x08u -#define SD_MOSI__PORT 3u -#define SD_MOSI__PRT CYREG_PRT3_PRT -#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_MOSI__PS CYREG_PRT3_PS -#define SD_MOSI__SHIFT 3u -#define SD_MOSI__SLW CYREG_PRT3_SLW - -/* SCSI_CLK */ -#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 -#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 -#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2 -#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u -#define SCSI_CLK__INDEX 0x01u -#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define SCSI_CLK__PM_ACT_MSK 0x02u -#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define SCSI_CLK__PM_STBY_MSK 0x02u +/* SCSI_Noise */ +#define SCSI_Noise__0__AG CYREG_PRT12_AG +#define SCSI_Noise__0__BIE CYREG_PRT12_BIE +#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_Noise__0__BYP CYREG_PRT12_BYP +#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0 +#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1 +#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2 +#define SCSI_Noise__0__DR CYREG_PRT12_DR +#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_Noise__0__INTTYPE CYREG_PICU12_INTTYPE5 +#define SCSI_Noise__0__MASK 0x20u +#define SCSI_Noise__0__PC CYREG_PRT12_PC5 +#define SCSI_Noise__0__PORT 12u +#define SCSI_Noise__0__PRT CYREG_PRT12_PRT +#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_Noise__0__PS CYREG_PRT12_PS +#define SCSI_Noise__0__SHIFT 5u +#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_Noise__0__SLW CYREG_PRT12_SLW +#define SCSI_Noise__1__AG CYREG_PRT6_AG +#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__1__BIE CYREG_PRT6_BIE +#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__1__BYP CYREG_PRT6_BYP +#define SCSI_Noise__1__CTL CYREG_PRT6_CTL +#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__1__DR CYREG_PRT6_DR +#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__1__INTTYPE CYREG_PICU6_INTTYPE4 +#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__1__MASK 0x10u +#define SCSI_Noise__1__PC CYREG_PRT6_PC4 +#define SCSI_Noise__1__PORT 6u +#define SCSI_Noise__1__PRT CYREG_PRT6_PRT +#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__1__PS CYREG_PRT6_PS +#define SCSI_Noise__1__SHIFT 4u +#define SCSI_Noise__1__SLW CYREG_PRT6_SLW +#define SCSI_Noise__2__AG CYREG_PRT5_AG +#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX +#define SCSI_Noise__2__BIE CYREG_PRT5_BIE +#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Noise__2__BYP CYREG_PRT5_BYP +#define SCSI_Noise__2__CTL CYREG_PRT5_CTL +#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0 +#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1 +#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2 +#define SCSI_Noise__2__DR CYREG_PRT5_DR +#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Noise__2__INTTYPE CYREG_PICU5_INTTYPE0 +#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Noise__2__MASK 0x01u +#define SCSI_Noise__2__PC CYREG_PRT5_PC0 +#define SCSI_Noise__2__PORT 5u +#define SCSI_Noise__2__PRT CYREG_PRT5_PRT +#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Noise__2__PS CYREG_PRT5_PS +#define SCSI_Noise__2__SHIFT 0u +#define SCSI_Noise__2__SLW CYREG_PRT5_SLW +#define SCSI_Noise__3__AG CYREG_PRT6_AG +#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__3__BIE CYREG_PRT6_BIE +#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__3__BYP CYREG_PRT6_BYP +#define SCSI_Noise__3__CTL CYREG_PRT6_CTL +#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__3__DR CYREG_PRT6_DR +#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__3__INTTYPE CYREG_PICU6_INTTYPE6 +#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__3__MASK 0x40u +#define SCSI_Noise__3__PC CYREG_PRT6_PC6 +#define SCSI_Noise__3__PORT 6u +#define SCSI_Noise__3__PRT CYREG_PRT6_PRT +#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__3__PS CYREG_PRT6_PS +#define SCSI_Noise__3__SHIFT 6u +#define SCSI_Noise__3__SLW CYREG_PRT6_SLW +#define SCSI_Noise__4__AG CYREG_PRT6_AG +#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__4__BIE CYREG_PRT6_BIE +#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__4__BYP CYREG_PRT6_BYP +#define SCSI_Noise__4__CTL CYREG_PRT6_CTL +#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__4__DR CYREG_PRT6_DR +#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__4__INTTYPE CYREG_PICU6_INTTYPE5 +#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__4__MASK 0x20u +#define SCSI_Noise__4__PC CYREG_PRT6_PC5 +#define SCSI_Noise__4__PORT 6u +#define SCSI_Noise__4__PRT CYREG_PRT6_PRT +#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__4__PS CYREG_PRT6_PS +#define SCSI_Noise__4__SHIFT 5u +#define SCSI_Noise__4__SLW CYREG_PRT6_SLW +#define SCSI_Noise__ACK__AG CYREG_PRT6_AG +#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE +#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP +#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL +#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__ACK__DR CYREG_PRT6_DR +#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__ACK__INTTYPE CYREG_PICU6_INTTYPE5 +#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__ACK__MASK 0x20u +#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5 +#define SCSI_Noise__ACK__PORT 6u +#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT +#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__ACK__PS CYREG_PRT6_PS +#define SCSI_Noise__ACK__SHIFT 5u +#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW +#define SCSI_Noise__ATN__AG CYREG_PRT12_AG +#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE +#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP +#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0 +#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1 +#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2 +#define SCSI_Noise__ATN__DR CYREG_PRT12_DR +#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_Noise__ATN__INTTYPE CYREG_PICU12_INTTYPE5 +#define SCSI_Noise__ATN__MASK 0x20u +#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5 +#define SCSI_Noise__ATN__PORT 12u +#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT +#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_Noise__ATN__PS CYREG_PRT12_PS +#define SCSI_Noise__ATN__SHIFT 5u +#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW +#define SCSI_Noise__BSY__AG CYREG_PRT6_AG +#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE +#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP +#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL +#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__BSY__DR CYREG_PRT6_DR +#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__BSY__INTTYPE CYREG_PICU6_INTTYPE4 +#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__BSY__MASK 0x10u +#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4 +#define SCSI_Noise__BSY__PORT 6u +#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT +#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__BSY__PS CYREG_PRT6_PS +#define SCSI_Noise__BSY__SHIFT 4u +#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW +#define SCSI_Noise__RST__AG CYREG_PRT6_AG +#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE +#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP +#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL +#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__RST__DR CYREG_PRT6_DR +#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__RST__INTTYPE CYREG_PICU6_INTTYPE6 +#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__RST__MASK 0x40u +#define SCSI_Noise__RST__PC CYREG_PRT6_PC6 +#define SCSI_Noise__RST__PORT 6u +#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT +#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__RST__PS CYREG_PRT6_PS +#define SCSI_Noise__RST__SHIFT 6u +#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW +#define SCSI_Noise__SEL__AG CYREG_PRT5_AG +#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX +#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE +#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP +#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL +#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0 +#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1 +#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2 +#define SCSI_Noise__SEL__DR CYREG_PRT5_DR +#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Noise__SEL__INTTYPE CYREG_PICU5_INTTYPE0 +#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Noise__SEL__MASK 0x01u +#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0 +#define SCSI_Noise__SEL__PORT 5u +#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT +#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Noise__SEL__PS CYREG_PRT5_PS +#define SCSI_Noise__SEL__SHIFT 0u +#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW /* SCSI_Out */ #define SCSI_Out__0__AG CYREG_PRT4_AG @@ -1941,8 +1726,6 @@ #define SCSI_Out__SEL__PS CYREG_PRT0_PS #define SCSI_Out__SEL__SHIFT 3u #define SCSI_Out__SEL__SLW CYREG_PRT0_SLW - -/* SCSI_Out_Bits */ #define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u @@ -1977,8 +1760,6 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL #define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL #define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB08_MSK - -/* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL @@ -1999,8 +1780,6 @@ #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL #define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL #define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK - -/* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG #define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX #define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE @@ -2450,6 +2229,370 @@ #define SCSI_Out_DBx__DB7__SHIFT 4u #define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW +/* SCSI_Parity_Error */ +#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__0__POS 0 +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST + +/* SCSI_RST_ISR */ +#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RST_ISR__INTC_MASK 0x02u +#define SCSI_RST_ISR__INTC_NUMBER 1u +#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u +#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_RX_DMA */ +#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_RX_DMA__DRQ_NUMBER 0u +#define SCSI_RX_DMA__NUMBEROF_TDS 0u +#define SCSI_RX_DMA__PRIORITY 2u +#define SCSI_RX_DMA__TERMIN_EN 0u +#define SCSI_RX_DMA__TERMIN_SEL 0u +#define SCSI_RX_DMA__TERMOUT0_EN 1u +#define SCSI_RX_DMA__TERMOUT0_SEL 0u +#define SCSI_RX_DMA__TERMOUT1_EN 0u +#define SCSI_RX_DMA__TERMOUT1_SEL 0u +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u +#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_SEL_ISR__INTC_MASK 0x08u +#define SCSI_SEL_ISR__INTC_NUMBER 3u +#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u +#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_TX_DMA__DRQ_NUMBER 1u +#define SCSI_TX_DMA__NUMBEROF_TDS 0u +#define SCSI_TX_DMA__PRIORITY 2u +#define SCSI_TX_DMA__TERMIN_EN 0u +#define SCSI_TX_DMA__TERMIN_SEL 0u +#define SCSI_TX_DMA__TERMOUT0_EN 1u +#define SCSI_TX_DMA__TERMOUT0_SEL 1u +#define SCSI_TX_DMA__TERMOUT1_EN 0u +#define SCSI_TX_DMA__TERMOUT1_SEL 0u +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u +#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SDCard_BSPIM */ +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST +#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_RxStsReg__4__POS 4 +#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u +#define SDCard_BSPIM_RxStsReg__5__POS 5 +#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u +#define SDCard_BSPIM_RxStsReg__6__POS 6 +#define SDCard_BSPIM_RxStsReg__MASK 0x70u +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK +#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL +#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 +#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u +#define SDCard_BSPIM_TxStsReg__0__POS 0 +#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u +#define SDCard_BSPIM_TxStsReg__1__POS 1 +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u +#define SDCard_BSPIM_TxStsReg__2__POS 2 +#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u +#define SDCard_BSPIM_TxStsReg__3__POS 3 +#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_TxStsReg__4__POS 4 +#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST + +/* SD_CD */ +#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE6 +#define SD_CD__0__MASK 0x40u +#define SD_CD__0__PC CYREG_PRT3_PC6 +#define SD_CD__0__PORT 3u +#define SD_CD__0__SHIFT 6u +#define SD_CD__AG CYREG_PRT3_AG +#define SD_CD__AMUX CYREG_PRT3_AMUX +#define SD_CD__BIE CYREG_PRT3_BIE +#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CD__BYP CYREG_PRT3_BYP +#define SD_CD__CTL CYREG_PRT3_CTL +#define SD_CD__DM0 CYREG_PRT3_DM0 +#define SD_CD__DM1 CYREG_PRT3_DM1 +#define SD_CD__DM2 CYREG_PRT3_DM2 +#define SD_CD__DR CYREG_PRT3_DR +#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CD__MASK 0x40u +#define SD_CD__PORT 3u +#define SD_CD__PRT CYREG_PRT3_PRT +#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CD__PS CYREG_PRT3_PS +#define SD_CD__SHIFT 6u +#define SD_CD__SLW CYREG_PRT3_SLW + +/* SD_CS */ +#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4 +#define SD_CS__0__MASK 0x10u +#define SD_CS__0__PC CYREG_PRT3_PC4 +#define SD_CS__0__PORT 3u +#define SD_CS__0__SHIFT 4u +#define SD_CS__AG CYREG_PRT3_AG +#define SD_CS__AMUX CYREG_PRT3_AMUX +#define SD_CS__BIE CYREG_PRT3_BIE +#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CS__BYP CYREG_PRT3_BYP +#define SD_CS__CTL CYREG_PRT3_CTL +#define SD_CS__DM0 CYREG_PRT3_DM0 +#define SD_CS__DM1 CYREG_PRT3_DM1 +#define SD_CS__DM2 CYREG_PRT3_DM2 +#define SD_CS__DR CYREG_PRT3_DR +#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CS__MASK 0x10u +#define SD_CS__PORT 3u +#define SD_CS__PRT CYREG_PRT3_PRT +#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CS__PS CYREG_PRT3_PS +#define SD_CS__SHIFT 4u +#define SD_CS__SLW CYREG_PRT3_SLW + +/* SD_DAT1 */ +#define SD_DAT1__0__INTTYPE CYREG_PICU3_INTTYPE0 +#define SD_DAT1__0__MASK 0x01u +#define SD_DAT1__0__PC CYREG_PRT3_PC0 +#define SD_DAT1__0__PORT 3u +#define SD_DAT1__0__SHIFT 0u +#define SD_DAT1__AG CYREG_PRT3_AG +#define SD_DAT1__AMUX CYREG_PRT3_AMUX +#define SD_DAT1__BIE CYREG_PRT3_BIE +#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_DAT1__BYP CYREG_PRT3_BYP +#define SD_DAT1__CTL CYREG_PRT3_CTL +#define SD_DAT1__DM0 CYREG_PRT3_DM0 +#define SD_DAT1__DM1 CYREG_PRT3_DM1 +#define SD_DAT1__DM2 CYREG_PRT3_DM2 +#define SD_DAT1__DR CYREG_PRT3_DR +#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS +#define SD_DAT1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN +#define SD_DAT1__MASK 0x01u +#define SD_DAT1__PORT 3u +#define SD_DAT1__PRT CYREG_PRT3_PRT +#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_DAT1__PS CYREG_PRT3_PS +#define SD_DAT1__SHIFT 0u +#define SD_DAT1__SLW CYREG_PRT3_SLW + +/* SD_DAT2 */ +#define SD_DAT2__0__INTTYPE CYREG_PICU3_INTTYPE5 +#define SD_DAT2__0__MASK 0x20u +#define SD_DAT2__0__PC CYREG_PRT3_PC5 +#define SD_DAT2__0__PORT 3u +#define SD_DAT2__0__SHIFT 5u +#define SD_DAT2__AG CYREG_PRT3_AG +#define SD_DAT2__AMUX CYREG_PRT3_AMUX +#define SD_DAT2__BIE CYREG_PRT3_BIE +#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_DAT2__BYP CYREG_PRT3_BYP +#define SD_DAT2__CTL CYREG_PRT3_CTL +#define SD_DAT2__DM0 CYREG_PRT3_DM0 +#define SD_DAT2__DM1 CYREG_PRT3_DM1 +#define SD_DAT2__DM2 CYREG_PRT3_DM2 +#define SD_DAT2__DR CYREG_PRT3_DR +#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS +#define SD_DAT2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN +#define SD_DAT2__MASK 0x20u +#define SD_DAT2__PORT 3u +#define SD_DAT2__PRT CYREG_PRT3_PRT +#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_DAT2__PS CYREG_PRT3_PS +#define SD_DAT2__SHIFT 5u +#define SD_DAT2__SLW CYREG_PRT3_SLW + +/* SD_Data_Clk */ +#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 +#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 +#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 +#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u +#define SD_Data_Clk__INDEX 0x00u +#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SD_Data_Clk__PM_ACT_MSK 0x01u +#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SD_Data_Clk__PM_STBY_MSK 0x01u + +/* SD_MISO */ +#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1 +#define SD_MISO__0__MASK 0x02u +#define SD_MISO__0__PC CYREG_PRT3_PC1 +#define SD_MISO__0__PORT 3u +#define SD_MISO__0__SHIFT 1u +#define SD_MISO__AG CYREG_PRT3_AG +#define SD_MISO__AMUX CYREG_PRT3_AMUX +#define SD_MISO__BIE CYREG_PRT3_BIE +#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MISO__BYP CYREG_PRT3_BYP +#define SD_MISO__CTL CYREG_PRT3_CTL +#define SD_MISO__DM0 CYREG_PRT3_DM0 +#define SD_MISO__DM1 CYREG_PRT3_DM1 +#define SD_MISO__DM2 CYREG_PRT3_DM2 +#define SD_MISO__DR CYREG_PRT3_DR +#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MISO__MASK 0x02u +#define SD_MISO__PORT 3u +#define SD_MISO__PRT CYREG_PRT3_PRT +#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MISO__PS CYREG_PRT3_PS +#define SD_MISO__SHIFT 1u +#define SD_MISO__SLW CYREG_PRT3_SLW + +/* SD_MOSI */ +#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3 +#define SD_MOSI__0__MASK 0x08u +#define SD_MOSI__0__PC CYREG_PRT3_PC3 +#define SD_MOSI__0__PORT 3u +#define SD_MOSI__0__SHIFT 3u +#define SD_MOSI__AG CYREG_PRT3_AG +#define SD_MOSI__AMUX CYREG_PRT3_AMUX +#define SD_MOSI__BIE CYREG_PRT3_BIE +#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MOSI__BYP CYREG_PRT3_BYP +#define SD_MOSI__CTL CYREG_PRT3_CTL +#define SD_MOSI__DM0 CYREG_PRT3_DM0 +#define SD_MOSI__DM1 CYREG_PRT3_DM1 +#define SD_MOSI__DM2 CYREG_PRT3_DM2 +#define SD_MOSI__DR CYREG_PRT3_DR +#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MOSI__MASK 0x08u +#define SD_MOSI__PORT 3u +#define SD_MOSI__PRT CYREG_PRT3_PRT +#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MOSI__PS CYREG_PRT3_PS +#define SD_MOSI__SHIFT 3u +#define SD_MOSI__SLW CYREG_PRT3_SLW + /* SD_RX_DMA */ #define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_RX_DMA__DRQ_NUMBER 2u @@ -2461,8 +2604,6 @@ #define SD_RX_DMA__TERMOUT0_SEL 2u #define SD_RX_DMA__TERMOUT1_EN 0u #define SD_RX_DMA__TERMOUT1_SEL 0u - -/* SD_RX_DMA_COMPLETE */ #define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 #define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u @@ -2472,6 +2613,40 @@ #define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* SD_SCK */ +#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2 +#define SD_SCK__0__MASK 0x04u +#define SD_SCK__0__PC CYREG_PRT3_PC2 +#define SD_SCK__0__PORT 3u +#define SD_SCK__0__SHIFT 2u +#define SD_SCK__AG CYREG_PRT3_AG +#define SD_SCK__AMUX CYREG_PRT3_AMUX +#define SD_SCK__BIE CYREG_PRT3_BIE +#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_SCK__BYP CYREG_PRT3_BYP +#define SD_SCK__CTL CYREG_PRT3_CTL +#define SD_SCK__DM0 CYREG_PRT3_DM0 +#define SD_SCK__DM1 CYREG_PRT3_DM1 +#define SD_SCK__DM2 CYREG_PRT3_DM2 +#define SD_SCK__DR CYREG_PRT3_DR +#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS +#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN +#define SD_SCK__MASK 0x04u +#define SD_SCK__PORT 3u +#define SD_SCK__PRT CYREG_PRT3_PRT +#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_SCK__PS CYREG_PRT3_PS +#define SD_SCK__SHIFT 2u +#define SD_SCK__SLW CYREG_PRT3_SLW + /* SD_TX_DMA */ #define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_TX_DMA__DRQ_NUMBER 3u @@ -2483,8 +2658,6 @@ #define SD_TX_DMA__TERMOUT0_SEL 3u #define SD_TX_DMA__TERMOUT1_EN 0u #define SD_TX_DMA__TERMOUT1_SEL 0u - -/* SD_TX_DMA_COMPLETE */ #define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 #define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u @@ -2494,285 +2667,269 @@ #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -/* SCSI_Noise */ -#define SCSI_Noise__0__AG CYREG_PRT12_AG -#define SCSI_Noise__0__BIE CYREG_PRT12_BIE -#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK -#define SCSI_Noise__0__BYP CYREG_PRT12_BYP -#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0 -#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1 -#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2 -#define SCSI_Noise__0__DR CYREG_PRT12_DR -#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS -#define SCSI_Noise__0__INTTYPE CYREG_PICU12_INTTYPE5 -#define SCSI_Noise__0__MASK 0x20u -#define SCSI_Noise__0__PC CYREG_PRT12_PC5 -#define SCSI_Noise__0__PORT 12u -#define SCSI_Noise__0__PRT CYREG_PRT12_PRT -#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN -#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 -#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 -#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 -#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 -#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT -#define SCSI_Noise__0__PS CYREG_PRT12_PS -#define SCSI_Noise__0__SHIFT 5u -#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG -#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF -#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN -#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ -#define SCSI_Noise__0__SLW CYREG_PRT12_SLW -#define SCSI_Noise__1__AG CYREG_PRT6_AG -#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__1__BIE CYREG_PRT6_BIE -#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__1__BYP CYREG_PRT6_BYP -#define SCSI_Noise__1__CTL CYREG_PRT6_CTL -#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__1__DR CYREG_PRT6_DR -#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__1__INTTYPE CYREG_PICU6_INTTYPE4 -#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__1__MASK 0x10u -#define SCSI_Noise__1__PC CYREG_PRT6_PC4 -#define SCSI_Noise__1__PORT 6u -#define SCSI_Noise__1__PRT CYREG_PRT6_PRT -#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__1__PS CYREG_PRT6_PS -#define SCSI_Noise__1__SHIFT 4u -#define SCSI_Noise__1__SLW CYREG_PRT6_SLW -#define SCSI_Noise__2__AG CYREG_PRT5_AG -#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX -#define SCSI_Noise__2__BIE CYREG_PRT5_BIE -#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK -#define SCSI_Noise__2__BYP CYREG_PRT5_BYP -#define SCSI_Noise__2__CTL CYREG_PRT5_CTL -#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0 -#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1 -#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2 -#define SCSI_Noise__2__DR CYREG_PRT5_DR -#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS -#define SCSI_Noise__2__INTTYPE CYREG_PICU5_INTTYPE0 -#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG -#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN -#define SCSI_Noise__2__MASK 0x01u -#define SCSI_Noise__2__PC CYREG_PRT5_PC0 -#define SCSI_Noise__2__PORT 5u -#define SCSI_Noise__2__PRT CYREG_PRT5_PRT -#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL -#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN -#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 -#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 -#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 -#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 -#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT -#define SCSI_Noise__2__PS CYREG_PRT5_PS -#define SCSI_Noise__2__SHIFT 0u -#define SCSI_Noise__2__SLW CYREG_PRT5_SLW -#define SCSI_Noise__3__AG CYREG_PRT6_AG -#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__3__BIE CYREG_PRT6_BIE -#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__3__BYP CYREG_PRT6_BYP -#define SCSI_Noise__3__CTL CYREG_PRT6_CTL -#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__3__DR CYREG_PRT6_DR -#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__3__INTTYPE CYREG_PICU6_INTTYPE6 -#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__3__MASK 0x40u -#define SCSI_Noise__3__PC CYREG_PRT6_PC6 -#define SCSI_Noise__3__PORT 6u -#define SCSI_Noise__3__PRT CYREG_PRT6_PRT -#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__3__PS CYREG_PRT6_PS -#define SCSI_Noise__3__SHIFT 6u -#define SCSI_Noise__3__SLW CYREG_PRT6_SLW -#define SCSI_Noise__4__AG CYREG_PRT6_AG -#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__4__BIE CYREG_PRT6_BIE -#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__4__BYP CYREG_PRT6_BYP -#define SCSI_Noise__4__CTL CYREG_PRT6_CTL -#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__4__DR CYREG_PRT6_DR -#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__4__INTTYPE CYREG_PICU6_INTTYPE5 -#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__4__MASK 0x20u -#define SCSI_Noise__4__PC CYREG_PRT6_PC5 -#define SCSI_Noise__4__PORT 6u -#define SCSI_Noise__4__PRT CYREG_PRT6_PRT -#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__4__PS CYREG_PRT6_PS -#define SCSI_Noise__4__SHIFT 5u -#define SCSI_Noise__4__SLW CYREG_PRT6_SLW -#define SCSI_Noise__ACK__AG CYREG_PRT6_AG -#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE -#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP -#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL -#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__ACK__DR CYREG_PRT6_DR -#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__ACK__INTTYPE CYREG_PICU6_INTTYPE5 -#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__ACK__MASK 0x20u -#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5 -#define SCSI_Noise__ACK__PORT 6u -#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT -#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__ACK__PS CYREG_PRT6_PS -#define SCSI_Noise__ACK__SHIFT 5u -#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW -#define SCSI_Noise__ATN__AG CYREG_PRT12_AG -#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE -#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK -#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP -#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0 -#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1 -#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2 -#define SCSI_Noise__ATN__DR CYREG_PRT12_DR -#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS -#define SCSI_Noise__ATN__INTTYPE CYREG_PICU12_INTTYPE5 -#define SCSI_Noise__ATN__MASK 0x20u -#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5 -#define SCSI_Noise__ATN__PORT 12u -#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT -#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN -#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 -#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 -#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 -#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 -#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT -#define SCSI_Noise__ATN__PS CYREG_PRT12_PS -#define SCSI_Noise__ATN__SHIFT 5u -#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG -#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF -#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN -#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ -#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW -#define SCSI_Noise__BSY__AG CYREG_PRT6_AG -#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE -#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP -#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL -#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__BSY__DR CYREG_PRT6_DR -#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__BSY__INTTYPE CYREG_PICU6_INTTYPE4 -#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__BSY__MASK 0x10u -#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4 -#define SCSI_Noise__BSY__PORT 6u -#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT -#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__BSY__PS CYREG_PRT6_PS -#define SCSI_Noise__BSY__SHIFT 4u -#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW -#define SCSI_Noise__RST__AG CYREG_PRT6_AG -#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE -#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP -#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL -#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__RST__DR CYREG_PRT6_DR -#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__RST__INTTYPE CYREG_PICU6_INTTYPE6 -#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__RST__MASK 0x40u -#define SCSI_Noise__RST__PC CYREG_PRT6_PC6 -#define SCSI_Noise__RST__PORT 6u -#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT -#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__RST__PS CYREG_PRT6_PS -#define SCSI_Noise__RST__SHIFT 6u -#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW -#define SCSI_Noise__SEL__AG CYREG_PRT5_AG -#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX -#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE -#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK -#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP -#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL -#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0 -#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1 -#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2 -#define SCSI_Noise__SEL__DR CYREG_PRT5_DR -#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS -#define SCSI_Noise__SEL__INTTYPE CYREG_PICU5_INTTYPE0 -#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG -#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN -#define SCSI_Noise__SEL__MASK 0x01u -#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0 -#define SCSI_Noise__SEL__PORT 5u -#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT -#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL -#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN -#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 -#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 -#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 -#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 -#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT -#define SCSI_Noise__SEL__PS CYREG_PRT5_PS -#define SCSI_Noise__SEL__SHIFT 0u -#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW +/* USBFS */ +#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_arb_int__INTC_MASK 0x400000u +#define USBFS_arb_int__INTC_NUMBER 22u +#define USBFS_arb_int__INTC_PRIOR_NUM 6u +#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 +#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_bus_reset__INTC_MASK 0x800000u +#define USBFS_bus_reset__INTC_NUMBER 23u +#define USBFS_bus_reset__INTC_PRIOR_NUM 7u +#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 +#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7 +#define USBFS_Dm__0__MASK 0x80u +#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 +#define USBFS_Dm__0__PORT 15u +#define USBFS_Dm__0__SHIFT 7u +#define USBFS_Dm__AG CYREG_PRT15_AG +#define USBFS_Dm__AMUX CYREG_PRT15_AMUX +#define USBFS_Dm__BIE CYREG_PRT15_BIE +#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dm__BYP CYREG_PRT15_BYP +#define USBFS_Dm__CTL CYREG_PRT15_CTL +#define USBFS_Dm__DM0 CYREG_PRT15_DM0 +#define USBFS_Dm__DM1 CYREG_PRT15_DM1 +#define USBFS_Dm__DM2 CYREG_PRT15_DM2 +#define USBFS_Dm__DR CYREG_PRT15_DR +#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dm__MASK 0x80u +#define USBFS_Dm__PORT 15u +#define USBFS_Dm__PRT CYREG_PRT15_PRT +#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dm__PS CYREG_PRT15_PS +#define USBFS_Dm__SHIFT 7u +#define USBFS_Dm__SLW CYREG_PRT15_SLW +#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6 +#define USBFS_Dp__0__MASK 0x40u +#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 +#define USBFS_Dp__0__PORT 15u +#define USBFS_Dp__0__SHIFT 6u +#define USBFS_Dp__AG CYREG_PRT15_AG +#define USBFS_Dp__AMUX CYREG_PRT15_AMUX +#define USBFS_Dp__BIE CYREG_PRT15_BIE +#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dp__BYP CYREG_PRT15_BYP +#define USBFS_Dp__CTL CYREG_PRT15_CTL +#define USBFS_Dp__DM0 CYREG_PRT15_DM0 +#define USBFS_Dp__DM1 CYREG_PRT15_DM1 +#define USBFS_Dp__DM2 CYREG_PRT15_DM2 +#define USBFS_Dp__DR CYREG_PRT15_DR +#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT +#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dp__MASK 0x40u +#define USBFS_Dp__PORT 15u +#define USBFS_Dp__PRT CYREG_PRT15_PRT +#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dp__PS CYREG_PRT15_PS +#define USBFS_Dp__SHIFT 6u +#define USBFS_Dp__SLW CYREG_PRT15_SLW +#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 +#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_dp_int__INTC_MASK 0x1000u +#define USBFS_dp_int__INTC_NUMBER 12u +#define USBFS_dp_int__INTC_PRIOR_NUM 7u +#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 +#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_0__INTC_MASK 0x1000000u +#define USBFS_ep_0__INTC_NUMBER 24u +#define USBFS_ep_0__INTC_PRIOR_NUM 7u +#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 +#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_1__INTC_MASK 0x80u +#define USBFS_ep_1__INTC_NUMBER 7u +#define USBFS_ep_1__INTC_PRIOR_NUM 7u +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 +#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_2__INTC_MASK 0x100u +#define USBFS_ep_2__INTC_NUMBER 8u +#define USBFS_ep_2__INTC_PRIOR_NUM 7u +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 +#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_3__INTC_MASK 0x200u +#define USBFS_ep_3__INTC_NUMBER 9u +#define USBFS_ep_3__INTC_PRIOR_NUM 7u +#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 +#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_4__INTC_MASK 0x400u +#define USBFS_ep_4__INTC_NUMBER 10u +#define USBFS_ep_4__INTC_PRIOR_NUM 7u +#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 +#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_sof_int__INTC_MASK 0x200000u +#define USBFS_sof_int__INTC_NUMBER 21u +#define USBFS_sof_int__INTC_PRIOR_NUM 7u +#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 +#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG +#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG +#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN +#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR +#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG +#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN +#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR +#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG +#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN +#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR +#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG +#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN +#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR +#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG +#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN +#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR +#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG +#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN +#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR +#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG +#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN +#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR +#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG +#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN +#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR +#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN +#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR +#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR +#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA +#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB +#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA +#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB +#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR +#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA +#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB +#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA +#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB +#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR +#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA +#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB +#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA +#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB +#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR +#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA +#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB +#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA +#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB +#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR +#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA +#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB +#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA +#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB +#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR +#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA +#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB +#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA +#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB +#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR +#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA +#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB +#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA +#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB +#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR +#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA +#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB +#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA +#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB +#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE +#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT +#define USBFS_USB__CR0 CYREG_USB_CR0 +#define USBFS_USB__CR1 CYREG_USB_CR1 +#define USBFS_USB__CWA CYREG_USB_CWA +#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB +#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES +#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB +#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG +#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE +#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE +#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT +#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR +#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 +#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 +#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 +#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 +#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 +#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 +#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 +#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 +#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE +#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 +#define USBFS_USB__PM_ACT_MSK 0x01u +#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 +#define USBFS_USB__PM_STBY_MSK 0x01u +#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN +#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR +#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 +#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 +#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 +#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 +#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 +#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 +#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 +#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 +#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 +#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 +#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 +#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 +#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 +#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 +#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 +#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 +#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 +#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 +#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 +#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 +#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 +#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 +#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 +#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 +#define USBFS_USB__SOF0 CYREG_USB_SOF0 +#define USBFS_USB__SOF1 CYREG_USB_SOF1 +#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN +#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 +#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 /* scsiTarget */ #define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0 @@ -2841,89 +2998,6 @@ #define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL #define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB07_ST -/* Debug_Timer_Interrupt */ -#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define Debug_Timer_Interrupt__INTC_MASK 0x02u -#define Debug_Timer_Interrupt__INTC_NUMBER 1u -#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u -#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1 -#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0 -#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1 -#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0 -#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1 -#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2 -#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 -#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 -#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0 -#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1 -#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 -#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u -#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 -#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u -#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0 -#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1 -#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0 - -/* SCSI_RX_DMA */ -#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_RX_DMA__DRQ_NUMBER 0u -#define SCSI_RX_DMA__NUMBEROF_TDS 0u -#define SCSI_RX_DMA__PRIORITY 2u -#define SCSI_RX_DMA__TERMIN_EN 0u -#define SCSI_RX_DMA__TERMIN_SEL 0u -#define SCSI_RX_DMA__TERMOUT0_EN 1u -#define SCSI_RX_DMA__TERMOUT0_SEL 0u -#define SCSI_RX_DMA__TERMOUT1_EN 0u -#define SCSI_RX_DMA__TERMOUT1_SEL 0u - -/* SCSI_RX_DMA_COMPLETE */ -#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u -#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u -#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0 -#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_TX_DMA__DRQ_NUMBER 1u -#define SCSI_TX_DMA__NUMBEROF_TDS 0u -#define SCSI_TX_DMA__PRIORITY 2u -#define SCSI_TX_DMA__TERMIN_EN 0u -#define SCSI_TX_DMA__TERMIN_SEL 0u -#define SCSI_TX_DMA__TERMOUT0_EN 1u -#define SCSI_TX_DMA__TERMOUT0_SEL 1u -#define SCSI_TX_DMA__TERMOUT1_EN 0u -#define SCSI_TX_DMA__TERMOUT1_SEL 0u - -/* SCSI_TX_DMA_COMPLETE */ -#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u -#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 -#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SD_Data_Clk */ -#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 -#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 -#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 -#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u -#define SD_Data_Clk__INDEX 0x00u -#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define SD_Data_Clk__PM_ACT_MSK 0x01u -#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define SD_Data_Clk__PM_STBY_MSK 0x01u - /* timer_clock */ #define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0 #define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1 @@ -2935,148 +3009,55 @@ #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2 #define timer_clock__PM_STBY_MSK 0x04u -/* SCSI_RST_ISR */ -#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RST_ISR__INTC_MASK 0x04u -#define SCSI_RST_ISR__INTC_NUMBER 2u -#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u -#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2 -#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_SEL_ISR__INTC_MASK 0x08u -#define SCSI_SEL_ISR__INTC_NUMBER 3u -#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u -#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 -#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_Filtered */ -#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u -#define SCSI_Filtered_sts_sts_reg__0__POS 0 -#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u -#define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST -#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u -#define SCSI_Filtered_sts_sts_reg__2__POS 2 -#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u -#define SCSI_Filtered_sts_sts_reg__3__POS 3 -#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u -#define SCSI_Filtered_sts_sts_reg__4__POS 4 -#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST - -/* SCSI_CTL_PHASE */ -#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK - -/* SCSI_Glitch_Ctl */ -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK - -/* SCSI_Parity_Error */ -#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST -#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST - /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U #define BCLK__BUS_CLK__KHZ 50000U #define BCLK__BUS_CLK__MHZ 50U #define CY_PROJECT_NAME "SCSI2SD" -#define CY_VERSION "PSoC Creator 4.0 Update 1" +#define CY_VERSION "PSoC Creator 4.1" #define CYDEV_CHIP_DIE_LEOPARD 1u -#define CYDEV_CHIP_DIE_PSOC4A 12u -#define CYDEV_CHIP_DIE_PSOC5LP 19u -#define CYDEV_CHIP_DIE_PSOC5TM 20u -#define CYDEV_CHIP_DIE_TMA4 2u +#define CYDEV_CHIP_DIE_PSOC4A 16u +#define CYDEV_CHIP_DIE_PSOC5LP 2u +#define CYDEV_CHIP_DIE_PSOC5TM 3u +#define CYDEV_CHIP_DIE_TMA4 4u #define CYDEV_CHIP_DIE_UNKNOWN 0u -#define CYDEV_CHIP_FAMILY_FM0P 4u -#define CYDEV_CHIP_FAMILY_FM3 5u -#define CYDEV_CHIP_FAMILY_FM4 6u +#define CYDEV_CHIP_FAMILY_FM0P 5u +#define CYDEV_CHIP_FAMILY_FM3 6u +#define CYDEV_CHIP_FAMILY_FM4 7u #define CYDEV_CHIP_FAMILY_PSOC3 1u #define CYDEV_CHIP_FAMILY_PSOC4 2u #define CYDEV_CHIP_FAMILY_PSOC5 3u +#define CYDEV_CHIP_FAMILY_PSOC6 4u #define CYDEV_CHIP_FAMILY_UNKNOWN 0u #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 #define CYDEV_CHIP_JTAG_ID 0x2E133069u #define CYDEV_CHIP_MEMBER_3A 1u -#define CYDEV_CHIP_MEMBER_4A 12u -#define CYDEV_CHIP_MEMBER_4C 18u -#define CYDEV_CHIP_MEMBER_4D 8u -#define CYDEV_CHIP_MEMBER_4E 4u -#define CYDEV_CHIP_MEMBER_4F 13u -#define CYDEV_CHIP_MEMBER_4G 2u -#define CYDEV_CHIP_MEMBER_4H 11u -#define CYDEV_CHIP_MEMBER_4I 17u -#define CYDEV_CHIP_MEMBER_4J 9u -#define CYDEV_CHIP_MEMBER_4K 10u -#define CYDEV_CHIP_MEMBER_4L 16u -#define CYDEV_CHIP_MEMBER_4M 15u -#define CYDEV_CHIP_MEMBER_4N 6u -#define CYDEV_CHIP_MEMBER_4O 5u -#define CYDEV_CHIP_MEMBER_4P 14u -#define CYDEV_CHIP_MEMBER_4Q 7u -#define CYDEV_CHIP_MEMBER_4U 3u -#define CYDEV_CHIP_MEMBER_5A 20u -#define CYDEV_CHIP_MEMBER_5B 19u -#define CYDEV_CHIP_MEMBER_FM3 24u -#define CYDEV_CHIP_MEMBER_FM4 25u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 21u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 22u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 23u +#define CYDEV_CHIP_MEMBER_4A 16u +#define CYDEV_CHIP_MEMBER_4D 12u +#define CYDEV_CHIP_MEMBER_4E 6u +#define CYDEV_CHIP_MEMBER_4F 17u +#define CYDEV_CHIP_MEMBER_4G 4u +#define CYDEV_CHIP_MEMBER_4H 15u +#define CYDEV_CHIP_MEMBER_4I 21u +#define CYDEV_CHIP_MEMBER_4J 13u +#define CYDEV_CHIP_MEMBER_4K 14u +#define CYDEV_CHIP_MEMBER_4L 20u +#define CYDEV_CHIP_MEMBER_4M 19u +#define CYDEV_CHIP_MEMBER_4N 9u +#define CYDEV_CHIP_MEMBER_4O 7u +#define CYDEV_CHIP_MEMBER_4P 18u +#define CYDEV_CHIP_MEMBER_4Q 11u +#define CYDEV_CHIP_MEMBER_4R 8u +#define CYDEV_CHIP_MEMBER_4S 10u +#define CYDEV_CHIP_MEMBER_4U 5u +#define CYDEV_CHIP_MEMBER_5A 3u +#define CYDEV_CHIP_MEMBER_5B 2u +#define CYDEV_CHIP_MEMBER_6A 22u +#define CYDEV_CHIP_MEMBER_FM3 26u +#define CYDEV_CHIP_MEMBER_FM4 27u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 23u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 24u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 25u #define CYDEV_CHIP_MEMBER_UNKNOWN 0u #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED @@ -3101,7 +3082,6 @@ #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u #define CYDEV_CHIP_REVISION_4A_ES0 17u #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u -#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u @@ -3120,12 +3100,16 @@ #define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u #define CYDEV_CHIP_REVISION_5A_ES0 0u #define CYDEV_CHIP_REVISION_5A_ES1 1u #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u #define CYDEV_CHIP_REVISION_5B_ES0 0u #define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_6A_NO_UDB 0u +#define CYDEV_CHIP_REVISION_6A_PRODUCTION 0u #define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u #define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u #define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u @@ -3157,7 +3141,7 @@ #define CYDEV_ECC_ENABLE 0 #define CYDEV_HEAP_SIZE 0x0400 #define CYDEV_INSTRUCT_CACHE_ENABLED 1 -#define CYDEV_INTR_RISING 0x0000007Eu +#define CYDEV_INTR_RISING 0x0000007Fu #define CYDEV_IS_EXPORTING_CODE 0 #define CYDEV_IS_IMPORTING_CODE 0 #define CYDEV_PROJ_TYPE 2 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 3b157aa..5800f1e 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -1,7 +1,8 @@ + /******************************************************************************* * File Name: cyfitter_cfg.c * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file contains device initialization code. @@ -9,7 +10,7 @@ * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -55,6 +56,19 @@ #error Unsupported toolchain #endif +#ifndef CYCODE + #define CYCODE +#endif +#ifndef CYDATA + #define CYDATA +#endif +#ifndef CYFAR + #define CYFAR +#endif +#ifndef CYXDATA + #define CYXDATA +#endif + CY_CFG_UNUSED static void CYMEMZERO(void *s, size_t n); @@ -86,6 +100,7 @@ static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) #define CYCLOCKSTART_XTAL_ERROR 1u #define CYCLOCKSTART_32KHZ_ERROR 2u #define CYCLOCKSTART_PLL_ERROR 3u +#define CYCLOCKSTART_FLL_ERROR 4u #ifdef CY_NEED_CYCLOCKSTARTUPERROR @@ -109,17 +124,21 @@ static void CyClockStartupError(uint8 errorCode); CY_CFG_UNUSED static void CyClockStartupError(uint8 errorCode) { - /* To remove the compiler warning if errorCode not used. */ + /* To remove the compiler warning if errorCode not used. */ +#if defined(CY_PSOC3) && (CY_PSOC3) errorCode = errorCode; +#else + (void)errorCode; +#endif /* CY_PSOC3 */ /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ /* we will end up here to allow the customer to implement something to */ /* deal with the clock condition. */ #ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK - CY_CFG_Clock_Startup_ErrorCallback(); + CY_CFG_Clock_Startup_ErrorCallback(); #else - /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */ + /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */ /* `#START CyClockStartupError` */ /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ @@ -128,10 +147,8 @@ static void CyClockStartupError(uint8 errorCode) /* `#END` */ - /* If nothing else, stop here since the clocks have not started */ - /* correctly. */ while(1) {} -#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ +#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ } #endif @@ -170,7 +187,7 @@ static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_ baseAddr &= 0xFFFFFF00u; while (count != 0u) { - CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value); + CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); j++; count--; } @@ -205,8 +222,8 @@ static void ClockSetup(void) CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u); - CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0031u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x18u); /* Configure ILO based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); @@ -305,7 +322,7 @@ void SetAnalogRoutingPumps(uint8 enabled) CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue); } -#define CY_AMUX_UNUSED CYREG_BOOST_SR + /******************************************************************************* @@ -317,7 +334,7 @@ void SetAnalogRoutingPumps(uint8 enabled) * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * -* Parameters: +* Parameters: * void * * Return: @@ -402,38 +419,38 @@ void cyfitter_cfg(void) 0x40006401u, /* Base address: 0x40006400 Count: 1 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ 0x4001004Au, /* Base address: 0x40010000 Count: 74 */ - 0x40010142u, /* Base address: 0x40010100 Count: 66 */ + 0x4001013Bu, /* Base address: 0x40010100 Count: 59 */ 0x40010248u, /* Base address: 0x40010200 Count: 72 */ - 0x40010355u, /* Base address: 0x40010300 Count: 85 */ + 0x40010353u, /* Base address: 0x40010300 Count: 83 */ 0x4001045Du, /* Base address: 0x40010400 Count: 93 */ - 0x4001055Au, /* Base address: 0x40010500 Count: 90 */ + 0x40010560u, /* Base address: 0x40010500 Count: 96 */ 0x40010657u, /* Base address: 0x40010600 Count: 87 */ - 0x4001075Au, /* Base address: 0x40010700 Count: 90 */ + 0x40010750u, /* Base address: 0x40010700 Count: 80 */ 0x40010851u, /* Base address: 0x40010800 Count: 81 */ - 0x40010953u, /* Base address: 0x40010900 Count: 83 */ + 0x40010955u, /* Base address: 0x40010900 Count: 85 */ 0x40010A4Au, /* Base address: 0x40010A00 Count: 74 */ - 0x40010B45u, /* Base address: 0x40010B00 Count: 69 */ - 0x40010D13u, /* Base address: 0x40010D00 Count: 19 */ + 0x40010B47u, /* Base address: 0x40010B00 Count: 71 */ + 0x40010D11u, /* Base address: 0x40010D00 Count: 17 */ 0x40010F06u, /* Base address: 0x40010F00 Count: 6 */ 0x4001141Au, /* Base address: 0x40011400 Count: 26 */ - 0x40011550u, /* Base address: 0x40011500 Count: 80 */ - 0x4001164Fu, /* Base address: 0x40011600 Count: 79 */ - 0x40011758u, /* Base address: 0x40011700 Count: 88 */ + 0x40011557u, /* Base address: 0x40011500 Count: 87 */ + 0x4001164Eu, /* Base address: 0x40011600 Count: 78 */ + 0x40011751u, /* Base address: 0x40011700 Count: 81 */ 0x40011849u, /* Base address: 0x40011800 Count: 73 */ - 0x40011955u, /* Base address: 0x40011900 Count: 85 */ + 0x40011950u, /* Base address: 0x40011900 Count: 80 */ 0x40011B09u, /* Base address: 0x40011B00 Count: 9 */ - 0x4001401Cu, /* Base address: 0x40014000 Count: 28 */ - 0x4001411Du, /* Base address: 0x40014100 Count: 29 */ + 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */ + 0x40014120u, /* Base address: 0x40014100 Count: 32 */ 0x40014214u, /* Base address: 0x40014200 Count: 20 */ - 0x40014309u, /* Base address: 0x40014300 Count: 9 */ + 0x4001430Cu, /* Base address: 0x40014300 Count: 12 */ 0x4001440Du, /* Base address: 0x40014400 Count: 13 */ - 0x40014515u, /* Base address: 0x40014500 Count: 21 */ - 0x40014613u, /* Base address: 0x40014600 Count: 19 */ - 0x40014711u, /* Base address: 0x40014700 Count: 17 */ - 0x40014808u, /* Base address: 0x40014800 Count: 8 */ - 0x4001490Au, /* Base address: 0x40014900 Count: 10 */ - 0x40014C06u, /* Base address: 0x40014C00 Count: 6 */ - 0x40014D06u, /* Base address: 0x40014D00 Count: 6 */ + 0x40014517u, /* Base address: 0x40014500 Count: 23 */ + 0x40014614u, /* Base address: 0x40014600 Count: 20 */ + 0x40014713u, /* Base address: 0x40014700 Count: 19 */ + 0x4001480Au, /* Base address: 0x40014800 Count: 10 */ + 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */ + 0x40014C05u, /* Base address: 0x40014C00 Count: 5 */ + 0x40014D05u, /* Base address: 0x40014D00 Count: 5 */ 0x40015006u, /* Base address: 0x40015000 Count: 6 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; @@ -448,10 +465,10 @@ void cyfitter_cfg(void) {0x19u, 0x04u}, {0x1Cu, 0x71u}, {0x20u, 0xA0u}, - {0x21u, 0x98u}, + {0x21u, 0x90u}, {0x2Cu, 0x0Eu}, - {0x30u, 0x05u}, - {0x31u, 0x09u}, + {0x30u, 0x09u}, + {0x31u, 0x05u}, {0x34u, 0x80u}, {0x7Cu, 0x40u}, {0x20u, 0x01u}, @@ -464,19 +481,19 @@ void cyfitter_cfg(void) {0x09u, 0x55u}, {0x0Au, 0x24u}, {0x0Bu, 0xAAu}, - {0x0Fu, 0xFFu}, - {0x10u, 0x24u}, {0x11u, 0x0Fu}, - {0x12u, 0x09u}, {0x13u, 0xF0u}, {0x17u, 0xFFu}, {0x18u, 0x24u}, {0x19u, 0xFFu}, {0x1Au, 0x12u}, {0x22u, 0x20u}, + {0x23u, 0xFFu}, {0x25u, 0x33u}, {0x26u, 0x04u}, {0x27u, 0xCCu}, + {0x28u, 0x24u}, + {0x2Au, 0x09u}, {0x2Bu, 0xFFu}, {0x30u, 0x07u}, {0x33u, 0xFFu}, @@ -487,10 +504,10 @@ void cyfitter_cfg(void) {0x40u, 0x32u}, {0x41u, 0x06u}, {0x42u, 0x10u}, - {0x45u, 0x0Du}, - {0x46u, 0x2Eu}, - {0x47u, 0xCFu}, - {0x48u, 0x3Du}, + {0x45u, 0xCEu}, + {0x46u, 0x2Du}, + {0x47u, 0x0Fu}, + {0x48u, 0x1Fu}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, {0x4Bu, 0xFFu}, @@ -511,7 +528,6 @@ void cyfitter_cfg(void) {0x6Eu, 0x08u}, {0x81u, 0x33u}, {0x83u, 0xCCu}, - {0x85u, 0xFFu}, {0x8Bu, 0xFFu}, {0x8Du, 0x0Fu}, {0x8Fu, 0xF0u}, @@ -519,7 +535,8 @@ void cyfitter_cfg(void) {0x93u, 0xAAu}, {0x97u, 0xFFu}, {0x99u, 0xFFu}, - {0xABu, 0xFFu}, + {0xA3u, 0xFFu}, + {0xA9u, 0xFFu}, {0xADu, 0x96u}, {0xAFu, 0x69u}, {0xB7u, 0xFFu}, @@ -531,87 +548,80 @@ void cyfitter_cfg(void) {0xDDu, 0x10u}, {0xDFu, 0x01u}, {0x00u, 0x04u}, - {0x01u, 0x02u}, + {0x01u, 0x0Au}, {0x03u, 0x04u}, - {0x09u, 0x22u}, + {0x09u, 0x20u}, {0x10u, 0x80u}, - {0x13u, 0x08u}, + {0x13u, 0x18u}, {0x18u, 0x04u}, {0x19u, 0x02u}, {0x23u, 0x22u}, {0x25u, 0x40u}, {0x29u, 0x20u}, - {0x2Au, 0x04u}, - {0x2Du, 0x60u}, + {0x2Au, 0x06u}, + {0x2Du, 0x40u}, + {0x2Eu, 0x02u}, + {0x2Fu, 0x04u}, {0x31u, 0x10u}, {0x33u, 0x05u}, {0x34u, 0x02u}, {0x35u, 0x10u}, {0x37u, 0x04u}, - {0x3Au, 0x99u}, - {0x3Bu, 0x80u}, - {0x3Cu, 0x20u}, + {0x3Au, 0x11u}, + {0x3Bu, 0x08u}, {0x3Du, 0x80u}, - {0x3Eu, 0x08u}, - {0x3Fu, 0x02u}, + {0x3Fu, 0x12u}, {0x41u, 0x20u}, - {0x42u, 0x08u}, {0x43u, 0x84u}, - {0x49u, 0x20u}, + {0x48u, 0x40u}, + {0x49u, 0x24u}, {0x4Au, 0x04u}, - {0x4Bu, 0x08u}, - {0x51u, 0x44u}, - {0x52u, 0x02u}, - {0x53u, 0x10u}, + {0x4Bu, 0x10u}, + {0x51u, 0x04u}, + {0x53u, 0x50u}, {0x5Au, 0xAAu}, {0x5Eu, 0x80u}, {0x61u, 0x08u}, {0x62u, 0x40u}, {0x63u, 0x44u}, - {0x69u, 0x24u}, - {0x6Au, 0x40u}, + {0x69u, 0xA4u}, {0x6Bu, 0x40u}, {0x70u, 0x8Au}, {0x73u, 0x08u}, - {0x80u, 0x04u}, - {0x81u, 0x40u}, + {0x81u, 0x42u}, {0x83u, 0x40u}, - {0x86u, 0x40u}, - {0x87u, 0x10u}, - {0x88u, 0x10u}, {0x89u, 0x10u}, - {0x8Bu, 0x40u}, + {0x8Du, 0x08u}, {0x8Fu, 0x40u}, {0xC0u, 0x0Eu}, - {0xC2u, 0x0Au}, - {0xC4u, 0x0Cu}, - {0xCAu, 0x36u}, + {0xC2u, 0x02u}, + {0xC4u, 0x0Eu}, + {0xCAu, 0xB7u}, {0xCCu, 0xE7u}, - {0xCEu, 0xFFu}, + {0xCEu, 0xB7u}, {0xD0u, 0x0Eu}, {0xD2u, 0x04u}, {0xD6u, 0x1Fu}, {0xD8u, 0x0Fu}, - {0xE0u, 0x04u}, - {0xE2u, 0x10u}, - {0xE4u, 0x01u}, - {0xE6u, 0x44u}, + {0xE0u, 0x01u}, + {0xE4u, 0x05u}, + {0xE6u, 0x40u}, {0x01u, 0x40u}, {0x03u, 0x80u}, {0x05u, 0x01u}, - {0x0Du, 0x0Bu}, - {0x0Fu, 0xF4u}, - {0x11u, 0x06u}, - {0x15u, 0x11u}, - {0x17u, 0xECu}, + {0x09u, 0x11u}, + {0x0Bu, 0xECu}, + {0x0Du, 0x06u}, + {0x13u, 0xFFu}, + {0x15u, 0x0Bu}, + {0x17u, 0xF4u}, {0x19u, 0xE0u}, - {0x21u, 0xCAu}, - {0x22u, 0x01u}, - {0x23u, 0x15u}, + {0x23u, 0x10u}, {0x25u, 0x40u}, {0x27u, 0x80u}, - {0x2Bu, 0x10u}, - {0x2Fu, 0xFFu}, + {0x29u, 0xCAu}, + {0x2Bu, 0x15u}, + {0x2Eu, 0x01u}, {0x32u, 0x01u}, {0x33u, 0xC0u}, {0x35u, 0x3Fu}, @@ -624,14 +634,14 @@ void cyfitter_cfg(void) {0x81u, 0x03u}, {0x82u, 0x02u}, {0x83u, 0x0Cu}, - {0x85u, 0x02u}, + {0x85u, 0x40u}, {0x86u, 0x0Du}, + {0x87u, 0x80u}, {0x8Au, 0x90u}, {0x8Bu, 0x01u}, - {0x8Du, 0xF4u}, + {0x8Du, 0x02u}, {0x8Eu, 0x60u}, {0x90u, 0x01u}, - {0x91u, 0x08u}, {0x92u, 0x02u}, {0x93u, 0xF7u}, {0x95u, 0x0Bu}, @@ -640,19 +650,19 @@ void cyfitter_cfg(void) {0x99u, 0x40u}, {0x9Au, 0x48u}, {0x9Bu, 0x80u}, - {0x9Cu, 0x90u}, - {0x9Du, 0xFDu}, - {0x9Eu, 0x24u}, - {0x9Fu, 0x02u}, + {0x9Du, 0x08u}, + {0x9Fu, 0xF7u}, + {0xA0u, 0x90u}, {0xA1u, 0x10u}, + {0xA2u, 0x24u}, {0xA3u, 0x20u}, {0xA5u, 0x10u}, {0xA7u, 0x20u}, - {0xA9u, 0x40u}, + {0xA9u, 0xF4u}, {0xAAu, 0x80u}, - {0xABu, 0x80u}, + {0xADu, 0xFDu}, {0xAEu, 0x10u}, - {0xAFu, 0xF7u}, + {0xAFu, 0x02u}, {0xB0u, 0xE0u}, {0xB3u, 0x30u}, {0xB4u, 0x1Cu}, @@ -670,128 +680,126 @@ void cyfitter_cfg(void) {0xDFu, 0x01u}, {0x00u, 0x02u}, {0x03u, 0x26u}, - {0x05u, 0x02u}, - {0x06u, 0x80u}, - {0x08u, 0x81u}, - {0x09u, 0x10u}, + {0x08u, 0x01u}, + {0x09u, 0x20u}, + {0x0Bu, 0x08u}, {0x10u, 0x0Au}, - {0x16u, 0x40u}, + {0x12u, 0x80u}, + {0x15u, 0x80u}, + {0x1Au, 0x04u}, {0x1Bu, 0x62u}, {0x1Eu, 0x20u}, + {0x20u, 0x04u}, {0x22u, 0x14u}, {0x23u, 0x01u}, - {0x25u, 0x38u}, - {0x2Au, 0x91u}, + {0x25u, 0x28u}, + {0x29u, 0x50u}, + {0x2Au, 0x01u}, {0x2Bu, 0x10u}, - {0x2Cu, 0x90u}, - {0x2Eu, 0x80u}, - {0x2Fu, 0x04u}, - {0x30u, 0x80u}, - {0x31u, 0x02u}, - {0x32u, 0x10u}, + {0x2Cu, 0x10u}, + {0x2Fu, 0x44u}, + {0x32u, 0xA2u}, {0x33u, 0x04u}, - {0x35u, 0x10u}, - {0x36u, 0x02u}, - {0x37u, 0x04u}, - {0x38u, 0x80u}, - {0x3Bu, 0x29u}, - {0x3Du, 0x08u}, - {0x3Eu, 0x40u}, + {0x35u, 0x12u}, + {0x36u, 0x06u}, + {0x38u, 0x04u}, + {0x3Bu, 0xA1u}, + {0x3Cu, 0x80u}, + {0x3Du, 0x28u}, + {0x3Eu, 0x80u}, {0x3Fu, 0x02u}, - {0x40u, 0x80u}, - {0x41u, 0x02u}, - {0x42u, 0x40u}, {0x44u, 0x10u}, {0x45u, 0x08u}, {0x4Eu, 0x04u}, {0x4Fu, 0x20u}, - {0x58u, 0x44u}, + {0x58u, 0x04u}, {0x5Au, 0x11u}, + {0x5Bu, 0x40u}, {0x5Du, 0x9Au}, {0x60u, 0x02u}, {0x61u, 0x80u}, - {0x62u, 0x15u}, + {0x62u, 0x35u}, {0x67u, 0x02u}, {0x81u, 0x08u}, {0x83u, 0x01u}, {0x84u, 0x01u}, {0x85u, 0x80u}, - {0x88u, 0x80u}, + {0x86u, 0x04u}, {0x89u, 0x20u}, - {0x8Fu, 0x20u}, - {0x91u, 0x8Cu}, - {0x93u, 0x28u}, + {0x8Bu, 0x10u}, + {0x8Fu, 0x42u}, + {0x91u, 0x0Cu}, + {0x93u, 0xA0u}, {0x95u, 0x40u}, {0x96u, 0xAAu}, - {0x97u, 0x54u}, + {0x97u, 0x4Cu}, {0x98u, 0x04u}, - {0x9Au, 0x80u}, + {0x99u, 0x04u}, {0x9Bu, 0x20u}, {0x9Cu, 0x02u}, {0x9Du, 0x10u}, - {0x9Eu, 0x15u}, + {0x9Eu, 0x57u}, {0x9Fu, 0x04u}, - {0xA0u, 0x0Au}, + {0xA0u, 0x4Au}, {0xA1u, 0x40u}, - {0xA2u, 0x02u}, - {0xA4u, 0x10u}, - {0xA5u, 0x2Au}, + {0xA5u, 0x28u}, {0xA6u, 0x44u}, {0xA7u, 0xC1u}, {0xADu, 0x04u}, {0xAFu, 0x23u}, {0xB0u, 0x04u}, - {0xB5u, 0x02u}, - {0xB6u, 0x40u}, + {0xB5u, 0x04u}, {0xC0u, 0x0Fu}, - {0xC2u, 0x0Bu}, - {0xC4u, 0x13u}, - {0xCAu, 0xFFu}, + {0xC2u, 0x0Au}, + {0xC4u, 0x8Bu}, + {0xCAu, 0xEFu}, {0xCCu, 0xEFu}, - {0xCEu, 0xDFu}, + {0xCEu, 0xFFu}, {0xD6u, 0xFFu}, {0xD8u, 0x1Fu}, + {0xE0u, 0x02u}, {0xE2u, 0x08u}, - {0xE6u, 0x0Du}, + {0xE6u, 0x0Eu}, + {0xEAu, 0x50u}, {0x00u, 0x04u}, - {0x01u, 0x04u}, + {0x01u, 0x10u}, {0x02u, 0x08u}, - {0x03u, 0x08u}, + {0x03u, 0x20u}, {0x04u, 0x08u}, {0x05u, 0x10u}, {0x06u, 0x37u}, {0x07u, 0x20u}, - {0x09u, 0x01u}, - {0x0Au, 0x40u}, - {0x0Bu, 0x02u}, - {0x0Du, 0x40u}, - {0x0Fu, 0x3Fu}, + {0x08u, 0x33u}, + {0x09u, 0x7Fu}, + {0x0Au, 0x04u}, + {0x0Eu, 0x37u}, + {0x0Fu, 0x40u}, {0x10u, 0x10u}, + {0x11u, 0x04u}, {0x12u, 0x20u}, - {0x13u, 0x40u}, - {0x14u, 0x01u}, - {0x15u, 0x40u}, - {0x16u, 0x02u}, - {0x17u, 0x3Fu}, + {0x13u, 0x08u}, + {0x14u, 0x08u}, + {0x15u, 0x01u}, + {0x16u, 0x37u}, + {0x17u, 0x02u}, {0x18u, 0x33u}, - {0x19u, 0x7Fu}, + {0x19u, 0x3Fu}, {0x1Au, 0x04u}, {0x1Cu, 0x01u}, {0x1Du, 0x01u}, {0x1Eu, 0x02u}, {0x1Fu, 0x02u}, - {0x20u, 0x33u}, - {0x21u, 0x10u}, - {0x22u, 0x04u}, - {0x23u, 0x20u}, - {0x25u, 0x04u}, - {0x26u, 0x37u}, - {0x27u, 0x08u}, + {0x21u, 0x04u}, + {0x23u, 0x08u}, + {0x25u, 0x40u}, + {0x26u, 0x40u}, + {0x27u, 0x3Fu}, {0x28u, 0x10u}, - {0x29u, 0x3Fu}, + {0x29u, 0x40u}, {0x2Au, 0x20u}, - {0x2Cu, 0x08u}, - {0x2Eu, 0x37u}, + {0x2Bu, 0x3Fu}, + {0x2Cu, 0x01u}, + {0x2Eu, 0x02u}, {0x2Fu, 0x3Fu}, {0x30u, 0x30u}, {0x31u, 0x0Cu}, @@ -812,182 +820,189 @@ void cyfitter_cfg(void) {0x5Du, 0x90u}, {0x5Fu, 0x01u}, {0x80u, 0x01u}, - {0x81u, 0x81u}, {0x82u, 0x02u}, - {0x83u, 0x2Eu}, + {0x83u, 0x60u}, {0x87u, 0x80u}, - {0x8Bu, 0x1Fu}, - {0x93u, 0x60u}, + {0x89u, 0x03u}, + {0x8Bu, 0x94u}, + {0x93u, 0x1Fu}, {0x94u, 0x02u}, - {0x95u, 0x03u}, + {0x95u, 0x81u}, {0x96u, 0x01u}, - {0x97u, 0x94u}, + {0x97u, 0x2Eu}, {0x98u, 0x02u}, + {0x99u, 0x04u}, {0x9Au, 0x11u}, - {0x9Bu, 0x01u}, {0x9Cu, 0x02u}, {0x9Eu, 0x09u}, {0xA0u, 0x02u}, - {0xA1u, 0x98u}, + {0xA1u, 0x02u}, {0xA2u, 0x05u}, - {0xA3u, 0x43u}, {0xA7u, 0x08u}, - {0xA9u, 0x02u}, - {0xADu, 0x04u}, + {0xA9u, 0x98u}, + {0xABu, 0x43u}, + {0xAFu, 0x01u}, {0xB0u, 0x03u}, + {0xB1u, 0xE0u}, {0xB2u, 0x10u}, {0xB4u, 0x08u}, {0xB5u, 0x1Fu}, {0xB6u, 0x04u}, - {0xB7u, 0xE0u}, {0xBAu, 0x02u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDCu, 0x11u}, {0xDFu, 0x01u}, - {0x02u, 0x28u}, + {0x01u, 0x20u}, + {0x02u, 0x22u}, {0x03u, 0x80u}, {0x05u, 0x01u}, + {0x08u, 0x08u}, {0x09u, 0x80u}, - {0x0Au, 0xA8u}, - {0x0Cu, 0x02u}, - {0x0Du, 0x0Au}, + {0x0Au, 0x80u}, + {0x0Bu, 0x08u}, + {0x0Du, 0x08u}, {0x0Eu, 0x06u}, - {0x10u, 0x82u}, + {0x10u, 0x10u}, {0x12u, 0x04u}, - {0x13u, 0x08u}, + {0x13u, 0x40u}, {0x14u, 0x20u}, {0x15u, 0x08u}, - {0x17u, 0x02u}, - {0x1Au, 0xA0u}, - {0x1Bu, 0xA8u}, + {0x16u, 0x40u}, + {0x18u, 0x04u}, + {0x1Au, 0x80u}, + {0x1Bu, 0x88u}, {0x1Cu, 0x80u}, {0x1Du, 0x09u}, {0x1Eu, 0x06u}, {0x1Fu, 0x01u}, - {0x21u, 0x01u}, - {0x22u, 0x81u}, - {0x23u, 0x14u}, + {0x22u, 0x09u}, + {0x23u, 0x05u}, + {0x25u, 0x11u}, {0x26u, 0x20u}, - {0x27u, 0x05u}, - {0x28u, 0x10u}, - {0x29u, 0x92u}, - {0x2Cu, 0x80u}, - {0x2Eu, 0x40u}, - {0x2Fu, 0x14u}, - {0x30u, 0x40u}, - {0x31u, 0x20u}, - {0x32u, 0x02u}, - {0x33u, 0x06u}, - {0x37u, 0x15u}, + {0x27u, 0x04u}, + {0x28u, 0x8Au}, + {0x2Au, 0x08u}, + {0x2Cu, 0x02u}, + {0x2Du, 0x02u}, + {0x2Fu, 0x54u}, + {0x31u, 0x10u}, + {0x32u, 0x89u}, + {0x34u, 0x02u}, + {0x35u, 0x10u}, + {0x36u, 0x06u}, {0x39u, 0x02u}, {0x3Au, 0x80u}, {0x3Bu, 0x14u}, - {0x3Cu, 0x20u}, - {0x3Du, 0x06u}, - {0x45u, 0x01u}, - {0x46u, 0x80u}, - {0x5Bu, 0x40u}, + {0x3Du, 0x27u}, + {0x42u, 0x80u}, + {0x43u, 0x02u}, + {0x44u, 0x02u}, + {0x45u, 0x10u}, + {0x46u, 0x0Au}, + {0x59u, 0x80u}, {0x63u, 0x02u}, {0x6Cu, 0x09u}, {0x6Du, 0x08u}, - {0x6Fu, 0x10u}, - {0x81u, 0x02u}, {0x83u, 0x04u}, - {0x84u, 0x50u}, - {0x88u, 0x08u}, + {0x84u, 0x80u}, + {0x85u, 0x01u}, + {0x86u, 0x80u}, + {0x87u, 0x48u}, + {0x89u, 0x81u}, + {0x8Cu, 0x08u}, {0x8Du, 0x40u}, {0x8Eu, 0x01u}, - {0x91u, 0x8Cu}, - {0x93u, 0x28u}, - {0x94u, 0x80u}, - {0x95u, 0x50u}, + {0x91u, 0x0Cu}, + {0x93u, 0xB8u}, + {0x95u, 0xC0u}, {0x96u, 0x82u}, - {0x97u, 0x16u}, - {0x9Au, 0x04u}, - {0x9Bu, 0x60u}, + {0x97u, 0x46u}, + {0x99u, 0x04u}, + {0x9Au, 0x84u}, + {0x9Bu, 0x20u}, {0x9Du, 0x10u}, - {0x9Eu, 0x40u}, + {0x9Eu, 0x02u}, {0x9Fu, 0x04u}, - {0xA0u, 0x80u}, - {0xA1u, 0xF0u}, - {0xA2u, 0x12u}, - {0xA4u, 0x10u}, - {0xA5u, 0x06u}, - {0xA6u, 0x44u}, - {0xA7u, 0x89u}, - {0xAAu, 0x10u}, - {0xABu, 0x40u}, - {0xACu, 0x41u}, - {0xAFu, 0x4Au}, + {0xA1u, 0xC0u}, + {0xA2u, 0x10u}, + {0xA5u, 0x14u}, + {0xA6u, 0x4Eu}, + {0xA7u, 0x81u}, + {0xAAu, 0x94u}, + {0xACu, 0x01u}, + {0xADu, 0x10u}, + {0xAEu, 0x48u}, + {0xB1u, 0x40u}, {0xB2u, 0x01u}, - {0xB5u, 0x04u}, - {0xC0u, 0x1Eu}, + {0xB3u, 0x04u}, + {0xC0u, 0x1Fu}, {0xC2u, 0xEFu}, - {0xC4u, 0x1Fu}, + {0xC4u, 0x17u}, {0xCAu, 0xFFu}, {0xCCu, 0xEFu}, {0xCEu, 0xEFu}, {0xD6u, 0x08u}, {0xD8u, 0x08u}, - {0xE0u, 0x01u}, - {0xE6u, 0x6Eu}, - {0xE8u, 0x08u}, + {0xE0u, 0x09u}, + {0xE2u, 0x10u}, + {0xE6u, 0x58u}, {0xEAu, 0x03u}, - {0xEEu, 0x4Du}, + {0xEEu, 0x08u}, {0x01u, 0x80u}, + {0x04u, 0xFFu}, {0x05u, 0x0Fu}, - {0x06u, 0xFFu}, - {0x08u, 0x60u}, - {0x09u, 0x20u}, - {0x0Au, 0x90u}, - {0x0Bu, 0x4Fu}, - {0x0Cu, 0x05u}, + {0x08u, 0x0Fu}, + {0x09u, 0x40u}, + {0x0Au, 0xF0u}, + {0x0Bu, 0x1Fu}, + {0x0Cu, 0x50u}, {0x0Du, 0x06u}, - {0x0Eu, 0x0Au}, + {0x0Eu, 0xA0u}, {0x0Fu, 0x09u}, - {0x10u, 0x50u}, {0x11u, 0x80u}, - {0x12u, 0xA0u}, + {0x12u, 0xFFu}, {0x14u, 0x30u}, - {0x15u, 0x40u}, + {0x15u, 0x10u}, {0x16u, 0xC0u}, - {0x17u, 0x1Fu}, + {0x17u, 0x2Fu}, {0x19u, 0x03u}, {0x1Au, 0xFFu}, {0x1Bu, 0x0Cu}, - {0x1Cu, 0xFFu}, + {0x1Cu, 0x03u}, + {0x1Eu, 0x0Cu}, {0x1Fu, 0x70u}, - {0x20u, 0x06u}, - {0x21u, 0x80u}, - {0x22u, 0x09u}, - {0x24u, 0x0Fu}, + {0x20u, 0x60u}, + {0x21u, 0x05u}, + {0x22u, 0x90u}, + {0x23u, 0x0Au}, + {0x24u, 0x05u}, {0x25u, 0x80u}, - {0x26u, 0xF0u}, - {0x28u, 0x03u}, - {0x29u, 0x05u}, - {0x2Au, 0x0Cu}, - {0x2Bu, 0x0Au}, - {0x2Du, 0x10u}, - {0x2Fu, 0x2Fu}, - {0x33u, 0x80u}, - {0x36u, 0xFFu}, + {0x26u, 0x0Au}, + {0x28u, 0x06u}, + {0x29u, 0x20u}, + {0x2Au, 0x09u}, + {0x2Bu, 0x4Fu}, + {0x2Du, 0x80u}, + {0x30u, 0xFFu}, + {0x35u, 0x80u}, {0x37u, 0x7Fu}, - {0x39u, 0x08u}, - {0x3Eu, 0x40u}, - {0x3Fu, 0x04u}, + {0x39u, 0x20u}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x10u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Cu, 0x10u}, {0x5Fu, 0x01u}, {0x81u, 0xD6u}, {0x84u, 0x01u}, - {0x85u, 0x17u}, + {0x85u, 0xD2u}, {0x86u, 0x06u}, - {0x87u, 0x28u}, + {0x87u, 0x04u}, {0x89u, 0xD0u}, {0x8Bu, 0x06u}, + {0x8Du, 0xD6u}, {0x8Eu, 0x08u}, {0x90u, 0x05u}, {0x91u, 0xD6u}, @@ -997,158 +1012,147 @@ void cyfitter_cfg(void) {0x99u, 0x29u}, {0x9Bu, 0x46u}, {0x9Cu, 0x04u}, - {0x9Du, 0xD6u}, + {0x9Du, 0x04u}, {0x9Eu, 0x03u}, {0xA1u, 0x21u}, {0xA2u, 0x10u}, {0xA3u, 0x8Eu}, {0xA4u, 0x03u}, - {0xA5u, 0xD2u}, + {0xA5u, 0x17u}, {0xA6u, 0x04u}, - {0xA7u, 0x04u}, + {0xA7u, 0x28u}, {0xA9u, 0x02u}, {0xACu, 0x08u}, - {0xADu, 0x04u}, {0xAEu, 0x10u}, - {0xB0u, 0x18u}, + {0xB1u, 0x0Fu}, {0xB3u, 0xF0u}, {0xB4u, 0x18u}, {0xB5u, 0x0Fu}, {0xB6u, 0x07u}, - {0xB9u, 0x20u}, + {0xB9u, 0x22u}, {0xBAu, 0x80u}, {0xBBu, 0x08u}, - {0xBEu, 0x11u}, + {0xBEu, 0x10u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, {0x00u, 0x84u}, - {0x05u, 0x40u}, - {0x06u, 0x04u}, - {0x07u, 0x10u}, + {0x04u, 0x20u}, + {0x05u, 0x08u}, + {0x06u, 0x02u}, {0x0Au, 0x82u}, - {0x0Du, 0x01u}, + {0x0Cu, 0x89u}, {0x0Eu, 0x04u}, - {0x0Fu, 0x22u}, + {0x0Fu, 0x40u}, {0x11u, 0x40u}, - {0x12u, 0x20u}, - {0x13u, 0x03u}, - {0x14u, 0x80u}, - {0x15u, 0x20u}, - {0x16u, 0x10u}, - {0x18u, 0x80u}, - {0x19u, 0x10u}, - {0x1Au, 0x4Au}, + {0x12u, 0x60u}, + {0x16u, 0x90u}, + {0x17u, 0x10u}, + {0x18u, 0x08u}, + {0x19u, 0x30u}, + {0x1Au, 0x02u}, {0x1Bu, 0x40u}, - {0x1Fu, 0x40u}, + {0x1Eu, 0x40u}, + {0x20u, 0x48u}, {0x21u, 0x08u}, {0x22u, 0x20u}, - {0x24u, 0x10u}, + {0x25u, 0x20u}, {0x26u, 0x40u}, {0x29u, 0x01u}, - {0x2Au, 0x08u}, - {0x2Bu, 0x06u}, - {0x2Cu, 0x20u}, - {0x2Eu, 0xA0u}, - {0x2Fu, 0x40u}, - {0x31u, 0x88u}, - {0x32u, 0x20u}, + {0x2Bu, 0x14u}, + {0x2Eu, 0x48u}, + {0x2Fu, 0x44u}, + {0x31u, 0x08u}, + {0x32u, 0xA0u}, {0x33u, 0x01u}, - {0x35u, 0x02u}, - {0x36u, 0x40u}, - {0x37u, 0x24u}, - {0x38u, 0x04u}, - {0x39u, 0x11u}, + {0x36u, 0x45u}, + {0x37u, 0x20u}, + {0x38u, 0x80u}, + {0x39u, 0x19u}, {0x3Du, 0xA8u}, {0x3Eu, 0x05u}, - {0x41u, 0x40u}, - {0x43u, 0x40u}, - {0x58u, 0x26u}, + {0x58u, 0x24u}, + {0x59u, 0x02u}, {0x5Bu, 0x40u}, - {0x62u, 0x80u}, + {0x63u, 0x01u}, {0x69u, 0x40u}, - {0x7Fu, 0x0Cu}, - {0x82u, 0x04u}, - {0x83u, 0x10u}, - {0x84u, 0x80u}, - {0x88u, 0x40u}, + {0x80u, 0x90u}, + {0x81u, 0x08u}, + {0x84u, 0x08u}, + {0x86u, 0x02u}, + {0x87u, 0x40u}, + {0x89u, 0x20u}, {0x8Au, 0x10u}, - {0x8Bu, 0x01u}, - {0x8Cu, 0x10u}, - {0x8Du, 0x02u}, - {0x8Fu, 0x10u}, - {0x91u, 0xA0u}, - {0x93u, 0x08u}, - {0x94u, 0x80u}, - {0x96u, 0x48u}, + {0x8Bu, 0x40u}, + {0x8Cu, 0x08u}, + {0x8Eu, 0x05u}, + {0x93u, 0x09u}, + {0x95u, 0x80u}, {0x98u, 0x24u}, - {0x9Bu, 0x24u}, - {0x9Du, 0x10u}, + {0x99u, 0x06u}, + {0x9Bu, 0x20u}, + {0x9Cu, 0x1Au}, + {0x9Du, 0x30u}, {0x9Eu, 0x41u}, - {0x9Fu, 0x0Au}, {0xA0u, 0xC0u}, {0xA1u, 0x54u}, - {0xA2u, 0x90u}, - {0xA3u, 0x20u}, - {0xA4u, 0x10u}, - {0xA5u, 0x03u}, - {0xA6u, 0x4Cu}, - {0xA8u, 0x01u}, - {0xADu, 0x90u}, - {0xAFu, 0x09u}, + {0xA2u, 0x10u}, + {0xA6u, 0x44u}, + {0xA8u, 0x03u}, + {0xA9u, 0x04u}, + {0xACu, 0x80u}, {0xB0u, 0x04u}, - {0xB1u, 0x10u}, {0xB3u, 0x02u}, + {0xB4u, 0x04u}, {0xC0u, 0xE5u}, {0xC2u, 0xF9u}, {0xC4u, 0x7Du}, - {0xCAu, 0xFFu}, + {0xCAu, 0xF7u}, {0xCCu, 0xFFu}, - {0xCEu, 0xF7u}, + {0xCEu, 0xFFu}, {0xD6u, 0x0Fu}, {0xD8u, 0x08u}, - {0xE2u, 0x11u}, - {0xE6u, 0x03u}, - {0xE8u, 0x02u}, - {0xEAu, 0x20u}, - {0xEEu, 0x01u}, + {0xE2u, 0x0Eu}, + {0xE6u, 0x8Du}, + {0xEAu, 0x40u}, + {0xEEu, 0x02u}, + {0x00u, 0xFFu}, {0x01u, 0x08u}, {0x03u, 0x05u}, {0x04u, 0x55u}, - {0x05u, 0x40u}, {0x06u, 0xAAu}, - {0x07u, 0x10u}, + {0x07u, 0x30u}, {0x0Au, 0xFFu}, - {0x0Bu, 0x30u}, - {0x0Cu, 0xFFu}, - {0x0Fu, 0x40u}, - {0x10u, 0x0Fu}, + {0x0Bu, 0x40u}, {0x11u, 0x08u}, - {0x12u, 0xF0u}, {0x13u, 0x06u}, {0x15u, 0x04u}, {0x16u, 0xFFu}, {0x17u, 0x08u}, + {0x18u, 0x0Fu}, {0x19u, 0x08u}, - {0x1Au, 0xFFu}, + {0x1Au, 0xF0u}, {0x1Bu, 0x04u}, - {0x1Cu, 0x69u}, - {0x1Eu, 0x96u}, + {0x1Cu, 0xFFu}, + {0x20u, 0x69u}, {0x21u, 0x40u}, + {0x22u, 0x96u}, {0x23u, 0x20u}, - {0x24u, 0xFFu}, + {0x24u, 0x33u}, {0x25u, 0x08u}, + {0x26u, 0xCCu}, {0x27u, 0x04u}, - {0x28u, 0x33u}, - {0x2Au, 0xCCu}, {0x2Bu, 0x40u}, - {0x30u, 0xFFu}, + {0x2Du, 0x40u}, + {0x2Eu, 0xFFu}, + {0x2Fu, 0x10u}, {0x31u, 0x01u}, {0x33u, 0x0Cu}, + {0x34u, 0xFFu}, {0x35u, 0x70u}, {0x37u, 0x02u}, - {0x3Au, 0x02u}, + {0x3Au, 0x20u}, {0x3Bu, 0x08u}, {0x56u, 0x08u}, {0x58u, 0x04u}, @@ -1158,35 +1162,35 @@ void cyfitter_cfg(void) {0x5Du, 0x90u}, {0x5Fu, 0x01u}, {0x80u, 0xFFu}, + {0x83u, 0x02u}, {0x84u, 0x30u}, {0x86u, 0xC0u}, {0x87u, 0x01u}, - {0x88u, 0x50u}, - {0x8Au, 0xA0u}, {0x8Bu, 0x20u}, - {0x8Cu, 0x90u}, - {0x8Eu, 0x60u}, - {0x90u, 0x03u}, - {0x92u, 0x0Cu}, - {0x93u, 0x04u}, + {0x8Cu, 0x03u}, + {0x8Eu, 0x0Cu}, + {0x8Fu, 0x04u}, {0x94u, 0xFFu}, - {0x97u, 0x10u}, {0x98u, 0x05u}, {0x9Au, 0x0Au}, - {0x9Bu, 0x08u}, + {0x9Cu, 0x90u}, + {0x9Eu, 0x60u}, {0xA2u, 0xFFu}, - {0xA3u, 0x02u}, - {0xA8u, 0x09u}, - {0xAAu, 0x06u}, + {0xA4u, 0x09u}, + {0xA6u, 0x06u}, + {0xA7u, 0x10u}, + {0xA8u, 0x50u}, + {0xAAu, 0xA0u}, + {0xABu, 0x08u}, {0xACu, 0x0Fu}, {0xADu, 0x15u}, {0xAEu, 0xF0u}, {0xAFu, 0x2Au}, - {0xB1u, 0x03u}, - {0xB3u, 0x0Cu}, - {0xB5u, 0x30u}, - {0xB6u, 0xFFu}, - {0xBEu, 0x40u}, + {0xB1u, 0x0Cu}, + {0xB3u, 0x30u}, + {0xB4u, 0xFFu}, + {0xB5u, 0x03u}, + {0xBEu, 0x10u}, {0xBFu, 0x15u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, @@ -1194,110 +1198,112 @@ void cyfitter_cfg(void) {0xDBu, 0x04u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x10u}, - {0x02u, 0x23u}, - {0x03u, 0x88u}, - {0x05u, 0x80u}, + {0x00u, 0x40u}, + {0x01u, 0x02u}, + {0x02u, 0x10u}, + {0x03u, 0x80u}, {0x06u, 0x20u}, - {0x07u, 0x04u}, - {0x08u, 0x01u}, - {0x09u, 0x04u}, - {0x0Au, 0x08u}, - {0x0Bu, 0x20u}, - {0x0Cu, 0x68u}, - {0x0Eu, 0x40u}, - {0x0Fu, 0x08u}, - {0x11u, 0xA0u}, - {0x13u, 0x02u}, - {0x16u, 0x08u}, - {0x17u, 0x08u}, - {0x18u, 0x02u}, - {0x1Eu, 0x40u}, - {0x20u, 0x80u}, + {0x07u, 0x44u}, + {0x0Au, 0x04u}, + {0x0Bu, 0x22u}, + {0x0Cu, 0x08u}, + {0x0Du, 0x20u}, + {0x0Eu, 0x01u}, + {0x10u, 0x80u}, + {0x11u, 0x90u}, + {0x13u, 0x04u}, + {0x14u, 0x50u}, + {0x15u, 0x40u}, + {0x19u, 0x20u}, + {0x1Du, 0x20u}, + {0x20u, 0x08u}, {0x21u, 0x08u}, - {0x23u, 0x04u}, + {0x23u, 0x40u}, {0x24u, 0x04u}, - {0x25u, 0x10u}, {0x26u, 0x85u}, - {0x2Au, 0x01u}, - {0x2Bu, 0x02u}, + {0x2Au, 0x10u}, + {0x2Bu, 0x12u}, {0x2Cu, 0x08u}, - {0x2Fu, 0x60u}, - {0x30u, 0x01u}, - {0x32u, 0x24u}, - {0x36u, 0x15u}, - {0x38u, 0x04u}, - {0x39u, 0x14u}, - {0x3Du, 0x20u}, - {0x3Fu, 0x8Au}, + {0x2Du, 0x40u}, + {0x2Eu, 0x01u}, + {0x2Fu, 0x20u}, + {0x36u, 0x25u}, + {0x38u, 0x46u}, + {0x39u, 0x10u}, + {0x3Bu, 0x82u}, + {0x3Cu, 0x04u}, + {0x3Du, 0x28u}, + {0x3Fu, 0x06u}, {0x5Au, 0x80u}, {0x5Eu, 0x80u}, {0x63u, 0x02u}, {0x64u, 0x02u}, {0x6Du, 0x80u}, {0x6Fu, 0x03u}, - {0x82u, 0x22u}, - {0x85u, 0x0Cu}, - {0x8Au, 0x40u}, - {0x8Bu, 0x81u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x04u}, - {0x90u, 0x20u}, - {0x92u, 0x18u}, + {0x81u, 0x0Au}, + {0x83u, 0x02u}, + {0x85u, 0x30u}, + {0x86u, 0x10u}, + {0x87u, 0x40u}, + {0x8Au, 0x04u}, + {0x8Bu, 0x10u}, + {0x8Du, 0x60u}, + {0x92u, 0x15u}, {0x93u, 0xA0u}, - {0x95u, 0x01u}, - {0x97u, 0x44u}, - {0x98u, 0x41u}, - {0x9Au, 0x28u}, - {0x9Bu, 0x18u}, - {0x9Du, 0x25u}, - {0x9Eu, 0x10u}, + {0x95u, 0x41u}, + {0x98u, 0x58u}, + {0x99u, 0x80u}, + {0x9Au, 0x20u}, + {0x9Bu, 0x10u}, + {0x9Du, 0x15u}, {0x9Fu, 0x01u}, {0xA0u, 0x08u}, - {0xA2u, 0x10u}, - {0xA3u, 0x40u}, - {0xA4u, 0x65u}, + {0xA1u, 0x10u}, + {0xA2u, 0x60u}, + {0xA3u, 0x10u}, + {0xA4u, 0x45u}, {0xA6u, 0x84u}, {0xA8u, 0x40u}, {0xAAu, 0x40u}, - {0xACu, 0x01u}, - {0xAFu, 0x10u}, - {0xB0u, 0x05u}, - {0xB7u, 0x02u}, - {0xC0u, 0xEFu}, - {0xC2u, 0xFEu}, - {0xC4u, 0x6Bu}, - {0xCAu, 0xE9u}, - {0xCCu, 0xE7u}, - {0xCEu, 0xF6u}, + {0xACu, 0x10u}, + {0xB2u, 0x40u}, + {0xB5u, 0xA0u}, + {0xC0u, 0x7Du}, + {0xC2u, 0xE7u}, + {0xC4u, 0xBFu}, + {0xCAu, 0xFEu}, + {0xCCu, 0xE0u}, + {0xCEu, 0xEFu}, {0xD6u, 0x18u}, {0xD8u, 0x18u}, - {0xE0u, 0x02u}, - {0xE2u, 0xC0u}, - {0xE6u, 0x60u}, - {0xEAu, 0xACu}, - {0xEEu, 0x05u}, + {0xE0u, 0x41u}, + {0xE2u, 0x30u}, + {0xE4u, 0x02u}, + {0xE6u, 0x21u}, + {0xEAu, 0x44u}, + {0xECu, 0x40u}, + {0xEEu, 0x04u}, {0x01u, 0x02u}, {0x02u, 0x02u}, {0x03u, 0x01u}, {0x0Cu, 0x01u}, {0x0Eu, 0x02u}, - {0x10u, 0x90u}, - {0x12u, 0x48u}, {0x15u, 0x02u}, {0x16u, 0x61u}, {0x17u, 0x09u}, {0x19u, 0x01u}, {0x1Au, 0x0Cu}, {0x1Bu, 0x02u}, + {0x1Cu, 0x90u}, {0x1Du, 0x02u}, - {0x1Eu, 0x10u}, + {0x1Eu, 0x48u}, {0x1Fu, 0x11u}, {0x22u, 0x80u}, - {0x24u, 0x90u}, - {0x26u, 0x24u}, + {0x26u, 0x10u}, {0x2Au, 0x90u}, + {0x2Cu, 0x90u}, {0x2Du, 0x02u}, + {0x2Eu, 0x24u}, {0x2Fu, 0x05u}, {0x30u, 0x03u}, {0x31u, 0x10u}, @@ -1325,18 +1331,18 @@ void cyfitter_cfg(void) {0x8Cu, 0x0Fu}, {0x8Eu, 0xF0u}, {0x8Fu, 0x01u}, + {0x90u, 0x03u}, {0x91u, 0x0Au}, + {0x92u, 0x0Cu}, {0x93u, 0x14u}, - {0x97u, 0x04u}, + {0x97u, 0x02u}, {0x98u, 0x06u}, {0x9Au, 0x09u}, - {0x9Bu, 0x02u}, + {0x9Bu, 0x10u}, {0x9Fu, 0x20u}, {0xA4u, 0x05u}, {0xA6u, 0x0Au}, - {0xABu, 0x10u}, - {0xACu, 0x03u}, - {0xAEu, 0x0Cu}, + {0xA7u, 0x04u}, {0xB1u, 0x06u}, {0xB3u, 0x01u}, {0xB4u, 0xFFu}, @@ -1353,115 +1359,115 @@ void cyfitter_cfg(void) {0xDFu, 0x01u}, {0x01u, 0x01u}, {0x03u, 0x01u}, - {0x05u, 0x2Bu}, - {0x06u, 0x10u}, + {0x05u, 0x1Fu}, {0x07u, 0x01u}, - {0x09u, 0x40u}, - {0x0Au, 0x14u}, - {0x0Bu, 0x80u}, + {0x0Au, 0x15u}, + {0x0Cu, 0x01u}, {0x0Fu, 0x08u}, {0x10u, 0x28u}, - {0x11u, 0x02u}, - {0x14u, 0x20u}, - {0x15u, 0x48u}, - {0x1Au, 0x1Cu}, - {0x1Bu, 0x02u}, + {0x11u, 0x42u}, + {0x17u, 0x08u}, + {0x1Au, 0x14u}, + {0x1Bu, 0x12u}, {0x1Fu, 0x10u}, {0x21u, 0x29u}, {0x22u, 0x40u}, {0x24u, 0x02u}, - {0x26u, 0x11u}, + {0x26u, 0x21u}, {0x27u, 0x10u}, {0x28u, 0x02u}, - {0x2Du, 0x20u}, + {0x2Du, 0x08u}, {0x31u, 0x28u}, {0x32u, 0x40u}, - {0x34u, 0x20u}, - {0x35u, 0x08u}, + {0x35u, 0x10u}, {0x36u, 0x80u}, - {0x37u, 0x01u}, + {0x37u, 0x09u}, {0x39u, 0x02u}, - {0x3Fu, 0x48u}, + {0x3Cu, 0x80u}, + {0x3Fu, 0x08u}, {0x5Au, 0x40u}, {0x5Cu, 0x44u}, - {0x5Fu, 0x12u}, + {0x5Du, 0x20u}, + {0x5Fu, 0x02u}, {0x60u, 0x02u}, - {0x64u, 0x40u}, - {0x66u, 0x2Au}, - {0x67u, 0x0Au}, + {0x64u, 0x50u}, + {0x66u, 0x20u}, + {0x67u, 0x4Au}, {0x80u, 0x08u}, - {0x82u, 0x02u}, - {0x86u, 0x08u}, - {0x87u, 0x04u}, - {0x8Bu, 0x04u}, + {0x84u, 0x04u}, + {0x87u, 0x44u}, + {0x8Bu, 0x40u}, + {0x8Eu, 0x01u}, {0x8Fu, 0x03u}, - {0x90u, 0x24u}, - {0x91u, 0x48u}, - {0x93u, 0x80u}, + {0x90u, 0x04u}, + {0x92u, 0x01u}, {0x94u, 0x02u}, - {0x9Bu, 0x08u}, - {0x9Du, 0x06u}, + {0x98u, 0x09u}, + {0x9Bu, 0x0Au}, + {0x9Du, 0x02u}, {0x9Fu, 0x01u}, - {0xA1u, 0x41u}, - {0xA3u, 0x44u}, - {0xA4u, 0x40u}, + {0xA0u, 0x20u}, + {0xA1u, 0x11u}, + {0xA3u, 0x04u}, + {0xA4u, 0x01u}, {0xA5u, 0x20u}, - {0xA6u, 0x05u}, - {0xADu, 0x04u}, + {0xA6u, 0x04u}, + {0xABu, 0x02u}, + {0xACu, 0x01u}, {0xAFu, 0x01u}, {0xC0u, 0xF9u}, - {0xC2u, 0x4Fu}, - {0xC4u, 0xAEu}, - {0xCAu, 0x28u}, + {0xC2u, 0x57u}, + {0xC4u, 0x2Fu}, + {0xCAu, 0x48u}, {0xCCu, 0xFEu}, {0xCEu, 0x51u}, {0xD6u, 0xF8u}, {0xD8u, 0xF8u}, - {0xE2u, 0x40u}, + {0xE2u, 0x70u}, + {0xE4u, 0x02u}, + {0xE6u, 0x80u}, {0xEAu, 0x01u}, - {0xEEu, 0x8Du}, + {0xEEu, 0x81u}, {0x80u, 0x04u}, - {0x81u, 0x04u}, {0x82u, 0x04u}, + {0x84u, 0x01u}, {0x85u, 0x22u}, - {0x88u, 0x40u}, - {0x8Bu, 0x48u}, - {0x8Du, 0x40u}, - {0x90u, 0x20u}, + {0x8Au, 0x01u}, + {0x8Fu, 0x08u}, {0x94u, 0x02u}, - {0xA1u, 0x41u}, - {0xA3u, 0x44u}, - {0xA6u, 0x01u}, - {0xB7u, 0x44u}, - {0xE0u, 0x40u}, - {0xE2u, 0x04u}, - {0xE4u, 0x80u}, - {0xE8u, 0x40u}, - {0xECu, 0x40u}, + {0x98u, 0x08u}, + {0xA0u, 0x20u}, + {0xA1u, 0x11u}, + {0xA3u, 0x04u}, + {0xB4u, 0x01u}, + {0xE2u, 0x14u}, + {0xE4u, 0xC0u}, + {0xE6u, 0x02u}, + {0xEAu, 0x40u}, {0xEEu, 0x80u}, - {0x80u, 0x11u}, - {0x81u, 0x01u}, - {0x89u, 0x40u}, - {0x8Eu, 0x01u}, - {0xE2u, 0x10u}, + {0x81u, 0x11u}, + {0x83u, 0x04u}, + {0x88u, 0x20u}, + {0x8Cu, 0x08u}, + {0xE0u, 0x40u}, {0xE4u, 0x20u}, {0x82u, 0x02u}, {0x83u, 0x07u}, + {0x87u, 0x2Au}, {0x88u, 0x11u}, {0x8Au, 0x22u}, - {0x8Cu, 0x28u}, - {0x8Eu, 0x13u}, - {0x91u, 0x34u}, + {0x8Cu, 0x14u}, + {0x8Du, 0x34u}, + {0x8Eu, 0x43u}, + {0x90u, 0x28u}, + {0x92u, 0x13u}, {0x95u, 0x07u}, {0x96u, 0x01u}, {0x98u, 0x60u}, - {0x9Bu, 0x2Au}, + {0x99u, 0x01u}, + {0x9Bu, 0x18u}, {0x9Eu, 0x0Cu}, {0x9Fu, 0x08u}, - {0xA4u, 0x14u}, - {0xA6u, 0x43u}, - {0xA9u, 0x01u}, - {0xABu, 0x18u}, {0xB1u, 0x38u}, {0xB4u, 0x70u}, {0xB6u, 0x0Fu}, @@ -1471,116 +1477,122 @@ void cyfitter_cfg(void) {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDFu, 0x01u}, - {0x00u, 0x04u}, - {0x01u, 0x01u}, + {0x00u, 0x08u}, + {0x01u, 0x21u}, {0x03u, 0x01u}, {0x04u, 0x40u}, - {0x05u, 0x20u}, + {0x05u, 0x10u}, {0x06u, 0x40u}, {0x09u, 0x80u}, - {0x0Au, 0x94u}, - {0x0Eu, 0x2Au}, - {0x0Fu, 0x01u}, + {0x0Au, 0x54u}, + {0x0Eu, 0x6Au}, + {0x0Fu, 0x02u}, {0x11u, 0x10u}, - {0x12u, 0x21u}, - {0x13u, 0x08u}, - {0x17u, 0x08u}, - {0x18u, 0x44u}, - {0x19u, 0x29u}, - {0x1Au, 0x90u}, - {0x1Bu, 0x04u}, + {0x12u, 0x80u}, + {0x18u, 0x04u}, + {0x19u, 0x31u}, + {0x1Au, 0xF0u}, + {0x1Bu, 0x14u}, {0x1Eu, 0x0Au}, {0x22u, 0x02u}, {0x27u, 0x82u}, - {0x29u, 0x29u}, + {0x29u, 0x11u}, {0x2Au, 0x40u}, - {0x2Du, 0x20u}, - {0x31u, 0x10u}, - {0x32u, 0x20u}, + {0x32u, 0x10u}, {0x33u, 0x49u}, - {0x35u, 0x01u}, - {0x36u, 0x24u}, + {0x35u, 0x10u}, + {0x36u, 0x04u}, {0x37u, 0x80u}, - {0x38u, 0x80u}, + {0x38u, 0x40u}, {0x39u, 0x18u}, - {0x3Fu, 0x01u}, - {0x40u, 0x64u}, - {0x49u, 0x14u}, + {0x3Au, 0x02u}, + {0x3Cu, 0x08u}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x02u}, + {0x40u, 0x04u}, + {0x42u, 0x60u}, + {0x48u, 0x04u}, + {0x49u, 0x04u}, + {0x4Au, 0x80u}, {0x4Bu, 0x40u}, {0x50u, 0x20u}, - {0x52u, 0x41u}, - {0x53u, 0x06u}, + {0x51u, 0x42u}, + {0x52u, 0x40u}, + {0x53u, 0x80u}, {0x63u, 0x80u}, {0x69u, 0x19u}, {0x6Au, 0x04u}, {0x6Bu, 0x61u}, {0x70u, 0x40u}, {0x71u, 0x80u}, - {0x80u, 0x20u}, + {0x72u, 0x02u}, + {0x82u, 0x20u}, + {0x85u, 0x02u}, {0x87u, 0x02u}, {0x8Bu, 0x80u}, + {0x90u, 0x40u}, {0x93u, 0x40u}, {0x94u, 0x84u}, - {0x95u, 0x19u}, + {0x95u, 0x99u}, {0x96u, 0x90u}, - {0x97u, 0x08u}, {0x9Du, 0x05u}, - {0x9Eu, 0x40u}, {0x9Fu, 0x61u}, - {0xA2u, 0x30u}, + {0xA0u, 0x04u}, + {0xA2u, 0x10u}, {0xA3u, 0x48u}, {0xA4u, 0x20u}, {0xA5u, 0x80u}, - {0xA6u, 0x02u}, - {0xA7u, 0x06u}, - {0xA8u, 0x08u}, - {0xAEu, 0x60u}, - {0xB1u, 0x04u}, - {0xB2u, 0x08u}, - {0xB3u, 0x20u}, + {0xA6u, 0x82u}, + {0xA7u, 0x94u}, + {0xA9u, 0x04u}, + {0xABu, 0x01u}, + {0xAEu, 0x20u}, + {0xB0u, 0x20u}, {0xB4u, 0x01u}, - {0xC0u, 0xDDu}, - {0xC2u, 0xEFu}, - {0xC4u, 0x27u}, - {0xCAu, 0x2Fu}, - {0xCCu, 0xFFu}, - {0xCEu, 0x8Eu}, + {0xB5u, 0x10u}, + {0xB6u, 0x88u}, + {0xC0u, 0xDFu}, + {0xC2u, 0xFFu}, + {0xC4u, 0x0Au}, + {0xCAu, 0x0Du}, + {0xCCu, 0x7Fu}, + {0xCEu, 0xDFu}, {0xD0u, 0x07u}, {0xD2u, 0x0Cu}, {0xD8u, 0x01u}, + {0xE0u, 0x02u}, {0xE6u, 0x20u}, - {0xEAu, 0x09u}, - {0xEEu, 0x02u}, - {0x01u, 0x05u}, - {0x03u, 0x08u}, - {0x04u, 0x0Fu}, - {0x06u, 0xF0u}, + {0xE8u, 0x04u}, + {0xEAu, 0x29u}, + {0x00u, 0x60u}, + {0x02u, 0x90u}, + {0x06u, 0xFFu}, {0x07u, 0x01u}, - {0x08u, 0x60u}, - {0x0Au, 0x90u}, - {0x0Cu, 0x05u}, - {0x0Eu, 0x0Au}, - {0x0Fu, 0x08u}, - {0x10u, 0x50u}, - {0x12u, 0xA0u}, + {0x08u, 0x0Fu}, + {0x09u, 0x01u}, + {0x0Au, 0xF0u}, + {0x0Bu, 0x08u}, + {0x0Cu, 0x50u}, + {0x0Eu, 0xA0u}, + {0x10u, 0xFFu}, + {0x11u, 0x02u}, {0x14u, 0x30u}, - {0x15u, 0x01u}, + {0x15u, 0x05u}, {0x16u, 0xC0u}, {0x17u, 0x08u}, - {0x18u, 0x03u}, - {0x1Au, 0x0Cu}, - {0x1Eu, 0xFFu}, - {0x20u, 0x06u}, - {0x21u, 0x04u}, - {0x22u, 0x09u}, - {0x23u, 0x08u}, - {0x26u, 0xFFu}, - {0x28u, 0xFFu}, - {0x2Du, 0x02u}, - {0x31u, 0x0Fu}, + {0x1Au, 0xFFu}, + {0x1Bu, 0x08u}, + {0x1Cu, 0x03u}, + {0x1Eu, 0x0Cu}, + {0x24u, 0x05u}, + {0x26u, 0x0Au}, + {0x28u, 0x06u}, + {0x29u, 0x04u}, + {0x2Au, 0x09u}, + {0x2Bu, 0x08u}, {0x33u, 0x0Fu}, {0x36u, 0xFFu}, - {0x39u, 0x0Au}, + {0x39u, 0x08u}, {0x3Eu, 0x40u}, {0x56u, 0x08u}, {0x58u, 0x04u}, @@ -1590,6 +1602,7 @@ void cyfitter_cfg(void) {0x5Du, 0x90u}, {0x5Fu, 0x01u}, {0x80u, 0x10u}, + {0x83u, 0x04u}, {0x84u, 0x87u}, {0x85u, 0x03u}, {0x86u, 0x18u}, @@ -1601,7 +1614,6 @@ void cyfitter_cfg(void) {0x92u, 0x08u}, {0x93u, 0x03u}, {0x94u, 0x01u}, - {0x97u, 0x04u}, {0x98u, 0x40u}, {0x9Bu, 0x01u}, {0x9Cu, 0x01u}, @@ -1631,105 +1643,97 @@ void cyfitter_cfg(void) {0xDCu, 0x10u}, {0xDFu, 0x01u}, {0x00u, 0x04u}, - {0x02u, 0x40u}, - {0x03u, 0x09u}, - {0x05u, 0x40u}, - {0x06u, 0x14u}, + {0x03u, 0x89u}, + {0x04u, 0x20u}, + {0x05u, 0x08u}, + {0x06u, 0x82u}, {0x09u, 0x80u}, {0x0Au, 0x98u}, - {0x0Cu, 0x40u}, - {0x0Du, 0x11u}, - {0x0Fu, 0x20u}, + {0x0Cu, 0x89u}, + {0x0Eu, 0x04u}, {0x11u, 0x01u}, {0x12u, 0x22u}, {0x13u, 0x20u}, - {0x14u, 0x80u}, - {0x15u, 0x04u}, + {0x16u, 0x10u}, {0x17u, 0x10u}, {0x19u, 0x80u}, {0x1Au, 0x08u}, {0x1Bu, 0x09u}, {0x1Eu, 0x01u}, - {0x20u, 0x09u}, + {0x20u, 0x01u}, {0x22u, 0x09u}, - {0x23u, 0x40u}, - {0x25u, 0x03u}, + {0x23u, 0x44u}, {0x26u, 0x04u}, - {0x28u, 0x02u}, {0x2Au, 0x20u}, - {0x2Bu, 0x02u}, - {0x2Cu, 0x82u}, - {0x30u, 0x28u}, - {0x32u, 0x10u}, + {0x2Fu, 0x04u}, + {0x30u, 0x20u}, {0x33u, 0x41u}, - {0x37u, 0x04u}, + {0x34u, 0x02u}, + {0x35u, 0x20u}, + {0x36u, 0x04u}, {0x38u, 0x80u}, {0x39u, 0x18u}, - {0x3Au, 0x08u}, - {0x3Du, 0x0Eu}, - {0x3Eu, 0x40u}, - {0x58u, 0x10u}, - {0x59u, 0x84u}, + {0x3Bu, 0x01u}, + {0x3Du, 0x28u}, + {0x59u, 0x94u}, {0x5Au, 0x02u}, - {0x5Eu, 0x80u}, + {0x5Cu, 0x80u}, {0x62u, 0x01u}, {0x63u, 0x02u}, - {0x67u, 0x01u}, - {0x84u, 0x12u}, - {0x88u, 0x16u}, - {0x8Bu, 0x0Cu}, - {0x8Eu, 0x10u}, - {0x91u, 0x22u}, - {0x92u, 0x40u}, - {0x94u, 0x04u}, - {0x95u, 0x11u}, + {0x66u, 0x40u}, + {0x78u, 0x10u}, + {0x7Au, 0x08u}, + {0x80u, 0x02u}, + {0x87u, 0x04u}, + {0x8Au, 0x80u}, + {0x90u, 0x60u}, + {0x92u, 0x04u}, + {0x93u, 0x08u}, + {0x94u, 0x84u}, + {0x95u, 0x99u}, {0x96u, 0x81u}, - {0x97u, 0x01u}, - {0x98u, 0xC0u}, - {0x99u, 0x40u}, - {0x9Au, 0x14u}, - {0x9Bu, 0x14u}, + {0x98u, 0x81u}, + {0x99u, 0x28u}, + {0x9Au, 0x12u}, + {0x9Bu, 0x10u}, + {0x9Cu, 0x12u}, {0x9Du, 0x01u}, - {0x9Eu, 0x49u}, - {0x9Fu, 0x09u}, - {0xA0u, 0x80u}, - {0xA1u, 0x04u}, + {0x9Eu, 0xC1u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x8Cu}, + {0xA1u, 0x14u}, {0xA2u, 0x30u}, - {0xA3u, 0x70u}, - {0xA4u, 0x10u}, - {0xA5u, 0x83u}, - {0xA6u, 0x0Cu}, - {0xA7u, 0x06u}, - {0xA8u, 0x22u}, - {0xAAu, 0x40u}, - {0xABu, 0x08u}, - {0xB1u, 0x43u}, - {0xB2u, 0x80u}, - {0xB6u, 0x20u}, - {0xC0u, 0xEFu}, + {0xA3u, 0x40u}, + {0xA6u, 0x84u}, + {0xA7u, 0x14u}, + {0xA9u, 0x04u}, + {0xABu, 0x50u}, + {0xB2u, 0x08u}, + {0xB4u, 0x04u}, + {0xC0u, 0xFFu}, {0xC2u, 0xFFu}, - {0xC4u, 0x7Fu}, - {0xCAu, 0x94u}, - {0xCCu, 0x4Fu}, - {0xCEu, 0xDEu}, + {0xC4u, 0x6Fu}, + {0xCAu, 0x24u}, + {0xCCu, 0xEDu}, + {0xCEu, 0x6Fu}, {0xD6u, 0x1Fu}, {0xD8u, 0x19u}, - {0xE6u, 0x44u}, - {0xE8u, 0x04u}, - {0xEAu, 0x03u}, + {0xE0u, 0x02u}, + {0xE2u, 0x10u}, + {0xE6u, 0x49u}, + {0xEAu, 0x06u}, {0xEEu, 0x08u}, {0x01u, 0x01u}, {0x03u, 0x02u}, + {0x04u, 0x01u}, {0x05u, 0x02u}, {0x07u, 0x01u}, - {0x08u, 0x08u}, {0x09u, 0x02u}, - {0x0Au, 0x12u}, {0x0Bu, 0x01u}, - {0x0Cu, 0x1Au}, + {0x0Cu, 0x20u}, {0x0Du, 0x10u}, - {0x0Eu, 0x64u}, - {0x0Fu, 0x08u}, + {0x0Eu, 0x44u}, + {0x0Fu, 0x0Cu}, {0x11u, 0x02u}, {0x13u, 0x21u}, {0x14u, 0x10u}, @@ -1739,17 +1743,18 @@ void cyfitter_cfg(void) {0x18u, 0x80u}, {0x19u, 0x10u}, {0x1Bu, 0x08u}, - {0x1Cu, 0x20u}, - {0x1Eu, 0x44u}, - {0x20u, 0x40u}, - {0x21u, 0x10u}, - {0x22u, 0x20u}, - {0x23u, 0x0Cu}, - {0x24u, 0x01u}, + {0x1Cu, 0x40u}, + {0x1Eu, 0x20u}, + {0x20u, 0x1Au}, + {0x22u, 0x64u}, {0x25u, 0x10u}, {0x27u, 0x08u}, - {0x29u, 0x02u}, - {0x2Bu, 0x01u}, + {0x28u, 0x08u}, + {0x29u, 0x10u}, + {0x2Au, 0x12u}, + {0x2Bu, 0x08u}, + {0x2Du, 0x02u}, + {0x2Fu, 0x01u}, {0x30u, 0x80u}, {0x31u, 0x03u}, {0x32u, 0x01u}, @@ -1779,305 +1784,311 @@ void cyfitter_cfg(void) {0x96u, 0xFFu}, {0x98u, 0x05u}, {0x9Au, 0x0Au}, + {0x9Cu, 0x90u}, + {0x9Eu, 0x60u}, {0xA2u, 0xFFu}, {0xA4u, 0x30u}, {0xA6u, 0xC0u}, - {0xACu, 0x90u}, - {0xAEu, 0x60u}, - {0xB0u, 0xFFu}, - {0xBEu, 0x01u}, + {0xB6u, 0xFFu}, + {0xBEu, 0x40u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xDBu, 0x04u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x44u}, + {0x00u, 0x04u}, {0x01u, 0x10u}, - {0x03u, 0x82u}, - {0x04u, 0x60u}, - {0x08u, 0x01u}, - {0x0Au, 0x08u}, - {0x0Bu, 0x20u}, - {0x0Cu, 0x80u}, - {0x0Eu, 0x18u}, - {0x11u, 0x84u}, - {0x12u, 0x21u}, - {0x13u, 0x02u}, - {0x15u, 0x01u}, - {0x17u, 0x08u}, - {0x18u, 0x80u}, - {0x1Cu, 0x08u}, - {0x1Du, 0x04u}, + {0x03u, 0x83u}, + {0x04u, 0x08u}, + {0x05u, 0x40u}, + {0x09u, 0x40u}, + {0x0Au, 0x04u}, + {0x0Bu, 0xA0u}, + {0x0Eu, 0x19u}, + {0x10u, 0x80u}, + {0x11u, 0x04u}, + {0x12u, 0x10u}, + {0x14u, 0x08u}, + {0x17u, 0x01u}, + {0x1Au, 0x02u}, + {0x1Cu, 0x18u}, {0x1Eu, 0x40u}, {0x1Fu, 0x80u}, - {0x24u, 0x01u}, - {0x25u, 0x25u}, + {0x24u, 0x09u}, + {0x25u, 0x05u}, {0x26u, 0x08u}, - {0x27u, 0x0Cu}, - {0x2Cu, 0x60u}, - {0x2Fu, 0x04u}, + {0x27u, 0x04u}, + {0x2Cu, 0x28u}, + {0x2Du, 0x80u}, {0x34u, 0x02u}, {0x37u, 0x14u}, + {0x3Au, 0x40u}, + {0x3Bu, 0x40u}, {0x3Cu, 0x02u}, {0x3Du, 0x0Au}, {0x3Eu, 0x20u}, {0x3Fu, 0x40u}, - {0x44u, 0x40u}, - {0x46u, 0x40u}, - {0x59u, 0x80u}, + {0x5Au, 0x80u}, {0x62u, 0x40u}, - {0x64u, 0x08u}, - {0x66u, 0x06u}, - {0x67u, 0x02u}, + {0x66u, 0x86u}, + {0x67u, 0x04u}, + {0x6Cu, 0x01u}, {0x6Du, 0x95u}, - {0x74u, 0x80u}, - {0x75u, 0x21u}, - {0x76u, 0x10u}, - {0x82u, 0x02u}, - {0x88u, 0x08u}, - {0x89u, 0x20u}, - {0x8Bu, 0x40u}, + {0x6Eu, 0x01u}, + {0x75u, 0x55u}, + {0x80u, 0x04u}, + {0x84u, 0x48u}, + {0x86u, 0x02u}, + {0x89u, 0x40u}, + {0x8Cu, 0x10u}, {0x8Eu, 0x40u}, - {0x8Fu, 0x01u}, - {0x90u, 0x24u}, - {0x92u, 0x18u}, - {0x93u, 0x20u}, - {0x94u, 0x80u}, + {0x90u, 0x04u}, + {0x92u, 0x14u}, + {0x93u, 0xA0u}, + {0x94u, 0x02u}, {0x95u, 0x11u}, - {0x97u, 0x40u}, - {0x98u, 0x03u}, + {0x96u, 0x02u}, + {0x98u, 0x0Au}, + {0x99u, 0x80u}, {0x9Bu, 0x10u}, - {0x9Du, 0x25u}, - {0x9Eu, 0x11u}, - {0x9Fu, 0x06u}, + {0x9Du, 0x15u}, + {0x9Eu, 0x10u}, + {0x9Fu, 0x04u}, {0xA2u, 0x04u}, {0xA3u, 0x02u}, - {0xA4u, 0x05u}, - {0xA6u, 0x20u}, + {0xA4u, 0xC1u}, {0xA7u, 0x80u}, - {0xA8u, 0x40u}, - {0xA9u, 0x80u}, + {0xA9u, 0x04u}, {0xAAu, 0x40u}, - {0xB0u, 0x20u}, - {0xB2u, 0x04u}, - {0xB3u, 0x08u}, - {0xB6u, 0xC0u}, - {0xB7u, 0x20u}, - {0xC0u, 0xCFu}, - {0xC2u, 0xEEu}, - {0xC4u, 0x3Du}, - {0xCAu, 0xE0u}, + {0xB2u, 0x01u}, + {0xB6u, 0x80u}, + {0xB7u, 0x60u}, + {0xC0u, 0xAFu}, + {0xC2u, 0xEFu}, + {0xC4u, 0x5Cu}, + {0xCAu, 0x70u}, {0xCCu, 0xE0u}, {0xCEu, 0xF0u}, {0xD6u, 0x08u}, {0xD8u, 0xF8u}, - {0xE0u, 0xE0u}, - {0xE6u, 0xC0u}, - {0xEAu, 0xA2u}, - {0xECu, 0x20u}, - {0xEEu, 0x49u}, - {0xA8u, 0x21u}, + {0xE2u, 0x10u}, + {0xE6u, 0x60u}, + {0xE8u, 0x10u}, + {0xEAu, 0x22u}, + {0xEEu, 0x09u}, + {0x87u, 0x04u}, + {0x97u, 0x04u}, + {0xA8u, 0xA1u}, {0xAEu, 0x08u}, - {0xB2u, 0x20u}, - {0xB3u, 0x06u}, - {0xB5u, 0x80u}, - {0xB6u, 0x04u}, - {0xE8u, 0xA0u}, - {0xECu, 0x90u}, - {0xEEu, 0x02u}, + {0xB0u, 0x04u}, + {0xB2u, 0x80u}, + {0xB6u, 0x64u}, + {0xEAu, 0x20u}, + {0xECu, 0x70u}, {0x12u, 0x08u}, + {0x13u, 0x02u}, {0x16u, 0x80u}, {0x17u, 0x80u}, - {0x33u, 0x08u}, + {0x30u, 0x10u}, + {0x33u, 0x01u}, {0x35u, 0x01u}, - {0x36u, 0x80u}, + {0x36u, 0x20u}, + {0x38u, 0x08u}, {0x3Au, 0x80u}, - {0x3Bu, 0x01u}, - {0x3Fu, 0x18u}, + {0x3Cu, 0x02u}, + {0x3Fu, 0x10u}, {0x40u, 0x04u}, + {0x53u, 0x40u}, {0x59u, 0x08u}, - {0x5Au, 0x80u}, {0x5Eu, 0x02u}, {0x61u, 0x20u}, {0x65u, 0x20u}, - {0x81u, 0x08u}, - {0x83u, 0x01u}, + {0x6Bu, 0x03u}, {0x8Du, 0x20u}, - {0x8Eu, 0x01u}, - {0xC4u, 0xE0u}, - {0xCCu, 0xE0u}, + {0xC4u, 0xF0u}, + {0xCCu, 0xF0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, - {0xD4u, 0x80u}, + {0xD4u, 0x20u}, {0xD6u, 0xC0u}, {0xD8u, 0xC0u}, - {0xE2u, 0x80u}, - {0xE6u, 0x20u}, {0x33u, 0x11u}, {0x34u, 0x02u}, {0x37u, 0x80u}, {0x39u, 0x40u}, {0x51u, 0x08u}, {0x52u, 0x02u}, + {0x57u, 0x02u}, {0x5Du, 0x02u}, - {0x5Eu, 0x40u}, {0x82u, 0x02u}, - {0x83u, 0x08u}, + {0x84u, 0x02u}, {0x92u, 0x02u}, {0x94u, 0x04u}, - {0x96u, 0x80u}, + {0x97u, 0x80u}, {0x9Bu, 0x90u}, + {0x9Cu, 0x10u}, {0x9Du, 0x21u}, - {0xA6u, 0x80u}, - {0xA7u, 0x0Cu}, + {0xA4u, 0x01u}, + {0xA6u, 0x21u}, {0xAAu, 0x08u}, {0xABu, 0x10u}, {0xAEu, 0x01u}, {0xAFu, 0x10u}, + {0xB4u, 0x04u}, + {0xB5u, 0x08u}, {0xCCu, 0xF0u}, {0xCEu, 0x10u}, {0xD4u, 0xA0u}, {0xD6u, 0xA0u}, {0xE2u, 0x80u}, - {0xE6u, 0x80u}, + {0xE6u, 0x40u}, {0xEAu, 0x10u}, {0xEEu, 0x40u}, - {0x12u, 0x80u}, + {0x10u, 0x10u}, {0x33u, 0x80u}, {0x5Au, 0x02u}, - {0x89u, 0x08u}, {0x8Cu, 0x04u}, + {0x8Du, 0x08u}, + {0x8Eu, 0x01u}, {0x92u, 0x02u}, {0x94u, 0x04u}, - {0x96u, 0x80u}, - {0x9Cu, 0x02u}, + {0x95u, 0x40u}, + {0x97u, 0x80u}, + {0x9Cu, 0x10u}, {0x9Du, 0x23u}, {0x9Fu, 0x01u}, + {0xA4u, 0x01u}, {0xA5u, 0x08u}, - {0xA6u, 0x80u}, - {0xA7u, 0x04u}, - {0xA9u, 0x40u}, - {0xB6u, 0x40u}, + {0xA6u, 0x21u}, + {0xA7u, 0x02u}, {0xC4u, 0x10u}, {0xCCu, 0x10u}, {0xD6u, 0x40u}, - {0xEEu, 0x20u}, - {0x8Eu, 0x40u}, - {0x96u, 0x80u}, - {0x9Du, 0x01u}, + {0x8Bu, 0x40u}, + {0x97u, 0x80u}, + {0x9Du, 0x21u}, {0x9Fu, 0x01u}, - {0xA7u, 0x84u}, - {0xA8u, 0x02u}, + {0xA4u, 0x01u}, + {0xA6u, 0x20u}, + {0xA7u, 0x80u}, {0xA9u, 0x02u}, - {0xB1u, 0x20u}, - {0xEEu, 0xA0u}, - {0x08u, 0x02u}, - {0x09u, 0x20u}, - {0x0Du, 0x01u}, + {0xABu, 0x02u}, + {0xB5u, 0x40u}, + {0xEAu, 0x20u}, + {0xEEu, 0x20u}, + {0x09u, 0x80u}, + {0x0Bu, 0x40u}, + {0x0Fu, 0x20u}, {0x10u, 0x80u}, {0x17u, 0x08u}, - {0x51u, 0x10u}, - {0x54u, 0x40u}, - {0x5Bu, 0x80u}, + {0x51u, 0x02u}, + {0x53u, 0x10u}, + {0x57u, 0x08u}, {0x5Du, 0x80u}, {0xC2u, 0x0Eu}, {0xC4u, 0x0Cu}, {0xD4u, 0x07u}, {0xD6u, 0x04u}, - {0x03u, 0x88u}, + {0x00u, 0x20u}, + {0x01u, 0x08u}, {0x04u, 0x10u}, - {0x05u, 0x02u}, + {0x07u, 0x40u}, + {0x08u, 0x02u}, {0x0Au, 0x01u}, - {0x0Bu, 0x80u}, {0x0Cu, 0x22u}, {0x80u, 0x02u}, - {0x8Bu, 0x80u}, - {0x91u, 0x02u}, - {0x95u, 0x20u}, - {0x98u, 0x02u}, + {0x86u, 0x40u}, + {0x8Fu, 0x40u}, + {0x93u, 0x40u}, + {0x97u, 0x20u}, {0x9Bu, 0x08u}, {0x9Du, 0x80u}, - {0x9Fu, 0x80u}, - {0xA1u, 0x20u}, - {0xA4u, 0x40u}, + {0xA1u, 0x80u}, + {0xA3u, 0x10u}, + {0xA5u, 0x02u}, + {0xA7u, 0x08u}, {0xB0u, 0x80u}, {0xC0u, 0x0Fu}, {0xC2u, 0x0Fu}, - {0xE4u, 0x04u}, + {0xE2u, 0x08u}, {0xEEu, 0x01u}, - {0x88u, 0x40u}, + {0x87u, 0x08u}, + {0x88u, 0x10u}, {0x8Du, 0x80u}, - {0x90u, 0x10u}, - {0x91u, 0x02u}, - {0x93u, 0x80u}, - {0x95u, 0x20u}, - {0x97u, 0x02u}, + {0x93u, 0x40u}, + {0x97u, 0x20u}, {0x98u, 0x02u}, + {0x99u, 0x08u}, {0x9Bu, 0x08u}, {0x9Du, 0x80u}, - {0xA1u, 0x20u}, - {0xA3u, 0x80u}, - {0xA4u, 0x40u}, - {0xA8u, 0x20u}, - {0xABu, 0x09u}, - {0xADu, 0x02u}, + {0xA0u, 0x10u}, + {0xA1u, 0x80u}, + {0xA3u, 0x10u}, + {0xA5u, 0x02u}, + {0xA6u, 0x40u}, + {0xA7u, 0x08u}, + {0xA8u, 0x30u}, {0xB2u, 0x01u}, - {0xE4u, 0x06u}, + {0xE4u, 0x02u}, + {0xE6u, 0x01u}, {0xEEu, 0x01u}, {0x09u, 0x08u}, {0x0Bu, 0x02u}, - {0x0Fu, 0x22u}, - {0x85u, 0x10u}, - {0x88u, 0x02u}, - {0x91u, 0x02u}, - {0x95u, 0x20u}, - {0x97u, 0x02u}, - {0x98u, 0x02u}, - {0xA1u, 0x20u}, - {0xA7u, 0x10u}, - {0xABu, 0x98u}, - {0xAFu, 0x40u}, - {0xB4u, 0x10u}, + {0x0Eu, 0x80u}, + {0x0Fu, 0x02u}, + {0x81u, 0x02u}, + {0x83u, 0x10u}, + {0x87u, 0x10u}, + {0x97u, 0x22u}, + {0xA1u, 0x80u}, + {0xA3u, 0x10u}, + {0xA5u, 0x02u}, + {0xA6u, 0x40u}, + {0xA9u, 0x08u}, + {0xABu, 0x08u}, + {0xB3u, 0x40u}, + {0xB4u, 0x02u}, + {0xB7u, 0x01u}, {0xC2u, 0x0Fu}, - {0xE2u, 0x04u}, - {0xEAu, 0x08u}, - {0x83u, 0x04u}, + {0xEAu, 0x0Eu}, + {0x84u, 0x01u}, {0x8Du, 0x01u}, - {0x9Du, 0x01u}, - {0xA7u, 0x04u}, + {0x8Eu, 0x20u}, + {0x9Du, 0x21u}, + {0xA4u, 0x01u}, + {0xA6u, 0x20u}, {0xAFu, 0x81u}, - {0xE6u, 0x20u}, + {0xE6u, 0x10u}, {0xEAu, 0x40u}, {0xEEu, 0x10u}, - {0x05u, 0x02u}, + {0x07u, 0x10u}, {0x57u, 0x08u}, {0x5Bu, 0x20u}, - {0x81u, 0x02u}, + {0x83u, 0x10u}, {0x87u, 0x08u}, {0x8Bu, 0x20u}, + {0xB1u, 0x20u}, {0xC0u, 0x20u}, {0xD4u, 0xC0u}, - {0xE4u, 0x20u}, + {0xE0u, 0x20u}, {0xE6u, 0x40u}, - {0x91u, 0x02u}, {0x9Fu, 0x40u}, - {0xA1u, 0x20u}, + {0xA1u, 0x80u}, {0xABu, 0x40u}, {0xADu, 0x08u}, {0xAFu, 0x01u}, {0x03u, 0x40u}, {0x9Fu, 0x40u}, - {0xADu, 0x01u}, - {0xB5u, 0x20u}, + {0xB5u, 0x80u}, {0xC0u, 0x08u}, - {0xEEu, 0x02u}, + {0xEAu, 0x08u}, {0x10u, 0x03u}, {0x11u, 0x01u}, {0x1Au, 0x03u}, {0x1Bu, 0x01u}, {0x1Cu, 0x03u}, {0x1Du, 0x01u}, - {0x00u, 0xFDu}, + {0x00u, 0xFFu}, {0x01u, 0xBFu}, {0x02u, 0x2Au}, {0x10u, 0x95u}, @@ -2097,7 +2108,7 @@ void cyfitter_cfg(void) uint16 size; } CYPACKED_ATTR cfg_memcpy_t; - static const cfg_memset_t CYCODE cfg_memset_list [] = { + static const cfg_memset_t CYCODE cfg_memset_list[] = { /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, @@ -2109,11 +2120,11 @@ void cyfitter_cfg(void) /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { - 0x6Cu, 0x00u, 0x00u, 0x00u, 0x71u, 0xC0u, 0x82u, 0x04u, 0x00u, 0xC0u, 0x00u, 0x08u, 0x2Cu, 0xC0u, 0x40u, 0x01u, - 0xC0u, 0x90u, 0x2Fu, 0x40u, 0xA4u, 0x00u, 0x40u, 0x60u, 0x64u, 0x00u, 0x08u, 0xFFu, 0x6Cu, 0xC0u, 0x00u, 0x02u, - 0x00u, 0x7Fu, 0x00u, 0x80u, 0x91u, 0x80u, 0x4Eu, 0x00u, 0x40u, 0x1Fu, 0x2Cu, 0x20u, 0x08u, 0x00u, 0x10u, 0x9Fu, + 0x6Cu, 0xC0u, 0x00u, 0x01u, 0x91u, 0xC0u, 0x4Eu, 0x04u, 0x71u, 0xC0u, 0x82u, 0x08u, 0x2Cu, 0x00u, 0x40u, 0xFFu, + 0xC0u, 0x90u, 0x2Fu, 0x40u, 0xA4u, 0x00u, 0x40u, 0x60u, 0x64u, 0x80u, 0x08u, 0x00u, 0x6Cu, 0xC0u, 0x00u, 0x02u, + 0x08u, 0x7Fu, 0x10u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x1Fu, 0x2Cu, 0x20u, 0x00u, 0x00u, 0x00u, 0x9Fu, 0x31u, 0xFFu, 0xC0u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Bu, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, - 0x64u, 0x02u, 0x50u, 0x00u, 0x03u, 0x0Eu, 0xDBu, 0xCFu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x64u, 0x02u, 0x50u, 0x00u, 0x03u, 0xCEu, 0xDBu, 0xF0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h index 7252135..3a40dcb 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfitter_cfg.h * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: -* This file provides basic startup and mux configration settings +* This file provides basic startup and mux configuration settings * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 4d4b204..33a4bd8 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -1,8 +1,52 @@ +/******************************************************************************* +* File Name: cyfittergnu.inc +* +* PSoC Creator 4.1 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + .ifndef INCLUDED_CYFITTERGNU_INC .set INCLUDED_CYFITTERGNU_INC, 1 .include "cydevicegnu.inc" .include "cydevicegnu_trm.inc" +/* Debug_Timer_Interrupt */ +.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set Debug_Timer_Interrupt__INTC_MASK, 0x01 +.set Debug_Timer_Interrupt__INTC_NUMBER, 0 +.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7 +.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* Debug_Timer_TimerHW */ +.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0 +.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1 +.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0 +.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1 +.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2 +.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0 +.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1 +.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0 +.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1 +.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3 +.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01 +.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3 +.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01 +.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0 +.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1 +.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0 + /* LED1 */ .set LED1__0__INTTYPE, CYREG_PICU12_INTTYPE3 .set LED1__0__MASK, 0x08 @@ -36,472 +80,82 @@ .set LED1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ .set LED1__SLW, CYREG_PRT12_SLW -/* SD_CD */ -.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE6 -.set SD_CD__0__MASK, 0x40 -.set SD_CD__0__PC, CYREG_PRT3_PC6 -.set SD_CD__0__PORT, 3 -.set SD_CD__0__SHIFT, 6 -.set SD_CD__AG, CYREG_PRT3_AG -.set SD_CD__AMUX, CYREG_PRT3_AMUX -.set SD_CD__BIE, CYREG_PRT3_BIE -.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_CD__BYP, CYREG_PRT3_BYP -.set SD_CD__CTL, CYREG_PRT3_CTL -.set SD_CD__DM0, CYREG_PRT3_DM0 -.set SD_CD__DM1, CYREG_PRT3_DM1 -.set SD_CD__DM2, CYREG_PRT3_DM2 -.set SD_CD__DR, CYREG_PRT3_DR -.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_CD__MASK, 0x40 -.set SD_CD__PORT, 3 -.set SD_CD__PRT, CYREG_PRT3_PRT -.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_CD__PS, CYREG_PRT3_PS -.set SD_CD__SHIFT, 6 -.set SD_CD__SLW, CYREG_PRT3_SLW +/* SCSI_CLK */ +.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 +.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 +.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2 +.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07 +.set SCSI_CLK__INDEX, 0x01 +.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SCSI_CLK__PM_ACT_MSK, 0x02 +.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SCSI_CLK__PM_STBY_MSK, 0x02 -/* SD_CS */ -.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4 -.set SD_CS__0__MASK, 0x10 -.set SD_CS__0__PC, CYREG_PRT3_PC4 -.set SD_CS__0__PORT, 3 -.set SD_CS__0__SHIFT, 4 -.set SD_CS__AG, CYREG_PRT3_AG -.set SD_CS__AMUX, CYREG_PRT3_AMUX -.set SD_CS__BIE, CYREG_PRT3_BIE -.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_CS__BYP, CYREG_PRT3_BYP -.set SD_CS__CTL, CYREG_PRT3_CTL -.set SD_CS__DM0, CYREG_PRT3_DM0 -.set SD_CS__DM1, CYREG_PRT3_DM1 -.set SD_CS__DM2, CYREG_PRT3_DM2 -.set SD_CS__DR, CYREG_PRT3_DR -.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_CS__MASK, 0x10 -.set SD_CS__PORT, 3 -.set SD_CS__PRT, CYREG_PRT3_PRT -.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_CS__PS, CYREG_PRT3_PS -.set SD_CS__SHIFT, 4 -.set SD_CS__SLW, CYREG_PRT3_SLW +/* SCSI_CTL_PHASE */ +.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK -/* USBFS_arb_int */ -.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_arb_int__INTC_MASK, 0x400000 -.set USBFS_arb_int__INTC_NUMBER, 22 -.set USBFS_arb_int__INTC_PRIOR_NUM, 6 -.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 -.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* SCSI_Filtered */ +.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Filtered_sts_sts_reg__0__POS, 0 +.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 +.set SCSI_Filtered_sts_sts_reg__1__POS, 1 +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST +.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 +.set SCSI_Filtered_sts_sts_reg__2__POS, 2 +.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 +.set SCSI_Filtered_sts_sts_reg__3__POS, 3 +.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 +.set SCSI_Filtered_sts_sts_reg__4__POS, 4 +.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST -/* USBFS_bus_reset */ -.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_bus_reset__INTC_MASK, 0x800000 -.set USBFS_bus_reset__INTC_NUMBER, 23 -.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 -.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 -.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_Dm */ -.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7 -.set USBFS_Dm__0__MASK, 0x80 -.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 -.set USBFS_Dm__0__PORT, 15 -.set USBFS_Dm__0__SHIFT, 7 -.set USBFS_Dm__AG, CYREG_PRT15_AG -.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX -.set USBFS_Dm__BIE, CYREG_PRT15_BIE -.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK -.set USBFS_Dm__BYP, CYREG_PRT15_BYP -.set USBFS_Dm__CTL, CYREG_PRT15_CTL -.set USBFS_Dm__DM0, CYREG_PRT15_DM0 -.set USBFS_Dm__DM1, CYREG_PRT15_DM1 -.set USBFS_Dm__DM2, CYREG_PRT15_DM2 -.set USBFS_Dm__DR, CYREG_PRT15_DR -.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS -.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE -.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG -.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN -.set USBFS_Dm__MASK, 0x80 -.set USBFS_Dm__PORT, 15 -.set USBFS_Dm__PRT, CYREG_PRT15_PRT -.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL -.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN -.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 -.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 -.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 -.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 -.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT -.set USBFS_Dm__PS, CYREG_PRT15_PS -.set USBFS_Dm__SHIFT, 7 -.set USBFS_Dm__SLW, CYREG_PRT15_SLW - -/* USBFS_Dp */ -.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6 -.set USBFS_Dp__0__MASK, 0x40 -.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 -.set USBFS_Dp__0__PORT, 15 -.set USBFS_Dp__0__SHIFT, 6 -.set USBFS_Dp__AG, CYREG_PRT15_AG -.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX -.set USBFS_Dp__BIE, CYREG_PRT15_BIE -.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK -.set USBFS_Dp__BYP, CYREG_PRT15_BYP -.set USBFS_Dp__CTL, CYREG_PRT15_CTL -.set USBFS_Dp__DM0, CYREG_PRT15_DM0 -.set USBFS_Dp__DM1, CYREG_PRT15_DM1 -.set USBFS_Dp__DM2, CYREG_PRT15_DM2 -.set USBFS_Dp__DR, CYREG_PRT15_DR -.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS -.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT -.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE -.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG -.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN -.set USBFS_Dp__MASK, 0x40 -.set USBFS_Dp__PORT, 15 -.set USBFS_Dp__PRT, CYREG_PRT15_PRT -.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL -.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN -.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 -.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 -.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 -.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 -.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT -.set USBFS_Dp__PS, CYREG_PRT15_PS -.set USBFS_Dp__SHIFT, 6 -.set USBFS_Dp__SLW, CYREG_PRT15_SLW -.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 - -/* USBFS_dp_int */ -.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_dp_int__INTC_MASK, 0x1000 -.set USBFS_dp_int__INTC_NUMBER, 12 -.set USBFS_dp_int__INTC_PRIOR_NUM, 7 -.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 -.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_0 */ -.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_0__INTC_MASK, 0x1000000 -.set USBFS_ep_0__INTC_NUMBER, 24 -.set USBFS_ep_0__INTC_PRIOR_NUM, 7 -.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 -.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_1 */ -.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x80 -.set USBFS_ep_1__INTC_NUMBER, 7 -.set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 -.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_2 */ -.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x100 -.set USBFS_ep_2__INTC_NUMBER, 8 -.set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 -.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_3 */ -.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_3__INTC_MASK, 0x200 -.set USBFS_ep_3__INTC_NUMBER, 9 -.set USBFS_ep_3__INTC_PRIOR_NUM, 7 -.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 -.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_4 */ -.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_4__INTC_MASK, 0x400 -.set USBFS_ep_4__INTC_NUMBER, 10 -.set USBFS_ep_4__INTC_PRIOR_NUM, 7 -.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 -.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_sof_int */ -.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_sof_int__INTC_MASK, 0x200000 -.set USBFS_sof_int__INTC_NUMBER, 21 -.set USBFS_sof_int__INTC_PRIOR_NUM, 7 -.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 -.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_USB */ -.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG -.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG -.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN -.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR -.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG -.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN -.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR -.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG -.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN -.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR -.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG -.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN -.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR -.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG -.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN -.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR -.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG -.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN -.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR -.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG -.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN -.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR -.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG -.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN -.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR -.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN -.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR -.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR -.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA -.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB -.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA -.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB -.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR -.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA -.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB -.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA -.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB -.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR -.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA -.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB -.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA -.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB -.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR -.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA -.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB -.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA -.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB -.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR -.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA -.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB -.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA -.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB -.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR -.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA -.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB -.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA -.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB -.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR -.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA -.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB -.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA -.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB -.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR -.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA -.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB -.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA -.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB -.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE -.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT -.set USBFS_USB__CR0, CYREG_USB_CR0 -.set USBFS_USB__CR1, CYREG_USB_CR1 -.set USBFS_USB__CWA, CYREG_USB_CWA -.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB -.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES -.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB -.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG -.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE -.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE -.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT -.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR -.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 -.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 -.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 -.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 -.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 -.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 -.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 -.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 -.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE -.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 -.set USBFS_USB__PM_ACT_MSK, 0x01 -.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 -.set USBFS_USB__PM_STBY_MSK, 0x01 -.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN -.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR -.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 -.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 -.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 -.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 -.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 -.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 -.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 -.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 -.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 -.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 -.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 -.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 -.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 -.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 -.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 -.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 -.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 -.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 -.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 -.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 -.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 -.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 -.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 -.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 -.set USBFS_USB__SOF0, CYREG_USB_SOF0 -.set USBFS_USB__SOF1, CYREG_USB_SOF1 -.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN -.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 -.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 - -/* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST -.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 -.set SDCard_BSPIM_RxStsReg__4__POS, 4 -.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 -.set SDCard_BSPIM_RxStsReg__5__POS, 5 -.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 -.set SDCard_BSPIM_RxStsReg__6__POS, 6 -.set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK -.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB08_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB08_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 -.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 -.set SDCard_BSPIM_TxStsReg__0__POS, 0 -.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 -.set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST -.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 -.set SDCard_BSPIM_TxStsReg__2__POS, 2 -.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 -.set SDCard_BSPIM_TxStsReg__3__POS, 3 -.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 -.set SDCard_BSPIM_TxStsReg__4__POS, 4 -.set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST - -/* SD_SCK */ -.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2 -.set SD_SCK__0__MASK, 0x04 -.set SD_SCK__0__PC, CYREG_PRT3_PC2 -.set SD_SCK__0__PORT, 3 -.set SD_SCK__0__SHIFT, 2 -.set SD_SCK__AG, CYREG_PRT3_AG -.set SD_SCK__AMUX, CYREG_PRT3_AMUX -.set SD_SCK__BIE, CYREG_PRT3_BIE -.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_SCK__BYP, CYREG_PRT3_BYP -.set SD_SCK__CTL, CYREG_PRT3_CTL -.set SD_SCK__DM0, CYREG_PRT3_DM0 -.set SD_SCK__DM1, CYREG_PRT3_DM1 -.set SD_SCK__DM2, CYREG_PRT3_DM2 -.set SD_SCK__DR, CYREG_PRT3_DR -.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_SCK__MASK, 0x04 -.set SD_SCK__PORT, 3 -.set SD_SCK__PRT, CYREG_PRT3_PRT -.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_SCK__PS, CYREG_PRT3_PS -.set SD_SCK__SHIFT, 2 -.set SD_SCK__SLW, CYREG_PRT3_SLW +/* SCSI_Glitch_Ctl */ +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK /* SCSI_In */ .set SCSI_In__0__AG, CYREG_PRT2_AG @@ -784,8 +438,6 @@ .set SCSI_In__REQ__PS, CYREG_PRT5_PS .set SCSI_In__REQ__SHIFT, 2 .set SCSI_In__REQ__SLW, CYREG_PRT5_SLW - -/* SCSI_In_DBx */ .set SCSI_In_DBx__0__AG, CYREG_PRT12_AG .set SCSI_In_DBx__0__BIE, CYREG_PRT12_BIE .set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT12_BIT_MASK @@ -1233,152 +885,285 @@ .set SCSI_In_DBx__DB7__SHIFT, 1 .set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW -/* SD_DAT1 */ -.set SD_DAT1__0__INTTYPE, CYREG_PICU3_INTTYPE0 -.set SD_DAT1__0__MASK, 0x01 -.set SD_DAT1__0__PC, CYREG_PRT3_PC0 -.set SD_DAT1__0__PORT, 3 -.set SD_DAT1__0__SHIFT, 0 -.set SD_DAT1__AG, CYREG_PRT3_AG -.set SD_DAT1__AMUX, CYREG_PRT3_AMUX -.set SD_DAT1__BIE, CYREG_PRT3_BIE -.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_DAT1__BYP, CYREG_PRT3_BYP -.set SD_DAT1__CTL, CYREG_PRT3_CTL -.set SD_DAT1__DM0, CYREG_PRT3_DM0 -.set SD_DAT1__DM1, CYREG_PRT3_DM1 -.set SD_DAT1__DM2, CYREG_PRT3_DM2 -.set SD_DAT1__DR, CYREG_PRT3_DR -.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_DAT1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_DAT1__MASK, 0x01 -.set SD_DAT1__PORT, 3 -.set SD_DAT1__PRT, CYREG_PRT3_PRT -.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_DAT1__PS, CYREG_PRT3_PS -.set SD_DAT1__SHIFT, 0 -.set SD_DAT1__SLW, CYREG_PRT3_SLW - -/* SD_DAT2 */ -.set SD_DAT2__0__INTTYPE, CYREG_PICU3_INTTYPE5 -.set SD_DAT2__0__MASK, 0x20 -.set SD_DAT2__0__PC, CYREG_PRT3_PC5 -.set SD_DAT2__0__PORT, 3 -.set SD_DAT2__0__SHIFT, 5 -.set SD_DAT2__AG, CYREG_PRT3_AG -.set SD_DAT2__AMUX, CYREG_PRT3_AMUX -.set SD_DAT2__BIE, CYREG_PRT3_BIE -.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_DAT2__BYP, CYREG_PRT3_BYP -.set SD_DAT2__CTL, CYREG_PRT3_CTL -.set SD_DAT2__DM0, CYREG_PRT3_DM0 -.set SD_DAT2__DM1, CYREG_PRT3_DM1 -.set SD_DAT2__DM2, CYREG_PRT3_DM2 -.set SD_DAT2__DR, CYREG_PRT3_DR -.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_DAT2__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_DAT2__MASK, 0x20 -.set SD_DAT2__PORT, 3 -.set SD_DAT2__PRT, CYREG_PRT3_PRT -.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_DAT2__PS, CYREG_PRT3_PS -.set SD_DAT2__SHIFT, 5 -.set SD_DAT2__SLW, CYREG_PRT3_SLW - -/* SD_MISO */ -.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1 -.set SD_MISO__0__MASK, 0x02 -.set SD_MISO__0__PC, CYREG_PRT3_PC1 -.set SD_MISO__0__PORT, 3 -.set SD_MISO__0__SHIFT, 1 -.set SD_MISO__AG, CYREG_PRT3_AG -.set SD_MISO__AMUX, CYREG_PRT3_AMUX -.set SD_MISO__BIE, CYREG_PRT3_BIE -.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_MISO__BYP, CYREG_PRT3_BYP -.set SD_MISO__CTL, CYREG_PRT3_CTL -.set SD_MISO__DM0, CYREG_PRT3_DM0 -.set SD_MISO__DM1, CYREG_PRT3_DM1 -.set SD_MISO__DM2, CYREG_PRT3_DM2 -.set SD_MISO__DR, CYREG_PRT3_DR -.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_MISO__MASK, 0x02 -.set SD_MISO__PORT, 3 -.set SD_MISO__PRT, CYREG_PRT3_PRT -.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_MISO__PS, CYREG_PRT3_PS -.set SD_MISO__SHIFT, 1 -.set SD_MISO__SLW, CYREG_PRT3_SLW - -/* SD_MOSI */ -.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3 -.set SD_MOSI__0__MASK, 0x08 -.set SD_MOSI__0__PC, CYREG_PRT3_PC3 -.set SD_MOSI__0__PORT, 3 -.set SD_MOSI__0__SHIFT, 3 -.set SD_MOSI__AG, CYREG_PRT3_AG -.set SD_MOSI__AMUX, CYREG_PRT3_AMUX -.set SD_MOSI__BIE, CYREG_PRT3_BIE -.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_MOSI__BYP, CYREG_PRT3_BYP -.set SD_MOSI__CTL, CYREG_PRT3_CTL -.set SD_MOSI__DM0, CYREG_PRT3_DM0 -.set SD_MOSI__DM1, CYREG_PRT3_DM1 -.set SD_MOSI__DM2, CYREG_PRT3_DM2 -.set SD_MOSI__DR, CYREG_PRT3_DR -.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_MOSI__MASK, 0x08 -.set SD_MOSI__PORT, 3 -.set SD_MOSI__PRT, CYREG_PRT3_PRT -.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_MOSI__PS, CYREG_PRT3_PS -.set SD_MOSI__SHIFT, 3 -.set SD_MOSI__SLW, CYREG_PRT3_SLW - -/* SCSI_CLK */ -.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 -.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 -.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2 -.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07 -.set SCSI_CLK__INDEX, 0x01 -.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set SCSI_CLK__PM_ACT_MSK, 0x02 -.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set SCSI_CLK__PM_STBY_MSK, 0x02 +/* SCSI_Noise */ +.set SCSI_Noise__0__AG, CYREG_PRT12_AG +.set SCSI_Noise__0__BIE, CYREG_PRT12_BIE +.set SCSI_Noise__0__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_Noise__0__BYP, CYREG_PRT12_BYP +.set SCSI_Noise__0__DM0, CYREG_PRT12_DM0 +.set SCSI_Noise__0__DM1, CYREG_PRT12_DM1 +.set SCSI_Noise__0__DM2, CYREG_PRT12_DM2 +.set SCSI_Noise__0__DR, CYREG_PRT12_DR +.set SCSI_Noise__0__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_Noise__0__INTTYPE, CYREG_PICU12_INTTYPE5 +.set SCSI_Noise__0__MASK, 0x20 +.set SCSI_Noise__0__PC, CYREG_PRT12_PC5 +.set SCSI_Noise__0__PORT, 12 +.set SCSI_Noise__0__PRT, CYREG_PRT12_PRT +.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_Noise__0__PS, CYREG_PRT12_PS +.set SCSI_Noise__0__SHIFT, 5 +.set SCSI_Noise__0__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_Noise__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_Noise__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_Noise__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_Noise__0__SLW, CYREG_PRT12_SLW +.set SCSI_Noise__1__AG, CYREG_PRT6_AG +.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__1__DR, CYREG_PRT6_DR +.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__1__INTTYPE, CYREG_PICU6_INTTYPE4 +.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__1__MASK, 0x10 +.set SCSI_Noise__1__PC, CYREG_PRT6_PC4 +.set SCSI_Noise__1__PORT, 6 +.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__1__PS, CYREG_PRT6_PS +.set SCSI_Noise__1__SHIFT, 4 +.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__2__AG, CYREG_PRT5_AG +.set SCSI_Noise__2__AMUX, CYREG_PRT5_AMUX +.set SCSI_Noise__2__BIE, CYREG_PRT5_BIE +.set SCSI_Noise__2__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Noise__2__BYP, CYREG_PRT5_BYP +.set SCSI_Noise__2__CTL, CYREG_PRT5_CTL +.set SCSI_Noise__2__DM0, CYREG_PRT5_DM0 +.set SCSI_Noise__2__DM1, CYREG_PRT5_DM1 +.set SCSI_Noise__2__DM2, CYREG_PRT5_DM2 +.set SCSI_Noise__2__DR, CYREG_PRT5_DR +.set SCSI_Noise__2__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Noise__2__INTTYPE, CYREG_PICU5_INTTYPE0 +.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Noise__2__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Noise__2__MASK, 0x01 +.set SCSI_Noise__2__PC, CYREG_PRT5_PC0 +.set SCSI_Noise__2__PORT, 5 +.set SCSI_Noise__2__PRT, CYREG_PRT5_PRT +.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Noise__2__PS, CYREG_PRT5_PS +.set SCSI_Noise__2__SHIFT, 0 +.set SCSI_Noise__2__SLW, CYREG_PRT5_SLW +.set SCSI_Noise__3__AG, CYREG_PRT6_AG +.set SCSI_Noise__3__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__3__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__3__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__3__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__3__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__3__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__3__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__3__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__3__DR, CYREG_PRT6_DR +.set SCSI_Noise__3__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__3__INTTYPE, CYREG_PICU6_INTTYPE6 +.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__3__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__3__MASK, 0x40 +.set SCSI_Noise__3__PC, CYREG_PRT6_PC6 +.set SCSI_Noise__3__PORT, 6 +.set SCSI_Noise__3__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__3__PS, CYREG_PRT6_PS +.set SCSI_Noise__3__SHIFT, 6 +.set SCSI_Noise__3__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__4__AG, CYREG_PRT6_AG +.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__4__DR, CYREG_PRT6_DR +.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__4__INTTYPE, CYREG_PICU6_INTTYPE5 +.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__4__MASK, 0x20 +.set SCSI_Noise__4__PC, CYREG_PRT6_PC5 +.set SCSI_Noise__4__PORT, 6 +.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__4__PS, CYREG_PRT6_PS +.set SCSI_Noise__4__SHIFT, 5 +.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG +.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR +.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__ACK__INTTYPE, CYREG_PICU6_INTTYPE5 +.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__ACK__MASK, 0x20 +.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC5 +.set SCSI_Noise__ACK__PORT, 6 +.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS +.set SCSI_Noise__ACK__SHIFT, 5 +.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__ATN__AG, CYREG_PRT12_AG +.set SCSI_Noise__ATN__BIE, CYREG_PRT12_BIE +.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_Noise__ATN__BYP, CYREG_PRT12_BYP +.set SCSI_Noise__ATN__DM0, CYREG_PRT12_DM0 +.set SCSI_Noise__ATN__DM1, CYREG_PRT12_DM1 +.set SCSI_Noise__ATN__DM2, CYREG_PRT12_DM2 +.set SCSI_Noise__ATN__DR, CYREG_PRT12_DR +.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_Noise__ATN__INTTYPE, CYREG_PICU12_INTTYPE5 +.set SCSI_Noise__ATN__MASK, 0x20 +.set SCSI_Noise__ATN__PC, CYREG_PRT12_PC5 +.set SCSI_Noise__ATN__PORT, 12 +.set SCSI_Noise__ATN__PRT, CYREG_PRT12_PRT +.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_Noise__ATN__PS, CYREG_PRT12_PS +.set SCSI_Noise__ATN__SHIFT, 5 +.set SCSI_Noise__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_Noise__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_Noise__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_Noise__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_Noise__ATN__SLW, CYREG_PRT12_SLW +.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG +.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR +.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__BSY__INTTYPE, CYREG_PICU6_INTTYPE4 +.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__BSY__MASK, 0x10 +.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC4 +.set SCSI_Noise__BSY__PORT, 6 +.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS +.set SCSI_Noise__BSY__SHIFT, 4 +.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__RST__AG, CYREG_PRT6_AG +.set SCSI_Noise__RST__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__RST__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__RST__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__RST__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__RST__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__RST__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__RST__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__RST__DR, CYREG_PRT6_DR +.set SCSI_Noise__RST__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__RST__INTTYPE, CYREG_PICU6_INTTYPE6 +.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__RST__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__RST__MASK, 0x40 +.set SCSI_Noise__RST__PC, CYREG_PRT6_PC6 +.set SCSI_Noise__RST__PORT, 6 +.set SCSI_Noise__RST__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__RST__PS, CYREG_PRT6_PS +.set SCSI_Noise__RST__SHIFT, 6 +.set SCSI_Noise__RST__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__SEL__AG, CYREG_PRT5_AG +.set SCSI_Noise__SEL__AMUX, CYREG_PRT5_AMUX +.set SCSI_Noise__SEL__BIE, CYREG_PRT5_BIE +.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Noise__SEL__BYP, CYREG_PRT5_BYP +.set SCSI_Noise__SEL__CTL, CYREG_PRT5_CTL +.set SCSI_Noise__SEL__DM0, CYREG_PRT5_DM0 +.set SCSI_Noise__SEL__DM1, CYREG_PRT5_DM1 +.set SCSI_Noise__SEL__DM2, CYREG_PRT5_DM2 +.set SCSI_Noise__SEL__DR, CYREG_PRT5_DR +.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Noise__SEL__INTTYPE, CYREG_PICU5_INTTYPE0 +.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Noise__SEL__MASK, 0x01 +.set SCSI_Noise__SEL__PC, CYREG_PRT5_PC0 +.set SCSI_Noise__SEL__PORT, 5 +.set SCSI_Noise__SEL__PRT, CYREG_PRT5_PRT +.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Noise__SEL__PS, CYREG_PRT5_PS +.set SCSI_Noise__SEL__SHIFT, 0 +.set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW /* SCSI_Out */ .set SCSI_Out__0__AG, CYREG_PRT4_AG @@ -1941,8 +1726,6 @@ .set SCSI_Out__SEL__PS, CYREG_PRT0_PS .set SCSI_Out__SEL__SHIFT, 3 .set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW - -/* SCSI_Out_Bits */ .set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 @@ -1977,8 +1760,6 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL .set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL .set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB08_MSK - -/* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL @@ -1999,8 +1780,6 @@ .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL .set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL .set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK - -/* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG .set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX .set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE @@ -2450,6 +2229,370 @@ .set SCSI_Out_DBx__DB7__SHIFT, 4 .set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW +/* SCSI_Parity_Error */ +.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST + +/* SCSI_RST_ISR */ +.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RST_ISR__INTC_MASK, 0x02 +.set SCSI_RST_ISR__INTC_NUMBER, 1 +.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_RX_DMA */ +.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_RX_DMA__DRQ_NUMBER, 0 +.set SCSI_RX_DMA__NUMBEROF_TDS, 0 +.set SCSI_RX_DMA__PRIORITY, 2 +.set SCSI_RX_DMA__TERMIN_EN, 0 +.set SCSI_RX_DMA__TERMIN_SEL, 0 +.set SCSI_RX_DMA__TERMOUT0_EN, 1 +.set SCSI_RX_DMA__TERMOUT0_SEL, 0 +.set SCSI_RX_DMA__TERMOUT1_EN, 0 +.set SCSI_RX_DMA__TERMOUT1_SEL, 0 +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04 +.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_SEL_ISR__INTC_MASK, 0x08 +.set SCSI_SEL_ISR__INTC_NUMBER, 3 +.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_TX_DMA__DRQ_NUMBER, 1 +.set SCSI_TX_DMA__NUMBEROF_TDS, 0 +.set SCSI_TX_DMA__PRIORITY, 2 +.set SCSI_TX_DMA__TERMIN_EN, 0 +.set SCSI_TX_DMA__TERMIN_SEL, 0 +.set SCSI_TX_DMA__TERMOUT0_EN, 1 +.set SCSI_TX_DMA__TERMOUT0_SEL, 1 +.set SCSI_TX_DMA__TERMOUT1_EN, 0 +.set SCSI_TX_DMA__TERMOUT1_SEL, 0 +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 +.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SDCard_BSPIM */ +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST +.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_RxStsReg__4__POS, 4 +.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 +.set SDCard_BSPIM_RxStsReg__5__POS, 5 +.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 +.set SDCard_BSPIM_RxStsReg__6__POS, 6 +.set SDCard_BSPIM_RxStsReg__MASK, 0x70 +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK +.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB08_ST_CTL +.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB08_ST_CTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 +.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 +.set SDCard_BSPIM_TxStsReg__0__POS, 0 +.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 +.set SDCard_BSPIM_TxStsReg__1__POS, 1 +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 +.set SDCard_BSPIM_TxStsReg__2__POS, 2 +.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 +.set SDCard_BSPIM_TxStsReg__3__POS, 3 +.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_TxStsReg__4__POS, 4 +.set SDCard_BSPIM_TxStsReg__MASK, 0x1F +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST + +/* SD_CD */ +.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE6 +.set SD_CD__0__MASK, 0x40 +.set SD_CD__0__PC, CYREG_PRT3_PC6 +.set SD_CD__0__PORT, 3 +.set SD_CD__0__SHIFT, 6 +.set SD_CD__AG, CYREG_PRT3_AG +.set SD_CD__AMUX, CYREG_PRT3_AMUX +.set SD_CD__BIE, CYREG_PRT3_BIE +.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CD__BYP, CYREG_PRT3_BYP +.set SD_CD__CTL, CYREG_PRT3_CTL +.set SD_CD__DM0, CYREG_PRT3_DM0 +.set SD_CD__DM1, CYREG_PRT3_DM1 +.set SD_CD__DM2, CYREG_PRT3_DM2 +.set SD_CD__DR, CYREG_PRT3_DR +.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CD__MASK, 0x40 +.set SD_CD__PORT, 3 +.set SD_CD__PRT, CYREG_PRT3_PRT +.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CD__PS, CYREG_PRT3_PS +.set SD_CD__SHIFT, 6 +.set SD_CD__SLW, CYREG_PRT3_SLW + +/* SD_CS */ +.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4 +.set SD_CS__0__MASK, 0x10 +.set SD_CS__0__PC, CYREG_PRT3_PC4 +.set SD_CS__0__PORT, 3 +.set SD_CS__0__SHIFT, 4 +.set SD_CS__AG, CYREG_PRT3_AG +.set SD_CS__AMUX, CYREG_PRT3_AMUX +.set SD_CS__BIE, CYREG_PRT3_BIE +.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CS__BYP, CYREG_PRT3_BYP +.set SD_CS__CTL, CYREG_PRT3_CTL +.set SD_CS__DM0, CYREG_PRT3_DM0 +.set SD_CS__DM1, CYREG_PRT3_DM1 +.set SD_CS__DM2, CYREG_PRT3_DM2 +.set SD_CS__DR, CYREG_PRT3_DR +.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CS__MASK, 0x10 +.set SD_CS__PORT, 3 +.set SD_CS__PRT, CYREG_PRT3_PRT +.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CS__PS, CYREG_PRT3_PS +.set SD_CS__SHIFT, 4 +.set SD_CS__SLW, CYREG_PRT3_SLW + +/* SD_DAT1 */ +.set SD_DAT1__0__INTTYPE, CYREG_PICU3_INTTYPE0 +.set SD_DAT1__0__MASK, 0x01 +.set SD_DAT1__0__PC, CYREG_PRT3_PC0 +.set SD_DAT1__0__PORT, 3 +.set SD_DAT1__0__SHIFT, 0 +.set SD_DAT1__AG, CYREG_PRT3_AG +.set SD_DAT1__AMUX, CYREG_PRT3_AMUX +.set SD_DAT1__BIE, CYREG_PRT3_BIE +.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_DAT1__BYP, CYREG_PRT3_BYP +.set SD_DAT1__CTL, CYREG_PRT3_CTL +.set SD_DAT1__DM0, CYREG_PRT3_DM0 +.set SD_DAT1__DM1, CYREG_PRT3_DM1 +.set SD_DAT1__DM2, CYREG_PRT3_DM2 +.set SD_DAT1__DR, CYREG_PRT3_DR +.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_DAT1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_DAT1__MASK, 0x01 +.set SD_DAT1__PORT, 3 +.set SD_DAT1__PRT, CYREG_PRT3_PRT +.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_DAT1__PS, CYREG_PRT3_PS +.set SD_DAT1__SHIFT, 0 +.set SD_DAT1__SLW, CYREG_PRT3_SLW + +/* SD_DAT2 */ +.set SD_DAT2__0__INTTYPE, CYREG_PICU3_INTTYPE5 +.set SD_DAT2__0__MASK, 0x20 +.set SD_DAT2__0__PC, CYREG_PRT3_PC5 +.set SD_DAT2__0__PORT, 3 +.set SD_DAT2__0__SHIFT, 5 +.set SD_DAT2__AG, CYREG_PRT3_AG +.set SD_DAT2__AMUX, CYREG_PRT3_AMUX +.set SD_DAT2__BIE, CYREG_PRT3_BIE +.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_DAT2__BYP, CYREG_PRT3_BYP +.set SD_DAT2__CTL, CYREG_PRT3_CTL +.set SD_DAT2__DM0, CYREG_PRT3_DM0 +.set SD_DAT2__DM1, CYREG_PRT3_DM1 +.set SD_DAT2__DM2, CYREG_PRT3_DM2 +.set SD_DAT2__DR, CYREG_PRT3_DR +.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_DAT2__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_DAT2__MASK, 0x20 +.set SD_DAT2__PORT, 3 +.set SD_DAT2__PRT, CYREG_PRT3_PRT +.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_DAT2__PS, CYREG_PRT3_PS +.set SD_DAT2__SHIFT, 5 +.set SD_DAT2__SLW, CYREG_PRT3_SLW + +/* SD_Data_Clk */ +.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 +.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 +.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 +.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 +.set SD_Data_Clk__INDEX, 0x00 +.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SD_Data_Clk__PM_ACT_MSK, 0x01 +.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SD_Data_Clk__PM_STBY_MSK, 0x01 + +/* SD_MISO */ +.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1 +.set SD_MISO__0__MASK, 0x02 +.set SD_MISO__0__PC, CYREG_PRT3_PC1 +.set SD_MISO__0__PORT, 3 +.set SD_MISO__0__SHIFT, 1 +.set SD_MISO__AG, CYREG_PRT3_AG +.set SD_MISO__AMUX, CYREG_PRT3_AMUX +.set SD_MISO__BIE, CYREG_PRT3_BIE +.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MISO__BYP, CYREG_PRT3_BYP +.set SD_MISO__CTL, CYREG_PRT3_CTL +.set SD_MISO__DM0, CYREG_PRT3_DM0 +.set SD_MISO__DM1, CYREG_PRT3_DM1 +.set SD_MISO__DM2, CYREG_PRT3_DM2 +.set SD_MISO__DR, CYREG_PRT3_DR +.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MISO__MASK, 0x02 +.set SD_MISO__PORT, 3 +.set SD_MISO__PRT, CYREG_PRT3_PRT +.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MISO__PS, CYREG_PRT3_PS +.set SD_MISO__SHIFT, 1 +.set SD_MISO__SLW, CYREG_PRT3_SLW + +/* SD_MOSI */ +.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3 +.set SD_MOSI__0__MASK, 0x08 +.set SD_MOSI__0__PC, CYREG_PRT3_PC3 +.set SD_MOSI__0__PORT, 3 +.set SD_MOSI__0__SHIFT, 3 +.set SD_MOSI__AG, CYREG_PRT3_AG +.set SD_MOSI__AMUX, CYREG_PRT3_AMUX +.set SD_MOSI__BIE, CYREG_PRT3_BIE +.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MOSI__BYP, CYREG_PRT3_BYP +.set SD_MOSI__CTL, CYREG_PRT3_CTL +.set SD_MOSI__DM0, CYREG_PRT3_DM0 +.set SD_MOSI__DM1, CYREG_PRT3_DM1 +.set SD_MOSI__DM2, CYREG_PRT3_DM2 +.set SD_MOSI__DR, CYREG_PRT3_DR +.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MOSI__MASK, 0x08 +.set SD_MOSI__PORT, 3 +.set SD_MOSI__PRT, CYREG_PRT3_PRT +.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MOSI__PS, CYREG_PRT3_PS +.set SD_MOSI__SHIFT, 3 +.set SD_MOSI__SLW, CYREG_PRT3_SLW + /* SD_RX_DMA */ .set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_RX_DMA__DRQ_NUMBER, 2 @@ -2461,8 +2604,6 @@ .set SD_RX_DMA__TERMOUT0_SEL, 2 .set SD_RX_DMA__TERMOUT1_EN, 0 .set SD_RX_DMA__TERMOUT1_SEL, 0 - -/* SD_RX_DMA_COMPLETE */ .set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 .set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20 @@ -2472,6 +2613,40 @@ .set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* SD_SCK */ +.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2 +.set SD_SCK__0__MASK, 0x04 +.set SD_SCK__0__PC, CYREG_PRT3_PC2 +.set SD_SCK__0__PORT, 3 +.set SD_SCK__0__SHIFT, 2 +.set SD_SCK__AG, CYREG_PRT3_AG +.set SD_SCK__AMUX, CYREG_PRT3_AMUX +.set SD_SCK__BIE, CYREG_PRT3_BIE +.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_SCK__BYP, CYREG_PRT3_BYP +.set SD_SCK__CTL, CYREG_PRT3_CTL +.set SD_SCK__DM0, CYREG_PRT3_DM0 +.set SD_SCK__DM1, CYREG_PRT3_DM1 +.set SD_SCK__DM2, CYREG_PRT3_DM2 +.set SD_SCK__DR, CYREG_PRT3_DR +.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_SCK__MASK, 0x04 +.set SD_SCK__PORT, 3 +.set SD_SCK__PRT, CYREG_PRT3_PRT +.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_SCK__PS, CYREG_PRT3_PS +.set SD_SCK__SHIFT, 2 +.set SD_SCK__SLW, CYREG_PRT3_SLW + /* SD_TX_DMA */ .set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_TX_DMA__DRQ_NUMBER, 3 @@ -2483,8 +2658,6 @@ .set SD_TX_DMA__TERMOUT0_SEL, 3 .set SD_TX_DMA__TERMOUT1_EN, 0 .set SD_TX_DMA__TERMOUT1_SEL, 0 - -/* SD_TX_DMA_COMPLETE */ .set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 .set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40 @@ -2494,285 +2667,269 @@ .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -/* SCSI_Noise */ -.set SCSI_Noise__0__AG, CYREG_PRT12_AG -.set SCSI_Noise__0__BIE, CYREG_PRT12_BIE -.set SCSI_Noise__0__BIT_MASK, CYREG_PRT12_BIT_MASK -.set SCSI_Noise__0__BYP, CYREG_PRT12_BYP -.set SCSI_Noise__0__DM0, CYREG_PRT12_DM0 -.set SCSI_Noise__0__DM1, CYREG_PRT12_DM1 -.set SCSI_Noise__0__DM2, CYREG_PRT12_DM2 -.set SCSI_Noise__0__DR, CYREG_PRT12_DR -.set SCSI_Noise__0__INP_DIS, CYREG_PRT12_INP_DIS -.set SCSI_Noise__0__INTTYPE, CYREG_PICU12_INTTYPE5 -.set SCSI_Noise__0__MASK, 0x20 -.set SCSI_Noise__0__PC, CYREG_PRT12_PC5 -.set SCSI_Noise__0__PORT, 12 -.set SCSI_Noise__0__PRT, CYREG_PRT12_PRT -.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN -.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 -.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 -.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 -.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 -.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT -.set SCSI_Noise__0__PS, CYREG_PRT12_PS -.set SCSI_Noise__0__SHIFT, 5 -.set SCSI_Noise__0__SIO_CFG, CYREG_PRT12_SIO_CFG -.set SCSI_Noise__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF -.set SCSI_Noise__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN -.set SCSI_Noise__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ -.set SCSI_Noise__0__SLW, CYREG_PRT12_SLW -.set SCSI_Noise__1__AG, CYREG_PRT6_AG -.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__1__DR, CYREG_PRT6_DR -.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__1__INTTYPE, CYREG_PICU6_INTTYPE4 -.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__1__MASK, 0x10 -.set SCSI_Noise__1__PC, CYREG_PRT6_PC4 -.set SCSI_Noise__1__PORT, 6 -.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__1__PS, CYREG_PRT6_PS -.set SCSI_Noise__1__SHIFT, 4 -.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__2__AG, CYREG_PRT5_AG -.set SCSI_Noise__2__AMUX, CYREG_PRT5_AMUX -.set SCSI_Noise__2__BIE, CYREG_PRT5_BIE -.set SCSI_Noise__2__BIT_MASK, CYREG_PRT5_BIT_MASK -.set SCSI_Noise__2__BYP, CYREG_PRT5_BYP -.set SCSI_Noise__2__CTL, CYREG_PRT5_CTL -.set SCSI_Noise__2__DM0, CYREG_PRT5_DM0 -.set SCSI_Noise__2__DM1, CYREG_PRT5_DM1 -.set SCSI_Noise__2__DM2, CYREG_PRT5_DM2 -.set SCSI_Noise__2__DR, CYREG_PRT5_DR -.set SCSI_Noise__2__INP_DIS, CYREG_PRT5_INP_DIS -.set SCSI_Noise__2__INTTYPE, CYREG_PICU5_INTTYPE0 -.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG -.set SCSI_Noise__2__LCD_EN, CYREG_PRT5_LCD_EN -.set SCSI_Noise__2__MASK, 0x01 -.set SCSI_Noise__2__PC, CYREG_PRT5_PC0 -.set SCSI_Noise__2__PORT, 5 -.set SCSI_Noise__2__PRT, CYREG_PRT5_PRT -.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL -.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN -.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 -.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 -.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 -.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 -.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT -.set SCSI_Noise__2__PS, CYREG_PRT5_PS -.set SCSI_Noise__2__SHIFT, 0 -.set SCSI_Noise__2__SLW, CYREG_PRT5_SLW -.set SCSI_Noise__3__AG, CYREG_PRT6_AG -.set SCSI_Noise__3__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__3__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__3__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__3__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__3__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__3__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__3__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__3__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__3__DR, CYREG_PRT6_DR -.set SCSI_Noise__3__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__3__INTTYPE, CYREG_PICU6_INTTYPE6 -.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__3__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__3__MASK, 0x40 -.set SCSI_Noise__3__PC, CYREG_PRT6_PC6 -.set SCSI_Noise__3__PORT, 6 -.set SCSI_Noise__3__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__3__PS, CYREG_PRT6_PS -.set SCSI_Noise__3__SHIFT, 6 -.set SCSI_Noise__3__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__4__AG, CYREG_PRT6_AG -.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__4__DR, CYREG_PRT6_DR -.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__4__INTTYPE, CYREG_PICU6_INTTYPE5 -.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__4__MASK, 0x20 -.set SCSI_Noise__4__PC, CYREG_PRT6_PC5 -.set SCSI_Noise__4__PORT, 6 -.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__4__PS, CYREG_PRT6_PS -.set SCSI_Noise__4__SHIFT, 5 -.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG -.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR -.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__ACK__INTTYPE, CYREG_PICU6_INTTYPE5 -.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__ACK__MASK, 0x20 -.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC5 -.set SCSI_Noise__ACK__PORT, 6 -.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS -.set SCSI_Noise__ACK__SHIFT, 5 -.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__ATN__AG, CYREG_PRT12_AG -.set SCSI_Noise__ATN__BIE, CYREG_PRT12_BIE -.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK -.set SCSI_Noise__ATN__BYP, CYREG_PRT12_BYP -.set SCSI_Noise__ATN__DM0, CYREG_PRT12_DM0 -.set SCSI_Noise__ATN__DM1, CYREG_PRT12_DM1 -.set SCSI_Noise__ATN__DM2, CYREG_PRT12_DM2 -.set SCSI_Noise__ATN__DR, CYREG_PRT12_DR -.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT12_INP_DIS -.set SCSI_Noise__ATN__INTTYPE, CYREG_PICU12_INTTYPE5 -.set SCSI_Noise__ATN__MASK, 0x20 -.set SCSI_Noise__ATN__PC, CYREG_PRT12_PC5 -.set SCSI_Noise__ATN__PORT, 12 -.set SCSI_Noise__ATN__PRT, CYREG_PRT12_PRT -.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN -.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 -.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 -.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 -.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 -.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT -.set SCSI_Noise__ATN__PS, CYREG_PRT12_PS -.set SCSI_Noise__ATN__SHIFT, 5 -.set SCSI_Noise__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG -.set SCSI_Noise__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF -.set SCSI_Noise__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN -.set SCSI_Noise__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ -.set SCSI_Noise__ATN__SLW, CYREG_PRT12_SLW -.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG -.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR -.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__BSY__INTTYPE, CYREG_PICU6_INTTYPE4 -.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__BSY__MASK, 0x10 -.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC4 -.set SCSI_Noise__BSY__PORT, 6 -.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS -.set SCSI_Noise__BSY__SHIFT, 4 -.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__RST__AG, CYREG_PRT6_AG -.set SCSI_Noise__RST__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__RST__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__RST__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__RST__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__RST__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__RST__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__RST__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__RST__DR, CYREG_PRT6_DR -.set SCSI_Noise__RST__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__RST__INTTYPE, CYREG_PICU6_INTTYPE6 -.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__RST__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__RST__MASK, 0x40 -.set SCSI_Noise__RST__PC, CYREG_PRT6_PC6 -.set SCSI_Noise__RST__PORT, 6 -.set SCSI_Noise__RST__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__RST__PS, CYREG_PRT6_PS -.set SCSI_Noise__RST__SHIFT, 6 -.set SCSI_Noise__RST__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__SEL__AG, CYREG_PRT5_AG -.set SCSI_Noise__SEL__AMUX, CYREG_PRT5_AMUX -.set SCSI_Noise__SEL__BIE, CYREG_PRT5_BIE -.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK -.set SCSI_Noise__SEL__BYP, CYREG_PRT5_BYP -.set SCSI_Noise__SEL__CTL, CYREG_PRT5_CTL -.set SCSI_Noise__SEL__DM0, CYREG_PRT5_DM0 -.set SCSI_Noise__SEL__DM1, CYREG_PRT5_DM1 -.set SCSI_Noise__SEL__DM2, CYREG_PRT5_DM2 -.set SCSI_Noise__SEL__DR, CYREG_PRT5_DR -.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT5_INP_DIS -.set SCSI_Noise__SEL__INTTYPE, CYREG_PICU5_INTTYPE0 -.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG -.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT5_LCD_EN -.set SCSI_Noise__SEL__MASK, 0x01 -.set SCSI_Noise__SEL__PC, CYREG_PRT5_PC0 -.set SCSI_Noise__SEL__PORT, 5 -.set SCSI_Noise__SEL__PRT, CYREG_PRT5_PRT -.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL -.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN -.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 -.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 -.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 -.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 -.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT -.set SCSI_Noise__SEL__PS, CYREG_PRT5_PS -.set SCSI_Noise__SEL__SHIFT, 0 -.set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW +/* USBFS */ +.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_arb_int__INTC_MASK, 0x400000 +.set USBFS_arb_int__INTC_NUMBER, 22 +.set USBFS_arb_int__INTC_PRIOR_NUM, 6 +.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 +.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_bus_reset__INTC_MASK, 0x800000 +.set USBFS_bus_reset__INTC_NUMBER, 23 +.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 +.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 +.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7 +.set USBFS_Dm__0__MASK, 0x80 +.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 +.set USBFS_Dm__0__PORT, 15 +.set USBFS_Dm__0__SHIFT, 7 +.set USBFS_Dm__AG, CYREG_PRT15_AG +.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dm__BIE, CYREG_PRT15_BIE +.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dm__BYP, CYREG_PRT15_BYP +.set USBFS_Dm__CTL, CYREG_PRT15_CTL +.set USBFS_Dm__DM0, CYREG_PRT15_DM0 +.set USBFS_Dm__DM1, CYREG_PRT15_DM1 +.set USBFS_Dm__DM2, CYREG_PRT15_DM2 +.set USBFS_Dm__DR, CYREG_PRT15_DR +.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dm__MASK, 0x80 +.set USBFS_Dm__PORT, 15 +.set USBFS_Dm__PRT, CYREG_PRT15_PRT +.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dm__PS, CYREG_PRT15_PS +.set USBFS_Dm__SHIFT, 7 +.set USBFS_Dm__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6 +.set USBFS_Dp__0__MASK, 0x40 +.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 +.set USBFS_Dp__0__PORT, 15 +.set USBFS_Dp__0__SHIFT, 6 +.set USBFS_Dp__AG, CYREG_PRT15_AG +.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dp__BIE, CYREG_PRT15_BIE +.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dp__BYP, CYREG_PRT15_BYP +.set USBFS_Dp__CTL, CYREG_PRT15_CTL +.set USBFS_Dp__DM0, CYREG_PRT15_DM0 +.set USBFS_Dp__DM1, CYREG_PRT15_DM1 +.set USBFS_Dp__DM2, CYREG_PRT15_DM2 +.set USBFS_Dp__DR, CYREG_PRT15_DR +.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT +.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dp__MASK, 0x40 +.set USBFS_Dp__PORT, 15 +.set USBFS_Dp__PRT, CYREG_PRT15_PRT +.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dp__PS, CYREG_PRT15_PS +.set USBFS_Dp__SHIFT, 6 +.set USBFS_Dp__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 +.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_dp_int__INTC_MASK, 0x1000 +.set USBFS_dp_int__INTC_NUMBER, 12 +.set USBFS_dp_int__INTC_PRIOR_NUM, 7 +.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 +.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_0__INTC_MASK, 0x1000000 +.set USBFS_ep_0__INTC_NUMBER, 24 +.set USBFS_ep_0__INTC_PRIOR_NUM, 7 +.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 +.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_1__INTC_MASK, 0x80 +.set USBFS_ep_1__INTC_NUMBER, 7 +.set USBFS_ep_1__INTC_PRIOR_NUM, 7 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 +.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_2__INTC_MASK, 0x100 +.set USBFS_ep_2__INTC_NUMBER, 8 +.set USBFS_ep_2__INTC_PRIOR_NUM, 7 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 +.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_3__INTC_MASK, 0x200 +.set USBFS_ep_3__INTC_NUMBER, 9 +.set USBFS_ep_3__INTC_PRIOR_NUM, 7 +.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 +.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_4__INTC_MASK, 0x400 +.set USBFS_ep_4__INTC_NUMBER, 10 +.set USBFS_ep_4__INTC_PRIOR_NUM, 7 +.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 +.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_sof_int__INTC_MASK, 0x200000 +.set USBFS_sof_int__INTC_NUMBER, 21 +.set USBFS_sof_int__INTC_PRIOR_NUM, 7 +.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 +.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG +.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG +.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN +.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR +.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG +.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN +.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR +.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG +.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN +.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR +.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG +.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN +.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR +.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG +.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN +.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR +.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG +.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN +.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR +.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG +.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN +.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR +.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG +.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN +.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR +.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN +.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR +.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR +.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA +.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB +.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA +.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB +.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR +.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA +.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB +.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA +.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB +.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR +.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA +.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB +.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA +.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB +.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR +.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA +.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB +.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA +.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB +.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR +.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA +.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB +.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA +.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB +.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR +.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA +.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB +.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA +.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB +.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR +.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA +.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB +.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA +.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB +.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR +.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA +.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB +.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA +.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB +.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE +.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT +.set USBFS_USB__CR0, CYREG_USB_CR0 +.set USBFS_USB__CR1, CYREG_USB_CR1 +.set USBFS_USB__CWA, CYREG_USB_CWA +.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB +.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES +.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB +.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG +.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE +.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE +.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT +.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR +.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 +.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 +.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 +.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 +.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 +.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 +.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 +.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 +.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE +.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 +.set USBFS_USB__PM_ACT_MSK, 0x01 +.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 +.set USBFS_USB__PM_STBY_MSK, 0x01 +.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN +.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR +.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 +.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 +.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 +.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 +.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 +.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 +.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 +.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 +.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 +.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 +.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 +.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 +.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 +.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 +.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 +.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 +.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 +.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 +.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 +.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 +.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 +.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 +.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 +.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 +.set USBFS_USB__SOF0, CYREG_USB_SOF0 +.set USBFS_USB__SOF1, CYREG_USB_SOF1 +.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN +.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 +.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 /* scsiTarget */ .set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0 @@ -2841,89 +2998,6 @@ .set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL .set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB07_ST -/* Debug_Timer_Interrupt */ -.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set Debug_Timer_Interrupt__INTC_MASK, 0x02 -.set Debug_Timer_Interrupt__INTC_NUMBER, 1 -.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7 -.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 -.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0 -.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1 -.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0 -.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1 -.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2 -.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0 -.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1 -.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0 -.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1 -.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3 -.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01 -.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3 -.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01 -.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0 -.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1 -.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0 - -/* SCSI_RX_DMA */ -.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_RX_DMA__DRQ_NUMBER, 0 -.set SCSI_RX_DMA__NUMBEROF_TDS, 0 -.set SCSI_RX_DMA__PRIORITY, 2 -.set SCSI_RX_DMA__TERMIN_EN, 0 -.set SCSI_RX_DMA__TERMIN_SEL, 0 -.set SCSI_RX_DMA__TERMOUT0_EN, 1 -.set SCSI_RX_DMA__TERMOUT0_SEL, 0 -.set SCSI_RX_DMA__TERMOUT1_EN, 0 -.set SCSI_RX_DMA__TERMOUT1_SEL, 0 - -/* SCSI_RX_DMA_COMPLETE */ -.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01 -.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0 -.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 -.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_TX_DMA__DRQ_NUMBER, 1 -.set SCSI_TX_DMA__NUMBEROF_TDS, 0 -.set SCSI_TX_DMA__PRIORITY, 2 -.set SCSI_TX_DMA__TERMIN_EN, 0 -.set SCSI_TX_DMA__TERMIN_SEL, 0 -.set SCSI_TX_DMA__TERMOUT0_EN, 1 -.set SCSI_TX_DMA__TERMOUT0_SEL, 1 -.set SCSI_TX_DMA__TERMOUT1_EN, 0 -.set SCSI_TX_DMA__TERMOUT1_SEL, 0 - -/* SCSI_TX_DMA_COMPLETE */ -.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 -.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 -.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SD_Data_Clk */ -.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 -.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 -.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 -.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 -.set SD_Data_Clk__INDEX, 0x00 -.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set SD_Data_Clk__PM_ACT_MSK, 0x01 -.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set SD_Data_Clk__PM_STBY_MSK, 0x01 - /* timer_clock */ .set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0 .set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1 @@ -2935,146 +3009,53 @@ .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2 .set timer_clock__PM_STBY_MSK, 0x04 -/* SCSI_RST_ISR */ -.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RST_ISR__INTC_MASK, 0x04 -.set SCSI_RST_ISR__INTC_NUMBER, 2 -.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 -.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_SEL_ISR__INTC_MASK, 0x08 -.set SCSI_SEL_ISR__INTC_NUMBER, 3 -.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 -.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_Filtered */ -.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 -.set SCSI_Filtered_sts_sts_reg__0__POS, 0 -.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 -.set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST -.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 -.set SCSI_Filtered_sts_sts_reg__2__POS, 2 -.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 -.set SCSI_Filtered_sts_sts_reg__3__POS, 3 -.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 -.set SCSI_Filtered_sts_sts_reg__4__POS, 4 -.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST - -/* SCSI_CTL_PHASE */ -.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK - -/* SCSI_Glitch_Ctl */ -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK - -/* SCSI_Parity_Error */ -.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST -.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST - /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 .set BCLK__BUS_CLK__KHZ, 50000 .set BCLK__BUS_CLK__MHZ, 50 .set CYDEV_CHIP_DIE_LEOPARD, 1 -.set CYDEV_CHIP_DIE_PSOC4A, 12 -.set CYDEV_CHIP_DIE_PSOC5LP, 19 -.set CYDEV_CHIP_DIE_PSOC5TM, 20 -.set CYDEV_CHIP_DIE_TMA4, 2 +.set CYDEV_CHIP_DIE_PSOC4A, 16 +.set CYDEV_CHIP_DIE_PSOC5LP, 2 +.set CYDEV_CHIP_DIE_PSOC5TM, 3 +.set CYDEV_CHIP_DIE_TMA4, 4 .set CYDEV_CHIP_DIE_UNKNOWN, 0 -.set CYDEV_CHIP_FAMILY_FM0P, 4 -.set CYDEV_CHIP_FAMILY_FM3, 5 -.set CYDEV_CHIP_FAMILY_FM4, 6 +.set CYDEV_CHIP_FAMILY_FM0P, 5 +.set CYDEV_CHIP_FAMILY_FM3, 6 +.set CYDEV_CHIP_FAMILY_FM4, 7 .set CYDEV_CHIP_FAMILY_PSOC3, 1 .set CYDEV_CHIP_FAMILY_PSOC4, 2 .set CYDEV_CHIP_FAMILY_PSOC5, 3 +.set CYDEV_CHIP_FAMILY_PSOC6, 4 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 .set CYDEV_CHIP_JTAG_ID, 0x2E133069 .set CYDEV_CHIP_MEMBER_3A, 1 -.set CYDEV_CHIP_MEMBER_4A, 12 -.set CYDEV_CHIP_MEMBER_4C, 18 -.set CYDEV_CHIP_MEMBER_4D, 8 -.set CYDEV_CHIP_MEMBER_4E, 4 -.set CYDEV_CHIP_MEMBER_4F, 13 -.set CYDEV_CHIP_MEMBER_4G, 2 -.set CYDEV_CHIP_MEMBER_4H, 11 -.set CYDEV_CHIP_MEMBER_4I, 17 -.set CYDEV_CHIP_MEMBER_4J, 9 -.set CYDEV_CHIP_MEMBER_4K, 10 -.set CYDEV_CHIP_MEMBER_4L, 16 -.set CYDEV_CHIP_MEMBER_4M, 15 -.set CYDEV_CHIP_MEMBER_4N, 6 -.set CYDEV_CHIP_MEMBER_4O, 5 -.set CYDEV_CHIP_MEMBER_4P, 14 -.set CYDEV_CHIP_MEMBER_4Q, 7 -.set CYDEV_CHIP_MEMBER_4U, 3 -.set CYDEV_CHIP_MEMBER_5A, 20 -.set CYDEV_CHIP_MEMBER_5B, 19 -.set CYDEV_CHIP_MEMBER_FM3, 24 -.set CYDEV_CHIP_MEMBER_FM4, 25 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 21 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 22 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 23 +.set CYDEV_CHIP_MEMBER_4A, 16 +.set CYDEV_CHIP_MEMBER_4D, 12 +.set CYDEV_CHIP_MEMBER_4E, 6 +.set CYDEV_CHIP_MEMBER_4F, 17 +.set CYDEV_CHIP_MEMBER_4G, 4 +.set CYDEV_CHIP_MEMBER_4H, 15 +.set CYDEV_CHIP_MEMBER_4I, 21 +.set CYDEV_CHIP_MEMBER_4J, 13 +.set CYDEV_CHIP_MEMBER_4K, 14 +.set CYDEV_CHIP_MEMBER_4L, 20 +.set CYDEV_CHIP_MEMBER_4M, 19 +.set CYDEV_CHIP_MEMBER_4N, 9 +.set CYDEV_CHIP_MEMBER_4O, 7 +.set CYDEV_CHIP_MEMBER_4P, 18 +.set CYDEV_CHIP_MEMBER_4Q, 11 +.set CYDEV_CHIP_MEMBER_4R, 8 +.set CYDEV_CHIP_MEMBER_4S, 10 +.set CYDEV_CHIP_MEMBER_4U, 5 +.set CYDEV_CHIP_MEMBER_5A, 3 +.set CYDEV_CHIP_MEMBER_5B, 2 +.set CYDEV_CHIP_MEMBER_6A, 22 +.set CYDEV_CHIP_MEMBER_FM3, 26 +.set CYDEV_CHIP_MEMBER_FM4, 27 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 23 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 24 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 25 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED @@ -3099,7 +3080,6 @@ .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 .set CYDEV_CHIP_REVISION_4A_ES0, 17 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 -.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0 @@ -3118,12 +3098,16 @@ .set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_5A_ES0, 0 .set CYDEV_CHIP_REVISION_5A_ES1, 1 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 .set CYDEV_CHIP_REVISION_5B_ES0, 0 .set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_6A_NO_UDB, 0 +.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0 @@ -3155,7 +3139,7 @@ .set CYDEV_ECC_ENABLE, 0 .set CYDEV_HEAP_SIZE, 0x0400 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 -.set CYDEV_INTR_RISING, 0x0000007E +.set CYDEV_INTR_RISING, 0x0000007F .set CYDEV_IS_EXPORTING_CODE, 0 .set CYDEV_IS_IMPORTING_CODE, 0 .set CYDEV_PROJ_TYPE, 2 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 1dae089..f222dd3 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -1,8 +1,51 @@ +; +; File Name: cyfitteriar.inc +; +; PSoC Creator 4.1 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + #ifndef INCLUDED_CYFITTERIAR_INC #define INCLUDED_CYFITTERIAR_INC INCLUDE cydeviceiar.inc INCLUDE cydeviceiar_trm.inc +/* Debug_Timer_Interrupt */ +Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x01 +Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* Debug_Timer_TimerHW */ +Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 +Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 +Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 +Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 +Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 +Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 +Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 + /* LED1 */ LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE3 LED1__0__MASK EQU 0x08 @@ -36,472 +79,82 @@ LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ LED1__SLW EQU CYREG_PRT12_SLW -/* SD_CD */ -SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6 -SD_CD__0__MASK EQU 0x40 -SD_CD__0__PC EQU CYREG_PRT3_PC6 -SD_CD__0__PORT EQU 3 -SD_CD__0__SHIFT EQU 6 -SD_CD__AG EQU CYREG_PRT3_AG -SD_CD__AMUX EQU CYREG_PRT3_AMUX -SD_CD__BIE EQU CYREG_PRT3_BIE -SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CD__BYP EQU CYREG_PRT3_BYP -SD_CD__CTL EQU CYREG_PRT3_CTL -SD_CD__DM0 EQU CYREG_PRT3_DM0 -SD_CD__DM1 EQU CYREG_PRT3_DM1 -SD_CD__DM2 EQU CYREG_PRT3_DM2 -SD_CD__DR EQU CYREG_PRT3_DR -SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CD__MASK EQU 0x40 -SD_CD__PORT EQU 3 -SD_CD__PRT EQU CYREG_PRT3_PRT -SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CD__PS EQU CYREG_PRT3_PS -SD_CD__SHIFT EQU 6 -SD_CD__SLW EQU CYREG_PRT3_SLW +/* SCSI_CLK */ +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 -/* SD_CS */ -SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 -SD_CS__0__MASK EQU 0x10 -SD_CS__0__PC EQU CYREG_PRT3_PC4 -SD_CS__0__PORT EQU 3 -SD_CS__0__SHIFT EQU 4 -SD_CS__AG EQU CYREG_PRT3_AG -SD_CS__AMUX EQU CYREG_PRT3_AMUX -SD_CS__BIE EQU CYREG_PRT3_BIE -SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CS__BYP EQU CYREG_PRT3_BYP -SD_CS__CTL EQU CYREG_PRT3_CTL -SD_CS__DM0 EQU CYREG_PRT3_DM0 -SD_CS__DM1 EQU CYREG_PRT3_DM1 -SD_CS__DM2 EQU CYREG_PRT3_DM2 -SD_CS__DR EQU CYREG_PRT3_DR -SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CS__MASK EQU 0x10 -SD_CS__PORT EQU 3 -SD_CS__PRT EQU CYREG_PRT3_PRT -SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CS__PS EQU CYREG_PRT3_PS -SD_CS__SHIFT EQU 4 -SD_CS__SLW EQU CYREG_PRT3_SLW +/* SCSI_CTL_PHASE */ +SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK -/* USBFS_arb_int */ -USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_arb_int__INTC_MASK EQU 0x400000 -USBFS_arb_int__INTC_NUMBER EQU 22 -USBFS_arb_int__INTC_PRIOR_NUM EQU 6 -USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 -USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* SCSI_Filtered */ +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST -/* USBFS_bus_reset */ -USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_bus_reset__INTC_MASK EQU 0x800000 -USBFS_bus_reset__INTC_NUMBER EQU 23 -USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 -USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 -USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_Dm */ -USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 -USBFS_Dm__0__MASK EQU 0x80 -USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 -USBFS_Dm__0__PORT EQU 15 -USBFS_Dm__0__SHIFT EQU 7 -USBFS_Dm__AG EQU CYREG_PRT15_AG -USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dm__BIE EQU CYREG_PRT15_BIE -USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dm__BYP EQU CYREG_PRT15_BYP -USBFS_Dm__CTL EQU CYREG_PRT15_CTL -USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dm__DR EQU CYREG_PRT15_DR -USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dm__MASK EQU 0x80 -USBFS_Dm__PORT EQU 15 -USBFS_Dm__PRT EQU CYREG_PRT15_PRT -USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dm__PS EQU CYREG_PRT15_PS -USBFS_Dm__SHIFT EQU 7 -USBFS_Dm__SLW EQU CYREG_PRT15_SLW - -/* USBFS_Dp */ -USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 -USBFS_Dp__0__MASK EQU 0x40 -USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 -USBFS_Dp__0__PORT EQU 15 -USBFS_Dp__0__SHIFT EQU 6 -USBFS_Dp__AG EQU CYREG_PRT15_AG -USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dp__BIE EQU CYREG_PRT15_BIE -USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dp__BYP EQU CYREG_PRT15_BYP -USBFS_Dp__CTL EQU CYREG_PRT15_CTL -USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dp__DR EQU CYREG_PRT15_DR -USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT -USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dp__MASK EQU 0x40 -USBFS_Dp__PORT EQU 15 -USBFS_Dp__PRT EQU CYREG_PRT15_PRT -USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dp__PS EQU CYREG_PRT15_PS -USBFS_Dp__SHIFT EQU 6 -USBFS_Dp__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 - -/* USBFS_dp_int */ -USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_dp_int__INTC_MASK EQU 0x1000 -USBFS_dp_int__INTC_NUMBER EQU 12 -USBFS_dp_int__INTC_PRIOR_NUM EQU 7 -USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 -USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_0 */ -USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_0__INTC_MASK EQU 0x1000000 -USBFS_ep_0__INTC_NUMBER EQU 24 -USBFS_ep_0__INTC_PRIOR_NUM EQU 7 -USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 -USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_1 */ -USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 -USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 -USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_2 */ -USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 -USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 -USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_3 */ -USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 -USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 -USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_4 */ -USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 -USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 -USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_sof_int */ -USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_sof_int__INTC_MASK EQU 0x200000 -USBFS_sof_int__INTC_NUMBER EQU 21 -USBFS_sof_int__INTC_PRIOR_NUM EQU 7 -USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 -USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_USB */ -USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG -USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG -USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN -USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR -USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG -USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN -USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR -USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG -USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN -USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR -USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG -USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN -USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR -USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG -USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN -USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR -USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG -USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN -USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR -USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG -USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN -USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR -USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG -USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN -USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR -USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN -USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR -USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR -USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA -USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB -USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA -USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB -USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR -USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA -USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB -USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA -USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB -USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR -USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA -USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB -USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA -USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB -USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR -USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA -USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB -USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA -USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB -USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR -USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA -USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB -USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA -USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB -USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR -USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA -USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB -USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA -USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB -USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR -USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA -USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB -USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA -USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB -USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR -USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA -USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB -USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA -USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB -USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE -USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT -USBFS_USB__CR0 EQU CYREG_USB_CR0 -USBFS_USB__CR1 EQU CYREG_USB_CR1 -USBFS_USB__CWA EQU CYREG_USB_CWA -USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB -USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES -USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB -USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG -USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE -USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE -USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT -USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR -USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 -USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 -USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 -USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 -USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 -USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 -USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 -USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 -USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE -USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 -USBFS_USB__PM_ACT_MSK EQU 0x01 -USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 -USBFS_USB__PM_STBY_MSK EQU 0x01 -USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN -USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR -USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 -USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 -USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 -USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 -USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 -USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 -USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 -USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 -USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 -USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 -USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 -USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 -USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 -USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 -USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 -USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 -USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 -USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 -USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 -USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 -USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 -USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 -USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 -USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 -USBFS_USB__SOF0 EQU CYREG_USB_SOF0 -USBFS_USB__SOF1 EQU CYREG_USB_SOF1 -USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 -USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 - -/* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST -SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_RxStsReg__4__POS EQU 4 -SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 -SDCard_BSPIM_RxStsReg__5__POS EQU 5 -SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 -SDCard_BSPIM_RxStsReg__6__POS EQU 6 -SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 -SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 -SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 -SDCard_BSPIM_TxStsReg__2__POS EQU 2 -SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 -SDCard_BSPIM_TxStsReg__3__POS EQU 3 -SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_TxStsReg__4__POS EQU 4 -SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST - -/* SD_SCK */ -SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 -SD_SCK__0__MASK EQU 0x04 -SD_SCK__0__PC EQU CYREG_PRT3_PC2 -SD_SCK__0__PORT EQU 3 -SD_SCK__0__SHIFT EQU 2 -SD_SCK__AG EQU CYREG_PRT3_AG -SD_SCK__AMUX EQU CYREG_PRT3_AMUX -SD_SCK__BIE EQU CYREG_PRT3_BIE -SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_SCK__BYP EQU CYREG_PRT3_BYP -SD_SCK__CTL EQU CYREG_PRT3_CTL -SD_SCK__DM0 EQU CYREG_PRT3_DM0 -SD_SCK__DM1 EQU CYREG_PRT3_DM1 -SD_SCK__DM2 EQU CYREG_PRT3_DM2 -SD_SCK__DR EQU CYREG_PRT3_DR -SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_SCK__MASK EQU 0x04 -SD_SCK__PORT EQU 3 -SD_SCK__PRT EQU CYREG_PRT3_PRT -SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_SCK__PS EQU CYREG_PRT3_PS -SD_SCK__SHIFT EQU 2 -SD_SCK__SLW EQU CYREG_PRT3_SLW +/* SCSI_Glitch_Ctl */ +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK /* SCSI_In */ SCSI_In__0__AG EQU CYREG_PRT2_AG @@ -784,8 +437,6 @@ SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT SCSI_In__REQ__PS EQU CYREG_PRT5_PS SCSI_In__REQ__SHIFT EQU 2 SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW - -/* SCSI_In_DBx */ SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK @@ -1233,152 +884,285 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_In_DBx__DB7__SHIFT EQU 1 SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW -/* SD_DAT1 */ -SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0 -SD_DAT1__0__MASK EQU 0x01 -SD_DAT1__0__PC EQU CYREG_PRT3_PC0 -SD_DAT1__0__PORT EQU 3 -SD_DAT1__0__SHIFT EQU 0 -SD_DAT1__AG EQU CYREG_PRT3_AG -SD_DAT1__AMUX EQU CYREG_PRT3_AMUX -SD_DAT1__BIE EQU CYREG_PRT3_BIE -SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_DAT1__BYP EQU CYREG_PRT3_BYP -SD_DAT1__CTL EQU CYREG_PRT3_CTL -SD_DAT1__DM0 EQU CYREG_PRT3_DM0 -SD_DAT1__DM1 EQU CYREG_PRT3_DM1 -SD_DAT1__DM2 EQU CYREG_PRT3_DM2 -SD_DAT1__DR EQU CYREG_PRT3_DR -SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_DAT1__MASK EQU 0x01 -SD_DAT1__PORT EQU 3 -SD_DAT1__PRT EQU CYREG_PRT3_PRT -SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_DAT1__PS EQU CYREG_PRT3_PS -SD_DAT1__SHIFT EQU 0 -SD_DAT1__SLW EQU CYREG_PRT3_SLW - -/* SD_DAT2 */ -SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 -SD_DAT2__0__MASK EQU 0x20 -SD_DAT2__0__PC EQU CYREG_PRT3_PC5 -SD_DAT2__0__PORT EQU 3 -SD_DAT2__0__SHIFT EQU 5 -SD_DAT2__AG EQU CYREG_PRT3_AG -SD_DAT2__AMUX EQU CYREG_PRT3_AMUX -SD_DAT2__BIE EQU CYREG_PRT3_BIE -SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_DAT2__BYP EQU CYREG_PRT3_BYP -SD_DAT2__CTL EQU CYREG_PRT3_CTL -SD_DAT2__DM0 EQU CYREG_PRT3_DM0 -SD_DAT2__DM1 EQU CYREG_PRT3_DM1 -SD_DAT2__DM2 EQU CYREG_PRT3_DM2 -SD_DAT2__DR EQU CYREG_PRT3_DR -SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_DAT2__MASK EQU 0x20 -SD_DAT2__PORT EQU 3 -SD_DAT2__PRT EQU CYREG_PRT3_PRT -SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_DAT2__PS EQU CYREG_PRT3_PS -SD_DAT2__SHIFT EQU 5 -SD_DAT2__SLW EQU CYREG_PRT3_SLW - -/* SD_MISO */ -SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 -SD_MISO__0__MASK EQU 0x02 -SD_MISO__0__PC EQU CYREG_PRT3_PC1 -SD_MISO__0__PORT EQU 3 -SD_MISO__0__SHIFT EQU 1 -SD_MISO__AG EQU CYREG_PRT3_AG -SD_MISO__AMUX EQU CYREG_PRT3_AMUX -SD_MISO__BIE EQU CYREG_PRT3_BIE -SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MISO__BYP EQU CYREG_PRT3_BYP -SD_MISO__CTL EQU CYREG_PRT3_CTL -SD_MISO__DM0 EQU CYREG_PRT3_DM0 -SD_MISO__DM1 EQU CYREG_PRT3_DM1 -SD_MISO__DM2 EQU CYREG_PRT3_DM2 -SD_MISO__DR EQU CYREG_PRT3_DR -SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MISO__MASK EQU 0x02 -SD_MISO__PORT EQU 3 -SD_MISO__PRT EQU CYREG_PRT3_PRT -SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MISO__PS EQU CYREG_PRT3_PS -SD_MISO__SHIFT EQU 1 -SD_MISO__SLW EQU CYREG_PRT3_SLW - -/* SD_MOSI */ -SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 -SD_MOSI__0__MASK EQU 0x08 -SD_MOSI__0__PC EQU CYREG_PRT3_PC3 -SD_MOSI__0__PORT EQU 3 -SD_MOSI__0__SHIFT EQU 3 -SD_MOSI__AG EQU CYREG_PRT3_AG -SD_MOSI__AMUX EQU CYREG_PRT3_AMUX -SD_MOSI__BIE EQU CYREG_PRT3_BIE -SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MOSI__BYP EQU CYREG_PRT3_BYP -SD_MOSI__CTL EQU CYREG_PRT3_CTL -SD_MOSI__DM0 EQU CYREG_PRT3_DM0 -SD_MOSI__DM1 EQU CYREG_PRT3_DM1 -SD_MOSI__DM2 EQU CYREG_PRT3_DM2 -SD_MOSI__DR EQU CYREG_PRT3_DR -SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MOSI__MASK EQU 0x08 -SD_MOSI__PORT EQU 3 -SD_MOSI__PRT EQU CYREG_PRT3_PRT -SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MOSI__PS EQU CYREG_PRT3_PS -SD_MOSI__SHIFT EQU 3 -SD_MOSI__SLW EQU CYREG_PRT3_SLW - -/* SCSI_CLK */ -SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 -SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 -SCSI_CLK__INDEX EQU 0x01 -SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SCSI_CLK__PM_ACT_MSK EQU 0x02 -SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SCSI_CLK__PM_STBY_MSK EQU 0x02 +/* SCSI_Noise */ +SCSI_Noise__0__AG EQU CYREG_PRT12_AG +SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP +SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT12_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Noise__0__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Noise__0__MASK EQU 0x20 +SCSI_Noise__0__PC EQU CYREG_PRT12_PC5 +SCSI_Noise__0__PORT EQU 12 +SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT12_PS +SCSI_Noise__0__SHIFT EQU 5 +SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW +SCSI_Noise__1__AG EQU CYREG_PRT6_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT6_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE4 +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__1__MASK EQU 0x10 +SCSI_Noise__1__PC EQU CYREG_PRT6_PC4 +SCSI_Noise__1__PORT EQU 6 +SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT6_PS +SCSI_Noise__1__SHIFT EQU 4 +SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__2__AG EQU CYREG_PRT5_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT5_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Noise__2__INTTYPE EQU CYREG_PICU5_INTTYPE0 +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Noise__2__MASK EQU 0x01 +SCSI_Noise__2__PC EQU CYREG_PRT5_PC0 +SCSI_Noise__2__PORT EQU 5 +SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT5_PS +SCSI_Noise__2__SHIFT EQU 0 +SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW +SCSI_Noise__3__AG EQU CYREG_PRT6_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT6_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__3__INTTYPE EQU CYREG_PICU6_INTTYPE6 +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__3__MASK EQU 0x40 +SCSI_Noise__3__PC EQU CYREG_PRT6_PC6 +SCSI_Noise__3__PORT EQU 6 +SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT6_PS +SCSI_Noise__3__SHIFT EQU 6 +SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__4__AG EQU CYREG_PRT6_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT6_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__4__MASK EQU 0x20 +SCSI_Noise__4__PC EQU CYREG_PRT6_PC5 +SCSI_Noise__4__PORT EQU 6 +SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT6_PS +SCSI_Noise__4__SHIFT EQU 5 +SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x20 +SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5 +SCSI_Noise__ACK__PORT EQU 6 +SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS +SCSI_Noise__ACK__SHIFT EQU 5 +SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG +SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP +SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Noise__ATN__MASK EQU 0x20 +SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5 +SCSI_Noise__ATN__PORT EQU 12 +SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS +SCSI_Noise__ATN__SHIFT EQU 5 +SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE4 +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x10 +SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4 +SCSI_Noise__BSY__PORT EQU 6 +SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS +SCSI_Noise__BSY__SHIFT EQU 4 +SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT6_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT6_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__RST__INTTYPE EQU CYREG_PICU6_INTTYPE6 +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__RST__MASK EQU 0x40 +SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6 +SCSI_Noise__RST__PORT EQU 6 +SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT6_PS +SCSI_Noise__RST__SHIFT EQU 6 +SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU5_INTTYPE0 +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x01 +SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0 +SCSI_Noise__SEL__PORT EQU 5 +SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS +SCSI_Noise__SEL__SHIFT EQU 0 +SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW /* SCSI_Out */ SCSI_Out__0__AG EQU CYREG_PRT4_AG @@ -1941,8 +1725,6 @@ SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT SCSI_Out__SEL__PS EQU CYREG_PRT0_PS SCSI_Out__SEL__SHIFT EQU 3 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW - -/* SCSI_Out_Bits */ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 @@ -1977,8 +1759,6 @@ SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK - -/* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL @@ -1999,8 +1779,6 @@ SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK - -/* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -2450,6 +2228,370 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS SCSI_Out_DBx__DB7__SHIFT EQU 4 SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW +/* SCSI_Parity_Error */ +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST + +/* SCSI_RST_ISR */ +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x02 +SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_RX_DMA */ +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SDCard_BSPIM */ +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST + +/* SD_CD */ +SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6 +SD_CD__0__MASK EQU 0x40 +SD_CD__0__PC EQU CYREG_PRT3_PC6 +SD_CD__0__PORT EQU 3 +SD_CD__0__SHIFT EQU 6 +SD_CD__AG EQU CYREG_PRT3_AG +SD_CD__AMUX EQU CYREG_PRT3_AMUX +SD_CD__BIE EQU CYREG_PRT3_BIE +SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CD__BYP EQU CYREG_PRT3_BYP +SD_CD__CTL EQU CYREG_PRT3_CTL +SD_CD__DM0 EQU CYREG_PRT3_DM0 +SD_CD__DM1 EQU CYREG_PRT3_DM1 +SD_CD__DM2 EQU CYREG_PRT3_DM2 +SD_CD__DR EQU CYREG_PRT3_DR +SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CD__MASK EQU 0x40 +SD_CD__PORT EQU 3 +SD_CD__PRT EQU CYREG_PRT3_PRT +SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CD__PS EQU CYREG_PRT3_PS +SD_CD__SHIFT EQU 6 +SD_CD__SLW EQU CYREG_PRT3_SLW + +/* SD_CS */ +SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SD_CS__0__MASK EQU 0x10 +SD_CS__0__PC EQU CYREG_PRT3_PC4 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 4 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x10 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 4 +SD_CS__SLW EQU CYREG_PRT3_SLW + +/* SD_DAT1 */ +SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0 +SD_DAT1__0__MASK EQU 0x01 +SD_DAT1__0__PC EQU CYREG_PRT3_PC0 +SD_DAT1__0__PORT EQU 3 +SD_DAT1__0__SHIFT EQU 0 +SD_DAT1__AG EQU CYREG_PRT3_AG +SD_DAT1__AMUX EQU CYREG_PRT3_AMUX +SD_DAT1__BIE EQU CYREG_PRT3_BIE +SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_DAT1__BYP EQU CYREG_PRT3_BYP +SD_DAT1__CTL EQU CYREG_PRT3_CTL +SD_DAT1__DM0 EQU CYREG_PRT3_DM0 +SD_DAT1__DM1 EQU CYREG_PRT3_DM1 +SD_DAT1__DM2 EQU CYREG_PRT3_DM2 +SD_DAT1__DR EQU CYREG_PRT3_DR +SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_DAT1__MASK EQU 0x01 +SD_DAT1__PORT EQU 3 +SD_DAT1__PRT EQU CYREG_PRT3_PRT +SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_DAT1__PS EQU CYREG_PRT3_PS +SD_DAT1__SHIFT EQU 0 +SD_DAT1__SLW EQU CYREG_PRT3_SLW + +/* SD_DAT2 */ +SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SD_DAT2__0__MASK EQU 0x20 +SD_DAT2__0__PC EQU CYREG_PRT3_PC5 +SD_DAT2__0__PORT EQU 3 +SD_DAT2__0__SHIFT EQU 5 +SD_DAT2__AG EQU CYREG_PRT3_AG +SD_DAT2__AMUX EQU CYREG_PRT3_AMUX +SD_DAT2__BIE EQU CYREG_PRT3_BIE +SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_DAT2__BYP EQU CYREG_PRT3_BYP +SD_DAT2__CTL EQU CYREG_PRT3_CTL +SD_DAT2__DM0 EQU CYREG_PRT3_DM0 +SD_DAT2__DM1 EQU CYREG_PRT3_DM1 +SD_DAT2__DM2 EQU CYREG_PRT3_DM2 +SD_DAT2__DR EQU CYREG_PRT3_DR +SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_DAT2__MASK EQU 0x20 +SD_DAT2__PORT EQU 3 +SD_DAT2__PRT EQU CYREG_PRT3_PRT +SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_DAT2__PS EQU CYREG_PRT3_PS +SD_DAT2__SHIFT EQU 5 +SD_DAT2__SLW EQU CYREG_PRT3_SLW + +/* SD_Data_Clk */ +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 + +/* SD_MISO */ +SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 +SD_MISO__0__MASK EQU 0x02 +SD_MISO__0__PC EQU CYREG_PRT3_PC1 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 1 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x02 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 1 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +/* SD_MOSI */ +SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_MOSI__0__MASK EQU 0x08 +SD_MOSI__0__PC EQU CYREG_PRT3_PC3 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 3 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x08 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 3 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + /* SD_RX_DMA */ SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 @@ -2461,8 +2603,6 @@ SD_RX_DMA__TERMOUT0_EN EQU 1 SD_RX_DMA__TERMOUT0_SEL EQU 2 SD_RX_DMA__TERMOUT1_EN EQU 0 SD_RX_DMA__TERMOUT1_SEL EQU 0 - -/* SD_RX_DMA_COMPLETE */ SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 @@ -2472,6 +2612,40 @@ SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* SD_SCK */ +SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_SCK__0__MASK EQU 0x04 +SD_SCK__0__PC EQU CYREG_PRT3_PC2 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 2 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x04 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 2 +SD_SCK__SLW EQU CYREG_PRT3_SLW + /* SD_TX_DMA */ SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_TX_DMA__DRQ_NUMBER EQU 3 @@ -2483,8 +2657,6 @@ SD_TX_DMA__TERMOUT0_EN EQU 1 SD_TX_DMA__TERMOUT0_SEL EQU 3 SD_TX_DMA__TERMOUT1_EN EQU 0 SD_TX_DMA__TERMOUT1_SEL EQU 0 - -/* SD_TX_DMA_COMPLETE */ SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 @@ -2494,285 +2666,269 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -/* SCSI_Noise */ -SCSI_Noise__0__AG EQU CYREG_PRT12_AG -SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE -SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK -SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP -SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0 -SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1 -SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2 -SCSI_Noise__0__DR EQU CYREG_PRT12_DR -SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS -SCSI_Noise__0__INTTYPE EQU CYREG_PICU12_INTTYPE5 -SCSI_Noise__0__MASK EQU 0x20 -SCSI_Noise__0__PC EQU CYREG_PRT12_PC5 -SCSI_Noise__0__PORT EQU 12 -SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT -SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN -SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 -SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 -SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 -SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 -SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT -SCSI_Noise__0__PS EQU CYREG_PRT12_PS -SCSI_Noise__0__SHIFT EQU 5 -SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG -SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF -SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN -SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ -SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW -SCSI_Noise__1__AG EQU CYREG_PRT6_AG -SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__1__DR EQU CYREG_PRT6_DR -SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE4 -SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__1__MASK EQU 0x10 -SCSI_Noise__1__PC EQU CYREG_PRT6_PC4 -SCSI_Noise__1__PORT EQU 6 -SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__1__PS EQU CYREG_PRT6_PS -SCSI_Noise__1__SHIFT EQU 4 -SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__2__AG EQU CYREG_PRT5_AG -SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX -SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE -SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP -SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL -SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0 -SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1 -SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2 -SCSI_Noise__2__DR EQU CYREG_PRT5_DR -SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_Noise__2__INTTYPE EQU CYREG_PICU5_INTTYPE0 -SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_Noise__2__MASK EQU 0x01 -SCSI_Noise__2__PC EQU CYREG_PRT5_PC0 -SCSI_Noise__2__PORT EQU 5 -SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT -SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_Noise__2__PS EQU CYREG_PRT5_PS -SCSI_Noise__2__SHIFT EQU 0 -SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW -SCSI_Noise__3__AG EQU CYREG_PRT6_AG -SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__3__DR EQU CYREG_PRT6_DR -SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__3__INTTYPE EQU CYREG_PICU6_INTTYPE6 -SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__3__MASK EQU 0x40 -SCSI_Noise__3__PC EQU CYREG_PRT6_PC6 -SCSI_Noise__3__PORT EQU 6 -SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__3__PS EQU CYREG_PRT6_PS -SCSI_Noise__3__SHIFT EQU 6 -SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__4__AG EQU CYREG_PRT6_AG -SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__4__DR EQU CYREG_PRT6_DR -SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE5 -SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__4__MASK EQU 0x20 -SCSI_Noise__4__PC EQU CYREG_PRT6_PC5 -SCSI_Noise__4__PORT EQU 6 -SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__4__PS EQU CYREG_PRT6_PS -SCSI_Noise__4__SHIFT EQU 5 -SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG -SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR -SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE5 -SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__ACK__MASK EQU 0x20 -SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5 -SCSI_Noise__ACK__PORT EQU 6 -SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS -SCSI_Noise__ACK__SHIFT EQU 5 -SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG -SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE -SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK -SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP -SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0 -SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1 -SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2 -SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR -SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS -SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU12_INTTYPE5 -SCSI_Noise__ATN__MASK EQU 0x20 -SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5 -SCSI_Noise__ATN__PORT EQU 12 -SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT -SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN -SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 -SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 -SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 -SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 -SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT -SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS -SCSI_Noise__ATN__SHIFT EQU 5 -SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG -SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF -SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN -SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ -SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW -SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG -SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR -SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE4 -SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__BSY__MASK EQU 0x10 -SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4 -SCSI_Noise__BSY__PORT EQU 6 -SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS -SCSI_Noise__BSY__SHIFT EQU 4 -SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__RST__AG EQU CYREG_PRT6_AG -SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__RST__DR EQU CYREG_PRT6_DR -SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__RST__INTTYPE EQU CYREG_PICU6_INTTYPE6 -SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__RST__MASK EQU 0x40 -SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6 -SCSI_Noise__RST__PORT EQU 6 -SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__RST__PS EQU CYREG_PRT6_PS -SCSI_Noise__RST__SHIFT EQU 6 -SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG -SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX -SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE -SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP -SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL -SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0 -SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1 -SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2 -SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR -SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU5_INTTYPE0 -SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_Noise__SEL__MASK EQU 0x01 -SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0 -SCSI_Noise__SEL__PORT EQU 5 -SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT -SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS -SCSI_Noise__SEL__SHIFT EQU 0 -SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW +/* USBFS */ +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 6 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_PRIOR_NUM EQU 7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_PRIOR_NUM EQU 7 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 /* scsiTarget */ scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 @@ -2841,89 +2997,6 @@ scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST -/* Debug_Timer_Interrupt */ -Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -Debug_Timer_Interrupt__INTC_MASK EQU 0x02 -Debug_Timer_Interrupt__INTC_NUMBER EQU 1 -Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 -Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 -Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 -Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 -Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 -Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 -Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 -Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 -Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 -Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 -Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 -Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 -Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 -Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 -Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 -Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 -Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 -Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 - -/* SCSI_RX_DMA */ -SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 -SCSI_RX_DMA__NUMBEROF_TDS EQU 0 -SCSI_RX_DMA__PRIORITY EQU 2 -SCSI_RX_DMA__TERMIN_EN EQU 0 -SCSI_RX_DMA__TERMIN_SEL EQU 0 -SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 -SCSI_RX_DMA__TERMOUT1_EN EQU 0 -SCSI_RX_DMA__TERMOUT1_SEL EQU 0 - -/* SCSI_RX_DMA_COMPLETE */ -SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 -SCSI_TX_DMA__NUMBEROF_TDS EQU 0 -SCSI_TX_DMA__PRIORITY EQU 2 -SCSI_TX_DMA__TERMIN_EN EQU 0 -SCSI_TX_DMA__TERMIN_SEL EQU 0 -SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 -SCSI_TX_DMA__TERMOUT1_EN EQU 0 -SCSI_TX_DMA__TERMOUT1_SEL EQU 0 - -/* SCSI_TX_DMA_COMPLETE */ -SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 -SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SD_Data_Clk */ -SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 -SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 -SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 -SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Data_Clk__INDEX EQU 0x00 -SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Data_Clk__PM_ACT_MSK EQU 0x01 -SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Data_Clk__PM_STBY_MSK EQU 0x01 - /* timer_clock */ timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 @@ -2935,146 +3008,53 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 -/* SCSI_RST_ISR */ -SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x04 -SCSI_RST_ISR__INTC_NUMBER EQU 2 -SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 -SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 -SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 -SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_Filtered */ -SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Filtered_sts_sts_reg__0__POS EQU 0 -SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 -SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST -SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 -SCSI_Filtered_sts_sts_reg__2__POS EQU 2 -SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 -SCSI_Filtered_sts_sts_reg__3__POS EQU 3 -SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 -SCSI_Filtered_sts_sts_reg__4__POS EQU 4 -SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST - -/* SCSI_CTL_PHASE */ -SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 -SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK - -/* SCSI_Glitch_Ctl */ -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK - -/* SCSI_Parity_Error */ -SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST -SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST - /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 12 -CYDEV_CHIP_DIE_PSOC5LP EQU 19 -CYDEV_CHIP_DIE_PSOC5TM EQU 20 -CYDEV_CHIP_DIE_TMA4 EQU 2 +CYDEV_CHIP_DIE_PSOC4A EQU 16 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 CYDEV_CHIP_DIE_UNKNOWN EQU 0 -CYDEV_CHIP_FAMILY_FM0P EQU 4 -CYDEV_CHIP_FAMILY_FM3 EQU 5 -CYDEV_CHIP_FAMILY_FM4 EQU 6 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 CYDEV_CHIP_FAMILY_PSOC3 EQU 1 CYDEV_CHIP_FAMILY_PSOC4 EQU 2 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 12 -CYDEV_CHIP_MEMBER_4C EQU 18 -CYDEV_CHIP_MEMBER_4D EQU 8 -CYDEV_CHIP_MEMBER_4E EQU 4 -CYDEV_CHIP_MEMBER_4F EQU 13 -CYDEV_CHIP_MEMBER_4G EQU 2 -CYDEV_CHIP_MEMBER_4H EQU 11 -CYDEV_CHIP_MEMBER_4I EQU 17 -CYDEV_CHIP_MEMBER_4J EQU 9 -CYDEV_CHIP_MEMBER_4K EQU 10 -CYDEV_CHIP_MEMBER_4L EQU 16 -CYDEV_CHIP_MEMBER_4M EQU 15 -CYDEV_CHIP_MEMBER_4N EQU 6 -CYDEV_CHIP_MEMBER_4O EQU 5 -CYDEV_CHIP_MEMBER_4P EQU 14 -CYDEV_CHIP_MEMBER_4Q EQU 7 -CYDEV_CHIP_MEMBER_4U EQU 3 -CYDEV_CHIP_MEMBER_5A EQU 20 -CYDEV_CHIP_MEMBER_5B EQU 19 -CYDEV_CHIP_MEMBER_FM3 EQU 24 -CYDEV_CHIP_MEMBER_FM4 EQU 25 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23 +CYDEV_CHIP_MEMBER_4A EQU 16 +CYDEV_CHIP_MEMBER_4D EQU 12 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 17 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 15 +CYDEV_CHIP_MEMBER_4I EQU 21 +CYDEV_CHIP_MEMBER_4J EQU 13 +CYDEV_CHIP_MEMBER_4K EQU 14 +CYDEV_CHIP_MEMBER_4L EQU 20 +CYDEV_CHIP_MEMBER_4M EQU 19 +CYDEV_CHIP_MEMBER_4N EQU 9 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 18 +CYDEV_CHIP_MEMBER_4Q EQU 11 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 10 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 22 +CYDEV_CHIP_MEMBER_FM3 EQU 26 +CYDEV_CHIP_MEMBER_FM4 EQU 27 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -3099,7 +3079,6 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 -CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 @@ -3118,12 +3097,16 @@ CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 @@ -3155,7 +3138,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000007E +CYDEV_INTR_RISING EQU 0x0000007F CYDEV_IS_EXPORTING_CODE EQU 0 CYDEV_IS_IMPORTING_CODE EQU 0 CYDEV_PROJ_TYPE EQU 2 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 05b0356..90a305e 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -1,8 +1,51 @@ +; +; File Name: cyfitterrv.inc +; +; PSoC Creator 4.1 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC INCLUDED_CYFITTERRV_INC EQU 1 GET cydevicerv.inc GET cydevicerv_trm.inc +; Debug_Timer_Interrupt +Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x01 +Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; Debug_Timer_TimerHW +Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 +Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 +Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 +Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 +Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 +Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 +Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 + ; LED1 LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE3 LED1__0__MASK EQU 0x08 @@ -36,472 +79,82 @@ LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ LED1__SLW EQU CYREG_PRT12_SLW -; SD_CD -SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6 -SD_CD__0__MASK EQU 0x40 -SD_CD__0__PC EQU CYREG_PRT3_PC6 -SD_CD__0__PORT EQU 3 -SD_CD__0__SHIFT EQU 6 -SD_CD__AG EQU CYREG_PRT3_AG -SD_CD__AMUX EQU CYREG_PRT3_AMUX -SD_CD__BIE EQU CYREG_PRT3_BIE -SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CD__BYP EQU CYREG_PRT3_BYP -SD_CD__CTL EQU CYREG_PRT3_CTL -SD_CD__DM0 EQU CYREG_PRT3_DM0 -SD_CD__DM1 EQU CYREG_PRT3_DM1 -SD_CD__DM2 EQU CYREG_PRT3_DM2 -SD_CD__DR EQU CYREG_PRT3_DR -SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CD__MASK EQU 0x40 -SD_CD__PORT EQU 3 -SD_CD__PRT EQU CYREG_PRT3_PRT -SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CD__PS EQU CYREG_PRT3_PS -SD_CD__SHIFT EQU 6 -SD_CD__SLW EQU CYREG_PRT3_SLW +; SCSI_CLK +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 -; SD_CS -SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 -SD_CS__0__MASK EQU 0x10 -SD_CS__0__PC EQU CYREG_PRT3_PC4 -SD_CS__0__PORT EQU 3 -SD_CS__0__SHIFT EQU 4 -SD_CS__AG EQU CYREG_PRT3_AG -SD_CS__AMUX EQU CYREG_PRT3_AMUX -SD_CS__BIE EQU CYREG_PRT3_BIE -SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CS__BYP EQU CYREG_PRT3_BYP -SD_CS__CTL EQU CYREG_PRT3_CTL -SD_CS__DM0 EQU CYREG_PRT3_DM0 -SD_CS__DM1 EQU CYREG_PRT3_DM1 -SD_CS__DM2 EQU CYREG_PRT3_DM2 -SD_CS__DR EQU CYREG_PRT3_DR -SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CS__MASK EQU 0x10 -SD_CS__PORT EQU 3 -SD_CS__PRT EQU CYREG_PRT3_PRT -SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CS__PS EQU CYREG_PRT3_PS -SD_CS__SHIFT EQU 4 -SD_CS__SLW EQU CYREG_PRT3_SLW +; SCSI_CTL_PHASE +SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK -; USBFS_arb_int -USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_arb_int__INTC_MASK EQU 0x400000 -USBFS_arb_int__INTC_NUMBER EQU 22 -USBFS_arb_int__INTC_PRIOR_NUM EQU 6 -USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 -USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; SCSI_Filtered +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST -; USBFS_bus_reset -USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_bus_reset__INTC_MASK EQU 0x800000 -USBFS_bus_reset__INTC_NUMBER EQU 23 -USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 -USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 -USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_Dm -USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 -USBFS_Dm__0__MASK EQU 0x80 -USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 -USBFS_Dm__0__PORT EQU 15 -USBFS_Dm__0__SHIFT EQU 7 -USBFS_Dm__AG EQU CYREG_PRT15_AG -USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dm__BIE EQU CYREG_PRT15_BIE -USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dm__BYP EQU CYREG_PRT15_BYP -USBFS_Dm__CTL EQU CYREG_PRT15_CTL -USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dm__DR EQU CYREG_PRT15_DR -USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dm__MASK EQU 0x80 -USBFS_Dm__PORT EQU 15 -USBFS_Dm__PRT EQU CYREG_PRT15_PRT -USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dm__PS EQU CYREG_PRT15_PS -USBFS_Dm__SHIFT EQU 7 -USBFS_Dm__SLW EQU CYREG_PRT15_SLW - -; USBFS_Dp -USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 -USBFS_Dp__0__MASK EQU 0x40 -USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 -USBFS_Dp__0__PORT EQU 15 -USBFS_Dp__0__SHIFT EQU 6 -USBFS_Dp__AG EQU CYREG_PRT15_AG -USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dp__BIE EQU CYREG_PRT15_BIE -USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dp__BYP EQU CYREG_PRT15_BYP -USBFS_Dp__CTL EQU CYREG_PRT15_CTL -USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dp__DR EQU CYREG_PRT15_DR -USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT -USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dp__MASK EQU 0x40 -USBFS_Dp__PORT EQU 15 -USBFS_Dp__PRT EQU CYREG_PRT15_PRT -USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dp__PS EQU CYREG_PRT15_PS -USBFS_Dp__SHIFT EQU 6 -USBFS_Dp__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 - -; USBFS_dp_int -USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_dp_int__INTC_MASK EQU 0x1000 -USBFS_dp_int__INTC_NUMBER EQU 12 -USBFS_dp_int__INTC_PRIOR_NUM EQU 7 -USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 -USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_0 -USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_0__INTC_MASK EQU 0x1000000 -USBFS_ep_0__INTC_NUMBER EQU 24 -USBFS_ep_0__INTC_PRIOR_NUM EQU 7 -USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 -USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_1 -USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 -USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 -USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_2 -USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 -USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 -USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_3 -USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 -USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 -USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_4 -USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 -USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 -USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_sof_int -USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_sof_int__INTC_MASK EQU 0x200000 -USBFS_sof_int__INTC_NUMBER EQU 21 -USBFS_sof_int__INTC_PRIOR_NUM EQU 7 -USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 -USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_USB -USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG -USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG -USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN -USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR -USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG -USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN -USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR -USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG -USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN -USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR -USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG -USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN -USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR -USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG -USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN -USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR -USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG -USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN -USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR -USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG -USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN -USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR -USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG -USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN -USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR -USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN -USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR -USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR -USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA -USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB -USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA -USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB -USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR -USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA -USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB -USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA -USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB -USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR -USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA -USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB -USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA -USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB -USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR -USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA -USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB -USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA -USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB -USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR -USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA -USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB -USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA -USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB -USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR -USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA -USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB -USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA -USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB -USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR -USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA -USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB -USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA -USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB -USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR -USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA -USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB -USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA -USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB -USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE -USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT -USBFS_USB__CR0 EQU CYREG_USB_CR0 -USBFS_USB__CR1 EQU CYREG_USB_CR1 -USBFS_USB__CWA EQU CYREG_USB_CWA -USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB -USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES -USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB -USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG -USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE -USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE -USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT -USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR -USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 -USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 -USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 -USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 -USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 -USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 -USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 -USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 -USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE -USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 -USBFS_USB__PM_ACT_MSK EQU 0x01 -USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 -USBFS_USB__PM_STBY_MSK EQU 0x01 -USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN -USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR -USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 -USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 -USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 -USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 -USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 -USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 -USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 -USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 -USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 -USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 -USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 -USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 -USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 -USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 -USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 -USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 -USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 -USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 -USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 -USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 -USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 -USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 -USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 -USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 -USBFS_USB__SOF0 EQU CYREG_USB_SOF0 -USBFS_USB__SOF1 EQU CYREG_USB_SOF1 -USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 -USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 - -; SDCard_BSPIM -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST -SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_RxStsReg__4__POS EQU 4 -SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 -SDCard_BSPIM_RxStsReg__5__POS EQU 5 -SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 -SDCard_BSPIM_RxStsReg__6__POS EQU 6 -SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 -SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 -SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 -SDCard_BSPIM_TxStsReg__2__POS EQU 2 -SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 -SDCard_BSPIM_TxStsReg__3__POS EQU 3 -SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_TxStsReg__4__POS EQU 4 -SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST - -; SD_SCK -SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 -SD_SCK__0__MASK EQU 0x04 -SD_SCK__0__PC EQU CYREG_PRT3_PC2 -SD_SCK__0__PORT EQU 3 -SD_SCK__0__SHIFT EQU 2 -SD_SCK__AG EQU CYREG_PRT3_AG -SD_SCK__AMUX EQU CYREG_PRT3_AMUX -SD_SCK__BIE EQU CYREG_PRT3_BIE -SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_SCK__BYP EQU CYREG_PRT3_BYP -SD_SCK__CTL EQU CYREG_PRT3_CTL -SD_SCK__DM0 EQU CYREG_PRT3_DM0 -SD_SCK__DM1 EQU CYREG_PRT3_DM1 -SD_SCK__DM2 EQU CYREG_PRT3_DM2 -SD_SCK__DR EQU CYREG_PRT3_DR -SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_SCK__MASK EQU 0x04 -SD_SCK__PORT EQU 3 -SD_SCK__PRT EQU CYREG_PRT3_PRT -SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_SCK__PS EQU CYREG_PRT3_PS -SD_SCK__SHIFT EQU 2 -SD_SCK__SLW EQU CYREG_PRT3_SLW +; SCSI_Glitch_Ctl +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK ; SCSI_In SCSI_In__0__AG EQU CYREG_PRT2_AG @@ -784,8 +437,6 @@ SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT SCSI_In__REQ__PS EQU CYREG_PRT5_PS SCSI_In__REQ__SHIFT EQU 2 SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW - -; SCSI_In_DBx SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK @@ -1233,152 +884,285 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_In_DBx__DB7__SHIFT EQU 1 SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW -; SD_DAT1 -SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0 -SD_DAT1__0__MASK EQU 0x01 -SD_DAT1__0__PC EQU CYREG_PRT3_PC0 -SD_DAT1__0__PORT EQU 3 -SD_DAT1__0__SHIFT EQU 0 -SD_DAT1__AG EQU CYREG_PRT3_AG -SD_DAT1__AMUX EQU CYREG_PRT3_AMUX -SD_DAT1__BIE EQU CYREG_PRT3_BIE -SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_DAT1__BYP EQU CYREG_PRT3_BYP -SD_DAT1__CTL EQU CYREG_PRT3_CTL -SD_DAT1__DM0 EQU CYREG_PRT3_DM0 -SD_DAT1__DM1 EQU CYREG_PRT3_DM1 -SD_DAT1__DM2 EQU CYREG_PRT3_DM2 -SD_DAT1__DR EQU CYREG_PRT3_DR -SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_DAT1__MASK EQU 0x01 -SD_DAT1__PORT EQU 3 -SD_DAT1__PRT EQU CYREG_PRT3_PRT -SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_DAT1__PS EQU CYREG_PRT3_PS -SD_DAT1__SHIFT EQU 0 -SD_DAT1__SLW EQU CYREG_PRT3_SLW - -; SD_DAT2 -SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 -SD_DAT2__0__MASK EQU 0x20 -SD_DAT2__0__PC EQU CYREG_PRT3_PC5 -SD_DAT2__0__PORT EQU 3 -SD_DAT2__0__SHIFT EQU 5 -SD_DAT2__AG EQU CYREG_PRT3_AG -SD_DAT2__AMUX EQU CYREG_PRT3_AMUX -SD_DAT2__BIE EQU CYREG_PRT3_BIE -SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_DAT2__BYP EQU CYREG_PRT3_BYP -SD_DAT2__CTL EQU CYREG_PRT3_CTL -SD_DAT2__DM0 EQU CYREG_PRT3_DM0 -SD_DAT2__DM1 EQU CYREG_PRT3_DM1 -SD_DAT2__DM2 EQU CYREG_PRT3_DM2 -SD_DAT2__DR EQU CYREG_PRT3_DR -SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_DAT2__MASK EQU 0x20 -SD_DAT2__PORT EQU 3 -SD_DAT2__PRT EQU CYREG_PRT3_PRT -SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_DAT2__PS EQU CYREG_PRT3_PS -SD_DAT2__SHIFT EQU 5 -SD_DAT2__SLW EQU CYREG_PRT3_SLW - -; SD_MISO -SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 -SD_MISO__0__MASK EQU 0x02 -SD_MISO__0__PC EQU CYREG_PRT3_PC1 -SD_MISO__0__PORT EQU 3 -SD_MISO__0__SHIFT EQU 1 -SD_MISO__AG EQU CYREG_PRT3_AG -SD_MISO__AMUX EQU CYREG_PRT3_AMUX -SD_MISO__BIE EQU CYREG_PRT3_BIE -SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MISO__BYP EQU CYREG_PRT3_BYP -SD_MISO__CTL EQU CYREG_PRT3_CTL -SD_MISO__DM0 EQU CYREG_PRT3_DM0 -SD_MISO__DM1 EQU CYREG_PRT3_DM1 -SD_MISO__DM2 EQU CYREG_PRT3_DM2 -SD_MISO__DR EQU CYREG_PRT3_DR -SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MISO__MASK EQU 0x02 -SD_MISO__PORT EQU 3 -SD_MISO__PRT EQU CYREG_PRT3_PRT -SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MISO__PS EQU CYREG_PRT3_PS -SD_MISO__SHIFT EQU 1 -SD_MISO__SLW EQU CYREG_PRT3_SLW - -; SD_MOSI -SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 -SD_MOSI__0__MASK EQU 0x08 -SD_MOSI__0__PC EQU CYREG_PRT3_PC3 -SD_MOSI__0__PORT EQU 3 -SD_MOSI__0__SHIFT EQU 3 -SD_MOSI__AG EQU CYREG_PRT3_AG -SD_MOSI__AMUX EQU CYREG_PRT3_AMUX -SD_MOSI__BIE EQU CYREG_PRT3_BIE -SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MOSI__BYP EQU CYREG_PRT3_BYP -SD_MOSI__CTL EQU CYREG_PRT3_CTL -SD_MOSI__DM0 EQU CYREG_PRT3_DM0 -SD_MOSI__DM1 EQU CYREG_PRT3_DM1 -SD_MOSI__DM2 EQU CYREG_PRT3_DM2 -SD_MOSI__DR EQU CYREG_PRT3_DR -SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MOSI__MASK EQU 0x08 -SD_MOSI__PORT EQU 3 -SD_MOSI__PRT EQU CYREG_PRT3_PRT -SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MOSI__PS EQU CYREG_PRT3_PS -SD_MOSI__SHIFT EQU 3 -SD_MOSI__SLW EQU CYREG_PRT3_SLW - -; SCSI_CLK -SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 -SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 -SCSI_CLK__INDEX EQU 0x01 -SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SCSI_CLK__PM_ACT_MSK EQU 0x02 -SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SCSI_CLK__PM_STBY_MSK EQU 0x02 +; SCSI_Noise +SCSI_Noise__0__AG EQU CYREG_PRT12_AG +SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP +SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT12_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Noise__0__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Noise__0__MASK EQU 0x20 +SCSI_Noise__0__PC EQU CYREG_PRT12_PC5 +SCSI_Noise__0__PORT EQU 12 +SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT12_PS +SCSI_Noise__0__SHIFT EQU 5 +SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW +SCSI_Noise__1__AG EQU CYREG_PRT6_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT6_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE4 +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__1__MASK EQU 0x10 +SCSI_Noise__1__PC EQU CYREG_PRT6_PC4 +SCSI_Noise__1__PORT EQU 6 +SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT6_PS +SCSI_Noise__1__SHIFT EQU 4 +SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__2__AG EQU CYREG_PRT5_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT5_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Noise__2__INTTYPE EQU CYREG_PICU5_INTTYPE0 +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Noise__2__MASK EQU 0x01 +SCSI_Noise__2__PC EQU CYREG_PRT5_PC0 +SCSI_Noise__2__PORT EQU 5 +SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT5_PS +SCSI_Noise__2__SHIFT EQU 0 +SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW +SCSI_Noise__3__AG EQU CYREG_PRT6_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT6_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__3__INTTYPE EQU CYREG_PICU6_INTTYPE6 +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__3__MASK EQU 0x40 +SCSI_Noise__3__PC EQU CYREG_PRT6_PC6 +SCSI_Noise__3__PORT EQU 6 +SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT6_PS +SCSI_Noise__3__SHIFT EQU 6 +SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__4__AG EQU CYREG_PRT6_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT6_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__4__MASK EQU 0x20 +SCSI_Noise__4__PC EQU CYREG_PRT6_PC5 +SCSI_Noise__4__PORT EQU 6 +SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT6_PS +SCSI_Noise__4__SHIFT EQU 5 +SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x20 +SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5 +SCSI_Noise__ACK__PORT EQU 6 +SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS +SCSI_Noise__ACK__SHIFT EQU 5 +SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG +SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP +SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Noise__ATN__MASK EQU 0x20 +SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5 +SCSI_Noise__ATN__PORT EQU 12 +SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS +SCSI_Noise__ATN__SHIFT EQU 5 +SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE4 +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x10 +SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4 +SCSI_Noise__BSY__PORT EQU 6 +SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS +SCSI_Noise__BSY__SHIFT EQU 4 +SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT6_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT6_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__RST__INTTYPE EQU CYREG_PICU6_INTTYPE6 +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__RST__MASK EQU 0x40 +SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6 +SCSI_Noise__RST__PORT EQU 6 +SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT6_PS +SCSI_Noise__RST__SHIFT EQU 6 +SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU5_INTTYPE0 +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x01 +SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0 +SCSI_Noise__SEL__PORT EQU 5 +SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS +SCSI_Noise__SEL__SHIFT EQU 0 +SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW ; SCSI_Out SCSI_Out__0__AG EQU CYREG_PRT4_AG @@ -1941,8 +1725,6 @@ SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT SCSI_Out__SEL__PS EQU CYREG_PRT0_PS SCSI_Out__SEL__SHIFT EQU 3 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW - -; SCSI_Out_Bits SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 @@ -1977,8 +1759,6 @@ SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK - -; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL @@ -1999,8 +1779,6 @@ SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK - -; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -2450,6 +2228,370 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS SCSI_Out_DBx__DB7__SHIFT EQU 4 SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW +; SCSI_Parity_Error +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST + +; SCSI_RST_ISR +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x02 +SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_RX_DMA +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_SEL_ISR +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_TX_DMA +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SDCard_BSPIM +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST + +; SD_CD +SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6 +SD_CD__0__MASK EQU 0x40 +SD_CD__0__PC EQU CYREG_PRT3_PC6 +SD_CD__0__PORT EQU 3 +SD_CD__0__SHIFT EQU 6 +SD_CD__AG EQU CYREG_PRT3_AG +SD_CD__AMUX EQU CYREG_PRT3_AMUX +SD_CD__BIE EQU CYREG_PRT3_BIE +SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CD__BYP EQU CYREG_PRT3_BYP +SD_CD__CTL EQU CYREG_PRT3_CTL +SD_CD__DM0 EQU CYREG_PRT3_DM0 +SD_CD__DM1 EQU CYREG_PRT3_DM1 +SD_CD__DM2 EQU CYREG_PRT3_DM2 +SD_CD__DR EQU CYREG_PRT3_DR +SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CD__MASK EQU 0x40 +SD_CD__PORT EQU 3 +SD_CD__PRT EQU CYREG_PRT3_PRT +SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CD__PS EQU CYREG_PRT3_PS +SD_CD__SHIFT EQU 6 +SD_CD__SLW EQU CYREG_PRT3_SLW + +; SD_CS +SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SD_CS__0__MASK EQU 0x10 +SD_CS__0__PC EQU CYREG_PRT3_PC4 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 4 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x10 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 4 +SD_CS__SLW EQU CYREG_PRT3_SLW + +; SD_DAT1 +SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0 +SD_DAT1__0__MASK EQU 0x01 +SD_DAT1__0__PC EQU CYREG_PRT3_PC0 +SD_DAT1__0__PORT EQU 3 +SD_DAT1__0__SHIFT EQU 0 +SD_DAT1__AG EQU CYREG_PRT3_AG +SD_DAT1__AMUX EQU CYREG_PRT3_AMUX +SD_DAT1__BIE EQU CYREG_PRT3_BIE +SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_DAT1__BYP EQU CYREG_PRT3_BYP +SD_DAT1__CTL EQU CYREG_PRT3_CTL +SD_DAT1__DM0 EQU CYREG_PRT3_DM0 +SD_DAT1__DM1 EQU CYREG_PRT3_DM1 +SD_DAT1__DM2 EQU CYREG_PRT3_DM2 +SD_DAT1__DR EQU CYREG_PRT3_DR +SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_DAT1__MASK EQU 0x01 +SD_DAT1__PORT EQU 3 +SD_DAT1__PRT EQU CYREG_PRT3_PRT +SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_DAT1__PS EQU CYREG_PRT3_PS +SD_DAT1__SHIFT EQU 0 +SD_DAT1__SLW EQU CYREG_PRT3_SLW + +; SD_DAT2 +SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SD_DAT2__0__MASK EQU 0x20 +SD_DAT2__0__PC EQU CYREG_PRT3_PC5 +SD_DAT2__0__PORT EQU 3 +SD_DAT2__0__SHIFT EQU 5 +SD_DAT2__AG EQU CYREG_PRT3_AG +SD_DAT2__AMUX EQU CYREG_PRT3_AMUX +SD_DAT2__BIE EQU CYREG_PRT3_BIE +SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_DAT2__BYP EQU CYREG_PRT3_BYP +SD_DAT2__CTL EQU CYREG_PRT3_CTL +SD_DAT2__DM0 EQU CYREG_PRT3_DM0 +SD_DAT2__DM1 EQU CYREG_PRT3_DM1 +SD_DAT2__DM2 EQU CYREG_PRT3_DM2 +SD_DAT2__DR EQU CYREG_PRT3_DR +SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_DAT2__MASK EQU 0x20 +SD_DAT2__PORT EQU 3 +SD_DAT2__PRT EQU CYREG_PRT3_PRT +SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_DAT2__PS EQU CYREG_PRT3_PS +SD_DAT2__SHIFT EQU 5 +SD_DAT2__SLW EQU CYREG_PRT3_SLW + +; SD_Data_Clk +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 + +; SD_MISO +SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 +SD_MISO__0__MASK EQU 0x02 +SD_MISO__0__PC EQU CYREG_PRT3_PC1 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 1 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x02 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 1 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +; SD_MOSI +SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_MOSI__0__MASK EQU 0x08 +SD_MOSI__0__PC EQU CYREG_PRT3_PC3 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 3 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x08 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 3 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + ; SD_RX_DMA SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 @@ -2461,8 +2603,6 @@ SD_RX_DMA__TERMOUT0_EN EQU 1 SD_RX_DMA__TERMOUT0_SEL EQU 2 SD_RX_DMA__TERMOUT1_EN EQU 0 SD_RX_DMA__TERMOUT1_SEL EQU 0 - -; SD_RX_DMA_COMPLETE SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 @@ -2472,6 +2612,40 @@ SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; SD_SCK +SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_SCK__0__MASK EQU 0x04 +SD_SCK__0__PC EQU CYREG_PRT3_PC2 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 2 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x04 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 2 +SD_SCK__SLW EQU CYREG_PRT3_SLW + ; SD_TX_DMA SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_TX_DMA__DRQ_NUMBER EQU 3 @@ -2483,8 +2657,6 @@ SD_TX_DMA__TERMOUT0_EN EQU 1 SD_TX_DMA__TERMOUT0_SEL EQU 3 SD_TX_DMA__TERMOUT1_EN EQU 0 SD_TX_DMA__TERMOUT1_SEL EQU 0 - -; SD_TX_DMA_COMPLETE SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 @@ -2494,285 +2666,269 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -; SCSI_Noise -SCSI_Noise__0__AG EQU CYREG_PRT12_AG -SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE -SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK -SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP -SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0 -SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1 -SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2 -SCSI_Noise__0__DR EQU CYREG_PRT12_DR -SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS -SCSI_Noise__0__INTTYPE EQU CYREG_PICU12_INTTYPE5 -SCSI_Noise__0__MASK EQU 0x20 -SCSI_Noise__0__PC EQU CYREG_PRT12_PC5 -SCSI_Noise__0__PORT EQU 12 -SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT -SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN -SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 -SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 -SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 -SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 -SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT -SCSI_Noise__0__PS EQU CYREG_PRT12_PS -SCSI_Noise__0__SHIFT EQU 5 -SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG -SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF -SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN -SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ -SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW -SCSI_Noise__1__AG EQU CYREG_PRT6_AG -SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__1__DR EQU CYREG_PRT6_DR -SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE4 -SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__1__MASK EQU 0x10 -SCSI_Noise__1__PC EQU CYREG_PRT6_PC4 -SCSI_Noise__1__PORT EQU 6 -SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__1__PS EQU CYREG_PRT6_PS -SCSI_Noise__1__SHIFT EQU 4 -SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__2__AG EQU CYREG_PRT5_AG -SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX -SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE -SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP -SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL -SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0 -SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1 -SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2 -SCSI_Noise__2__DR EQU CYREG_PRT5_DR -SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_Noise__2__INTTYPE EQU CYREG_PICU5_INTTYPE0 -SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_Noise__2__MASK EQU 0x01 -SCSI_Noise__2__PC EQU CYREG_PRT5_PC0 -SCSI_Noise__2__PORT EQU 5 -SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT -SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_Noise__2__PS EQU CYREG_PRT5_PS -SCSI_Noise__2__SHIFT EQU 0 -SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW -SCSI_Noise__3__AG EQU CYREG_PRT6_AG -SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__3__DR EQU CYREG_PRT6_DR -SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__3__INTTYPE EQU CYREG_PICU6_INTTYPE6 -SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__3__MASK EQU 0x40 -SCSI_Noise__3__PC EQU CYREG_PRT6_PC6 -SCSI_Noise__3__PORT EQU 6 -SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__3__PS EQU CYREG_PRT6_PS -SCSI_Noise__3__SHIFT EQU 6 -SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__4__AG EQU CYREG_PRT6_AG -SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__4__DR EQU CYREG_PRT6_DR -SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE5 -SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__4__MASK EQU 0x20 -SCSI_Noise__4__PC EQU CYREG_PRT6_PC5 -SCSI_Noise__4__PORT EQU 6 -SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__4__PS EQU CYREG_PRT6_PS -SCSI_Noise__4__SHIFT EQU 5 -SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG -SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR -SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE5 -SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__ACK__MASK EQU 0x20 -SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5 -SCSI_Noise__ACK__PORT EQU 6 -SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS -SCSI_Noise__ACK__SHIFT EQU 5 -SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG -SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE -SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK -SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP -SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0 -SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1 -SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2 -SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR -SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS -SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU12_INTTYPE5 -SCSI_Noise__ATN__MASK EQU 0x20 -SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5 -SCSI_Noise__ATN__PORT EQU 12 -SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT -SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN -SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 -SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 -SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 -SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 -SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT -SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS -SCSI_Noise__ATN__SHIFT EQU 5 -SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG -SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF -SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN -SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ -SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW -SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG -SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR -SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE4 -SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__BSY__MASK EQU 0x10 -SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4 -SCSI_Noise__BSY__PORT EQU 6 -SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS -SCSI_Noise__BSY__SHIFT EQU 4 -SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__RST__AG EQU CYREG_PRT6_AG -SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__RST__DR EQU CYREG_PRT6_DR -SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__RST__INTTYPE EQU CYREG_PICU6_INTTYPE6 -SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__RST__MASK EQU 0x40 -SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6 -SCSI_Noise__RST__PORT EQU 6 -SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__RST__PS EQU CYREG_PRT6_PS -SCSI_Noise__RST__SHIFT EQU 6 -SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG -SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX -SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE -SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP -SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL -SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0 -SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1 -SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2 -SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR -SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU5_INTTYPE0 -SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_Noise__SEL__MASK EQU 0x01 -SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0 -SCSI_Noise__SEL__PORT EQU 5 -SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT -SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS -SCSI_Noise__SEL__SHIFT EQU 0 -SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW +; USBFS +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 6 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_PRIOR_NUM EQU 7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_PRIOR_NUM EQU 7 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 ; scsiTarget scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 @@ -2841,89 +2997,6 @@ scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST -; Debug_Timer_Interrupt -Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -Debug_Timer_Interrupt__INTC_MASK EQU 0x02 -Debug_Timer_Interrupt__INTC_NUMBER EQU 1 -Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 -Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 -Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; Debug_Timer_TimerHW -Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 -Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 -Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 -Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 -Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 -Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 -Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 -Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 -Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 -Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 -Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 -Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 -Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 -Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 -Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 -Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 - -; SCSI_RX_DMA -SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 -SCSI_RX_DMA__NUMBEROF_TDS EQU 0 -SCSI_RX_DMA__PRIORITY EQU 2 -SCSI_RX_DMA__TERMIN_EN EQU 0 -SCSI_RX_DMA__TERMIN_SEL EQU 0 -SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 -SCSI_RX_DMA__TERMOUT1_EN EQU 0 -SCSI_RX_DMA__TERMOUT1_SEL EQU 0 - -; SCSI_RX_DMA_COMPLETE -SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_TX_DMA -SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 -SCSI_TX_DMA__NUMBEROF_TDS EQU 0 -SCSI_TX_DMA__PRIORITY EQU 2 -SCSI_TX_DMA__TERMIN_EN EQU 0 -SCSI_TX_DMA__TERMIN_SEL EQU 0 -SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 -SCSI_TX_DMA__TERMOUT1_EN EQU 0 -SCSI_TX_DMA__TERMOUT1_SEL EQU 0 - -; SCSI_TX_DMA_COMPLETE -SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 -SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SD_Data_Clk -SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 -SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 -SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 -SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Data_Clk__INDEX EQU 0x00 -SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Data_Clk__PM_ACT_MSK EQU 0x01 -SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Data_Clk__PM_STBY_MSK EQU 0x01 - ; timer_clock timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 @@ -2935,146 +3008,53 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 -; SCSI_RST_ISR -SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x04 -SCSI_RST_ISR__INTC_NUMBER EQU 2 -SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 -SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_SEL_ISR -SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 -SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 -SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_Filtered -SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Filtered_sts_sts_reg__0__POS EQU 0 -SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 -SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST -SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 -SCSI_Filtered_sts_sts_reg__2__POS EQU 2 -SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 -SCSI_Filtered_sts_sts_reg__3__POS EQU 3 -SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 -SCSI_Filtered_sts_sts_reg__4__POS EQU 4 -SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST - -; SCSI_CTL_PHASE -SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 -SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK - -; SCSI_Glitch_Ctl -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK - -; SCSI_Parity_Error -SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST -SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST - ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 12 -CYDEV_CHIP_DIE_PSOC5LP EQU 19 -CYDEV_CHIP_DIE_PSOC5TM EQU 20 -CYDEV_CHIP_DIE_TMA4 EQU 2 +CYDEV_CHIP_DIE_PSOC4A EQU 16 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 CYDEV_CHIP_DIE_UNKNOWN EQU 0 -CYDEV_CHIP_FAMILY_FM0P EQU 4 -CYDEV_CHIP_FAMILY_FM3 EQU 5 -CYDEV_CHIP_FAMILY_FM4 EQU 6 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 CYDEV_CHIP_FAMILY_PSOC3 EQU 1 CYDEV_CHIP_FAMILY_PSOC4 EQU 2 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 12 -CYDEV_CHIP_MEMBER_4C EQU 18 -CYDEV_CHIP_MEMBER_4D EQU 8 -CYDEV_CHIP_MEMBER_4E EQU 4 -CYDEV_CHIP_MEMBER_4F EQU 13 -CYDEV_CHIP_MEMBER_4G EQU 2 -CYDEV_CHIP_MEMBER_4H EQU 11 -CYDEV_CHIP_MEMBER_4I EQU 17 -CYDEV_CHIP_MEMBER_4J EQU 9 -CYDEV_CHIP_MEMBER_4K EQU 10 -CYDEV_CHIP_MEMBER_4L EQU 16 -CYDEV_CHIP_MEMBER_4M EQU 15 -CYDEV_CHIP_MEMBER_4N EQU 6 -CYDEV_CHIP_MEMBER_4O EQU 5 -CYDEV_CHIP_MEMBER_4P EQU 14 -CYDEV_CHIP_MEMBER_4Q EQU 7 -CYDEV_CHIP_MEMBER_4U EQU 3 -CYDEV_CHIP_MEMBER_5A EQU 20 -CYDEV_CHIP_MEMBER_5B EQU 19 -CYDEV_CHIP_MEMBER_FM3 EQU 24 -CYDEV_CHIP_MEMBER_FM4 EQU 25 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23 +CYDEV_CHIP_MEMBER_4A EQU 16 +CYDEV_CHIP_MEMBER_4D EQU 12 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 17 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 15 +CYDEV_CHIP_MEMBER_4I EQU 21 +CYDEV_CHIP_MEMBER_4J EQU 13 +CYDEV_CHIP_MEMBER_4K EQU 14 +CYDEV_CHIP_MEMBER_4L EQU 20 +CYDEV_CHIP_MEMBER_4M EQU 19 +CYDEV_CHIP_MEMBER_4N EQU 9 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 18 +CYDEV_CHIP_MEMBER_4Q EQU 11 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 10 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 22 +CYDEV_CHIP_MEMBER_FM3 EQU 26 +CYDEV_CHIP_MEMBER_FM4 EQU 27 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -3099,7 +3079,6 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 -CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 @@ -3118,12 +3097,16 @@ CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 @@ -3155,7 +3138,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000007E +CYDEV_INTR_RISING EQU 0x0000007F CYDEV_IS_EXPORTING_CODE EQU 0 CYDEV_IS_IMPORTING_CODE EQU 0 CYDEV_PROJ_TYPE EQU 2 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c index 8638ffb..e8e92b1 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -1,21 +1,21 @@ /******************************************************************************* * File Name: cymetadata.c * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file defines all extra memory spaces that need to be included. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. ********************************************************************************/ -#include "cytypes.h" +#include "stdint.h" #if defined(__GNUC__) || defined(__ARMCC_VERSION) @@ -28,7 +28,7 @@ CY_LOADABLE_META_SECTION #else #error "Unsupported toolchain" #endif -const uint8 cy_meta_loadable[] = { +const uint8_t cy_meta_loadable[] = { 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x71u, 0x04u, @@ -49,6 +49,6 @@ CY_CONFIG_ECC_SECTION #else #error "Unsupported toolchain" #endif -const uint8 cy_meta_configecc[] = { +const uint8_t cy_meta_configecc[] = { 0x00u }; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index 83e11bd..a6cfaf8 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: project.h * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * It contains references to all generated header files and should not be modified. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. 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-996,7 +996,7 @@ - + @@ -1204,7 +1204,7 @@ - + @@ -1230,7 +1230,7 @@ - + @@ -1256,7 +1256,7 @@ - + @@ -1282,7 +1282,7 @@ - + @@ -1329,7 +1329,7 @@ - + @@ -1362,7 +1362,7 @@ - + @@ -1395,7 +1395,7 @@ - + @@ -1421,7 +1421,7 @@ - + @@ -1489,7 +1489,7 @@ - + @@ -1515,7 +1515,7 @@ - + @@ -1541,7 +1541,7 @@ - + @@ -1567,7 +1567,7 @@ - + @@ -1593,7 +1593,7 @@ - + @@ -1619,7 +1619,7 @@ - + @@ -1771,7 +1771,7 @@ - + @@ -1804,7 +1804,7 @@ - + @@ -1851,7 +1851,7 @@ - + @@ -1877,7 +1877,7 @@ - + @@ -2050,7 +2050,7 @@ - + @@ -2083,7 +2083,7 @@ - + @@ -2116,7 +2116,7 @@ - + @@ -2149,7 +2149,7 @@ - + @@ -2175,7 +2175,7 @@ - + @@ -2208,7 +2208,7 @@ - + @@ -2234,7 +2234,7 @@ - + @@ -2267,7 +2267,7 @@ - + @@ -2300,7 +2300,7 @@ - + @@ -2333,7 +2333,7 @@ - + @@ -2359,7 +2359,7 @@ - + @@ -2385,7 +2385,7 @@ - + @@ -2411,7 +2411,7 @@ - + @@ -2437,7 +2437,7 @@ - + @@ -2463,7 +2463,7 @@ - + @@ -2489,7 +2489,7 @@ - + @@ -2515,7 +2515,7 @@ - + @@ -2541,7 +2541,7 @@ - + @@ -2567,7 +2567,7 @@ - + @@ -2593,7 +2593,7 @@ - + @@ -2619,7 +2619,7 @@ - + @@ -2645,7 +2645,7 @@ - + @@ -2671,7 +2671,7 @@ - + @@ -2697,7 +2697,7 @@ - + @@ -2723,7 +2723,7 @@ - + @@ -2742,7 +2742,7 @@ - + @@ -2768,7 +2768,7 @@ - + @@ -2794,7 +2794,7 @@ - + @@ -2864,7 +2864,7 @@ - + @@ -2894,7 +2894,7 @@ - + @@ -2973,10 +2973,10 @@ - - - + + + @@ -2989,6 +2989,15 @@ + + + + + + + + + @@ -3007,10 +3016,10 @@ - - - + + + @@ -3023,6 +3032,15 @@ + + + + + + + + + @@ -3041,10 +3059,10 @@ - - - + + + @@ -3057,6 +3075,15 @@ + + + + + + + + + @@ -3075,10 +3102,10 @@ - - - + + + @@ -3091,6 +3118,15 @@ + + + + + + + + + @@ -3113,10 +3149,10 @@ - - - + + + @@ -3129,6 +3165,15 @@ + + + + + + + + + @@ -3147,10 +3192,10 @@ - - - + + + @@ -3163,6 +3208,15 @@ + + + + + + + + + @@ -3181,10 +3235,10 @@ - - - + + + @@ -3197,6 +3251,15 @@ + + + + + + + + + @@ -3215,10 +3278,10 @@ - - - + + + @@ -3231,14 +3294,31 @@ + + + + + + + + + + + + + + + + + @@ -3249,6 +3329,7 @@ + @@ -3259,6 +3340,7 @@ + @@ -3268,12 +3350,15 @@ + + + @@ -3284,6 +3369,7 @@ + @@ -3293,12 +3379,15 @@ + + + @@ -3309,6 +3398,7 @@ + @@ -3318,12 +3408,15 @@ + + + @@ -3334,6 +3427,7 @@ + @@ -3343,31 +3437,33 @@ + + + + + - - - + + - - diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h index dbb256b..f3d1b70 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h @@ -17,7 +17,15 @@ #if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */ #define CY_CONTROL_REG_SCSI_CTL_PHASE_H -#include "cytypes.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h index dba5218..14605f1 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h @@ -17,8 +17,16 @@ #if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */ #define CY_STATUS_REG_SCSI_Filtered_H -#include "cytypes.h" -#include "CyLib.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" + #include "CyLib.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h index 50da66e..80cd7ba 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h @@ -17,7 +17,15 @@ #if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */ #define CY_CONTROL_REG_SCSI_Glitch_Ctl_H -#include "cytypes.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h index 4431995..dbdc2f3 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h @@ -17,7 +17,15 @@ #if !defined(CY_CONTROL_REG_SCSI_Out_Bits_H) /* CY_CONTROL_REG_SCSI_Out_Bits_H */ #define CY_CONTROL_REG_SCSI_Out_Bits_H -#include "cytypes.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h index 6dd3acb..7419fb7 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h @@ -17,7 +17,15 @@ #if !defined(CY_CONTROL_REG_SCSI_Out_Ctl_H) /* CY_CONTROL_REG_SCSI_Out_Ctl_H */ #define CY_CONTROL_REG_SCSI_Out_Ctl_H -#include "cytypes.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h index 9309c16..f7ce887 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h @@ -17,8 +17,16 @@ #if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */ #define CY_STATUS_REG_SCSI_Parity_Error_H -#include "cytypes.h" -#include "CyLib.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" + #include "CyLib.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h index 6d566df..6a8ae5d 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h @@ -19,15 +19,9 @@ #if !defined(CY_SPIM_SDCard_H) #define CY_SPIM_SDCard_H -#include "cytypes.h" #include "cyfitter.h" -#include "CyLib.h" - -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component SPI_Master_v2_50 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ +#include "cytypes.h" +#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */ /*************************************** diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h index e9a0eaf..160bd6a 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice.h * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h index b7f270a..bff26ed 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice_trm.h * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc index bacd4b7..5db8be3 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu.inc * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc index 22e5061..e0ed758 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu_trm.inc * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc index 019dd7c..6b49c48 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.0 Update 1 +; PSoC Creator 4.1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc index 0e2c8a3..c7c07d0 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar_trm.inc ; -; PSoC Creator 4.0 Update 1 +; PSoC Creator 4.1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc index 228aba9..e9f2b78 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.0 Update 1 +; PSoC Creator 4.1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc index 473b655..4a32cab 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv_trm.inc ; -; PSoC Creator 4.0 Update 1 +; PSoC Creator 4.1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 8a9a8f4..a11569b 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -1,395 +1,51 @@ +/******************************************************************************* +* File Name: cyfitter.h +* +* PSoC Creator 4.1 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + #ifndef INCLUDED_CYFITTER_H #define INCLUDED_CYFITTER_H #include "cydevice.h" #include "cydevice_trm.h" -/* LED1 */ -#define LED1__0__INTTYPE CYREG_PICU0_INTTYPE1 -#define LED1__0__MASK 0x02u -#define LED1__0__PC CYREG_PRT0_PC1 -#define LED1__0__PORT 0u -#define LED1__0__SHIFT 1u -#define LED1__AG CYREG_PRT0_AG -#define LED1__AMUX CYREG_PRT0_AMUX -#define LED1__BIE CYREG_PRT0_BIE -#define LED1__BIT_MASK CYREG_PRT0_BIT_MASK -#define LED1__BYP CYREG_PRT0_BYP -#define LED1__CTL CYREG_PRT0_CTL -#define LED1__DM0 CYREG_PRT0_DM0 -#define LED1__DM1 CYREG_PRT0_DM1 -#define LED1__DM2 CYREG_PRT0_DM2 -#define LED1__DR CYREG_PRT0_DR -#define LED1__INP_DIS CYREG_PRT0_INP_DIS -#define LED1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE -#define LED1__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define LED1__LCD_EN CYREG_PRT0_LCD_EN -#define LED1__MASK 0x02u -#define LED1__PORT 0u -#define LED1__PRT CYREG_PRT0_PRT -#define LED1__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define LED1__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define LED1__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define LED1__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define LED1__PS CYREG_PRT0_PS -#define LED1__SHIFT 1u -#define LED1__SLW CYREG_PRT0_SLW +/* Debug_Timer_Interrupt */ +#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define Debug_Timer_Interrupt__INTC_MASK 0x01u +#define Debug_Timer_Interrupt__INTC_NUMBER 0u +#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u +#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -/* SD_CD */ -#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE5 -#define SD_CD__0__MASK 0x20u -#define SD_CD__0__PC CYREG_PRT3_PC5 -#define SD_CD__0__PORT 3u -#define SD_CD__0__SHIFT 5u -#define SD_CD__AG CYREG_PRT3_AG -#define SD_CD__AMUX CYREG_PRT3_AMUX -#define SD_CD__BIE CYREG_PRT3_BIE -#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_CD__BYP CYREG_PRT3_BYP -#define SD_CD__CTL CYREG_PRT3_CTL -#define SD_CD__DM0 CYREG_PRT3_DM0 -#define SD_CD__DM1 CYREG_PRT3_DM1 -#define SD_CD__DM2 CYREG_PRT3_DM2 -#define SD_CD__DR CYREG_PRT3_DR -#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS -#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN -#define SD_CD__MASK 0x20u -#define SD_CD__PORT 3u -#define SD_CD__PRT CYREG_PRT3_PRT -#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_CD__PS CYREG_PRT3_PS -#define SD_CD__SHIFT 5u -#define SD_CD__SLW CYREG_PRT3_SLW - -/* SD_CS */ -#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4 -#define SD_CS__0__MASK 0x10u -#define SD_CS__0__PC CYREG_PRT3_PC4 -#define SD_CS__0__PORT 3u -#define SD_CS__0__SHIFT 4u -#define SD_CS__AG CYREG_PRT3_AG -#define SD_CS__AMUX CYREG_PRT3_AMUX -#define SD_CS__BIE CYREG_PRT3_BIE -#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_CS__BYP CYREG_PRT3_BYP -#define SD_CS__CTL CYREG_PRT3_CTL -#define SD_CS__DM0 CYREG_PRT3_DM0 -#define SD_CS__DM1 CYREG_PRT3_DM1 -#define SD_CS__DM2 CYREG_PRT3_DM2 -#define SD_CS__DR CYREG_PRT3_DR -#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS -#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN -#define SD_CS__MASK 0x10u -#define SD_CS__PORT 3u -#define SD_CS__PRT CYREG_PRT3_PRT -#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_CS__PS CYREG_PRT3_PS -#define SD_CS__SHIFT 4u -#define SD_CS__SLW CYREG_PRT3_SLW - -/* USBFS_arb_int */ -#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_arb_int__INTC_MASK 0x400000u -#define USBFS_arb_int__INTC_NUMBER 22u -#define USBFS_arb_int__INTC_PRIOR_NUM 6u -#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 -#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_bus_reset */ -#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_bus_reset__INTC_MASK 0x800000u -#define USBFS_bus_reset__INTC_NUMBER 23u -#define USBFS_bus_reset__INTC_PRIOR_NUM 7u -#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 -#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_Dm */ -#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7 -#define USBFS_Dm__0__MASK 0x80u -#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 -#define USBFS_Dm__0__PORT 15u -#define USBFS_Dm__0__SHIFT 7u -#define USBFS_Dm__AG CYREG_PRT15_AG -#define USBFS_Dm__AMUX CYREG_PRT15_AMUX -#define USBFS_Dm__BIE CYREG_PRT15_BIE -#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK -#define USBFS_Dm__BYP CYREG_PRT15_BYP -#define USBFS_Dm__CTL CYREG_PRT15_CTL -#define USBFS_Dm__DM0 CYREG_PRT15_DM0 -#define USBFS_Dm__DM1 CYREG_PRT15_DM1 -#define USBFS_Dm__DM2 CYREG_PRT15_DM2 -#define USBFS_Dm__DR CYREG_PRT15_DR -#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS -#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE -#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG -#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN -#define USBFS_Dm__MASK 0x80u -#define USBFS_Dm__PORT 15u -#define USBFS_Dm__PRT CYREG_PRT15_PRT -#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL -#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN -#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 -#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 -#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 -#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 -#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT -#define USBFS_Dm__PS CYREG_PRT15_PS -#define USBFS_Dm__SHIFT 7u -#define USBFS_Dm__SLW CYREG_PRT15_SLW - -/* USBFS_Dp */ -#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6 -#define USBFS_Dp__0__MASK 0x40u -#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 -#define USBFS_Dp__0__PORT 15u -#define USBFS_Dp__0__SHIFT 6u -#define USBFS_Dp__AG CYREG_PRT15_AG -#define USBFS_Dp__AMUX CYREG_PRT15_AMUX -#define USBFS_Dp__BIE CYREG_PRT15_BIE -#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK -#define USBFS_Dp__BYP CYREG_PRT15_BYP -#define USBFS_Dp__CTL CYREG_PRT15_CTL -#define USBFS_Dp__DM0 CYREG_PRT15_DM0 -#define USBFS_Dp__DM1 CYREG_PRT15_DM1 -#define USBFS_Dp__DM2 CYREG_PRT15_DM2 -#define USBFS_Dp__DR CYREG_PRT15_DR -#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS -#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT -#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE -#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG -#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN -#define USBFS_Dp__MASK 0x40u -#define USBFS_Dp__PORT 15u -#define USBFS_Dp__PRT CYREG_PRT15_PRT -#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL -#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN -#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 -#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 -#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 -#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 -#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT -#define USBFS_Dp__PS CYREG_PRT15_PS -#define USBFS_Dp__SHIFT 6u -#define USBFS_Dp__SLW CYREG_PRT15_SLW -#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 - -/* USBFS_dp_int */ -#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_dp_int__INTC_MASK 0x1000u -#define USBFS_dp_int__INTC_NUMBER 12u -#define USBFS_dp_int__INTC_PRIOR_NUM 7u -#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 -#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_0 */ -#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_0__INTC_MASK 0x1000000u -#define USBFS_ep_0__INTC_NUMBER 24u -#define USBFS_ep_0__INTC_PRIOR_NUM 7u -#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 -#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_1 */ -#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x80u -#define USBFS_ep_1__INTC_NUMBER 7u -#define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 -#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_2 */ -#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x100u -#define USBFS_ep_2__INTC_NUMBER 8u -#define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 -#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_3 */ -#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_3__INTC_MASK 0x200u -#define USBFS_ep_3__INTC_NUMBER 9u -#define USBFS_ep_3__INTC_PRIOR_NUM 7u -#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 -#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_4 */ -#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_4__INTC_MASK 0x400u -#define USBFS_ep_4__INTC_NUMBER 10u -#define USBFS_ep_4__INTC_PRIOR_NUM 7u -#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 -#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_sof_int */ -#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_sof_int__INTC_MASK 0x200000u -#define USBFS_sof_int__INTC_NUMBER 21u -#define USBFS_sof_int__INTC_PRIOR_NUM 7u -#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 -#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_USB */ -#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG -#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG -#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN -#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR -#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG -#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN -#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR -#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG -#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN -#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR -#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG -#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN -#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR -#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG -#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN -#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR -#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG -#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN -#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR -#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG -#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN -#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR -#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG -#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN -#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR -#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN -#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR -#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR -#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA -#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB -#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA -#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB -#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR -#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA -#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB -#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA -#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB -#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR -#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA -#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB -#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA -#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB -#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR -#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA -#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB -#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA -#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB -#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR -#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA -#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB -#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA -#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB -#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR -#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA -#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB -#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA -#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB -#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR -#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA -#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB -#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA -#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB -#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR -#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA -#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB -#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA -#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB -#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE -#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT -#define USBFS_USB__CR0 CYREG_USB_CR0 -#define USBFS_USB__CR1 CYREG_USB_CR1 -#define USBFS_USB__CWA CYREG_USB_CWA -#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB -#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES -#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB -#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG -#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE -#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE -#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT -#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR -#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 -#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 -#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 -#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 -#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 -#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 -#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 -#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 -#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE -#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 -#define USBFS_USB__PM_ACT_MSK 0x01u -#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 -#define USBFS_USB__PM_STBY_MSK 0x01u -#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN -#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR -#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 -#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 -#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 -#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 -#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 -#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 -#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 -#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 -#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 -#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 -#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 -#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 -#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 -#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 -#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 -#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 -#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 -#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 -#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 -#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 -#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 -#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 -#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 -#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 -#define USBFS_USB__SOF0 CYREG_USB_SOF0 -#define USBFS_USB__SOF1 CYREG_USB_SOF1 -#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN -#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 -#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 +/* Debug_Timer_TimerHW */ +#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0 +#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1 +#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0 +#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1 +#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2 +#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 +#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 +#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0 +#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1 +#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 +#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u +#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 +#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u +#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0 +#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1 +#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0 /* EXTLED */ #define EXTLED__0__INTTYPE CYREG_PICU0_INTTYPE0 @@ -425,112 +81,116 @@ #define EXTLED__SHIFT 0u #define EXTLED__SLW CYREG_PRT0_SLW -/* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST -#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u -#define SDCard_BSPIM_RxStsReg__4__POS 4 -#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u -#define SDCard_BSPIM_RxStsReg__5__POS 5 -#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u -#define SDCard_BSPIM_RxStsReg__6__POS 6 -#define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 -#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u -#define SDCard_BSPIM_TxStsReg__0__POS 0 -#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u -#define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST -#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u -#define SDCard_BSPIM_TxStsReg__2__POS 2 -#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u -#define SDCard_BSPIM_TxStsReg__3__POS 3 -#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u -#define SDCard_BSPIM_TxStsReg__4__POS 4 -#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST +/* LED1 */ +#define LED1__0__INTTYPE CYREG_PICU0_INTTYPE1 +#define LED1__0__MASK 0x02u +#define LED1__0__PC CYREG_PRT0_PC1 +#define LED1__0__PORT 0u +#define LED1__0__SHIFT 1u +#define LED1__AG CYREG_PRT0_AG +#define LED1__AMUX CYREG_PRT0_AMUX +#define LED1__BIE CYREG_PRT0_BIE +#define LED1__BIT_MASK CYREG_PRT0_BIT_MASK +#define LED1__BYP CYREG_PRT0_BYP +#define LED1__CTL CYREG_PRT0_CTL +#define LED1__DM0 CYREG_PRT0_DM0 +#define LED1__DM1 CYREG_PRT0_DM1 +#define LED1__DM2 CYREG_PRT0_DM2 +#define LED1__DR CYREG_PRT0_DR +#define LED1__INP_DIS CYREG_PRT0_INP_DIS +#define LED1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE +#define LED1__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define LED1__LCD_EN CYREG_PRT0_LCD_EN +#define LED1__MASK 0x02u +#define LED1__PORT 0u +#define LED1__PRT CYREG_PRT0_PRT +#define LED1__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define LED1__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define LED1__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define LED1__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define LED1__PS CYREG_PRT0_PS +#define LED1__SHIFT 1u +#define LED1__SLW CYREG_PRT0_SLW -/* SD_SCK */ -#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2 -#define SD_SCK__0__MASK 0x04u -#define SD_SCK__0__PC CYREG_PRT3_PC2 -#define SD_SCK__0__PORT 3u -#define SD_SCK__0__SHIFT 2u -#define SD_SCK__AG CYREG_PRT3_AG -#define SD_SCK__AMUX CYREG_PRT3_AMUX -#define SD_SCK__BIE CYREG_PRT3_BIE -#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_SCK__BYP CYREG_PRT3_BYP -#define SD_SCK__CTL CYREG_PRT3_CTL -#define SD_SCK__DM0 CYREG_PRT3_DM0 -#define SD_SCK__DM1 CYREG_PRT3_DM1 -#define SD_SCK__DM2 CYREG_PRT3_DM2 -#define SD_SCK__DR CYREG_PRT3_DR -#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS -#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN -#define SD_SCK__MASK 0x04u -#define SD_SCK__PORT 3u -#define SD_SCK__PRT CYREG_PRT3_PRT -#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_SCK__PS CYREG_PRT3_PS -#define SD_SCK__SHIFT 2u -#define SD_SCK__SLW CYREG_PRT3_SLW +/* SCSI_CLK */ +#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 +#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 +#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2 +#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u +#define SCSI_CLK__INDEX 0x01u +#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SCSI_CLK__PM_ACT_MSK 0x02u +#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SCSI_CLK__PM_STBY_MSK 0x02u + +/* SCSI_CTL_PHASE */ +#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK + +/* SCSI_Filtered */ +#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u +#define SCSI_Filtered_sts_sts_reg__0__POS 0 +#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u +#define SCSI_Filtered_sts_sts_reg__1__POS 1 +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST +#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u +#define SCSI_Filtered_sts_sts_reg__2__POS 2 +#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u +#define SCSI_Filtered_sts_sts_reg__3__POS 3 +#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u +#define SCSI_Filtered_sts_sts_reg__4__POS 4 +#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST + +/* SCSI_Glitch_Ctl */ +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK /* SCSI_In */ #define SCSI_In__0__AG CYREG_PRT2_AG @@ -813,8 +473,6 @@ #define SCSI_In__REQ__PS CYREG_PRT0_PS #define SCSI_In__REQ__SHIFT 5u #define SCSI_In__REQ__SLW CYREG_PRT0_SLW - -/* SCSI_In_DBx */ #define SCSI_In_DBx__0__AG CYREG_PRT5_AG #define SCSI_In_DBx__0__AMUX CYREG_PRT5_AMUX #define SCSI_In_DBx__0__BIE CYREG_PRT5_BIE @@ -1260,84 +918,287 @@ #define SCSI_In_DBx__DB7__SHIFT 4u #define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW -/* SD_MISO */ -#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1 -#define SD_MISO__0__MASK 0x02u -#define SD_MISO__0__PC CYREG_PRT3_PC1 -#define SD_MISO__0__PORT 3u -#define SD_MISO__0__SHIFT 1u -#define SD_MISO__AG CYREG_PRT3_AG -#define SD_MISO__AMUX CYREG_PRT3_AMUX -#define SD_MISO__BIE CYREG_PRT3_BIE -#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_MISO__BYP CYREG_PRT3_BYP -#define SD_MISO__CTL CYREG_PRT3_CTL -#define SD_MISO__DM0 CYREG_PRT3_DM0 -#define SD_MISO__DM1 CYREG_PRT3_DM1 -#define SD_MISO__DM2 CYREG_PRT3_DM2 -#define SD_MISO__DR CYREG_PRT3_DR -#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS -#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN -#define SD_MISO__MASK 0x02u -#define SD_MISO__PORT 3u -#define SD_MISO__PRT CYREG_PRT3_PRT -#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_MISO__PS CYREG_PRT3_PS -#define SD_MISO__SHIFT 1u -#define SD_MISO__SLW CYREG_PRT3_SLW - -/* SD_MOSI */ -#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3 -#define SD_MOSI__0__MASK 0x08u -#define SD_MOSI__0__PC CYREG_PRT3_PC3 -#define SD_MOSI__0__PORT 3u -#define SD_MOSI__0__SHIFT 3u -#define SD_MOSI__AG CYREG_PRT3_AG -#define SD_MOSI__AMUX CYREG_PRT3_AMUX -#define SD_MOSI__BIE CYREG_PRT3_BIE -#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_MOSI__BYP CYREG_PRT3_BYP -#define SD_MOSI__CTL CYREG_PRT3_CTL -#define SD_MOSI__DM0 CYREG_PRT3_DM0 -#define SD_MOSI__DM1 CYREG_PRT3_DM1 -#define SD_MOSI__DM2 CYREG_PRT3_DM2 -#define SD_MOSI__DR CYREG_PRT3_DR -#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS -#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN -#define SD_MOSI__MASK 0x08u -#define SD_MOSI__PORT 3u -#define SD_MOSI__PRT CYREG_PRT3_PRT -#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_MOSI__PS CYREG_PRT3_PS -#define SD_MOSI__SHIFT 3u -#define SD_MOSI__SLW CYREG_PRT3_SLW - -/* SCSI_CLK */ -#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 -#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 -#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2 -#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u -#define SCSI_CLK__INDEX 0x01u -#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define SCSI_CLK__PM_ACT_MSK 0x02u -#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define SCSI_CLK__PM_STBY_MSK 0x02u +/* SCSI_Noise */ +#define SCSI_Noise__0__AG CYREG_PRT2_AG +#define SCSI_Noise__0__AMUX CYREG_PRT2_AMUX +#define SCSI_Noise__0__BIE CYREG_PRT2_BIE +#define SCSI_Noise__0__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Noise__0__BYP CYREG_PRT2_BYP +#define SCSI_Noise__0__CTL CYREG_PRT2_CTL +#define SCSI_Noise__0__DM0 CYREG_PRT2_DM0 +#define SCSI_Noise__0__DM1 CYREG_PRT2_DM1 +#define SCSI_Noise__0__DM2 CYREG_PRT2_DM2 +#define SCSI_Noise__0__DR CYREG_PRT2_DR +#define SCSI_Noise__0__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Noise__0__INTTYPE CYREG_PICU2_INTTYPE0 +#define SCSI_Noise__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Noise__0__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Noise__0__MASK 0x01u +#define SCSI_Noise__0__PC CYREG_PRT2_PC0 +#define SCSI_Noise__0__PORT 2u +#define SCSI_Noise__0__PRT CYREG_PRT2_PRT +#define SCSI_Noise__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Noise__0__PS CYREG_PRT2_PS +#define SCSI_Noise__0__SHIFT 0u +#define SCSI_Noise__0__SLW CYREG_PRT2_SLW +#define SCSI_Noise__1__AG CYREG_PRT6_AG +#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__1__BIE CYREG_PRT6_BIE +#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__1__BYP CYREG_PRT6_BYP +#define SCSI_Noise__1__CTL CYREG_PRT6_CTL +#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__1__DR CYREG_PRT6_DR +#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__1__INTTYPE CYREG_PICU6_INTTYPE3 +#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__1__MASK 0x08u +#define SCSI_Noise__1__PC CYREG_PRT6_PC3 +#define SCSI_Noise__1__PORT 6u +#define SCSI_Noise__1__PRT CYREG_PRT6_PRT +#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__1__PS CYREG_PRT6_PS +#define SCSI_Noise__1__SHIFT 3u +#define SCSI_Noise__1__SLW CYREG_PRT6_SLW +#define SCSI_Noise__2__AG CYREG_PRT4_AG +#define SCSI_Noise__2__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__2__BIE CYREG_PRT4_BIE +#define SCSI_Noise__2__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__2__BYP CYREG_PRT4_BYP +#define SCSI_Noise__2__CTL CYREG_PRT4_CTL +#define SCSI_Noise__2__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__2__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__2__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__2__DR CYREG_PRT4_DR +#define SCSI_Noise__2__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__2__INTTYPE CYREG_PICU4_INTTYPE3 +#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__2__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__2__MASK 0x08u +#define SCSI_Noise__2__PC CYREG_PRT4_PC3 +#define SCSI_Noise__2__PORT 4u +#define SCSI_Noise__2__PRT CYREG_PRT4_PRT +#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__2__PS CYREG_PRT4_PS +#define SCSI_Noise__2__SHIFT 3u +#define SCSI_Noise__2__SLW CYREG_PRT4_SLW +#define SCSI_Noise__3__AG CYREG_PRT4_AG +#define SCSI_Noise__3__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__3__BIE CYREG_PRT4_BIE +#define SCSI_Noise__3__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__3__BYP CYREG_PRT4_BYP +#define SCSI_Noise__3__CTL CYREG_PRT4_CTL +#define SCSI_Noise__3__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__3__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__3__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__3__DR CYREG_PRT4_DR +#define SCSI_Noise__3__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__3__INTTYPE CYREG_PICU4_INTTYPE7 +#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__3__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__3__MASK 0x80u +#define SCSI_Noise__3__PC CYREG_PRT4_PC7 +#define SCSI_Noise__3__PORT 4u +#define SCSI_Noise__3__PRT CYREG_PRT4_PRT +#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__3__PS CYREG_PRT4_PS +#define SCSI_Noise__3__SHIFT 7u +#define SCSI_Noise__3__SLW CYREG_PRT4_SLW +#define SCSI_Noise__4__AG CYREG_PRT6_AG +#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__4__BIE CYREG_PRT6_BIE +#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__4__BYP CYREG_PRT6_BYP +#define SCSI_Noise__4__CTL CYREG_PRT6_CTL +#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__4__DR CYREG_PRT6_DR +#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__4__INTTYPE CYREG_PICU6_INTTYPE2 +#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__4__MASK 0x04u +#define SCSI_Noise__4__PC CYREG_PRT6_PC2 +#define SCSI_Noise__4__PORT 6u +#define SCSI_Noise__4__PRT CYREG_PRT6_PRT +#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__4__PS CYREG_PRT6_PS +#define SCSI_Noise__4__SHIFT 2u +#define SCSI_Noise__4__SLW CYREG_PRT6_SLW +#define SCSI_Noise__ACK__AG CYREG_PRT6_AG +#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE +#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP +#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL +#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__ACK__DR CYREG_PRT6_DR +#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__ACK__INTTYPE CYREG_PICU6_INTTYPE2 +#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__ACK__MASK 0x04u +#define SCSI_Noise__ACK__PC CYREG_PRT6_PC2 +#define SCSI_Noise__ACK__PORT 6u +#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT +#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__ACK__PS CYREG_PRT6_PS +#define SCSI_Noise__ACK__SHIFT 2u +#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW +#define SCSI_Noise__ATN__AG CYREG_PRT2_AG +#define SCSI_Noise__ATN__AMUX CYREG_PRT2_AMUX +#define SCSI_Noise__ATN__BIE CYREG_PRT2_BIE +#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Noise__ATN__BYP CYREG_PRT2_BYP +#define SCSI_Noise__ATN__CTL CYREG_PRT2_CTL +#define SCSI_Noise__ATN__DM0 CYREG_PRT2_DM0 +#define SCSI_Noise__ATN__DM1 CYREG_PRT2_DM1 +#define SCSI_Noise__ATN__DM2 CYREG_PRT2_DM2 +#define SCSI_Noise__ATN__DR CYREG_PRT2_DR +#define SCSI_Noise__ATN__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Noise__ATN__INTTYPE CYREG_PICU2_INTTYPE0 +#define SCSI_Noise__ATN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Noise__ATN__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Noise__ATN__MASK 0x01u +#define SCSI_Noise__ATN__PC CYREG_PRT2_PC0 +#define SCSI_Noise__ATN__PORT 2u +#define SCSI_Noise__ATN__PRT CYREG_PRT2_PRT +#define SCSI_Noise__ATN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Noise__ATN__PS CYREG_PRT2_PS +#define SCSI_Noise__ATN__SHIFT 0u +#define SCSI_Noise__ATN__SLW CYREG_PRT2_SLW +#define SCSI_Noise__BSY__AG CYREG_PRT6_AG +#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE +#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP +#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL +#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__BSY__DR CYREG_PRT6_DR +#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__BSY__INTTYPE CYREG_PICU6_INTTYPE3 +#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__BSY__MASK 0x08u +#define SCSI_Noise__BSY__PC CYREG_PRT6_PC3 +#define SCSI_Noise__BSY__PORT 6u +#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT +#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__BSY__PS CYREG_PRT6_PS +#define SCSI_Noise__BSY__SHIFT 3u +#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW +#define SCSI_Noise__RST__AG CYREG_PRT4_AG +#define SCSI_Noise__RST__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__RST__BIE CYREG_PRT4_BIE +#define SCSI_Noise__RST__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__RST__BYP CYREG_PRT4_BYP +#define SCSI_Noise__RST__CTL CYREG_PRT4_CTL +#define SCSI_Noise__RST__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__RST__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__RST__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__RST__DR CYREG_PRT4_DR +#define SCSI_Noise__RST__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__RST__INTTYPE CYREG_PICU4_INTTYPE7 +#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__RST__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__RST__MASK 0x80u +#define SCSI_Noise__RST__PC CYREG_PRT4_PC7 +#define SCSI_Noise__RST__PORT 4u +#define SCSI_Noise__RST__PRT CYREG_PRT4_PRT +#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__RST__PS CYREG_PRT4_PS +#define SCSI_Noise__RST__SHIFT 7u +#define SCSI_Noise__RST__SLW CYREG_PRT4_SLW +#define SCSI_Noise__SEL__AG CYREG_PRT4_AG +#define SCSI_Noise__SEL__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__SEL__BIE CYREG_PRT4_BIE +#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__SEL__BYP CYREG_PRT4_BYP +#define SCSI_Noise__SEL__CTL CYREG_PRT4_CTL +#define SCSI_Noise__SEL__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__SEL__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__SEL__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__SEL__DR CYREG_PRT4_DR +#define SCSI_Noise__SEL__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__SEL__INTTYPE CYREG_PICU4_INTTYPE3 +#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__SEL__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__SEL__MASK 0x08u +#define SCSI_Noise__SEL__PC CYREG_PRT4_PC3 +#define SCSI_Noise__SEL__PORT 4u +#define SCSI_Noise__SEL__PRT CYREG_PRT4_PRT +#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__SEL__PS CYREG_PRT4_PS +#define SCSI_Noise__SEL__SHIFT 3u +#define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW /* SCSI_Out */ #define SCSI_Out__0__AG CYREG_PRT15_AG @@ -1900,8 +1761,6 @@ #define SCSI_Out__SEL__PS CYREG_PRT0_PS #define SCSI_Out__SEL__SHIFT 7u #define SCSI_Out__SEL__SLW CYREG_PRT0_SLW - -/* SCSI_Out_Bits */ #define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u @@ -1936,8 +1795,6 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL #define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL #define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK - -/* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL @@ -1958,8 +1815,6 @@ #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL #define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL #define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK - -/* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT5_AG #define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX #define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE @@ -2409,6 +2264,296 @@ #define SCSI_Out_DBx__DB7__SHIFT 2u #define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW +/* SCSI_Parity_Error */ +#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__0__POS 0 +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST + +/* SCSI_RST_ISR */ +#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RST_ISR__INTC_MASK 0x02u +#define SCSI_RST_ISR__INTC_NUMBER 1u +#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u +#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_RX_DMA */ +#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_RX_DMA__DRQ_NUMBER 0u +#define SCSI_RX_DMA__NUMBEROF_TDS 0u +#define SCSI_RX_DMA__PRIORITY 2u +#define SCSI_RX_DMA__TERMIN_EN 0u +#define SCSI_RX_DMA__TERMIN_SEL 0u +#define SCSI_RX_DMA__TERMOUT0_EN 1u +#define SCSI_RX_DMA__TERMOUT0_SEL 0u +#define SCSI_RX_DMA__TERMOUT1_EN 0u +#define SCSI_RX_DMA__TERMOUT1_SEL 0u +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u +#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_SEL_ISR__INTC_MASK 0x08u +#define SCSI_SEL_ISR__INTC_NUMBER 3u +#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u +#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_TX_DMA__DRQ_NUMBER 1u +#define SCSI_TX_DMA__NUMBEROF_TDS 0u +#define SCSI_TX_DMA__PRIORITY 2u +#define SCSI_TX_DMA__TERMIN_EN 0u +#define SCSI_TX_DMA__TERMIN_SEL 0u +#define SCSI_TX_DMA__TERMOUT0_EN 1u +#define SCSI_TX_DMA__TERMOUT0_SEL 1u +#define SCSI_TX_DMA__TERMOUT1_EN 0u +#define SCSI_TX_DMA__TERMOUT1_SEL 0u +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u +#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SDCard_BSPIM */ +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_RxStsReg__4__POS 4 +#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u +#define SDCard_BSPIM_RxStsReg__5__POS 5 +#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u +#define SDCard_BSPIM_RxStsReg__6__POS 6 +#define SDCard_BSPIM_RxStsReg__MASK 0x70u +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 +#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u +#define SDCard_BSPIM_TxStsReg__0__POS 0 +#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u +#define SDCard_BSPIM_TxStsReg__1__POS 1 +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u +#define SDCard_BSPIM_TxStsReg__2__POS 2 +#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u +#define SDCard_BSPIM_TxStsReg__3__POS 3 +#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_TxStsReg__4__POS 4 +#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST + +/* SD_CD */ +#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE5 +#define SD_CD__0__MASK 0x20u +#define SD_CD__0__PC CYREG_PRT3_PC5 +#define SD_CD__0__PORT 3u +#define SD_CD__0__SHIFT 5u +#define SD_CD__AG CYREG_PRT3_AG +#define SD_CD__AMUX CYREG_PRT3_AMUX +#define SD_CD__BIE CYREG_PRT3_BIE +#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CD__BYP CYREG_PRT3_BYP +#define SD_CD__CTL CYREG_PRT3_CTL +#define SD_CD__DM0 CYREG_PRT3_DM0 +#define SD_CD__DM1 CYREG_PRT3_DM1 +#define SD_CD__DM2 CYREG_PRT3_DM2 +#define SD_CD__DR CYREG_PRT3_DR +#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CD__MASK 0x20u +#define SD_CD__PORT 3u +#define SD_CD__PRT CYREG_PRT3_PRT +#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CD__PS CYREG_PRT3_PS +#define SD_CD__SHIFT 5u +#define SD_CD__SLW CYREG_PRT3_SLW + +/* SD_CS */ +#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4 +#define SD_CS__0__MASK 0x10u +#define SD_CS__0__PC CYREG_PRT3_PC4 +#define SD_CS__0__PORT 3u +#define SD_CS__0__SHIFT 4u +#define SD_CS__AG CYREG_PRT3_AG +#define SD_CS__AMUX CYREG_PRT3_AMUX +#define SD_CS__BIE CYREG_PRT3_BIE +#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CS__BYP CYREG_PRT3_BYP +#define SD_CS__CTL CYREG_PRT3_CTL +#define SD_CS__DM0 CYREG_PRT3_DM0 +#define SD_CS__DM1 CYREG_PRT3_DM1 +#define SD_CS__DM2 CYREG_PRT3_DM2 +#define SD_CS__DR CYREG_PRT3_DR +#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CS__MASK 0x10u +#define SD_CS__PORT 3u +#define SD_CS__PRT CYREG_PRT3_PRT +#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CS__PS CYREG_PRT3_PS +#define SD_CS__SHIFT 4u +#define SD_CS__SLW CYREG_PRT3_SLW + +/* SD_Data_Clk */ +#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 +#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 +#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 +#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u +#define SD_Data_Clk__INDEX 0x00u +#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SD_Data_Clk__PM_ACT_MSK 0x01u +#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SD_Data_Clk__PM_STBY_MSK 0x01u + +/* SD_MISO */ +#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1 +#define SD_MISO__0__MASK 0x02u +#define SD_MISO__0__PC CYREG_PRT3_PC1 +#define SD_MISO__0__PORT 3u +#define SD_MISO__0__SHIFT 1u +#define SD_MISO__AG CYREG_PRT3_AG +#define SD_MISO__AMUX CYREG_PRT3_AMUX +#define SD_MISO__BIE CYREG_PRT3_BIE +#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MISO__BYP CYREG_PRT3_BYP +#define SD_MISO__CTL CYREG_PRT3_CTL +#define SD_MISO__DM0 CYREG_PRT3_DM0 +#define SD_MISO__DM1 CYREG_PRT3_DM1 +#define SD_MISO__DM2 CYREG_PRT3_DM2 +#define SD_MISO__DR CYREG_PRT3_DR +#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MISO__MASK 0x02u +#define SD_MISO__PORT 3u +#define SD_MISO__PRT CYREG_PRT3_PRT +#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MISO__PS CYREG_PRT3_PS +#define SD_MISO__SHIFT 1u +#define SD_MISO__SLW CYREG_PRT3_SLW + +/* SD_MOSI */ +#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3 +#define SD_MOSI__0__MASK 0x08u +#define SD_MOSI__0__PC CYREG_PRT3_PC3 +#define SD_MOSI__0__PORT 3u +#define SD_MOSI__0__SHIFT 3u +#define SD_MOSI__AG CYREG_PRT3_AG +#define SD_MOSI__AMUX CYREG_PRT3_AMUX +#define SD_MOSI__BIE CYREG_PRT3_BIE +#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MOSI__BYP CYREG_PRT3_BYP +#define SD_MOSI__CTL CYREG_PRT3_CTL +#define SD_MOSI__DM0 CYREG_PRT3_DM0 +#define SD_MOSI__DM1 CYREG_PRT3_DM1 +#define SD_MOSI__DM2 CYREG_PRT3_DM2 +#define SD_MOSI__DR CYREG_PRT3_DR +#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MOSI__MASK 0x08u +#define SD_MOSI__PORT 3u +#define SD_MOSI__PRT CYREG_PRT3_PRT +#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MOSI__PS CYREG_PRT3_PS +#define SD_MOSI__SHIFT 3u +#define SD_MOSI__SLW CYREG_PRT3_SLW + /* SD_RX_DMA */ #define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_RX_DMA__DRQ_NUMBER 2u @@ -2420,8 +2565,6 @@ #define SD_RX_DMA__TERMOUT0_SEL 2u #define SD_RX_DMA__TERMOUT1_EN 0u #define SD_RX_DMA__TERMOUT1_SEL 0u - -/* SD_RX_DMA_COMPLETE */ #define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 #define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u @@ -2431,6 +2574,40 @@ #define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* SD_SCK */ +#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2 +#define SD_SCK__0__MASK 0x04u +#define SD_SCK__0__PC CYREG_PRT3_PC2 +#define SD_SCK__0__PORT 3u +#define SD_SCK__0__SHIFT 2u +#define SD_SCK__AG CYREG_PRT3_AG +#define SD_SCK__AMUX CYREG_PRT3_AMUX +#define SD_SCK__BIE CYREG_PRT3_BIE +#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_SCK__BYP CYREG_PRT3_BYP +#define SD_SCK__CTL CYREG_PRT3_CTL +#define SD_SCK__DM0 CYREG_PRT3_DM0 +#define SD_SCK__DM1 CYREG_PRT3_DM1 +#define SD_SCK__DM2 CYREG_PRT3_DM2 +#define SD_SCK__DR CYREG_PRT3_DR +#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS +#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN +#define SD_SCK__MASK 0x04u +#define SD_SCK__PORT 3u +#define SD_SCK__PRT CYREG_PRT3_PRT +#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_SCK__PS CYREG_PRT3_PS +#define SD_SCK__SHIFT 2u +#define SD_SCK__SLW CYREG_PRT3_SLW + /* SD_TX_DMA */ #define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_TX_DMA__DRQ_NUMBER 3u @@ -2442,8 +2619,6 @@ #define SD_TX_DMA__TERMOUT0_SEL 3u #define SD_TX_DMA__TERMOUT1_EN 0u #define SD_TX_DMA__TERMOUT1_SEL 0u - -/* SD_TX_DMA_COMPLETE */ #define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 #define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u @@ -2453,287 +2628,269 @@ #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -/* SCSI_Noise */ -#define SCSI_Noise__0__AG CYREG_PRT2_AG -#define SCSI_Noise__0__AMUX CYREG_PRT2_AMUX -#define SCSI_Noise__0__BIE CYREG_PRT2_BIE -#define SCSI_Noise__0__BIT_MASK CYREG_PRT2_BIT_MASK -#define SCSI_Noise__0__BYP CYREG_PRT2_BYP -#define SCSI_Noise__0__CTL CYREG_PRT2_CTL -#define SCSI_Noise__0__DM0 CYREG_PRT2_DM0 -#define SCSI_Noise__0__DM1 CYREG_PRT2_DM1 -#define SCSI_Noise__0__DM2 CYREG_PRT2_DM2 -#define SCSI_Noise__0__DR CYREG_PRT2_DR -#define SCSI_Noise__0__INP_DIS CYREG_PRT2_INP_DIS -#define SCSI_Noise__0__INTTYPE CYREG_PICU2_INTTYPE0 -#define SCSI_Noise__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG -#define SCSI_Noise__0__LCD_EN CYREG_PRT2_LCD_EN -#define SCSI_Noise__0__MASK 0x01u -#define SCSI_Noise__0__PC CYREG_PRT2_PC0 -#define SCSI_Noise__0__PORT 2u -#define SCSI_Noise__0__PRT CYREG_PRT2_PRT -#define SCSI_Noise__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL -#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN -#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 -#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 -#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 -#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 -#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT -#define SCSI_Noise__0__PS CYREG_PRT2_PS -#define SCSI_Noise__0__SHIFT 0u -#define SCSI_Noise__0__SLW CYREG_PRT2_SLW -#define SCSI_Noise__1__AG CYREG_PRT6_AG -#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__1__BIE CYREG_PRT6_BIE -#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__1__BYP CYREG_PRT6_BYP -#define SCSI_Noise__1__CTL CYREG_PRT6_CTL -#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__1__DR CYREG_PRT6_DR -#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__1__INTTYPE CYREG_PICU6_INTTYPE3 -#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__1__MASK 0x08u -#define SCSI_Noise__1__PC CYREG_PRT6_PC3 -#define SCSI_Noise__1__PORT 6u -#define SCSI_Noise__1__PRT CYREG_PRT6_PRT -#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__1__PS CYREG_PRT6_PS -#define SCSI_Noise__1__SHIFT 3u -#define SCSI_Noise__1__SLW CYREG_PRT6_SLW -#define SCSI_Noise__2__AG CYREG_PRT4_AG -#define SCSI_Noise__2__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__2__BIE CYREG_PRT4_BIE -#define SCSI_Noise__2__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__2__BYP CYREG_PRT4_BYP -#define SCSI_Noise__2__CTL CYREG_PRT4_CTL -#define SCSI_Noise__2__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__2__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__2__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__2__DR CYREG_PRT4_DR -#define SCSI_Noise__2__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__2__INTTYPE CYREG_PICU4_INTTYPE3 -#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__2__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__2__MASK 0x08u -#define SCSI_Noise__2__PC CYREG_PRT4_PC3 -#define SCSI_Noise__2__PORT 4u -#define SCSI_Noise__2__PRT CYREG_PRT4_PRT -#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__2__PS CYREG_PRT4_PS -#define SCSI_Noise__2__SHIFT 3u -#define SCSI_Noise__2__SLW CYREG_PRT4_SLW -#define SCSI_Noise__3__AG CYREG_PRT4_AG -#define SCSI_Noise__3__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__3__BIE CYREG_PRT4_BIE -#define SCSI_Noise__3__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__3__BYP CYREG_PRT4_BYP -#define SCSI_Noise__3__CTL CYREG_PRT4_CTL -#define SCSI_Noise__3__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__3__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__3__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__3__DR CYREG_PRT4_DR -#define SCSI_Noise__3__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__3__INTTYPE CYREG_PICU4_INTTYPE7 -#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__3__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__3__MASK 0x80u -#define SCSI_Noise__3__PC CYREG_PRT4_PC7 -#define SCSI_Noise__3__PORT 4u -#define SCSI_Noise__3__PRT CYREG_PRT4_PRT -#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__3__PS CYREG_PRT4_PS -#define SCSI_Noise__3__SHIFT 7u -#define SCSI_Noise__3__SLW CYREG_PRT4_SLW -#define SCSI_Noise__4__AG CYREG_PRT6_AG -#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__4__BIE CYREG_PRT6_BIE -#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__4__BYP CYREG_PRT6_BYP -#define SCSI_Noise__4__CTL CYREG_PRT6_CTL -#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__4__DR CYREG_PRT6_DR -#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__4__INTTYPE CYREG_PICU6_INTTYPE2 -#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__4__MASK 0x04u -#define SCSI_Noise__4__PC CYREG_PRT6_PC2 -#define SCSI_Noise__4__PORT 6u -#define SCSI_Noise__4__PRT CYREG_PRT6_PRT -#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__4__PS CYREG_PRT6_PS -#define SCSI_Noise__4__SHIFT 2u -#define SCSI_Noise__4__SLW CYREG_PRT6_SLW -#define SCSI_Noise__ACK__AG CYREG_PRT6_AG -#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE -#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP -#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL -#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__ACK__DR CYREG_PRT6_DR -#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__ACK__INTTYPE CYREG_PICU6_INTTYPE2 -#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__ACK__MASK 0x04u -#define SCSI_Noise__ACK__PC CYREG_PRT6_PC2 -#define SCSI_Noise__ACK__PORT 6u -#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT -#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__ACK__PS CYREG_PRT6_PS -#define SCSI_Noise__ACK__SHIFT 2u -#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW -#define SCSI_Noise__ATN__AG CYREG_PRT2_AG -#define SCSI_Noise__ATN__AMUX CYREG_PRT2_AMUX -#define SCSI_Noise__ATN__BIE CYREG_PRT2_BIE -#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT2_BIT_MASK -#define SCSI_Noise__ATN__BYP CYREG_PRT2_BYP -#define SCSI_Noise__ATN__CTL CYREG_PRT2_CTL -#define SCSI_Noise__ATN__DM0 CYREG_PRT2_DM0 -#define SCSI_Noise__ATN__DM1 CYREG_PRT2_DM1 -#define SCSI_Noise__ATN__DM2 CYREG_PRT2_DM2 -#define SCSI_Noise__ATN__DR CYREG_PRT2_DR -#define SCSI_Noise__ATN__INP_DIS CYREG_PRT2_INP_DIS -#define SCSI_Noise__ATN__INTTYPE CYREG_PICU2_INTTYPE0 -#define SCSI_Noise__ATN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG -#define SCSI_Noise__ATN__LCD_EN CYREG_PRT2_LCD_EN -#define SCSI_Noise__ATN__MASK 0x01u -#define SCSI_Noise__ATN__PC CYREG_PRT2_PC0 -#define SCSI_Noise__ATN__PORT 2u -#define SCSI_Noise__ATN__PRT CYREG_PRT2_PRT -#define SCSI_Noise__ATN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL -#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN -#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 -#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 -#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 -#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 -#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT -#define SCSI_Noise__ATN__PS CYREG_PRT2_PS -#define SCSI_Noise__ATN__SHIFT 0u -#define SCSI_Noise__ATN__SLW CYREG_PRT2_SLW -#define SCSI_Noise__BSY__AG CYREG_PRT6_AG -#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE -#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP -#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL -#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__BSY__DR CYREG_PRT6_DR -#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__BSY__INTTYPE CYREG_PICU6_INTTYPE3 -#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__BSY__MASK 0x08u -#define SCSI_Noise__BSY__PC CYREG_PRT6_PC3 -#define SCSI_Noise__BSY__PORT 6u -#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT -#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__BSY__PS CYREG_PRT6_PS -#define SCSI_Noise__BSY__SHIFT 3u -#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW -#define SCSI_Noise__RST__AG CYREG_PRT4_AG -#define SCSI_Noise__RST__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__RST__BIE CYREG_PRT4_BIE -#define SCSI_Noise__RST__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__RST__BYP CYREG_PRT4_BYP -#define SCSI_Noise__RST__CTL CYREG_PRT4_CTL -#define SCSI_Noise__RST__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__RST__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__RST__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__RST__DR CYREG_PRT4_DR -#define SCSI_Noise__RST__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__RST__INTTYPE CYREG_PICU4_INTTYPE7 -#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__RST__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__RST__MASK 0x80u -#define SCSI_Noise__RST__PC CYREG_PRT4_PC7 -#define SCSI_Noise__RST__PORT 4u -#define SCSI_Noise__RST__PRT CYREG_PRT4_PRT -#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__RST__PS CYREG_PRT4_PS -#define SCSI_Noise__RST__SHIFT 7u -#define SCSI_Noise__RST__SLW CYREG_PRT4_SLW -#define SCSI_Noise__SEL__AG CYREG_PRT4_AG -#define SCSI_Noise__SEL__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__SEL__BIE CYREG_PRT4_BIE -#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__SEL__BYP CYREG_PRT4_BYP -#define SCSI_Noise__SEL__CTL CYREG_PRT4_CTL -#define SCSI_Noise__SEL__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__SEL__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__SEL__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__SEL__DR CYREG_PRT4_DR -#define SCSI_Noise__SEL__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__SEL__INTTYPE CYREG_PICU4_INTTYPE3 -#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__SEL__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__SEL__MASK 0x08u -#define SCSI_Noise__SEL__PC CYREG_PRT4_PC3 -#define SCSI_Noise__SEL__PORT 4u -#define SCSI_Noise__SEL__PRT CYREG_PRT4_PRT -#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__SEL__PS CYREG_PRT4_PS -#define SCSI_Noise__SEL__SHIFT 3u -#define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW +/* USBFS */ +#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_arb_int__INTC_MASK 0x400000u +#define USBFS_arb_int__INTC_NUMBER 22u +#define USBFS_arb_int__INTC_PRIOR_NUM 6u +#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 +#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_bus_reset__INTC_MASK 0x800000u +#define USBFS_bus_reset__INTC_NUMBER 23u +#define USBFS_bus_reset__INTC_PRIOR_NUM 7u +#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 +#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7 +#define USBFS_Dm__0__MASK 0x80u +#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 +#define USBFS_Dm__0__PORT 15u +#define USBFS_Dm__0__SHIFT 7u +#define USBFS_Dm__AG CYREG_PRT15_AG +#define USBFS_Dm__AMUX CYREG_PRT15_AMUX +#define USBFS_Dm__BIE CYREG_PRT15_BIE +#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dm__BYP CYREG_PRT15_BYP +#define USBFS_Dm__CTL CYREG_PRT15_CTL +#define USBFS_Dm__DM0 CYREG_PRT15_DM0 +#define USBFS_Dm__DM1 CYREG_PRT15_DM1 +#define USBFS_Dm__DM2 CYREG_PRT15_DM2 +#define USBFS_Dm__DR CYREG_PRT15_DR +#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dm__MASK 0x80u +#define USBFS_Dm__PORT 15u +#define USBFS_Dm__PRT CYREG_PRT15_PRT +#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dm__PS CYREG_PRT15_PS +#define USBFS_Dm__SHIFT 7u +#define USBFS_Dm__SLW CYREG_PRT15_SLW +#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6 +#define USBFS_Dp__0__MASK 0x40u +#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 +#define USBFS_Dp__0__PORT 15u +#define USBFS_Dp__0__SHIFT 6u +#define USBFS_Dp__AG CYREG_PRT15_AG +#define USBFS_Dp__AMUX CYREG_PRT15_AMUX +#define USBFS_Dp__BIE CYREG_PRT15_BIE +#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dp__BYP CYREG_PRT15_BYP +#define USBFS_Dp__CTL CYREG_PRT15_CTL +#define USBFS_Dp__DM0 CYREG_PRT15_DM0 +#define USBFS_Dp__DM1 CYREG_PRT15_DM1 +#define USBFS_Dp__DM2 CYREG_PRT15_DM2 +#define USBFS_Dp__DR CYREG_PRT15_DR +#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT +#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dp__MASK 0x40u +#define USBFS_Dp__PORT 15u +#define USBFS_Dp__PRT CYREG_PRT15_PRT +#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dp__PS CYREG_PRT15_PS +#define USBFS_Dp__SHIFT 6u +#define USBFS_Dp__SLW CYREG_PRT15_SLW +#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 +#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_dp_int__INTC_MASK 0x1000u +#define USBFS_dp_int__INTC_NUMBER 12u +#define USBFS_dp_int__INTC_PRIOR_NUM 7u +#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 +#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_0__INTC_MASK 0x1000000u +#define USBFS_ep_0__INTC_NUMBER 24u +#define USBFS_ep_0__INTC_PRIOR_NUM 7u +#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 +#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_1__INTC_MASK 0x80u +#define USBFS_ep_1__INTC_NUMBER 7u +#define USBFS_ep_1__INTC_PRIOR_NUM 7u +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 +#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_2__INTC_MASK 0x100u +#define USBFS_ep_2__INTC_NUMBER 8u +#define USBFS_ep_2__INTC_PRIOR_NUM 7u +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 +#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_3__INTC_MASK 0x200u +#define USBFS_ep_3__INTC_NUMBER 9u +#define USBFS_ep_3__INTC_PRIOR_NUM 7u +#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 +#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_4__INTC_MASK 0x400u +#define USBFS_ep_4__INTC_NUMBER 10u +#define USBFS_ep_4__INTC_PRIOR_NUM 7u +#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 +#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_sof_int__INTC_MASK 0x200000u +#define USBFS_sof_int__INTC_NUMBER 21u +#define USBFS_sof_int__INTC_PRIOR_NUM 7u +#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 +#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG +#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG +#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN +#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR +#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG +#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN +#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR +#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG +#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN +#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR +#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG +#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN +#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR +#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG +#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN +#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR +#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG +#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN +#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR +#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG +#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN +#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR +#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG +#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN +#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR +#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN +#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR +#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR +#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA +#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB +#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA +#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB +#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR +#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA +#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB +#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA +#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB +#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR +#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA +#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB +#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA +#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB +#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR +#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA +#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB +#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA +#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB +#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR +#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA +#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB +#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA +#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB +#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR +#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA +#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB +#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA +#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB +#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR +#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA +#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB +#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA +#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB +#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR +#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA +#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB +#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA +#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB +#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE +#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT +#define USBFS_USB__CR0 CYREG_USB_CR0 +#define USBFS_USB__CR1 CYREG_USB_CR1 +#define USBFS_USB__CWA CYREG_USB_CWA +#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB +#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES +#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB +#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG +#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE +#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE +#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT +#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR +#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 +#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 +#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 +#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 +#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 +#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 +#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 +#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 +#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE +#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 +#define USBFS_USB__PM_ACT_MSK 0x01u +#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 +#define USBFS_USB__PM_STBY_MSK 0x01u +#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN +#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR +#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 +#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 +#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 +#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 +#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 +#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 +#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 +#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 +#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 +#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 +#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 +#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 +#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 +#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 +#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 +#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 +#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 +#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 +#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 +#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 +#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 +#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 +#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 +#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 +#define USBFS_USB__SOF0 CYREG_USB_SOF0 +#define USBFS_USB__SOF1 CYREG_USB_SOF1 +#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN +#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 +#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 /* scsiTarget */ #define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0 @@ -2798,89 +2955,6 @@ #define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL #define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB02_ST -/* Debug_Timer_Interrupt */ -#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define Debug_Timer_Interrupt__INTC_MASK 0x02u -#define Debug_Timer_Interrupt__INTC_NUMBER 1u -#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u -#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1 -#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0 -#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1 -#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0 -#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1 -#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2 -#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 -#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 -#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0 -#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1 -#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 -#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u -#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 -#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u -#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0 -#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1 -#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0 - -/* SCSI_RX_DMA */ -#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_RX_DMA__DRQ_NUMBER 0u -#define SCSI_RX_DMA__NUMBEROF_TDS 0u -#define SCSI_RX_DMA__PRIORITY 2u -#define SCSI_RX_DMA__TERMIN_EN 0u -#define SCSI_RX_DMA__TERMIN_SEL 0u -#define SCSI_RX_DMA__TERMOUT0_EN 1u -#define SCSI_RX_DMA__TERMOUT0_SEL 0u -#define SCSI_RX_DMA__TERMOUT1_EN 0u -#define SCSI_RX_DMA__TERMOUT1_SEL 0u - -/* SCSI_RX_DMA_COMPLETE */ -#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u -#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u -#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0 -#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_TX_DMA__DRQ_NUMBER 1u -#define SCSI_TX_DMA__NUMBEROF_TDS 0u -#define SCSI_TX_DMA__PRIORITY 2u -#define SCSI_TX_DMA__TERMIN_EN 0u -#define SCSI_TX_DMA__TERMIN_SEL 0u -#define SCSI_TX_DMA__TERMOUT0_EN 1u -#define SCSI_TX_DMA__TERMOUT0_SEL 1u -#define SCSI_TX_DMA__TERMOUT1_EN 0u -#define SCSI_TX_DMA__TERMOUT1_SEL 0u - -/* SCSI_TX_DMA_COMPLETE */ -#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u -#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 -#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SD_Data_Clk */ -#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 -#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 -#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 -#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u -#define SD_Data_Clk__INDEX 0x00u -#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define SD_Data_Clk__PM_ACT_MSK 0x01u -#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define SD_Data_Clk__PM_STBY_MSK 0x01u - /* timer_clock */ #define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0 #define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1 @@ -2892,148 +2966,55 @@ #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2 #define timer_clock__PM_STBY_MSK 0x04u -/* SCSI_RST_ISR */ -#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RST_ISR__INTC_MASK 0x04u -#define SCSI_RST_ISR__INTC_NUMBER 2u -#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u -#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2 -#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_SEL_ISR__INTC_MASK 0x08u -#define SCSI_SEL_ISR__INTC_NUMBER 3u -#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u -#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 -#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_Filtered */ -#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u -#define SCSI_Filtered_sts_sts_reg__0__POS 0 -#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u -#define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST -#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u -#define SCSI_Filtered_sts_sts_reg__2__POS 2 -#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u -#define SCSI_Filtered_sts_sts_reg__3__POS 3 -#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u -#define SCSI_Filtered_sts_sts_reg__4__POS 4 -#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST - -/* SCSI_CTL_PHASE */ -#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK - -/* SCSI_Glitch_Ctl */ -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK - -/* SCSI_Parity_Error */ -#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST -#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST - /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U #define BCLK__BUS_CLK__KHZ 50000U #define BCLK__BUS_CLK__MHZ 50U #define CY_PROJECT_NAME "SCSI2SD" -#define CY_VERSION "PSoC Creator 4.0 Update 1" +#define CY_VERSION "PSoC Creator 4.1" #define CYDEV_CHIP_DIE_LEOPARD 1u -#define CYDEV_CHIP_DIE_PSOC4A 12u -#define CYDEV_CHIP_DIE_PSOC5LP 19u -#define CYDEV_CHIP_DIE_PSOC5TM 20u -#define CYDEV_CHIP_DIE_TMA4 2u +#define CYDEV_CHIP_DIE_PSOC4A 16u +#define CYDEV_CHIP_DIE_PSOC5LP 2u +#define CYDEV_CHIP_DIE_PSOC5TM 3u +#define CYDEV_CHIP_DIE_TMA4 4u #define CYDEV_CHIP_DIE_UNKNOWN 0u -#define CYDEV_CHIP_FAMILY_FM0P 4u -#define CYDEV_CHIP_FAMILY_FM3 5u -#define CYDEV_CHIP_FAMILY_FM4 6u +#define CYDEV_CHIP_FAMILY_FM0P 5u +#define CYDEV_CHIP_FAMILY_FM3 6u +#define CYDEV_CHIP_FAMILY_FM4 7u #define CYDEV_CHIP_FAMILY_PSOC3 1u #define CYDEV_CHIP_FAMILY_PSOC4 2u #define CYDEV_CHIP_FAMILY_PSOC5 3u +#define CYDEV_CHIP_FAMILY_PSOC6 4u #define CYDEV_CHIP_FAMILY_UNKNOWN 0u #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 #define CYDEV_CHIP_JTAG_ID 0x2E133069u #define CYDEV_CHIP_MEMBER_3A 1u -#define CYDEV_CHIP_MEMBER_4A 12u -#define CYDEV_CHIP_MEMBER_4C 18u -#define CYDEV_CHIP_MEMBER_4D 8u -#define CYDEV_CHIP_MEMBER_4E 4u -#define CYDEV_CHIP_MEMBER_4F 13u -#define CYDEV_CHIP_MEMBER_4G 2u -#define CYDEV_CHIP_MEMBER_4H 11u -#define CYDEV_CHIP_MEMBER_4I 17u -#define CYDEV_CHIP_MEMBER_4J 9u -#define CYDEV_CHIP_MEMBER_4K 10u -#define CYDEV_CHIP_MEMBER_4L 16u -#define CYDEV_CHIP_MEMBER_4M 15u -#define CYDEV_CHIP_MEMBER_4N 6u -#define CYDEV_CHIP_MEMBER_4O 5u -#define CYDEV_CHIP_MEMBER_4P 14u -#define CYDEV_CHIP_MEMBER_4Q 7u -#define CYDEV_CHIP_MEMBER_4U 3u -#define CYDEV_CHIP_MEMBER_5A 20u -#define CYDEV_CHIP_MEMBER_5B 19u -#define CYDEV_CHIP_MEMBER_FM3 24u -#define CYDEV_CHIP_MEMBER_FM4 25u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 21u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 22u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 23u +#define CYDEV_CHIP_MEMBER_4A 16u +#define CYDEV_CHIP_MEMBER_4D 12u +#define CYDEV_CHIP_MEMBER_4E 6u +#define CYDEV_CHIP_MEMBER_4F 17u +#define CYDEV_CHIP_MEMBER_4G 4u +#define CYDEV_CHIP_MEMBER_4H 15u +#define CYDEV_CHIP_MEMBER_4I 21u +#define CYDEV_CHIP_MEMBER_4J 13u +#define CYDEV_CHIP_MEMBER_4K 14u +#define CYDEV_CHIP_MEMBER_4L 20u +#define CYDEV_CHIP_MEMBER_4M 19u +#define CYDEV_CHIP_MEMBER_4N 9u +#define CYDEV_CHIP_MEMBER_4O 7u +#define CYDEV_CHIP_MEMBER_4P 18u +#define CYDEV_CHIP_MEMBER_4Q 11u +#define CYDEV_CHIP_MEMBER_4R 8u +#define CYDEV_CHIP_MEMBER_4S 10u +#define CYDEV_CHIP_MEMBER_4U 5u +#define CYDEV_CHIP_MEMBER_5A 3u +#define CYDEV_CHIP_MEMBER_5B 2u +#define CYDEV_CHIP_MEMBER_6A 22u +#define CYDEV_CHIP_MEMBER_FM3 26u +#define CYDEV_CHIP_MEMBER_FM4 27u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 23u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 24u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 25u #define CYDEV_CHIP_MEMBER_UNKNOWN 0u #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED @@ -3058,7 +3039,6 @@ #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u #define CYDEV_CHIP_REVISION_4A_ES0 17u #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u -#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u @@ -3077,12 +3057,16 @@ #define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u #define CYDEV_CHIP_REVISION_5A_ES0 0u #define CYDEV_CHIP_REVISION_5A_ES1 1u #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u #define CYDEV_CHIP_REVISION_5B_ES0 0u #define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_6A_NO_UDB 0u +#define CYDEV_CHIP_REVISION_6A_PRODUCTION 0u #define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u #define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u #define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u @@ -3114,7 +3098,7 @@ #define CYDEV_ECC_ENABLE 0 #define CYDEV_HEAP_SIZE 0x0400 #define CYDEV_INSTRUCT_CACHE_ENABLED 1 -#define CYDEV_INTR_RISING 0x0000007Eu +#define CYDEV_INTR_RISING 0x0000007Fu #define CYDEV_IS_EXPORTING_CODE 0 #define CYDEV_IS_IMPORTING_CODE 0 #define CYDEV_PROJ_TYPE 2 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 480eb29..2e1f70d 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -1,7 +1,8 @@ + /******************************************************************************* * File Name: cyfitter_cfg.c * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file contains device initialization code. @@ -9,7 +10,7 @@ * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -55,6 +56,19 @@ #error Unsupported toolchain #endif +#ifndef CYCODE + #define CYCODE +#endif +#ifndef CYDATA + #define CYDATA +#endif +#ifndef CYFAR + #define CYFAR +#endif +#ifndef CYXDATA + #define CYXDATA +#endif + CY_CFG_UNUSED static void CYMEMZERO(void *s, size_t n); @@ -86,6 +100,7 @@ static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) #define CYCLOCKSTART_XTAL_ERROR 1u #define CYCLOCKSTART_32KHZ_ERROR 2u #define CYCLOCKSTART_PLL_ERROR 3u +#define CYCLOCKSTART_FLL_ERROR 4u #ifdef CY_NEED_CYCLOCKSTARTUPERROR @@ -109,17 +124,21 @@ static void CyClockStartupError(uint8 errorCode); CY_CFG_UNUSED static void CyClockStartupError(uint8 errorCode) { - /* To remove the compiler warning if errorCode not used. */ + /* To remove the compiler warning if errorCode not used. */ +#if defined(CY_PSOC3) && (CY_PSOC3) errorCode = errorCode; +#else + (void)errorCode; +#endif /* CY_PSOC3 */ /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ /* we will end up here to allow the customer to implement something to */ /* deal with the clock condition. */ #ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK - CY_CFG_Clock_Startup_ErrorCallback(); + CY_CFG_Clock_Startup_ErrorCallback(); #else - /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */ + /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */ /* `#START CyClockStartupError` */ /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ @@ -128,10 +147,8 @@ static void CyClockStartupError(uint8 errorCode) /* `#END` */ - /* If nothing else, stop here since the clocks have not started */ - /* correctly. */ while(1) {} -#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ +#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ } #endif @@ -170,7 +187,7 @@ static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_ baseAddr &= 0xFFFFFF00u; while (count != 0u) { - CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value); + CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); j++; count--; } @@ -205,8 +222,8 @@ static void ClockSetup(void) CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u); - CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0031u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x18u); /* Configure ILO based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); @@ -305,7 +322,7 @@ void SetAnalogRoutingPumps(uint8 enabled) CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue); } -#define CY_AMUX_UNUSED CYREG_BOOST_SR + /******************************************************************************* @@ -317,7 +334,7 @@ void SetAnalogRoutingPumps(uint8 enabled) * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * -* Parameters: +* Parameters: * void * * Return: @@ -398,44 +415,44 @@ void cyfitter_cfg(void) static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004501u, /* Base address: 0x40004500 Count: 1 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */ + 0x4000520Eu, /* Base address: 0x40005200 Count: 14 */ 0x40006401u, /* Base address: 0x40006400 Count: 1 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ 0x40010045u, /* Base address: 0x40010000 Count: 69 */ 0x4001013Du, /* Base address: 0x40010100 Count: 61 */ 0x40010247u, /* Base address: 0x40010200 Count: 71 */ - 0x40010355u, /* Base address: 0x40010300 Count: 85 */ + 0x4001035Fu, /* Base address: 0x40010300 Count: 95 */ 0x4001045Fu, /* Base address: 0x40010400 Count: 95 */ - 0x40010563u, /* Base address: 0x40010500 Count: 99 */ + 0x40010560u, /* Base address: 0x40010500 Count: 96 */ 0x40010650u, /* Base address: 0x40010600 Count: 80 */ - 0x4001074Eu, /* Base address: 0x40010700 Count: 78 */ - 0x4001090Du, /* Base address: 0x40010900 Count: 13 */ + 0x40010755u, /* Base address: 0x40010700 Count: 85 */ + 0x40010912u, /* Base address: 0x40010900 Count: 18 */ 0x40010A46u, /* Base address: 0x40010A00 Count: 70 */ - 0x40010B51u, /* Base address: 0x40010B00 Count: 81 */ + 0x40010B50u, /* Base address: 0x40010B00 Count: 80 */ 0x40010C56u, /* Base address: 0x40010C00 Count: 86 */ - 0x40010D52u, /* Base address: 0x40010D00 Count: 82 */ + 0x40010D58u, /* Base address: 0x40010D00 Count: 88 */ 0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */ 0x40010F3Bu, /* Base address: 0x40010F00 Count: 59 */ 0x4001141Fu, /* Base address: 0x40011400 Count: 31 */ - 0x4001154Fu, /* Base address: 0x40011500 Count: 79 */ + 0x40011554u, /* Base address: 0x40011500 Count: 84 */ 0x40011656u, /* Base address: 0x40011600 Count: 86 */ - 0x40011745u, /* Base address: 0x40011700 Count: 69 */ + 0x40011744u, /* Base address: 0x40011700 Count: 68 */ 0x40011804u, /* Base address: 0x40011800 Count: 4 */ - 0x4001190Au, /* Base address: 0x40011900 Count: 10 */ + 0x40011905u, /* Base address: 0x40011900 Count: 5 */ 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */ - 0x40014016u, /* Base address: 0x40014000 Count: 22 */ - 0x4001411Bu, /* Base address: 0x40014100 Count: 27 */ - 0x4001420Bu, /* Base address: 0x40014200 Count: 11 */ - 0x4001430Cu, /* Base address: 0x40014300 Count: 12 */ - 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */ - 0x4001451Du, /* Base address: 0x40014500 Count: 29 */ - 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */ - 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */ + 0x40014019u, /* Base address: 0x40014000 Count: 25 */ + 0x40014118u, /* Base address: 0x40014100 Count: 24 */ + 0x4001420Du, /* Base address: 0x40014200 Count: 13 */ + 0x4001430Du, /* Base address: 0x40014300 Count: 13 */ + 0x40014411u, /* Base address: 0x40014400 Count: 17 */ + 0x40014518u, /* Base address: 0x40014500 Count: 24 */ + 0x4001460Eu, /* Base address: 0x40014600 Count: 14 */ + 0x4001470Fu, /* Base address: 0x40014700 Count: 15 */ 0x40014809u, /* Base address: 0x40014800 Count: 9 */ - 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */ - 0x40014C07u, /* Base address: 0x40014C00 Count: 7 */ + 0x4001490Du, /* Base address: 0x40014900 Count: 13 */ + 0x40014C08u, /* Base address: 0x40014C00 Count: 8 */ 0x40014D0Bu, /* Base address: 0x40014D00 Count: 11 */ - 0x40015002u, /* Base address: 0x40015000 Count: 2 */ + 0x40015004u, /* Base address: 0x40015000 Count: 4 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; @@ -451,8 +468,11 @@ void cyfitter_cfg(void) {0x18u, 0x04u}, {0x1Cu, 0x30u}, {0x24u, 0x44u}, - {0x28u, 0x01u}, - {0x31u, 0x20u}, + {0x28u, 0x02u}, + {0x30u, 0x20u}, + {0x31u, 0x30u}, + {0x78u, 0x20u}, + {0x79u, 0x20u}, {0x7Cu, 0x40u}, {0x20u, 0x01u}, {0x85u, 0x0Fu}, @@ -460,10 +480,9 @@ void cyfitter_cfg(void) {0x04u, 0x0Fu}, {0x06u, 0xF0u}, {0x0Au, 0xFFu}, - {0x0Bu, 0x01u}, - {0x0Cu, 0x69u}, - {0x0Eu, 0x96u}, - {0x12u, 0xFFu}, + {0x0Eu, 0xFFu}, + {0x10u, 0x69u}, + {0x12u, 0x96u}, {0x14u, 0xFFu}, {0x18u, 0x55u}, {0x19u, 0x04u}, @@ -471,20 +490,21 @@ void cyfitter_cfg(void) {0x1Cu, 0xFFu}, {0x1Du, 0x01u}, {0x1Fu, 0x02u}, + {0x23u, 0x01u}, {0x28u, 0x33u}, {0x2Au, 0xCCu}, {0x2Bu, 0x02u}, {0x31u, 0x04u}, {0x32u, 0xFFu}, - {0x37u, 0x03u}, + {0x35u, 0x03u}, {0x3Au, 0x08u}, - {0x3Fu, 0x40u}, + {0x3Fu, 0x10u}, {0x40u, 0x53u}, {0x41u, 0x06u}, {0x42u, 0x40u}, {0x45u, 0xEFu}, - {0x46u, 0xD2u}, - {0x47u, 0xC0u}, + {0x46u, 0xDCu}, + {0x47u, 0x20u}, {0x48u, 0x2Fu}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, @@ -525,69 +545,68 @@ void cyfitter_cfg(void) {0xDCu, 0x10u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x28u}, - {0x02u, 0x01u}, + {0x01u, 0xA8u}, {0x03u, 0x40u}, {0x09u, 0x08u}, - {0x0Au, 0x01u}, + {0x0Au, 0x02u}, {0x0Bu, 0x44u}, {0x12u, 0x04u}, {0x19u, 0x08u}, {0x1Au, 0x10u}, - {0x21u, 0x82u}, + {0x21u, 0x02u}, + {0x22u, 0x10u}, {0x25u, 0x41u}, {0x27u, 0x18u}, {0x2Au, 0x10u}, + {0x2Bu, 0xC0u}, {0x32u, 0x80u}, {0x33u, 0x10u}, {0x34u, 0x02u}, {0x37u, 0x18u}, - {0x3Au, 0x20u}, {0x3Du, 0x82u}, {0x41u, 0x09u}, {0x48u, 0x01u}, - {0x49u, 0x20u}, + {0x49u, 0xA0u}, {0x4Au, 0x50u}, - {0x4Bu, 0x40u}, - {0x50u, 0x41u}, - {0x51u, 0x10u}, - {0x52u, 0x20u}, + {0x51u, 0x50u}, + {0x52u, 0x21u}, {0x59u, 0x10u}, {0x5Au, 0x84u}, {0x5Bu, 0x01u}, {0x5Cu, 0x40u}, + {0x60u, 0x80u}, {0x61u, 0x20u}, - {0x62u, 0x0Au}, + {0x62u, 0x08u}, {0x63u, 0x02u}, {0x64u, 0x02u}, {0x68u, 0x04u}, {0x69u, 0x45u}, {0x70u, 0x94u}, - {0x71u, 0x01u}, - {0x81u, 0x81u}, + {0x72u, 0x80u}, + {0x81u, 0x04u}, {0x82u, 0x80u}, {0x83u, 0x01u}, - {0x85u, 0x14u}, + {0x85u, 0x04u}, {0x86u, 0x10u}, {0x88u, 0x04u}, + {0x8Au, 0x10u}, {0x8Cu, 0x10u}, {0x8Du, 0x20u}, + {0x8Eu, 0x90u}, {0xC0u, 0x0Fu}, {0xC2u, 0x0Fu}, {0xC4u, 0x02u}, - {0xCAu, 0x04u}, + {0xCAu, 0x05u}, {0xCCu, 0xECu}, - {0xCEu, 0x94u}, + {0xCEu, 0x90u}, {0xD0u, 0x03u}, {0xD2u, 0x0Cu}, {0xD6u, 0x1Fu}, {0xD8u, 0x1Fu}, - {0xE0u, 0x84u}, - {0xE2u, 0x02u}, - {0xE4u, 0x03u}, - {0xE6u, 0x0Cu}, - {0x00u, 0x06u}, - {0x04u, 0x01u}, + {0xE2u, 0x82u}, + {0xE4u, 0x02u}, + {0xE6u, 0x05u}, + {0x02u, 0xFFu}, {0x08u, 0x0Bu}, {0x0Au, 0xF4u}, {0x10u, 0xE0u}, @@ -595,12 +614,13 @@ void cyfitter_cfg(void) {0x16u, 0x15u}, {0x18u, 0x40u}, {0x1Au, 0x80u}, - {0x1Cu, 0x40u}, - {0x1Eu, 0x80u}, - {0x24u, 0x11u}, - {0x26u, 0xECu}, + {0x1Cu, 0x11u}, + {0x1Eu, 0xECu}, + {0x20u, 0x40u}, + {0x22u, 0x80u}, + {0x24u, 0x01u}, {0x2Au, 0x10u}, - {0x2Eu, 0xFFu}, + {0x2Cu, 0x06u}, {0x32u, 0x3Fu}, {0x34u, 0xC0u}, {0x3Au, 0x20u}, @@ -608,48 +628,48 @@ void cyfitter_cfg(void) {0x5Bu, 0x04u}, {0x5Cu, 0x01u}, {0x5Fu, 0x01u}, - {0x80u, 0x05u}, - {0x81u, 0x01u}, - {0x82u, 0x0Au}, - {0x83u, 0x02u}, - {0x84u, 0x06u}, - {0x86u, 0x09u}, + {0x80u, 0x03u}, + {0x81u, 0x08u}, + {0x82u, 0x0Cu}, + {0x83u, 0x10u}, + {0x86u, 0xFFu}, {0x87u, 0x80u}, - {0x88u, 0x60u}, - {0x8Au, 0x90u}, + {0x88u, 0x05u}, + {0x8Au, 0x0Au}, {0x8Bu, 0x04u}, {0x8Fu, 0x9Bu}, - {0x92u, 0xFFu}, + {0x90u, 0x06u}, + {0x92u, 0x09u}, {0x93u, 0x60u}, - {0x94u, 0x03u}, {0x95u, 0x01u}, - {0x96u, 0x0Cu}, {0x97u, 0x02u}, - {0x98u, 0x50u}, - {0x9Au, 0xA0u}, - {0x9Bu, 0x1Bu}, + {0x98u, 0x60u}, + {0x99u, 0x9Bu}, + {0x9Au, 0x90u}, + {0x9Bu, 0x40u}, {0x9Cu, 0x0Fu}, {0x9Du, 0x08u}, {0x9Eu, 0xF0u}, {0x9Fu, 0x10u}, {0xA1u, 0x1Bu}, + {0xA2u, 0xFFu}, {0xA4u, 0x30u}, - {0xA5u, 0x9Bu}, + {0xA5u, 0x01u}, {0xA6u, 0xC0u}, - {0xA7u, 0x40u}, + {0xA7u, 0x02u}, {0xA8u, 0xFFu}, {0xA9u, 0x80u}, {0xABu, 0x3Bu}, - {0xADu, 0x08u}, - {0xAEu, 0xFFu}, - {0xAFu, 0x10u}, - {0xB0u, 0xFFu}, + {0xACu, 0x50u}, + {0xAEu, 0xA0u}, + {0xAFu, 0x1Bu}, {0xB1u, 0xE0u}, {0xB3u, 0x03u}, + {0xB4u, 0xFFu}, {0xB5u, 0x04u}, {0xB7u, 0x18u}, {0xBBu, 0x88u}, - {0xBEu, 0x01u}, + {0xBEu, 0x10u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, @@ -657,91 +677,101 @@ void cyfitter_cfg(void) {0xDCu, 0x10u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x04u}, - {0x01u, 0x10u}, - {0x03u, 0x80u}, - {0x04u, 0x02u}, + {0x01u, 0x04u}, + {0x03u, 0x84u}, {0x05u, 0x20u}, - {0x06u, 0x20u}, - {0x09u, 0x14u}, - {0x0Bu, 0x42u}, + {0x07u, 0x40u}, + {0x0Au, 0x48u}, + {0x0Bu, 0x02u}, {0x0Du, 0x08u}, - {0x0Eu, 0x04u}, - {0x0Fu, 0x81u}, - {0x10u, 0x02u}, + {0x0Eu, 0x05u}, + {0x0Fu, 0x80u}, + {0x11u, 0x02u}, {0x12u, 0x10u}, - {0x13u, 0x20u}, - {0x14u, 0x20u}, - {0x15u, 0x20u}, - {0x17u, 0x40u}, - {0x1Bu, 0x02u}, - {0x1Du, 0x0Cu}, + {0x13u, 0x90u}, + {0x15u, 0xA4u}, + {0x16u, 0x40u}, + {0x1Bu, 0x20u}, + {0x1Du, 0x08u}, {0x1Eu, 0x04u}, - {0x22u, 0x99u}, - {0x23u, 0x02u}, - {0x29u, 0xA4u}, + {0x22u, 0x9Au}, + {0x28u, 0x22u}, + {0x29u, 0x20u}, {0x2Bu, 0x40u}, - {0x30u, 0x20u}, - {0x32u, 0x89u}, - {0x36u, 0x02u}, - {0x37u, 0x02u}, + {0x2Cu, 0x20u}, + {0x2Fu, 0x20u}, + {0x30u, 0x10u}, + {0x32u, 0x8Au}, + {0x34u, 0x80u}, + {0x36u, 0x80u}, {0x38u, 0x28u}, {0x3Au, 0x02u}, {0x3Bu, 0x80u}, - {0x58u, 0x99u}, - {0x5Du, 0x08u}, + {0x44u, 0x10u}, + {0x45u, 0x08u}, + {0x58u, 0x01u}, + {0x59u, 0x84u}, + {0x5Bu, 0x20u}, + {0x5Cu, 0x04u}, {0x5Eu, 0xA2u}, - {0x60u, 0x02u}, - {0x61u, 0x81u}, - {0x62u, 0x05u}, - {0x63u, 0x0Cu}, + {0x60u, 0x08u}, + {0x62u, 0x04u}, + {0x63u, 0x45u}, {0x66u, 0x80u}, - {0x80u, 0x82u}, - {0x81u, 0x10u}, - {0x82u, 0x20u}, - {0x83u, 0x80u}, - {0x86u, 0x02u}, - {0x88u, 0x08u}, - {0x8Bu, 0x40u}, - {0x90u, 0x8Au}, - {0x91u, 0x71u}, + {0x79u, 0x80u}, + {0x7Bu, 0x02u}, + {0x81u, 0x81u}, + {0x82u, 0x02u}, + {0x84u, 0x20u}, + {0x88u, 0x40u}, + {0x89u, 0x44u}, + {0x8Bu, 0x10u}, + {0x8Cu, 0x04u}, + {0x8Eu, 0x21u}, + {0x8Fu, 0x02u}, + {0x90u, 0x08u}, + {0x91u, 0xE1u}, {0x92u, 0x10u}, {0x93u, 0x02u}, {0x95u, 0x02u}, - {0x96u, 0x85u}, - {0x97u, 0x04u}, - {0x98u, 0x11u}, - {0x9Au, 0x10u}, - {0x9Bu, 0x10u}, + {0x96u, 0x86u}, + {0x97u, 0x44u}, + {0x98u, 0x01u}, + {0x99u, 0x04u}, + {0x9Au, 0x11u}, + {0x9Bu, 0x30u}, + {0x9Cu, 0x80u}, {0x9Du, 0x30u}, - {0x9Eu, 0x05u}, + {0x9Eu, 0x04u}, {0x9Fu, 0x41u}, {0xA0u, 0x80u}, - {0xA1u, 0x04u}, {0xA2u, 0x70u}, + {0xA3u, 0x80u}, {0xA4u, 0x01u}, {0xA5u, 0x28u}, - {0xA6u, 0x0Au}, + {0xA6u, 0x08u}, {0xA7u, 0x01u}, - {0xA9u, 0x06u}, - {0xAAu, 0x20u}, - {0xAEu, 0x50u}, - {0xB0u, 0x11u}, + {0xA9u, 0x02u}, + {0xABu, 0x40u}, + {0xACu, 0x01u}, + {0xAEu, 0x40u}, + {0xAFu, 0x20u}, + {0xB0u, 0x01u}, {0xB4u, 0x40u}, {0xB5u, 0x08u}, - {0xC0u, 0x7Eu}, - {0xC2u, 0xFFu}, - {0xC4u, 0xE7u}, + {0xC0u, 0x5Eu}, + {0xC2u, 0xFBu}, + {0xC4u, 0xFFu}, {0xCAu, 0x0Fu}, {0xCCu, 0x0Fu}, {0xCEu, 0x0Fu}, {0xD6u, 0xFFu}, {0xD8u, 0x1Fu}, - {0xE0u, 0x04u}, - {0xE2u, 0x01u}, - {0xE6u, 0x2Du}, + {0xE2u, 0x24u}, + {0xE6u, 0x0Du}, {0xE8u, 0x40u}, - {0xEAu, 0x04u}, + {0xEAu, 0x06u}, + {0xECu, 0x08u}, {0x01u, 0x40u}, {0x02u, 0x24u}, {0x03u, 0x80u}, @@ -752,12 +782,12 @@ void cyfitter_cfg(void) {0x09u, 0x04u}, {0x0Au, 0x09u}, {0x0Bu, 0x08u}, - {0x0Du, 0x80u}, + {0x0Du, 0x01u}, {0x0Eu, 0x20u}, - {0x0Fu, 0x7Fu}, - {0x11u, 0x01u}, + {0x0Fu, 0x02u}, + {0x11u, 0x3Fu}, {0x12u, 0x18u}, - {0x13u, 0x02u}, + {0x13u, 0x40u}, {0x14u, 0x24u}, {0x15u, 0x3Fu}, {0x16u, 0x12u}, @@ -765,17 +795,17 @@ void cyfitter_cfg(void) {0x19u, 0x01u}, {0x1Au, 0x03u}, {0x1Bu, 0x02u}, - {0x1Du, 0x10u}, {0x1Eu, 0x80u}, - {0x1Fu, 0x20u}, - {0x21u, 0x3Fu}, + {0x1Fu, 0x7Fu}, + {0x21u, 0x10u}, {0x22u, 0x04u}, - {0x23u, 0x40u}, + {0x23u, 0x20u}, {0x25u, 0x80u}, {0x27u, 0x7Fu}, {0x29u, 0x10u}, {0x2Bu, 0x20u}, {0x2Cu, 0x40u}, + {0x2Du, 0x80u}, {0x2Eu, 0x80u}, {0x2Fu, 0x7Fu}, {0x30u, 0x38u}, @@ -794,42 +824,42 @@ void cyfitter_cfg(void) {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x64u}, - {0x84u, 0x78u}, + {0x82u, 0x7Fu}, {0x85u, 0x0Fu}, - {0x86u, 0x03u}, {0x88u, 0x20u}, {0x89u, 0x05u}, {0x8Au, 0x40u}, {0x8Bu, 0x0Au}, {0x8Eu, 0x08u}, - {0x91u, 0xA0u}, - {0x93u, 0x4Fu}, + {0x90u, 0x64u}, + {0x94u, 0x78u}, {0x95u, 0x06u}, + {0x96u, 0x03u}, {0x97u, 0x09u}, {0x98u, 0x02u}, - {0x9Bu, 0x80u}, + {0x99u, 0x90u}, + {0x9Bu, 0x2Fu}, {0x9Cu, 0x03u}, {0x9Eu, 0x74u}, {0x9Fu, 0x70u}, - {0xA0u, 0x20u}, {0xA1u, 0xC0u}, - {0xA2u, 0x40u}, {0xA3u, 0x1Fu}, {0xA5u, 0x03u}, {0xA6u, 0x01u}, {0xA7u, 0x0Cu}, {0xA8u, 0x01u}, - {0xA9u, 0x90u}, + {0xA9u, 0xA0u}, {0xAAu, 0x6Eu}, - {0xABu, 0x2Fu}, - {0xAEu, 0x7Fu}, + {0xABu, 0x4Fu}, + {0xACu, 0x20u}, + {0xAEu, 0x40u}, + {0xAFu, 0x80u}, {0xB1u, 0x7Fu}, {0xB4u, 0x60u}, + {0xB5u, 0x80u}, {0xB6u, 0x1Fu}, - {0xB7u, 0x80u}, {0xBAu, 0x20u}, - {0xBFu, 0x40u}, + {0xBFu, 0x10u}, {0xD4u, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, @@ -840,117 +870,114 @@ void cyfitter_cfg(void) {0x00u, 0x02u}, {0x01u, 0x60u}, {0x03u, 0x20u}, - {0x04u, 0x81u}, - {0x05u, 0x14u}, - {0x09u, 0x88u}, + {0x04u, 0x80u}, + {0x05u, 0x10u}, + {0x06u, 0x01u}, + {0x07u, 0x40u}, + {0x09u, 0x08u}, {0x0Au, 0x48u}, - {0x0Du, 0x10u}, - {0x0Eu, 0x02u}, + {0x0Bu, 0x01u}, + {0x0Du, 0x18u}, + {0x0Eu, 0x01u}, + {0x0Fu, 0x80u}, {0x10u, 0x82u}, - {0x14u, 0x01u}, - {0x16u, 0x68u}, - {0x17u, 0x40u}, - {0x18u, 0x01u}, - {0x1Au, 0x49u}, - {0x1Bu, 0x50u}, + {0x14u, 0x02u}, + {0x15u, 0x04u}, + {0x16u, 0x08u}, + {0x18u, 0x09u}, + {0x1Au, 0x4Au}, + {0x1Bu, 0x40u}, {0x1Cu, 0x02u}, - {0x1Du, 0x10u}, - {0x1Eu, 0x02u}, + {0x1Du, 0x50u}, + {0x1Eu, 0x01u}, {0x1Fu, 0x40u}, {0x21u, 0x21u}, {0x22u, 0x40u}, {0x23u, 0x30u}, - {0x25u, 0x40u}, + {0x25u, 0x10u}, {0x27u, 0x80u}, - {0x28u, 0x01u}, + {0x28u, 0x80u}, + {0x29u, 0x40u}, {0x2Au, 0x18u}, - {0x2Bu, 0x40u}, - {0x2Du, 0x20u}, {0x2Eu, 0x04u}, - {0x2Fu, 0x40u}, - {0x31u, 0x25u}, - {0x32u, 0x40u}, - {0x34u, 0x20u}, - {0x36u, 0x02u}, + {0x2Fu, 0x4Au}, + {0x31u, 0x28u}, + {0x32u, 0x01u}, + {0x33u, 0x48u}, + {0x35u, 0x20u}, {0x37u, 0x88u}, {0x39u, 0x02u}, {0x3Au, 0x04u}, - {0x3Bu, 0x90u}, - {0x3Du, 0x88u}, - {0x3Eu, 0x90u}, - {0x59u, 0x80u}, + {0x3Bu, 0x50u}, + {0x3Du, 0x04u}, + {0x3Eu, 0x10u}, + {0x58u, 0x40u}, {0x5Fu, 0x80u}, - {0x63u, 0x01u}, + {0x62u, 0x40u}, {0x68u, 0x02u}, - {0x78u, 0x10u}, - {0x7Bu, 0x04u}, - {0x80u, 0x20u}, - {0x83u, 0x50u}, - {0x85u, 0x08u}, - {0x86u, 0x02u}, - {0x87u, 0x60u}, - {0x89u, 0xA0u}, + {0x83u, 0x14u}, + {0x87u, 0x20u}, + {0x88u, 0x01u}, + {0x89u, 0x20u}, {0x8Au, 0x08u}, - {0x90u, 0x82u}, + {0x8Cu, 0x24u}, {0x91u, 0x61u}, {0x92u, 0x30u}, + {0x93u, 0x41u}, {0x94u, 0x20u}, - {0x95u, 0x02u}, - {0x96u, 0xC1u}, - {0x97u, 0x81u}, - {0x98u, 0x02u}, - {0x99u, 0x05u}, - {0x9Au, 0x04u}, - {0x9Bu, 0x10u}, + {0x95u, 0x06u}, + {0x96u, 0xC3u}, + {0x97u, 0x80u}, + {0x98u, 0x48u}, + {0x9Au, 0x05u}, + {0x9Bu, 0x50u}, {0x9Du, 0x30u}, - {0x9Eu, 0xA0u}, - {0x9Fu, 0x41u}, - {0xA0u, 0x80u}, - {0xA1u, 0x88u}, + {0x9Eu, 0x40u}, + {0x9Fu, 0x05u}, + {0xA0u, 0xA0u}, + {0xA1u, 0x48u}, {0xA2u, 0x20u}, - {0xA3u, 0x06u}, + {0xA3u, 0x02u}, {0xA4u, 0x01u}, - {0xA5u, 0x20u}, - {0xA7u, 0x51u}, - {0xA8u, 0x04u}, - {0xAAu, 0x61u}, - {0xACu, 0x20u}, - {0xAEu, 0x01u}, - {0xB0u, 0x21u}, - {0xB1u, 0x80u}, - {0xB4u, 0x01u}, - {0xB5u, 0x08u}, - {0xB7u, 0x30u}, - {0xC0u, 0xFFu}, - {0xC2u, 0xCFu}, - {0xC4u, 0xF9u}, - {0xCAu, 0xEFu}, - {0xCCu, 0xFFu}, + {0xA5u, 0x30u}, + {0xA7u, 0x41u}, + {0xA8u, 0x02u}, + {0xAAu, 0x42u}, + {0xABu, 0x40u}, + {0xAEu, 0x04u}, + {0xAFu, 0x80u}, + {0xB5u, 0x10u}, + {0xB6u, 0x80u}, + {0xC0u, 0xDFu}, + {0xC2u, 0xFFu}, + {0xC4u, 0xE9u}, + {0xCAu, 0xFFu}, + {0xCCu, 0x7Fu}, {0xCEu, 0x6Fu}, {0xD6u, 0x18u}, {0xD8u, 0x08u}, - {0xE0u, 0x06u}, + {0xE0u, 0x04u}, {0xE2u, 0x01u}, {0xE4u, 0x08u}, - {0xE6u, 0x43u}, - {0xE8u, 0x04u}, - {0xEAu, 0x02u}, - {0xECu, 0x02u}, + {0xE8u, 0x05u}, + {0xEAu, 0x12u}, + {0xECu, 0x80u}, + {0xEEu, 0x09u}, {0x00u, 0x55u}, {0x02u, 0xAAu}, - {0x04u, 0xFFu}, {0x0Au, 0xFFu}, {0x0Eu, 0xFFu}, {0x0Fu, 0x12u}, {0x10u, 0xFFu}, {0x13u, 0x01u}, + {0x14u, 0xFFu}, {0x17u, 0x0Cu}, {0x18u, 0x0Fu}, {0x19u, 0x24u}, {0x1Au, 0xF0u}, {0x1Bu, 0x03u}, - {0x1Cu, 0x69u}, - {0x1Eu, 0x96u}, + {0x20u, 0x69u}, + {0x22u, 0x96u}, {0x24u, 0x33u}, {0x25u, 0x28u}, {0x26u, 0xCCu}, @@ -959,11 +986,11 @@ void cyfitter_cfg(void) {0x2Bu, 0x02u}, {0x2Eu, 0xFFu}, {0x31u, 0x10u}, + {0x33u, 0x20u}, {0x34u, 0xFFu}, {0x35u, 0x0Fu}, - {0x37u, 0x20u}, {0x3Au, 0x20u}, - {0x3Fu, 0x40u}, + {0x3Fu, 0x04u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, @@ -974,22 +1001,22 @@ void cyfitter_cfg(void) {0x83u, 0x40u}, {0x84u, 0x01u}, {0x86u, 0x02u}, - {0x87u, 0x30u}, - {0x88u, 0x02u}, - {0x8Au, 0x01u}, {0x8Bu, 0x80u}, - {0x8Cu, 0x10u}, + {0x8Cu, 0x02u}, + {0x8Eu, 0x01u}, {0x8Fu, 0x01u}, - {0x90u, 0x02u}, {0x91u, 0x03u}, - {0x92u, 0x05u}, {0x93u, 0x0Cu}, {0x94u, 0x02u}, {0x96u, 0x01u}, + {0x97u, 0x30u}, {0x98u, 0x10u}, {0x99u, 0x02u}, + {0x9Cu, 0x10u}, {0x9Fu, 0x07u}, + {0xA0u, 0x02u}, {0xA1u, 0x04u}, + {0xA2u, 0x05u}, {0xA4u, 0x10u}, {0xA5u, 0x4Du}, {0xA7u, 0x22u}, @@ -1016,116 +1043,128 @@ void cyfitter_cfg(void) {0xDCu, 0x11u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x02u}, - {0x03u, 0x2Au}, - {0x05u, 0xA4u}, - {0x06u, 0x42u}, - {0x08u, 0x22u}, + {0x01u, 0x82u}, + {0x03u, 0x20u}, + {0x04u, 0x01u}, + {0x05u, 0x60u}, + {0x08u, 0x20u}, + {0x09u, 0x40u}, {0x0Au, 0x20u}, + {0x0Cu, 0x04u}, + {0x0Du, 0x08u}, {0x0Eu, 0x04u}, - {0x0Fu, 0x81u}, + {0x0Fu, 0xA0u}, {0x10u, 0x20u}, - {0x13u, 0x40u}, - {0x14u, 0x01u}, - {0x16u, 0x90u}, - {0x17u, 0x42u}, + {0x11u, 0x40u}, + {0x13u, 0x01u}, + {0x16u, 0x50u}, + {0x17u, 0x40u}, {0x18u, 0x20u}, - {0x19u, 0x42u}, - {0x1Bu, 0x28u}, + {0x19u, 0x02u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x20u}, {0x1Eu, 0x04u}, {0x20u, 0x08u}, - {0x21u, 0x06u}, + {0x21u, 0x02u}, + {0x22u, 0x04u}, {0x26u, 0x02u}, - {0x27u, 0x0Au}, - {0x29u, 0xA4u}, - {0x2Au, 0x04u}, - {0x2Bu, 0x40u}, - {0x2Fu, 0x14u}, + {0x27u, 0x28u}, + {0x29u, 0x60u}, + {0x2Bu, 0x50u}, + {0x2Fu, 0x18u}, {0x31u, 0x02u}, - {0x32u, 0x20u}, + {0x32u, 0x24u}, {0x33u, 0x40u}, {0x35u, 0x08u}, {0x36u, 0x02u}, {0x37u, 0x18u}, {0x38u, 0x80u}, - {0x39u, 0x19u}, - {0x3Cu, 0x82u}, - {0x3Du, 0x02u}, - {0x3Eu, 0x02u}, - {0x45u, 0x04u}, - {0x46u, 0x20u}, + {0x39u, 0x11u}, + {0x3Cu, 0x80u}, + {0x49u, 0x40u}, + {0x4Bu, 0x80u}, {0x58u, 0x40u}, - {0x5Bu, 0x20u}, - {0x62u, 0x50u}, - {0x6Du, 0x08u}, + {0x59u, 0x10u}, + {0x60u, 0x03u}, + {0x62u, 0x10u}, + {0x6Du, 0x04u}, {0x6Eu, 0x60u}, - {0x80u, 0x20u}, - {0x81u, 0x02u}, - {0x82u, 0x01u}, - {0x86u, 0x10u}, - {0x90u, 0x81u}, + {0x80u, 0x10u}, + {0x81u, 0xC2u}, + {0x86u, 0x11u}, + {0x8Au, 0x04u}, + {0x8Du, 0x10u}, + {0x90u, 0x80u}, {0x91u, 0x11u}, - {0x92u, 0x20u}, - {0x93u, 0x41u}, + {0x92u, 0x22u}, + {0x93u, 0x81u}, {0x94u, 0x20u}, + {0x95u, 0x04u}, {0x96u, 0x04u}, - {0x98u, 0x12u}, - {0x99u, 0x04u}, + {0x98u, 0x28u}, + {0x9Au, 0x40u}, {0x9Bu, 0x40u}, + {0x9Cu, 0x02u}, {0x9Du, 0x20u}, - {0x9Eu, 0x70u}, - {0xA0u, 0x21u}, + {0x9Eu, 0x10u}, + {0xA0u, 0x20u}, + {0xA1u, 0x48u}, {0xA2u, 0x20u}, - {0xA3u, 0x42u}, - {0xA5u, 0x04u}, + {0xA3u, 0x40u}, {0xA7u, 0x21u}, - {0xA8u, 0x21u}, + {0xA8u, 0x80u}, + {0xAAu, 0x40u}, {0xAFu, 0x29u}, - {0xB1u, 0x10u}, + {0xB1u, 0x18u}, {0xB4u, 0x01u}, - {0xC0u, 0xFFu}, - {0xC2u, 0xDEu}, - {0xC4u, 0xA5u}, + {0xC0u, 0xDDu}, + {0xC2u, 0x77u}, + {0xC4u, 0xBDu}, {0xCAu, 0x6Fu}, - {0xCCu, 0xEDu}, - {0xCEu, 0x1Fu}, + {0xCCu, 0xEFu}, + {0xCEu, 0x1Du}, {0xD6u, 0x0Cu}, {0xD8u, 0x0Cu}, - {0xE6u, 0x04u}, + {0xE0u, 0x08u}, + {0xE6u, 0x05u}, {0xEAu, 0x09u}, - {0xEEu, 0x20u}, - {0x83u, 0x01u}, - {0x90u, 0x80u}, - {0x93u, 0x02u}, - {0xA6u, 0x08u}, + {0x82u, 0x80u}, + {0x89u, 0x08u}, + {0x9Du, 0x08u}, + {0xA2u, 0x80u}, {0xA7u, 0x08u}, {0xADu, 0x08u}, + {0xAEu, 0x04u}, {0xAFu, 0x92u}, - {0xB2u, 0x10u}, + {0xB1u, 0x20u}, + {0xB2u, 0x14u}, + {0xB3u, 0x02u}, {0xB4u, 0x80u}, - {0xB6u, 0x80u}, + {0xB7u, 0x20u}, + {0xE0u, 0x88u}, + {0xE2u, 0x40u}, + {0xE6u, 0x01u}, {0xEAu, 0x81u}, - {0xECu, 0x10u}, - {0xEEu, 0x20u}, - {0x02u, 0x20u}, + {0xECu, 0x38u}, + {0x02u, 0x04u}, {0x05u, 0x08u}, + {0x06u, 0x08u}, {0x07u, 0x05u}, - {0x0Au, 0x40u}, {0x0Cu, 0x2Au}, {0x0Du, 0x08u}, {0x0Eu, 0x54u}, {0x0Fu, 0x04u}, {0x12u, 0x01u}, {0x15u, 0x04u}, - {0x16u, 0x04u}, + {0x16u, 0x02u}, {0x17u, 0x08u}, {0x19u, 0x08u}, + {0x1Au, 0x40u}, {0x1Bu, 0x06u}, {0x1Du, 0x08u}, + {0x1Eu, 0x20u}, {0x1Fu, 0x14u}, {0x22u, 0x10u}, - {0x26u, 0x02u}, - {0x2Au, 0x08u}, {0x30u, 0x06u}, {0x31u, 0x02u}, {0x32u, 0x01u}, @@ -1143,7 +1182,7 @@ void cyfitter_cfg(void) {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0xFFu}, + {0x84u, 0xFFu}, {0x89u, 0x04u}, {0x8Au, 0xFFu}, {0x8Bu, 0x03u}, @@ -1177,132 +1216,132 @@ void cyfitter_cfg(void) {0xDBu, 0x04u}, {0xDCu, 0x11u}, {0xDFu, 0x01u}, - {0x01u, 0x42u}, - {0x03u, 0x04u}, + {0x00u, 0x02u}, + {0x01u, 0x48u}, {0x05u, 0x20u}, - {0x06u, 0x80u}, - {0x08u, 0x04u}, + {0x07u, 0x20u}, + {0x09u, 0x04u}, {0x0Au, 0x80u}, + {0x0Bu, 0x05u}, {0x0Eu, 0x04u}, {0x0Fu, 0x12u}, {0x10u, 0x80u}, - {0x11u, 0x08u}, - {0x12u, 0x08u}, - {0x14u, 0x0Au}, - {0x15u, 0x04u}, + {0x14u, 0x02u}, + {0x15u, 0x14u}, {0x16u, 0x40u}, - {0x18u, 0x89u}, - {0x1Au, 0x20u}, + {0x19u, 0x01u}, + {0x1Au, 0x28u}, + {0x1Bu, 0x80u}, {0x1Fu, 0x02u}, {0x20u, 0x40u}, {0x21u, 0x88u}, {0x22u, 0x20u}, {0x24u, 0x10u}, - {0x26u, 0x14u}, + {0x26u, 0x18u}, {0x27u, 0x01u}, {0x2Fu, 0x08u}, {0x31u, 0x88u}, {0x32u, 0x20u}, - {0x36u, 0x14u}, + {0x36u, 0x18u}, {0x37u, 0x01u}, {0x38u, 0x44u}, {0x3Fu, 0x20u}, - {0x58u, 0x90u}, - {0x59u, 0x04u}, + {0x58u, 0x94u}, {0x5Cu, 0x10u}, {0x5Fu, 0x8Au}, {0x60u, 0x04u}, {0x62u, 0x40u}, {0x63u, 0x20u}, {0x65u, 0x40u}, - {0x81u, 0x30u}, - {0x83u, 0x0Au}, - {0x84u, 0x04u}, + {0x80u, 0x40u}, + {0x83u, 0x89u}, {0x85u, 0x40u}, - {0x86u, 0x04u}, - {0x89u, 0x04u}, - {0x8Cu, 0x01u}, + {0x88u, 0x04u}, + {0x89u, 0x14u}, + {0x8Du, 0x15u}, + {0x90u, 0x80u}, {0x91u, 0x40u}, {0x92u, 0x80u}, - {0x93u, 0x02u}, - {0x94u, 0x08u}, + {0x93u, 0x04u}, {0x96u, 0x20u}, - {0x98u, 0x1Eu}, - {0x99u, 0x26u}, - {0x9Bu, 0x04u}, - {0xA0u, 0x84u}, - {0xA1u, 0x14u}, + {0x98u, 0x12u}, + {0x99u, 0x30u}, + {0x9Du, 0x0Cu}, + {0xA0u, 0x81u}, + {0xA1u, 0x04u}, + {0xA2u, 0x80u}, {0xA3u, 0x01u}, - {0xA6u, 0x08u}, - {0xA9u, 0x04u}, - {0xABu, 0xC0u}, - {0xACu, 0x80u}, - {0xAEu, 0x04u}, - {0xAFu, 0x10u}, - {0xB0u, 0x18u}, - {0xB2u, 0x40u}, - {0xB3u, 0x24u}, + {0xA8u, 0x01u}, + {0xA9u, 0x24u}, + {0xAAu, 0x04u}, + {0xABu, 0x41u}, + {0xACu, 0x01u}, + {0xADu, 0x10u}, + {0xAFu, 0x80u}, + {0xB0u, 0x10u}, + {0xB2u, 0x02u}, + {0xB3u, 0x10u}, {0xB4u, 0x40u}, - {0xB5u, 0x08u}, {0xB6u, 0x20u}, - {0xC0u, 0x5Bu}, - {0xC2u, 0xECu}, - {0xC4u, 0xFEu}, + {0xC0u, 0x6Du}, + {0xC2u, 0xEFu}, + {0xC4u, 0xF8u}, {0xCAu, 0x20u}, {0xCCu, 0xEEu}, {0xCEu, 0x2Au}, {0xD6u, 0xFEu}, {0xD8u, 0x1Eu}, - {0xE0u, 0x20u}, - {0xE6u, 0xC0u}, - {0xE8u, 0x90u}, - {0xECu, 0x04u}, - {0xEEu, 0x90u}, - {0x00u, 0x05u}, - {0x02u, 0x0Au}, + {0xE0u, 0xB0u}, + {0xE2u, 0x40u}, + {0xE4u, 0x04u}, + {0xEAu, 0x10u}, + {0xECu, 0x84u}, + {0x01u, 0xFFu}, {0x04u, 0x03u}, - {0x05u, 0x30u}, + {0x05u, 0x03u}, {0x06u, 0x0Cu}, - {0x07u, 0xC0u}, + {0x07u, 0x0Cu}, + {0x09u, 0x30u}, {0x0Au, 0xFFu}, - {0x0Bu, 0xFFu}, - {0x0Cu, 0x0Fu}, + {0x0Bu, 0xC0u}, + {0x0Cu, 0x05u}, {0x0Du, 0x06u}, - {0x0Eu, 0xF0u}, + {0x0Eu, 0x0Au}, {0x0Fu, 0x09u}, {0x10u, 0x09u}, - {0x11u, 0x05u}, {0x12u, 0x06u}, - {0x13u, 0x0Au}, {0x14u, 0x90u}, - {0x15u, 0x50u}, {0x16u, 0x60u}, - {0x17u, 0xA0u}, - {0x19u, 0x60u}, - {0x1Au, 0xFFu}, - {0x1Bu, 0x90u}, - {0x21u, 0xFFu}, - {0x22u, 0xFFu}, - {0x24u, 0x50u}, - {0x26u, 0xA0u}, - {0x27u, 0xFFu}, + {0x17u, 0xFFu}, + {0x18u, 0x50u}, + {0x1Au, 0xA0u}, + {0x1Bu, 0xFFu}, + {0x1Du, 0x0Fu}, + {0x1Eu, 0xFFu}, + {0x1Fu, 0xF0u}, + {0x20u, 0x0Fu}, + {0x21u, 0x60u}, + {0x22u, 0xF0u}, + {0x23u, 0x90u}, + {0x25u, 0x50u}, + {0x26u, 0xFFu}, + {0x27u, 0xA0u}, {0x28u, 0x30u}, - {0x29u, 0x03u}, {0x2Au, 0xC0u}, - {0x2Bu, 0x0Cu}, - {0x2Du, 0x0Fu}, - {0x2Fu, 0xF0u}, - {0x34u, 0xFFu}, - {0x35u, 0xFFu}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x10u}, + {0x2Du, 0x05u}, + {0x2Fu, 0x0Au}, + {0x30u, 0xFFu}, + {0x37u, 0xFFu}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x40u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x86u, 0x02u}, + {0x81u, 0x08u}, + {0x83u, 0x50u}, {0x88u, 0x20u}, {0x8Au, 0x10u}, {0x8Cu, 0x01u}, @@ -1312,31 +1351,30 @@ void cyfitter_cfg(void) {0x92u, 0x10u}, {0x93u, 0x58u}, {0x94u, 0x20u}, - {0x95u, 0x04u}, + {0x95u, 0x02u}, {0x96u, 0x18u}, - {0x97u, 0x02u}, + {0x97u, 0x24u}, {0x98u, 0x10u}, - {0x99u, 0x02u}, {0x9Au, 0x20u}, - {0x9Bu, 0x24u}, {0x9Du, 0x10u}, {0x9Eu, 0x01u}, {0x9Fu, 0x08u}, - {0xA1u, 0x08u}, - {0xA3u, 0x50u}, {0xA4u, 0x20u}, + {0xA5u, 0x04u}, {0xA6u, 0x14u}, + {0xA7u, 0x02u}, {0xA9u, 0x01u}, + {0xAAu, 0x02u}, {0xB0u, 0x04u}, - {0xB1u, 0x01u}, + {0xB1u, 0x60u}, {0xB2u, 0x08u}, {0xB3u, 0x1Eu}, {0xB4u, 0x30u}, - {0xB5u, 0x60u}, + {0xB5u, 0x01u}, {0xB6u, 0x03u}, {0xBAu, 0x20u}, {0xBEu, 0x40u}, - {0xBFu, 0x14u}, + {0xBFu, 0x05u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, @@ -1344,99 +1382,105 @@ void cyfitter_cfg(void) {0xDCu, 0x91u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x04u}, {0x03u, 0x09u}, - {0x04u, 0x10u}, - {0x05u, 0x02u}, - {0x06u, 0x20u}, - {0x07u, 0x11u}, - {0x08u, 0x80u}, - {0x0Au, 0xA4u}, - {0x0Cu, 0x24u}, - {0x0Du, 0x20u}, - {0x0Eu, 0x20u}, - {0x0Fu, 0x80u}, + {0x04u, 0x84u}, + {0x05u, 0x80u}, + {0x06u, 0x08u}, + {0x07u, 0x14u}, + {0x0Au, 0xA8u}, + {0x0Bu, 0x01u}, + {0x0Cu, 0x20u}, + {0x0Du, 0x90u}, + {0x0Eu, 0x21u}, + {0x0Fu, 0x84u}, + {0x10u, 0x08u}, {0x12u, 0x10u}, - {0x15u, 0x03u}, - {0x16u, 0x08u}, - {0x17u, 0x24u}, + {0x14u, 0x20u}, + {0x15u, 0x18u}, + {0x17u, 0x21u}, + {0x18u, 0x02u}, {0x19u, 0x20u}, - {0x1Au, 0x84u}, - {0x1Bu, 0x88u}, - {0x1Cu, 0x08u}, - {0x20u, 0x90u}, - {0x21u, 0x08u}, - {0x23u, 0x04u}, - {0x25u, 0x10u}, - {0x29u, 0x20u}, - {0x2Au, 0x02u}, + {0x1Au, 0x88u}, + {0x1Bu, 0x08u}, + {0x1Cu, 0x80u}, + {0x21u, 0x04u}, + {0x22u, 0x22u}, + {0x26u, 0x80u}, + {0x29u, 0x28u}, {0x2Cu, 0x20u}, - {0x2Du, 0x41u}, - {0x2Eu, 0x20u}, + {0x2Du, 0x80u}, + {0x2Fu, 0x80u}, {0x30u, 0x80u}, - {0x32u, 0x28u}, - {0x33u, 0x41u}, - {0x35u, 0x02u}, - {0x36u, 0x10u}, + {0x31u, 0x04u}, + {0x33u, 0x01u}, + {0x34u, 0x20u}, + {0x36u, 0x40u}, {0x37u, 0x04u}, - {0x3Cu, 0x10u}, - {0x3Eu, 0x08u}, + {0x3Au, 0x02u}, + {0x3Cu, 0x04u}, + {0x3Du, 0x10u}, + {0x3Eu, 0x01u}, {0x3Fu, 0x80u}, - {0x59u, 0x80u}, + {0x5Bu, 0x80u}, {0x5Cu, 0x40u}, - {0x5Du, 0x10u}, + {0x5Fu, 0x10u}, {0x63u, 0x02u}, {0x64u, 0x02u}, - {0x66u, 0x50u}, + {0x66u, 0x10u}, + {0x67u, 0x02u}, {0x6Du, 0x40u}, + {0x6Eu, 0x80u}, {0x6Fu, 0x01u}, - {0x81u, 0x22u}, - {0x83u, 0x04u}, + {0x81u, 0x80u}, + {0x83u, 0x81u}, {0x87u, 0x01u}, {0x88u, 0x40u}, - {0x89u, 0x01u}, - {0x8Cu, 0x04u}, - {0x8Du, 0x80u}, - {0x91u, 0x16u}, - {0x93u, 0x02u}, - {0x95u, 0x40u}, - {0x97u, 0x20u}, - {0x99u, 0x06u}, + {0x89u, 0x04u}, + {0x8Au, 0x08u}, + {0x8Eu, 0x08u}, + {0x8Fu, 0x10u}, + {0x90u, 0x80u}, + {0x91u, 0x20u}, + {0x95u, 0x48u}, + {0x99u, 0x10u}, {0x9Au, 0x02u}, - {0x9Bu, 0x74u}, - {0x9Cu, 0x08u}, + {0x9Bu, 0x30u}, + {0x9Eu, 0x04u}, + {0xA0u, 0x89u}, + {0xA1u, 0x80u}, {0xA2u, 0x10u}, - {0xA5u, 0x28u}, - {0xA7u, 0x60u}, - {0xA9u, 0x04u}, - {0xAAu, 0x10u}, + {0xA7u, 0x50u}, + {0xA8u, 0x01u}, {0xABu, 0x10u}, + {0xACu, 0x08u}, + {0xAFu, 0x20u}, {0xB7u, 0x01u}, - {0xC0u, 0xF7u}, - {0xC2u, 0x7Fu}, - {0xC4u, 0x74u}, - {0xCAu, 0xF5u}, - {0xCCu, 0xEFu}, - {0xCEu, 0x70u}, + {0xC0u, 0xE3u}, + {0xC2u, 0xFFu}, + {0xC4u, 0x76u}, + {0xCAu, 0xD6u}, + {0xCCu, 0x7Bu}, + {0xCEu, 0xF1u}, {0xD6u, 0x38u}, {0xD8u, 0x38u}, - {0xE2u, 0xA0u}, - {0xE6u, 0x21u}, + {0xE0u, 0x20u}, + {0xE2u, 0x85u}, + {0xE6u, 0xA0u}, {0xE8u, 0x01u}, - {0xEAu, 0x20u}, + {0xEAu, 0x02u}, {0xECu, 0x10u}, - {0xEEu, 0x21u}, - {0x02u, 0x03u}, + {0xEEu, 0x20u}, + {0x00u, 0x24u}, + {0x02u, 0x09u}, {0x05u, 0x50u}, {0x06u, 0x58u}, {0x07u, 0xA0u}, - {0x09u, 0x05u}, - {0x0Bu, 0x0Au}, + {0x09u, 0x60u}, + {0x0Bu, 0x90u}, {0x0Du, 0x0Fu}, {0x0Fu, 0xF0u}, - {0x10u, 0x24u}, {0x11u, 0x30u}, - {0x12u, 0x09u}, + {0x12u, 0x03u}, {0x13u, 0xC0u}, {0x15u, 0x06u}, {0x16u, 0x24u}, @@ -1446,26 +1490,24 @@ void cyfitter_cfg(void) {0x1Eu, 0x04u}, {0x20u, 0x24u}, {0x22u, 0x12u}, + {0x25u, 0x05u}, {0x26u, 0x80u}, - {0x29u, 0x60u}, + {0x27u, 0x0Au}, {0x2Au, 0x20u}, - {0x2Bu, 0x90u}, {0x2Cu, 0x40u}, {0x2Eu, 0x80u}, {0x30u, 0x07u}, - {0x31u, 0xFFu}, - {0x32u, 0xC0u}, {0x34u, 0x38u}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x01u}, + {0x36u, 0xC0u}, + {0x37u, 0xFFu}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x40u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Cu, 0x01u}, {0x5Fu, 0x01u}, - {0x80u, 0x05u}, {0x81u, 0x90u}, - {0x82u, 0x0Au}, {0x83u, 0x48u}, {0x84u, 0x03u}, {0x86u, 0x0Cu}, @@ -1480,11 +1522,13 @@ void cyfitter_cfg(void) {0x91u, 0x90u}, {0x92u, 0x06u}, {0x93u, 0x24u}, - {0x94u, 0xFFu}, + {0x96u, 0xFFu}, {0x97u, 0x10u}, - {0x9Au, 0xFFu}, {0x9Bu, 0x60u}, + {0x9Cu, 0x05u}, + {0x9Eu, 0x0Au}, {0xA0u, 0xFFu}, + {0xA4u, 0xFFu}, {0xA7u, 0x90u}, {0xA8u, 0x30u}, {0xAAu, 0xC0u}, @@ -1492,75 +1536,75 @@ void cyfitter_cfg(void) {0xADu, 0x01u}, {0xAEu, 0xF0u}, {0xAFu, 0x02u}, - {0xB0u, 0xFFu}, {0xB3u, 0xE0u}, + {0xB4u, 0xFFu}, {0xB5u, 0x1Cu}, {0xB7u, 0x03u}, - {0xBEu, 0x01u}, + {0xBEu, 0x10u}, {0xBFu, 0x40u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDCu, 0x10u}, {0xDFu, 0x01u}, {0x00u, 0x04u}, - {0x01u, 0x02u}, - {0x05u, 0x42u}, - {0x07u, 0x14u}, - {0x08u, 0x0Au}, - {0x0Au, 0x02u}, - {0x0Du, 0x28u}, - {0x0Fu, 0x80u}, + {0x03u, 0x40u}, + {0x05u, 0x40u}, + {0x07u, 0x18u}, + {0x08u, 0x08u}, + {0x0Au, 0x42u}, + {0x0Fu, 0xA2u}, {0x10u, 0x20u}, {0x11u, 0x40u}, {0x12u, 0x08u}, {0x13u, 0x01u}, - {0x15u, 0x42u}, - {0x17u, 0x20u}, - {0x18u, 0x04u}, - {0x19u, 0x02u}, - {0x1Au, 0x18u}, - {0x1Fu, 0x01u}, - {0x21u, 0x01u}, + {0x15u, 0x48u}, + {0x17u, 0x22u}, + {0x18u, 0x85u}, + {0x1Au, 0x48u}, + {0x1Bu, 0x01u}, + {0x1Du, 0x10u}, + {0x21u, 0x80u}, + {0x23u, 0x02u}, {0x25u, 0x50u}, {0x26u, 0x20u}, {0x27u, 0x10u}, - {0x29u, 0x10u}, + {0x2Au, 0x04u}, {0x2Du, 0x40u}, {0x2Fu, 0x20u}, {0x31u, 0x02u}, {0x32u, 0x24u}, - {0x34u, 0x02u}, - {0x37u, 0x18u}, - {0x38u, 0x08u}, - {0x39u, 0x44u}, - {0x3Bu, 0x20u}, + {0x36u, 0x01u}, + {0x37u, 0x14u}, + {0x38u, 0x28u}, + {0x39u, 0x40u}, {0x3Du, 0x20u}, {0x3Eu, 0x08u}, {0x3Fu, 0x41u}, - {0x68u, 0x01u}, - {0x6Bu, 0x64u}, - {0x70u, 0x24u}, - {0x71u, 0x12u}, + {0x68u, 0x81u}, + {0x69u, 0x20u}, + {0x6Bu, 0x28u}, + {0x70u, 0x3Cu}, + {0x71u, 0x02u}, {0x72u, 0x02u}, {0x73u, 0x40u}, {0x81u, 0x40u}, - {0x83u, 0x08u}, {0x84u, 0x01u}, {0x85u, 0x40u}, {0x86u, 0x18u}, {0x87u, 0x20u}, - {0x89u, 0x50u}, + {0x89u, 0x40u}, {0x8Au, 0x01u}, - {0x8Cu, 0x02u}, - {0x8Eu, 0x08u}, - {0xC0u, 0xFCu}, - {0xC2u, 0x7Du}, - {0xC4u, 0xDFu}, - {0xCAu, 0x54u}, + {0x8Eu, 0x09u}, + {0x8Fu, 0x44u}, + {0xC0u, 0xECu}, + {0xC2u, 0xBDu}, + {0xC4u, 0xFFu}, + {0xCAu, 0x52u}, {0xCCu, 0xE7u}, {0xCEu, 0xFEu}, - {0xE0u, 0xB0u}, - {0xE4u, 0x41u}, + {0xE0u, 0x70u}, + {0xE4u, 0x50u}, + {0xE6u, 0x01u}, {0x84u, 0x08u}, {0x85u, 0x25u}, {0x86u, 0x13u}, @@ -1592,17 +1636,19 @@ void cyfitter_cfg(void) {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, - {0x01u, 0xA2u}, - {0x03u, 0x10u}, + {0x01u, 0x82u}, + {0x03u, 0x18u}, {0x05u, 0x04u}, {0x09u, 0x01u}, - {0x0Bu, 0x2Au}, + {0x0Au, 0x08u}, + {0x0Bu, 0x22u}, {0x0Eu, 0x25u}, {0x10u, 0x20u}, {0x11u, 0x40u}, {0x12u, 0x88u}, {0x17u, 0x10u}, - {0x19u, 0x23u}, + {0x19u, 0x03u}, + {0x1Au, 0x08u}, {0x1Cu, 0x20u}, {0x1Eu, 0x21u}, {0x22u, 0x08u}, @@ -1641,7 +1687,7 @@ void cyfitter_cfg(void) {0x8Cu, 0x02u}, {0x90u, 0x04u}, {0x92u, 0x04u}, - {0x93u, 0x2Au}, + {0x93u, 0x22u}, {0x94u, 0x28u}, {0x95u, 0x41u}, {0x97u, 0x04u}, @@ -1655,6 +1701,9 @@ void cyfitter_cfg(void) {0xA4u, 0xC8u}, {0xA6u, 0x20u}, {0xA7u, 0x20u}, + {0xA9u, 0x02u}, + {0xAEu, 0x80u}, + {0xAFu, 0x20u}, {0xB0u, 0x80u}, {0xB1u, 0x10u}, {0xB2u, 0x80u}, @@ -1722,9 +1771,10 @@ void cyfitter_cfg(void) {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Fu, 0x01u}, - {0x80u, 0x30u}, + {0x80u, 0x02u}, {0x81u, 0x03u}, - {0x82u, 0x08u}, + {0x82u, 0x30u}, + {0x86u, 0x01u}, {0x87u, 0x01u}, {0x88u, 0x05u}, {0x89u, 0x03u}, @@ -1734,15 +1784,14 @@ void cyfitter_cfg(void) {0x8Fu, 0x03u}, {0x90u, 0x01u}, {0x92u, 0x38u}, + {0x94u, 0x10u}, {0x95u, 0x03u}, - {0x98u, 0x10u}, - {0x9Au, 0x20u}, - {0xA6u, 0x01u}, + {0x96u, 0x20u}, + {0x9Cu, 0x30u}, + {0x9Eu, 0x08u}, {0xA8u, 0x34u}, {0xAAu, 0x08u}, - {0xACu, 0x02u}, {0xADu, 0x03u}, - {0xAEu, 0x30u}, {0xB0u, 0x30u}, {0xB3u, 0x01u}, {0xB4u, 0x0Fu}, @@ -1757,18 +1806,16 @@ void cyfitter_cfg(void) {0xDBu, 0x04u}, {0xDCu, 0x01u}, {0xDFu, 0x01u}, - {0x00u, 0x01u}, - {0x01u, 0x20u}, - {0x03u, 0x02u}, + {0x01u, 0x24u}, + {0x03u, 0x42u}, {0x04u, 0x20u}, {0x05u, 0x45u}, - {0x08u, 0x10u}, - {0x09u, 0x01u}, + {0x08u, 0x08u}, + {0x0Au, 0x02u}, + {0x0Bu, 0x80u}, {0x0Cu, 0x88u}, {0x0Eu, 0x04u}, - {0x10u, 0x01u}, - {0x11u, 0x08u}, - {0x12u, 0x04u}, + {0x10u, 0x04u}, {0x15u, 0x41u}, {0x17u, 0x10u}, {0x19u, 0x20u}, @@ -1776,7 +1823,7 @@ void cyfitter_cfg(void) {0x1Cu, 0x04u}, {0x1Du, 0x05u}, {0x1Eu, 0x04u}, - {0x1Fu, 0x1Du}, + {0x1Fu, 0x19u}, {0x20u, 0x02u}, {0x22u, 0x08u}, {0x23u, 0x01u}, @@ -1798,236 +1845,237 @@ void cyfitter_cfg(void) {0x4Du, 0x10u}, {0x5Eu, 0x80u}, {0x5Fu, 0x15u}, - {0x62u, 0xAAu}, - {0x66u, 0x81u}, - {0x86u, 0x02u}, - {0x8Bu, 0x20u}, - {0x90u, 0x01u}, - {0x97u, 0x28u}, - {0x98u, 0x11u}, + {0x61u, 0x02u}, + {0x62u, 0xA8u}, + {0x64u, 0x80u}, + {0x66u, 0x80u}, + {0x91u, 0x04u}, + {0x92u, 0x02u}, + {0x93u, 0x80u}, + {0x97u, 0x20u}, + {0x98u, 0x0Cu}, {0x99u, 0x08u}, - {0x9Au, 0x84u}, - {0x9Cu, 0x40u}, + {0x9Bu, 0x60u}, + {0x9Cu, 0xC0u}, {0x9Du, 0x20u}, - {0x9Eu, 0x01u}, - {0x9Fu, 0x30u}, - {0xA1u, 0x05u}, + {0x9Fu, 0x10u}, {0xA4u, 0x40u}, - {0xA7u, 0x01u}, + {0xA7u, 0x09u}, {0xAAu, 0x40u}, {0xB0u, 0x04u}, - {0xB1u, 0x44u}, - {0xC0u, 0xFBu}, - {0xC2u, 0xEAu}, - {0xC4u, 0xD7u}, + {0xB4u, 0x80u}, + {0xC0u, 0xFFu}, + {0xC2u, 0xEDu}, + {0xC4u, 0xD2u}, {0xCAu, 0xF8u}, {0xCCu, 0xF2u}, {0xCEu, 0xEFu}, {0xD6u, 0xF0u}, {0xD8u, 0x9Fu}, - {0xEEu, 0x01u}, + {0xEAu, 0x12u}, + {0xEEu, 0x08u}, {0xB8u, 0x08u}, {0xBEu, 0x04u}, {0xD8u, 0x04u}, {0xDFu, 0x01u}, {0x1Bu, 0x08u}, - {0x80u, 0x40u}, - {0x90u, 0x80u}, - {0xB2u, 0x08u}, {0xB3u, 0x08u}, - {0xE0u, 0x01u}, - {0xE6u, 0x20u}, - {0xE8u, 0xA0u}, - {0xECu, 0x80u}, - {0xEEu, 0x01u}, + {0xE8u, 0x20u}, + {0xEAu, 0x02u}, + {0xEEu, 0x08u}, {0xAFu, 0x08u}, {0xE2u, 0x80u}, {0x06u, 0x02u}, - {0x0Fu, 0x02u}, + {0x0Du, 0x20u}, {0x12u, 0x08u}, + {0x13u, 0x02u}, {0x16u, 0x80u}, {0x17u, 0x80u}, - {0x30u, 0x08u}, - {0x36u, 0x80u}, + {0x30u, 0x10u}, + {0x33u, 0x01u}, + {0x36u, 0x20u}, {0x37u, 0x04u}, {0x39u, 0x04u}, {0x3Au, 0x80u}, + {0x3Cu, 0x01u}, {0x3Du, 0x10u}, - {0x3Eu, 0x04u}, - {0x41u, 0x20u}, + {0x40u, 0x02u}, {0x5Bu, 0x08u}, - {0x8Bu, 0x01u}, + {0x6Bu, 0x03u}, + {0x89u, 0x10u}, {0xC0u, 0x80u}, {0xC2u, 0x80u}, - {0xC4u, 0xE0u}, - {0xCCu, 0xE0u}, + {0xC4u, 0xF0u}, + {0xCCu, 0xF0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, {0xD6u, 0x40u}, - {0x31u, 0x02u}, - {0x33u, 0x10u}, - {0x36u, 0x08u}, + {0x33u, 0x11u}, + {0x36u, 0x01u}, {0x37u, 0x80u}, {0x39u, 0x80u}, {0x5Au, 0x10u}, - {0x5Eu, 0x40u}, + {0x5Eu, 0x80u}, {0x63u, 0x02u}, - {0x82u, 0x40u}, - {0x88u, 0x08u}, - {0x96u, 0x04u}, + {0x8Au, 0x40u}, + {0x94u, 0x01u}, {0x9Bu, 0x90u}, + {0x9Cu, 0x12u}, {0x9Fu, 0x08u}, - {0xA4u, 0x08u}, - {0xA5u, 0x20u}, - {0xA6u, 0x80u}, + {0xA1u, 0x20u}, + {0xA6u, 0x20u}, {0xAAu, 0x08u}, {0xABu, 0x14u}, - {0xADu, 0x14u}, + {0xADu, 0x04u}, {0xB6u, 0x02u}, {0xCCu, 0xF0u}, {0xCEu, 0x10u}, {0xD4u, 0x80u}, {0xD6u, 0x60u}, - {0xE2u, 0x20u}, {0xEAu, 0x80u}, - {0xEEu, 0x50u}, - {0x12u, 0x80u}, - {0x32u, 0x40u}, - {0x8Eu, 0x08u}, + {0xEEu, 0x40u}, + {0x10u, 0x10u}, + {0x31u, 0x40u}, + {0x94u, 0x01u}, {0x95u, 0x80u}, - {0x96u, 0x14u}, - {0x9Fu, 0x08u}, - {0xA5u, 0x22u}, - {0xA6u, 0x88u}, + {0x96u, 0x10u}, + {0x9Cu, 0x12u}, + {0x9Fu, 0x09u}, + {0xA6u, 0x01u}, {0xA7u, 0x01u}, + {0xB1u, 0x20u}, + {0xB6u, 0x20u}, {0xC4u, 0x10u}, {0xCCu, 0x10u}, - {0x81u, 0x20u}, - {0x82u, 0x10u}, + {0x82u, 0x11u}, {0x87u, 0x01u}, - {0x96u, 0x94u}, - {0x9Fu, 0x08u}, - {0xA5u, 0x20u}, + {0x94u, 0x01u}, + {0x96u, 0x10u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x40u}, + {0x9Fu, 0x09u}, + {0xA6u, 0x01u}, {0xA7u, 0x01u}, {0xA9u, 0x40u}, - {0xB1u, 0x02u}, - {0xE2u, 0xA0u}, - {0xE6u, 0x10u}, + {0xE2u, 0x80u}, + {0xE6u, 0x90u}, {0xEAu, 0x80u}, - {0x01u, 0x20u}, - {0x07u, 0x02u}, - {0x0Au, 0x08u}, - {0x0Eu, 0x01u}, + {0x02u, 0x01u}, + {0x07u, 0x08u}, + {0x09u, 0x80u}, + {0x0Cu, 0x40u}, {0x10u, 0x20u}, - {0x14u, 0x10u}, - {0x61u, 0x84u}, - {0x81u, 0x04u}, + {0x16u, 0x80u}, + {0x60u, 0x20u}, + {0x66u, 0x02u}, + {0x81u, 0x80u}, {0x8Bu, 0x20u}, + {0x8Eu, 0x02u}, {0xC0u, 0x03u}, {0xC2u, 0x03u}, {0xC4u, 0x0Cu}, - {0xD6u, 0x02u}, - {0xD8u, 0x02u}, + {0xD8u, 0x03u}, + {0xE0u, 0x02u}, {0xE4u, 0x04u}, {0x00u, 0x08u}, - {0x07u, 0x40u}, + {0x05u, 0x04u}, {0x0Au, 0x20u}, - {0x0Eu, 0x40u}, + {0x0Cu, 0x08u}, {0x52u, 0x80u}, {0x5Fu, 0x20u}, {0x66u, 0x84u}, - {0x81u, 0x20u}, - {0x8Au, 0x04u}, - {0x8Du, 0x80u}, - {0x8Eu, 0x40u}, - {0x92u, 0x09u}, - {0x99u, 0x20u}, - {0x9Au, 0x04u}, - {0x9Bu, 0x20u}, - {0xA5u, 0x80u}, + {0x80u, 0x08u}, + {0x82u, 0x01u}, + {0x88u, 0x40u}, + {0x98u, 0x40u}, + {0x9Au, 0x05u}, + {0x9Bu, 0x28u}, + {0x9Cu, 0x20u}, {0xAAu, 0x04u}, - {0xABu, 0x02u}, - {0xB0u, 0x30u}, + {0xAEu, 0x80u}, + {0xB0u, 0x20u}, {0xC0u, 0x0Cu}, {0xC2u, 0x0Cu}, {0xD4u, 0x04u}, {0xD6u, 0x05u}, {0xD8u, 0x01u}, - {0xE0u, 0x08u}, {0xE2u, 0x01u}, - {0xE6u, 0x02u}, - {0xEAu, 0x04u}, {0xEEu, 0x04u}, - {0x53u, 0x04u}, - {0x8Au, 0x01u}, - {0x8Cu, 0x02u}, - {0x8Eu, 0x80u}, - {0x92u, 0x01u}, - {0x9Bu, 0x40u}, + {0x83u, 0x20u}, + {0x8Bu, 0x08u}, + {0x8Du, 0x04u}, + {0x99u, 0x04u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x20u}, {0xAAu, 0x80u}, {0xB0u, 0x04u}, {0xB2u, 0x80u}, {0xB6u, 0x10u}, - {0xD4u, 0x04u}, - {0xE4u, 0x08u}, - {0xE6u, 0x03u}, + {0xE4u, 0x02u}, + {0xE6u, 0x01u}, {0xEAu, 0x06u}, {0xECu, 0x04u}, {0x09u, 0x08u}, {0x0Bu, 0x01u}, - {0x0Cu, 0x02u}, - {0x0Eu, 0x02u}, - {0x97u, 0x09u}, - {0x9Au, 0x80u}, - {0xA4u, 0x02u}, - {0xA5u, 0x08u}, + {0x0Fu, 0x22u}, + {0x83u, 0x10u}, + {0x86u, 0x20u}, + {0x8Du, 0x10u}, + {0x97u, 0x01u}, + {0xA1u, 0x04u}, + {0xA3u, 0x20u}, {0xABu, 0x01u}, - {0xB1u, 0x08u}, - {0xB7u, 0x40u}, + {0xACu, 0x20u}, + {0xB5u, 0x04u}, {0xC2u, 0x0Fu}, + {0xE2u, 0x02u}, {0xEAu, 0x08u}, - {0xEEu, 0x04u}, {0x67u, 0x40u}, - {0x86u, 0x04u}, - {0x96u, 0x04u}, - {0xAAu, 0x40u}, + {0x94u, 0x01u}, {0xABu, 0x08u}, + {0xADu, 0x40u}, + {0xAFu, 0x01u}, + {0xB4u, 0x02u}, {0xD8u, 0x80u}, - {0xE2u, 0x40u}, - {0xEAu, 0x20u}, - {0xEEu, 0x80u}, + {0xEAu, 0x60u}, + {0xEEu, 0x10u}, {0x04u, 0x08u}, {0x51u, 0x10u}, {0x56u, 0x40u}, {0x86u, 0x40u}, {0x89u, 0x10u}, {0x8Cu, 0x04u}, + {0xA8u, 0x01u}, {0xAFu, 0x40u}, {0xC0u, 0x20u}, {0xD4u, 0x60u}, {0xE2u, 0x10u}, + {0xEAu, 0x80u}, {0xEEu, 0x40u}, - {0x81u, 0x08u}, - {0x8Bu, 0x01u}, - {0x9Au, 0x80u}, - {0xAAu, 0x01u}, - {0xB3u, 0x04u}, - {0xE6u, 0x04u}, - {0xE8u, 0x01u}, + {0x76u, 0x20u}, + {0x9Au, 0x20u}, + {0x9Du, 0x10u}, + {0xA1u, 0x04u}, + {0xA3u, 0x20u}, + {0xADu, 0x08u}, + {0xAFu, 0x01u}, + {0xDEu, 0x04u}, {0x01u, 0x10u}, - {0x07u, 0x01u}, - {0x51u, 0x08u}, - {0x56u, 0x80u}, + {0x05u, 0x10u}, + {0x53u, 0x20u}, + {0x55u, 0x04u}, {0x89u, 0x10u}, - {0x9Au, 0x80u}, - {0x9Fu, 0x01u}, - {0xA1u, 0x08u}, + {0x9Du, 0x10u}, + {0xA1u, 0x04u}, + {0xA3u, 0x20u}, {0xC0u, 0x03u}, {0xD4u, 0x06u}, {0xE2u, 0x01u}, {0x10u, 0x03u}, + {0x11u, 0x01u}, {0x1Au, 0x03u}, - {0x00u, 0xFDu}, + {0x1Bu, 0x01u}, + {0x00u, 0xFFu}, {0x01u, 0xBFu}, {0x02u, 0x2Au}, {0x10u, 0x95u}, @@ -2047,7 +2095,7 @@ void cyfitter_cfg(void) uint16 size; } CYPACKED_ATTR cfg_memcpy_t; - static const cfg_memset_t CYCODE cfg_memset_list [] = { + static const cfg_memset_t CYCODE cfg_memset_list[] = { /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, @@ -2059,8 +2107,8 @@ void cyfitter_cfg(void) /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { - 0x04u, 0x80u, 0x00u, 0x00u, 0x08u, 0x00u, 0x21u, 0x00u, 0x40u, 0x7Fu, 0x00u, 0x80u, 0x01u, 0xC0u, 0x00u, 0x02u, - 0x01u, 0x90u, 0x00u, 0x40u, 0x22u, 0xC0u, 0x08u, 0x08u, 0x07u, 0x00u, 0x18u, 0xFFu, 0x01u, 0x00u, 0x00u, 0x9Fu, + 0x04u, 0x80u, 0x00u, 0x00u, 0x08u, 0x00u, 0x21u, 0x00u, 0x07u, 0x7Fu, 0x18u, 0x80u, 0x01u, 0xC0u, 0x00u, 0x02u, + 0x01u, 0x90u, 0x00u, 0x40u, 0x22u, 0xC0u, 0x08u, 0x08u, 0x40u, 0x00u, 0x00u, 0xFFu, 0x01u, 0x00u, 0x00u, 0x9Fu, 0x10u, 0x00u, 0x00u, 0x60u, 0x01u, 0xC0u, 0x00u, 0x04u, 0x40u, 0x1Fu, 0x00u, 0x20u, 0x01u, 0xC0u, 0x00u, 0x01u, 0x40u, 0x00u, 0x00u, 0xFFu, 0x3Fu, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x04u, 0x62u, 0x03u, 0x50u, 0x00u, 0x01u, 0xBEu, 0xFCu, 0x0Du, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h index 7252135..3a40dcb 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfitter_cfg.h * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: -* This file provides basic startup and mux configration settings +* This file provides basic startup and mux configuration settings * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 07d8d56..9a3d42a 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -1,395 +1,51 @@ +/******************************************************************************* +* File Name: cyfittergnu.inc +* +* PSoC Creator 4.1 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + .ifndef INCLUDED_CYFITTERGNU_INC .set INCLUDED_CYFITTERGNU_INC, 1 .include "cydevicegnu.inc" .include "cydevicegnu_trm.inc" -/* LED1 */ -.set LED1__0__INTTYPE, CYREG_PICU0_INTTYPE1 -.set LED1__0__MASK, 0x02 -.set LED1__0__PC, CYREG_PRT0_PC1 -.set LED1__0__PORT, 0 -.set LED1__0__SHIFT, 1 -.set LED1__AG, CYREG_PRT0_AG -.set LED1__AMUX, CYREG_PRT0_AMUX -.set LED1__BIE, CYREG_PRT0_BIE -.set LED1__BIT_MASK, CYREG_PRT0_BIT_MASK -.set LED1__BYP, CYREG_PRT0_BYP -.set LED1__CTL, CYREG_PRT0_CTL -.set LED1__DM0, CYREG_PRT0_DM0 -.set LED1__DM1, CYREG_PRT0_DM1 -.set LED1__DM2, CYREG_PRT0_DM2 -.set LED1__DR, CYREG_PRT0_DR -.set LED1__INP_DIS, CYREG_PRT0_INP_DIS -.set LED1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU0_BASE -.set LED1__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set LED1__LCD_EN, CYREG_PRT0_LCD_EN -.set LED1__MASK, 0x02 -.set LED1__PORT, 0 -.set LED1__PRT, CYREG_PRT0_PRT -.set LED1__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set LED1__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set LED1__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set LED1__PS, CYREG_PRT0_PS -.set LED1__SHIFT, 1 -.set LED1__SLW, CYREG_PRT0_SLW +/* Debug_Timer_Interrupt */ +.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set Debug_Timer_Interrupt__INTC_MASK, 0x01 +.set Debug_Timer_Interrupt__INTC_NUMBER, 0 +.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7 +.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -/* SD_CD */ -.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE5 -.set SD_CD__0__MASK, 0x20 -.set SD_CD__0__PC, CYREG_PRT3_PC5 -.set SD_CD__0__PORT, 3 -.set SD_CD__0__SHIFT, 5 -.set SD_CD__AG, CYREG_PRT3_AG -.set SD_CD__AMUX, CYREG_PRT3_AMUX -.set SD_CD__BIE, CYREG_PRT3_BIE -.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_CD__BYP, CYREG_PRT3_BYP -.set SD_CD__CTL, CYREG_PRT3_CTL -.set SD_CD__DM0, CYREG_PRT3_DM0 -.set SD_CD__DM1, CYREG_PRT3_DM1 -.set SD_CD__DM2, CYREG_PRT3_DM2 -.set SD_CD__DR, CYREG_PRT3_DR -.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_CD__MASK, 0x20 -.set SD_CD__PORT, 3 -.set SD_CD__PRT, CYREG_PRT3_PRT -.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_CD__PS, CYREG_PRT3_PS -.set SD_CD__SHIFT, 5 -.set SD_CD__SLW, CYREG_PRT3_SLW - -/* SD_CS */ -.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4 -.set SD_CS__0__MASK, 0x10 -.set SD_CS__0__PC, CYREG_PRT3_PC4 -.set SD_CS__0__PORT, 3 -.set SD_CS__0__SHIFT, 4 -.set SD_CS__AG, CYREG_PRT3_AG -.set SD_CS__AMUX, CYREG_PRT3_AMUX -.set SD_CS__BIE, CYREG_PRT3_BIE -.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_CS__BYP, CYREG_PRT3_BYP -.set SD_CS__CTL, CYREG_PRT3_CTL -.set SD_CS__DM0, CYREG_PRT3_DM0 -.set SD_CS__DM1, CYREG_PRT3_DM1 -.set SD_CS__DM2, CYREG_PRT3_DM2 -.set SD_CS__DR, CYREG_PRT3_DR -.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_CS__MASK, 0x10 -.set SD_CS__PORT, 3 -.set SD_CS__PRT, CYREG_PRT3_PRT -.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_CS__PS, CYREG_PRT3_PS -.set SD_CS__SHIFT, 4 -.set SD_CS__SLW, CYREG_PRT3_SLW - -/* USBFS_arb_int */ -.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_arb_int__INTC_MASK, 0x400000 -.set USBFS_arb_int__INTC_NUMBER, 22 -.set USBFS_arb_int__INTC_PRIOR_NUM, 6 -.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 -.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_bus_reset */ -.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_bus_reset__INTC_MASK, 0x800000 -.set USBFS_bus_reset__INTC_NUMBER, 23 -.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 -.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 -.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_Dm */ -.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7 -.set USBFS_Dm__0__MASK, 0x80 -.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 -.set USBFS_Dm__0__PORT, 15 -.set USBFS_Dm__0__SHIFT, 7 -.set USBFS_Dm__AG, CYREG_PRT15_AG -.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX -.set USBFS_Dm__BIE, CYREG_PRT15_BIE -.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK -.set USBFS_Dm__BYP, CYREG_PRT15_BYP -.set USBFS_Dm__CTL, CYREG_PRT15_CTL -.set USBFS_Dm__DM0, CYREG_PRT15_DM0 -.set USBFS_Dm__DM1, CYREG_PRT15_DM1 -.set USBFS_Dm__DM2, CYREG_PRT15_DM2 -.set USBFS_Dm__DR, CYREG_PRT15_DR -.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS -.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE -.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG -.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN -.set USBFS_Dm__MASK, 0x80 -.set USBFS_Dm__PORT, 15 -.set USBFS_Dm__PRT, CYREG_PRT15_PRT -.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL -.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN -.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 -.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 -.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 -.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 -.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT -.set USBFS_Dm__PS, CYREG_PRT15_PS -.set USBFS_Dm__SHIFT, 7 -.set USBFS_Dm__SLW, CYREG_PRT15_SLW - -/* USBFS_Dp */ -.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6 -.set USBFS_Dp__0__MASK, 0x40 -.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 -.set USBFS_Dp__0__PORT, 15 -.set USBFS_Dp__0__SHIFT, 6 -.set USBFS_Dp__AG, CYREG_PRT15_AG -.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX -.set USBFS_Dp__BIE, CYREG_PRT15_BIE -.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK -.set USBFS_Dp__BYP, CYREG_PRT15_BYP -.set USBFS_Dp__CTL, CYREG_PRT15_CTL -.set USBFS_Dp__DM0, CYREG_PRT15_DM0 -.set USBFS_Dp__DM1, CYREG_PRT15_DM1 -.set USBFS_Dp__DM2, CYREG_PRT15_DM2 -.set USBFS_Dp__DR, CYREG_PRT15_DR -.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS -.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT -.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE -.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG -.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN -.set USBFS_Dp__MASK, 0x40 -.set USBFS_Dp__PORT, 15 -.set USBFS_Dp__PRT, CYREG_PRT15_PRT -.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL -.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN -.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 -.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 -.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 -.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 -.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT -.set USBFS_Dp__PS, CYREG_PRT15_PS -.set USBFS_Dp__SHIFT, 6 -.set USBFS_Dp__SLW, CYREG_PRT15_SLW -.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 - -/* USBFS_dp_int */ -.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_dp_int__INTC_MASK, 0x1000 -.set USBFS_dp_int__INTC_NUMBER, 12 -.set USBFS_dp_int__INTC_PRIOR_NUM, 7 -.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 -.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_0 */ -.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_0__INTC_MASK, 0x1000000 -.set USBFS_ep_0__INTC_NUMBER, 24 -.set USBFS_ep_0__INTC_PRIOR_NUM, 7 -.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 -.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_1 */ -.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x80 -.set USBFS_ep_1__INTC_NUMBER, 7 -.set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 -.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_2 */ -.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x100 -.set USBFS_ep_2__INTC_NUMBER, 8 -.set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 -.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_3 */ -.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_3__INTC_MASK, 0x200 -.set USBFS_ep_3__INTC_NUMBER, 9 -.set USBFS_ep_3__INTC_PRIOR_NUM, 7 -.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 -.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_4 */ -.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_4__INTC_MASK, 0x400 -.set USBFS_ep_4__INTC_NUMBER, 10 -.set USBFS_ep_4__INTC_PRIOR_NUM, 7 -.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 -.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_sof_int */ -.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_sof_int__INTC_MASK, 0x200000 -.set USBFS_sof_int__INTC_NUMBER, 21 -.set USBFS_sof_int__INTC_PRIOR_NUM, 7 -.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 -.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_USB */ -.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG -.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG -.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN -.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR -.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG -.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN -.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR -.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG -.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN -.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR -.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG -.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN -.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR -.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG -.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN -.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR -.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG -.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN -.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR -.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG -.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN -.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR -.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG -.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN -.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR -.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN -.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR -.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR -.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA -.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB -.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA -.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB -.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR -.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA -.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB -.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA -.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB -.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR -.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA -.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB -.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA -.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB -.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR -.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA -.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB -.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA -.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB -.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR -.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA -.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB -.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA -.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB -.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR -.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA -.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB -.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA -.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB -.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR -.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA -.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB -.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA -.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB -.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR -.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA -.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB -.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA -.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB -.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE -.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT -.set USBFS_USB__CR0, CYREG_USB_CR0 -.set USBFS_USB__CR1, CYREG_USB_CR1 -.set USBFS_USB__CWA, CYREG_USB_CWA -.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB -.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES -.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB -.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG -.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE -.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE -.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT -.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR -.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 -.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 -.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 -.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 -.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 -.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 -.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 -.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 -.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE -.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 -.set USBFS_USB__PM_ACT_MSK, 0x01 -.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 -.set USBFS_USB__PM_STBY_MSK, 0x01 -.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN -.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR -.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 -.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 -.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 -.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 -.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 -.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 -.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 -.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 -.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 -.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 -.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 -.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 -.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 -.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 -.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 -.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 -.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 -.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 -.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 -.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 -.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 -.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 -.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 -.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 -.set USBFS_USB__SOF0, CYREG_USB_SOF0 -.set USBFS_USB__SOF1, CYREG_USB_SOF1 -.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN -.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 -.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 +/* Debug_Timer_TimerHW */ +.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0 +.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1 +.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0 +.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1 +.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2 +.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0 +.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1 +.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0 +.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1 +.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3 +.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01 +.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3 +.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01 +.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0 +.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1 +.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0 /* EXTLED */ .set EXTLED__0__INTTYPE, CYREG_PICU0_INTTYPE0 @@ -425,112 +81,116 @@ .set EXTLED__SHIFT, 0 .set EXTLED__SLW, CYREG_PRT0_SLW -/* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST -.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 -.set SDCard_BSPIM_RxStsReg__4__POS, 4 -.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 -.set SDCard_BSPIM_RxStsReg__5__POS, 5 -.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 -.set SDCard_BSPIM_RxStsReg__6__POS, 6 -.set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 -.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 -.set SDCard_BSPIM_TxStsReg__0__POS, 0 -.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 -.set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST -.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 -.set SDCard_BSPIM_TxStsReg__2__POS, 2 -.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 -.set SDCard_BSPIM_TxStsReg__3__POS, 3 -.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 -.set SDCard_BSPIM_TxStsReg__4__POS, 4 -.set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST +/* LED1 */ +.set LED1__0__INTTYPE, CYREG_PICU0_INTTYPE1 +.set LED1__0__MASK, 0x02 +.set LED1__0__PC, CYREG_PRT0_PC1 +.set LED1__0__PORT, 0 +.set LED1__0__SHIFT, 1 +.set LED1__AG, CYREG_PRT0_AG +.set LED1__AMUX, CYREG_PRT0_AMUX +.set LED1__BIE, CYREG_PRT0_BIE +.set LED1__BIT_MASK, CYREG_PRT0_BIT_MASK +.set LED1__BYP, CYREG_PRT0_BYP +.set LED1__CTL, CYREG_PRT0_CTL +.set LED1__DM0, CYREG_PRT0_DM0 +.set LED1__DM1, CYREG_PRT0_DM1 +.set LED1__DM2, CYREG_PRT0_DM2 +.set LED1__DR, CYREG_PRT0_DR +.set LED1__INP_DIS, CYREG_PRT0_INP_DIS +.set LED1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU0_BASE +.set LED1__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set LED1__LCD_EN, CYREG_PRT0_LCD_EN +.set LED1__MASK, 0x02 +.set LED1__PORT, 0 +.set LED1__PRT, CYREG_PRT0_PRT +.set LED1__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set LED1__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set LED1__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set LED1__PS, CYREG_PRT0_PS +.set LED1__SHIFT, 1 +.set LED1__SLW, CYREG_PRT0_SLW -/* SD_SCK */ -.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2 -.set SD_SCK__0__MASK, 0x04 -.set SD_SCK__0__PC, CYREG_PRT3_PC2 -.set SD_SCK__0__PORT, 3 -.set SD_SCK__0__SHIFT, 2 -.set SD_SCK__AG, CYREG_PRT3_AG -.set SD_SCK__AMUX, CYREG_PRT3_AMUX -.set SD_SCK__BIE, CYREG_PRT3_BIE -.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_SCK__BYP, CYREG_PRT3_BYP -.set SD_SCK__CTL, CYREG_PRT3_CTL -.set SD_SCK__DM0, CYREG_PRT3_DM0 -.set SD_SCK__DM1, CYREG_PRT3_DM1 -.set SD_SCK__DM2, CYREG_PRT3_DM2 -.set SD_SCK__DR, CYREG_PRT3_DR -.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_SCK__MASK, 0x04 -.set SD_SCK__PORT, 3 -.set SD_SCK__PRT, CYREG_PRT3_PRT -.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_SCK__PS, CYREG_PRT3_PS -.set SD_SCK__SHIFT, 2 -.set SD_SCK__SLW, CYREG_PRT3_SLW +/* SCSI_CLK */ +.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 +.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 +.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2 +.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07 +.set SCSI_CLK__INDEX, 0x01 +.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SCSI_CLK__PM_ACT_MSK, 0x02 +.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SCSI_CLK__PM_STBY_MSK, 0x02 + +/* SCSI_CTL_PHASE */ +.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK + +/* SCSI_Filtered */ +.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Filtered_sts_sts_reg__0__POS, 0 +.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 +.set SCSI_Filtered_sts_sts_reg__1__POS, 1 +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST +.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 +.set SCSI_Filtered_sts_sts_reg__2__POS, 2 +.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 +.set SCSI_Filtered_sts_sts_reg__3__POS, 3 +.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 +.set SCSI_Filtered_sts_sts_reg__4__POS, 4 +.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST + +/* SCSI_Glitch_Ctl */ +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK /* SCSI_In */ .set SCSI_In__0__AG, CYREG_PRT2_AG @@ -813,8 +473,6 @@ .set SCSI_In__REQ__PS, CYREG_PRT0_PS .set SCSI_In__REQ__SHIFT, 5 .set SCSI_In__REQ__SLW, CYREG_PRT0_SLW - -/* SCSI_In_DBx */ .set SCSI_In_DBx__0__AG, CYREG_PRT5_AG .set SCSI_In_DBx__0__AMUX, CYREG_PRT5_AMUX .set SCSI_In_DBx__0__BIE, CYREG_PRT5_BIE @@ -1260,84 +918,287 @@ .set SCSI_In_DBx__DB7__SHIFT, 4 .set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW -/* SD_MISO */ -.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1 -.set SD_MISO__0__MASK, 0x02 -.set SD_MISO__0__PC, CYREG_PRT3_PC1 -.set SD_MISO__0__PORT, 3 -.set SD_MISO__0__SHIFT, 1 -.set SD_MISO__AG, CYREG_PRT3_AG -.set SD_MISO__AMUX, CYREG_PRT3_AMUX -.set SD_MISO__BIE, CYREG_PRT3_BIE -.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_MISO__BYP, CYREG_PRT3_BYP -.set SD_MISO__CTL, CYREG_PRT3_CTL -.set SD_MISO__DM0, CYREG_PRT3_DM0 -.set SD_MISO__DM1, CYREG_PRT3_DM1 -.set SD_MISO__DM2, CYREG_PRT3_DM2 -.set SD_MISO__DR, CYREG_PRT3_DR -.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_MISO__MASK, 0x02 -.set SD_MISO__PORT, 3 -.set SD_MISO__PRT, CYREG_PRT3_PRT -.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_MISO__PS, CYREG_PRT3_PS -.set SD_MISO__SHIFT, 1 -.set SD_MISO__SLW, CYREG_PRT3_SLW - -/* SD_MOSI */ -.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3 -.set SD_MOSI__0__MASK, 0x08 -.set SD_MOSI__0__PC, CYREG_PRT3_PC3 -.set SD_MOSI__0__PORT, 3 -.set SD_MOSI__0__SHIFT, 3 -.set SD_MOSI__AG, CYREG_PRT3_AG -.set SD_MOSI__AMUX, CYREG_PRT3_AMUX -.set SD_MOSI__BIE, CYREG_PRT3_BIE -.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_MOSI__BYP, CYREG_PRT3_BYP -.set SD_MOSI__CTL, CYREG_PRT3_CTL -.set SD_MOSI__DM0, CYREG_PRT3_DM0 -.set SD_MOSI__DM1, CYREG_PRT3_DM1 -.set SD_MOSI__DM2, CYREG_PRT3_DM2 -.set SD_MOSI__DR, CYREG_PRT3_DR -.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_MOSI__MASK, 0x08 -.set SD_MOSI__PORT, 3 -.set SD_MOSI__PRT, CYREG_PRT3_PRT -.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_MOSI__PS, CYREG_PRT3_PS -.set SD_MOSI__SHIFT, 3 -.set SD_MOSI__SLW, CYREG_PRT3_SLW - -/* SCSI_CLK */ -.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 -.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 -.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2 -.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07 -.set SCSI_CLK__INDEX, 0x01 -.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set SCSI_CLK__PM_ACT_MSK, 0x02 -.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set SCSI_CLK__PM_STBY_MSK, 0x02 +/* SCSI_Noise */ +.set SCSI_Noise__0__AG, CYREG_PRT2_AG +.set SCSI_Noise__0__AMUX, CYREG_PRT2_AMUX +.set SCSI_Noise__0__BIE, CYREG_PRT2_BIE +.set SCSI_Noise__0__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Noise__0__BYP, CYREG_PRT2_BYP +.set SCSI_Noise__0__CTL, CYREG_PRT2_CTL +.set SCSI_Noise__0__DM0, CYREG_PRT2_DM0 +.set SCSI_Noise__0__DM1, CYREG_PRT2_DM1 +.set SCSI_Noise__0__DM2, CYREG_PRT2_DM2 +.set SCSI_Noise__0__DR, CYREG_PRT2_DR +.set SCSI_Noise__0__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Noise__0__INTTYPE, CYREG_PICU2_INTTYPE0 +.set SCSI_Noise__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Noise__0__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Noise__0__MASK, 0x01 +.set SCSI_Noise__0__PC, CYREG_PRT2_PC0 +.set SCSI_Noise__0__PORT, 2 +.set SCSI_Noise__0__PRT, CYREG_PRT2_PRT +.set SCSI_Noise__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Noise__0__PS, CYREG_PRT2_PS +.set SCSI_Noise__0__SHIFT, 0 +.set SCSI_Noise__0__SLW, CYREG_PRT2_SLW +.set SCSI_Noise__1__AG, CYREG_PRT6_AG +.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__1__DR, CYREG_PRT6_DR +.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__1__INTTYPE, CYREG_PICU6_INTTYPE3 +.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__1__MASK, 0x08 +.set SCSI_Noise__1__PC, CYREG_PRT6_PC3 +.set SCSI_Noise__1__PORT, 6 +.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__1__PS, CYREG_PRT6_PS +.set SCSI_Noise__1__SHIFT, 3 +.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__2__AG, CYREG_PRT4_AG +.set SCSI_Noise__2__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__2__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__2__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__2__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__2__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__2__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__2__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__2__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__2__DR, CYREG_PRT4_DR +.set SCSI_Noise__2__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__2__INTTYPE, CYREG_PICU4_INTTYPE3 +.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__2__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__2__MASK, 0x08 +.set SCSI_Noise__2__PC, CYREG_PRT4_PC3 +.set SCSI_Noise__2__PORT, 4 +.set SCSI_Noise__2__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__2__PS, CYREG_PRT4_PS +.set SCSI_Noise__2__SHIFT, 3 +.set SCSI_Noise__2__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__3__AG, CYREG_PRT4_AG +.set SCSI_Noise__3__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__3__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__3__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__3__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__3__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__3__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__3__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__3__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__3__DR, CYREG_PRT4_DR +.set SCSI_Noise__3__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__3__INTTYPE, CYREG_PICU4_INTTYPE7 +.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__3__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__3__MASK, 0x80 +.set SCSI_Noise__3__PC, CYREG_PRT4_PC7 +.set SCSI_Noise__3__PORT, 4 +.set SCSI_Noise__3__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__3__PS, CYREG_PRT4_PS +.set SCSI_Noise__3__SHIFT, 7 +.set SCSI_Noise__3__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__4__AG, CYREG_PRT6_AG +.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__4__DR, CYREG_PRT6_DR +.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__4__INTTYPE, CYREG_PICU6_INTTYPE2 +.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__4__MASK, 0x04 +.set SCSI_Noise__4__PC, CYREG_PRT6_PC2 +.set SCSI_Noise__4__PORT, 6 +.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__4__PS, CYREG_PRT6_PS +.set SCSI_Noise__4__SHIFT, 2 +.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG +.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR +.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__ACK__INTTYPE, CYREG_PICU6_INTTYPE2 +.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__ACK__MASK, 0x04 +.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC2 +.set SCSI_Noise__ACK__PORT, 6 +.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS +.set SCSI_Noise__ACK__SHIFT, 2 +.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__ATN__AG, CYREG_PRT2_AG +.set SCSI_Noise__ATN__AMUX, CYREG_PRT2_AMUX +.set SCSI_Noise__ATN__BIE, CYREG_PRT2_BIE +.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Noise__ATN__BYP, CYREG_PRT2_BYP +.set SCSI_Noise__ATN__CTL, CYREG_PRT2_CTL +.set SCSI_Noise__ATN__DM0, CYREG_PRT2_DM0 +.set SCSI_Noise__ATN__DM1, CYREG_PRT2_DM1 +.set SCSI_Noise__ATN__DM2, CYREG_PRT2_DM2 +.set SCSI_Noise__ATN__DR, CYREG_PRT2_DR +.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Noise__ATN__INTTYPE, CYREG_PICU2_INTTYPE0 +.set SCSI_Noise__ATN__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Noise__ATN__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Noise__ATN__MASK, 0x01 +.set SCSI_Noise__ATN__PC, CYREG_PRT2_PC0 +.set SCSI_Noise__ATN__PORT, 2 +.set SCSI_Noise__ATN__PRT, CYREG_PRT2_PRT +.set SCSI_Noise__ATN__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Noise__ATN__PS, CYREG_PRT2_PS +.set SCSI_Noise__ATN__SHIFT, 0 +.set SCSI_Noise__ATN__SLW, CYREG_PRT2_SLW +.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG +.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR +.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__BSY__INTTYPE, CYREG_PICU6_INTTYPE3 +.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__BSY__MASK, 0x08 +.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC3 +.set SCSI_Noise__BSY__PORT, 6 +.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS +.set SCSI_Noise__BSY__SHIFT, 3 +.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__RST__AG, CYREG_PRT4_AG +.set SCSI_Noise__RST__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__RST__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__RST__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__RST__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__RST__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__RST__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__RST__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__RST__DR, CYREG_PRT4_DR +.set SCSI_Noise__RST__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__RST__INTTYPE, CYREG_PICU4_INTTYPE7 +.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__RST__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__RST__MASK, 0x80 +.set SCSI_Noise__RST__PC, CYREG_PRT4_PC7 +.set SCSI_Noise__RST__PORT, 4 +.set SCSI_Noise__RST__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__RST__PS, CYREG_PRT4_PS +.set SCSI_Noise__RST__SHIFT, 7 +.set SCSI_Noise__RST__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__SEL__AG, CYREG_PRT4_AG +.set SCSI_Noise__SEL__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__SEL__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__SEL__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__SEL__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__SEL__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__SEL__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__SEL__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__SEL__DR, CYREG_PRT4_DR +.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__SEL__INTTYPE, CYREG_PICU4_INTTYPE3 +.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__SEL__MASK, 0x08 +.set SCSI_Noise__SEL__PC, CYREG_PRT4_PC3 +.set SCSI_Noise__SEL__PORT, 4 +.set SCSI_Noise__SEL__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__SEL__PS, CYREG_PRT4_PS +.set SCSI_Noise__SEL__SHIFT, 3 +.set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW /* SCSI_Out */ .set SCSI_Out__0__AG, CYREG_PRT15_AG @@ -1900,8 +1761,6 @@ .set SCSI_Out__SEL__PS, CYREG_PRT0_PS .set SCSI_Out__SEL__SHIFT, 7 .set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW - -/* SCSI_Out_Bits */ .set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 @@ -1936,8 +1795,6 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL .set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL .set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK - -/* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL @@ -1958,8 +1815,6 @@ .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL .set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL .set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK - -/* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG .set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX .set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE @@ -2409,6 +2264,296 @@ .set SCSI_Out_DBx__DB7__SHIFT, 2 .set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW +/* SCSI_Parity_Error */ +.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST + +/* SCSI_RST_ISR */ +.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RST_ISR__INTC_MASK, 0x02 +.set SCSI_RST_ISR__INTC_NUMBER, 1 +.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_RX_DMA */ +.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_RX_DMA__DRQ_NUMBER, 0 +.set SCSI_RX_DMA__NUMBEROF_TDS, 0 +.set SCSI_RX_DMA__PRIORITY, 2 +.set SCSI_RX_DMA__TERMIN_EN, 0 +.set SCSI_RX_DMA__TERMIN_SEL, 0 +.set SCSI_RX_DMA__TERMOUT0_EN, 1 +.set SCSI_RX_DMA__TERMOUT0_SEL, 0 +.set SCSI_RX_DMA__TERMOUT1_EN, 0 +.set SCSI_RX_DMA__TERMOUT1_SEL, 0 +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04 +.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_SEL_ISR__INTC_MASK, 0x08 +.set SCSI_SEL_ISR__INTC_NUMBER, 3 +.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_TX_DMA__DRQ_NUMBER, 1 +.set SCSI_TX_DMA__NUMBEROF_TDS, 0 +.set SCSI_TX_DMA__PRIORITY, 2 +.set SCSI_TX_DMA__TERMIN_EN, 0 +.set SCSI_TX_DMA__TERMIN_SEL, 0 +.set SCSI_TX_DMA__TERMOUT0_EN, 1 +.set SCSI_TX_DMA__TERMOUT0_SEL, 1 +.set SCSI_TX_DMA__TERMOUT1_EN, 0 +.set SCSI_TX_DMA__TERMOUT1_SEL, 0 +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 +.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SDCard_BSPIM */ +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_RxStsReg__4__POS, 4 +.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 +.set SDCard_BSPIM_RxStsReg__5__POS, 5 +.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 +.set SDCard_BSPIM_RxStsReg__6__POS, 6 +.set SDCard_BSPIM_RxStsReg__MASK, 0x70 +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 +.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 +.set SDCard_BSPIM_TxStsReg__0__POS, 0 +.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 +.set SDCard_BSPIM_TxStsReg__1__POS, 1 +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 +.set SDCard_BSPIM_TxStsReg__2__POS, 2 +.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 +.set SDCard_BSPIM_TxStsReg__3__POS, 3 +.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_TxStsReg__4__POS, 4 +.set SDCard_BSPIM_TxStsReg__MASK, 0x1F +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST + +/* SD_CD */ +.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE5 +.set SD_CD__0__MASK, 0x20 +.set SD_CD__0__PC, CYREG_PRT3_PC5 +.set SD_CD__0__PORT, 3 +.set SD_CD__0__SHIFT, 5 +.set SD_CD__AG, CYREG_PRT3_AG +.set SD_CD__AMUX, CYREG_PRT3_AMUX +.set SD_CD__BIE, CYREG_PRT3_BIE +.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CD__BYP, CYREG_PRT3_BYP +.set SD_CD__CTL, CYREG_PRT3_CTL +.set SD_CD__DM0, CYREG_PRT3_DM0 +.set SD_CD__DM1, CYREG_PRT3_DM1 +.set SD_CD__DM2, CYREG_PRT3_DM2 +.set SD_CD__DR, CYREG_PRT3_DR +.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CD__MASK, 0x20 +.set SD_CD__PORT, 3 +.set SD_CD__PRT, CYREG_PRT3_PRT +.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CD__PS, CYREG_PRT3_PS +.set SD_CD__SHIFT, 5 +.set SD_CD__SLW, CYREG_PRT3_SLW + +/* SD_CS */ +.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4 +.set SD_CS__0__MASK, 0x10 +.set SD_CS__0__PC, CYREG_PRT3_PC4 +.set SD_CS__0__PORT, 3 +.set SD_CS__0__SHIFT, 4 +.set SD_CS__AG, CYREG_PRT3_AG +.set SD_CS__AMUX, CYREG_PRT3_AMUX +.set SD_CS__BIE, CYREG_PRT3_BIE +.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CS__BYP, CYREG_PRT3_BYP +.set SD_CS__CTL, CYREG_PRT3_CTL +.set SD_CS__DM0, CYREG_PRT3_DM0 +.set SD_CS__DM1, CYREG_PRT3_DM1 +.set SD_CS__DM2, CYREG_PRT3_DM2 +.set SD_CS__DR, CYREG_PRT3_DR +.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CS__MASK, 0x10 +.set SD_CS__PORT, 3 +.set SD_CS__PRT, CYREG_PRT3_PRT +.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CS__PS, CYREG_PRT3_PS +.set SD_CS__SHIFT, 4 +.set SD_CS__SLW, CYREG_PRT3_SLW + +/* SD_Data_Clk */ +.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 +.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 +.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 +.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 +.set SD_Data_Clk__INDEX, 0x00 +.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SD_Data_Clk__PM_ACT_MSK, 0x01 +.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SD_Data_Clk__PM_STBY_MSK, 0x01 + +/* SD_MISO */ +.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1 +.set SD_MISO__0__MASK, 0x02 +.set SD_MISO__0__PC, CYREG_PRT3_PC1 +.set SD_MISO__0__PORT, 3 +.set SD_MISO__0__SHIFT, 1 +.set SD_MISO__AG, CYREG_PRT3_AG +.set SD_MISO__AMUX, CYREG_PRT3_AMUX +.set SD_MISO__BIE, CYREG_PRT3_BIE +.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MISO__BYP, CYREG_PRT3_BYP +.set SD_MISO__CTL, CYREG_PRT3_CTL +.set SD_MISO__DM0, CYREG_PRT3_DM0 +.set SD_MISO__DM1, CYREG_PRT3_DM1 +.set SD_MISO__DM2, CYREG_PRT3_DM2 +.set SD_MISO__DR, CYREG_PRT3_DR +.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MISO__MASK, 0x02 +.set SD_MISO__PORT, 3 +.set SD_MISO__PRT, CYREG_PRT3_PRT +.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MISO__PS, CYREG_PRT3_PS +.set SD_MISO__SHIFT, 1 +.set SD_MISO__SLW, CYREG_PRT3_SLW + +/* SD_MOSI */ +.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3 +.set SD_MOSI__0__MASK, 0x08 +.set SD_MOSI__0__PC, CYREG_PRT3_PC3 +.set SD_MOSI__0__PORT, 3 +.set SD_MOSI__0__SHIFT, 3 +.set SD_MOSI__AG, CYREG_PRT3_AG +.set SD_MOSI__AMUX, CYREG_PRT3_AMUX +.set SD_MOSI__BIE, CYREG_PRT3_BIE +.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MOSI__BYP, CYREG_PRT3_BYP +.set SD_MOSI__CTL, CYREG_PRT3_CTL +.set SD_MOSI__DM0, CYREG_PRT3_DM0 +.set SD_MOSI__DM1, CYREG_PRT3_DM1 +.set SD_MOSI__DM2, CYREG_PRT3_DM2 +.set SD_MOSI__DR, CYREG_PRT3_DR +.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MOSI__MASK, 0x08 +.set SD_MOSI__PORT, 3 +.set SD_MOSI__PRT, CYREG_PRT3_PRT +.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MOSI__PS, CYREG_PRT3_PS +.set SD_MOSI__SHIFT, 3 +.set SD_MOSI__SLW, CYREG_PRT3_SLW + /* SD_RX_DMA */ .set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_RX_DMA__DRQ_NUMBER, 2 @@ -2420,8 +2565,6 @@ .set SD_RX_DMA__TERMOUT0_SEL, 2 .set SD_RX_DMA__TERMOUT1_EN, 0 .set SD_RX_DMA__TERMOUT1_SEL, 0 - -/* SD_RX_DMA_COMPLETE */ .set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 .set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20 @@ -2431,6 +2574,40 @@ .set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* SD_SCK */ +.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2 +.set SD_SCK__0__MASK, 0x04 +.set SD_SCK__0__PC, CYREG_PRT3_PC2 +.set SD_SCK__0__PORT, 3 +.set SD_SCK__0__SHIFT, 2 +.set SD_SCK__AG, CYREG_PRT3_AG +.set SD_SCK__AMUX, CYREG_PRT3_AMUX +.set SD_SCK__BIE, CYREG_PRT3_BIE +.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_SCK__BYP, CYREG_PRT3_BYP +.set SD_SCK__CTL, CYREG_PRT3_CTL +.set SD_SCK__DM0, CYREG_PRT3_DM0 +.set SD_SCK__DM1, CYREG_PRT3_DM1 +.set SD_SCK__DM2, CYREG_PRT3_DM2 +.set SD_SCK__DR, CYREG_PRT3_DR +.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_SCK__MASK, 0x04 +.set SD_SCK__PORT, 3 +.set SD_SCK__PRT, CYREG_PRT3_PRT +.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_SCK__PS, CYREG_PRT3_PS +.set SD_SCK__SHIFT, 2 +.set SD_SCK__SLW, CYREG_PRT3_SLW + /* SD_TX_DMA */ .set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_TX_DMA__DRQ_NUMBER, 3 @@ -2442,8 +2619,6 @@ .set SD_TX_DMA__TERMOUT0_SEL, 3 .set SD_TX_DMA__TERMOUT1_EN, 0 .set SD_TX_DMA__TERMOUT1_SEL, 0 - -/* SD_TX_DMA_COMPLETE */ .set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 .set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40 @@ -2453,287 +2628,269 @@ .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -/* SCSI_Noise */ -.set SCSI_Noise__0__AG, CYREG_PRT2_AG -.set SCSI_Noise__0__AMUX, CYREG_PRT2_AMUX -.set SCSI_Noise__0__BIE, CYREG_PRT2_BIE -.set SCSI_Noise__0__BIT_MASK, CYREG_PRT2_BIT_MASK -.set SCSI_Noise__0__BYP, CYREG_PRT2_BYP -.set SCSI_Noise__0__CTL, CYREG_PRT2_CTL -.set SCSI_Noise__0__DM0, CYREG_PRT2_DM0 -.set SCSI_Noise__0__DM1, CYREG_PRT2_DM1 -.set SCSI_Noise__0__DM2, CYREG_PRT2_DM2 -.set SCSI_Noise__0__DR, CYREG_PRT2_DR -.set SCSI_Noise__0__INP_DIS, CYREG_PRT2_INP_DIS -.set SCSI_Noise__0__INTTYPE, CYREG_PICU2_INTTYPE0 -.set SCSI_Noise__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG -.set SCSI_Noise__0__LCD_EN, CYREG_PRT2_LCD_EN -.set SCSI_Noise__0__MASK, 0x01 -.set SCSI_Noise__0__PC, CYREG_PRT2_PC0 -.set SCSI_Noise__0__PORT, 2 -.set SCSI_Noise__0__PRT, CYREG_PRT2_PRT -.set SCSI_Noise__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL -.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN -.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 -.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 -.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 -.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 -.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT -.set SCSI_Noise__0__PS, CYREG_PRT2_PS -.set SCSI_Noise__0__SHIFT, 0 -.set SCSI_Noise__0__SLW, CYREG_PRT2_SLW -.set SCSI_Noise__1__AG, CYREG_PRT6_AG -.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__1__DR, CYREG_PRT6_DR -.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__1__INTTYPE, CYREG_PICU6_INTTYPE3 -.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__1__MASK, 0x08 -.set SCSI_Noise__1__PC, CYREG_PRT6_PC3 -.set SCSI_Noise__1__PORT, 6 -.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__1__PS, CYREG_PRT6_PS -.set SCSI_Noise__1__SHIFT, 3 -.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__2__AG, CYREG_PRT4_AG -.set SCSI_Noise__2__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__2__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__2__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__2__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__2__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__2__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__2__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__2__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__2__DR, CYREG_PRT4_DR -.set SCSI_Noise__2__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__2__INTTYPE, CYREG_PICU4_INTTYPE3 -.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__2__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__2__MASK, 0x08 -.set SCSI_Noise__2__PC, CYREG_PRT4_PC3 -.set SCSI_Noise__2__PORT, 4 -.set SCSI_Noise__2__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__2__PS, CYREG_PRT4_PS -.set SCSI_Noise__2__SHIFT, 3 -.set SCSI_Noise__2__SLW, CYREG_PRT4_SLW -.set SCSI_Noise__3__AG, CYREG_PRT4_AG -.set SCSI_Noise__3__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__3__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__3__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__3__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__3__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__3__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__3__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__3__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__3__DR, CYREG_PRT4_DR -.set SCSI_Noise__3__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__3__INTTYPE, CYREG_PICU4_INTTYPE7 -.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__3__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__3__MASK, 0x80 -.set SCSI_Noise__3__PC, CYREG_PRT4_PC7 -.set SCSI_Noise__3__PORT, 4 -.set SCSI_Noise__3__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__3__PS, CYREG_PRT4_PS -.set SCSI_Noise__3__SHIFT, 7 -.set SCSI_Noise__3__SLW, CYREG_PRT4_SLW -.set SCSI_Noise__4__AG, CYREG_PRT6_AG -.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__4__DR, CYREG_PRT6_DR -.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__4__INTTYPE, CYREG_PICU6_INTTYPE2 -.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__4__MASK, 0x04 -.set SCSI_Noise__4__PC, CYREG_PRT6_PC2 -.set SCSI_Noise__4__PORT, 6 -.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__4__PS, CYREG_PRT6_PS -.set SCSI_Noise__4__SHIFT, 2 -.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG -.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR -.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__ACK__INTTYPE, CYREG_PICU6_INTTYPE2 -.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__ACK__MASK, 0x04 -.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC2 -.set SCSI_Noise__ACK__PORT, 6 -.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS -.set SCSI_Noise__ACK__SHIFT, 2 -.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__ATN__AG, CYREG_PRT2_AG -.set SCSI_Noise__ATN__AMUX, CYREG_PRT2_AMUX -.set SCSI_Noise__ATN__BIE, CYREG_PRT2_BIE -.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT2_BIT_MASK -.set SCSI_Noise__ATN__BYP, CYREG_PRT2_BYP -.set SCSI_Noise__ATN__CTL, CYREG_PRT2_CTL -.set SCSI_Noise__ATN__DM0, CYREG_PRT2_DM0 -.set SCSI_Noise__ATN__DM1, CYREG_PRT2_DM1 -.set SCSI_Noise__ATN__DM2, CYREG_PRT2_DM2 -.set SCSI_Noise__ATN__DR, CYREG_PRT2_DR -.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT2_INP_DIS -.set SCSI_Noise__ATN__INTTYPE, CYREG_PICU2_INTTYPE0 -.set SCSI_Noise__ATN__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG -.set SCSI_Noise__ATN__LCD_EN, CYREG_PRT2_LCD_EN -.set SCSI_Noise__ATN__MASK, 0x01 -.set SCSI_Noise__ATN__PC, CYREG_PRT2_PC0 -.set SCSI_Noise__ATN__PORT, 2 -.set SCSI_Noise__ATN__PRT, CYREG_PRT2_PRT -.set SCSI_Noise__ATN__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL -.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN -.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 -.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 -.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 -.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 -.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT -.set SCSI_Noise__ATN__PS, CYREG_PRT2_PS -.set SCSI_Noise__ATN__SHIFT, 0 -.set SCSI_Noise__ATN__SLW, CYREG_PRT2_SLW -.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG -.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR -.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__BSY__INTTYPE, CYREG_PICU6_INTTYPE3 -.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__BSY__MASK, 0x08 -.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC3 -.set SCSI_Noise__BSY__PORT, 6 -.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS -.set SCSI_Noise__BSY__SHIFT, 3 -.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__RST__AG, CYREG_PRT4_AG -.set SCSI_Noise__RST__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__RST__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__RST__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__RST__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__RST__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__RST__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__RST__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__RST__DR, CYREG_PRT4_DR -.set SCSI_Noise__RST__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__RST__INTTYPE, CYREG_PICU4_INTTYPE7 -.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__RST__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__RST__MASK, 0x80 -.set SCSI_Noise__RST__PC, CYREG_PRT4_PC7 -.set SCSI_Noise__RST__PORT, 4 -.set SCSI_Noise__RST__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__RST__PS, CYREG_PRT4_PS -.set SCSI_Noise__RST__SHIFT, 7 -.set SCSI_Noise__RST__SLW, CYREG_PRT4_SLW -.set SCSI_Noise__SEL__AG, CYREG_PRT4_AG -.set SCSI_Noise__SEL__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__SEL__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__SEL__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__SEL__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__SEL__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__SEL__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__SEL__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__SEL__DR, CYREG_PRT4_DR -.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__SEL__INTTYPE, CYREG_PICU4_INTTYPE3 -.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__SEL__MASK, 0x08 -.set SCSI_Noise__SEL__PC, CYREG_PRT4_PC3 -.set SCSI_Noise__SEL__PORT, 4 -.set SCSI_Noise__SEL__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__SEL__PS, CYREG_PRT4_PS -.set SCSI_Noise__SEL__SHIFT, 3 -.set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW +/* USBFS */ +.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_arb_int__INTC_MASK, 0x400000 +.set USBFS_arb_int__INTC_NUMBER, 22 +.set USBFS_arb_int__INTC_PRIOR_NUM, 6 +.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 +.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_bus_reset__INTC_MASK, 0x800000 +.set USBFS_bus_reset__INTC_NUMBER, 23 +.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 +.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 +.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7 +.set USBFS_Dm__0__MASK, 0x80 +.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 +.set USBFS_Dm__0__PORT, 15 +.set USBFS_Dm__0__SHIFT, 7 +.set USBFS_Dm__AG, CYREG_PRT15_AG +.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dm__BIE, CYREG_PRT15_BIE +.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dm__BYP, CYREG_PRT15_BYP +.set USBFS_Dm__CTL, CYREG_PRT15_CTL +.set USBFS_Dm__DM0, CYREG_PRT15_DM0 +.set USBFS_Dm__DM1, CYREG_PRT15_DM1 +.set USBFS_Dm__DM2, CYREG_PRT15_DM2 +.set USBFS_Dm__DR, CYREG_PRT15_DR +.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dm__MASK, 0x80 +.set USBFS_Dm__PORT, 15 +.set USBFS_Dm__PRT, CYREG_PRT15_PRT +.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dm__PS, CYREG_PRT15_PS +.set USBFS_Dm__SHIFT, 7 +.set USBFS_Dm__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6 +.set USBFS_Dp__0__MASK, 0x40 +.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 +.set USBFS_Dp__0__PORT, 15 +.set USBFS_Dp__0__SHIFT, 6 +.set USBFS_Dp__AG, CYREG_PRT15_AG +.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dp__BIE, CYREG_PRT15_BIE +.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dp__BYP, CYREG_PRT15_BYP +.set USBFS_Dp__CTL, CYREG_PRT15_CTL +.set USBFS_Dp__DM0, CYREG_PRT15_DM0 +.set USBFS_Dp__DM1, CYREG_PRT15_DM1 +.set USBFS_Dp__DM2, CYREG_PRT15_DM2 +.set USBFS_Dp__DR, CYREG_PRT15_DR +.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT +.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dp__MASK, 0x40 +.set USBFS_Dp__PORT, 15 +.set USBFS_Dp__PRT, CYREG_PRT15_PRT +.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dp__PS, CYREG_PRT15_PS +.set USBFS_Dp__SHIFT, 6 +.set USBFS_Dp__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 +.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_dp_int__INTC_MASK, 0x1000 +.set USBFS_dp_int__INTC_NUMBER, 12 +.set USBFS_dp_int__INTC_PRIOR_NUM, 7 +.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 +.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_0__INTC_MASK, 0x1000000 +.set USBFS_ep_0__INTC_NUMBER, 24 +.set USBFS_ep_0__INTC_PRIOR_NUM, 7 +.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 +.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_1__INTC_MASK, 0x80 +.set USBFS_ep_1__INTC_NUMBER, 7 +.set USBFS_ep_1__INTC_PRIOR_NUM, 7 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 +.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_2__INTC_MASK, 0x100 +.set USBFS_ep_2__INTC_NUMBER, 8 +.set USBFS_ep_2__INTC_PRIOR_NUM, 7 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 +.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_3__INTC_MASK, 0x200 +.set USBFS_ep_3__INTC_NUMBER, 9 +.set USBFS_ep_3__INTC_PRIOR_NUM, 7 +.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 +.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_4__INTC_MASK, 0x400 +.set USBFS_ep_4__INTC_NUMBER, 10 +.set USBFS_ep_4__INTC_PRIOR_NUM, 7 +.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 +.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_sof_int__INTC_MASK, 0x200000 +.set USBFS_sof_int__INTC_NUMBER, 21 +.set USBFS_sof_int__INTC_PRIOR_NUM, 7 +.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 +.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG +.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG +.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN +.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR +.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG +.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN +.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR +.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG +.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN +.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR +.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG +.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN +.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR +.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG +.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN +.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR +.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG +.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN +.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR +.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG +.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN +.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR +.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG +.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN +.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR +.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN +.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR +.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR +.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA +.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB +.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA +.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB +.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR +.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA +.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB +.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA +.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB +.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR +.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA +.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB +.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA +.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB +.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR +.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA +.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB +.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA +.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB +.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR +.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA +.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB +.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA +.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB +.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR +.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA +.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB +.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA +.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB +.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR +.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA +.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB +.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA +.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB +.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR +.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA +.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB +.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA +.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB +.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE +.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT +.set USBFS_USB__CR0, CYREG_USB_CR0 +.set USBFS_USB__CR1, CYREG_USB_CR1 +.set USBFS_USB__CWA, CYREG_USB_CWA +.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB +.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES +.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB +.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG +.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE +.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE +.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT +.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR +.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 +.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 +.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 +.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 +.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 +.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 +.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 +.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 +.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE +.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 +.set USBFS_USB__PM_ACT_MSK, 0x01 +.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 +.set USBFS_USB__PM_STBY_MSK, 0x01 +.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN +.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR +.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 +.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 +.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 +.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 +.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 +.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 +.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 +.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 +.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 +.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 +.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 +.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 +.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 +.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 +.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 +.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 +.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 +.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 +.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 +.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 +.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 +.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 +.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 +.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 +.set USBFS_USB__SOF0, CYREG_USB_SOF0 +.set USBFS_USB__SOF1, CYREG_USB_SOF1 +.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN +.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 +.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 /* scsiTarget */ .set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0 @@ -2798,89 +2955,6 @@ .set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL .set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB02_ST -/* Debug_Timer_Interrupt */ -.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set Debug_Timer_Interrupt__INTC_MASK, 0x02 -.set Debug_Timer_Interrupt__INTC_NUMBER, 1 -.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7 -.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 -.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0 -.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1 -.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0 -.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1 -.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2 -.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0 -.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1 -.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0 -.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1 -.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3 -.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01 -.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3 -.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01 -.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0 -.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1 -.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0 - -/* SCSI_RX_DMA */ -.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_RX_DMA__DRQ_NUMBER, 0 -.set SCSI_RX_DMA__NUMBEROF_TDS, 0 -.set SCSI_RX_DMA__PRIORITY, 2 -.set SCSI_RX_DMA__TERMIN_EN, 0 -.set SCSI_RX_DMA__TERMIN_SEL, 0 -.set SCSI_RX_DMA__TERMOUT0_EN, 1 -.set SCSI_RX_DMA__TERMOUT0_SEL, 0 -.set SCSI_RX_DMA__TERMOUT1_EN, 0 -.set SCSI_RX_DMA__TERMOUT1_SEL, 0 - -/* SCSI_RX_DMA_COMPLETE */ -.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01 -.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0 -.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 -.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_TX_DMA__DRQ_NUMBER, 1 -.set SCSI_TX_DMA__NUMBEROF_TDS, 0 -.set SCSI_TX_DMA__PRIORITY, 2 -.set SCSI_TX_DMA__TERMIN_EN, 0 -.set SCSI_TX_DMA__TERMIN_SEL, 0 -.set SCSI_TX_DMA__TERMOUT0_EN, 1 -.set SCSI_TX_DMA__TERMOUT0_SEL, 1 -.set SCSI_TX_DMA__TERMOUT1_EN, 0 -.set SCSI_TX_DMA__TERMOUT1_SEL, 0 - -/* SCSI_TX_DMA_COMPLETE */ -.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 -.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 -.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SD_Data_Clk */ -.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 -.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 -.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 -.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 -.set SD_Data_Clk__INDEX, 0x00 -.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set SD_Data_Clk__PM_ACT_MSK, 0x01 -.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set SD_Data_Clk__PM_STBY_MSK, 0x01 - /* timer_clock */ .set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0 .set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1 @@ -2892,146 +2966,53 @@ .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2 .set timer_clock__PM_STBY_MSK, 0x04 -/* SCSI_RST_ISR */ -.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RST_ISR__INTC_MASK, 0x04 -.set SCSI_RST_ISR__INTC_NUMBER, 2 -.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 -.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_SEL_ISR__INTC_MASK, 0x08 -.set SCSI_SEL_ISR__INTC_NUMBER, 3 -.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 -.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_Filtered */ -.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 -.set SCSI_Filtered_sts_sts_reg__0__POS, 0 -.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 -.set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST -.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 -.set SCSI_Filtered_sts_sts_reg__2__POS, 2 -.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 -.set SCSI_Filtered_sts_sts_reg__3__POS, 3 -.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 -.set SCSI_Filtered_sts_sts_reg__4__POS, 4 -.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST - -/* SCSI_CTL_PHASE */ -.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK - -/* SCSI_Glitch_Ctl */ -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK - -/* SCSI_Parity_Error */ -.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST -.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST - /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 .set BCLK__BUS_CLK__KHZ, 50000 .set BCLK__BUS_CLK__MHZ, 50 .set CYDEV_CHIP_DIE_LEOPARD, 1 -.set CYDEV_CHIP_DIE_PSOC4A, 12 -.set CYDEV_CHIP_DIE_PSOC5LP, 19 -.set CYDEV_CHIP_DIE_PSOC5TM, 20 -.set CYDEV_CHIP_DIE_TMA4, 2 +.set CYDEV_CHIP_DIE_PSOC4A, 16 +.set CYDEV_CHIP_DIE_PSOC5LP, 2 +.set CYDEV_CHIP_DIE_PSOC5TM, 3 +.set CYDEV_CHIP_DIE_TMA4, 4 .set CYDEV_CHIP_DIE_UNKNOWN, 0 -.set CYDEV_CHIP_FAMILY_FM0P, 4 -.set CYDEV_CHIP_FAMILY_FM3, 5 -.set CYDEV_CHIP_FAMILY_FM4, 6 +.set CYDEV_CHIP_FAMILY_FM0P, 5 +.set CYDEV_CHIP_FAMILY_FM3, 6 +.set CYDEV_CHIP_FAMILY_FM4, 7 .set CYDEV_CHIP_FAMILY_PSOC3, 1 .set CYDEV_CHIP_FAMILY_PSOC4, 2 .set CYDEV_CHIP_FAMILY_PSOC5, 3 +.set CYDEV_CHIP_FAMILY_PSOC6, 4 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 .set CYDEV_CHIP_JTAG_ID, 0x2E133069 .set CYDEV_CHIP_MEMBER_3A, 1 -.set CYDEV_CHIP_MEMBER_4A, 12 -.set CYDEV_CHIP_MEMBER_4C, 18 -.set CYDEV_CHIP_MEMBER_4D, 8 -.set CYDEV_CHIP_MEMBER_4E, 4 -.set CYDEV_CHIP_MEMBER_4F, 13 -.set CYDEV_CHIP_MEMBER_4G, 2 -.set CYDEV_CHIP_MEMBER_4H, 11 -.set CYDEV_CHIP_MEMBER_4I, 17 -.set CYDEV_CHIP_MEMBER_4J, 9 -.set CYDEV_CHIP_MEMBER_4K, 10 -.set CYDEV_CHIP_MEMBER_4L, 16 -.set CYDEV_CHIP_MEMBER_4M, 15 -.set CYDEV_CHIP_MEMBER_4N, 6 -.set CYDEV_CHIP_MEMBER_4O, 5 -.set CYDEV_CHIP_MEMBER_4P, 14 -.set CYDEV_CHIP_MEMBER_4Q, 7 -.set CYDEV_CHIP_MEMBER_4U, 3 -.set CYDEV_CHIP_MEMBER_5A, 20 -.set CYDEV_CHIP_MEMBER_5B, 19 -.set CYDEV_CHIP_MEMBER_FM3, 24 -.set CYDEV_CHIP_MEMBER_FM4, 25 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 21 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 22 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 23 +.set CYDEV_CHIP_MEMBER_4A, 16 +.set CYDEV_CHIP_MEMBER_4D, 12 +.set CYDEV_CHIP_MEMBER_4E, 6 +.set CYDEV_CHIP_MEMBER_4F, 17 +.set CYDEV_CHIP_MEMBER_4G, 4 +.set CYDEV_CHIP_MEMBER_4H, 15 +.set CYDEV_CHIP_MEMBER_4I, 21 +.set CYDEV_CHIP_MEMBER_4J, 13 +.set CYDEV_CHIP_MEMBER_4K, 14 +.set CYDEV_CHIP_MEMBER_4L, 20 +.set CYDEV_CHIP_MEMBER_4M, 19 +.set CYDEV_CHIP_MEMBER_4N, 9 +.set CYDEV_CHIP_MEMBER_4O, 7 +.set CYDEV_CHIP_MEMBER_4P, 18 +.set CYDEV_CHIP_MEMBER_4Q, 11 +.set CYDEV_CHIP_MEMBER_4R, 8 +.set CYDEV_CHIP_MEMBER_4S, 10 +.set CYDEV_CHIP_MEMBER_4U, 5 +.set CYDEV_CHIP_MEMBER_5A, 3 +.set CYDEV_CHIP_MEMBER_5B, 2 +.set CYDEV_CHIP_MEMBER_6A, 22 +.set CYDEV_CHIP_MEMBER_FM3, 26 +.set CYDEV_CHIP_MEMBER_FM4, 27 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 23 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 24 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 25 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED @@ -3056,7 +3037,6 @@ .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 .set CYDEV_CHIP_REVISION_4A_ES0, 17 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 -.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0 @@ -3075,12 +3055,16 @@ .set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_5A_ES0, 0 .set CYDEV_CHIP_REVISION_5A_ES1, 1 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 .set CYDEV_CHIP_REVISION_5B_ES0, 0 .set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_6A_NO_UDB, 0 +.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0 @@ -3112,7 +3096,7 @@ .set CYDEV_ECC_ENABLE, 0 .set CYDEV_HEAP_SIZE, 0x0400 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 -.set CYDEV_INTR_RISING, 0x0000007E +.set CYDEV_INTR_RISING, 0x0000007F .set CYDEV_IS_EXPORTING_CODE, 0 .set CYDEV_IS_IMPORTING_CODE, 0 .set CYDEV_PROJ_TYPE, 2 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index fcd0bff..0ecaa26 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -1,395 +1,50 @@ +; +; File Name: cyfitteriar.inc +; +; PSoC Creator 4.1 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + #ifndef INCLUDED_CYFITTERIAR_INC #define INCLUDED_CYFITTERIAR_INC INCLUDE cydeviceiar.inc INCLUDE cydeviceiar_trm.inc -/* LED1 */ -LED1__0__INTTYPE EQU CYREG_PICU0_INTTYPE1 -LED1__0__MASK EQU 0x02 -LED1__0__PC EQU CYREG_PRT0_PC1 -LED1__0__PORT EQU 0 -LED1__0__SHIFT EQU 1 -LED1__AG EQU CYREG_PRT0_AG -LED1__AMUX EQU CYREG_PRT0_AMUX -LED1__BIE EQU CYREG_PRT0_BIE -LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK -LED1__BYP EQU CYREG_PRT0_BYP -LED1__CTL EQU CYREG_PRT0_CTL -LED1__DM0 EQU CYREG_PRT0_DM0 -LED1__DM1 EQU CYREG_PRT0_DM1 -LED1__DM2 EQU CYREG_PRT0_DM2 -LED1__DR EQU CYREG_PRT0_DR -LED1__INP_DIS EQU CYREG_PRT0_INP_DIS -LED1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE -LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -LED1__LCD_EN EQU CYREG_PRT0_LCD_EN -LED1__MASK EQU 0x02 -LED1__PORT EQU 0 -LED1__PRT EQU CYREG_PRT0_PRT -LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -LED1__PS EQU CYREG_PRT0_PS -LED1__SHIFT EQU 1 -LED1__SLW EQU CYREG_PRT0_SLW +/* Debug_Timer_Interrupt */ +Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x01 +Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -/* SD_CD */ -SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 -SD_CD__0__MASK EQU 0x20 -SD_CD__0__PC EQU CYREG_PRT3_PC5 -SD_CD__0__PORT EQU 3 -SD_CD__0__SHIFT EQU 5 -SD_CD__AG EQU CYREG_PRT3_AG -SD_CD__AMUX EQU CYREG_PRT3_AMUX -SD_CD__BIE EQU CYREG_PRT3_BIE -SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CD__BYP EQU CYREG_PRT3_BYP -SD_CD__CTL EQU CYREG_PRT3_CTL -SD_CD__DM0 EQU CYREG_PRT3_DM0 -SD_CD__DM1 EQU CYREG_PRT3_DM1 -SD_CD__DM2 EQU CYREG_PRT3_DM2 -SD_CD__DR EQU CYREG_PRT3_DR -SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CD__MASK EQU 0x20 -SD_CD__PORT EQU 3 -SD_CD__PRT EQU CYREG_PRT3_PRT -SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CD__PS EQU CYREG_PRT3_PS -SD_CD__SHIFT EQU 5 -SD_CD__SLW EQU CYREG_PRT3_SLW - -/* SD_CS */ -SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 -SD_CS__0__MASK EQU 0x10 -SD_CS__0__PC EQU CYREG_PRT3_PC4 -SD_CS__0__PORT EQU 3 -SD_CS__0__SHIFT EQU 4 -SD_CS__AG EQU CYREG_PRT3_AG -SD_CS__AMUX EQU CYREG_PRT3_AMUX -SD_CS__BIE EQU CYREG_PRT3_BIE -SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CS__BYP EQU CYREG_PRT3_BYP -SD_CS__CTL EQU CYREG_PRT3_CTL -SD_CS__DM0 EQU CYREG_PRT3_DM0 -SD_CS__DM1 EQU CYREG_PRT3_DM1 -SD_CS__DM2 EQU CYREG_PRT3_DM2 -SD_CS__DR EQU CYREG_PRT3_DR -SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CS__MASK EQU 0x10 -SD_CS__PORT EQU 3 -SD_CS__PRT EQU CYREG_PRT3_PRT -SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CS__PS EQU CYREG_PRT3_PS -SD_CS__SHIFT EQU 4 -SD_CS__SLW EQU CYREG_PRT3_SLW - -/* USBFS_arb_int */ -USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_arb_int__INTC_MASK EQU 0x400000 -USBFS_arb_int__INTC_NUMBER EQU 22 -USBFS_arb_int__INTC_PRIOR_NUM EQU 6 -USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 -USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_bus_reset */ -USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_bus_reset__INTC_MASK EQU 0x800000 -USBFS_bus_reset__INTC_NUMBER EQU 23 -USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 -USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 -USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_Dm */ -USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 -USBFS_Dm__0__MASK EQU 0x80 -USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 -USBFS_Dm__0__PORT EQU 15 -USBFS_Dm__0__SHIFT EQU 7 -USBFS_Dm__AG EQU CYREG_PRT15_AG -USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dm__BIE EQU CYREG_PRT15_BIE -USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dm__BYP EQU CYREG_PRT15_BYP -USBFS_Dm__CTL EQU CYREG_PRT15_CTL -USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dm__DR EQU CYREG_PRT15_DR -USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dm__MASK EQU 0x80 -USBFS_Dm__PORT EQU 15 -USBFS_Dm__PRT EQU CYREG_PRT15_PRT -USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dm__PS EQU CYREG_PRT15_PS -USBFS_Dm__SHIFT EQU 7 -USBFS_Dm__SLW EQU CYREG_PRT15_SLW - -/* USBFS_Dp */ -USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 -USBFS_Dp__0__MASK EQU 0x40 -USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 -USBFS_Dp__0__PORT EQU 15 -USBFS_Dp__0__SHIFT EQU 6 -USBFS_Dp__AG EQU CYREG_PRT15_AG -USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dp__BIE EQU CYREG_PRT15_BIE -USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dp__BYP EQU CYREG_PRT15_BYP -USBFS_Dp__CTL EQU CYREG_PRT15_CTL -USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dp__DR EQU CYREG_PRT15_DR -USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT -USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dp__MASK EQU 0x40 -USBFS_Dp__PORT EQU 15 -USBFS_Dp__PRT EQU CYREG_PRT15_PRT -USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dp__PS EQU CYREG_PRT15_PS -USBFS_Dp__SHIFT EQU 6 -USBFS_Dp__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 - -/* USBFS_dp_int */ -USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_dp_int__INTC_MASK EQU 0x1000 -USBFS_dp_int__INTC_NUMBER EQU 12 -USBFS_dp_int__INTC_PRIOR_NUM EQU 7 -USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 -USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_0 */ -USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_0__INTC_MASK EQU 0x1000000 -USBFS_ep_0__INTC_NUMBER EQU 24 -USBFS_ep_0__INTC_PRIOR_NUM EQU 7 -USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 -USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_1 */ -USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 -USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 -USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_2 */ -USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 -USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 -USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_3 */ -USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 -USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 -USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_4 */ -USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 -USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 -USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_sof_int */ -USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_sof_int__INTC_MASK EQU 0x200000 -USBFS_sof_int__INTC_NUMBER EQU 21 -USBFS_sof_int__INTC_PRIOR_NUM EQU 7 -USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 -USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_USB */ -USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG -USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG -USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN -USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR -USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG -USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN -USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR -USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG -USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN -USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR -USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG -USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN -USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR -USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG -USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN -USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR -USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG -USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN -USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR -USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG -USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN -USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR -USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG -USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN -USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR -USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN -USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR -USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR -USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA -USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB -USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA -USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB -USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR -USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA -USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB -USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA -USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB -USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR -USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA -USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB -USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA -USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB -USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR -USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA -USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB -USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA -USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB -USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR -USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA -USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB -USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA -USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB -USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR -USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA -USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB -USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA -USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB -USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR -USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA -USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB -USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA -USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB -USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR -USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA -USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB -USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA -USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB -USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE -USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT -USBFS_USB__CR0 EQU CYREG_USB_CR0 -USBFS_USB__CR1 EQU CYREG_USB_CR1 -USBFS_USB__CWA EQU CYREG_USB_CWA -USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB -USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES -USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB -USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG -USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE -USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE -USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT -USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR -USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 -USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 -USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 -USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 -USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 -USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 -USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 -USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 -USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE -USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 -USBFS_USB__PM_ACT_MSK EQU 0x01 -USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 -USBFS_USB__PM_STBY_MSK EQU 0x01 -USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN -USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR -USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 -USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 -USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 -USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 -USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 -USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 -USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 -USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 -USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 -USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 -USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 -USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 -USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 -USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 -USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 -USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 -USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 -USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 -USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 -USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 -USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 -USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 -USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 -USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 -USBFS_USB__SOF0 EQU CYREG_USB_SOF0 -USBFS_USB__SOF1 EQU CYREG_USB_SOF1 -USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 -USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 +/* Debug_Timer_TimerHW */ +Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 +Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 +Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 +Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 +Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 +Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 +Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 /* EXTLED */ EXTLED__0__INTTYPE EQU CYREG_PICU0_INTTYPE0 @@ -425,112 +80,116 @@ EXTLED__PS EQU CYREG_PRT0_PS EXTLED__SHIFT EQU 0 EXTLED__SLW EQU CYREG_PRT0_SLW -/* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_RxStsReg__4__POS EQU 4 -SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 -SDCard_BSPIM_RxStsReg__5__POS EQU 5 -SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 -SDCard_BSPIM_RxStsReg__6__POS EQU 6 -SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 -SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 -SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST -SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 -SDCard_BSPIM_TxStsReg__2__POS EQU 2 -SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 -SDCard_BSPIM_TxStsReg__3__POS EQU 3 -SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_TxStsReg__4__POS EQU 4 -SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +/* LED1 */ +LED1__0__INTTYPE EQU CYREG_PICU0_INTTYPE1 +LED1__0__MASK EQU 0x02 +LED1__0__PC EQU CYREG_PRT0_PC1 +LED1__0__PORT EQU 0 +LED1__0__SHIFT EQU 1 +LED1__AG EQU CYREG_PRT0_AG +LED1__AMUX EQU CYREG_PRT0_AMUX +LED1__BIE EQU CYREG_PRT0_BIE +LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK +LED1__BYP EQU CYREG_PRT0_BYP +LED1__CTL EQU CYREG_PRT0_CTL +LED1__DM0 EQU CYREG_PRT0_DM0 +LED1__DM1 EQU CYREG_PRT0_DM1 +LED1__DM2 EQU CYREG_PRT0_DM2 +LED1__DR EQU CYREG_PRT0_DR +LED1__INP_DIS EQU CYREG_PRT0_INP_DIS +LED1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE +LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +LED1__LCD_EN EQU CYREG_PRT0_LCD_EN +LED1__MASK EQU 0x02 +LED1__PORT EQU 0 +LED1__PRT EQU CYREG_PRT0_PRT +LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +LED1__PS EQU CYREG_PRT0_PS +LED1__SHIFT EQU 1 +LED1__SLW EQU CYREG_PRT0_SLW -/* SD_SCK */ -SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 -SD_SCK__0__MASK EQU 0x04 -SD_SCK__0__PC EQU CYREG_PRT3_PC2 -SD_SCK__0__PORT EQU 3 -SD_SCK__0__SHIFT EQU 2 -SD_SCK__AG EQU CYREG_PRT3_AG -SD_SCK__AMUX EQU CYREG_PRT3_AMUX -SD_SCK__BIE EQU CYREG_PRT3_BIE -SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_SCK__BYP EQU CYREG_PRT3_BYP -SD_SCK__CTL EQU CYREG_PRT3_CTL -SD_SCK__DM0 EQU CYREG_PRT3_DM0 -SD_SCK__DM1 EQU CYREG_PRT3_DM1 -SD_SCK__DM2 EQU CYREG_PRT3_DM2 -SD_SCK__DR EQU CYREG_PRT3_DR -SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_SCK__MASK EQU 0x04 -SD_SCK__PORT EQU 3 -SD_SCK__PRT EQU CYREG_PRT3_PRT -SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_SCK__PS EQU CYREG_PRT3_PS -SD_SCK__SHIFT EQU 2 -SD_SCK__SLW EQU CYREG_PRT3_SLW +/* SCSI_CLK */ +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 + +/* SCSI_CTL_PHASE */ +SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK + +/* SCSI_Filtered */ +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST + +/* SCSI_Glitch_Ctl */ +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK /* SCSI_In */ SCSI_In__0__AG EQU CYREG_PRT2_AG @@ -813,8 +472,6 @@ SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT SCSI_In__REQ__PS EQU CYREG_PRT0_PS SCSI_In__REQ__SHIFT EQU 5 SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW - -/* SCSI_In_DBx */ SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE @@ -1260,84 +917,287 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_In_DBx__DB7__SHIFT EQU 4 SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW -/* SD_MISO */ -SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 -SD_MISO__0__MASK EQU 0x02 -SD_MISO__0__PC EQU CYREG_PRT3_PC1 -SD_MISO__0__PORT EQU 3 -SD_MISO__0__SHIFT EQU 1 -SD_MISO__AG EQU CYREG_PRT3_AG -SD_MISO__AMUX EQU CYREG_PRT3_AMUX -SD_MISO__BIE EQU CYREG_PRT3_BIE -SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MISO__BYP EQU CYREG_PRT3_BYP -SD_MISO__CTL EQU CYREG_PRT3_CTL -SD_MISO__DM0 EQU CYREG_PRT3_DM0 -SD_MISO__DM1 EQU CYREG_PRT3_DM1 -SD_MISO__DM2 EQU CYREG_PRT3_DM2 -SD_MISO__DR EQU CYREG_PRT3_DR -SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MISO__MASK EQU 0x02 -SD_MISO__PORT EQU 3 -SD_MISO__PRT EQU CYREG_PRT3_PRT -SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MISO__PS EQU CYREG_PRT3_PS -SD_MISO__SHIFT EQU 1 -SD_MISO__SLW EQU CYREG_PRT3_SLW - -/* SD_MOSI */ -SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 -SD_MOSI__0__MASK EQU 0x08 -SD_MOSI__0__PC EQU CYREG_PRT3_PC3 -SD_MOSI__0__PORT EQU 3 -SD_MOSI__0__SHIFT EQU 3 -SD_MOSI__AG EQU CYREG_PRT3_AG -SD_MOSI__AMUX EQU CYREG_PRT3_AMUX -SD_MOSI__BIE EQU CYREG_PRT3_BIE -SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MOSI__BYP EQU CYREG_PRT3_BYP -SD_MOSI__CTL EQU CYREG_PRT3_CTL -SD_MOSI__DM0 EQU CYREG_PRT3_DM0 -SD_MOSI__DM1 EQU CYREG_PRT3_DM1 -SD_MOSI__DM2 EQU CYREG_PRT3_DM2 -SD_MOSI__DR EQU CYREG_PRT3_DR -SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MOSI__MASK EQU 0x08 -SD_MOSI__PORT EQU 3 -SD_MOSI__PRT EQU CYREG_PRT3_PRT -SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MOSI__PS EQU CYREG_PRT3_PS -SD_MOSI__SHIFT EQU 3 -SD_MOSI__SLW EQU CYREG_PRT3_SLW - -/* SCSI_CLK */ -SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 -SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 -SCSI_CLK__INDEX EQU 0x01 -SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SCSI_CLK__PM_ACT_MSK EQU 0x02 -SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SCSI_CLK__PM_STBY_MSK EQU 0x02 +/* SCSI_Noise */ +SCSI_Noise__0__AG EQU CYREG_PRT2_AG +SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX +SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP +SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL +SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT2_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Noise__0__INTTYPE EQU CYREG_PICU2_INTTYPE0 +SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Noise__0__MASK EQU 0x01 +SCSI_Noise__0__PC EQU CYREG_PRT2_PC0 +SCSI_Noise__0__PORT EQU 2 +SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT +SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT2_PS +SCSI_Noise__0__SHIFT EQU 0 +SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW +SCSI_Noise__1__AG EQU CYREG_PRT6_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT6_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE3 +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__1__MASK EQU 0x08 +SCSI_Noise__1__PC EQU CYREG_PRT6_PC3 +SCSI_Noise__1__PORT EQU 6 +SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT6_PS +SCSI_Noise__1__SHIFT EQU 3 +SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__2__AG EQU CYREG_PRT4_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT4_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__2__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__2__MASK EQU 0x08 +SCSI_Noise__2__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__2__PORT EQU 4 +SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT4_PS +SCSI_Noise__2__SHIFT EQU 3 +SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__3__AG EQU CYREG_PRT4_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT4_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__3__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__3__MASK EQU 0x80 +SCSI_Noise__3__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__3__PORT EQU 4 +SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT4_PS +SCSI_Noise__3__SHIFT EQU 7 +SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__4__AG EQU CYREG_PRT6_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT6_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__4__MASK EQU 0x04 +SCSI_Noise__4__PC EQU CYREG_PRT6_PC2 +SCSI_Noise__4__PORT EQU 6 +SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT6_PS +SCSI_Noise__4__SHIFT EQU 2 +SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x04 +SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2 +SCSI_Noise__ACK__PORT EQU 6 +SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS +SCSI_Noise__ACK__SHIFT EQU 2 +SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG +SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX +SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP +SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL +SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU2_INTTYPE0 +SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Noise__ATN__MASK EQU 0x01 +SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0 +SCSI_Noise__ATN__PORT EQU 2 +SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT +SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS +SCSI_Noise__ATN__SHIFT EQU 0 +SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE3 +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x08 +SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3 +SCSI_Noise__BSY__PORT EQU 6 +SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS +SCSI_Noise__BSY__SHIFT EQU 3 +SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT4_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT4_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__RST__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__RST__MASK EQU 0x80 +SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__RST__PORT EQU 4 +SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT4_PS +SCSI_Noise__RST__SHIFT EQU 7 +SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x08 +SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__SEL__PORT EQU 4 +SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS +SCSI_Noise__SEL__SHIFT EQU 3 +SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW /* SCSI_Out */ SCSI_Out__0__AG EQU CYREG_PRT15_AG @@ -1900,8 +1760,6 @@ SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT SCSI_Out__SEL__PS EQU CYREG_PRT0_PS SCSI_Out__SEL__SHIFT EQU 7 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW - -/* SCSI_Out_Bits */ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 @@ -1936,8 +1794,6 @@ SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK - -/* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL @@ -1958,8 +1814,6 @@ SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK - -/* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE @@ -2409,6 +2263,296 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_Out_DBx__DB7__SHIFT EQU 2 SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW +/* SCSI_Parity_Error */ +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST + +/* SCSI_RST_ISR */ +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x02 +SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_RX_DMA */ +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SDCard_BSPIM */ +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST + +/* SD_CD */ +SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SD_CD__0__MASK EQU 0x20 +SD_CD__0__PC EQU CYREG_PRT3_PC5 +SD_CD__0__PORT EQU 3 +SD_CD__0__SHIFT EQU 5 +SD_CD__AG EQU CYREG_PRT3_AG +SD_CD__AMUX EQU CYREG_PRT3_AMUX +SD_CD__BIE EQU CYREG_PRT3_BIE +SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CD__BYP EQU CYREG_PRT3_BYP +SD_CD__CTL EQU CYREG_PRT3_CTL +SD_CD__DM0 EQU CYREG_PRT3_DM0 +SD_CD__DM1 EQU CYREG_PRT3_DM1 +SD_CD__DM2 EQU CYREG_PRT3_DM2 +SD_CD__DR EQU CYREG_PRT3_DR +SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CD__MASK EQU 0x20 +SD_CD__PORT EQU 3 +SD_CD__PRT EQU CYREG_PRT3_PRT +SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CD__PS EQU CYREG_PRT3_PS +SD_CD__SHIFT EQU 5 +SD_CD__SLW EQU CYREG_PRT3_SLW + +/* SD_CS */ +SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SD_CS__0__MASK EQU 0x10 +SD_CS__0__PC EQU CYREG_PRT3_PC4 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 4 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x10 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 4 +SD_CS__SLW EQU CYREG_PRT3_SLW + +/* SD_Data_Clk */ +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 + +/* SD_MISO */ +SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 +SD_MISO__0__MASK EQU 0x02 +SD_MISO__0__PC EQU CYREG_PRT3_PC1 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 1 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x02 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 1 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +/* SD_MOSI */ +SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_MOSI__0__MASK EQU 0x08 +SD_MOSI__0__PC EQU CYREG_PRT3_PC3 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 3 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x08 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 3 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + /* SD_RX_DMA */ SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 @@ -2420,8 +2564,6 @@ SD_RX_DMA__TERMOUT0_EN EQU 1 SD_RX_DMA__TERMOUT0_SEL EQU 2 SD_RX_DMA__TERMOUT1_EN EQU 0 SD_RX_DMA__TERMOUT1_SEL EQU 0 - -/* SD_RX_DMA_COMPLETE */ SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 @@ -2431,6 +2573,40 @@ SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* SD_SCK */ +SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_SCK__0__MASK EQU 0x04 +SD_SCK__0__PC EQU CYREG_PRT3_PC2 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 2 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x04 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 2 +SD_SCK__SLW EQU CYREG_PRT3_SLW + /* SD_TX_DMA */ SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_TX_DMA__DRQ_NUMBER EQU 3 @@ -2442,8 +2618,6 @@ SD_TX_DMA__TERMOUT0_EN EQU 1 SD_TX_DMA__TERMOUT0_SEL EQU 3 SD_TX_DMA__TERMOUT1_EN EQU 0 SD_TX_DMA__TERMOUT1_SEL EQU 0 - -/* SD_TX_DMA_COMPLETE */ SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 @@ -2453,287 +2627,269 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -/* SCSI_Noise */ -SCSI_Noise__0__AG EQU CYREG_PRT2_AG -SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX -SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE -SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK -SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP -SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL -SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0 -SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1 -SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2 -SCSI_Noise__0__DR EQU CYREG_PRT2_DR -SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS -SCSI_Noise__0__INTTYPE EQU CYREG_PICU2_INTTYPE0 -SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG -SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN -SCSI_Noise__0__MASK EQU 0x01 -SCSI_Noise__0__PC EQU CYREG_PRT2_PC0 -SCSI_Noise__0__PORT EQU 2 -SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT -SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL -SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN -SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 -SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 -SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 -SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 -SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT -SCSI_Noise__0__PS EQU CYREG_PRT2_PS -SCSI_Noise__0__SHIFT EQU 0 -SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW -SCSI_Noise__1__AG EQU CYREG_PRT6_AG -SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__1__DR EQU CYREG_PRT6_DR -SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE3 -SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__1__MASK EQU 0x08 -SCSI_Noise__1__PC EQU CYREG_PRT6_PC3 -SCSI_Noise__1__PORT EQU 6 -SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__1__PS EQU CYREG_PRT6_PS -SCSI_Noise__1__SHIFT EQU 3 -SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__2__AG EQU CYREG_PRT4_AG -SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__2__DR EQU CYREG_PRT4_DR -SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__2__INTTYPE EQU CYREG_PICU4_INTTYPE3 -SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__2__MASK EQU 0x08 -SCSI_Noise__2__PC EQU CYREG_PRT4_PC3 -SCSI_Noise__2__PORT EQU 4 -SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__2__PS EQU CYREG_PRT4_PS -SCSI_Noise__2__SHIFT EQU 3 -SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__3__AG EQU CYREG_PRT4_AG -SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__3__DR EQU CYREG_PRT4_DR -SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__3__INTTYPE EQU CYREG_PICU4_INTTYPE7 -SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__3__MASK EQU 0x80 -SCSI_Noise__3__PC EQU CYREG_PRT4_PC7 -SCSI_Noise__3__PORT EQU 4 -SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__3__PS EQU CYREG_PRT4_PS -SCSI_Noise__3__SHIFT EQU 7 -SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__4__AG EQU CYREG_PRT6_AG -SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__4__DR EQU CYREG_PRT6_DR -SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE2 -SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__4__MASK EQU 0x04 -SCSI_Noise__4__PC EQU CYREG_PRT6_PC2 -SCSI_Noise__4__PORT EQU 6 -SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__4__PS EQU CYREG_PRT6_PS -SCSI_Noise__4__SHIFT EQU 2 -SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG -SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR -SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE2 -SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__ACK__MASK EQU 0x04 -SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2 -SCSI_Noise__ACK__PORT EQU 6 -SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS -SCSI_Noise__ACK__SHIFT EQU 2 -SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG -SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX -SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE -SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK -SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP -SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL -SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0 -SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1 -SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2 -SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR -SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS -SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU2_INTTYPE0 -SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG -SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN -SCSI_Noise__ATN__MASK EQU 0x01 -SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0 -SCSI_Noise__ATN__PORT EQU 2 -SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT -SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL -SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN -SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 -SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 -SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 -SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 -SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT -SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS -SCSI_Noise__ATN__SHIFT EQU 0 -SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW -SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG -SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR -SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE3 -SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__BSY__MASK EQU 0x08 -SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3 -SCSI_Noise__BSY__PORT EQU 6 -SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS -SCSI_Noise__BSY__SHIFT EQU 3 -SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__RST__AG EQU CYREG_PRT4_AG -SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__RST__DR EQU CYREG_PRT4_DR -SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__RST__INTTYPE EQU CYREG_PICU4_INTTYPE7 -SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__RST__MASK EQU 0x80 -SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7 -SCSI_Noise__RST__PORT EQU 4 -SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__RST__PS EQU CYREG_PRT4_PS -SCSI_Noise__RST__SHIFT EQU 7 -SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG -SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR -SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU4_INTTYPE3 -SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__SEL__MASK EQU 0x08 -SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3 -SCSI_Noise__SEL__PORT EQU 4 -SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS -SCSI_Noise__SEL__SHIFT EQU 3 -SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW +/* USBFS */ +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 6 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_PRIOR_NUM EQU 7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_PRIOR_NUM EQU 7 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 /* scsiTarget */ scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 @@ -2798,89 +2954,6 @@ scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST -/* Debug_Timer_Interrupt */ -Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -Debug_Timer_Interrupt__INTC_MASK EQU 0x02 -Debug_Timer_Interrupt__INTC_NUMBER EQU 1 -Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 -Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 -Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 -Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 -Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 -Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 -Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 -Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 -Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 -Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 -Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 -Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 -Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 -Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 -Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 -Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 -Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 -Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 - -/* SCSI_RX_DMA */ -SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 -SCSI_RX_DMA__NUMBEROF_TDS EQU 0 -SCSI_RX_DMA__PRIORITY EQU 2 -SCSI_RX_DMA__TERMIN_EN EQU 0 -SCSI_RX_DMA__TERMIN_SEL EQU 0 -SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 -SCSI_RX_DMA__TERMOUT1_EN EQU 0 -SCSI_RX_DMA__TERMOUT1_SEL EQU 0 - -/* SCSI_RX_DMA_COMPLETE */ -SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 -SCSI_TX_DMA__NUMBEROF_TDS EQU 0 -SCSI_TX_DMA__PRIORITY EQU 2 -SCSI_TX_DMA__TERMIN_EN EQU 0 -SCSI_TX_DMA__TERMIN_SEL EQU 0 -SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 -SCSI_TX_DMA__TERMOUT1_EN EQU 0 -SCSI_TX_DMA__TERMOUT1_SEL EQU 0 - -/* SCSI_TX_DMA_COMPLETE */ -SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 -SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SD_Data_Clk */ -SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 -SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 -SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 -SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Data_Clk__INDEX EQU 0x00 -SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Data_Clk__PM_ACT_MSK EQU 0x01 -SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Data_Clk__PM_STBY_MSK EQU 0x01 - /* timer_clock */ timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 @@ -2892,146 +2965,53 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 -/* SCSI_RST_ISR */ -SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x04 -SCSI_RST_ISR__INTC_NUMBER EQU 2 -SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 -SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 -SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 -SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_Filtered */ -SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Filtered_sts_sts_reg__0__POS EQU 0 -SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 -SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST -SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 -SCSI_Filtered_sts_sts_reg__2__POS EQU 2 -SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 -SCSI_Filtered_sts_sts_reg__3__POS EQU 3 -SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 -SCSI_Filtered_sts_sts_reg__4__POS EQU 4 -SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST - -/* SCSI_CTL_PHASE */ -SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 -SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK - -/* SCSI_Glitch_Ctl */ -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK - -/* SCSI_Parity_Error */ -SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST -SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST - /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 12 -CYDEV_CHIP_DIE_PSOC5LP EQU 19 -CYDEV_CHIP_DIE_PSOC5TM EQU 20 -CYDEV_CHIP_DIE_TMA4 EQU 2 +CYDEV_CHIP_DIE_PSOC4A EQU 16 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 CYDEV_CHIP_DIE_UNKNOWN EQU 0 -CYDEV_CHIP_FAMILY_FM0P EQU 4 -CYDEV_CHIP_FAMILY_FM3 EQU 5 -CYDEV_CHIP_FAMILY_FM4 EQU 6 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 CYDEV_CHIP_FAMILY_PSOC3 EQU 1 CYDEV_CHIP_FAMILY_PSOC4 EQU 2 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 12 -CYDEV_CHIP_MEMBER_4C EQU 18 -CYDEV_CHIP_MEMBER_4D EQU 8 -CYDEV_CHIP_MEMBER_4E EQU 4 -CYDEV_CHIP_MEMBER_4F EQU 13 -CYDEV_CHIP_MEMBER_4G EQU 2 -CYDEV_CHIP_MEMBER_4H EQU 11 -CYDEV_CHIP_MEMBER_4I EQU 17 -CYDEV_CHIP_MEMBER_4J EQU 9 -CYDEV_CHIP_MEMBER_4K EQU 10 -CYDEV_CHIP_MEMBER_4L EQU 16 -CYDEV_CHIP_MEMBER_4M EQU 15 -CYDEV_CHIP_MEMBER_4N EQU 6 -CYDEV_CHIP_MEMBER_4O EQU 5 -CYDEV_CHIP_MEMBER_4P EQU 14 -CYDEV_CHIP_MEMBER_4Q EQU 7 -CYDEV_CHIP_MEMBER_4U EQU 3 -CYDEV_CHIP_MEMBER_5A EQU 20 -CYDEV_CHIP_MEMBER_5B EQU 19 -CYDEV_CHIP_MEMBER_FM3 EQU 24 -CYDEV_CHIP_MEMBER_FM4 EQU 25 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23 +CYDEV_CHIP_MEMBER_4A EQU 16 +CYDEV_CHIP_MEMBER_4D EQU 12 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 17 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 15 +CYDEV_CHIP_MEMBER_4I EQU 21 +CYDEV_CHIP_MEMBER_4J EQU 13 +CYDEV_CHIP_MEMBER_4K EQU 14 +CYDEV_CHIP_MEMBER_4L EQU 20 +CYDEV_CHIP_MEMBER_4M EQU 19 +CYDEV_CHIP_MEMBER_4N EQU 9 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 18 +CYDEV_CHIP_MEMBER_4Q EQU 11 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 10 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 22 +CYDEV_CHIP_MEMBER_FM3 EQU 26 +CYDEV_CHIP_MEMBER_FM4 EQU 27 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -3056,7 +3036,6 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 -CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 @@ -3075,12 +3054,16 @@ CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 @@ -3112,7 +3095,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000007E +CYDEV_INTR_RISING EQU 0x0000007F CYDEV_IS_EXPORTING_CODE EQU 0 CYDEV_IS_IMPORTING_CODE EQU 0 CYDEV_PROJ_TYPE EQU 2 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 85be674..a3484aa 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -1,395 +1,50 @@ +; +; File Name: cyfitterrv.inc +; +; PSoC Creator 4.1 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC INCLUDED_CYFITTERRV_INC EQU 1 GET cydevicerv.inc GET cydevicerv_trm.inc -; LED1 -LED1__0__INTTYPE EQU CYREG_PICU0_INTTYPE1 -LED1__0__MASK EQU 0x02 -LED1__0__PC EQU CYREG_PRT0_PC1 -LED1__0__PORT EQU 0 -LED1__0__SHIFT EQU 1 -LED1__AG EQU CYREG_PRT0_AG -LED1__AMUX EQU CYREG_PRT0_AMUX -LED1__BIE EQU CYREG_PRT0_BIE -LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK -LED1__BYP EQU CYREG_PRT0_BYP -LED1__CTL EQU CYREG_PRT0_CTL -LED1__DM0 EQU CYREG_PRT0_DM0 -LED1__DM1 EQU CYREG_PRT0_DM1 -LED1__DM2 EQU CYREG_PRT0_DM2 -LED1__DR EQU CYREG_PRT0_DR -LED1__INP_DIS EQU CYREG_PRT0_INP_DIS -LED1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE -LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -LED1__LCD_EN EQU CYREG_PRT0_LCD_EN -LED1__MASK EQU 0x02 -LED1__PORT EQU 0 -LED1__PRT EQU CYREG_PRT0_PRT -LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -LED1__PS EQU CYREG_PRT0_PS -LED1__SHIFT EQU 1 -LED1__SLW EQU CYREG_PRT0_SLW +; Debug_Timer_Interrupt +Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x01 +Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -; SD_CD -SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 -SD_CD__0__MASK EQU 0x20 -SD_CD__0__PC EQU CYREG_PRT3_PC5 -SD_CD__0__PORT EQU 3 -SD_CD__0__SHIFT EQU 5 -SD_CD__AG EQU CYREG_PRT3_AG -SD_CD__AMUX EQU CYREG_PRT3_AMUX -SD_CD__BIE EQU CYREG_PRT3_BIE -SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CD__BYP EQU CYREG_PRT3_BYP -SD_CD__CTL EQU CYREG_PRT3_CTL -SD_CD__DM0 EQU CYREG_PRT3_DM0 -SD_CD__DM1 EQU CYREG_PRT3_DM1 -SD_CD__DM2 EQU CYREG_PRT3_DM2 -SD_CD__DR EQU CYREG_PRT3_DR -SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CD__MASK EQU 0x20 -SD_CD__PORT EQU 3 -SD_CD__PRT EQU CYREG_PRT3_PRT -SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CD__PS EQU CYREG_PRT3_PS -SD_CD__SHIFT EQU 5 -SD_CD__SLW EQU CYREG_PRT3_SLW - -; SD_CS -SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 -SD_CS__0__MASK EQU 0x10 -SD_CS__0__PC EQU CYREG_PRT3_PC4 -SD_CS__0__PORT EQU 3 -SD_CS__0__SHIFT EQU 4 -SD_CS__AG EQU CYREG_PRT3_AG -SD_CS__AMUX EQU CYREG_PRT3_AMUX -SD_CS__BIE EQU CYREG_PRT3_BIE -SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CS__BYP EQU CYREG_PRT3_BYP -SD_CS__CTL EQU CYREG_PRT3_CTL -SD_CS__DM0 EQU CYREG_PRT3_DM0 -SD_CS__DM1 EQU CYREG_PRT3_DM1 -SD_CS__DM2 EQU CYREG_PRT3_DM2 -SD_CS__DR EQU CYREG_PRT3_DR -SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CS__MASK EQU 0x10 -SD_CS__PORT EQU 3 -SD_CS__PRT EQU CYREG_PRT3_PRT -SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CS__PS EQU CYREG_PRT3_PS -SD_CS__SHIFT EQU 4 -SD_CS__SLW EQU CYREG_PRT3_SLW - -; USBFS_arb_int -USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_arb_int__INTC_MASK EQU 0x400000 -USBFS_arb_int__INTC_NUMBER EQU 22 -USBFS_arb_int__INTC_PRIOR_NUM EQU 6 -USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 -USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_bus_reset -USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_bus_reset__INTC_MASK EQU 0x800000 -USBFS_bus_reset__INTC_NUMBER EQU 23 -USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 -USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 -USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_Dm -USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 -USBFS_Dm__0__MASK EQU 0x80 -USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 -USBFS_Dm__0__PORT EQU 15 -USBFS_Dm__0__SHIFT EQU 7 -USBFS_Dm__AG EQU CYREG_PRT15_AG -USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dm__BIE EQU CYREG_PRT15_BIE -USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dm__BYP EQU CYREG_PRT15_BYP -USBFS_Dm__CTL EQU CYREG_PRT15_CTL -USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dm__DR EQU CYREG_PRT15_DR -USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dm__MASK EQU 0x80 -USBFS_Dm__PORT EQU 15 -USBFS_Dm__PRT EQU CYREG_PRT15_PRT -USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dm__PS EQU CYREG_PRT15_PS -USBFS_Dm__SHIFT EQU 7 -USBFS_Dm__SLW EQU CYREG_PRT15_SLW - -; USBFS_Dp -USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 -USBFS_Dp__0__MASK EQU 0x40 -USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 -USBFS_Dp__0__PORT EQU 15 -USBFS_Dp__0__SHIFT EQU 6 -USBFS_Dp__AG EQU CYREG_PRT15_AG -USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dp__BIE EQU CYREG_PRT15_BIE -USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dp__BYP EQU CYREG_PRT15_BYP -USBFS_Dp__CTL EQU CYREG_PRT15_CTL -USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dp__DR EQU CYREG_PRT15_DR -USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT -USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dp__MASK EQU 0x40 -USBFS_Dp__PORT EQU 15 -USBFS_Dp__PRT EQU CYREG_PRT15_PRT -USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dp__PS EQU CYREG_PRT15_PS -USBFS_Dp__SHIFT EQU 6 -USBFS_Dp__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 - -; USBFS_dp_int -USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_dp_int__INTC_MASK EQU 0x1000 -USBFS_dp_int__INTC_NUMBER EQU 12 -USBFS_dp_int__INTC_PRIOR_NUM EQU 7 -USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 -USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_0 -USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_0__INTC_MASK EQU 0x1000000 -USBFS_ep_0__INTC_NUMBER EQU 24 -USBFS_ep_0__INTC_PRIOR_NUM EQU 7 -USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 -USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_1 -USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 -USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 -USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_2 -USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 -USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 -USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_3 -USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 -USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 -USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_4 -USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 -USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 -USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_sof_int -USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_sof_int__INTC_MASK EQU 0x200000 -USBFS_sof_int__INTC_NUMBER EQU 21 -USBFS_sof_int__INTC_PRIOR_NUM EQU 7 -USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 -USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_USB -USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG -USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG -USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN -USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR -USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG -USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN -USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR -USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG -USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN -USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR -USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG -USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN -USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR -USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG -USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN -USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR -USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG -USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN -USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR -USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG -USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN -USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR -USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG -USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN -USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR -USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN -USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR -USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR -USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA -USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB -USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA -USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB -USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR -USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA -USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB -USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA -USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB -USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR -USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA -USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB -USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA -USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB -USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR -USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA -USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB -USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA -USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB -USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR -USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA -USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB -USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA -USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB -USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR -USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA -USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB -USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA -USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB -USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR -USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA -USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB -USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA -USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB -USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR -USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA -USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB -USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA -USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB -USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE -USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT -USBFS_USB__CR0 EQU CYREG_USB_CR0 -USBFS_USB__CR1 EQU CYREG_USB_CR1 -USBFS_USB__CWA EQU CYREG_USB_CWA -USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB -USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES -USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB -USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG -USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE -USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE -USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT -USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR -USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 -USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 -USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 -USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 -USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 -USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 -USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 -USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 -USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE -USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 -USBFS_USB__PM_ACT_MSK EQU 0x01 -USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 -USBFS_USB__PM_STBY_MSK EQU 0x01 -USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN -USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR -USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 -USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 -USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 -USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 -USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 -USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 -USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 -USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 -USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 -USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 -USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 -USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 -USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 -USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 -USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 -USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 -USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 -USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 -USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 -USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 -USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 -USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 -USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 -USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 -USBFS_USB__SOF0 EQU CYREG_USB_SOF0 -USBFS_USB__SOF1 EQU CYREG_USB_SOF1 -USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 -USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 +; Debug_Timer_TimerHW +Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 +Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 +Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 +Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 +Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 +Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 +Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 ; EXTLED EXTLED__0__INTTYPE EQU CYREG_PICU0_INTTYPE0 @@ -425,112 +80,116 @@ EXTLED__PS EQU CYREG_PRT0_PS EXTLED__SHIFT EQU 0 EXTLED__SLW EQU CYREG_PRT0_SLW -; SDCard_BSPIM -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_RxStsReg__4__POS EQU 4 -SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 -SDCard_BSPIM_RxStsReg__5__POS EQU 5 -SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 -SDCard_BSPIM_RxStsReg__6__POS EQU 6 -SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 -SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 -SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST -SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 -SDCard_BSPIM_TxStsReg__2__POS EQU 2 -SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 -SDCard_BSPIM_TxStsReg__3__POS EQU 3 -SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_TxStsReg__4__POS EQU 4 -SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +; LED1 +LED1__0__INTTYPE EQU CYREG_PICU0_INTTYPE1 +LED1__0__MASK EQU 0x02 +LED1__0__PC EQU CYREG_PRT0_PC1 +LED1__0__PORT EQU 0 +LED1__0__SHIFT EQU 1 +LED1__AG EQU CYREG_PRT0_AG +LED1__AMUX EQU CYREG_PRT0_AMUX +LED1__BIE EQU CYREG_PRT0_BIE +LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK +LED1__BYP EQU CYREG_PRT0_BYP +LED1__CTL EQU CYREG_PRT0_CTL +LED1__DM0 EQU CYREG_PRT0_DM0 +LED1__DM1 EQU CYREG_PRT0_DM1 +LED1__DM2 EQU CYREG_PRT0_DM2 +LED1__DR EQU CYREG_PRT0_DR +LED1__INP_DIS EQU CYREG_PRT0_INP_DIS +LED1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE +LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +LED1__LCD_EN EQU CYREG_PRT0_LCD_EN +LED1__MASK EQU 0x02 +LED1__PORT EQU 0 +LED1__PRT EQU CYREG_PRT0_PRT +LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +LED1__PS EQU CYREG_PRT0_PS +LED1__SHIFT EQU 1 +LED1__SLW EQU CYREG_PRT0_SLW -; SD_SCK -SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 -SD_SCK__0__MASK EQU 0x04 -SD_SCK__0__PC EQU CYREG_PRT3_PC2 -SD_SCK__0__PORT EQU 3 -SD_SCK__0__SHIFT EQU 2 -SD_SCK__AG EQU CYREG_PRT3_AG -SD_SCK__AMUX EQU CYREG_PRT3_AMUX -SD_SCK__BIE EQU CYREG_PRT3_BIE -SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_SCK__BYP EQU CYREG_PRT3_BYP -SD_SCK__CTL EQU CYREG_PRT3_CTL -SD_SCK__DM0 EQU CYREG_PRT3_DM0 -SD_SCK__DM1 EQU CYREG_PRT3_DM1 -SD_SCK__DM2 EQU CYREG_PRT3_DM2 -SD_SCK__DR EQU CYREG_PRT3_DR -SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_SCK__MASK EQU 0x04 -SD_SCK__PORT EQU 3 -SD_SCK__PRT EQU CYREG_PRT3_PRT -SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_SCK__PS EQU CYREG_PRT3_PS -SD_SCK__SHIFT EQU 2 -SD_SCK__SLW EQU CYREG_PRT3_SLW +; SCSI_CLK +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 + +; SCSI_CTL_PHASE +SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK + +; SCSI_Filtered +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST + +; SCSI_Glitch_Ctl +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK ; SCSI_In SCSI_In__0__AG EQU CYREG_PRT2_AG @@ -813,8 +472,6 @@ SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT SCSI_In__REQ__PS EQU CYREG_PRT0_PS SCSI_In__REQ__SHIFT EQU 5 SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW - -; SCSI_In_DBx SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE @@ -1260,84 +917,287 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_In_DBx__DB7__SHIFT EQU 4 SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW -; SD_MISO -SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 -SD_MISO__0__MASK EQU 0x02 -SD_MISO__0__PC EQU CYREG_PRT3_PC1 -SD_MISO__0__PORT EQU 3 -SD_MISO__0__SHIFT EQU 1 -SD_MISO__AG EQU CYREG_PRT3_AG -SD_MISO__AMUX EQU CYREG_PRT3_AMUX -SD_MISO__BIE EQU CYREG_PRT3_BIE -SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MISO__BYP EQU CYREG_PRT3_BYP -SD_MISO__CTL EQU CYREG_PRT3_CTL -SD_MISO__DM0 EQU CYREG_PRT3_DM0 -SD_MISO__DM1 EQU CYREG_PRT3_DM1 -SD_MISO__DM2 EQU CYREG_PRT3_DM2 -SD_MISO__DR EQU CYREG_PRT3_DR -SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MISO__MASK EQU 0x02 -SD_MISO__PORT EQU 3 -SD_MISO__PRT EQU CYREG_PRT3_PRT -SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MISO__PS EQU CYREG_PRT3_PS -SD_MISO__SHIFT EQU 1 -SD_MISO__SLW EQU CYREG_PRT3_SLW - -; SD_MOSI -SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 -SD_MOSI__0__MASK EQU 0x08 -SD_MOSI__0__PC EQU CYREG_PRT3_PC3 -SD_MOSI__0__PORT EQU 3 -SD_MOSI__0__SHIFT EQU 3 -SD_MOSI__AG EQU CYREG_PRT3_AG -SD_MOSI__AMUX EQU CYREG_PRT3_AMUX -SD_MOSI__BIE EQU CYREG_PRT3_BIE -SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MOSI__BYP EQU CYREG_PRT3_BYP -SD_MOSI__CTL EQU CYREG_PRT3_CTL -SD_MOSI__DM0 EQU CYREG_PRT3_DM0 -SD_MOSI__DM1 EQU CYREG_PRT3_DM1 -SD_MOSI__DM2 EQU CYREG_PRT3_DM2 -SD_MOSI__DR EQU CYREG_PRT3_DR -SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MOSI__MASK EQU 0x08 -SD_MOSI__PORT EQU 3 -SD_MOSI__PRT EQU CYREG_PRT3_PRT -SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MOSI__PS EQU CYREG_PRT3_PS -SD_MOSI__SHIFT EQU 3 -SD_MOSI__SLW EQU CYREG_PRT3_SLW - -; SCSI_CLK -SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 -SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 -SCSI_CLK__INDEX EQU 0x01 -SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SCSI_CLK__PM_ACT_MSK EQU 0x02 -SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SCSI_CLK__PM_STBY_MSK EQU 0x02 +; SCSI_Noise +SCSI_Noise__0__AG EQU CYREG_PRT2_AG +SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX +SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP +SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL +SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT2_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Noise__0__INTTYPE EQU CYREG_PICU2_INTTYPE0 +SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Noise__0__MASK EQU 0x01 +SCSI_Noise__0__PC EQU CYREG_PRT2_PC0 +SCSI_Noise__0__PORT EQU 2 +SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT +SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT2_PS +SCSI_Noise__0__SHIFT EQU 0 +SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW +SCSI_Noise__1__AG EQU CYREG_PRT6_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT6_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE3 +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__1__MASK EQU 0x08 +SCSI_Noise__1__PC EQU CYREG_PRT6_PC3 +SCSI_Noise__1__PORT EQU 6 +SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT6_PS +SCSI_Noise__1__SHIFT EQU 3 +SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__2__AG EQU CYREG_PRT4_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT4_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__2__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__2__MASK EQU 0x08 +SCSI_Noise__2__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__2__PORT EQU 4 +SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT4_PS +SCSI_Noise__2__SHIFT EQU 3 +SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__3__AG EQU CYREG_PRT4_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT4_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__3__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__3__MASK EQU 0x80 +SCSI_Noise__3__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__3__PORT EQU 4 +SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT4_PS +SCSI_Noise__3__SHIFT EQU 7 +SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__4__AG EQU CYREG_PRT6_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT6_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__4__MASK EQU 0x04 +SCSI_Noise__4__PC EQU CYREG_PRT6_PC2 +SCSI_Noise__4__PORT EQU 6 +SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT6_PS +SCSI_Noise__4__SHIFT EQU 2 +SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x04 +SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2 +SCSI_Noise__ACK__PORT EQU 6 +SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS +SCSI_Noise__ACK__SHIFT EQU 2 +SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG +SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX +SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP +SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL +SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU2_INTTYPE0 +SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Noise__ATN__MASK EQU 0x01 +SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0 +SCSI_Noise__ATN__PORT EQU 2 +SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT +SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS +SCSI_Noise__ATN__SHIFT EQU 0 +SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE3 +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x08 +SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3 +SCSI_Noise__BSY__PORT EQU 6 +SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS +SCSI_Noise__BSY__SHIFT EQU 3 +SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT4_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT4_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__RST__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__RST__MASK EQU 0x80 +SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__RST__PORT EQU 4 +SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT4_PS +SCSI_Noise__RST__SHIFT EQU 7 +SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x08 +SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__SEL__PORT EQU 4 +SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS +SCSI_Noise__SEL__SHIFT EQU 3 +SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW ; SCSI_Out SCSI_Out__0__AG EQU CYREG_PRT15_AG @@ -1900,8 +1760,6 @@ SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT SCSI_Out__SEL__PS EQU CYREG_PRT0_PS SCSI_Out__SEL__SHIFT EQU 7 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW - -; SCSI_Out_Bits SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 @@ -1936,8 +1794,6 @@ SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK - -; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL @@ -1958,8 +1814,6 @@ SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK - -; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE @@ -2409,6 +2263,296 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_Out_DBx__DB7__SHIFT EQU 2 SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW +; SCSI_Parity_Error +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST + +; SCSI_RST_ISR +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x02 +SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_RX_DMA +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_SEL_ISR +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_TX_DMA +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SDCard_BSPIM +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST + +; SD_CD +SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SD_CD__0__MASK EQU 0x20 +SD_CD__0__PC EQU CYREG_PRT3_PC5 +SD_CD__0__PORT EQU 3 +SD_CD__0__SHIFT EQU 5 +SD_CD__AG EQU CYREG_PRT3_AG +SD_CD__AMUX EQU CYREG_PRT3_AMUX +SD_CD__BIE EQU CYREG_PRT3_BIE +SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CD__BYP EQU CYREG_PRT3_BYP +SD_CD__CTL EQU CYREG_PRT3_CTL +SD_CD__DM0 EQU CYREG_PRT3_DM0 +SD_CD__DM1 EQU CYREG_PRT3_DM1 +SD_CD__DM2 EQU CYREG_PRT3_DM2 +SD_CD__DR EQU CYREG_PRT3_DR +SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CD__MASK EQU 0x20 +SD_CD__PORT EQU 3 +SD_CD__PRT EQU CYREG_PRT3_PRT +SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CD__PS EQU CYREG_PRT3_PS +SD_CD__SHIFT EQU 5 +SD_CD__SLW EQU CYREG_PRT3_SLW + +; SD_CS +SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SD_CS__0__MASK EQU 0x10 +SD_CS__0__PC EQU CYREG_PRT3_PC4 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 4 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x10 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 4 +SD_CS__SLW EQU CYREG_PRT3_SLW + +; SD_Data_Clk +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 + +; SD_MISO +SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 +SD_MISO__0__MASK EQU 0x02 +SD_MISO__0__PC EQU CYREG_PRT3_PC1 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 1 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x02 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 1 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +; SD_MOSI +SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_MOSI__0__MASK EQU 0x08 +SD_MOSI__0__PC EQU CYREG_PRT3_PC3 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 3 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x08 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 3 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + ; SD_RX_DMA SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 @@ -2420,8 +2564,6 @@ SD_RX_DMA__TERMOUT0_EN EQU 1 SD_RX_DMA__TERMOUT0_SEL EQU 2 SD_RX_DMA__TERMOUT1_EN EQU 0 SD_RX_DMA__TERMOUT1_SEL EQU 0 - -; SD_RX_DMA_COMPLETE SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 @@ -2431,6 +2573,40 @@ SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; SD_SCK +SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_SCK__0__MASK EQU 0x04 +SD_SCK__0__PC EQU CYREG_PRT3_PC2 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 2 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x04 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 2 +SD_SCK__SLW EQU CYREG_PRT3_SLW + ; SD_TX_DMA SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_TX_DMA__DRQ_NUMBER EQU 3 @@ -2442,8 +2618,6 @@ SD_TX_DMA__TERMOUT0_EN EQU 1 SD_TX_DMA__TERMOUT0_SEL EQU 3 SD_TX_DMA__TERMOUT1_EN EQU 0 SD_TX_DMA__TERMOUT1_SEL EQU 0 - -; SD_TX_DMA_COMPLETE SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 @@ -2453,287 +2627,269 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -; SCSI_Noise -SCSI_Noise__0__AG EQU CYREG_PRT2_AG -SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX -SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE -SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK -SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP -SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL -SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0 -SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1 -SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2 -SCSI_Noise__0__DR EQU CYREG_PRT2_DR -SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS -SCSI_Noise__0__INTTYPE EQU CYREG_PICU2_INTTYPE0 -SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG -SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN -SCSI_Noise__0__MASK EQU 0x01 -SCSI_Noise__0__PC EQU CYREG_PRT2_PC0 -SCSI_Noise__0__PORT EQU 2 -SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT -SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL -SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN -SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 -SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 -SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 -SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 -SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT -SCSI_Noise__0__PS EQU CYREG_PRT2_PS -SCSI_Noise__0__SHIFT EQU 0 -SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW -SCSI_Noise__1__AG EQU CYREG_PRT6_AG -SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__1__DR EQU CYREG_PRT6_DR -SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE3 -SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__1__MASK EQU 0x08 -SCSI_Noise__1__PC EQU CYREG_PRT6_PC3 -SCSI_Noise__1__PORT EQU 6 -SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__1__PS EQU CYREG_PRT6_PS -SCSI_Noise__1__SHIFT EQU 3 -SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__2__AG EQU CYREG_PRT4_AG -SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__2__DR EQU CYREG_PRT4_DR -SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__2__INTTYPE EQU CYREG_PICU4_INTTYPE3 -SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__2__MASK EQU 0x08 -SCSI_Noise__2__PC EQU CYREG_PRT4_PC3 -SCSI_Noise__2__PORT EQU 4 -SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__2__PS EQU CYREG_PRT4_PS -SCSI_Noise__2__SHIFT EQU 3 -SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__3__AG EQU CYREG_PRT4_AG -SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__3__DR EQU CYREG_PRT4_DR -SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__3__INTTYPE EQU CYREG_PICU4_INTTYPE7 -SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__3__MASK EQU 0x80 -SCSI_Noise__3__PC EQU CYREG_PRT4_PC7 -SCSI_Noise__3__PORT EQU 4 -SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__3__PS EQU CYREG_PRT4_PS -SCSI_Noise__3__SHIFT EQU 7 -SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__4__AG EQU CYREG_PRT6_AG -SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__4__DR EQU CYREG_PRT6_DR -SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE2 -SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__4__MASK EQU 0x04 -SCSI_Noise__4__PC EQU CYREG_PRT6_PC2 -SCSI_Noise__4__PORT EQU 6 -SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__4__PS EQU CYREG_PRT6_PS -SCSI_Noise__4__SHIFT EQU 2 -SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG -SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR -SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE2 -SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__ACK__MASK EQU 0x04 -SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2 -SCSI_Noise__ACK__PORT EQU 6 -SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS -SCSI_Noise__ACK__SHIFT EQU 2 -SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG -SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX -SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE -SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK -SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP -SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL -SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0 -SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1 -SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2 -SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR -SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS -SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU2_INTTYPE0 -SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG -SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN -SCSI_Noise__ATN__MASK EQU 0x01 -SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0 -SCSI_Noise__ATN__PORT EQU 2 -SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT -SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL -SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN -SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 -SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 -SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 -SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 -SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT -SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS -SCSI_Noise__ATN__SHIFT EQU 0 -SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW -SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG -SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR -SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE3 -SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__BSY__MASK EQU 0x08 -SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3 -SCSI_Noise__BSY__PORT EQU 6 -SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS -SCSI_Noise__BSY__SHIFT EQU 3 -SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__RST__AG EQU CYREG_PRT4_AG -SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__RST__DR EQU CYREG_PRT4_DR -SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__RST__INTTYPE EQU CYREG_PICU4_INTTYPE7 -SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__RST__MASK EQU 0x80 -SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7 -SCSI_Noise__RST__PORT EQU 4 -SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__RST__PS EQU CYREG_PRT4_PS -SCSI_Noise__RST__SHIFT EQU 7 -SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG -SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR -SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU4_INTTYPE3 -SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__SEL__MASK EQU 0x08 -SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3 -SCSI_Noise__SEL__PORT EQU 4 -SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS -SCSI_Noise__SEL__SHIFT EQU 3 -SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW +; USBFS +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 6 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_PRIOR_NUM EQU 7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_PRIOR_NUM EQU 7 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 ; scsiTarget scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 @@ -2798,89 +2954,6 @@ scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST -; Debug_Timer_Interrupt -Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -Debug_Timer_Interrupt__INTC_MASK EQU 0x02 -Debug_Timer_Interrupt__INTC_NUMBER EQU 1 -Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 -Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 -Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; Debug_Timer_TimerHW -Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 -Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 -Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 -Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 -Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 -Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 -Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 -Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 -Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 -Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 -Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 -Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 -Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 -Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 -Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 -Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 - -; SCSI_RX_DMA -SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 -SCSI_RX_DMA__NUMBEROF_TDS EQU 0 -SCSI_RX_DMA__PRIORITY EQU 2 -SCSI_RX_DMA__TERMIN_EN EQU 0 -SCSI_RX_DMA__TERMIN_SEL EQU 0 -SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 -SCSI_RX_DMA__TERMOUT1_EN EQU 0 -SCSI_RX_DMA__TERMOUT1_SEL EQU 0 - -; SCSI_RX_DMA_COMPLETE -SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_TX_DMA -SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 -SCSI_TX_DMA__NUMBEROF_TDS EQU 0 -SCSI_TX_DMA__PRIORITY EQU 2 -SCSI_TX_DMA__TERMIN_EN EQU 0 -SCSI_TX_DMA__TERMIN_SEL EQU 0 -SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 -SCSI_TX_DMA__TERMOUT1_EN EQU 0 -SCSI_TX_DMA__TERMOUT1_SEL EQU 0 - -; SCSI_TX_DMA_COMPLETE -SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 -SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SD_Data_Clk -SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 -SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 -SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 -SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Data_Clk__INDEX EQU 0x00 -SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Data_Clk__PM_ACT_MSK EQU 0x01 -SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Data_Clk__PM_STBY_MSK EQU 0x01 - ; timer_clock timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 @@ -2892,146 +2965,53 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 -; SCSI_RST_ISR -SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x04 -SCSI_RST_ISR__INTC_NUMBER EQU 2 -SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 -SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_SEL_ISR -SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 -SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 -SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_Filtered -SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Filtered_sts_sts_reg__0__POS EQU 0 -SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 -SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST -SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 -SCSI_Filtered_sts_sts_reg__2__POS EQU 2 -SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 -SCSI_Filtered_sts_sts_reg__3__POS EQU 3 -SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 -SCSI_Filtered_sts_sts_reg__4__POS EQU 4 -SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST - -; SCSI_CTL_PHASE -SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 -SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK - -; SCSI_Glitch_Ctl -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK - -; SCSI_Parity_Error -SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST -SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST - ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 12 -CYDEV_CHIP_DIE_PSOC5LP EQU 19 -CYDEV_CHIP_DIE_PSOC5TM EQU 20 -CYDEV_CHIP_DIE_TMA4 EQU 2 +CYDEV_CHIP_DIE_PSOC4A EQU 16 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 CYDEV_CHIP_DIE_UNKNOWN EQU 0 -CYDEV_CHIP_FAMILY_FM0P EQU 4 -CYDEV_CHIP_FAMILY_FM3 EQU 5 -CYDEV_CHIP_FAMILY_FM4 EQU 6 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 CYDEV_CHIP_FAMILY_PSOC3 EQU 1 CYDEV_CHIP_FAMILY_PSOC4 EQU 2 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 12 -CYDEV_CHIP_MEMBER_4C EQU 18 -CYDEV_CHIP_MEMBER_4D EQU 8 -CYDEV_CHIP_MEMBER_4E EQU 4 -CYDEV_CHIP_MEMBER_4F EQU 13 -CYDEV_CHIP_MEMBER_4G EQU 2 -CYDEV_CHIP_MEMBER_4H EQU 11 -CYDEV_CHIP_MEMBER_4I EQU 17 -CYDEV_CHIP_MEMBER_4J EQU 9 -CYDEV_CHIP_MEMBER_4K EQU 10 -CYDEV_CHIP_MEMBER_4L EQU 16 -CYDEV_CHIP_MEMBER_4M EQU 15 -CYDEV_CHIP_MEMBER_4N EQU 6 -CYDEV_CHIP_MEMBER_4O EQU 5 -CYDEV_CHIP_MEMBER_4P EQU 14 -CYDEV_CHIP_MEMBER_4Q EQU 7 -CYDEV_CHIP_MEMBER_4U EQU 3 -CYDEV_CHIP_MEMBER_5A EQU 20 -CYDEV_CHIP_MEMBER_5B EQU 19 -CYDEV_CHIP_MEMBER_FM3 EQU 24 -CYDEV_CHIP_MEMBER_FM4 EQU 25 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23 +CYDEV_CHIP_MEMBER_4A EQU 16 +CYDEV_CHIP_MEMBER_4D EQU 12 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 17 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 15 +CYDEV_CHIP_MEMBER_4I EQU 21 +CYDEV_CHIP_MEMBER_4J EQU 13 +CYDEV_CHIP_MEMBER_4K EQU 14 +CYDEV_CHIP_MEMBER_4L EQU 20 +CYDEV_CHIP_MEMBER_4M EQU 19 +CYDEV_CHIP_MEMBER_4N EQU 9 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 18 +CYDEV_CHIP_MEMBER_4Q EQU 11 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 10 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 22 +CYDEV_CHIP_MEMBER_FM3 EQU 26 +CYDEV_CHIP_MEMBER_FM4 EQU 27 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -3056,7 +3036,6 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 -CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 @@ -3075,12 +3054,16 @@ CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 @@ -3112,7 +3095,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000007E +CYDEV_INTR_RISING EQU 0x0000007F CYDEV_IS_EXPORTING_CODE EQU 0 CYDEV_IS_IMPORTING_CODE EQU 0 CYDEV_PROJ_TYPE EQU 2 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c index 8638ffb..e8e92b1 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -1,21 +1,21 @@ /******************************************************************************* * File Name: cymetadata.c * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file defines all extra memory spaces that need to be included. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. ********************************************************************************/ -#include "cytypes.h" +#include "stdint.h" #if defined(__GNUC__) || defined(__ARMCC_VERSION) @@ -28,7 +28,7 @@ CY_LOADABLE_META_SECTION #else #error "Unsupported toolchain" #endif -const uint8 cy_meta_loadable[] = { +const uint8_t cy_meta_loadable[] = { 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x71u, 0x04u, @@ -49,6 +49,6 @@ CY_CONFIG_ECC_SECTION #else #error "Unsupported toolchain" #endif -const uint8 cy_meta_configecc[] = { +const uint8_t cy_meta_configecc[] = { 0x00u }; diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index 90728b2..9e44652 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: project.h * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * It contains references to all generated header files and should not be modified. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. 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a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj index 23db925..c18637d 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -4,14 +4,14 @@ - + - + @@ -161,7 +161,7 @@ - + @@ -331,7 +331,7 @@ - + @@ -363,7 +363,7 @@ - + @@ -372,7 +372,7 @@ - + @@ -519,7 +519,7 @@ - + @@ -538,7 +538,7 @@ - + @@ -557,7 +557,7 @@ - + @@ -583,7 +583,7 @@ - + @@ -609,7 +609,7 @@ - + @@ -635,7 +635,7 @@ - + @@ -668,7 +668,7 @@ - + @@ -694,7 +694,7 @@ - + @@ -713,7 +713,7 @@ - + @@ -732,7 +732,7 @@ - + @@ -758,7 +758,7 @@ - + @@ -791,7 +791,7 @@ - + @@ -824,7 +824,7 @@ - + @@ -857,7 +857,7 @@ - + @@ -890,7 +890,7 @@ - + @@ -923,7 +923,7 @@ - + @@ -949,7 +949,7 @@ - + @@ -982,7 +982,7 @@ - + @@ -1029,7 +1029,7 @@ - + @@ -1062,7 +1062,7 @@ - + @@ -1235,7 +1235,7 @@ - + @@ -1261,7 +1261,7 @@ - + @@ -1294,7 +1294,7 @@ - + @@ -1327,7 +1327,7 @@ - + @@ -1528,7 +1528,7 @@ - + @@ -1554,7 +1554,7 @@ - + @@ -1580,7 +1580,7 @@ - + @@ -1606,7 +1606,7 @@ - + @@ -1639,7 +1639,7 @@ - + @@ -1665,7 +1665,7 @@ - + @@ -1691,7 +1691,7 @@ - + @@ -1717,7 +1717,7 @@ - + @@ -1743,7 +1743,7 @@ - + @@ -1769,7 +1769,7 @@ - + @@ -1802,7 +1802,7 @@ - + @@ -1835,7 +1835,7 @@ - + @@ -1868,7 +1868,7 @@ - + @@ -1894,7 +1894,7 @@ - + @@ -1920,7 +1920,7 @@ - + @@ -1953,7 +1953,7 @@ - + @@ -1979,7 +1979,7 @@ - + @@ -2005,7 +2005,7 @@ - + @@ -2024,7 +2024,7 @@ - + @@ -2050,7 +2050,7 @@ - + @@ -2076,7 +2076,7 @@ - + @@ -2102,7 +2102,7 @@ - + @@ -2172,7 +2172,7 @@ - + @@ -2202,7 +2202,7 @@ - + @@ -2281,10 +2281,10 @@ - - - + + + @@ -2297,6 +2297,15 @@ + + + + + + + + + @@ -2315,10 +2324,10 @@ - - - + + + @@ -2331,6 +2340,15 @@ + + + + + + + + + @@ -2349,10 +2367,10 @@ - - - + + + @@ -2365,6 +2383,15 @@ + + + + + + + + + @@ -2383,10 +2410,10 @@ - - - + + + @@ -2399,6 +2426,15 @@ + + + + + + + + + @@ -2421,10 +2457,10 @@ - - - + + + @@ -2437,6 +2473,15 @@ + + + + + + + + + @@ -2455,10 +2500,10 @@ - - - + + + @@ -2471,6 +2516,15 @@ + + + + + + + + + @@ -2489,10 +2543,10 @@ - - - + + + @@ -2505,6 +2559,15 @@ + + + + + + + + + @@ -2523,10 +2586,10 @@ - - - + + + @@ -2539,14 +2602,31 @@ + + + + + + + + + + + + + + + + + @@ -2557,6 +2637,7 @@ + @@ -2567,6 +2648,7 @@ + @@ -2576,12 +2658,15 @@ + + + @@ -2592,6 +2677,7 @@ + @@ -2601,12 +2687,15 @@ + + + @@ -2617,6 +2706,7 @@ + @@ -2626,12 +2716,15 @@ + + + @@ -2642,6 +2735,7 @@ + @@ -2651,31 +2745,33 @@ + + + + + - - - + + - - diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h index f974855..4db2bae 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h @@ -17,7 +17,15 @@ #if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */ #define CY_CONTROL_REG_SCSI_CTL_PHASE_H -#include "cytypes.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h index 87326f5..c64ec62 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h @@ -17,8 +17,16 @@ #if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */ #define CY_STATUS_REG_SCSI_Filtered_H -#include "cytypes.h" -#include "CyLib.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" + #include "CyLib.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h index d6c0d24..88e1557 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h @@ -17,7 +17,15 @@ #if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */ #define CY_CONTROL_REG_SCSI_Glitch_Ctl_H -#include "cytypes.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h index 94ea62a..1ada4ee 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h @@ -17,7 +17,15 @@ #if !defined(CY_CONTROL_REG_SCSI_Out_Bits_H) /* CY_CONTROL_REG_SCSI_Out_Bits_H */ #define CY_CONTROL_REG_SCSI_Out_Bits_H -#include "cytypes.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h index e473a95..725873f 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h @@ -17,7 +17,15 @@ #if !defined(CY_CONTROL_REG_SCSI_Out_Ctl_H) /* CY_CONTROL_REG_SCSI_Out_Ctl_H */ #define CY_CONTROL_REG_SCSI_Out_Ctl_H -#include "cytypes.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h index 532aff3..de1ddc8 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h @@ -17,8 +17,16 @@ #if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */ #define CY_STATUS_REG_SCSI_Parity_Error_H -#include "cytypes.h" -#include "CyLib.h" +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" + #include "CyLib.h" +#else + #include "syslib/cy_syslib.h" +#endif /*************************************** diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h index b209145..45b000e 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h @@ -19,15 +19,9 @@ #if !defined(CY_SPIM_SDCard_H) #define CY_SPIM_SDCard_H -#include "cytypes.h" #include "cyfitter.h" -#include "CyLib.h" - -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component SPI_Master_v2_50 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ +#include "cytypes.h" +#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */ /*************************************** diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h index 952bd9d..0cccfc8 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice.h * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h index 89243ea..67ddde7 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice_trm.h * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc index a80cb2b..250050a 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu.inc * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc index cd2972d..e8bf75d 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu_trm.inc * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc index 78618ea..e6ddc72 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.0 Update 1 +; PSoC Creator 4.1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc index 5a152e4..8b2eb91 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar_trm.inc ; -; PSoC Creator 4.0 Update 1 +; PSoC Creator 4.1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc index 44f36d2..66261a1 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.0 Update 1 +; PSoC Creator 4.1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc index 77f5e53..cc1c324 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv_trm.inc ; -; PSoC Creator 4.0 Update 1 +; PSoC Creator 4.1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 4d9d0a2..cc0e752 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -1,8 +1,52 @@ +/******************************************************************************* +* File Name: cyfitter.h +* +* PSoC Creator 4.1 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + #ifndef INCLUDED_CYFITTER_H #define INCLUDED_CYFITTER_H #include "cydevice.h" #include "cydevice_trm.h" +/* Debug_Timer_Interrupt */ +#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define Debug_Timer_Interrupt__INTC_MASK 0x01u +#define Debug_Timer_Interrupt__INTC_NUMBER 0u +#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u +#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* Debug_Timer_TimerHW */ +#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0 +#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1 +#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0 +#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1 +#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2 +#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 +#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 +#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0 +#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1 +#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 +#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u +#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 +#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u +#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0 +#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1 +#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0 + /* LED1 */ #define LED1__0__INTTYPE CYREG_PICU12_INTTYPE0 #define LED1__0__MASK 0x01u @@ -41,438 +85,86 @@ #define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ #define LED1__SLW CYREG_PRT12_SLW -/* SD_CS */ -#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE5 -#define SD_CS__0__MASK 0x20u -#define SD_CS__0__PC CYREG_PRT3_PC5 -#define SD_CS__0__PORT 3u -#define SD_CS__0__SHIFT 5u -#define SD_CS__AG CYREG_PRT3_AG -#define SD_CS__AMUX CYREG_PRT3_AMUX -#define SD_CS__BIE CYREG_PRT3_BIE -#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_CS__BYP CYREG_PRT3_BYP -#define SD_CS__CTL CYREG_PRT3_CTL -#define SD_CS__DM0 CYREG_PRT3_DM0 -#define SD_CS__DM1 CYREG_PRT3_DM1 -#define SD_CS__DM2 CYREG_PRT3_DM2 -#define SD_CS__DR CYREG_PRT3_DR -#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS -#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN -#define SD_CS__MASK 0x20u -#define SD_CS__PORT 3u -#define SD_CS__PRT CYREG_PRT3_PRT -#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_CS__PS CYREG_PRT3_PS -#define SD_CS__SHIFT 5u -#define SD_CS__SLW CYREG_PRT3_SLW +/* SCSI_CLK */ +#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 +#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 +#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2 +#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u +#define SCSI_CLK__INDEX 0x01u +#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SCSI_CLK__PM_ACT_MSK 0x02u +#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SCSI_CLK__PM_STBY_MSK 0x02u -/* USBFS_arb_int */ -#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_arb_int__INTC_MASK 0x400000u -#define USBFS_arb_int__INTC_NUMBER 22u -#define USBFS_arb_int__INTC_PRIOR_NUM 6u -#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 -#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* SCSI_CTL_PHASE */ +#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK -/* USBFS_bus_reset */ -#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_bus_reset__INTC_MASK 0x800000u -#define USBFS_bus_reset__INTC_NUMBER 23u -#define USBFS_bus_reset__INTC_PRIOR_NUM 7u -#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 -#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* SCSI_Filtered */ +#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u +#define SCSI_Filtered_sts_sts_reg__0__POS 0 +#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u +#define SCSI_Filtered_sts_sts_reg__1__POS 1 +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST +#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u +#define SCSI_Filtered_sts_sts_reg__2__POS 2 +#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u +#define SCSI_Filtered_sts_sts_reg__3__POS 3 +#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u +#define SCSI_Filtered_sts_sts_reg__4__POS 4 +#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK +#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST -/* USBFS_Dm */ -#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7 -#define USBFS_Dm__0__MASK 0x80u -#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 -#define USBFS_Dm__0__PORT 15u -#define USBFS_Dm__0__SHIFT 7u -#define USBFS_Dm__AG CYREG_PRT15_AG -#define USBFS_Dm__AMUX CYREG_PRT15_AMUX -#define USBFS_Dm__BIE CYREG_PRT15_BIE -#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK -#define USBFS_Dm__BYP CYREG_PRT15_BYP -#define USBFS_Dm__CTL CYREG_PRT15_CTL -#define USBFS_Dm__DM0 CYREG_PRT15_DM0 -#define USBFS_Dm__DM1 CYREG_PRT15_DM1 -#define USBFS_Dm__DM2 CYREG_PRT15_DM2 -#define USBFS_Dm__DR CYREG_PRT15_DR -#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS -#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE -#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG -#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN -#define USBFS_Dm__MASK 0x80u -#define USBFS_Dm__PORT 15u -#define USBFS_Dm__PRT CYREG_PRT15_PRT -#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL -#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN -#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 -#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 -#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 -#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 -#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT -#define USBFS_Dm__PS CYREG_PRT15_PS -#define USBFS_Dm__SHIFT 7u -#define USBFS_Dm__SLW CYREG_PRT15_SLW - -/* USBFS_Dp */ -#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6 -#define USBFS_Dp__0__MASK 0x40u -#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 -#define USBFS_Dp__0__PORT 15u -#define USBFS_Dp__0__SHIFT 6u -#define USBFS_Dp__AG CYREG_PRT15_AG -#define USBFS_Dp__AMUX CYREG_PRT15_AMUX -#define USBFS_Dp__BIE CYREG_PRT15_BIE -#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK -#define USBFS_Dp__BYP CYREG_PRT15_BYP -#define USBFS_Dp__CTL CYREG_PRT15_CTL -#define USBFS_Dp__DM0 CYREG_PRT15_DM0 -#define USBFS_Dp__DM1 CYREG_PRT15_DM1 -#define USBFS_Dp__DM2 CYREG_PRT15_DM2 -#define USBFS_Dp__DR CYREG_PRT15_DR -#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS -#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT -#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE -#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG -#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN -#define USBFS_Dp__MASK 0x40u -#define USBFS_Dp__PORT 15u -#define USBFS_Dp__PRT CYREG_PRT15_PRT -#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL -#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN -#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 -#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 -#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 -#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 -#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT -#define USBFS_Dp__PS CYREG_PRT15_PS -#define USBFS_Dp__SHIFT 6u -#define USBFS_Dp__SLW CYREG_PRT15_SLW -#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 - -/* USBFS_dp_int */ -#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_dp_int__INTC_MASK 0x1000u -#define USBFS_dp_int__INTC_NUMBER 12u -#define USBFS_dp_int__INTC_PRIOR_NUM 7u -#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 -#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_0 */ -#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_0__INTC_MASK 0x1000000u -#define USBFS_ep_0__INTC_NUMBER 24u -#define USBFS_ep_0__INTC_PRIOR_NUM 7u -#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 -#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_1 */ -#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x80u -#define USBFS_ep_1__INTC_NUMBER 7u -#define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 -#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_2 */ -#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x100u -#define USBFS_ep_2__INTC_NUMBER 8u -#define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 -#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_3 */ -#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_3__INTC_MASK 0x200u -#define USBFS_ep_3__INTC_NUMBER 9u -#define USBFS_ep_3__INTC_PRIOR_NUM 7u -#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 -#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_4 */ -#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_4__INTC_MASK 0x400u -#define USBFS_ep_4__INTC_NUMBER 10u -#define USBFS_ep_4__INTC_PRIOR_NUM 7u -#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 -#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_sof_int */ -#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_sof_int__INTC_MASK 0x200000u -#define USBFS_sof_int__INTC_NUMBER 21u -#define USBFS_sof_int__INTC_PRIOR_NUM 7u -#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 -#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_USB */ -#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG -#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG -#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN -#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR -#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG -#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN -#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR -#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG -#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN -#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR -#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG -#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN -#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR -#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG -#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN -#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR -#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG -#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN -#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR -#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG -#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN -#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR -#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG -#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN -#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR -#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN -#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR -#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR -#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA -#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB -#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA -#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB -#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR -#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA -#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB -#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA -#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB -#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR -#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA -#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB -#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA -#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB -#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR -#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA -#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB -#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA -#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB -#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR -#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA -#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB -#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA -#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB -#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR -#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA -#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB -#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA -#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB -#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR -#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA -#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB -#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA -#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB -#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR -#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA -#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB -#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA -#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB -#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE -#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT -#define USBFS_USB__CR0 CYREG_USB_CR0 -#define USBFS_USB__CR1 CYREG_USB_CR1 -#define USBFS_USB__CWA CYREG_USB_CWA -#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB -#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES -#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB -#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG -#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE -#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE -#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT -#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR -#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 -#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 -#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 -#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 -#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 -#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 -#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 -#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 -#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE -#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 -#define USBFS_USB__PM_ACT_MSK 0x01u -#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 -#define USBFS_USB__PM_STBY_MSK 0x01u -#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN -#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR -#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 -#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 -#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 -#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 -#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 -#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 -#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 -#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 -#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 -#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 -#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 -#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 -#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 -#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 -#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 -#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 -#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 -#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 -#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 -#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 -#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 -#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 -#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 -#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 -#define USBFS_USB__SOF0 CYREG_USB_SOF0 -#define USBFS_USB__SOF1 CYREG_USB_SOF1 -#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN -#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 -#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 - -/* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST -#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u -#define SDCard_BSPIM_RxStsReg__4__POS 4 -#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u -#define SDCard_BSPIM_RxStsReg__5__POS 5 -#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u -#define SDCard_BSPIM_RxStsReg__6__POS 6 -#define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK -#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 -#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u -#define SDCard_BSPIM_TxStsReg__0__POS 0 -#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u -#define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST -#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u -#define SDCard_BSPIM_TxStsReg__2__POS 2 -#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u -#define SDCard_BSPIM_TxStsReg__3__POS 3 -#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u -#define SDCard_BSPIM_TxStsReg__4__POS 4 -#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST - -/* SD_SCK */ -#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE3 -#define SD_SCK__0__MASK 0x08u -#define SD_SCK__0__PC CYREG_PRT3_PC3 -#define SD_SCK__0__PORT 3u -#define SD_SCK__0__SHIFT 3u -#define SD_SCK__AG CYREG_PRT3_AG -#define SD_SCK__AMUX CYREG_PRT3_AMUX -#define SD_SCK__BIE CYREG_PRT3_BIE -#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_SCK__BYP CYREG_PRT3_BYP -#define SD_SCK__CTL CYREG_PRT3_CTL -#define SD_SCK__DM0 CYREG_PRT3_DM0 -#define SD_SCK__DM1 CYREG_PRT3_DM1 -#define SD_SCK__DM2 CYREG_PRT3_DM2 -#define SD_SCK__DR CYREG_PRT3_DR -#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS -#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN -#define SD_SCK__MASK 0x08u -#define SD_SCK__PORT 3u -#define SD_SCK__PRT CYREG_PRT3_PRT -#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_SCK__PS CYREG_PRT3_PS -#define SD_SCK__SHIFT 3u -#define SD_SCK__SLW CYREG_PRT3_SLW +/* SCSI_Glitch_Ctl */ +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK /* SCSI_In */ #define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1 @@ -512,8 +204,6 @@ #define SCSI_In__PS CYREG_PRT6_PS #define SCSI_In__SHIFT 1u #define SCSI_In__SLW CYREG_PRT6_SLW - -/* SCSI_In_DBx */ #define SCSI_In_DBx__0__AG CYREG_PRT6_AG #define SCSI_In_DBx__0__AMUX CYREG_PRT6_AMUX #define SCSI_In_DBx__0__BIE CYREG_PRT6_BIE @@ -961,118 +651,287 @@ #define SCSI_In_DBx__DB7__SHIFT 3u #define SCSI_In_DBx__DB7__SLW CYREG_PRT6_SLW -/* SD_MISO */ -#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE2 -#define SD_MISO__0__MASK 0x04u -#define SD_MISO__0__PC CYREG_PRT3_PC2 -#define SD_MISO__0__PORT 3u -#define SD_MISO__0__SHIFT 2u -#define SD_MISO__AG CYREG_PRT3_AG -#define SD_MISO__AMUX CYREG_PRT3_AMUX -#define SD_MISO__BIE CYREG_PRT3_BIE -#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_MISO__BYP CYREG_PRT3_BYP -#define SD_MISO__CTL CYREG_PRT3_CTL -#define SD_MISO__DM0 CYREG_PRT3_DM0 -#define SD_MISO__DM1 CYREG_PRT3_DM1 -#define SD_MISO__DM2 CYREG_PRT3_DM2 -#define SD_MISO__DR CYREG_PRT3_DR -#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS -#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN -#define SD_MISO__MASK 0x04u -#define SD_MISO__PORT 3u -#define SD_MISO__PRT CYREG_PRT3_PRT -#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_MISO__PS CYREG_PRT3_PS -#define SD_MISO__SHIFT 2u -#define SD_MISO__SLW CYREG_PRT3_SLW - -/* SD_MOSI */ -#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE4 -#define SD_MOSI__0__MASK 0x10u -#define SD_MOSI__0__PC CYREG_PRT3_PC4 -#define SD_MOSI__0__PORT 3u -#define SD_MOSI__0__SHIFT 4u -#define SD_MOSI__AG CYREG_PRT3_AG -#define SD_MOSI__AMUX CYREG_PRT3_AMUX -#define SD_MOSI__BIE CYREG_PRT3_BIE -#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_MOSI__BYP CYREG_PRT3_BYP -#define SD_MOSI__CTL CYREG_PRT3_CTL -#define SD_MOSI__DM0 CYREG_PRT3_DM0 -#define SD_MOSI__DM1 CYREG_PRT3_DM1 -#define SD_MOSI__DM2 CYREG_PRT3_DM2 -#define SD_MOSI__DR CYREG_PRT3_DR -#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS -#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN -#define SD_MOSI__MASK 0x10u -#define SD_MOSI__PORT 3u -#define SD_MOSI__PRT CYREG_PRT3_PRT -#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_MOSI__PS CYREG_PRT3_PS -#define SD_MOSI__SHIFT 4u -#define SD_MOSI__SLW CYREG_PRT3_SLW - -/* TERM_EN */ -#define TERM_EN__0__INTTYPE CYREG_PICU15_INTTYPE3 -#define TERM_EN__0__MASK 0x08u -#define TERM_EN__0__PC CYREG_IO_PC_PRT15_PC3 -#define TERM_EN__0__PORT 15u -#define TERM_EN__0__SHIFT 3u -#define TERM_EN__AG CYREG_PRT15_AG -#define TERM_EN__AMUX CYREG_PRT15_AMUX -#define TERM_EN__BIE CYREG_PRT15_BIE -#define TERM_EN__BIT_MASK CYREG_PRT15_BIT_MASK -#define TERM_EN__BYP CYREG_PRT15_BYP -#define TERM_EN__CTL CYREG_PRT15_CTL -#define TERM_EN__DM0 CYREG_PRT15_DM0 -#define TERM_EN__DM1 CYREG_PRT15_DM1 -#define TERM_EN__DM2 CYREG_PRT15_DM2 -#define TERM_EN__DR CYREG_PRT15_DR -#define TERM_EN__INP_DIS CYREG_PRT15_INP_DIS -#define TERM_EN__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE -#define TERM_EN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG -#define TERM_EN__LCD_EN CYREG_PRT15_LCD_EN -#define TERM_EN__MASK 0x08u -#define TERM_EN__PORT 15u -#define TERM_EN__PRT CYREG_PRT15_PRT -#define TERM_EN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL -#define TERM_EN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN -#define TERM_EN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 -#define TERM_EN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 -#define TERM_EN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 -#define TERM_EN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 -#define TERM_EN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT -#define TERM_EN__PS CYREG_PRT15_PS -#define TERM_EN__SHIFT 3u -#define TERM_EN__SLW CYREG_PRT15_SLW - -/* SCSI_CLK */ -#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 -#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 -#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2 -#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u -#define SCSI_CLK__INDEX 0x01u -#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define SCSI_CLK__PM_ACT_MSK 0x02u -#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define SCSI_CLK__PM_STBY_MSK 0x02u +/* SCSI_Noise */ +#define SCSI_Noise__0__AG CYREG_PRT4_AG +#define SCSI_Noise__0__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__0__BIE CYREG_PRT4_BIE +#define SCSI_Noise__0__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__0__BYP CYREG_PRT4_BYP +#define SCSI_Noise__0__CTL CYREG_PRT4_CTL +#define SCSI_Noise__0__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__0__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__0__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__0__DR CYREG_PRT4_DR +#define SCSI_Noise__0__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__0__INTTYPE CYREG_PICU4_INTTYPE7 +#define SCSI_Noise__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__0__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__0__MASK 0x80u +#define SCSI_Noise__0__PC CYREG_PRT4_PC7 +#define SCSI_Noise__0__PORT 4u +#define SCSI_Noise__0__PRT CYREG_PRT4_PRT +#define SCSI_Noise__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__0__PS CYREG_PRT4_PS +#define SCSI_Noise__0__SHIFT 7u +#define SCSI_Noise__0__SLW CYREG_PRT4_SLW +#define SCSI_Noise__1__AG CYREG_PRT4_AG +#define SCSI_Noise__1__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__1__BIE CYREG_PRT4_BIE +#define SCSI_Noise__1__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__1__BYP CYREG_PRT4_BYP +#define SCSI_Noise__1__CTL CYREG_PRT4_CTL +#define SCSI_Noise__1__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__1__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__1__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__1__DR CYREG_PRT4_DR +#define SCSI_Noise__1__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__1__INTTYPE CYREG_PICU4_INTTYPE5 +#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__1__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__1__MASK 0x20u +#define SCSI_Noise__1__PC CYREG_PRT4_PC5 +#define SCSI_Noise__1__PORT 4u +#define SCSI_Noise__1__PRT CYREG_PRT4_PRT +#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__1__PS CYREG_PRT4_PS +#define SCSI_Noise__1__SHIFT 5u +#define SCSI_Noise__1__SLW CYREG_PRT4_SLW +#define SCSI_Noise__2__AG CYREG_PRT0_AG +#define SCSI_Noise__2__AMUX CYREG_PRT0_AMUX +#define SCSI_Noise__2__BIE CYREG_PRT0_BIE +#define SCSI_Noise__2__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Noise__2__BYP CYREG_PRT0_BYP +#define SCSI_Noise__2__CTL CYREG_PRT0_CTL +#define SCSI_Noise__2__DM0 CYREG_PRT0_DM0 +#define SCSI_Noise__2__DM1 CYREG_PRT0_DM1 +#define SCSI_Noise__2__DM2 CYREG_PRT0_DM2 +#define SCSI_Noise__2__DR CYREG_PRT0_DR +#define SCSI_Noise__2__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Noise__2__INTTYPE CYREG_PICU0_INTTYPE2 +#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Noise__2__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Noise__2__MASK 0x04u +#define SCSI_Noise__2__PC CYREG_PRT0_PC2 +#define SCSI_Noise__2__PORT 0u +#define SCSI_Noise__2__PRT CYREG_PRT0_PRT +#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Noise__2__PS CYREG_PRT0_PS +#define SCSI_Noise__2__SHIFT 2u +#define SCSI_Noise__2__SLW CYREG_PRT0_SLW +#define SCSI_Noise__3__AG CYREG_PRT0_AG +#define SCSI_Noise__3__AMUX CYREG_PRT0_AMUX +#define SCSI_Noise__3__BIE CYREG_PRT0_BIE +#define SCSI_Noise__3__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Noise__3__BYP CYREG_PRT0_BYP +#define SCSI_Noise__3__CTL CYREG_PRT0_CTL +#define SCSI_Noise__3__DM0 CYREG_PRT0_DM0 +#define SCSI_Noise__3__DM1 CYREG_PRT0_DM1 +#define SCSI_Noise__3__DM2 CYREG_PRT0_DM2 +#define SCSI_Noise__3__DR CYREG_PRT0_DR +#define SCSI_Noise__3__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Noise__3__INTTYPE CYREG_PICU0_INTTYPE6 +#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Noise__3__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Noise__3__MASK 0x40u +#define SCSI_Noise__3__PC CYREG_PRT0_PC6 +#define SCSI_Noise__3__PORT 0u +#define SCSI_Noise__3__PRT CYREG_PRT0_PRT +#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Noise__3__PS CYREG_PRT0_PS +#define SCSI_Noise__3__SHIFT 6u +#define SCSI_Noise__3__SLW CYREG_PRT0_SLW +#define SCSI_Noise__4__AG CYREG_PRT4_AG +#define SCSI_Noise__4__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__4__BIE CYREG_PRT4_BIE +#define SCSI_Noise__4__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__4__BYP CYREG_PRT4_BYP +#define SCSI_Noise__4__CTL CYREG_PRT4_CTL +#define SCSI_Noise__4__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__4__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__4__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__4__DR CYREG_PRT4_DR +#define SCSI_Noise__4__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__4__INTTYPE CYREG_PICU4_INTTYPE3 +#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__4__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__4__MASK 0x08u +#define SCSI_Noise__4__PC CYREG_PRT4_PC3 +#define SCSI_Noise__4__PORT 4u +#define SCSI_Noise__4__PRT CYREG_PRT4_PRT +#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__4__PS CYREG_PRT4_PS +#define SCSI_Noise__4__SHIFT 3u +#define SCSI_Noise__4__SLW CYREG_PRT4_SLW +#define SCSI_Noise__ACK__AG CYREG_PRT4_AG +#define SCSI_Noise__ACK__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__ACK__BIE CYREG_PRT4_BIE +#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__ACK__BYP CYREG_PRT4_BYP +#define SCSI_Noise__ACK__CTL CYREG_PRT4_CTL +#define SCSI_Noise__ACK__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__ACK__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__ACK__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__ACK__DR CYREG_PRT4_DR +#define SCSI_Noise__ACK__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__ACK__INTTYPE CYREG_PICU4_INTTYPE3 +#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__ACK__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__ACK__MASK 0x08u +#define SCSI_Noise__ACK__PC CYREG_PRT4_PC3 +#define SCSI_Noise__ACK__PORT 4u +#define SCSI_Noise__ACK__PRT CYREG_PRT4_PRT +#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__ACK__PS CYREG_PRT4_PS +#define SCSI_Noise__ACK__SHIFT 3u +#define SCSI_Noise__ACK__SLW CYREG_PRT4_SLW +#define SCSI_Noise__ATN__AG CYREG_PRT4_AG +#define SCSI_Noise__ATN__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__ATN__BIE CYREG_PRT4_BIE +#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__ATN__BYP CYREG_PRT4_BYP +#define SCSI_Noise__ATN__CTL CYREG_PRT4_CTL +#define SCSI_Noise__ATN__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__ATN__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__ATN__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__ATN__DR CYREG_PRT4_DR +#define SCSI_Noise__ATN__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__ATN__INTTYPE CYREG_PICU4_INTTYPE7 +#define SCSI_Noise__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__ATN__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__ATN__MASK 0x80u +#define SCSI_Noise__ATN__PC CYREG_PRT4_PC7 +#define SCSI_Noise__ATN__PORT 4u +#define SCSI_Noise__ATN__PRT CYREG_PRT4_PRT +#define SCSI_Noise__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__ATN__PS CYREG_PRT4_PS +#define SCSI_Noise__ATN__SHIFT 7u +#define SCSI_Noise__ATN__SLW CYREG_PRT4_SLW +#define SCSI_Noise__BSY__AG CYREG_PRT4_AG +#define SCSI_Noise__BSY__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__BSY__BIE CYREG_PRT4_BIE +#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__BSY__BYP CYREG_PRT4_BYP +#define SCSI_Noise__BSY__CTL CYREG_PRT4_CTL +#define SCSI_Noise__BSY__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__BSY__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__BSY__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__BSY__DR CYREG_PRT4_DR +#define SCSI_Noise__BSY__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__BSY__INTTYPE CYREG_PICU4_INTTYPE5 +#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__BSY__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__BSY__MASK 0x20u +#define SCSI_Noise__BSY__PC CYREG_PRT4_PC5 +#define SCSI_Noise__BSY__PORT 4u +#define SCSI_Noise__BSY__PRT CYREG_PRT4_PRT +#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__BSY__PS CYREG_PRT4_PS +#define SCSI_Noise__BSY__SHIFT 5u +#define SCSI_Noise__BSY__SLW CYREG_PRT4_SLW +#define SCSI_Noise__RST__AG CYREG_PRT0_AG +#define SCSI_Noise__RST__AMUX CYREG_PRT0_AMUX +#define SCSI_Noise__RST__BIE CYREG_PRT0_BIE +#define SCSI_Noise__RST__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Noise__RST__BYP CYREG_PRT0_BYP +#define SCSI_Noise__RST__CTL CYREG_PRT0_CTL +#define SCSI_Noise__RST__DM0 CYREG_PRT0_DM0 +#define SCSI_Noise__RST__DM1 CYREG_PRT0_DM1 +#define SCSI_Noise__RST__DM2 CYREG_PRT0_DM2 +#define SCSI_Noise__RST__DR CYREG_PRT0_DR +#define SCSI_Noise__RST__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Noise__RST__INTTYPE CYREG_PICU0_INTTYPE6 +#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Noise__RST__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Noise__RST__MASK 0x40u +#define SCSI_Noise__RST__PC CYREG_PRT0_PC6 +#define SCSI_Noise__RST__PORT 0u +#define SCSI_Noise__RST__PRT CYREG_PRT0_PRT +#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Noise__RST__PS CYREG_PRT0_PS +#define SCSI_Noise__RST__SHIFT 6u +#define SCSI_Noise__RST__SLW CYREG_PRT0_SLW +#define SCSI_Noise__SEL__AG CYREG_PRT0_AG +#define SCSI_Noise__SEL__AMUX CYREG_PRT0_AMUX +#define SCSI_Noise__SEL__BIE CYREG_PRT0_BIE +#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Noise__SEL__BYP CYREG_PRT0_BYP +#define SCSI_Noise__SEL__CTL CYREG_PRT0_CTL +#define SCSI_Noise__SEL__DM0 CYREG_PRT0_DM0 +#define SCSI_Noise__SEL__DM1 CYREG_PRT0_DM1 +#define SCSI_Noise__SEL__DM2 CYREG_PRT0_DM2 +#define SCSI_Noise__SEL__DR CYREG_PRT0_DR +#define SCSI_Noise__SEL__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Noise__SEL__INTTYPE CYREG_PICU0_INTTYPE2 +#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Noise__SEL__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Noise__SEL__MASK 0x04u +#define SCSI_Noise__SEL__PC CYREG_PRT0_PC2 +#define SCSI_Noise__SEL__PORT 0u +#define SCSI_Noise__SEL__PRT CYREG_PRT0_PRT +#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Noise__SEL__PS CYREG_PRT0_PS +#define SCSI_Noise__SEL__SHIFT 2u +#define SCSI_Noise__SEL__SLW CYREG_PRT0_SLW /* SCSI_Out */ #define SCSI_Out__0__AG CYREG_PRT6_AG @@ -1521,8 +1380,6 @@ #define SCSI_Out__SEL__PS CYREG_PRT0_PS #define SCSI_Out__SEL__SHIFT 3u #define SCSI_Out__SEL__SLW CYREG_PRT0_SLW - -/* SCSI_Out_Bits */ #define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u @@ -1557,8 +1414,6 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL #define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL #define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK - -/* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL @@ -1579,8 +1434,6 @@ #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL #define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL #define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK - -/* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG #define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX #define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE @@ -2028,6 +1881,272 @@ #define SCSI_Out_DBx__DB7__SHIFT 5u #define SCSI_Out_DBx__DB7__SLW CYREG_PRT15_SLW +/* SCSI_Parity_Error */ +#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__0__POS 0 +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK +#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST + +/* SCSI_RST_ISR */ +#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RST_ISR__INTC_MASK 0x02u +#define SCSI_RST_ISR__INTC_NUMBER 1u +#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u +#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_RX_DMA */ +#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_RX_DMA__DRQ_NUMBER 0u +#define SCSI_RX_DMA__NUMBEROF_TDS 0u +#define SCSI_RX_DMA__PRIORITY 2u +#define SCSI_RX_DMA__TERMIN_EN 0u +#define SCSI_RX_DMA__TERMIN_SEL 0u +#define SCSI_RX_DMA__TERMOUT0_EN 1u +#define SCSI_RX_DMA__TERMOUT0_SEL 0u +#define SCSI_RX_DMA__TERMOUT1_EN 0u +#define SCSI_RX_DMA__TERMOUT1_SEL 0u +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u +#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_SEL_ISR__INTC_MASK 0x08u +#define SCSI_SEL_ISR__INTC_NUMBER 3u +#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u +#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_TX_DMA__DRQ_NUMBER 1u +#define SCSI_TX_DMA__NUMBEROF_TDS 0u +#define SCSI_TX_DMA__PRIORITY 2u +#define SCSI_TX_DMA__TERMIN_EN 0u +#define SCSI_TX_DMA__TERMIN_SEL 0u +#define SCSI_TX_DMA__TERMOUT0_EN 1u +#define SCSI_TX_DMA__TERMOUT0_SEL 1u +#define SCSI_TX_DMA__TERMOUT1_EN 0u +#define SCSI_TX_DMA__TERMOUT1_SEL 0u +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u +#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SDCard_BSPIM */ +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST +#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_RxStsReg__4__POS 4 +#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u +#define SDCard_BSPIM_RxStsReg__5__POS 5 +#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u +#define SDCard_BSPIM_RxStsReg__6__POS 6 +#define SDCard_BSPIM_RxStsReg__MASK 0x70u +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK +#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL +#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 +#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u +#define SDCard_BSPIM_TxStsReg__0__POS 0 +#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u +#define SDCard_BSPIM_TxStsReg__1__POS 1 +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u +#define SDCard_BSPIM_TxStsReg__2__POS 2 +#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u +#define SDCard_BSPIM_TxStsReg__3__POS 3 +#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_TxStsReg__4__POS 4 +#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST + +/* SD_CS */ +#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE5 +#define SD_CS__0__MASK 0x20u +#define SD_CS__0__PC CYREG_PRT3_PC5 +#define SD_CS__0__PORT 3u +#define SD_CS__0__SHIFT 5u +#define SD_CS__AG CYREG_PRT3_AG +#define SD_CS__AMUX CYREG_PRT3_AMUX +#define SD_CS__BIE CYREG_PRT3_BIE +#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CS__BYP CYREG_PRT3_BYP +#define SD_CS__CTL CYREG_PRT3_CTL +#define SD_CS__DM0 CYREG_PRT3_DM0 +#define SD_CS__DM1 CYREG_PRT3_DM1 +#define SD_CS__DM2 CYREG_PRT3_DM2 +#define SD_CS__DR CYREG_PRT3_DR +#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CS__MASK 0x20u +#define SD_CS__PORT 3u +#define SD_CS__PRT CYREG_PRT3_PRT +#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CS__PS CYREG_PRT3_PS +#define SD_CS__SHIFT 5u +#define SD_CS__SLW CYREG_PRT3_SLW + +/* SD_Data_Clk */ +#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 +#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 +#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 +#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u +#define SD_Data_Clk__INDEX 0x00u +#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SD_Data_Clk__PM_ACT_MSK 0x01u +#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SD_Data_Clk__PM_STBY_MSK 0x01u + +/* SD_MISO */ +#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE2 +#define SD_MISO__0__MASK 0x04u +#define SD_MISO__0__PC CYREG_PRT3_PC2 +#define SD_MISO__0__PORT 3u +#define SD_MISO__0__SHIFT 2u +#define SD_MISO__AG CYREG_PRT3_AG +#define SD_MISO__AMUX CYREG_PRT3_AMUX +#define SD_MISO__BIE CYREG_PRT3_BIE +#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MISO__BYP CYREG_PRT3_BYP +#define SD_MISO__CTL CYREG_PRT3_CTL +#define SD_MISO__DM0 CYREG_PRT3_DM0 +#define SD_MISO__DM1 CYREG_PRT3_DM1 +#define SD_MISO__DM2 CYREG_PRT3_DM2 +#define SD_MISO__DR CYREG_PRT3_DR +#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MISO__MASK 0x04u +#define SD_MISO__PORT 3u +#define SD_MISO__PRT CYREG_PRT3_PRT +#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MISO__PS CYREG_PRT3_PS +#define SD_MISO__SHIFT 2u +#define SD_MISO__SLW CYREG_PRT3_SLW + +/* SD_MOSI */ +#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE4 +#define SD_MOSI__0__MASK 0x10u +#define SD_MOSI__0__PC CYREG_PRT3_PC4 +#define SD_MOSI__0__PORT 3u +#define SD_MOSI__0__SHIFT 4u +#define SD_MOSI__AG CYREG_PRT3_AG +#define SD_MOSI__AMUX CYREG_PRT3_AMUX +#define SD_MOSI__BIE CYREG_PRT3_BIE +#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MOSI__BYP CYREG_PRT3_BYP +#define SD_MOSI__CTL CYREG_PRT3_CTL +#define SD_MOSI__DM0 CYREG_PRT3_DM0 +#define SD_MOSI__DM1 CYREG_PRT3_DM1 +#define SD_MOSI__DM2 CYREG_PRT3_DM2 +#define SD_MOSI__DR CYREG_PRT3_DR +#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MOSI__MASK 0x10u +#define SD_MOSI__PORT 3u +#define SD_MOSI__PRT CYREG_PRT3_PRT +#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MOSI__PS CYREG_PRT3_PS +#define SD_MOSI__SHIFT 4u +#define SD_MOSI__SLW CYREG_PRT3_SLW + /* SD_RX_DMA */ #define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_RX_DMA__DRQ_NUMBER 2u @@ -2039,8 +2158,6 @@ #define SD_RX_DMA__TERMOUT0_SEL 2u #define SD_RX_DMA__TERMOUT1_EN 0u #define SD_RX_DMA__TERMOUT1_SEL 0u - -/* SD_RX_DMA_COMPLETE */ #define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 #define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u @@ -2050,6 +2167,40 @@ #define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* SD_SCK */ +#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE3 +#define SD_SCK__0__MASK 0x08u +#define SD_SCK__0__PC CYREG_PRT3_PC3 +#define SD_SCK__0__PORT 3u +#define SD_SCK__0__SHIFT 3u +#define SD_SCK__AG CYREG_PRT3_AG +#define SD_SCK__AMUX CYREG_PRT3_AMUX +#define SD_SCK__BIE CYREG_PRT3_BIE +#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_SCK__BYP CYREG_PRT3_BYP +#define SD_SCK__CTL CYREG_PRT3_CTL +#define SD_SCK__DM0 CYREG_PRT3_DM0 +#define SD_SCK__DM1 CYREG_PRT3_DM1 +#define SD_SCK__DM2 CYREG_PRT3_DM2 +#define SD_SCK__DR CYREG_PRT3_DR +#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS +#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN +#define SD_SCK__MASK 0x08u +#define SD_SCK__PORT 3u +#define SD_SCK__PRT CYREG_PRT3_PRT +#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_SCK__PS CYREG_PRT3_PS +#define SD_SCK__SHIFT 3u +#define SD_SCK__SLW CYREG_PRT3_SLW + /* SD_TX_DMA */ #define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_TX_DMA__DRQ_NUMBER 3u @@ -2061,8 +2212,6 @@ #define SD_TX_DMA__TERMOUT0_SEL 3u #define SD_TX_DMA__TERMOUT1_EN 0u #define SD_TX_DMA__TERMOUT1_SEL 0u - -/* SD_TX_DMA_COMPLETE */ #define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 #define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u @@ -2072,287 +2221,303 @@ #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -/* SCSI_Noise */ -#define SCSI_Noise__0__AG CYREG_PRT4_AG -#define SCSI_Noise__0__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__0__BIE CYREG_PRT4_BIE -#define SCSI_Noise__0__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__0__BYP CYREG_PRT4_BYP -#define SCSI_Noise__0__CTL CYREG_PRT4_CTL -#define SCSI_Noise__0__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__0__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__0__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__0__DR CYREG_PRT4_DR -#define SCSI_Noise__0__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__0__INTTYPE CYREG_PICU4_INTTYPE7 -#define SCSI_Noise__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__0__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__0__MASK 0x80u -#define SCSI_Noise__0__PC CYREG_PRT4_PC7 -#define SCSI_Noise__0__PORT 4u -#define SCSI_Noise__0__PRT CYREG_PRT4_PRT -#define SCSI_Noise__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__0__PS CYREG_PRT4_PS -#define SCSI_Noise__0__SHIFT 7u -#define SCSI_Noise__0__SLW CYREG_PRT4_SLW -#define SCSI_Noise__1__AG CYREG_PRT4_AG -#define SCSI_Noise__1__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__1__BIE CYREG_PRT4_BIE -#define SCSI_Noise__1__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__1__BYP CYREG_PRT4_BYP -#define SCSI_Noise__1__CTL CYREG_PRT4_CTL -#define SCSI_Noise__1__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__1__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__1__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__1__DR CYREG_PRT4_DR -#define SCSI_Noise__1__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__1__INTTYPE CYREG_PICU4_INTTYPE5 -#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__1__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__1__MASK 0x20u -#define SCSI_Noise__1__PC CYREG_PRT4_PC5 -#define SCSI_Noise__1__PORT 4u -#define SCSI_Noise__1__PRT CYREG_PRT4_PRT -#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__1__PS CYREG_PRT4_PS -#define SCSI_Noise__1__SHIFT 5u -#define SCSI_Noise__1__SLW CYREG_PRT4_SLW -#define SCSI_Noise__2__AG CYREG_PRT0_AG -#define SCSI_Noise__2__AMUX CYREG_PRT0_AMUX -#define SCSI_Noise__2__BIE CYREG_PRT0_BIE -#define SCSI_Noise__2__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Noise__2__BYP CYREG_PRT0_BYP -#define SCSI_Noise__2__CTL CYREG_PRT0_CTL -#define SCSI_Noise__2__DM0 CYREG_PRT0_DM0 -#define SCSI_Noise__2__DM1 CYREG_PRT0_DM1 -#define SCSI_Noise__2__DM2 CYREG_PRT0_DM2 -#define SCSI_Noise__2__DR CYREG_PRT0_DR -#define SCSI_Noise__2__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Noise__2__INTTYPE CYREG_PICU0_INTTYPE2 -#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Noise__2__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Noise__2__MASK 0x04u -#define SCSI_Noise__2__PC CYREG_PRT0_PC2 -#define SCSI_Noise__2__PORT 0u -#define SCSI_Noise__2__PRT CYREG_PRT0_PRT -#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Noise__2__PS CYREG_PRT0_PS -#define SCSI_Noise__2__SHIFT 2u -#define SCSI_Noise__2__SLW CYREG_PRT0_SLW -#define SCSI_Noise__3__AG CYREG_PRT0_AG -#define SCSI_Noise__3__AMUX CYREG_PRT0_AMUX -#define SCSI_Noise__3__BIE CYREG_PRT0_BIE -#define SCSI_Noise__3__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Noise__3__BYP CYREG_PRT0_BYP -#define SCSI_Noise__3__CTL CYREG_PRT0_CTL -#define SCSI_Noise__3__DM0 CYREG_PRT0_DM0 -#define SCSI_Noise__3__DM1 CYREG_PRT0_DM1 -#define SCSI_Noise__3__DM2 CYREG_PRT0_DM2 -#define SCSI_Noise__3__DR CYREG_PRT0_DR -#define SCSI_Noise__3__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Noise__3__INTTYPE CYREG_PICU0_INTTYPE6 -#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Noise__3__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Noise__3__MASK 0x40u -#define SCSI_Noise__3__PC CYREG_PRT0_PC6 -#define SCSI_Noise__3__PORT 0u -#define SCSI_Noise__3__PRT CYREG_PRT0_PRT -#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Noise__3__PS CYREG_PRT0_PS -#define SCSI_Noise__3__SHIFT 6u -#define SCSI_Noise__3__SLW CYREG_PRT0_SLW -#define SCSI_Noise__4__AG CYREG_PRT4_AG -#define SCSI_Noise__4__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__4__BIE CYREG_PRT4_BIE -#define SCSI_Noise__4__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__4__BYP CYREG_PRT4_BYP -#define SCSI_Noise__4__CTL CYREG_PRT4_CTL -#define SCSI_Noise__4__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__4__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__4__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__4__DR CYREG_PRT4_DR -#define SCSI_Noise__4__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__4__INTTYPE CYREG_PICU4_INTTYPE3 -#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__4__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__4__MASK 0x08u -#define SCSI_Noise__4__PC CYREG_PRT4_PC3 -#define SCSI_Noise__4__PORT 4u -#define SCSI_Noise__4__PRT CYREG_PRT4_PRT -#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__4__PS CYREG_PRT4_PS -#define SCSI_Noise__4__SHIFT 3u -#define SCSI_Noise__4__SLW CYREG_PRT4_SLW -#define SCSI_Noise__ACK__AG CYREG_PRT4_AG -#define SCSI_Noise__ACK__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__ACK__BIE CYREG_PRT4_BIE -#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__ACK__BYP CYREG_PRT4_BYP -#define SCSI_Noise__ACK__CTL CYREG_PRT4_CTL -#define SCSI_Noise__ACK__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__ACK__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__ACK__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__ACK__DR CYREG_PRT4_DR -#define SCSI_Noise__ACK__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__ACK__INTTYPE CYREG_PICU4_INTTYPE3 -#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__ACK__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__ACK__MASK 0x08u -#define SCSI_Noise__ACK__PC CYREG_PRT4_PC3 -#define SCSI_Noise__ACK__PORT 4u -#define SCSI_Noise__ACK__PRT CYREG_PRT4_PRT -#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__ACK__PS CYREG_PRT4_PS -#define SCSI_Noise__ACK__SHIFT 3u -#define SCSI_Noise__ACK__SLW CYREG_PRT4_SLW -#define SCSI_Noise__ATN__AG CYREG_PRT4_AG -#define SCSI_Noise__ATN__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__ATN__BIE CYREG_PRT4_BIE -#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__ATN__BYP CYREG_PRT4_BYP -#define SCSI_Noise__ATN__CTL CYREG_PRT4_CTL -#define SCSI_Noise__ATN__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__ATN__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__ATN__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__ATN__DR CYREG_PRT4_DR -#define SCSI_Noise__ATN__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__ATN__INTTYPE CYREG_PICU4_INTTYPE7 -#define SCSI_Noise__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__ATN__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__ATN__MASK 0x80u -#define SCSI_Noise__ATN__PC CYREG_PRT4_PC7 -#define SCSI_Noise__ATN__PORT 4u -#define SCSI_Noise__ATN__PRT CYREG_PRT4_PRT -#define SCSI_Noise__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__ATN__PS CYREG_PRT4_PS -#define SCSI_Noise__ATN__SHIFT 7u -#define SCSI_Noise__ATN__SLW CYREG_PRT4_SLW -#define SCSI_Noise__BSY__AG CYREG_PRT4_AG -#define SCSI_Noise__BSY__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__BSY__BIE CYREG_PRT4_BIE -#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__BSY__BYP CYREG_PRT4_BYP -#define SCSI_Noise__BSY__CTL CYREG_PRT4_CTL -#define SCSI_Noise__BSY__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__BSY__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__BSY__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__BSY__DR CYREG_PRT4_DR -#define SCSI_Noise__BSY__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__BSY__INTTYPE CYREG_PICU4_INTTYPE5 -#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__BSY__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__BSY__MASK 0x20u -#define SCSI_Noise__BSY__PC CYREG_PRT4_PC5 -#define SCSI_Noise__BSY__PORT 4u -#define SCSI_Noise__BSY__PRT CYREG_PRT4_PRT -#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__BSY__PS CYREG_PRT4_PS -#define SCSI_Noise__BSY__SHIFT 5u -#define SCSI_Noise__BSY__SLW CYREG_PRT4_SLW -#define SCSI_Noise__RST__AG CYREG_PRT0_AG -#define SCSI_Noise__RST__AMUX CYREG_PRT0_AMUX -#define SCSI_Noise__RST__BIE CYREG_PRT0_BIE -#define SCSI_Noise__RST__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Noise__RST__BYP CYREG_PRT0_BYP -#define SCSI_Noise__RST__CTL CYREG_PRT0_CTL -#define SCSI_Noise__RST__DM0 CYREG_PRT0_DM0 -#define SCSI_Noise__RST__DM1 CYREG_PRT0_DM1 -#define SCSI_Noise__RST__DM2 CYREG_PRT0_DM2 -#define SCSI_Noise__RST__DR CYREG_PRT0_DR -#define SCSI_Noise__RST__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Noise__RST__INTTYPE CYREG_PICU0_INTTYPE6 -#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Noise__RST__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Noise__RST__MASK 0x40u -#define SCSI_Noise__RST__PC CYREG_PRT0_PC6 -#define SCSI_Noise__RST__PORT 0u -#define SCSI_Noise__RST__PRT CYREG_PRT0_PRT -#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Noise__RST__PS CYREG_PRT0_PS -#define SCSI_Noise__RST__SHIFT 6u -#define SCSI_Noise__RST__SLW CYREG_PRT0_SLW -#define SCSI_Noise__SEL__AG CYREG_PRT0_AG -#define SCSI_Noise__SEL__AMUX CYREG_PRT0_AMUX -#define SCSI_Noise__SEL__BIE CYREG_PRT0_BIE -#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Noise__SEL__BYP CYREG_PRT0_BYP -#define SCSI_Noise__SEL__CTL CYREG_PRT0_CTL -#define SCSI_Noise__SEL__DM0 CYREG_PRT0_DM0 -#define SCSI_Noise__SEL__DM1 CYREG_PRT0_DM1 -#define SCSI_Noise__SEL__DM2 CYREG_PRT0_DM2 -#define SCSI_Noise__SEL__DR CYREG_PRT0_DR -#define SCSI_Noise__SEL__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Noise__SEL__INTTYPE CYREG_PICU0_INTTYPE2 -#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Noise__SEL__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Noise__SEL__MASK 0x04u -#define SCSI_Noise__SEL__PC CYREG_PRT0_PC2 -#define SCSI_Noise__SEL__PORT 0u -#define SCSI_Noise__SEL__PRT CYREG_PRT0_PRT -#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Noise__SEL__PS CYREG_PRT0_PS -#define SCSI_Noise__SEL__SHIFT 2u -#define SCSI_Noise__SEL__SLW CYREG_PRT0_SLW +/* TERM_EN */ +#define TERM_EN__0__INTTYPE CYREG_PICU15_INTTYPE3 +#define TERM_EN__0__MASK 0x08u +#define TERM_EN__0__PC CYREG_IO_PC_PRT15_PC3 +#define TERM_EN__0__PORT 15u +#define TERM_EN__0__SHIFT 3u +#define TERM_EN__AG CYREG_PRT15_AG +#define TERM_EN__AMUX CYREG_PRT15_AMUX +#define TERM_EN__BIE CYREG_PRT15_BIE +#define TERM_EN__BIT_MASK CYREG_PRT15_BIT_MASK +#define TERM_EN__BYP CYREG_PRT15_BYP +#define TERM_EN__CTL CYREG_PRT15_CTL +#define TERM_EN__DM0 CYREG_PRT15_DM0 +#define TERM_EN__DM1 CYREG_PRT15_DM1 +#define TERM_EN__DM2 CYREG_PRT15_DM2 +#define TERM_EN__DR CYREG_PRT15_DR +#define TERM_EN__INP_DIS CYREG_PRT15_INP_DIS +#define TERM_EN__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define TERM_EN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define TERM_EN__LCD_EN CYREG_PRT15_LCD_EN +#define TERM_EN__MASK 0x08u +#define TERM_EN__PORT 15u +#define TERM_EN__PRT CYREG_PRT15_PRT +#define TERM_EN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define TERM_EN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define TERM_EN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define TERM_EN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define TERM_EN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define TERM_EN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define TERM_EN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define TERM_EN__PS CYREG_PRT15_PS +#define TERM_EN__SHIFT 3u +#define TERM_EN__SLW CYREG_PRT15_SLW + +/* USBFS */ +#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_arb_int__INTC_MASK 0x400000u +#define USBFS_arb_int__INTC_NUMBER 22u +#define USBFS_arb_int__INTC_PRIOR_NUM 6u +#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 +#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_bus_reset__INTC_MASK 0x800000u +#define USBFS_bus_reset__INTC_NUMBER 23u +#define USBFS_bus_reset__INTC_PRIOR_NUM 7u +#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 +#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7 +#define USBFS_Dm__0__MASK 0x80u +#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 +#define USBFS_Dm__0__PORT 15u +#define USBFS_Dm__0__SHIFT 7u +#define USBFS_Dm__AG CYREG_PRT15_AG +#define USBFS_Dm__AMUX CYREG_PRT15_AMUX +#define USBFS_Dm__BIE CYREG_PRT15_BIE +#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dm__BYP CYREG_PRT15_BYP +#define USBFS_Dm__CTL CYREG_PRT15_CTL +#define USBFS_Dm__DM0 CYREG_PRT15_DM0 +#define USBFS_Dm__DM1 CYREG_PRT15_DM1 +#define USBFS_Dm__DM2 CYREG_PRT15_DM2 +#define USBFS_Dm__DR CYREG_PRT15_DR +#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dm__MASK 0x80u +#define USBFS_Dm__PORT 15u +#define USBFS_Dm__PRT CYREG_PRT15_PRT +#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dm__PS CYREG_PRT15_PS +#define USBFS_Dm__SHIFT 7u +#define USBFS_Dm__SLW CYREG_PRT15_SLW +#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6 +#define USBFS_Dp__0__MASK 0x40u +#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 +#define USBFS_Dp__0__PORT 15u +#define USBFS_Dp__0__SHIFT 6u +#define USBFS_Dp__AG CYREG_PRT15_AG +#define USBFS_Dp__AMUX CYREG_PRT15_AMUX +#define USBFS_Dp__BIE CYREG_PRT15_BIE +#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dp__BYP CYREG_PRT15_BYP +#define USBFS_Dp__CTL CYREG_PRT15_CTL +#define USBFS_Dp__DM0 CYREG_PRT15_DM0 +#define USBFS_Dp__DM1 CYREG_PRT15_DM1 +#define USBFS_Dp__DM2 CYREG_PRT15_DM2 +#define USBFS_Dp__DR CYREG_PRT15_DR +#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT +#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dp__MASK 0x40u +#define USBFS_Dp__PORT 15u +#define USBFS_Dp__PRT CYREG_PRT15_PRT +#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dp__PS CYREG_PRT15_PS +#define USBFS_Dp__SHIFT 6u +#define USBFS_Dp__SLW CYREG_PRT15_SLW +#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 +#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_dp_int__INTC_MASK 0x1000u +#define USBFS_dp_int__INTC_NUMBER 12u +#define USBFS_dp_int__INTC_PRIOR_NUM 7u +#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 +#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_0__INTC_MASK 0x1000000u +#define USBFS_ep_0__INTC_NUMBER 24u +#define USBFS_ep_0__INTC_PRIOR_NUM 7u +#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 +#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_1__INTC_MASK 0x80u +#define USBFS_ep_1__INTC_NUMBER 7u +#define USBFS_ep_1__INTC_PRIOR_NUM 7u +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 +#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_2__INTC_MASK 0x100u +#define USBFS_ep_2__INTC_NUMBER 8u +#define USBFS_ep_2__INTC_PRIOR_NUM 7u +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 +#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_3__INTC_MASK 0x200u +#define USBFS_ep_3__INTC_NUMBER 9u +#define USBFS_ep_3__INTC_PRIOR_NUM 7u +#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 +#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_4__INTC_MASK 0x400u +#define USBFS_ep_4__INTC_NUMBER 10u +#define USBFS_ep_4__INTC_PRIOR_NUM 7u +#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 +#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_sof_int__INTC_MASK 0x200000u +#define USBFS_sof_int__INTC_NUMBER 21u +#define USBFS_sof_int__INTC_PRIOR_NUM 7u +#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 +#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG +#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG +#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN +#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR +#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG +#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN +#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR +#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG +#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN +#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR +#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG +#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN +#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR +#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG +#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN +#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR +#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG +#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN +#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR +#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG +#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN +#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR +#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG +#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN +#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR +#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN +#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR +#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR +#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA +#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB +#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA +#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB +#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR +#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA +#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB +#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA +#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB +#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR +#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA +#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB +#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA +#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB +#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR +#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA +#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB +#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA +#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB +#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR +#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA +#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB +#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA +#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB +#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR +#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA +#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB +#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA +#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB +#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR +#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA +#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB +#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA +#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB +#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR +#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA +#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB +#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA +#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB +#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE +#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT +#define USBFS_USB__CR0 CYREG_USB_CR0 +#define USBFS_USB__CR1 CYREG_USB_CR1 +#define USBFS_USB__CWA CYREG_USB_CWA +#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB +#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES +#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB +#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG +#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE +#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE +#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT +#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR +#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 +#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 +#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 +#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 +#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 +#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 +#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 +#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 +#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE +#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 +#define USBFS_USB__PM_ACT_MSK 0x01u +#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 +#define USBFS_USB__PM_STBY_MSK 0x01u +#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN +#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR +#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 +#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 +#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 +#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 +#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 +#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 +#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 +#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 +#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 +#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 +#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 +#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 +#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 +#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 +#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 +#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 +#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 +#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 +#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 +#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 +#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 +#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 +#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 +#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 +#define USBFS_USB__SOF0 CYREG_USB_SOF0 +#define USBFS_USB__SOF1 CYREG_USB_SOF1 +#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN +#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 +#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 /* scsiTarget */ #define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0 @@ -2415,89 +2580,6 @@ #define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL #define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST -/* Debug_Timer_Interrupt */ -#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define Debug_Timer_Interrupt__INTC_MASK 0x02u -#define Debug_Timer_Interrupt__INTC_NUMBER 1u -#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u -#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1 -#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0 -#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1 -#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0 -#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1 -#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2 -#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 -#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 -#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0 -#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1 -#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 -#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u -#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 -#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u -#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0 -#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1 -#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0 - -/* SCSI_RX_DMA */ -#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_RX_DMA__DRQ_NUMBER 0u -#define SCSI_RX_DMA__NUMBEROF_TDS 0u -#define SCSI_RX_DMA__PRIORITY 2u -#define SCSI_RX_DMA__TERMIN_EN 0u -#define SCSI_RX_DMA__TERMIN_SEL 0u -#define SCSI_RX_DMA__TERMOUT0_EN 1u -#define SCSI_RX_DMA__TERMOUT0_SEL 0u -#define SCSI_RX_DMA__TERMOUT1_EN 0u -#define SCSI_RX_DMA__TERMOUT1_SEL 0u - -/* SCSI_RX_DMA_COMPLETE */ -#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u -#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u -#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0 -#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_TX_DMA__DRQ_NUMBER 1u -#define SCSI_TX_DMA__NUMBEROF_TDS 0u -#define SCSI_TX_DMA__PRIORITY 2u -#define SCSI_TX_DMA__TERMIN_EN 0u -#define SCSI_TX_DMA__TERMIN_SEL 0u -#define SCSI_TX_DMA__TERMOUT0_EN 1u -#define SCSI_TX_DMA__TERMOUT0_SEL 1u -#define SCSI_TX_DMA__TERMOUT1_EN 0u -#define SCSI_TX_DMA__TERMOUT1_SEL 0u - -/* SCSI_TX_DMA_COMPLETE */ -#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u -#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 -#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SD_Data_Clk */ -#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 -#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 -#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 -#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u -#define SD_Data_Clk__INDEX 0x00u -#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define SD_Data_Clk__PM_ACT_MSK 0x01u -#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define SD_Data_Clk__PM_STBY_MSK 0x01u - /* timer_clock */ #define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0 #define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1 @@ -2509,156 +2591,55 @@ #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2 #define timer_clock__PM_STBY_MSK 0x04u -/* SCSI_RST_ISR */ -#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RST_ISR__INTC_MASK 0x04u -#define SCSI_RST_ISR__INTC_NUMBER 2u -#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u -#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2 -#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_SEL_ISR__INTC_MASK 0x08u -#define SCSI_SEL_ISR__INTC_NUMBER 3u -#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u -#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 -#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_Filtered */ -#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u -#define SCSI_Filtered_sts_sts_reg__0__POS 0 -#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u -#define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST -#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u -#define SCSI_Filtered_sts_sts_reg__2__POS 2 -#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u -#define SCSI_Filtered_sts_sts_reg__3__POS 3 -#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u -#define SCSI_Filtered_sts_sts_reg__4__POS 4 -#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK -#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL -#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST - -/* SCSI_CTL_PHASE */ -#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK - -/* SCSI_Glitch_Ctl */ -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK - -/* SCSI_Parity_Error */ -#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST -#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK -#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST - /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U #define BCLK__BUS_CLK__KHZ 50000U #define BCLK__BUS_CLK__MHZ 50U #define CY_PROJECT_NAME "SCSI2SD" -#define CY_VERSION "PSoC Creator 4.0 Update 1" +#define CY_VERSION "PSoC Creator 4.1" #define CYDEV_CHIP_DIE_LEOPARD 1u -#define CYDEV_CHIP_DIE_PSOC4A 12u -#define CYDEV_CHIP_DIE_PSOC5LP 19u -#define CYDEV_CHIP_DIE_PSOC5TM 20u -#define CYDEV_CHIP_DIE_TMA4 2u +#define CYDEV_CHIP_DIE_PSOC4A 16u +#define CYDEV_CHIP_DIE_PSOC5LP 2u +#define CYDEV_CHIP_DIE_PSOC5TM 3u +#define CYDEV_CHIP_DIE_TMA4 4u #define CYDEV_CHIP_DIE_UNKNOWN 0u -#define CYDEV_CHIP_FAMILY_FM0P 4u -#define CYDEV_CHIP_FAMILY_FM3 5u -#define CYDEV_CHIP_FAMILY_FM4 6u +#define CYDEV_CHIP_FAMILY_FM0P 5u +#define CYDEV_CHIP_FAMILY_FM3 6u +#define CYDEV_CHIP_FAMILY_FM4 7u #define CYDEV_CHIP_FAMILY_PSOC3 1u #define CYDEV_CHIP_FAMILY_PSOC4 2u #define CYDEV_CHIP_FAMILY_PSOC5 3u +#define CYDEV_CHIP_FAMILY_PSOC6 4u #define CYDEV_CHIP_FAMILY_UNKNOWN 0u #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 #define CYDEV_CHIP_JTAG_ID 0x2E133069u #define CYDEV_CHIP_MEMBER_3A 1u -#define CYDEV_CHIP_MEMBER_4A 12u -#define CYDEV_CHIP_MEMBER_4C 18u -#define CYDEV_CHIP_MEMBER_4D 8u -#define CYDEV_CHIP_MEMBER_4E 4u -#define CYDEV_CHIP_MEMBER_4F 13u -#define CYDEV_CHIP_MEMBER_4G 2u -#define CYDEV_CHIP_MEMBER_4H 11u -#define CYDEV_CHIP_MEMBER_4I 17u -#define CYDEV_CHIP_MEMBER_4J 9u -#define CYDEV_CHIP_MEMBER_4K 10u -#define CYDEV_CHIP_MEMBER_4L 16u -#define CYDEV_CHIP_MEMBER_4M 15u -#define CYDEV_CHIP_MEMBER_4N 6u -#define CYDEV_CHIP_MEMBER_4O 5u -#define CYDEV_CHIP_MEMBER_4P 14u -#define CYDEV_CHIP_MEMBER_4Q 7u -#define CYDEV_CHIP_MEMBER_4U 3u -#define CYDEV_CHIP_MEMBER_5A 20u -#define CYDEV_CHIP_MEMBER_5B 19u -#define CYDEV_CHIP_MEMBER_FM3 24u -#define CYDEV_CHIP_MEMBER_FM4 25u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 21u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 22u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 23u +#define CYDEV_CHIP_MEMBER_4A 16u +#define CYDEV_CHIP_MEMBER_4D 12u +#define CYDEV_CHIP_MEMBER_4E 6u +#define CYDEV_CHIP_MEMBER_4F 17u +#define CYDEV_CHIP_MEMBER_4G 4u +#define CYDEV_CHIP_MEMBER_4H 15u +#define CYDEV_CHIP_MEMBER_4I 21u +#define CYDEV_CHIP_MEMBER_4J 13u +#define CYDEV_CHIP_MEMBER_4K 14u +#define CYDEV_CHIP_MEMBER_4L 20u +#define CYDEV_CHIP_MEMBER_4M 19u +#define CYDEV_CHIP_MEMBER_4N 9u +#define CYDEV_CHIP_MEMBER_4O 7u +#define CYDEV_CHIP_MEMBER_4P 18u +#define CYDEV_CHIP_MEMBER_4Q 11u +#define CYDEV_CHIP_MEMBER_4R 8u +#define CYDEV_CHIP_MEMBER_4S 10u +#define CYDEV_CHIP_MEMBER_4U 5u +#define CYDEV_CHIP_MEMBER_5A 3u +#define CYDEV_CHIP_MEMBER_5B 2u +#define CYDEV_CHIP_MEMBER_6A 22u +#define CYDEV_CHIP_MEMBER_FM3 26u +#define CYDEV_CHIP_MEMBER_FM4 27u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 23u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 24u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 25u #define CYDEV_CHIP_MEMBER_UNKNOWN 0u #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED @@ -2683,7 +2664,6 @@ #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u #define CYDEV_CHIP_REVISION_4A_ES0 17u #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u -#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u @@ -2702,12 +2682,16 @@ #define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u #define CYDEV_CHIP_REVISION_5A_ES0 0u #define CYDEV_CHIP_REVISION_5A_ES1 1u #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u #define CYDEV_CHIP_REVISION_5B_ES0 0u #define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_6A_NO_UDB 0u +#define CYDEV_CHIP_REVISION_6A_PRODUCTION 0u #define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u #define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u #define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u @@ -2739,7 +2723,7 @@ #define CYDEV_ECC_ENABLE 0 #define CYDEV_HEAP_SIZE 0x0400 #define CYDEV_INSTRUCT_CACHE_ENABLED 1 -#define CYDEV_INTR_RISING 0x0000007Eu +#define CYDEV_INTR_RISING 0x0000007Fu #define CYDEV_IS_EXPORTING_CODE 0 #define CYDEV_IS_IMPORTING_CODE 0 #define CYDEV_PROJ_TYPE 2 diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 43b6244..ebdbdfe 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -1,7 +1,8 @@ + /******************************************************************************* * File Name: cyfitter_cfg.c * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file contains device initialization code. @@ -9,7 +10,7 @@ * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -55,6 +56,19 @@ #error Unsupported toolchain #endif +#ifndef CYCODE + #define CYCODE +#endif +#ifndef CYDATA + #define CYDATA +#endif +#ifndef CYFAR + #define CYFAR +#endif +#ifndef CYXDATA + #define CYXDATA +#endif + CY_CFG_UNUSED static void CYMEMZERO(void *s, size_t n); @@ -86,6 +100,7 @@ static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) #define CYCLOCKSTART_XTAL_ERROR 1u #define CYCLOCKSTART_32KHZ_ERROR 2u #define CYCLOCKSTART_PLL_ERROR 3u +#define CYCLOCKSTART_FLL_ERROR 4u #ifdef CY_NEED_CYCLOCKSTARTUPERROR @@ -109,17 +124,21 @@ static void CyClockStartupError(uint8 errorCode); CY_CFG_UNUSED static void CyClockStartupError(uint8 errorCode) { - /* To remove the compiler warning if errorCode not used. */ + /* To remove the compiler warning if errorCode not used. */ +#if defined(CY_PSOC3) && (CY_PSOC3) errorCode = errorCode; +#else + (void)errorCode; +#endif /* CY_PSOC3 */ /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ /* we will end up here to allow the customer to implement something to */ /* deal with the clock condition. */ #ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK - CY_CFG_Clock_Startup_ErrorCallback(); + CY_CFG_Clock_Startup_ErrorCallback(); #else - /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */ + /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */ /* `#START CyClockStartupError` */ /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ @@ -128,10 +147,8 @@ static void CyClockStartupError(uint8 errorCode) /* `#END` */ - /* If nothing else, stop here since the clocks have not started */ - /* correctly. */ while(1) {} -#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ +#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ } #endif @@ -170,7 +187,7 @@ static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_ baseAddr &= 0xFFFFFF00u; while (count != 0u) { - CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value); + CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); j++; count--; } @@ -205,8 +222,8 @@ static void ClockSetup(void) CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u); - CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0031u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x18u); /* Configure ILO based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); @@ -305,7 +322,7 @@ void SetAnalogRoutingPumps(uint8 enabled) CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue); } -#define CY_AMUX_UNUSED CYREG_BOOST_SR + /******************************************************************************* @@ -317,7 +334,7 @@ void SetAnalogRoutingPumps(uint8 enabled) * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * -* Parameters: +* Parameters: * void * * Return: @@ -394,39 +411,39 @@ void cyfitter_cfg(void) static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004501u, /* Base address: 0x40004500 Count: 1 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */ + 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */ 0x40006401u, /* Base address: 0x40006400 Count: 1 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ 0x40010047u, /* Base address: 0x40010000 Count: 71 */ - 0x4001013Cu, /* Base address: 0x40010100 Count: 60 */ + 0x4001013Fu, /* Base address: 0x40010100 Count: 63 */ 0x4001025Fu, /* Base address: 0x40010200 Count: 95 */ - 0x40010362u, /* Base address: 0x40010300 Count: 98 */ + 0x4001035Eu, /* Base address: 0x40010300 Count: 94 */ 0x4001044Du, /* Base address: 0x40010400 Count: 77 */ - 0x4001055Eu, /* Base address: 0x40010500 Count: 94 */ + 0x4001055Au, /* Base address: 0x40010500 Count: 90 */ 0x40010650u, /* Base address: 0x40010600 Count: 80 */ - 0x40010761u, /* Base address: 0x40010700 Count: 97 */ + 0x40010758u, /* Base address: 0x40010700 Count: 88 */ 0x40010918u, /* Base address: 0x40010900 Count: 24 */ 0x40010A4Eu, /* Base address: 0x40010A00 Count: 78 */ - 0x40010B51u, /* Base address: 0x40010B00 Count: 81 */ + 0x40010B50u, /* Base address: 0x40010B00 Count: 80 */ 0x40010C50u, /* Base address: 0x40010C00 Count: 80 */ - 0x40010D53u, /* Base address: 0x40010D00 Count: 83 */ + 0x40010D57u, /* Base address: 0x40010D00 Count: 87 */ 0x40010E4Au, /* Base address: 0x40010E00 Count: 74 */ - 0x40010F3Eu, /* Base address: 0x40010F00 Count: 62 */ + 0x40010F3Au, /* Base address: 0x40010F00 Count: 58 */ 0x40011414u, /* Base address: 0x40011400 Count: 20 */ - 0x40011548u, /* Base address: 0x40011500 Count: 72 */ + 0x4001154Cu, /* Base address: 0x40011500 Count: 76 */ 0x4001164Fu, /* Base address: 0x40011600 Count: 79 */ - 0x40011755u, /* Base address: 0x40011700 Count: 85 */ - 0x4001190Au, /* Base address: 0x40011900 Count: 10 */ - 0x40011B04u, /* Base address: 0x40011B00 Count: 4 */ - 0x4001401Cu, /* Base address: 0x40014000 Count: 28 */ - 0x4001411Au, /* Base address: 0x40014100 Count: 26 */ + 0x40011759u, /* Base address: 0x40011700 Count: 89 */ + 0x4001190Cu, /* Base address: 0x40011900 Count: 12 */ + 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */ + 0x40014020u, /* Base address: 0x40014000 Count: 32 */ + 0x40014119u, /* Base address: 0x40014100 Count: 25 */ 0x40014217u, /* Base address: 0x40014200 Count: 23 */ - 0x40014311u, /* Base address: 0x40014300 Count: 17 */ - 0x40014414u, /* Base address: 0x40014400 Count: 20 */ - 0x40014518u, /* Base address: 0x40014500 Count: 24 */ + 0x4001430Du, /* Base address: 0x40014300 Count: 13 */ + 0x40014413u, /* Base address: 0x40014400 Count: 19 */ + 0x4001451Au, /* Base address: 0x40014500 Count: 26 */ 0x40014612u, /* Base address: 0x40014600 Count: 18 */ 0x4001470Cu, /* Base address: 0x40014700 Count: 12 */ - 0x40014808u, /* Base address: 0x40014800 Count: 8 */ + 0x4001480Au, /* Base address: 0x40014800 Count: 10 */ 0x4001490Eu, /* Base address: 0x40014900 Count: 14 */ 0x40015004u, /* Base address: 0x40015000 Count: 4 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ @@ -436,10 +453,9 @@ void cyfitter_cfg(void) {0x7Eu, 0x02u}, {0x01u, 0x20u}, {0x0Au, 0x4Bu}, - {0x00u, 0x20u}, - {0x01u, 0x02u}, - {0x10u, 0x88u}, - {0x11u, 0x22u}, + {0x01u, 0x22u}, + {0x10u, 0x28u}, + {0x11u, 0x02u}, {0x18u, 0x10u}, {0x19u, 0x08u}, {0x1Cu, 0x20u}, @@ -450,33 +466,33 @@ void cyfitter_cfg(void) {0x7Cu, 0x40u}, {0x20u, 0x01u}, {0x84u, 0x0Fu}, - {0x01u, 0x0Bu}, - {0x03u, 0x34u}, - {0x04u, 0x11u}, - {0x05u, 0x11u}, - {0x06u, 0x02u}, - {0x07u, 0x2Cu}, - {0x08u, 0x13u}, + {0x01u, 0x11u}, + {0x03u, 0x2Cu}, + {0x05u, 0x0Bu}, + {0x07u, 0x34u}, {0x09u, 0x06u}, - {0x0Au, 0x2Cu}, + {0x0Fu, 0x10u}, {0x10u, 0x02u}, {0x11u, 0x20u}, {0x12u, 0x01u}, + {0x14u, 0x11u}, + {0x16u, 0x02u}, + {0x18u, 0x13u}, {0x19u, 0x01u}, - {0x1Cu, 0x24u}, - {0x1Eu, 0x08u}, + {0x1Au, 0x2Cu}, + {0x1Du, 0x0Au}, + {0x1Fu, 0x15u}, {0x20u, 0x08u}, {0x22u, 0x04u}, {0x23u, 0x3Fu}, - {0x29u, 0x0Au}, - {0x2Bu, 0x15u}, - {0x2Fu, 0x10u}, - {0x32u, 0x30u}, - {0x35u, 0x3Fu}, + {0x2Cu, 0x24u}, + {0x2Eu, 0x08u}, + {0x30u, 0x30u}, {0x36u, 0x0Fu}, - {0x3Eu, 0x44u}, - {0x40u, 0x32u}, - {0x41u, 0x04u}, + {0x37u, 0x3Fu}, + {0x3Eu, 0x41u}, + {0x40u, 0x45u}, + {0x41u, 0x03u}, {0x42u, 0x60u}, {0x45u, 0xF2u}, {0x46u, 0xCDu}, @@ -500,127 +516,130 @@ void cyfitter_cfg(void) {0x68u, 0x40u}, {0x69u, 0x40u}, {0x6Eu, 0x08u}, - {0x82u, 0xFFu}, - {0x88u, 0x0Fu}, - {0x8Au, 0xF0u}, + {0x80u, 0xFFu}, {0x8Cu, 0xFFu}, {0x92u, 0xFFu}, {0x96u, 0xFFu}, + {0x98u, 0x0Fu}, + {0x9Au, 0xF0u}, {0x9Cu, 0x33u}, {0x9Eu, 0xCCu}, {0xA0u, 0x55u}, {0xA2u, 0xAAu}, {0xA4u, 0x69u}, {0xA6u, 0x96u}, - {0xA8u, 0xFFu}, - {0xB2u, 0xFFu}, - {0xBAu, 0x08u}, + {0xAEu, 0xFFu}, + {0xB6u, 0xFFu}, + {0xBAu, 0x80u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xDBu, 0x04u}, {0xDCu, 0x01u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x20u}, - {0x03u, 0x10u}, - {0x04u, 0x90u}, - {0x05u, 0x01u}, - {0x0Bu, 0x82u}, - {0x0Du, 0x06u}, - {0x0Fu, 0x02u}, + {0x07u, 0x82u}, + {0x09u, 0x08u}, + {0x0Au, 0x04u}, + {0x0Bu, 0x80u}, + {0x0Du, 0x01u}, + {0x0Eu, 0x10u}, + {0x0Fu, 0x0Au}, + {0x10u, 0x01u}, {0x11u, 0x01u}, - {0x15u, 0x20u}, - {0x16u, 0xA0u}, + {0x16u, 0xA1u}, + {0x18u, 0x40u}, {0x1Au, 0x02u}, - {0x1Bu, 0x04u}, - {0x1Cu, 0x10u}, - {0x1Fu, 0x04u}, - {0x21u, 0x10u}, - {0x28u, 0x08u}, - {0x29u, 0x01u}, - {0x2Au, 0x41u}, + {0x1Fu, 0x80u}, + {0x20u, 0x02u}, + {0x22u, 0x40u}, + {0x23u, 0x02u}, + {0x2Au, 0x01u}, {0x2Cu, 0x40u}, {0x2Eu, 0x01u}, {0x30u, 0x20u}, - {0x32u, 0x02u}, + {0x32u, 0x42u}, {0x38u, 0x20u}, - {0x39u, 0x0Au}, - {0x40u, 0x08u}, - {0x41u, 0x17u}, - {0x49u, 0x20u}, + {0x39u, 0x02u}, + {0x3Au, 0x40u}, + {0x3Bu, 0x08u}, + {0x41u, 0x01u}, + {0x42u, 0x10u}, + {0x48u, 0x01u}, + {0x49u, 0x28u}, {0x4Au, 0xA0u}, {0x50u, 0x10u}, {0x52u, 0x40u}, {0x53u, 0x08u}, - {0x59u, 0x42u}, + {0x59u, 0x82u}, {0x5Au, 0x28u}, {0x5Cu, 0xA0u}, {0x61u, 0x10u}, {0x63u, 0xA1u}, {0x66u, 0xA0u}, {0x68u, 0x84u}, - {0x6Bu, 0x21u}, - {0x71u, 0x24u}, + {0x69u, 0x80u}, + {0x6Bu, 0x20u}, + {0x71u, 0x25u}, {0x72u, 0x01u}, - {0x73u, 0x40u}, + {0x80u, 0x40u}, {0x81u, 0x04u}, - {0x82u, 0xC0u}, + {0x82u, 0x40u}, {0x85u, 0x20u}, {0x87u, 0x08u}, {0x8Cu, 0x10u}, - {0x8Fu, 0x04u}, - {0xC0u, 0xD6u}, - {0xC2u, 0xB9u}, - {0xC4u, 0x78u}, - {0xCAu, 0x0Du}, - {0xCCu, 0x05u}, - {0xCEu, 0x07u}, - {0xD0u, 0x07u}, - {0xD2u, 0x04u}, + {0x8Fu, 0x84u}, + {0xC0u, 0x90u}, + {0xC2u, 0xFEu}, + {0xC4u, 0xB9u}, + {0xCAu, 0x01u}, + {0xCCu, 0x0Du}, + {0xCEu, 0x0Fu}, + {0xD0u, 0x03u}, + {0xD2u, 0x0Cu}, {0xD6u, 0x3Fu}, {0xD8u, 0x3Fu}, {0xE0u, 0x18u}, - {0xE4u, 0x03u}, - {0x00u, 0xF0u}, - {0x02u, 0x08u}, + {0xE4u, 0x07u}, + {0x00u, 0x10u}, + {0x02u, 0x20u}, {0x04u, 0x40u}, {0x05u, 0x03u}, {0x06u, 0x80u}, {0x07u, 0x0Cu}, {0x09u, 0x80u}, {0x0Cu, 0x02u}, - {0x0Du, 0x06u}, + {0x0Du, 0x40u}, {0x0Eu, 0xF0u}, - {0x0Fu, 0x09u}, - {0x10u, 0x05u}, - {0x11u, 0x10u}, + {0x0Fu, 0x1Fu}, + {0x10u, 0x01u}, + {0x11u, 0x20u}, {0x12u, 0xF8u}, - {0x13u, 0x2Fu}, - {0x14u, 0x01u}, - {0x15u, 0x40u}, + {0x13u, 0x4Fu}, + {0x14u, 0x05u}, + {0x15u, 0x06u}, {0x16u, 0xF8u}, - {0x17u, 0x1Fu}, - {0x19u, 0x20u}, + {0x17u, 0x09u}, {0x1Au, 0x01u}, - {0x1Bu, 0x4Fu}, {0x1Cu, 0x10u}, {0x1Eu, 0x20u}, {0x1Fu, 0x70u}, - {0x20u, 0x10u}, - {0x22u, 0x20u}, + {0x20u, 0xF4u}, + {0x21u, 0x05u}, + {0x22u, 0x08u}, + {0x23u, 0x0Au}, {0x24u, 0x40u}, {0x25u, 0x0Fu}, {0x26u, 0x80u}, - {0x28u, 0xF4u}, - {0x29u, 0x05u}, - {0x2Au, 0x08u}, - {0x2Bu, 0x0Au}, - {0x30u, 0x0Fu}, + {0x29u, 0x10u}, + {0x2Bu, 0x2Fu}, + {0x2Cu, 0xF0u}, + {0x2Eu, 0x08u}, {0x31u, 0x7Fu}, + {0x32u, 0x0Fu}, {0x34u, 0xC0u}, {0x35u, 0x80u}, {0x36u, 0x30u}, - {0x38u, 0x02u}, + {0x38u, 0x08u}, {0x3Au, 0xA0u}, {0x3Fu, 0x10u}, {0x54u, 0x01u}, @@ -630,14 +649,13 @@ void cyfitter_cfg(void) {0x5Cu, 0x11u}, {0x5Du, 0x10u}, {0x5Fu, 0x01u}, + {0x80u, 0x3Fu}, {0x83u, 0x7Fu}, {0x84u, 0x01u}, - {0x85u, 0x20u}, + {0x85u, 0x01u}, {0x86u, 0x02u}, - {0x87u, 0x40u}, - {0x88u, 0x3Fu}, - {0x89u, 0x78u}, - {0x8Bu, 0x03u}, + {0x87u, 0x6Eu}, + {0x8Au, 0x3Fu}, {0x8Cu, 0x10u}, {0x8Du, 0x02u}, {0x8Eu, 0x20u}, @@ -645,11 +663,10 @@ void cyfitter_cfg(void) {0x91u, 0x64u}, {0x92u, 0x20u}, {0x95u, 0x03u}, - {0x96u, 0x3Fu}, {0x97u, 0x74u}, - {0x99u, 0x80u}, + {0x99u, 0x20u}, {0x9Au, 0x3Fu}, - {0x9Bu, 0x01u}, + {0x9Bu, 0x40u}, {0x9Cu, 0x04u}, {0x9Eu, 0x08u}, {0xA0u, 0x3Fu}, @@ -657,139 +674,137 @@ void cyfitter_cfg(void) {0xA3u, 0x40u}, {0xA4u, 0x01u}, {0xA6u, 0x02u}, + {0xA7u, 0x08u}, {0xA8u, 0x04u}, + {0xA9u, 0x80u}, {0xAAu, 0x08u}, - {0xABu, 0x08u}, - {0xADu, 0x01u}, + {0xABu, 0x01u}, + {0xADu, 0x78u}, {0xAEu, 0x3Fu}, - {0xAFu, 0x6Eu}, + {0xAFu, 0x03u}, {0xB0u, 0x30u}, - {0xB1u, 0x80u}, - {0xB3u, 0x1Fu}, + {0xB1u, 0x1Fu}, {0xB4u, 0x03u}, {0xB5u, 0x60u}, {0xB6u, 0x0Cu}, + {0xB7u, 0x80u}, {0xBAu, 0xA2u}, {0xBBu, 0x20u}, - {0xBFu, 0x01u}, + {0xBFu, 0x40u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDCu, 0x11u}, {0xDFu, 0x01u}, - {0x01u, 0x10u}, - {0x03u, 0x22u}, + {0x00u, 0x02u}, + {0x03u, 0x2Au}, {0x04u, 0x04u}, - {0x06u, 0x01u}, - {0x07u, 0x80u}, + {0x06u, 0x81u}, {0x08u, 0x02u}, - {0x09u, 0x08u}, - {0x0Au, 0x05u}, - {0x0Cu, 0x21u}, - {0x0Du, 0x0Au}, - {0x0Eu, 0x02u}, - {0x10u, 0x04u}, + {0x0Au, 0x01u}, + {0x0Bu, 0x08u}, + {0x0Cu, 0x20u}, + {0x0Eu, 0x12u}, + {0x0Fu, 0x48u}, {0x11u, 0x02u}, - {0x12u, 0x01u}, + {0x12u, 0x09u}, {0x13u, 0x08u}, - {0x15u, 0x30u}, - {0x16u, 0xA0u}, - {0x19u, 0x42u}, + {0x16u, 0x20u}, + {0x17u, 0x82u}, + {0x19u, 0x82u}, {0x1Au, 0x01u}, {0x1Bu, 0x32u}, {0x1Cu, 0x04u}, - {0x1Du, 0x12u}, - {0x1Eu, 0x02u}, - {0x20u, 0x80u}, - {0x21u, 0x0Cu}, - {0x22u, 0x18u}, - {0x23u, 0x04u}, + {0x1Du, 0x10u}, + {0x1Eu, 0x12u}, + {0x1Fu, 0x04u}, + {0x21u, 0x01u}, + {0x22u, 0x90u}, + {0x23u, 0x40u}, {0x26u, 0x10u}, {0x27u, 0x40u}, - {0x28u, 0x09u}, + {0x29u, 0x48u}, {0x2Au, 0x02u}, + {0x2Bu, 0x04u}, {0x2Cu, 0x20u}, - {0x2Fu, 0x04u}, - {0x30u, 0x20u}, - {0x31u, 0x08u}, - {0x32u, 0x02u}, - {0x34u, 0x01u}, - {0x36u, 0x48u}, - {0x37u, 0x60u}, - {0x39u, 0x20u}, + {0x2Fu, 0x84u}, + {0x32u, 0x12u}, + {0x33u, 0x08u}, + {0x34u, 0x08u}, + {0x36u, 0x40u}, + {0x37u, 0x42u}, {0x3Au, 0x41u}, - {0x3Bu, 0x04u}, - {0x3Du, 0xA8u}, - {0x59u, 0x01u}, - {0x5Bu, 0x01u}, + {0x3Bu, 0x08u}, + {0x3Du, 0x28u}, + {0x3Fu, 0x40u}, + {0x58u, 0x04u}, + {0x5Au, 0x04u}, {0x5Eu, 0x82u}, {0x5Fu, 0x01u}, - {0x60u, 0x08u}, - {0x62u, 0x20u}, {0x6Cu, 0x22u}, {0x6Du, 0x20u}, {0x80u, 0x04u}, {0x82u, 0x02u}, - {0x84u, 0x10u}, - {0x85u, 0x90u}, - {0x87u, 0x20u}, - {0x88u, 0x04u}, - {0x89u, 0x40u}, - {0x91u, 0x20u}, + {0x86u, 0x18u}, + {0x88u, 0x08u}, + {0x89u, 0x04u}, + {0x8Au, 0x08u}, + {0x8Bu, 0x48u}, + {0x8Eu, 0x10u}, + {0x91u, 0x80u}, {0x92u, 0x42u}, - {0x93u, 0x48u}, - {0x94u, 0x80u}, - {0x95u, 0x09u}, - {0x96u, 0x28u}, - {0x97u, 0x83u}, + {0x95u, 0x03u}, + {0x96u, 0x3Cu}, + {0x97u, 0x89u}, {0x98u, 0x50u}, + {0x99u, 0x09u}, {0x9Au, 0xE0u}, - {0x9Bu, 0x01u}, - {0x9Cu, 0x20u}, - {0x9Du, 0x72u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0x21u}, + {0x9Du, 0xB2u}, {0x9Eu, 0x01u}, - {0x9Fu, 0x10u}, - {0xA0u, 0x80u}, + {0x9Fu, 0x80u}, + {0xA0u, 0x81u}, {0xA2u, 0x20u}, - {0xA4u, 0x30u}, - {0xA5u, 0x02u}, + {0xA3u, 0x80u}, + {0xA4u, 0x20u}, + {0xA5u, 0x08u}, {0xA6u, 0x02u}, {0xA7u, 0x51u}, {0xA8u, 0x80u}, {0xABu, 0x20u}, {0xACu, 0x04u}, - {0xADu, 0x14u}, {0xB0u, 0x10u}, {0xB2u, 0xC0u}, - {0xC0u, 0xB7u}, - {0xC2u, 0xFFu}, - {0xC4u, 0x7Fu}, - {0xCAu, 0x6Du}, - {0xCCu, 0xF7u}, - {0xCEu, 0x7Fu}, + {0xB6u, 0x80u}, + {0xC0u, 0xBFu}, + {0xC2u, 0xFBu}, + {0xC4u, 0xBFu}, + {0xCAu, 0xEFu}, + {0xCCu, 0xD7u}, + {0xCEu, 0x7Bu}, {0xD6u, 0x10u}, - {0xE0u, 0x02u}, - {0xE2u, 0x0Cu}, {0xE4u, 0x01u}, - {0xE6u, 0x0Cu}, - {0xE8u, 0x0Bu}, + {0xE6u, 0x26u}, + {0xE8u, 0x01u}, + {0xEAu, 0x40u}, {0xECu, 0x02u}, {0xEEu, 0x01u}, + {0x02u, 0x20u}, + {0x05u, 0x24u}, + {0x07u, 0x09u}, {0x0Au, 0x10u}, {0x0Bu, 0x18u}, - {0x0Cu, 0x05u}, - {0x0Eu, 0x0Au}, - {0x0Fu, 0x20u}, + {0x0Fu, 0x04u}, {0x10u, 0x04u}, - {0x11u, 0x24u}, - {0x13u, 0x09u}, {0x14u, 0x01u}, - {0x17u, 0x24u}, - {0x1Au, 0x20u}, {0x1Bu, 0x03u}, {0x20u, 0x08u}, - {0x23u, 0x04u}, - {0x29u, 0x24u}, - {0x2Bu, 0x12u}, + {0x23u, 0x20u}, + {0x25u, 0x24u}, + {0x27u, 0x12u}, + {0x28u, 0x05u}, + {0x2Au, 0x0Au}, + {0x2Bu, 0x24u}, {0x2Cu, 0x02u}, {0x30u, 0x10u}, {0x32u, 0x20u}, @@ -805,17 +820,17 @@ void cyfitter_cfg(void) {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x17u}, + {0x80u, 0x04u}, {0x81u, 0x02u}, - {0x82u, 0x28u}, {0x83u, 0x15u}, - {0x84u, 0x29u}, - {0x86u, 0x46u}, - {0x88u, 0x02u}, + {0x88u, 0x29u}, + {0x89u, 0x02u}, + {0x8Au, 0x46u}, + {0x8Bu, 0x01u}, {0x8Cu, 0xD6u}, - {0x8Du, 0x02u}, - {0x8Fu, 0x21u}, + {0x90u, 0x17u}, {0x91u, 0x08u}, + {0x92u, 0x28u}, {0x93u, 0x10u}, {0x94u, 0xD0u}, {0x95u, 0x01u}, @@ -824,23 +839,23 @@ void cyfitter_cfg(void) {0x98u, 0xD2u}, {0x99u, 0x02u}, {0x9Au, 0x04u}, - {0x9Bu, 0x01u}, + {0x9Bu, 0x21u}, {0x9Cu, 0x20u}, + {0x9Du, 0x02u}, {0x9Eu, 0xD0u}, + {0x9Fu, 0x01u}, {0xA0u, 0xD6u}, {0xA4u, 0x21u}, - {0xA5u, 0x02u}, {0xA6u, 0x8Eu}, - {0xA7u, 0x01u}, - {0xA8u, 0x04u}, + {0xA8u, 0x02u}, {0xACu, 0xD6u}, {0xB1u, 0x18u}, - {0xB2u, 0x0Fu}, {0xB3u, 0x03u}, - {0xB5u, 0x20u}, + {0xB4u, 0x0Fu}, + {0xB5u, 0x04u}, {0xB6u, 0xF0u}, - {0xB7u, 0x04u}, - {0xB8u, 0x08u}, + {0xB7u, 0x20u}, + {0xB8u, 0x20u}, {0xBAu, 0x80u}, {0xBBu, 0x08u}, {0xBFu, 0x01u}, @@ -852,44 +867,42 @@ void cyfitter_cfg(void) {0xDDu, 0x90u}, {0xDFu, 0x01u}, {0x00u, 0x20u}, - {0x01u, 0x80u}, - {0x04u, 0x20u}, - {0x05u, 0x44u}, - {0x07u, 0x40u}, - {0x09u, 0x10u}, + {0x02u, 0x80u}, + {0x05u, 0x52u}, {0x0Bu, 0xA0u}, {0x0Cu, 0x28u}, + {0x0Du, 0x02u}, {0x0Eu, 0x02u}, - {0x10u, 0x01u}, + {0x10u, 0x04u}, {0x11u, 0x01u}, - {0x16u, 0x86u}, - {0x17u, 0x04u}, - {0x19u, 0x0Au}, - {0x1Au, 0x02u}, - {0x1Bu, 0x10u}, - {0x1Du, 0x04u}, + {0x13u, 0x40u}, + {0x16u, 0x80u}, + {0x17u, 0x54u}, + {0x18u, 0x80u}, + {0x1Au, 0x12u}, + {0x1Bu, 0x20u}, + {0x1Cu, 0x08u}, + {0x1Du, 0x10u}, {0x1Eu, 0x02u}, - {0x1Fu, 0x08u}, {0x20u, 0x10u}, {0x22u, 0x10u}, - {0x24u, 0x80u}, - {0x25u, 0x51u}, - {0x26u, 0x1Au}, + {0x25u, 0x01u}, + {0x26u, 0x9Au}, {0x27u, 0x80u}, - {0x28u, 0x04u}, + {0x28u, 0x20u}, {0x29u, 0x01u}, - {0x2Du, 0x08u}, - {0x31u, 0x0Au}, + {0x2Bu, 0x08u}, {0x32u, 0x10u}, - {0x36u, 0x18u}, + {0x36u, 0x98u}, {0x37u, 0x01u}, {0x38u, 0x10u}, + {0x39u, 0x80u}, {0x3Au, 0x20u}, - {0x3Bu, 0x60u}, - {0x3Du, 0x80u}, + {0x3Bu, 0x28u}, + {0x3Eu, 0x10u}, {0x3Fu, 0x01u}, - {0x44u, 0x04u}, - {0x47u, 0x20u}, + {0x44u, 0x01u}, + {0x46u, 0x02u}, {0x58u, 0x90u}, {0x5Eu, 0x40u}, {0x5Fu, 0x10u}, @@ -897,63 +910,65 @@ void cyfitter_cfg(void) {0x63u, 0x02u}, {0x67u, 0x05u}, {0x6Fu, 0x01u}, - {0x81u, 0x40u}, - {0x83u, 0x08u}, {0x86u, 0x01u}, - {0x88u, 0x80u}, + {0x87u, 0x20u}, + {0x88u, 0xA1u}, {0x89u, 0x04u}, {0x8Du, 0x04u}, - {0x8Fu, 0x10u}, - {0x92u, 0x44u}, - {0x93u, 0x50u}, - {0x94u, 0x88u}, + {0x8Eu, 0x08u}, + {0x91u, 0x84u}, + {0x92u, 0x40u}, + {0x93u, 0x18u}, + {0x94u, 0x08u}, {0x95u, 0x01u}, {0x96u, 0x08u}, - {0x97u, 0x82u}, - {0x98u, 0x50u}, - {0x99u, 0x81u}, + {0x97u, 0x80u}, + {0x98u, 0x54u}, + {0x99u, 0x01u}, {0x9Au, 0x48u}, - {0x9Bu, 0x20u}, - {0x9Cu, 0x02u}, + {0x9Cu, 0x03u}, {0x9Du, 0x20u}, {0x9Eu, 0x01u}, - {0x9Fu, 0x98u}, - {0xA0u, 0xC2u}, - {0xA1u, 0x0Au}, + {0x9Fu, 0x88u}, + {0xA0u, 0x83u}, {0xA2u, 0x20u}, - {0xA5u, 0x05u}, + {0xA3u, 0x08u}, + {0xA5u, 0x0Du}, {0xA6u, 0x02u}, {0xA7u, 0x41u}, {0xACu, 0x20u}, - {0xAEu, 0x01u}, + {0xAEu, 0x81u}, {0xAFu, 0x10u}, - {0xB1u, 0x02u}, - {0xB2u, 0x14u}, + {0xB0u, 0x01u}, + {0xB1u, 0x41u}, + {0xB2u, 0x04u}, {0xB4u, 0x20u}, - {0xB6u, 0x08u}, - {0xC0u, 0xF3u}, - {0xC2u, 0xEEu}, - {0xC4u, 0xF9u}, - {0xCAu, 0x45u}, - {0xCCu, 0xE7u}, - {0xCEu, 0x9Cu}, + {0xC0u, 0xDAu}, + {0xC2u, 0xFCu}, + {0xC4u, 0xFBu}, + {0xCAu, 0x07u}, + {0xCCu, 0xF4u}, + {0xCEu, 0xAEu}, {0xD6u, 0x3Cu}, {0xD8u, 0x3Cu}, - {0xE0u, 0x01u}, - {0xE4u, 0x03u}, + {0xE2u, 0x02u}, + {0xE4u, 0x0Au}, {0xE6u, 0x20u}, {0xE8u, 0x02u}, - {0xEAu, 0x80u}, {0xECu, 0x42u}, {0x01u, 0x02u}, + {0x02u, 0x12u}, {0x03u, 0x01u}, {0x05u, 0x02u}, {0x06u, 0x01u}, {0x07u, 0x11u}, + {0x08u, 0x04u}, {0x09u, 0x02u}, + {0x0Au, 0x43u}, {0x0Bu, 0x05u}, + {0x10u, 0x21u}, {0x11u, 0x01u}, - {0x12u, 0x12u}, + {0x12u, 0x02u}, {0x13u, 0x02u}, {0x15u, 0x02u}, {0x17u, 0x09u}, @@ -961,10 +976,6 @@ void cyfitter_cfg(void) {0x20u, 0xE0u}, {0x24u, 0x88u}, {0x26u, 0x03u}, - {0x28u, 0x04u}, - {0x2Au, 0x43u}, - {0x2Cu, 0x21u}, - {0x2Eu, 0x02u}, {0x31u, 0x04u}, {0x32u, 0x10u}, {0x33u, 0x10u}, @@ -978,29 +989,31 @@ void cyfitter_cfg(void) {0x59u, 0x04u}, {0x5Cu, 0x10u}, {0x5Fu, 0x01u}, - {0x80u, 0x02u}, + {0x80u, 0xFDu}, + {0x82u, 0x02u}, {0x84u, 0x10u}, {0x85u, 0x50u}, {0x86u, 0x20u}, {0x87u, 0xA0u}, - {0x88u, 0xFDu}, - {0x8Au, 0x02u}, - {0x8Eu, 0xF7u}, + {0x88u, 0x0Bu}, + {0x89u, 0x60u}, + {0x8Au, 0xF4u}, + {0x8Bu, 0x90u}, + {0x8Cu, 0xF4u}, + {0x8Du, 0x30u}, + {0x8Fu, 0xC0u}, {0x90u, 0x03u}, - {0x91u, 0x30u}, {0x92u, 0x0Cu}, - {0x93u, 0xC0u}, - {0x94u, 0x0Bu}, - {0x96u, 0xF4u}, + {0x94u, 0x40u}, + {0x95u, 0x0Fu}, + {0x96u, 0x80u}, + {0x97u, 0xF0u}, {0x98u, 0x08u}, - {0x99u, 0x60u}, {0x9Au, 0xF7u}, - {0x9Bu, 0x90u}, {0x9Cu, 0x40u}, {0x9Eu, 0x80u}, - {0xA0u, 0x40u}, + {0xA0u, 0x02u}, {0xA1u, 0x05u}, - {0xA2u, 0x80u}, {0xA3u, 0x0Au}, {0xA5u, 0x06u}, {0xA6u, 0x01u}, @@ -1009,9 +1022,7 @@ void cyfitter_cfg(void) {0xA9u, 0x03u}, {0xAAu, 0x20u}, {0xABu, 0x0Cu}, - {0xACu, 0xF4u}, - {0xADu, 0x0Fu}, - {0xAFu, 0xF0u}, + {0xAEu, 0xF7u}, {0xB0u, 0x0Fu}, {0xB3u, 0xFFu}, {0xB4u, 0x30u}, @@ -1025,24 +1036,24 @@ void cyfitter_cfg(void) {0xDBu, 0x04u}, {0xDCu, 0x01u}, {0xDFu, 0x01u}, - {0x00u, 0x14u}, - {0x02u, 0x40u}, - {0x03u, 0x01u}, - {0x05u, 0x04u}, + {0x00u, 0x06u}, + {0x02u, 0x02u}, + {0x03u, 0x08u}, + {0x04u, 0x02u}, + {0x05u, 0x14u}, {0x06u, 0x01u}, {0x07u, 0x01u}, - {0x09u, 0x08u}, - {0x0Au, 0x46u}, + {0x08u, 0x08u}, + {0x0Au, 0x42u}, + {0x0Bu, 0x08u}, {0x0Du, 0x02u}, {0x0Eu, 0x02u}, {0x11u, 0x10u}, - {0x12u, 0x22u}, - {0x13u, 0x02u}, - {0x14u, 0x04u}, + {0x12u, 0x61u}, {0x15u, 0x02u}, - {0x17u, 0x44u}, + {0x17u, 0x04u}, {0x1Au, 0x4Au}, - {0x1Bu, 0x41u}, + {0x1Bu, 0x40u}, {0x1Du, 0x04u}, {0x1Eu, 0x02u}, {0x1Fu, 0x10u}, @@ -1051,109 +1062,100 @@ void cyfitter_cfg(void) {0x26u, 0x04u}, {0x27u, 0x01u}, {0x28u, 0x80u}, - {0x29u, 0x80u}, {0x2Au, 0x28u}, - {0x2Cu, 0x04u}, - {0x2Fu, 0x08u}, - {0x30u, 0x01u}, - {0x31u, 0x11u}, + {0x30u, 0x04u}, {0x36u, 0x04u}, {0x37u, 0x01u}, - {0x38u, 0x08u}, + {0x38u, 0x28u}, + {0x3Bu, 0x40u}, {0x3Du, 0x22u}, {0x3Fu, 0x04u}, - {0x40u, 0x02u}, - {0x43u, 0x80u}, {0x4Du, 0x10u}, {0x4Eu, 0x04u}, - {0x5Cu, 0x10u}, - {0x5Fu, 0x20u}, - {0x60u, 0x02u}, - {0x62u, 0x18u}, - {0x63u, 0x40u}, - {0x67u, 0x03u}, - {0x69u, 0x89u}, + {0x60u, 0x40u}, + {0x62u, 0x98u}, + {0x69u, 0x09u}, {0x6Au, 0x20u}, - {0x70u, 0x04u}, - {0x71u, 0x11u}, - {0x73u, 0x01u}, + {0x6Bu, 0x02u}, + {0x70u, 0x14u}, + {0x72u, 0x02u}, + {0x73u, 0x40u}, {0x80u, 0x80u}, - {0x84u, 0x04u}, - {0x86u, 0x10u}, - {0x8Bu, 0x51u}, - {0x8Du, 0x10u}, - {0x90u, 0x04u}, - {0x92u, 0x04u}, - {0x93u, 0x04u}, - {0x94u, 0x28u}, - {0x95u, 0x89u}, + {0x87u, 0x02u}, + {0x8Bu, 0x10u}, + {0x8Cu, 0x40u}, + {0x90u, 0x84u}, + {0x91u, 0x04u}, + {0x93u, 0x0Cu}, + {0x94u, 0x08u}, + {0x95u, 0x09u}, {0x96u, 0x08u}, - {0x97u, 0x82u}, - {0x98u, 0x40u}, - {0x99u, 0x82u}, + {0x97u, 0xC0u}, + {0x98u, 0x4Cu}, + {0x99u, 0x10u}, {0x9Au, 0x68u}, - {0x9Bu, 0x22u}, - {0x9Cu, 0x01u}, - {0x9Du, 0x60u}, - {0x9Eu, 0x87u}, + {0x9Du, 0x62u}, + {0x9Eu, 0x83u}, {0x9Fu, 0x54u}, - {0xA0u, 0x82u}, - {0xA1u, 0x08u}, + {0xA0u, 0x87u}, {0xA2u, 0x22u}, - {0xA3u, 0x08u}, + {0xA3u, 0x18u}, {0xA4u, 0x38u}, + {0xA5u, 0x0Au}, {0xA7u, 0x40u}, {0xAAu, 0x10u}, - {0xABu, 0x08u}, - {0xACu, 0x40u}, - {0xAFu, 0x02u}, + {0xABu, 0x10u}, + {0xAFu, 0x08u}, + {0xB0u, 0x08u}, {0xB2u, 0x08u}, {0xB4u, 0x04u}, + {0xB5u, 0x10u}, {0xB6u, 0x02u}, - {0xC0u, 0x2Fu}, + {0xC0u, 0x7Fu}, {0xC2u, 0x9Fu}, - {0xC4u, 0xFFu}, - {0xCAu, 0x0Fu}, - {0xCCu, 0xC5u}, - {0xCEu, 0xE2u}, + {0xC4u, 0x3Fu}, + {0xCAu, 0x07u}, + {0xCCu, 0xC2u}, + {0xCEu, 0xEEu}, {0xD8u, 0x0Fu}, - {0xE2u, 0x2Au}, - {0xE6u, 0x41u}, - {0xEAu, 0x04u}, + {0xE2u, 0x48u}, + {0xE4u, 0x02u}, + {0xE6u, 0x01u}, + {0xEAu, 0x0Au}, {0xECu, 0x04u}, - {0xEEu, 0x02u}, + {0xEEu, 0x03u}, {0x82u, 0x01u}, - {0x89u, 0x40u}, + {0x84u, 0x02u}, {0x8Bu, 0x40u}, - {0x8Du, 0x40u}, - {0x90u, 0x20u}, - {0x95u, 0x44u}, - {0x97u, 0x80u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x08u}, + {0x94u, 0x01u}, + {0x95u, 0x04u}, + {0x97u, 0x84u}, + {0x9Cu, 0x02u}, {0xA2u, 0x01u}, - {0xA5u, 0x18u}, + {0xA4u, 0xA0u}, + {0xA5u, 0x14u}, {0xA7u, 0x20u}, - {0xA8u, 0x01u}, - {0xA9u, 0x28u}, + {0xA8u, 0x10u}, {0xAAu, 0x04u}, - {0xACu, 0x02u}, - {0xB1u, 0x80u}, - {0xB4u, 0xA0u}, - {0xB7u, 0x28u}, - {0xE0u, 0xC0u}, - {0xE2u, 0x0Au}, + {0xADu, 0x20u}, + {0xAEu, 0x01u}, + {0xB1u, 0xC0u}, + {0xB4u, 0x80u}, + {0xB6u, 0x82u}, + {0xB7u, 0x08u}, + {0xE2u, 0x08u}, {0xE4u, 0x80u}, - {0xE6u, 0x40u}, + {0xE8u, 0x40u}, + {0xEAu, 0x82u}, {0xECu, 0xD0u}, + {0x00u, 0x02u}, {0x01u, 0x02u}, + {0x02u, 0x05u}, {0x03u, 0x01u}, {0x04u, 0x01u}, {0x06u, 0x02u}, {0x0Du, 0x01u}, {0x0Fu, 0x02u}, - {0x10u, 0x02u}, - {0x12u, 0x05u}, {0x14u, 0x02u}, {0x15u, 0x02u}, {0x16u, 0x11u}, @@ -1183,32 +1185,32 @@ void cyfitter_cfg(void) {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, + {0x80u, 0xFFu}, {0x81u, 0x03u}, {0x83u, 0x04u}, {0x84u, 0x33u}, - {0x85u, 0x10u}, + {0x85u, 0x08u}, {0x86u, 0xCCu}, {0x88u, 0x69u}, {0x89u, 0x05u}, {0x8Au, 0x96u}, {0x8Bu, 0x02u}, - {0x8Du, 0x20u}, + {0x8Du, 0x50u}, + {0x8Eu, 0xFFu}, + {0x8Fu, 0xA0u}, {0x90u, 0x0Fu}, - {0x91u, 0x50u}, + {0x91u, 0x80u}, {0x92u, 0xF0u}, - {0x93u, 0xA0u}, {0x95u, 0x40u}, - {0x96u, 0xFFu}, - {0x98u, 0xFFu}, {0x99u, 0x04u}, + {0x9Au, 0xFFu}, {0x9Bu, 0x03u}, - {0x9Du, 0x08u}, - {0xA2u, 0xFFu}, + {0x9Cu, 0xFFu}, + {0xA1u, 0x20u}, {0xA5u, 0x01u}, {0xA6u, 0xFFu}, {0xA7u, 0x06u}, - {0xA8u, 0xFFu}, - {0xA9u, 0x80u}, + {0xA9u, 0x10u}, {0xACu, 0x55u}, {0xAEu, 0xAAu}, {0xB0u, 0xFFu}, @@ -1224,118 +1226,117 @@ void cyfitter_cfg(void) {0xDBu, 0x04u}, {0xDCu, 0x01u}, {0xDFu, 0x01u}, - {0x01u, 0x08u}, - {0x06u, 0x20u}, + {0x01u, 0x0Au}, + {0x04u, 0x80u}, + {0x06u, 0xA0u}, {0x07u, 0x08u}, {0x08u, 0x08u}, - {0x0Au, 0x85u}, - {0x0Cu, 0x20u}, - {0x0Du, 0x08u}, + {0x0Au, 0x05u}, {0x0Eu, 0x40u}, - {0x14u, 0x01u}, - {0x15u, 0x01u}, - {0x16u, 0x10u}, - {0x17u, 0x20u}, - {0x19u, 0x08u}, - {0x1Au, 0x95u}, + {0x0Fu, 0x06u}, + {0x14u, 0x11u}, + {0x19u, 0x0Au}, + {0x1Au, 0x15u}, {0x1Eu, 0x40u}, {0x21u, 0x41u}, {0x22u, 0x14u}, - {0x24u, 0x20u}, + {0x24u, 0x10u}, {0x26u, 0x02u}, - {0x27u, 0x16u}, - {0x2Cu, 0x08u}, - {0x2Eu, 0x08u}, + {0x27u, 0x26u}, + {0x2Cu, 0xA0u}, + {0x2Fu, 0x08u}, {0x31u, 0x80u}, {0x32u, 0x14u}, - {0x35u, 0x40u}, + {0x34u, 0x02u}, {0x36u, 0x04u}, - {0x37u, 0x11u}, + {0x37u, 0x20u}, {0x38u, 0x40u}, {0x39u, 0x82u}, - {0x3Cu, 0x04u}, - {0x3Du, 0x62u}, - {0x58u, 0xA0u}, + {0x3Du, 0xA8u}, + {0x3Eu, 0x02u}, + {0x58u, 0x80u}, + {0x59u, 0x20u}, {0x5Cu, 0x41u}, {0x5Du, 0x04u}, {0x5Eu, 0x10u}, - {0x60u, 0x02u}, - {0x61u, 0x30u}, - {0x62u, 0x40u}, + {0x61u, 0x70u}, {0x65u, 0x80u}, - {0x6Fu, 0x03u}, - {0x80u, 0x08u}, - {0x81u, 0x01u}, + {0x6Du, 0x80u}, + {0x81u, 0x20u}, + {0x88u, 0x04u}, {0x8Au, 0x0Au}, + {0x8Bu, 0x01u}, {0x8Eu, 0x40u}, - {0x90u, 0x04u}, - {0x91u, 0x01u}, - {0x97u, 0x80u}, - {0x98u, 0x09u}, - {0x9Au, 0x30u}, - {0x9Du, 0x10u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x26u}, - {0xA0u, 0x20u}, + {0x8Fu, 0x0Cu}, + {0x90u, 0x80u}, + {0x92u, 0x02u}, + {0x97u, 0x84u}, + {0x98u, 0x19u}, + {0x9Au, 0x20u}, + {0x9Cu, 0x04u}, + {0x9Du, 0x50u}, + {0x9Eu, 0x80u}, + {0x9Fu, 0x02u}, {0xA1u, 0x80u}, {0xA2u, 0x01u}, - {0xA5u, 0x08u}, + {0xA5u, 0x40u}, {0xA6u, 0x08u}, - {0xA7u, 0x22u}, + {0xA7u, 0x20u}, {0xA8u, 0x10u}, {0xADu, 0xB0u}, {0xAEu, 0x04u}, {0xAFu, 0x10u}, - {0xB1u, 0x40u}, - {0xB2u, 0x10u}, - {0xB6u, 0x20u}, - {0xB7u, 0x14u}, - {0xC0u, 0x64u}, - {0xC2u, 0x7Fu}, - {0xC4u, 0xF0u}, - {0xCAu, 0x60u}, - {0xCCu, 0xFEu}, + {0xB0u, 0x10u}, + {0xB1u, 0x50u}, + {0xB3u, 0x40u}, + {0xB7u, 0x10u}, + {0xC0u, 0xFCu}, + {0xC2u, 0xD7u}, + {0xC4u, 0xA0u}, + {0xCAu, 0xE0u}, + {0xCCu, 0xEEu}, {0xCEu, 0xF9u}, {0xD6u, 0xFCu}, {0xD8u, 0x1Cu}, - {0xE0u, 0x10u}, - {0xE2u, 0x20u}, - {0xE4u, 0x82u}, - {0xE6u, 0x60u}, - {0xE8u, 0x04u}, - {0xEAu, 0x58u}, - {0xECu, 0x60u}, - {0x03u, 0x24u}, - {0x04u, 0xFFu}, + {0xE0u, 0x90u}, + {0xE2u, 0x22u}, + {0xE4u, 0x8Au}, + {0xE6u, 0x61u}, + {0xE8u, 0xA4u}, + {0xEAu, 0x48u}, + {0xECu, 0x40u}, + {0xEEu, 0x20u}, + {0x00u, 0xFFu}, + {0x01u, 0x24u}, + {0x03u, 0x09u}, {0x07u, 0x20u}, {0x08u, 0x33u}, - {0x09u, 0x40u}, + {0x09u, 0x24u}, {0x0Au, 0xCCu}, - {0x0Bu, 0x80u}, - {0x0Du, 0x24u}, - {0x0Fu, 0x09u}, - {0x10u, 0x0Fu}, + {0x0Bu, 0x12u}, + {0x0Cu, 0x55u}, + {0x0Du, 0x40u}, + {0x0Eu, 0xAAu}, + {0x0Fu, 0x80u}, {0x11u, 0x40u}, - {0x12u, 0xF0u}, + {0x12u, 0xFFu}, {0x13u, 0x18u}, - {0x16u, 0xFFu}, + {0x14u, 0x0Fu}, + {0x16u, 0xF0u}, {0x17u, 0x04u}, - {0x18u, 0xFFu}, + {0x1Au, 0xFFu}, {0x1Bu, 0x03u}, {0x1Cu, 0x96u}, {0x1Eu, 0x69u}, - {0x20u, 0x55u}, - {0x22u, 0xAAu}, - {0x25u, 0x24u}, {0x26u, 0xFFu}, - {0x27u, 0x12u}, + {0x27u, 0x24u}, + {0x28u, 0xFFu}, {0x29u, 0x80u}, - {0x2Eu, 0xFFu}, - {0x30u, 0xFFu}, {0x31u, 0x38u}, + {0x32u, 0xFFu}, {0x33u, 0xC0u}, {0x35u, 0x07u}, - {0x3Au, 0x02u}, + {0x3Au, 0x08u}, {0x3Fu, 0x04u}, {0x56u, 0x08u}, {0x58u, 0x04u}, @@ -1344,81 +1345,87 @@ void cyfitter_cfg(void) {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, + {0x81u, 0x11u}, + {0x83u, 0x22u}, {0x84u, 0x48u}, - {0x85u, 0x21u}, {0x86u, 0x84u}, - {0x87u, 0x12u}, {0x88u, 0x44u}, {0x8Au, 0x88u}, {0x8Bu, 0xFFu}, - {0x8Cu, 0x33u}, {0x8Du, 0x0Fu}, - {0x8Eu, 0xCCu}, {0x8Fu, 0xF0u}, {0x90u, 0x0Fu}, - {0x91u, 0x11u}, {0x92u, 0xF0u}, - {0x93u, 0x22u}, - {0x95u, 0x44u}, + {0x95u, 0x21u}, {0x96u, 0xFFu}, - {0x97u, 0x88u}, + {0x97u, 0x12u}, {0x9Au, 0xFFu}, {0x9Bu, 0xFFu}, + {0x9Cu, 0x33u}, {0x9Du, 0xFFu}, + {0x9Eu, 0xCCu}, + {0xA1u, 0x33u}, {0xA2u, 0xFFu}, + {0xA3u, 0xCCu}, {0xA4u, 0x12u}, {0xA5u, 0x84u}, {0xA6u, 0x21u}, {0xA7u, 0x48u}, + {0xA9u, 0x44u}, + {0xABu, 0x88u}, {0xACu, 0x11u}, - {0xADu, 0x33u}, {0xAEu, 0x22u}, - {0xAFu, 0xCCu}, {0xB0u, 0xFFu}, {0xB3u, 0xFFu}, - {0xB9u, 0x20u}, + {0xB9u, 0x02u}, {0xBEu, 0x01u}, - {0xBFu, 0x14u}, + {0xBFu, 0x05u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x14u}, + {0x01u, 0x04u}, {0x02u, 0x08u}, - {0x03u, 0x22u}, - {0x05u, 0x10u}, - {0x07u, 0x20u}, - {0x08u, 0x02u}, + {0x03u, 0x20u}, + {0x05u, 0x50u}, + {0x06u, 0x80u}, + {0x08u, 0x42u}, + {0x09u, 0x40u}, {0x0Au, 0x24u}, {0x0Bu, 0xA0u}, - {0x0Cu, 0x20u}, - {0x0Du, 0x0Au}, - {0x0Fu, 0x02u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x20u}, + {0x0Fu, 0x06u}, {0x10u, 0x80u}, {0x11u, 0x08u}, - {0x12u, 0x02u}, - {0x13u, 0x06u}, - {0x16u, 0x52u}, + {0x12u, 0x03u}, + {0x13u, 0x02u}, + {0x14u, 0x10u}, + {0x15u, 0x10u}, {0x1Au, 0x40u}, - {0x1Du, 0x02u}, + {0x1Eu, 0x20u}, + {0x1Fu, 0x04u}, {0x20u, 0x20u}, - {0x21u, 0x20u}, - {0x24u, 0x24u}, + {0x22u, 0x01u}, + {0x24u, 0x20u}, {0x26u, 0x21u}, - {0x2Bu, 0x22u}, - {0x2Cu, 0x20u}, + {0x28u, 0x44u}, + {0x2Bu, 0x20u}, + {0x2Cu, 0x10u}, {0x2Fu, 0x08u}, {0x30u, 0x80u}, - {0x32u, 0x1Au}, + {0x31u, 0x08u}, + {0x32u, 0x10u}, {0x36u, 0x21u}, {0x37u, 0x08u}, {0x39u, 0x20u}, - {0x3Bu, 0x84u}, - {0x3Du, 0x81u}, - {0x3Eu, 0x0Au}, - {0x3Fu, 0x10u}, + {0x3Au, 0x01u}, + {0x3Bu, 0x80u}, + {0x3Du, 0x90u}, + {0x3Eu, 0x08u}, + {0x3Fu, 0x01u}, {0x5Bu, 0x50u}, {0x5Cu, 0x20u}, {0x5Du, 0x80u}, @@ -1427,43 +1434,41 @@ void cyfitter_cfg(void) {0x64u, 0x01u}, {0x66u, 0x20u}, {0x67u, 0x02u}, - {0x81u, 0x20u}, {0x83u, 0x09u}, - {0x84u, 0x20u}, - {0x87u, 0x12u}, - {0x89u, 0x02u}, + {0x86u, 0x20u}, {0x8Au, 0x20u}, - {0x8Bu, 0x02u}, - {0x91u, 0x01u}, + {0x8Bu, 0x06u}, + {0x8Cu, 0x40u}, + {0x8Du, 0x02u}, + {0x8Fu, 0x01u}, {0x95u, 0x34u}, {0x96u, 0x44u}, - {0x97u, 0x10u}, + {0x97u, 0x41u}, {0x98u, 0x20u}, {0x9Au, 0x08u}, {0x9Bu, 0x48u}, - {0x9Cu, 0x02u}, + {0x9Cu, 0x46u}, {0x9Du, 0x20u}, {0x9Fu, 0x02u}, - {0xA1u, 0x04u}, + {0xA1u, 0x0Cu}, {0xA2u, 0x02u}, {0xA3u, 0x01u}, {0xA4u, 0x10u}, - {0xA5u, 0x40u}, {0xA8u, 0x20u}, - {0xADu, 0x01u}, {0xAEu, 0x24u}, - {0xAFu, 0x04u}, {0xB2u, 0x11u}, {0xB4u, 0x20u}, - {0xC0u, 0x67u}, - {0xC2u, 0xFEu}, - {0xC4u, 0xBDu}, - {0xCAu, 0x6Au}, - {0xCCu, 0xEFu}, - {0xCEu, 0xFEu}, + {0xC0u, 0xD6u}, + {0xC2u, 0xFFu}, + {0xC4u, 0x6Du}, + {0xCAu, 0x67u}, + {0xCCu, 0xEEu}, + {0xCEu, 0xFDu}, {0xD6u, 0x3Cu}, {0xD8u, 0x3Cu}, - {0xE6u, 0xA8u}, + {0xE2u, 0x80u}, + {0xE4u, 0x10u}, + {0xE6u, 0xA0u}, {0xE8u, 0x80u}, {0xEAu, 0x20u}, {0xECu, 0x88u}, @@ -1476,19 +1481,19 @@ void cyfitter_cfg(void) {0x08u, 0x01u}, {0x0Bu, 0xFFu}, {0x0Cu, 0x01u}, + {0x0Du, 0x11u}, + {0x0Fu, 0x22u}, {0x10u, 0x01u}, {0x13u, 0xFFu}, {0x14u, 0x02u}, {0x15u, 0x21u}, {0x17u, 0x12u}, {0x18u, 0x01u}, - {0x19u, 0x33u}, - {0x1Bu, 0xCCu}, - {0x21u, 0x11u}, - {0x23u, 0x22u}, - {0x24u, 0x0Au}, + {0x20u, 0x0Au}, + {0x21u, 0x33u}, + {0x22u, 0x14u}, + {0x23u, 0xCCu}, {0x25u, 0xFFu}, - {0x26u, 0x14u}, {0x28u, 0x10u}, {0x29u, 0x44u}, {0x2Bu, 0x88u}, @@ -1505,30 +1510,30 @@ void cyfitter_cfg(void) {0x5Bu, 0x04u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x40u}, - {0x83u, 0x24u}, + {0x81u, 0x64u}, + {0x83u, 0x09u}, {0x84u, 0x12u}, - {0x85u, 0x64u}, {0x86u, 0x21u}, - {0x87u, 0x12u}, {0x88u, 0xFFu}, {0x8Cu, 0xFFu}, - {0x8Du, 0x64u}, - {0x8Fu, 0x09u}, + {0x8Du, 0x40u}, + {0x8Fu, 0x24u}, {0x93u, 0x18u}, - {0x94u, 0x33u}, - {0x96u, 0xCCu}, + {0x94u, 0x44u}, + {0x96u, 0x88u}, {0x97u, 0x03u}, {0x9Au, 0xFFu}, {0x9Bu, 0x04u}, {0x9Cu, 0x11u}, {0x9Eu, 0x22u}, + {0xA0u, 0x33u}, + {0xA2u, 0xCCu}, {0xA3u, 0x40u}, {0xA4u, 0x48u}, {0xA6u, 0x84u}, {0xA7u, 0x20u}, - {0xA8u, 0x44u}, - {0xAAu, 0x88u}, + {0xA9u, 0x64u}, + {0xABu, 0x12u}, {0xACu, 0x0Fu}, {0xAEu, 0xF0u}, {0xB0u, 0xFFu}, @@ -1550,40 +1555,36 @@ void cyfitter_cfg(void) {0x07u, 0x13u}, {0x09u, 0x24u}, {0x0Au, 0x40u}, + {0x0Cu, 0x04u}, + {0x0Du, 0x40u}, {0x0Eu, 0x06u}, - {0x0Fu, 0x10u}, - {0x10u, 0x10u}, - {0x11u, 0x10u}, + {0x10u, 0x44u}, {0x12u, 0x02u}, - {0x14u, 0x0Au}, - {0x15u, 0x14u}, + {0x14u, 0x42u}, + {0x15u, 0x04u}, {0x16u, 0x01u}, {0x1Au, 0x18u}, {0x1Bu, 0x80u}, {0x1Fu, 0x02u}, {0x21u, 0x20u}, - {0x25u, 0x04u}, + {0x25u, 0x0Cu}, {0x26u, 0x8Bu}, {0x27u, 0x10u}, - {0x28u, 0x08u}, - {0x29u, 0x01u}, + {0x28u, 0x44u}, {0x2Au, 0x04u}, {0x2Cu, 0xA0u}, - {0x30u, 0x10u}, + {0x2Du, 0x10u}, {0x32u, 0x08u}, {0x33u, 0x01u}, - {0x35u, 0x01u}, {0x36u, 0x2Au}, - {0x39u, 0x24u}, + {0x39u, 0xA4u}, {0x3Au, 0x01u}, - {0x3Du, 0x81u}, - {0x3Fu, 0x04u}, + {0x3Fu, 0x41u}, {0x59u, 0x80u}, {0x5Cu, 0x04u}, {0x5Eu, 0xA1u}, {0x63u, 0x02u}, - {0x64u, 0x11u}, - {0x67u, 0x10u}, + {0x64u, 0x01u}, {0x78u, 0x01u}, {0x7Au, 0x80u}, {0x81u, 0x80u}, @@ -1595,17 +1596,17 @@ void cyfitter_cfg(void) {0x8Fu, 0x40u}, {0xC0u, 0xE7u}, {0xC2u, 0xEEu}, - {0xC4u, 0xE7u}, - {0xCAu, 0xC7u}, - {0xCCu, 0xE7u}, - {0xCEu, 0xD7u}, + {0xC4u, 0xBBu}, + {0xCAu, 0xE7u}, + {0xCCu, 0xE3u}, + {0xCEu, 0x9Fu}, {0xD6u, 0xF8u}, {0xD8u, 0x18u}, - {0xE0u, 0x50u}, + {0xE0u, 0x10u}, {0xE2u, 0x04u}, - {0xE4u, 0x48u}, - {0x80u, 0x02u}, - {0x82u, 0x05u}, + {0xE4u, 0x4Cu}, + {0x8Cu, 0x02u}, + {0x8Eu, 0x05u}, {0x94u, 0x02u}, {0x96u, 0x01u}, {0x98u, 0x01u}, @@ -1615,21 +1616,22 @@ void cyfitter_cfg(void) {0xA5u, 0x01u}, {0xACu, 0x02u}, {0xAEu, 0x09u}, + {0xB1u, 0x01u}, {0xB2u, 0x08u}, {0xB4u, 0x03u}, {0xB6u, 0x04u}, - {0xB7u, 0x01u}, {0xBAu, 0x20u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDCu, 0x91u}, {0xDFu, 0x01u}, - {0x00u, 0x04u}, + {0x00u, 0x08u}, {0x01u, 0x01u}, - {0x03u, 0x0Au}, - {0x05u, 0x02u}, - {0x09u, 0x15u}, - {0x0Eu, 0x26u}, + {0x03u, 0x06u}, + {0x04u, 0x80u}, + {0x09u, 0x06u}, + {0x0Au, 0x08u}, + {0x0Eu, 0x2Au}, {0x10u, 0x28u}, {0x11u, 0x40u}, {0x13u, 0x01u}, @@ -1638,91 +1640,94 @@ void cyfitter_cfg(void) {0x16u, 0x40u}, {0x19u, 0x08u}, {0x1Cu, 0x20u}, - {0x1Eu, 0x26u}, + {0x1Eu, 0x2Au}, {0x1Fu, 0x30u}, - {0x20u, 0x14u}, - {0x21u, 0x01u}, - {0x22u, 0x40u}, - {0x27u, 0x01u}, - {0x29u, 0x48u}, - {0x2Bu, 0x48u}, + {0x21u, 0x05u}, + {0x22u, 0x54u}, + {0x25u, 0x01u}, + {0x29u, 0x58u}, + {0x2Au, 0x01u}, {0x2Fu, 0x20u}, - {0x30u, 0x20u}, - {0x33u, 0x46u}, - {0x38u, 0x14u}, - {0x39u, 0x41u}, - {0x40u, 0x40u}, - {0x41u, 0x60u}, - {0x43u, 0x08u}, - {0x49u, 0x04u}, + {0x31u, 0x82u}, + {0x32u, 0x10u}, + {0x33u, 0x04u}, + {0x38u, 0x20u}, + {0x39u, 0x49u}, + {0x41u, 0x42u}, + {0x43u, 0x04u}, + {0x48u, 0x04u}, + {0x49u, 0x06u}, {0x4Au, 0x02u}, - {0x4Bu, 0x02u}, - {0x51u, 0x02u}, - {0x52u, 0x14u}, + {0x50u, 0x01u}, + {0x52u, 0x91u}, {0x53u, 0x82u}, - {0x61u, 0x01u}, + {0x63u, 0x20u}, {0x68u, 0x28u}, - {0x69u, 0x41u}, + {0x69u, 0x45u}, + {0x6Bu, 0x40u}, {0x71u, 0x40u}, {0x73u, 0x01u}, - {0x87u, 0x11u}, + {0x81u, 0x01u}, + {0x87u, 0x10u}, + {0x89u, 0x84u}, {0x8Au, 0x02u}, - {0x90u, 0x40u}, + {0x90u, 0xA0u}, {0x91u, 0x80u}, + {0x94u, 0x02u}, {0x95u, 0x41u}, {0x96u, 0x80u}, - {0x97u, 0x02u}, {0x98u, 0x01u}, - {0x99u, 0x03u}, - {0x9Bu, 0x44u}, - {0x9Du, 0x44u}, - {0x9Eu, 0x54u}, - {0xA1u, 0x35u}, - {0xA3u, 0x48u}, + {0x99u, 0x10u}, + {0x9Bu, 0x04u}, + {0x9Du, 0x46u}, + {0x9Eu, 0x50u}, + {0x9Fu, 0x40u}, + {0xA0u, 0x04u}, + {0xA1u, 0x06u}, + {0xA3u, 0x10u}, {0xA4u, 0x38u}, - {0xA5u, 0x02u}, + {0xA6u, 0x80u}, {0xA7u, 0x80u}, - {0xA9u, 0x04u}, - {0xABu, 0x40u}, - {0xADu, 0x10u}, - {0xB7u, 0x40u}, - {0xC0u, 0x1Fu}, + {0xA8u, 0x20u}, + {0xAAu, 0x02u}, + {0xAFu, 0x10u}, + {0xC0u, 0x8Fu}, {0xC2u, 0xEEu}, {0xC4u, 0x8Fu}, {0xCAu, 0x4Fu}, {0xCCu, 0x0Fu}, {0xCEu, 0x0Fu}, - {0xD0u, 0x0Fu}, - {0xD2u, 0x08u}, - {0xD8u, 0x01u}, + {0xD0u, 0x0Bu}, + {0xD2u, 0x0Cu}, + {0xD8u, 0x02u}, {0xE4u, 0x22u}, - {0x01u, 0x71u}, - {0x03u, 0x82u}, - {0x05u, 0xA4u}, - {0x07u, 0x40u}, - {0x09u, 0x91u}, - {0x0Bu, 0x4Eu}, + {0x01u, 0x6Cu}, + {0x05u, 0x91u}, + {0x07u, 0x4Eu}, {0x0Cu, 0x01u}, {0x0Du, 0x2Cu}, {0x0Fu, 0x40u}, {0x10u, 0x02u}, + {0x11u, 0x71u}, + {0x13u, 0x82u}, {0x15u, 0xC0u}, {0x17u, 0x2Fu}, + {0x19u, 0xA4u}, + {0x1Bu, 0x40u}, {0x1Du, 0x6Cu}, - {0x21u, 0x6Cu}, + {0x21u, 0x08u}, + {0x23u, 0x10u}, {0x25u, 0x64u}, {0x27u, 0x08u}, {0x29u, 0x40u}, {0x2Bu, 0x2Cu}, - {0x2Du, 0x08u}, - {0x2Fu, 0x10u}, + {0x30u, 0x01u}, {0x31u, 0x0Fu}, - {0x32u, 0x02u}, {0x33u, 0xC0u}, - {0x34u, 0x01u}, + {0x34u, 0x02u}, {0x35u, 0x31u}, {0x3Bu, 0x38u}, - {0x3Eu, 0x04u}, + {0x3Eu, 0x10u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, @@ -1730,9 +1735,12 @@ void cyfitter_cfg(void) {0x5Cu, 0x09u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, + {0x80u, 0x90u}, {0x81u, 0x11u}, + {0x82u, 0x49u}, + {0x84u, 0x02u}, {0x85u, 0xC4u}, - {0x86u, 0x0Cu}, + {0x86u, 0x91u}, {0x87u, 0x02u}, {0x88u, 0x01u}, {0x8Au, 0x02u}, @@ -1741,20 +1749,17 @@ void cyfitter_cfg(void) {0x8Fu, 0x11u}, {0x91u, 0x0Cu}, {0x92u, 0x60u}, - {0x94u, 0x02u}, {0x95u, 0x11u}, - {0x96u, 0x91u}, + {0x96u, 0x0Cu}, {0x98u, 0x92u}, {0x99u, 0x11u}, {0x9Au, 0x25u}, - {0x9Du, 0x02u}, {0x9Eu, 0x10u}, - {0x9Fu, 0x64u}, {0xA2u, 0x80u}, {0xA3u, 0x01u}, - {0xA8u, 0x90u}, + {0xA5u, 0x02u}, + {0xA7u, 0x64u}, {0xA9u, 0x02u}, - {0xAAu, 0x49u}, {0xABu, 0xA8u}, {0xADu, 0x11u}, {0xAEu, 0x01u}, @@ -1775,48 +1780,45 @@ void cyfitter_cfg(void) {0xDBu, 0x04u}, {0xDCu, 0x01u}, {0xDFu, 0x01u}, - {0x01u, 0x28u}, + {0x00u, 0x02u}, + {0x01u, 0x24u}, {0x02u, 0x02u}, - {0x03u, 0x10u}, {0x07u, 0x01u}, {0x08u, 0x40u}, {0x09u, 0x08u}, - {0x0Au, 0x44u}, - {0x0Bu, 0x80u}, + {0x0Au, 0x50u}, + {0x0Bu, 0x88u}, {0x0Cu, 0x02u}, {0x10u, 0x80u}, {0x12u, 0x01u}, - {0x13u, 0x20u}, - {0x19u, 0x28u}, - {0x1Au, 0x40u}, - {0x1Cu, 0x08u}, - {0x1Eu, 0x20u}, + {0x19u, 0x20u}, + {0x1Au, 0x50u}, + {0x1Eu, 0x80u}, + {0x1Fu, 0x10u}, {0x21u, 0x51u}, {0x22u, 0x09u}, {0x23u, 0x02u}, - {0x24u, 0x64u}, - {0x25u, 0x35u}, - {0x27u, 0x44u}, - {0x28u, 0x10u}, - {0x29u, 0x40u}, + {0x24u, 0x24u}, + {0x25u, 0x06u}, + {0x26u, 0x01u}, + {0x27u, 0x14u}, + {0x29u, 0x50u}, {0x2Au, 0x04u}, - {0x2Bu, 0x88u}, + {0x2Bu, 0x80u}, {0x2Cu, 0x28u}, - {0x2Du, 0x01u}, - {0x2Fu, 0x01u}, + {0x2Du, 0x02u}, + {0x2Eu, 0x02u}, {0x30u, 0x28u}, {0x32u, 0x01u}, - {0x33u, 0x40u}, {0x35u, 0x40u}, - {0x37u, 0x04u}, + {0x36u, 0x01u}, + {0x37u, 0x14u}, {0x38u, 0x04u}, {0x39u, 0x61u}, - {0x3Au, 0x82u}, - {0x3Du, 0x4Au}, - {0x3Eu, 0x20u}, - {0x42u, 0x20u}, - {0x43u, 0x08u}, - {0x58u, 0x10u}, + {0x3Au, 0x80u}, + {0x3Cu, 0x08u}, + {0x3Du, 0x41u}, + {0x58u, 0x20u}, {0x59u, 0x04u}, {0x5Au, 0x80u}, {0x5Bu, 0x02u}, @@ -1824,150 +1826,156 @@ void cyfitter_cfg(void) {0x62u, 0x40u}, {0x63u, 0x40u}, {0x64u, 0x01u}, - {0x81u, 0x01u}, {0x83u, 0x04u}, {0x87u, 0x40u}, + {0x89u, 0x10u}, + {0x8Au, 0x40u}, {0x8Cu, 0x80u}, - {0x92u, 0x04u}, - {0x94u, 0x20u}, + {0x8Du, 0x02u}, + {0x8Eu, 0x04u}, + {0x90u, 0x80u}, + {0x91u, 0x04u}, + {0x93u, 0x08u}, + {0x94u, 0x02u}, {0x95u, 0x02u}, {0x97u, 0x80u}, {0x98u, 0x40u}, - {0x99u, 0x02u}, + {0x99u, 0x10u}, {0x9Au, 0x01u}, - {0x9Bu, 0x21u}, - {0x9Du, 0x60u}, - {0x9Eu, 0x96u}, + {0x9Bu, 0x01u}, + {0x9Du, 0x62u}, + {0x9Eu, 0x90u}, {0x9Fu, 0x54u}, - {0xA0u, 0x82u}, - {0xA1u, 0x08u}, + {0xA0u, 0x87u}, {0xA2u, 0x02u}, - {0xA3u, 0x08u}, - {0xA4u, 0x3Cu}, - {0xA5u, 0x02u}, - {0xA6u, 0x18u}, - {0xA7u, 0x80u}, + {0xA3u, 0x10u}, + {0xA4u, 0x38u}, + {0xA5u, 0x0Au}, + {0xA6u, 0x88u}, + {0xAAu, 0x40u}, {0xB3u, 0x11u}, + {0xB4u, 0x10u}, {0xB6u, 0x10u}, - {0xC0u, 0x87u}, + {0xC0u, 0x8Fu}, {0xC2u, 0x1Fu}, - {0xC4u, 0x0Bu}, - {0xCAu, 0xFDu}, - {0xCCu, 0x5Fu}, - {0xCEu, 0xFFu}, + {0xC4u, 0x09u}, + {0xCAu, 0xEFu}, + {0xCCu, 0xF7u}, + {0xCEu, 0xDFu}, {0xD6u, 0x1Fu}, {0xD8u, 0x19u}, {0xE0u, 0x11u}, - {0xE2u, 0x04u}, + {0xE2u, 0x20u}, + {0xE6u, 0x20u}, + {0xE8u, 0x04u}, {0xEAu, 0x20u}, - {0x80u, 0x10u}, {0x81u, 0x10u}, - {0x90u, 0x20u}, + {0x8Cu, 0x20u}, {0x95u, 0x04u}, - {0x9Eu, 0x08u}, + {0xA4u, 0x20u}, {0xA5u, 0x10u}, - {0xB1u, 0x08u}, - {0xB7u, 0x20u}, + {0xA9u, 0x04u}, + {0xB3u, 0x84u}, + {0xB4u, 0x81u}, + {0xB7u, 0xA0u}, + {0xE4u, 0x10u}, {0xE8u, 0x40u}, - {0xECu, 0x20u}, + {0xECu, 0x60u}, {0x85u, 0x04u}, {0x95u, 0x04u}, - {0xB6u, 0x08u}, - {0xE8u, 0x10u}, {0x07u, 0x08u}, {0x0Du, 0x80u}, {0x0Eu, 0x40u}, - {0x13u, 0x20u}, + {0x11u, 0x08u}, + {0x12u, 0x02u}, {0x16u, 0x80u}, - {0x17u, 0x40u}, - {0x32u, 0x01u}, - {0x34u, 0x01u}, - {0x36u, 0x80u}, + {0x17u, 0x20u}, + {0x30u, 0x10u}, + {0x33u, 0x02u}, + {0x36u, 0x21u}, {0x39u, 0x02u}, {0x3Au, 0x80u}, - {0x3Cu, 0x08u}, {0x3Du, 0x40u}, + {0x3Fu, 0x08u}, {0x42u, 0x08u}, - {0x50u, 0x20u}, - {0x81u, 0x40u}, + {0x52u, 0x10u}, + {0x6Du, 0x08u}, + {0x6Fu, 0x02u}, + {0x77u, 0x10u}, + {0x7Eu, 0x02u}, {0x83u, 0x08u}, {0x85u, 0x01u}, {0x8Du, 0x80u}, {0xC0u, 0x80u}, {0xC2u, 0xA0u}, - {0xC4u, 0xE0u}, - {0xCCu, 0xE0u}, + {0xC4u, 0xF0u}, + {0xCCu, 0xF0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, {0xD4u, 0x20u}, {0xE0u, 0x20u}, - {0xE6u, 0x60u}, + {0xE6u, 0x40u}, {0x00u, 0x10u}, {0x0Au, 0x01u}, - {0x31u, 0x08u}, + {0x30u, 0x08u}, {0x33u, 0x10u}, - {0x37u, 0x48u}, - {0x39u, 0x10u}, + {0x34u, 0x01u}, + {0x37u, 0x20u}, + {0x3Au, 0x80u}, {0x58u, 0x40u}, - {0x5Du, 0x02u}, - {0x6Bu, 0x30u}, - {0x81u, 0x01u}, - {0x85u, 0x10u}, + {0x63u, 0x40u}, + {0x84u, 0x40u}, + {0x88u, 0x08u}, {0x92u, 0x40u}, - {0x96u, 0x02u}, - {0x9Bu, 0x60u}, - {0x9Cu, 0x01u}, - {0x9Eu, 0x08u}, - {0xA4u, 0x24u}, - {0xA6u, 0x80u}, + {0x9Bu, 0x30u}, + {0x9Cu, 0x10u}, + {0x9Eu, 0x18u}, + {0xA6u, 0x21u}, + {0xA7u, 0x04u}, + {0xB5u, 0x40u}, {0xC0u, 0x40u}, {0xC2u, 0x40u}, {0xCCu, 0xF0u}, {0xCEu, 0x10u}, {0xD4u, 0x80u}, - {0xD6u, 0x80u}, - {0xE2u, 0x20u}, + {0xD8u, 0x40u}, {0xE6u, 0x10u}, - {0x12u, 0x80u}, + {0x10u, 0x10u}, {0x30u, 0x80u}, - {0x52u, 0x10u}, - {0x59u, 0x01u}, - {0x88u, 0x20u}, + {0x53u, 0x04u}, + {0x5Au, 0x02u}, + {0x86u, 0x80u}, + {0x8Au, 0x10u}, {0x90u, 0x10u}, - {0x96u, 0x02u}, - {0x99u, 0x01u}, - {0x9Cu, 0x01u}, - {0x9Du, 0x02u}, - {0x9Eu, 0x08u}, - {0x9Fu, 0x08u}, - {0xA4u, 0x24u}, - {0xA5u, 0x08u}, - {0xA6u, 0x80u}, + {0x93u, 0x08u}, + {0x97u, 0x40u}, + {0x9Cu, 0x11u}, + {0x9Eu, 0x98u}, + {0xA6u, 0x21u}, + {0xA7u, 0x04u}, {0xAEu, 0x01u}, - {0xB0u, 0x40u}, + {0xAFu, 0x04u}, {0xB6u, 0x40u}, {0xC4u, 0x10u}, {0xCCu, 0x10u}, {0xD4u, 0x20u}, {0xD6u, 0x40u}, + {0xE2u, 0x40u}, {0xE8u, 0x10u}, + {0xEEu, 0x10u}, {0x84u, 0x80u}, - {0x85u, 0x0Au}, - {0x86u, 0x01u}, - {0x88u, 0x04u}, - {0x8Fu, 0x08u}, + {0x8Fu, 0x04u}, {0x90u, 0x10u}, - {0x96u, 0x02u}, - {0x9Cu, 0x01u}, - {0x9Du, 0x02u}, + {0x97u, 0x40u}, {0x9Eu, 0x08u}, - {0x9Fu, 0x08u}, - {0xA4u, 0x84u}, - {0xA5u, 0x08u}, - {0xAEu, 0x10u}, - {0xE2u, 0x50u}, - {0xE6u, 0x50u}, + {0xA4u, 0x80u}, + {0xA6u, 0x21u}, + {0xA7u, 0x04u}, + {0xACu, 0x01u}, + {0xAEu, 0x01u}, + {0xE2u, 0x10u}, {0xEAu, 0x40u}, + {0xEEu, 0x40u}, {0x04u, 0x10u}, {0x05u, 0x01u}, {0x08u, 0x04u}, @@ -1977,98 +1985,101 @@ void cyfitter_cfg(void) {0x63u, 0x40u}, {0x67u, 0x08u}, {0x70u, 0x08u}, - {0x81u, 0x01u}, + {0x81u, 0x03u}, {0x84u, 0x40u}, - {0x8Cu, 0x28u}, + {0x8Cu, 0x08u}, {0xC0u, 0x05u}, {0xC2u, 0x0Au}, {0xC4u, 0x08u}, {0xD4u, 0x01u}, {0xD8u, 0x03u}, {0xDCu, 0x01u}, - {0xE0u, 0x02u}, {0xE4u, 0x08u}, - {0x01u, 0x42u}, + {0x01u, 0x40u}, + {0x02u, 0x20u}, {0x08u, 0x80u}, - {0x0Au, 0x80u}, + {0x09u, 0x01u}, {0x56u, 0x80u}, {0x5Au, 0x40u}, - {0x5Fu, 0x02u}, - {0x60u, 0x20u}, - {0x87u, 0x04u}, + {0x5Du, 0x02u}, + {0x63u, 0x02u}, + {0x88u, 0x01u}, {0x8Bu, 0x40u}, {0x90u, 0x10u}, - {0x96u, 0x80u}, {0x97u, 0x40u}, - {0x98u, 0x24u}, - {0xAAu, 0x40u}, + {0x98u, 0x04u}, + {0x99u, 0x02u}, + {0xA5u, 0x01u}, + {0xA9u, 0x01u}, {0xAFu, 0x04u}, {0xB0u, 0x10u}, {0xB7u, 0x01u}, {0xC0u, 0x0Au}, {0xC2u, 0x0Au}, {0xD4u, 0x03u}, - {0xD6u, 0x01u}, - {0xD8u, 0x02u}, + {0xD6u, 0x03u}, {0xE0u, 0x04u}, + {0xE6u, 0x04u}, {0xEAu, 0x06u}, {0x57u, 0x08u}, - {0x87u, 0x08u}, + {0x82u, 0x20u}, + {0x87u, 0x0Du}, {0x88u, 0x80u}, - {0x8Fu, 0x02u}, + {0x8Eu, 0x80u}, {0x90u, 0x10u}, - {0x97u, 0x08u}, {0x98u, 0x80u}, - {0x99u, 0x02u}, - {0x9Fu, 0x02u}, + {0x9Cu, 0x01u}, + {0x9Eu, 0x80u}, + {0xA2u, 0x20u}, + {0xA7u, 0x01u}, {0xAAu, 0x40u}, {0xACu, 0x04u}, {0xB5u, 0x40u}, - {0xB6u, 0x80u}, {0xD4u, 0x02u}, - {0xE0u, 0x08u}, {0xE2u, 0x04u}, + {0xE4u, 0x08u}, {0xEAu, 0x02u}, - {0xECu, 0x08u}, - {0x09u, 0x02u}, - {0x0Bu, 0x08u}, - {0x0Eu, 0x41u}, - {0x85u, 0x02u}, + {0x08u, 0x01u}, + {0x0Bu, 0x04u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x01u}, {0x86u, 0x01u}, - {0x8Eu, 0x40u}, - {0x97u, 0x08u}, + {0x97u, 0x04u}, + {0x9Cu, 0x01u}, + {0xA5u, 0x02u}, + {0xADu, 0x02u}, {0xB4u, 0x10u}, - {0xB5u, 0x02u}, {0xC2u, 0x0Fu}, - {0xE6u, 0x02u}, - {0xEAu, 0x0Au}, + {0xEAu, 0x08u}, {0x86u, 0x08u}, + {0x8Au, 0x22u}, {0x8Cu, 0x10u}, {0x90u, 0x10u}, + {0x97u, 0x40u}, {0x98u, 0x02u}, - {0x9Cu, 0x01u}, {0x9Eu, 0x08u}, + {0xA6u, 0x21u}, {0xB0u, 0x02u}, {0xE6u, 0x40u}, {0x00u, 0x80u}, {0x52u, 0x02u}, {0x5Cu, 0x02u}, - {0x84u, 0x01u}, + {0x82u, 0x01u}, {0x88u, 0x40u}, {0x98u, 0x02u}, - {0x9Cu, 0x01u}, {0xA2u, 0x02u}, - {0xAEu, 0x02u}, + {0xA6u, 0x01u}, + {0xAFu, 0x40u}, {0xC0u, 0x40u}, {0xD4u, 0x80u}, {0xD6u, 0x80u}, - {0xE2u, 0x40u}, - {0xEAu, 0x40u}, + {0xE6u, 0x80u}, + {0xEEu, 0x40u}, {0x10u, 0x03u}, {0x11u, 0x01u}, {0x1Au, 0x03u}, {0x1Bu, 0x01u}, - {0x00u, 0xFDu}, + {0x00u, 0xFFu}, {0x01u, 0xBFu}, {0x02u, 0x2Au}, {0x10u, 0x95u}, @@ -2088,7 +2099,7 @@ void cyfitter_cfg(void) uint16 size; } CYPACKED_ATTR cfg_memcpy_t; - static const cfg_memset_t CYCODE cfg_memset_list [] = { + static const cfg_memset_t CYCODE cfg_memset_list[] = { /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT5_DR), 16u}, @@ -2101,12 +2112,12 @@ void cyfitter_cfg(void) /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { - 0xC0u, 0x01u, 0x02u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x00u, 0x40u, 0xFFu, 0x00u, 0x00u, 0x01u, 0x9Fu, 0x00u, - 0x1Fu, 0x10u, 0x20u, 0x00u, 0x80u, 0xA2u, 0x00u, 0x08u, 0x7Fu, 0x01u, 0x80u, 0x00u, 0x00u, 0x87u, 0x00u, 0x18u, - 0xC0u, 0x01u, 0x01u, 0x00u, 0xC0u, 0x40u, 0x04u, 0x00u, 0xC0u, 0x88u, 0x08u, 0x21u, 0x90u, 0x01u, 0x40u, 0x00u, - 0x00u, 0x80u, 0xFFu, 0x3Fu, 0x00u, 0x40u, 0x00u, 0x08u, 0x00u, 0x28u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x45u, - 0x32u, 0x04u, 0x10u, 0x00u, 0x05u, 0xCEu, 0xFDu, 0xBCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, + 0xC0u, 0x01u, 0x02u, 0x00u, 0x00u, 0x04u, 0xFFu, 0x00u, 0x7Fu, 0x01u, 0x80u, 0x00u, 0x00u, 0x01u, 0x9Fu, 0x00u, + 0x1Fu, 0x87u, 0x20u, 0x18u, 0x80u, 0xA2u, 0x00u, 0x08u, 0x00u, 0x40u, 0x60u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, + 0xC0u, 0x10u, 0x01u, 0x00u, 0xC0u, 0x40u, 0x04u, 0x00u, 0xC0u, 0x88u, 0x08u, 0x21u, 0x90u, 0x01u, 0x40u, 0x00u, + 0x00u, 0x80u, 0xFFu, 0x40u, 0x00u, 0x3Fu, 0x00u, 0x08u, 0x00u, 0x28u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x51u, + 0x63u, 0x04u, 0x10u, 0x00u, 0x05u, 0xCEu, 0xFDu, 0xB0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x28u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h index 17e8d5b..b0406f8 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfitter_cfg.h * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: -* This file provides basic startup and mux configration settings +* This file provides basic startup and mux configuration settings * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 876e1fb..b997c46 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -1,8 +1,52 @@ +/******************************************************************************* +* File Name: cyfittergnu.inc +* +* PSoC Creator 4.1 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + .ifndef INCLUDED_CYFITTERGNU_INC .set INCLUDED_CYFITTERGNU_INC, 1 .include "cydevicegnu.inc" .include "cydevicegnu_trm.inc" +/* Debug_Timer_Interrupt */ +.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set Debug_Timer_Interrupt__INTC_MASK, 0x01 +.set Debug_Timer_Interrupt__INTC_NUMBER, 0 +.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7 +.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* Debug_Timer_TimerHW */ +.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0 +.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1 +.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0 +.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1 +.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2 +.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0 +.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1 +.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0 +.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1 +.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3 +.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01 +.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3 +.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01 +.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0 +.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1 +.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0 + /* LED1 */ .set LED1__0__INTTYPE, CYREG_PICU12_INTTYPE0 .set LED1__0__MASK, 0x01 @@ -41,438 +85,86 @@ .set LED1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ .set LED1__SLW, CYREG_PRT12_SLW -/* SD_CS */ -.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE5 -.set SD_CS__0__MASK, 0x20 -.set SD_CS__0__PC, CYREG_PRT3_PC5 -.set SD_CS__0__PORT, 3 -.set SD_CS__0__SHIFT, 5 -.set SD_CS__AG, CYREG_PRT3_AG -.set SD_CS__AMUX, CYREG_PRT3_AMUX -.set SD_CS__BIE, CYREG_PRT3_BIE -.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_CS__BYP, CYREG_PRT3_BYP -.set SD_CS__CTL, CYREG_PRT3_CTL -.set SD_CS__DM0, CYREG_PRT3_DM0 -.set SD_CS__DM1, CYREG_PRT3_DM1 -.set SD_CS__DM2, CYREG_PRT3_DM2 -.set SD_CS__DR, CYREG_PRT3_DR -.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_CS__MASK, 0x20 -.set SD_CS__PORT, 3 -.set SD_CS__PRT, CYREG_PRT3_PRT -.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_CS__PS, CYREG_PRT3_PS -.set SD_CS__SHIFT, 5 -.set SD_CS__SLW, CYREG_PRT3_SLW +/* SCSI_CLK */ +.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 +.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 +.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2 +.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07 +.set SCSI_CLK__INDEX, 0x01 +.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SCSI_CLK__PM_ACT_MSK, 0x02 +.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SCSI_CLK__PM_STBY_MSK, 0x02 -/* USBFS_arb_int */ -.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_arb_int__INTC_MASK, 0x400000 -.set USBFS_arb_int__INTC_NUMBER, 22 -.set USBFS_arb_int__INTC_PRIOR_NUM, 6 -.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 -.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* SCSI_CTL_PHASE */ +.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK -/* USBFS_bus_reset */ -.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_bus_reset__INTC_MASK, 0x800000 -.set USBFS_bus_reset__INTC_NUMBER, 23 -.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 -.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 -.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* SCSI_Filtered */ +.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Filtered_sts_sts_reg__0__POS, 0 +.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 +.set SCSI_Filtered_sts_sts_reg__1__POS, 1 +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST +.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 +.set SCSI_Filtered_sts_sts_reg__2__POS, 2 +.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 +.set SCSI_Filtered_sts_sts_reg__3__POS, 3 +.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 +.set SCSI_Filtered_sts_sts_reg__4__POS, 4 +.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK +.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST -/* USBFS_Dm */ -.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7 -.set USBFS_Dm__0__MASK, 0x80 -.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 -.set USBFS_Dm__0__PORT, 15 -.set USBFS_Dm__0__SHIFT, 7 -.set USBFS_Dm__AG, CYREG_PRT15_AG -.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX -.set USBFS_Dm__BIE, CYREG_PRT15_BIE -.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK -.set USBFS_Dm__BYP, CYREG_PRT15_BYP -.set USBFS_Dm__CTL, CYREG_PRT15_CTL -.set USBFS_Dm__DM0, CYREG_PRT15_DM0 -.set USBFS_Dm__DM1, CYREG_PRT15_DM1 -.set USBFS_Dm__DM2, CYREG_PRT15_DM2 -.set USBFS_Dm__DR, CYREG_PRT15_DR -.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS -.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE -.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG -.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN -.set USBFS_Dm__MASK, 0x80 -.set USBFS_Dm__PORT, 15 -.set USBFS_Dm__PRT, CYREG_PRT15_PRT -.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL -.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN -.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 -.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 -.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 -.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 -.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT -.set USBFS_Dm__PS, CYREG_PRT15_PS -.set USBFS_Dm__SHIFT, 7 -.set USBFS_Dm__SLW, CYREG_PRT15_SLW - -/* USBFS_Dp */ -.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6 -.set USBFS_Dp__0__MASK, 0x40 -.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 -.set USBFS_Dp__0__PORT, 15 -.set USBFS_Dp__0__SHIFT, 6 -.set USBFS_Dp__AG, CYREG_PRT15_AG -.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX -.set USBFS_Dp__BIE, CYREG_PRT15_BIE -.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK -.set USBFS_Dp__BYP, CYREG_PRT15_BYP -.set USBFS_Dp__CTL, CYREG_PRT15_CTL -.set USBFS_Dp__DM0, CYREG_PRT15_DM0 -.set USBFS_Dp__DM1, CYREG_PRT15_DM1 -.set USBFS_Dp__DM2, CYREG_PRT15_DM2 -.set USBFS_Dp__DR, CYREG_PRT15_DR -.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS -.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT -.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE -.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG -.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN -.set USBFS_Dp__MASK, 0x40 -.set USBFS_Dp__PORT, 15 -.set USBFS_Dp__PRT, CYREG_PRT15_PRT -.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL -.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN -.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 -.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 -.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 -.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 -.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT -.set USBFS_Dp__PS, CYREG_PRT15_PS -.set USBFS_Dp__SHIFT, 6 -.set USBFS_Dp__SLW, CYREG_PRT15_SLW -.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 - -/* USBFS_dp_int */ -.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_dp_int__INTC_MASK, 0x1000 -.set USBFS_dp_int__INTC_NUMBER, 12 -.set USBFS_dp_int__INTC_PRIOR_NUM, 7 -.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 -.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_0 */ -.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_0__INTC_MASK, 0x1000000 -.set USBFS_ep_0__INTC_NUMBER, 24 -.set USBFS_ep_0__INTC_PRIOR_NUM, 7 -.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 -.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_1 */ -.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x80 -.set USBFS_ep_1__INTC_NUMBER, 7 -.set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 -.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_2 */ -.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x100 -.set USBFS_ep_2__INTC_NUMBER, 8 -.set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 -.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_3 */ -.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_3__INTC_MASK, 0x200 -.set USBFS_ep_3__INTC_NUMBER, 9 -.set USBFS_ep_3__INTC_PRIOR_NUM, 7 -.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 -.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_4 */ -.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_4__INTC_MASK, 0x400 -.set USBFS_ep_4__INTC_NUMBER, 10 -.set USBFS_ep_4__INTC_PRIOR_NUM, 7 -.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 -.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_sof_int */ -.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_sof_int__INTC_MASK, 0x200000 -.set USBFS_sof_int__INTC_NUMBER, 21 -.set USBFS_sof_int__INTC_PRIOR_NUM, 7 -.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 -.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_USB */ -.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG -.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG -.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN -.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR -.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG -.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN -.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR -.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG -.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN -.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR -.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG -.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN -.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR -.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG -.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN -.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR -.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG -.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN -.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR -.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG -.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN -.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR -.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG -.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN -.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR -.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN -.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR -.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR -.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA -.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB -.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA -.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB -.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR -.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA -.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB -.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA -.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB -.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR -.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA -.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB -.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA -.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB -.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR -.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA -.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB -.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA -.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB -.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR -.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA -.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB -.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA -.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB -.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR -.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA -.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB -.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA -.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB -.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR -.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA -.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB -.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA -.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB -.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR -.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA -.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB -.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA -.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB -.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE -.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT -.set USBFS_USB__CR0, CYREG_USB_CR0 -.set USBFS_USB__CR1, CYREG_USB_CR1 -.set USBFS_USB__CWA, CYREG_USB_CWA -.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB -.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES -.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB -.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG -.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE -.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE -.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT -.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR -.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 -.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 -.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 -.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 -.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 -.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 -.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 -.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 -.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE -.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 -.set USBFS_USB__PM_ACT_MSK, 0x01 -.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 -.set USBFS_USB__PM_STBY_MSK, 0x01 -.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN -.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR -.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 -.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 -.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 -.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 -.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 -.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 -.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 -.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 -.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 -.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 -.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 -.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 -.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 -.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 -.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 -.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 -.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 -.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 -.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 -.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 -.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 -.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 -.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 -.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 -.set USBFS_USB__SOF0, CYREG_USB_SOF0 -.set USBFS_USB__SOF1, CYREG_USB_SOF1 -.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN -.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 -.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 - -/* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST -.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 -.set SDCard_BSPIM_RxStsReg__4__POS, 4 -.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 -.set SDCard_BSPIM_RxStsReg__5__POS, 5 -.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 -.set SDCard_BSPIM_RxStsReg__6__POS, 6 -.set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK -.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 -.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 -.set SDCard_BSPIM_TxStsReg__0__POS, 0 -.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 -.set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST -.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 -.set SDCard_BSPIM_TxStsReg__2__POS, 2 -.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 -.set SDCard_BSPIM_TxStsReg__3__POS, 3 -.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 -.set SDCard_BSPIM_TxStsReg__4__POS, 4 -.set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST - -/* SD_SCK */ -.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE3 -.set SD_SCK__0__MASK, 0x08 -.set SD_SCK__0__PC, CYREG_PRT3_PC3 -.set SD_SCK__0__PORT, 3 -.set SD_SCK__0__SHIFT, 3 -.set SD_SCK__AG, CYREG_PRT3_AG -.set SD_SCK__AMUX, CYREG_PRT3_AMUX -.set SD_SCK__BIE, CYREG_PRT3_BIE -.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_SCK__BYP, CYREG_PRT3_BYP -.set SD_SCK__CTL, CYREG_PRT3_CTL -.set SD_SCK__DM0, CYREG_PRT3_DM0 -.set SD_SCK__DM1, CYREG_PRT3_DM1 -.set SD_SCK__DM2, CYREG_PRT3_DM2 -.set SD_SCK__DR, CYREG_PRT3_DR -.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_SCK__MASK, 0x08 -.set SD_SCK__PORT, 3 -.set SD_SCK__PRT, CYREG_PRT3_PRT -.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_SCK__PS, CYREG_PRT3_PS -.set SD_SCK__SHIFT, 3 -.set SD_SCK__SLW, CYREG_PRT3_SLW +/* SCSI_Glitch_Ctl */ +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK /* SCSI_In */ .set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1 @@ -512,8 +204,6 @@ .set SCSI_In__PS, CYREG_PRT6_PS .set SCSI_In__SHIFT, 1 .set SCSI_In__SLW, CYREG_PRT6_SLW - -/* SCSI_In_DBx */ .set SCSI_In_DBx__0__AG, CYREG_PRT6_AG .set SCSI_In_DBx__0__AMUX, CYREG_PRT6_AMUX .set SCSI_In_DBx__0__BIE, CYREG_PRT6_BIE @@ -961,118 +651,287 @@ .set SCSI_In_DBx__DB7__SHIFT, 3 .set SCSI_In_DBx__DB7__SLW, CYREG_PRT6_SLW -/* SD_MISO */ -.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE2 -.set SD_MISO__0__MASK, 0x04 -.set SD_MISO__0__PC, CYREG_PRT3_PC2 -.set SD_MISO__0__PORT, 3 -.set SD_MISO__0__SHIFT, 2 -.set SD_MISO__AG, CYREG_PRT3_AG -.set SD_MISO__AMUX, CYREG_PRT3_AMUX -.set SD_MISO__BIE, CYREG_PRT3_BIE -.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_MISO__BYP, CYREG_PRT3_BYP -.set SD_MISO__CTL, CYREG_PRT3_CTL -.set SD_MISO__DM0, CYREG_PRT3_DM0 -.set SD_MISO__DM1, CYREG_PRT3_DM1 -.set SD_MISO__DM2, CYREG_PRT3_DM2 -.set SD_MISO__DR, CYREG_PRT3_DR -.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_MISO__MASK, 0x04 -.set SD_MISO__PORT, 3 -.set SD_MISO__PRT, CYREG_PRT3_PRT -.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_MISO__PS, CYREG_PRT3_PS -.set SD_MISO__SHIFT, 2 -.set SD_MISO__SLW, CYREG_PRT3_SLW - -/* SD_MOSI */ -.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE4 -.set SD_MOSI__0__MASK, 0x10 -.set SD_MOSI__0__PC, CYREG_PRT3_PC4 -.set SD_MOSI__0__PORT, 3 -.set SD_MOSI__0__SHIFT, 4 -.set SD_MOSI__AG, CYREG_PRT3_AG -.set SD_MOSI__AMUX, CYREG_PRT3_AMUX -.set SD_MOSI__BIE, CYREG_PRT3_BIE -.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_MOSI__BYP, CYREG_PRT3_BYP -.set SD_MOSI__CTL, CYREG_PRT3_CTL -.set SD_MOSI__DM0, CYREG_PRT3_DM0 -.set SD_MOSI__DM1, CYREG_PRT3_DM1 -.set SD_MOSI__DM2, CYREG_PRT3_DM2 -.set SD_MOSI__DR, CYREG_PRT3_DR -.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_MOSI__MASK, 0x10 -.set SD_MOSI__PORT, 3 -.set SD_MOSI__PRT, CYREG_PRT3_PRT -.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_MOSI__PS, CYREG_PRT3_PS -.set SD_MOSI__SHIFT, 4 -.set SD_MOSI__SLW, CYREG_PRT3_SLW - -/* TERM_EN */ -.set TERM_EN__0__INTTYPE, CYREG_PICU15_INTTYPE3 -.set TERM_EN__0__MASK, 0x08 -.set TERM_EN__0__PC, CYREG_IO_PC_PRT15_PC3 -.set TERM_EN__0__PORT, 15 -.set TERM_EN__0__SHIFT, 3 -.set TERM_EN__AG, CYREG_PRT15_AG -.set TERM_EN__AMUX, CYREG_PRT15_AMUX -.set TERM_EN__BIE, CYREG_PRT15_BIE -.set TERM_EN__BIT_MASK, CYREG_PRT15_BIT_MASK -.set TERM_EN__BYP, CYREG_PRT15_BYP -.set TERM_EN__CTL, CYREG_PRT15_CTL -.set TERM_EN__DM0, CYREG_PRT15_DM0 -.set TERM_EN__DM1, CYREG_PRT15_DM1 -.set TERM_EN__DM2, CYREG_PRT15_DM2 -.set TERM_EN__DR, CYREG_PRT15_DR -.set TERM_EN__INP_DIS, CYREG_PRT15_INP_DIS -.set TERM_EN__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE -.set TERM_EN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG -.set TERM_EN__LCD_EN, CYREG_PRT15_LCD_EN -.set TERM_EN__MASK, 0x08 -.set TERM_EN__PORT, 15 -.set TERM_EN__PRT, CYREG_PRT15_PRT -.set TERM_EN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL -.set TERM_EN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN -.set TERM_EN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 -.set TERM_EN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 -.set TERM_EN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 -.set TERM_EN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 -.set TERM_EN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT -.set TERM_EN__PS, CYREG_PRT15_PS -.set TERM_EN__SHIFT, 3 -.set TERM_EN__SLW, CYREG_PRT15_SLW - -/* SCSI_CLK */ -.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 -.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 -.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2 -.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07 -.set SCSI_CLK__INDEX, 0x01 -.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set SCSI_CLK__PM_ACT_MSK, 0x02 -.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set SCSI_CLK__PM_STBY_MSK, 0x02 +/* SCSI_Noise */ +.set SCSI_Noise__0__AG, CYREG_PRT4_AG +.set SCSI_Noise__0__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__0__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__0__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__0__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__0__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__0__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__0__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__0__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__0__DR, CYREG_PRT4_DR +.set SCSI_Noise__0__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__0__INTTYPE, CYREG_PICU4_INTTYPE7 +.set SCSI_Noise__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__0__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__0__MASK, 0x80 +.set SCSI_Noise__0__PC, CYREG_PRT4_PC7 +.set SCSI_Noise__0__PORT, 4 +.set SCSI_Noise__0__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__0__PS, CYREG_PRT4_PS +.set SCSI_Noise__0__SHIFT, 7 +.set SCSI_Noise__0__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__1__AG, CYREG_PRT4_AG +.set SCSI_Noise__1__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__1__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__1__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__1__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__1__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__1__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__1__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__1__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__1__DR, CYREG_PRT4_DR +.set SCSI_Noise__1__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__1__INTTYPE, CYREG_PICU4_INTTYPE5 +.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__1__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__1__MASK, 0x20 +.set SCSI_Noise__1__PC, CYREG_PRT4_PC5 +.set SCSI_Noise__1__PORT, 4 +.set SCSI_Noise__1__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__1__PS, CYREG_PRT4_PS +.set SCSI_Noise__1__SHIFT, 5 +.set SCSI_Noise__1__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__2__AG, CYREG_PRT0_AG +.set SCSI_Noise__2__AMUX, CYREG_PRT0_AMUX +.set SCSI_Noise__2__BIE, CYREG_PRT0_BIE +.set SCSI_Noise__2__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Noise__2__BYP, CYREG_PRT0_BYP +.set SCSI_Noise__2__CTL, CYREG_PRT0_CTL +.set SCSI_Noise__2__DM0, CYREG_PRT0_DM0 +.set SCSI_Noise__2__DM1, CYREG_PRT0_DM1 +.set SCSI_Noise__2__DM2, CYREG_PRT0_DM2 +.set SCSI_Noise__2__DR, CYREG_PRT0_DR +.set SCSI_Noise__2__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Noise__2__INTTYPE, CYREG_PICU0_INTTYPE2 +.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Noise__2__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Noise__2__MASK, 0x04 +.set SCSI_Noise__2__PC, CYREG_PRT0_PC2 +.set SCSI_Noise__2__PORT, 0 +.set SCSI_Noise__2__PRT, CYREG_PRT0_PRT +.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Noise__2__PS, CYREG_PRT0_PS +.set SCSI_Noise__2__SHIFT, 2 +.set SCSI_Noise__2__SLW, CYREG_PRT0_SLW +.set SCSI_Noise__3__AG, CYREG_PRT0_AG +.set SCSI_Noise__3__AMUX, CYREG_PRT0_AMUX +.set SCSI_Noise__3__BIE, CYREG_PRT0_BIE +.set SCSI_Noise__3__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Noise__3__BYP, CYREG_PRT0_BYP +.set SCSI_Noise__3__CTL, CYREG_PRT0_CTL +.set SCSI_Noise__3__DM0, CYREG_PRT0_DM0 +.set SCSI_Noise__3__DM1, CYREG_PRT0_DM1 +.set SCSI_Noise__3__DM2, CYREG_PRT0_DM2 +.set SCSI_Noise__3__DR, CYREG_PRT0_DR +.set SCSI_Noise__3__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Noise__3__INTTYPE, CYREG_PICU0_INTTYPE6 +.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Noise__3__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Noise__3__MASK, 0x40 +.set SCSI_Noise__3__PC, CYREG_PRT0_PC6 +.set SCSI_Noise__3__PORT, 0 +.set SCSI_Noise__3__PRT, CYREG_PRT0_PRT +.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Noise__3__PS, CYREG_PRT0_PS +.set SCSI_Noise__3__SHIFT, 6 +.set SCSI_Noise__3__SLW, CYREG_PRT0_SLW +.set SCSI_Noise__4__AG, CYREG_PRT4_AG +.set SCSI_Noise__4__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__4__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__4__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__4__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__4__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__4__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__4__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__4__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__4__DR, CYREG_PRT4_DR +.set SCSI_Noise__4__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__4__INTTYPE, CYREG_PICU4_INTTYPE3 +.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__4__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__4__MASK, 0x08 +.set SCSI_Noise__4__PC, CYREG_PRT4_PC3 +.set SCSI_Noise__4__PORT, 4 +.set SCSI_Noise__4__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__4__PS, CYREG_PRT4_PS +.set SCSI_Noise__4__SHIFT, 3 +.set SCSI_Noise__4__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__ACK__AG, CYREG_PRT4_AG +.set SCSI_Noise__ACK__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__ACK__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__ACK__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__ACK__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__ACK__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__ACK__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__ACK__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__ACK__DR, CYREG_PRT4_DR +.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__ACK__INTTYPE, CYREG_PICU4_INTTYPE3 +.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__ACK__MASK, 0x08 +.set SCSI_Noise__ACK__PC, CYREG_PRT4_PC3 +.set SCSI_Noise__ACK__PORT, 4 +.set SCSI_Noise__ACK__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__ACK__PS, CYREG_PRT4_PS +.set SCSI_Noise__ACK__SHIFT, 3 +.set SCSI_Noise__ACK__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__ATN__AG, CYREG_PRT4_AG +.set SCSI_Noise__ATN__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__ATN__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__ATN__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__ATN__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__ATN__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__ATN__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__ATN__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__ATN__DR, CYREG_PRT4_DR +.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__ATN__INTTYPE, CYREG_PICU4_INTTYPE7 +.set SCSI_Noise__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__ATN__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__ATN__MASK, 0x80 +.set SCSI_Noise__ATN__PC, CYREG_PRT4_PC7 +.set SCSI_Noise__ATN__PORT, 4 +.set SCSI_Noise__ATN__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__ATN__PS, CYREG_PRT4_PS +.set SCSI_Noise__ATN__SHIFT, 7 +.set SCSI_Noise__ATN__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__BSY__AG, CYREG_PRT4_AG +.set SCSI_Noise__BSY__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__BSY__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__BSY__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__BSY__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__BSY__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__BSY__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__BSY__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__BSY__DR, CYREG_PRT4_DR +.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__BSY__INTTYPE, CYREG_PICU4_INTTYPE5 +.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__BSY__MASK, 0x20 +.set SCSI_Noise__BSY__PC, CYREG_PRT4_PC5 +.set SCSI_Noise__BSY__PORT, 4 +.set SCSI_Noise__BSY__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__BSY__PS, CYREG_PRT4_PS +.set SCSI_Noise__BSY__SHIFT, 5 +.set SCSI_Noise__BSY__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__RST__AG, CYREG_PRT0_AG +.set SCSI_Noise__RST__AMUX, CYREG_PRT0_AMUX +.set SCSI_Noise__RST__BIE, CYREG_PRT0_BIE +.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Noise__RST__BYP, CYREG_PRT0_BYP +.set SCSI_Noise__RST__CTL, CYREG_PRT0_CTL +.set SCSI_Noise__RST__DM0, CYREG_PRT0_DM0 +.set SCSI_Noise__RST__DM1, CYREG_PRT0_DM1 +.set SCSI_Noise__RST__DM2, CYREG_PRT0_DM2 +.set SCSI_Noise__RST__DR, CYREG_PRT0_DR +.set SCSI_Noise__RST__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Noise__RST__INTTYPE, CYREG_PICU0_INTTYPE6 +.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Noise__RST__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Noise__RST__MASK, 0x40 +.set SCSI_Noise__RST__PC, CYREG_PRT0_PC6 +.set SCSI_Noise__RST__PORT, 0 +.set SCSI_Noise__RST__PRT, CYREG_PRT0_PRT +.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Noise__RST__PS, CYREG_PRT0_PS +.set SCSI_Noise__RST__SHIFT, 6 +.set SCSI_Noise__RST__SLW, CYREG_PRT0_SLW +.set SCSI_Noise__SEL__AG, CYREG_PRT0_AG +.set SCSI_Noise__SEL__AMUX, CYREG_PRT0_AMUX +.set SCSI_Noise__SEL__BIE, CYREG_PRT0_BIE +.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Noise__SEL__BYP, CYREG_PRT0_BYP +.set SCSI_Noise__SEL__CTL, CYREG_PRT0_CTL +.set SCSI_Noise__SEL__DM0, CYREG_PRT0_DM0 +.set SCSI_Noise__SEL__DM1, CYREG_PRT0_DM1 +.set SCSI_Noise__SEL__DM2, CYREG_PRT0_DM2 +.set SCSI_Noise__SEL__DR, CYREG_PRT0_DR +.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Noise__SEL__INTTYPE, CYREG_PICU0_INTTYPE2 +.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Noise__SEL__MASK, 0x04 +.set SCSI_Noise__SEL__PC, CYREG_PRT0_PC2 +.set SCSI_Noise__SEL__PORT, 0 +.set SCSI_Noise__SEL__PRT, CYREG_PRT0_PRT +.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Noise__SEL__PS, CYREG_PRT0_PS +.set SCSI_Noise__SEL__SHIFT, 2 +.set SCSI_Noise__SEL__SLW, CYREG_PRT0_SLW /* SCSI_Out */ .set SCSI_Out__0__AG, CYREG_PRT6_AG @@ -1521,8 +1380,6 @@ .set SCSI_Out__SEL__PS, CYREG_PRT0_PS .set SCSI_Out__SEL__SHIFT, 3 .set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW - -/* SCSI_Out_Bits */ .set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 @@ -1557,8 +1414,6 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL .set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL .set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK - -/* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL @@ -1579,8 +1434,6 @@ .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL .set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL .set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK - -/* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG .set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX .set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE @@ -2028,6 +1881,272 @@ .set SCSI_Out_DBx__DB7__SHIFT, 5 .set SCSI_Out_DBx__DB7__SLW, CYREG_PRT15_SLW +/* SCSI_Parity_Error */ +.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK +.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST + +/* SCSI_RST_ISR */ +.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RST_ISR__INTC_MASK, 0x02 +.set SCSI_RST_ISR__INTC_NUMBER, 1 +.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_RX_DMA */ +.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_RX_DMA__DRQ_NUMBER, 0 +.set SCSI_RX_DMA__NUMBEROF_TDS, 0 +.set SCSI_RX_DMA__PRIORITY, 2 +.set SCSI_RX_DMA__TERMIN_EN, 0 +.set SCSI_RX_DMA__TERMIN_SEL, 0 +.set SCSI_RX_DMA__TERMOUT0_EN, 1 +.set SCSI_RX_DMA__TERMOUT0_SEL, 0 +.set SCSI_RX_DMA__TERMOUT1_EN, 0 +.set SCSI_RX_DMA__TERMOUT1_SEL, 0 +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04 +.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_SEL_ISR__INTC_MASK, 0x08 +.set SCSI_SEL_ISR__INTC_NUMBER, 3 +.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_TX_DMA__DRQ_NUMBER, 1 +.set SCSI_TX_DMA__NUMBEROF_TDS, 0 +.set SCSI_TX_DMA__PRIORITY, 2 +.set SCSI_TX_DMA__TERMIN_EN, 0 +.set SCSI_TX_DMA__TERMIN_SEL, 0 +.set SCSI_TX_DMA__TERMOUT0_EN, 1 +.set SCSI_TX_DMA__TERMOUT0_SEL, 1 +.set SCSI_TX_DMA__TERMOUT1_EN, 0 +.set SCSI_TX_DMA__TERMOUT1_SEL, 0 +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 +.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SDCard_BSPIM */ +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST +.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_RxStsReg__4__POS, 4 +.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 +.set SDCard_BSPIM_RxStsReg__5__POS, 5 +.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 +.set SDCard_BSPIM_RxStsReg__6__POS, 6 +.set SDCard_BSPIM_RxStsReg__MASK, 0x70 +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK +.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL +.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 +.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 +.set SDCard_BSPIM_TxStsReg__0__POS, 0 +.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 +.set SDCard_BSPIM_TxStsReg__1__POS, 1 +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 +.set SDCard_BSPIM_TxStsReg__2__POS, 2 +.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 +.set SDCard_BSPIM_TxStsReg__3__POS, 3 +.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_TxStsReg__4__POS, 4 +.set SDCard_BSPIM_TxStsReg__MASK, 0x1F +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST + +/* SD_CS */ +.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE5 +.set SD_CS__0__MASK, 0x20 +.set SD_CS__0__PC, CYREG_PRT3_PC5 +.set SD_CS__0__PORT, 3 +.set SD_CS__0__SHIFT, 5 +.set SD_CS__AG, CYREG_PRT3_AG +.set SD_CS__AMUX, CYREG_PRT3_AMUX +.set SD_CS__BIE, CYREG_PRT3_BIE +.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CS__BYP, CYREG_PRT3_BYP +.set SD_CS__CTL, CYREG_PRT3_CTL +.set SD_CS__DM0, CYREG_PRT3_DM0 +.set SD_CS__DM1, CYREG_PRT3_DM1 +.set SD_CS__DM2, CYREG_PRT3_DM2 +.set SD_CS__DR, CYREG_PRT3_DR +.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CS__MASK, 0x20 +.set SD_CS__PORT, 3 +.set SD_CS__PRT, CYREG_PRT3_PRT +.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CS__PS, CYREG_PRT3_PS +.set SD_CS__SHIFT, 5 +.set SD_CS__SLW, CYREG_PRT3_SLW + +/* SD_Data_Clk */ +.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 +.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 +.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 +.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 +.set SD_Data_Clk__INDEX, 0x00 +.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SD_Data_Clk__PM_ACT_MSK, 0x01 +.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SD_Data_Clk__PM_STBY_MSK, 0x01 + +/* SD_MISO */ +.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE2 +.set SD_MISO__0__MASK, 0x04 +.set SD_MISO__0__PC, CYREG_PRT3_PC2 +.set SD_MISO__0__PORT, 3 +.set SD_MISO__0__SHIFT, 2 +.set SD_MISO__AG, CYREG_PRT3_AG +.set SD_MISO__AMUX, CYREG_PRT3_AMUX +.set SD_MISO__BIE, CYREG_PRT3_BIE +.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MISO__BYP, CYREG_PRT3_BYP +.set SD_MISO__CTL, CYREG_PRT3_CTL +.set SD_MISO__DM0, CYREG_PRT3_DM0 +.set SD_MISO__DM1, CYREG_PRT3_DM1 +.set SD_MISO__DM2, CYREG_PRT3_DM2 +.set SD_MISO__DR, CYREG_PRT3_DR +.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MISO__MASK, 0x04 +.set SD_MISO__PORT, 3 +.set SD_MISO__PRT, CYREG_PRT3_PRT +.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MISO__PS, CYREG_PRT3_PS +.set SD_MISO__SHIFT, 2 +.set SD_MISO__SLW, CYREG_PRT3_SLW + +/* SD_MOSI */ +.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE4 +.set SD_MOSI__0__MASK, 0x10 +.set SD_MOSI__0__PC, CYREG_PRT3_PC4 +.set SD_MOSI__0__PORT, 3 +.set SD_MOSI__0__SHIFT, 4 +.set SD_MOSI__AG, CYREG_PRT3_AG +.set SD_MOSI__AMUX, CYREG_PRT3_AMUX +.set SD_MOSI__BIE, CYREG_PRT3_BIE +.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MOSI__BYP, CYREG_PRT3_BYP +.set SD_MOSI__CTL, CYREG_PRT3_CTL +.set SD_MOSI__DM0, CYREG_PRT3_DM0 +.set SD_MOSI__DM1, CYREG_PRT3_DM1 +.set SD_MOSI__DM2, CYREG_PRT3_DM2 +.set SD_MOSI__DR, CYREG_PRT3_DR +.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MOSI__MASK, 0x10 +.set SD_MOSI__PORT, 3 +.set SD_MOSI__PRT, CYREG_PRT3_PRT +.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MOSI__PS, CYREG_PRT3_PS +.set SD_MOSI__SHIFT, 4 +.set SD_MOSI__SLW, CYREG_PRT3_SLW + /* SD_RX_DMA */ .set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_RX_DMA__DRQ_NUMBER, 2 @@ -2039,8 +2158,6 @@ .set SD_RX_DMA__TERMOUT0_SEL, 2 .set SD_RX_DMA__TERMOUT1_EN, 0 .set SD_RX_DMA__TERMOUT1_SEL, 0 - -/* SD_RX_DMA_COMPLETE */ .set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 .set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20 @@ -2050,6 +2167,40 @@ .set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* SD_SCK */ +.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE3 +.set SD_SCK__0__MASK, 0x08 +.set SD_SCK__0__PC, CYREG_PRT3_PC3 +.set SD_SCK__0__PORT, 3 +.set SD_SCK__0__SHIFT, 3 +.set SD_SCK__AG, CYREG_PRT3_AG +.set SD_SCK__AMUX, CYREG_PRT3_AMUX +.set SD_SCK__BIE, CYREG_PRT3_BIE +.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_SCK__BYP, CYREG_PRT3_BYP +.set SD_SCK__CTL, CYREG_PRT3_CTL +.set SD_SCK__DM0, CYREG_PRT3_DM0 +.set SD_SCK__DM1, CYREG_PRT3_DM1 +.set SD_SCK__DM2, CYREG_PRT3_DM2 +.set SD_SCK__DR, CYREG_PRT3_DR +.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_SCK__MASK, 0x08 +.set SD_SCK__PORT, 3 +.set SD_SCK__PRT, CYREG_PRT3_PRT +.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_SCK__PS, CYREG_PRT3_PS +.set SD_SCK__SHIFT, 3 +.set SD_SCK__SLW, CYREG_PRT3_SLW + /* SD_TX_DMA */ .set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_TX_DMA__DRQ_NUMBER, 3 @@ -2061,8 +2212,6 @@ .set SD_TX_DMA__TERMOUT0_SEL, 3 .set SD_TX_DMA__TERMOUT1_EN, 0 .set SD_TX_DMA__TERMOUT1_SEL, 0 - -/* SD_TX_DMA_COMPLETE */ .set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 .set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40 @@ -2072,287 +2221,303 @@ .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -/* SCSI_Noise */ -.set SCSI_Noise__0__AG, CYREG_PRT4_AG -.set SCSI_Noise__0__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__0__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__0__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__0__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__0__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__0__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__0__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__0__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__0__DR, CYREG_PRT4_DR -.set SCSI_Noise__0__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__0__INTTYPE, CYREG_PICU4_INTTYPE7 -.set SCSI_Noise__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__0__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__0__MASK, 0x80 -.set SCSI_Noise__0__PC, CYREG_PRT4_PC7 -.set SCSI_Noise__0__PORT, 4 -.set SCSI_Noise__0__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__0__PS, CYREG_PRT4_PS -.set SCSI_Noise__0__SHIFT, 7 -.set SCSI_Noise__0__SLW, CYREG_PRT4_SLW -.set SCSI_Noise__1__AG, CYREG_PRT4_AG -.set SCSI_Noise__1__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__1__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__1__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__1__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__1__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__1__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__1__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__1__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__1__DR, CYREG_PRT4_DR -.set SCSI_Noise__1__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__1__INTTYPE, CYREG_PICU4_INTTYPE5 -.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__1__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__1__MASK, 0x20 -.set SCSI_Noise__1__PC, CYREG_PRT4_PC5 -.set SCSI_Noise__1__PORT, 4 -.set SCSI_Noise__1__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__1__PS, CYREG_PRT4_PS -.set SCSI_Noise__1__SHIFT, 5 -.set SCSI_Noise__1__SLW, CYREG_PRT4_SLW -.set SCSI_Noise__2__AG, CYREG_PRT0_AG -.set SCSI_Noise__2__AMUX, CYREG_PRT0_AMUX -.set SCSI_Noise__2__BIE, CYREG_PRT0_BIE -.set SCSI_Noise__2__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Noise__2__BYP, CYREG_PRT0_BYP -.set SCSI_Noise__2__CTL, CYREG_PRT0_CTL -.set SCSI_Noise__2__DM0, CYREG_PRT0_DM0 -.set SCSI_Noise__2__DM1, CYREG_PRT0_DM1 -.set SCSI_Noise__2__DM2, CYREG_PRT0_DM2 -.set SCSI_Noise__2__DR, CYREG_PRT0_DR -.set SCSI_Noise__2__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Noise__2__INTTYPE, CYREG_PICU0_INTTYPE2 -.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Noise__2__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Noise__2__MASK, 0x04 -.set SCSI_Noise__2__PC, CYREG_PRT0_PC2 -.set SCSI_Noise__2__PORT, 0 -.set SCSI_Noise__2__PRT, CYREG_PRT0_PRT -.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Noise__2__PS, CYREG_PRT0_PS -.set SCSI_Noise__2__SHIFT, 2 -.set SCSI_Noise__2__SLW, CYREG_PRT0_SLW -.set SCSI_Noise__3__AG, CYREG_PRT0_AG -.set SCSI_Noise__3__AMUX, CYREG_PRT0_AMUX -.set SCSI_Noise__3__BIE, CYREG_PRT0_BIE -.set SCSI_Noise__3__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Noise__3__BYP, CYREG_PRT0_BYP -.set SCSI_Noise__3__CTL, CYREG_PRT0_CTL -.set SCSI_Noise__3__DM0, CYREG_PRT0_DM0 -.set SCSI_Noise__3__DM1, CYREG_PRT0_DM1 -.set SCSI_Noise__3__DM2, CYREG_PRT0_DM2 -.set SCSI_Noise__3__DR, CYREG_PRT0_DR -.set SCSI_Noise__3__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Noise__3__INTTYPE, CYREG_PICU0_INTTYPE6 -.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Noise__3__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Noise__3__MASK, 0x40 -.set SCSI_Noise__3__PC, CYREG_PRT0_PC6 -.set SCSI_Noise__3__PORT, 0 -.set SCSI_Noise__3__PRT, CYREG_PRT0_PRT -.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Noise__3__PS, CYREG_PRT0_PS -.set SCSI_Noise__3__SHIFT, 6 -.set SCSI_Noise__3__SLW, CYREG_PRT0_SLW -.set SCSI_Noise__4__AG, CYREG_PRT4_AG -.set SCSI_Noise__4__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__4__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__4__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__4__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__4__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__4__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__4__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__4__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__4__DR, CYREG_PRT4_DR -.set SCSI_Noise__4__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__4__INTTYPE, CYREG_PICU4_INTTYPE3 -.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__4__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__4__MASK, 0x08 -.set SCSI_Noise__4__PC, CYREG_PRT4_PC3 -.set SCSI_Noise__4__PORT, 4 -.set SCSI_Noise__4__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__4__PS, CYREG_PRT4_PS -.set SCSI_Noise__4__SHIFT, 3 -.set SCSI_Noise__4__SLW, CYREG_PRT4_SLW -.set SCSI_Noise__ACK__AG, CYREG_PRT4_AG -.set SCSI_Noise__ACK__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__ACK__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__ACK__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__ACK__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__ACK__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__ACK__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__ACK__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__ACK__DR, CYREG_PRT4_DR -.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__ACK__INTTYPE, CYREG_PICU4_INTTYPE3 -.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__ACK__MASK, 0x08 -.set SCSI_Noise__ACK__PC, CYREG_PRT4_PC3 -.set SCSI_Noise__ACK__PORT, 4 -.set SCSI_Noise__ACK__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__ACK__PS, CYREG_PRT4_PS -.set SCSI_Noise__ACK__SHIFT, 3 -.set SCSI_Noise__ACK__SLW, CYREG_PRT4_SLW -.set SCSI_Noise__ATN__AG, CYREG_PRT4_AG -.set SCSI_Noise__ATN__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__ATN__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__ATN__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__ATN__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__ATN__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__ATN__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__ATN__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__ATN__DR, CYREG_PRT4_DR -.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__ATN__INTTYPE, CYREG_PICU4_INTTYPE7 -.set SCSI_Noise__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__ATN__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__ATN__MASK, 0x80 -.set SCSI_Noise__ATN__PC, CYREG_PRT4_PC7 -.set SCSI_Noise__ATN__PORT, 4 -.set SCSI_Noise__ATN__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__ATN__PS, CYREG_PRT4_PS -.set SCSI_Noise__ATN__SHIFT, 7 -.set SCSI_Noise__ATN__SLW, CYREG_PRT4_SLW -.set SCSI_Noise__BSY__AG, CYREG_PRT4_AG -.set SCSI_Noise__BSY__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__BSY__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__BSY__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__BSY__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__BSY__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__BSY__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__BSY__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__BSY__DR, CYREG_PRT4_DR -.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__BSY__INTTYPE, CYREG_PICU4_INTTYPE5 -.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__BSY__MASK, 0x20 -.set SCSI_Noise__BSY__PC, CYREG_PRT4_PC5 -.set SCSI_Noise__BSY__PORT, 4 -.set SCSI_Noise__BSY__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__BSY__PS, CYREG_PRT4_PS -.set SCSI_Noise__BSY__SHIFT, 5 -.set SCSI_Noise__BSY__SLW, CYREG_PRT4_SLW -.set SCSI_Noise__RST__AG, CYREG_PRT0_AG -.set SCSI_Noise__RST__AMUX, CYREG_PRT0_AMUX -.set SCSI_Noise__RST__BIE, CYREG_PRT0_BIE -.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Noise__RST__BYP, CYREG_PRT0_BYP -.set SCSI_Noise__RST__CTL, CYREG_PRT0_CTL -.set SCSI_Noise__RST__DM0, CYREG_PRT0_DM0 -.set SCSI_Noise__RST__DM1, CYREG_PRT0_DM1 -.set SCSI_Noise__RST__DM2, CYREG_PRT0_DM2 -.set SCSI_Noise__RST__DR, CYREG_PRT0_DR -.set SCSI_Noise__RST__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Noise__RST__INTTYPE, CYREG_PICU0_INTTYPE6 -.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Noise__RST__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Noise__RST__MASK, 0x40 -.set SCSI_Noise__RST__PC, CYREG_PRT0_PC6 -.set SCSI_Noise__RST__PORT, 0 -.set SCSI_Noise__RST__PRT, CYREG_PRT0_PRT -.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Noise__RST__PS, CYREG_PRT0_PS -.set SCSI_Noise__RST__SHIFT, 6 -.set SCSI_Noise__RST__SLW, CYREG_PRT0_SLW -.set SCSI_Noise__SEL__AG, CYREG_PRT0_AG -.set SCSI_Noise__SEL__AMUX, CYREG_PRT0_AMUX -.set SCSI_Noise__SEL__BIE, CYREG_PRT0_BIE -.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Noise__SEL__BYP, CYREG_PRT0_BYP -.set SCSI_Noise__SEL__CTL, CYREG_PRT0_CTL -.set SCSI_Noise__SEL__DM0, CYREG_PRT0_DM0 -.set SCSI_Noise__SEL__DM1, CYREG_PRT0_DM1 -.set SCSI_Noise__SEL__DM2, CYREG_PRT0_DM2 -.set SCSI_Noise__SEL__DR, CYREG_PRT0_DR -.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Noise__SEL__INTTYPE, CYREG_PICU0_INTTYPE2 -.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Noise__SEL__MASK, 0x04 -.set SCSI_Noise__SEL__PC, CYREG_PRT0_PC2 -.set SCSI_Noise__SEL__PORT, 0 -.set SCSI_Noise__SEL__PRT, CYREG_PRT0_PRT -.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Noise__SEL__PS, CYREG_PRT0_PS -.set SCSI_Noise__SEL__SHIFT, 2 -.set SCSI_Noise__SEL__SLW, CYREG_PRT0_SLW +/* TERM_EN */ +.set TERM_EN__0__INTTYPE, CYREG_PICU15_INTTYPE3 +.set TERM_EN__0__MASK, 0x08 +.set TERM_EN__0__PC, CYREG_IO_PC_PRT15_PC3 +.set TERM_EN__0__PORT, 15 +.set TERM_EN__0__SHIFT, 3 +.set TERM_EN__AG, CYREG_PRT15_AG +.set TERM_EN__AMUX, CYREG_PRT15_AMUX +.set TERM_EN__BIE, CYREG_PRT15_BIE +.set TERM_EN__BIT_MASK, CYREG_PRT15_BIT_MASK +.set TERM_EN__BYP, CYREG_PRT15_BYP +.set TERM_EN__CTL, CYREG_PRT15_CTL +.set TERM_EN__DM0, CYREG_PRT15_DM0 +.set TERM_EN__DM1, CYREG_PRT15_DM1 +.set TERM_EN__DM2, CYREG_PRT15_DM2 +.set TERM_EN__DR, CYREG_PRT15_DR +.set TERM_EN__INP_DIS, CYREG_PRT15_INP_DIS +.set TERM_EN__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set TERM_EN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set TERM_EN__LCD_EN, CYREG_PRT15_LCD_EN +.set TERM_EN__MASK, 0x08 +.set TERM_EN__PORT, 15 +.set TERM_EN__PRT, CYREG_PRT15_PRT +.set TERM_EN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set TERM_EN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set TERM_EN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set TERM_EN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set TERM_EN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set TERM_EN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set TERM_EN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set TERM_EN__PS, CYREG_PRT15_PS +.set TERM_EN__SHIFT, 3 +.set TERM_EN__SLW, CYREG_PRT15_SLW + +/* USBFS */ +.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_arb_int__INTC_MASK, 0x400000 +.set USBFS_arb_int__INTC_NUMBER, 22 +.set USBFS_arb_int__INTC_PRIOR_NUM, 6 +.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 +.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_bus_reset__INTC_MASK, 0x800000 +.set USBFS_bus_reset__INTC_NUMBER, 23 +.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 +.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 +.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7 +.set USBFS_Dm__0__MASK, 0x80 +.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 +.set USBFS_Dm__0__PORT, 15 +.set USBFS_Dm__0__SHIFT, 7 +.set USBFS_Dm__AG, CYREG_PRT15_AG +.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dm__BIE, CYREG_PRT15_BIE +.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dm__BYP, CYREG_PRT15_BYP +.set USBFS_Dm__CTL, CYREG_PRT15_CTL +.set USBFS_Dm__DM0, CYREG_PRT15_DM0 +.set USBFS_Dm__DM1, CYREG_PRT15_DM1 +.set USBFS_Dm__DM2, CYREG_PRT15_DM2 +.set USBFS_Dm__DR, CYREG_PRT15_DR +.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dm__MASK, 0x80 +.set USBFS_Dm__PORT, 15 +.set USBFS_Dm__PRT, CYREG_PRT15_PRT +.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dm__PS, CYREG_PRT15_PS +.set USBFS_Dm__SHIFT, 7 +.set USBFS_Dm__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6 +.set USBFS_Dp__0__MASK, 0x40 +.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 +.set USBFS_Dp__0__PORT, 15 +.set USBFS_Dp__0__SHIFT, 6 +.set USBFS_Dp__AG, CYREG_PRT15_AG +.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dp__BIE, CYREG_PRT15_BIE +.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dp__BYP, CYREG_PRT15_BYP +.set USBFS_Dp__CTL, CYREG_PRT15_CTL +.set USBFS_Dp__DM0, CYREG_PRT15_DM0 +.set USBFS_Dp__DM1, CYREG_PRT15_DM1 +.set USBFS_Dp__DM2, CYREG_PRT15_DM2 +.set USBFS_Dp__DR, CYREG_PRT15_DR +.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT +.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dp__MASK, 0x40 +.set USBFS_Dp__PORT, 15 +.set USBFS_Dp__PRT, CYREG_PRT15_PRT +.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dp__PS, CYREG_PRT15_PS +.set USBFS_Dp__SHIFT, 6 +.set USBFS_Dp__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 +.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_dp_int__INTC_MASK, 0x1000 +.set USBFS_dp_int__INTC_NUMBER, 12 +.set USBFS_dp_int__INTC_PRIOR_NUM, 7 +.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 +.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_0__INTC_MASK, 0x1000000 +.set USBFS_ep_0__INTC_NUMBER, 24 +.set USBFS_ep_0__INTC_PRIOR_NUM, 7 +.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 +.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_1__INTC_MASK, 0x80 +.set USBFS_ep_1__INTC_NUMBER, 7 +.set USBFS_ep_1__INTC_PRIOR_NUM, 7 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 +.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_2__INTC_MASK, 0x100 +.set USBFS_ep_2__INTC_NUMBER, 8 +.set USBFS_ep_2__INTC_PRIOR_NUM, 7 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 +.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_3__INTC_MASK, 0x200 +.set USBFS_ep_3__INTC_NUMBER, 9 +.set USBFS_ep_3__INTC_PRIOR_NUM, 7 +.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 +.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_4__INTC_MASK, 0x400 +.set USBFS_ep_4__INTC_NUMBER, 10 +.set USBFS_ep_4__INTC_PRIOR_NUM, 7 +.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 +.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_sof_int__INTC_MASK, 0x200000 +.set USBFS_sof_int__INTC_NUMBER, 21 +.set USBFS_sof_int__INTC_PRIOR_NUM, 7 +.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 +.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG +.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG +.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN +.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR +.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG +.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN +.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR +.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG +.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN +.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR +.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG +.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN +.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR +.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG +.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN +.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR +.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG +.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN +.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR +.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG +.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN +.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR +.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG +.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN +.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR +.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN +.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR +.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR +.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA +.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB +.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA +.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB +.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR +.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA +.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB +.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA +.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB +.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR +.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA +.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB +.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA +.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB +.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR +.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA +.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB +.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA +.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB +.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR +.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA +.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB +.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA +.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB +.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR +.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA +.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB +.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA +.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB +.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR +.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA +.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB +.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA +.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB +.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR +.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA +.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB +.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA +.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB +.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE +.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT +.set USBFS_USB__CR0, CYREG_USB_CR0 +.set USBFS_USB__CR1, CYREG_USB_CR1 +.set USBFS_USB__CWA, CYREG_USB_CWA +.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB +.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES +.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB +.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG +.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE +.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE +.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT +.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR +.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 +.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 +.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 +.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 +.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 +.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 +.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 +.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 +.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE +.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 +.set USBFS_USB__PM_ACT_MSK, 0x01 +.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 +.set USBFS_USB__PM_STBY_MSK, 0x01 +.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN +.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR +.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 +.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 +.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 +.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 +.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 +.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 +.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 +.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 +.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 +.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 +.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 +.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 +.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 +.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 +.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 +.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 +.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 +.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 +.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 +.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 +.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 +.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 +.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 +.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 +.set USBFS_USB__SOF0, CYREG_USB_SOF0 +.set USBFS_USB__SOF1, CYREG_USB_SOF1 +.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN +.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 +.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 /* scsiTarget */ .set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0 @@ -2415,89 +2580,6 @@ .set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL .set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST -/* Debug_Timer_Interrupt */ -.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set Debug_Timer_Interrupt__INTC_MASK, 0x02 -.set Debug_Timer_Interrupt__INTC_NUMBER, 1 -.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7 -.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 -.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0 -.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1 -.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0 -.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1 -.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2 -.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0 -.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1 -.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0 -.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1 -.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3 -.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01 -.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3 -.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01 -.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0 -.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1 -.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0 - -/* SCSI_RX_DMA */ -.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_RX_DMA__DRQ_NUMBER, 0 -.set SCSI_RX_DMA__NUMBEROF_TDS, 0 -.set SCSI_RX_DMA__PRIORITY, 2 -.set SCSI_RX_DMA__TERMIN_EN, 0 -.set SCSI_RX_DMA__TERMIN_SEL, 0 -.set SCSI_RX_DMA__TERMOUT0_EN, 1 -.set SCSI_RX_DMA__TERMOUT0_SEL, 0 -.set SCSI_RX_DMA__TERMOUT1_EN, 0 -.set SCSI_RX_DMA__TERMOUT1_SEL, 0 - -/* SCSI_RX_DMA_COMPLETE */ -.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01 -.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0 -.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 -.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_TX_DMA__DRQ_NUMBER, 1 -.set SCSI_TX_DMA__NUMBEROF_TDS, 0 -.set SCSI_TX_DMA__PRIORITY, 2 -.set SCSI_TX_DMA__TERMIN_EN, 0 -.set SCSI_TX_DMA__TERMIN_SEL, 0 -.set SCSI_TX_DMA__TERMOUT0_EN, 1 -.set SCSI_TX_DMA__TERMOUT0_SEL, 1 -.set SCSI_TX_DMA__TERMOUT1_EN, 0 -.set SCSI_TX_DMA__TERMOUT1_SEL, 0 - -/* SCSI_TX_DMA_COMPLETE */ -.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 -.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 -.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SD_Data_Clk */ -.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 -.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 -.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 -.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 -.set SD_Data_Clk__INDEX, 0x00 -.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set SD_Data_Clk__PM_ACT_MSK, 0x01 -.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set SD_Data_Clk__PM_STBY_MSK, 0x01 - /* timer_clock */ .set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0 .set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1 @@ -2509,154 +2591,53 @@ .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2 .set timer_clock__PM_STBY_MSK, 0x04 -/* SCSI_RST_ISR */ -.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RST_ISR__INTC_MASK, 0x04 -.set SCSI_RST_ISR__INTC_NUMBER, 2 -.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 -.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_SEL_ISR__INTC_MASK, 0x08 -.set SCSI_SEL_ISR__INTC_NUMBER, 3 -.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 -.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_Filtered */ -.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 -.set SCSI_Filtered_sts_sts_reg__0__POS, 0 -.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 -.set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST -.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 -.set SCSI_Filtered_sts_sts_reg__2__POS, 2 -.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 -.set SCSI_Filtered_sts_sts_reg__3__POS, 3 -.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 -.set SCSI_Filtered_sts_sts_reg__4__POS, 4 -.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK -.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL -.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST - -/* SCSI_CTL_PHASE */ -.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK - -/* SCSI_Glitch_Ctl */ -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK - -/* SCSI_Parity_Error */ -.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST -.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK -.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST - /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 .set BCLK__BUS_CLK__KHZ, 50000 .set BCLK__BUS_CLK__MHZ, 50 .set CYDEV_CHIP_DIE_LEOPARD, 1 -.set CYDEV_CHIP_DIE_PSOC4A, 12 -.set CYDEV_CHIP_DIE_PSOC5LP, 19 -.set CYDEV_CHIP_DIE_PSOC5TM, 20 -.set CYDEV_CHIP_DIE_TMA4, 2 +.set CYDEV_CHIP_DIE_PSOC4A, 16 +.set CYDEV_CHIP_DIE_PSOC5LP, 2 +.set CYDEV_CHIP_DIE_PSOC5TM, 3 +.set CYDEV_CHIP_DIE_TMA4, 4 .set CYDEV_CHIP_DIE_UNKNOWN, 0 -.set CYDEV_CHIP_FAMILY_FM0P, 4 -.set CYDEV_CHIP_FAMILY_FM3, 5 -.set CYDEV_CHIP_FAMILY_FM4, 6 +.set CYDEV_CHIP_FAMILY_FM0P, 5 +.set CYDEV_CHIP_FAMILY_FM3, 6 +.set CYDEV_CHIP_FAMILY_FM4, 7 .set CYDEV_CHIP_FAMILY_PSOC3, 1 .set CYDEV_CHIP_FAMILY_PSOC4, 2 .set CYDEV_CHIP_FAMILY_PSOC5, 3 +.set CYDEV_CHIP_FAMILY_PSOC6, 4 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 .set CYDEV_CHIP_JTAG_ID, 0x2E133069 .set CYDEV_CHIP_MEMBER_3A, 1 -.set CYDEV_CHIP_MEMBER_4A, 12 -.set CYDEV_CHIP_MEMBER_4C, 18 -.set CYDEV_CHIP_MEMBER_4D, 8 -.set CYDEV_CHIP_MEMBER_4E, 4 -.set CYDEV_CHIP_MEMBER_4F, 13 -.set CYDEV_CHIP_MEMBER_4G, 2 -.set CYDEV_CHIP_MEMBER_4H, 11 -.set CYDEV_CHIP_MEMBER_4I, 17 -.set CYDEV_CHIP_MEMBER_4J, 9 -.set CYDEV_CHIP_MEMBER_4K, 10 -.set CYDEV_CHIP_MEMBER_4L, 16 -.set CYDEV_CHIP_MEMBER_4M, 15 -.set CYDEV_CHIP_MEMBER_4N, 6 -.set CYDEV_CHIP_MEMBER_4O, 5 -.set CYDEV_CHIP_MEMBER_4P, 14 -.set CYDEV_CHIP_MEMBER_4Q, 7 -.set CYDEV_CHIP_MEMBER_4U, 3 -.set CYDEV_CHIP_MEMBER_5A, 20 -.set CYDEV_CHIP_MEMBER_5B, 19 -.set CYDEV_CHIP_MEMBER_FM3, 24 -.set CYDEV_CHIP_MEMBER_FM4, 25 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 21 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 22 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 23 +.set CYDEV_CHIP_MEMBER_4A, 16 +.set CYDEV_CHIP_MEMBER_4D, 12 +.set CYDEV_CHIP_MEMBER_4E, 6 +.set CYDEV_CHIP_MEMBER_4F, 17 +.set CYDEV_CHIP_MEMBER_4G, 4 +.set CYDEV_CHIP_MEMBER_4H, 15 +.set CYDEV_CHIP_MEMBER_4I, 21 +.set CYDEV_CHIP_MEMBER_4J, 13 +.set CYDEV_CHIP_MEMBER_4K, 14 +.set CYDEV_CHIP_MEMBER_4L, 20 +.set CYDEV_CHIP_MEMBER_4M, 19 +.set CYDEV_CHIP_MEMBER_4N, 9 +.set CYDEV_CHIP_MEMBER_4O, 7 +.set CYDEV_CHIP_MEMBER_4P, 18 +.set CYDEV_CHIP_MEMBER_4Q, 11 +.set CYDEV_CHIP_MEMBER_4R, 8 +.set CYDEV_CHIP_MEMBER_4S, 10 +.set CYDEV_CHIP_MEMBER_4U, 5 +.set CYDEV_CHIP_MEMBER_5A, 3 +.set CYDEV_CHIP_MEMBER_5B, 2 +.set CYDEV_CHIP_MEMBER_6A, 22 +.set CYDEV_CHIP_MEMBER_FM3, 26 +.set CYDEV_CHIP_MEMBER_FM4, 27 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 23 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 24 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 25 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED @@ -2681,7 +2662,6 @@ .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 .set CYDEV_CHIP_REVISION_4A_ES0, 17 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 -.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0 @@ -2700,12 +2680,16 @@ .set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_5A_ES0, 0 .set CYDEV_CHIP_REVISION_5A_ES1, 1 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 .set CYDEV_CHIP_REVISION_5B_ES0, 0 .set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_6A_NO_UDB, 0 +.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0 @@ -2737,7 +2721,7 @@ .set CYDEV_ECC_ENABLE, 0 .set CYDEV_HEAP_SIZE, 0x0400 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 -.set CYDEV_INTR_RISING, 0x0000007E +.set CYDEV_INTR_RISING, 0x0000007F .set CYDEV_IS_EXPORTING_CODE, 0 .set CYDEV_IS_IMPORTING_CODE, 0 .set CYDEV_PROJ_TYPE, 2 diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 18c7df3..d5db1af 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -1,8 +1,51 @@ +; +; File Name: cyfitteriar.inc +; +; PSoC Creator 4.1 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + #ifndef INCLUDED_CYFITTERIAR_INC #define INCLUDED_CYFITTERIAR_INC INCLUDE cydeviceiar.inc INCLUDE cydeviceiar_trm.inc +/* Debug_Timer_Interrupt */ +Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x01 +Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* Debug_Timer_TimerHW */ +Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 +Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 +Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 +Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 +Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 +Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 +Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 + /* LED1 */ LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE0 LED1__0__MASK EQU 0x01 @@ -41,438 +84,86 @@ LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ LED1__SLW EQU CYREG_PRT12_SLW -/* SD_CS */ -SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 -SD_CS__0__MASK EQU 0x20 -SD_CS__0__PC EQU CYREG_PRT3_PC5 -SD_CS__0__PORT EQU 3 -SD_CS__0__SHIFT EQU 5 -SD_CS__AG EQU CYREG_PRT3_AG -SD_CS__AMUX EQU CYREG_PRT3_AMUX -SD_CS__BIE EQU CYREG_PRT3_BIE -SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CS__BYP EQU CYREG_PRT3_BYP -SD_CS__CTL EQU CYREG_PRT3_CTL -SD_CS__DM0 EQU CYREG_PRT3_DM0 -SD_CS__DM1 EQU CYREG_PRT3_DM1 -SD_CS__DM2 EQU CYREG_PRT3_DM2 -SD_CS__DR EQU CYREG_PRT3_DR -SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CS__MASK EQU 0x20 -SD_CS__PORT EQU 3 -SD_CS__PRT EQU CYREG_PRT3_PRT -SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CS__PS EQU CYREG_PRT3_PS -SD_CS__SHIFT EQU 5 -SD_CS__SLW EQU CYREG_PRT3_SLW +/* SCSI_CLK */ +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 -/* USBFS_arb_int */ -USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_arb_int__INTC_MASK EQU 0x400000 -USBFS_arb_int__INTC_NUMBER EQU 22 -USBFS_arb_int__INTC_PRIOR_NUM EQU 6 -USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 -USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* SCSI_CTL_PHASE */ +SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK -/* USBFS_bus_reset */ -USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_bus_reset__INTC_MASK EQU 0x800000 -USBFS_bus_reset__INTC_NUMBER EQU 23 -USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 -USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 -USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* SCSI_Filtered */ +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK +SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST -/* USBFS_Dm */ -USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 -USBFS_Dm__0__MASK EQU 0x80 -USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 -USBFS_Dm__0__PORT EQU 15 -USBFS_Dm__0__SHIFT EQU 7 -USBFS_Dm__AG EQU CYREG_PRT15_AG -USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dm__BIE EQU CYREG_PRT15_BIE -USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dm__BYP EQU CYREG_PRT15_BYP -USBFS_Dm__CTL EQU CYREG_PRT15_CTL -USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dm__DR EQU CYREG_PRT15_DR -USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dm__MASK EQU 0x80 -USBFS_Dm__PORT EQU 15 -USBFS_Dm__PRT EQU CYREG_PRT15_PRT -USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dm__PS EQU CYREG_PRT15_PS -USBFS_Dm__SHIFT EQU 7 -USBFS_Dm__SLW EQU CYREG_PRT15_SLW - -/* USBFS_Dp */ -USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 -USBFS_Dp__0__MASK EQU 0x40 -USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 -USBFS_Dp__0__PORT EQU 15 -USBFS_Dp__0__SHIFT EQU 6 -USBFS_Dp__AG EQU CYREG_PRT15_AG -USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dp__BIE EQU CYREG_PRT15_BIE -USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dp__BYP EQU CYREG_PRT15_BYP -USBFS_Dp__CTL EQU CYREG_PRT15_CTL -USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dp__DR EQU CYREG_PRT15_DR -USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT -USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dp__MASK EQU 0x40 -USBFS_Dp__PORT EQU 15 -USBFS_Dp__PRT EQU CYREG_PRT15_PRT -USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dp__PS EQU CYREG_PRT15_PS -USBFS_Dp__SHIFT EQU 6 -USBFS_Dp__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 - -/* USBFS_dp_int */ -USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_dp_int__INTC_MASK EQU 0x1000 -USBFS_dp_int__INTC_NUMBER EQU 12 -USBFS_dp_int__INTC_PRIOR_NUM EQU 7 -USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 -USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_0 */ -USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_0__INTC_MASK EQU 0x1000000 -USBFS_ep_0__INTC_NUMBER EQU 24 -USBFS_ep_0__INTC_PRIOR_NUM EQU 7 -USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 -USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_1 */ -USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 -USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 -USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_2 */ -USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 -USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 -USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_3 */ -USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 -USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 -USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_4 */ -USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 -USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 -USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_sof_int */ -USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_sof_int__INTC_MASK EQU 0x200000 -USBFS_sof_int__INTC_NUMBER EQU 21 -USBFS_sof_int__INTC_PRIOR_NUM EQU 7 -USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 -USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_USB */ -USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG -USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG -USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN -USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR -USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG -USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN -USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR -USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG -USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN -USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR -USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG -USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN -USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR -USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG -USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN -USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR -USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG -USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN -USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR -USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG -USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN -USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR -USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG -USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN -USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR -USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN -USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR -USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR -USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA -USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB -USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA -USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB -USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR -USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA -USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB -USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA -USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB -USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR -USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA -USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB -USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA -USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB -USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR -USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA -USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB -USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA -USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB -USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR -USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA -USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB -USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA -USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB -USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR -USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA -USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB -USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA -USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB -USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR -USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA -USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB -USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA -USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB -USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR -USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA -USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB -USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA -USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB -USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE -USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT -USBFS_USB__CR0 EQU CYREG_USB_CR0 -USBFS_USB__CR1 EQU CYREG_USB_CR1 -USBFS_USB__CWA EQU CYREG_USB_CWA -USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB -USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES -USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB -USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG -USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE -USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE -USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT -USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR -USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 -USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 -USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 -USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 -USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 -USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 -USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 -USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 -USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE -USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 -USBFS_USB__PM_ACT_MSK EQU 0x01 -USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 -USBFS_USB__PM_STBY_MSK EQU 0x01 -USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN -USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR -USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 -USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 -USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 -USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 -USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 -USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 -USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 -USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 -USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 -USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 -USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 -USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 -USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 -USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 -USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 -USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 -USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 -USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 -USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 -USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 -USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 -USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 -USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 -USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 -USBFS_USB__SOF0 EQU CYREG_USB_SOF0 -USBFS_USB__SOF1 EQU CYREG_USB_SOF1 -USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 -USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 - -/* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST -SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_RxStsReg__4__POS EQU 4 -SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 -SDCard_BSPIM_RxStsReg__5__POS EQU 5 -SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 -SDCard_BSPIM_RxStsReg__6__POS EQU 6 -SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 -SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 -SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 -SDCard_BSPIM_TxStsReg__2__POS EQU 2 -SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 -SDCard_BSPIM_TxStsReg__3__POS EQU 3 -SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_TxStsReg__4__POS EQU 4 -SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST - -/* SD_SCK */ -SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 -SD_SCK__0__MASK EQU 0x08 -SD_SCK__0__PC EQU CYREG_PRT3_PC3 -SD_SCK__0__PORT EQU 3 -SD_SCK__0__SHIFT EQU 3 -SD_SCK__AG EQU CYREG_PRT3_AG -SD_SCK__AMUX EQU CYREG_PRT3_AMUX -SD_SCK__BIE EQU CYREG_PRT3_BIE -SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_SCK__BYP EQU CYREG_PRT3_BYP -SD_SCK__CTL EQU CYREG_PRT3_CTL -SD_SCK__DM0 EQU CYREG_PRT3_DM0 -SD_SCK__DM1 EQU CYREG_PRT3_DM1 -SD_SCK__DM2 EQU CYREG_PRT3_DM2 -SD_SCK__DR EQU CYREG_PRT3_DR -SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_SCK__MASK EQU 0x08 -SD_SCK__PORT EQU 3 -SD_SCK__PRT EQU CYREG_PRT3_PRT -SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_SCK__PS EQU CYREG_PRT3_PS -SD_SCK__SHIFT EQU 3 -SD_SCK__SLW EQU CYREG_PRT3_SLW +/* SCSI_Glitch_Ctl */ +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK /* SCSI_In */ SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1 @@ -512,8 +203,6 @@ SCSI_In__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT SCSI_In__PS EQU CYREG_PRT6_PS SCSI_In__SHIFT EQU 1 SCSI_In__SLW EQU CYREG_PRT6_SLW - -/* SCSI_In_DBx */ SCSI_In_DBx__0__AG EQU CYREG_PRT6_AG SCSI_In_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_In_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -961,118 +650,287 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT6_PS SCSI_In_DBx__DB7__SHIFT EQU 3 SCSI_In_DBx__DB7__SLW EQU CYREG_PRT6_SLW -/* SD_MISO */ -SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 -SD_MISO__0__MASK EQU 0x04 -SD_MISO__0__PC EQU CYREG_PRT3_PC2 -SD_MISO__0__PORT EQU 3 -SD_MISO__0__SHIFT EQU 2 -SD_MISO__AG EQU CYREG_PRT3_AG -SD_MISO__AMUX EQU CYREG_PRT3_AMUX -SD_MISO__BIE EQU CYREG_PRT3_BIE -SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MISO__BYP EQU CYREG_PRT3_BYP -SD_MISO__CTL EQU CYREG_PRT3_CTL -SD_MISO__DM0 EQU CYREG_PRT3_DM0 -SD_MISO__DM1 EQU CYREG_PRT3_DM1 -SD_MISO__DM2 EQU CYREG_PRT3_DM2 -SD_MISO__DR EQU CYREG_PRT3_DR -SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MISO__MASK EQU 0x04 -SD_MISO__PORT EQU 3 -SD_MISO__PRT EQU CYREG_PRT3_PRT -SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MISO__PS EQU CYREG_PRT3_PS -SD_MISO__SHIFT EQU 2 -SD_MISO__SLW EQU CYREG_PRT3_SLW - -/* SD_MOSI */ -SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 -SD_MOSI__0__MASK EQU 0x10 -SD_MOSI__0__PC EQU CYREG_PRT3_PC4 -SD_MOSI__0__PORT EQU 3 -SD_MOSI__0__SHIFT EQU 4 -SD_MOSI__AG EQU CYREG_PRT3_AG -SD_MOSI__AMUX EQU CYREG_PRT3_AMUX -SD_MOSI__BIE EQU CYREG_PRT3_BIE -SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MOSI__BYP EQU CYREG_PRT3_BYP -SD_MOSI__CTL EQU CYREG_PRT3_CTL -SD_MOSI__DM0 EQU CYREG_PRT3_DM0 -SD_MOSI__DM1 EQU CYREG_PRT3_DM1 -SD_MOSI__DM2 EQU CYREG_PRT3_DM2 -SD_MOSI__DR EQU CYREG_PRT3_DR -SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MOSI__MASK EQU 0x10 -SD_MOSI__PORT EQU 3 -SD_MOSI__PRT EQU CYREG_PRT3_PRT -SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MOSI__PS EQU CYREG_PRT3_PS -SD_MOSI__SHIFT EQU 4 -SD_MOSI__SLW EQU CYREG_PRT3_SLW - -/* TERM_EN */ -TERM_EN__0__INTTYPE EQU CYREG_PICU15_INTTYPE3 -TERM_EN__0__MASK EQU 0x08 -TERM_EN__0__PC EQU CYREG_IO_PC_PRT15_PC3 -TERM_EN__0__PORT EQU 15 -TERM_EN__0__SHIFT EQU 3 -TERM_EN__AG EQU CYREG_PRT15_AG -TERM_EN__AMUX EQU CYREG_PRT15_AMUX -TERM_EN__BIE EQU CYREG_PRT15_BIE -TERM_EN__BIT_MASK EQU CYREG_PRT15_BIT_MASK -TERM_EN__BYP EQU CYREG_PRT15_BYP -TERM_EN__CTL EQU CYREG_PRT15_CTL -TERM_EN__DM0 EQU CYREG_PRT15_DM0 -TERM_EN__DM1 EQU CYREG_PRT15_DM1 -TERM_EN__DM2 EQU CYREG_PRT15_DM2 -TERM_EN__DR EQU CYREG_PRT15_DR -TERM_EN__INP_DIS EQU CYREG_PRT15_INP_DIS -TERM_EN__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -TERM_EN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -TERM_EN__LCD_EN EQU CYREG_PRT15_LCD_EN -TERM_EN__MASK EQU 0x08 -TERM_EN__PORT EQU 15 -TERM_EN__PRT EQU CYREG_PRT15_PRT -TERM_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -TERM_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -TERM_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -TERM_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -TERM_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -TERM_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -TERM_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -TERM_EN__PS EQU CYREG_PRT15_PS -TERM_EN__SHIFT EQU 3 -TERM_EN__SLW EQU CYREG_PRT15_SLW - -/* SCSI_CLK */ -SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 -SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 -SCSI_CLK__INDEX EQU 0x01 -SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SCSI_CLK__PM_ACT_MSK EQU 0x02 -SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SCSI_CLK__PM_STBY_MSK EQU 0x02 +/* SCSI_Noise */ +SCSI_Noise__0__AG EQU CYREG_PRT4_AG +SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__0__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__0__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__0__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT4_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__0__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__0__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__0__MASK EQU 0x80 +SCSI_Noise__0__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__0__PORT EQU 4 +SCSI_Noise__0__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT4_PS +SCSI_Noise__0__SHIFT EQU 7 +SCSI_Noise__0__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__1__AG EQU CYREG_PRT4_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT4_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__1__INTTYPE EQU CYREG_PICU4_INTTYPE5 +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__1__MASK EQU 0x20 +SCSI_Noise__1__PC EQU CYREG_PRT4_PC5 +SCSI_Noise__1__PORT EQU 4 +SCSI_Noise__1__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT4_PS +SCSI_Noise__1__SHIFT EQU 5 +SCSI_Noise__1__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__2__AG EQU CYREG_PRT0_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT0_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__2__INTTYPE EQU CYREG_PICU0_INTTYPE2 +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__2__MASK EQU 0x04 +SCSI_Noise__2__PC EQU CYREG_PRT0_PC2 +SCSI_Noise__2__PORT EQU 0 +SCSI_Noise__2__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT0_PS +SCSI_Noise__2__SHIFT EQU 2 +SCSI_Noise__2__SLW EQU CYREG_PRT0_SLW +SCSI_Noise__3__AG EQU CYREG_PRT0_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT0_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__3__INTTYPE EQU CYREG_PICU0_INTTYPE6 +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__3__MASK EQU 0x40 +SCSI_Noise__3__PC EQU CYREG_PRT0_PC6 +SCSI_Noise__3__PORT EQU 0 +SCSI_Noise__3__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT0_PS +SCSI_Noise__3__SHIFT EQU 6 +SCSI_Noise__3__SLW EQU CYREG_PRT0_SLW +SCSI_Noise__4__AG EQU CYREG_PRT4_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT4_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__4__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__4__MASK EQU 0x08 +SCSI_Noise__4__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__4__PORT EQU 4 +SCSI_Noise__4__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT4_PS +SCSI_Noise__4__SHIFT EQU 3 +SCSI_Noise__4__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT4_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT4_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x08 +SCSI_Noise__ACK__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__ACK__PORT EQU 4 +SCSI_Noise__ACK__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT4_PS +SCSI_Noise__ACK__SHIFT EQU 3 +SCSI_Noise__ACK__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT4_AG +SCSI_Noise__ATN__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__ATN__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__ATN__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__ATN__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT4_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__ATN__MASK EQU 0x80 +SCSI_Noise__ATN__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__ATN__PORT EQU 4 +SCSI_Noise__ATN__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT4_PS +SCSI_Noise__ATN__SHIFT EQU 7 +SCSI_Noise__ATN__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT4_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT4_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE5 +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x20 +SCSI_Noise__BSY__PC EQU CYREG_PRT4_PC5 +SCSI_Noise__BSY__PORT EQU 4 +SCSI_Noise__BSY__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT4_PS +SCSI_Noise__BSY__SHIFT EQU 5 +SCSI_Noise__BSY__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT0_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT0_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__RST__INTTYPE EQU CYREG_PICU0_INTTYPE6 +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__RST__MASK EQU 0x40 +SCSI_Noise__RST__PC EQU CYREG_PRT0_PC6 +SCSI_Noise__RST__PORT EQU 0 +SCSI_Noise__RST__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT0_PS +SCSI_Noise__RST__SHIFT EQU 6 +SCSI_Noise__RST__SLW EQU CYREG_PRT0_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT0_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT0_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE2 +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x04 +SCSI_Noise__SEL__PC EQU CYREG_PRT0_PC2 +SCSI_Noise__SEL__PORT EQU 0 +SCSI_Noise__SEL__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT0_PS +SCSI_Noise__SEL__SHIFT EQU 2 +SCSI_Noise__SEL__SLW EQU CYREG_PRT0_SLW /* SCSI_Out */ SCSI_Out__0__AG EQU CYREG_PRT6_AG @@ -1521,8 +1379,6 @@ SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT SCSI_Out__SEL__PS EQU CYREG_PRT0_PS SCSI_Out__SEL__SHIFT EQU 3 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW - -/* SCSI_Out_Bits */ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 @@ -1557,8 +1413,6 @@ SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK - -/* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL @@ -1579,8 +1433,6 @@ SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK - -/* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -2028,6 +1880,272 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS SCSI_Out_DBx__DB7__SHIFT EQU 5 SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW +/* SCSI_Parity_Error */ +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK +SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST + +/* SCSI_RST_ISR */ +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x02 +SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_RX_DMA */ +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SDCard_BSPIM */ +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST + +/* SD_CS */ +SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SD_CS__0__MASK EQU 0x20 +SD_CS__0__PC EQU CYREG_PRT3_PC5 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 5 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x20 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 5 +SD_CS__SLW EQU CYREG_PRT3_SLW + +/* SD_Data_Clk */ +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 + +/* SD_MISO */ +SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_MISO__0__MASK EQU 0x04 +SD_MISO__0__PC EQU CYREG_PRT3_PC2 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 2 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x04 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 2 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +/* SD_MOSI */ +SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SD_MOSI__0__MASK EQU 0x10 +SD_MOSI__0__PC EQU CYREG_PRT3_PC4 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 4 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x10 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 4 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + /* SD_RX_DMA */ SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 @@ -2039,8 +2157,6 @@ SD_RX_DMA__TERMOUT0_EN EQU 1 SD_RX_DMA__TERMOUT0_SEL EQU 2 SD_RX_DMA__TERMOUT1_EN EQU 0 SD_RX_DMA__TERMOUT1_SEL EQU 0 - -/* SD_RX_DMA_COMPLETE */ SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 @@ -2050,6 +2166,40 @@ SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* SD_SCK */ +SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_SCK__0__MASK EQU 0x08 +SD_SCK__0__PC EQU CYREG_PRT3_PC3 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 3 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x08 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 3 +SD_SCK__SLW EQU CYREG_PRT3_SLW + /* SD_TX_DMA */ SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_TX_DMA__DRQ_NUMBER EQU 3 @@ -2061,8 +2211,6 @@ SD_TX_DMA__TERMOUT0_EN EQU 1 SD_TX_DMA__TERMOUT0_SEL EQU 3 SD_TX_DMA__TERMOUT1_EN EQU 0 SD_TX_DMA__TERMOUT1_SEL EQU 0 - -/* SD_TX_DMA_COMPLETE */ SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 @@ -2072,287 +2220,303 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -/* SCSI_Noise */ -SCSI_Noise__0__AG EQU CYREG_PRT4_AG -SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__0__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__0__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__0__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__0__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__0__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__0__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__0__DR EQU CYREG_PRT4_DR -SCSI_Noise__0__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__0__INTTYPE EQU CYREG_PICU4_INTTYPE7 -SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__0__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__0__MASK EQU 0x80 -SCSI_Noise__0__PC EQU CYREG_PRT4_PC7 -SCSI_Noise__0__PORT EQU 4 -SCSI_Noise__0__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__0__PS EQU CYREG_PRT4_PS -SCSI_Noise__0__SHIFT EQU 7 -SCSI_Noise__0__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__1__AG EQU CYREG_PRT4_AG -SCSI_Noise__1__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__1__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__1__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__1__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__1__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__1__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__1__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__1__DR EQU CYREG_PRT4_DR -SCSI_Noise__1__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__1__INTTYPE EQU CYREG_PICU4_INTTYPE5 -SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__1__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__1__MASK EQU 0x20 -SCSI_Noise__1__PC EQU CYREG_PRT4_PC5 -SCSI_Noise__1__PORT EQU 4 -SCSI_Noise__1__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__1__PS EQU CYREG_PRT4_PS -SCSI_Noise__1__SHIFT EQU 5 -SCSI_Noise__1__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__2__AG EQU CYREG_PRT0_AG -SCSI_Noise__2__AMUX EQU CYREG_PRT0_AMUX -SCSI_Noise__2__BIE EQU CYREG_PRT0_BIE -SCSI_Noise__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Noise__2__BYP EQU CYREG_PRT0_BYP -SCSI_Noise__2__CTL EQU CYREG_PRT0_CTL -SCSI_Noise__2__DM0 EQU CYREG_PRT0_DM0 -SCSI_Noise__2__DM1 EQU CYREG_PRT0_DM1 -SCSI_Noise__2__DM2 EQU CYREG_PRT0_DM2 -SCSI_Noise__2__DR EQU CYREG_PRT0_DR -SCSI_Noise__2__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Noise__2__INTTYPE EQU CYREG_PICU0_INTTYPE2 -SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Noise__2__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Noise__2__MASK EQU 0x04 -SCSI_Noise__2__PC EQU CYREG_PRT0_PC2 -SCSI_Noise__2__PORT EQU 0 -SCSI_Noise__2__PRT EQU CYREG_PRT0_PRT -SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Noise__2__PS EQU CYREG_PRT0_PS -SCSI_Noise__2__SHIFT EQU 2 -SCSI_Noise__2__SLW EQU CYREG_PRT0_SLW -SCSI_Noise__3__AG EQU CYREG_PRT0_AG -SCSI_Noise__3__AMUX EQU CYREG_PRT0_AMUX -SCSI_Noise__3__BIE EQU CYREG_PRT0_BIE -SCSI_Noise__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Noise__3__BYP EQU CYREG_PRT0_BYP -SCSI_Noise__3__CTL EQU CYREG_PRT0_CTL -SCSI_Noise__3__DM0 EQU CYREG_PRT0_DM0 -SCSI_Noise__3__DM1 EQU CYREG_PRT0_DM1 -SCSI_Noise__3__DM2 EQU CYREG_PRT0_DM2 -SCSI_Noise__3__DR EQU CYREG_PRT0_DR -SCSI_Noise__3__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Noise__3__INTTYPE EQU CYREG_PICU0_INTTYPE6 -SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Noise__3__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Noise__3__MASK EQU 0x40 -SCSI_Noise__3__PC EQU CYREG_PRT0_PC6 -SCSI_Noise__3__PORT EQU 0 -SCSI_Noise__3__PRT EQU CYREG_PRT0_PRT -SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Noise__3__PS EQU CYREG_PRT0_PS -SCSI_Noise__3__SHIFT EQU 6 -SCSI_Noise__3__SLW EQU CYREG_PRT0_SLW -SCSI_Noise__4__AG EQU CYREG_PRT4_AG -SCSI_Noise__4__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__4__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__4__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__4__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__4__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__4__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__4__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__4__DR EQU CYREG_PRT4_DR -SCSI_Noise__4__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__4__INTTYPE EQU CYREG_PICU4_INTTYPE3 -SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__4__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__4__MASK EQU 0x08 -SCSI_Noise__4__PC EQU CYREG_PRT4_PC3 -SCSI_Noise__4__PORT EQU 4 -SCSI_Noise__4__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__4__PS EQU CYREG_PRT4_PS -SCSI_Noise__4__SHIFT EQU 3 -SCSI_Noise__4__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__ACK__AG EQU CYREG_PRT4_AG -SCSI_Noise__ACK__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__ACK__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__ACK__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__ACK__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__ACK__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__ACK__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__ACK__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__ACK__DR EQU CYREG_PRT4_DR -SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU4_INTTYPE3 -SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__ACK__MASK EQU 0x08 -SCSI_Noise__ACK__PC EQU CYREG_PRT4_PC3 -SCSI_Noise__ACK__PORT EQU 4 -SCSI_Noise__ACK__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__ACK__PS EQU CYREG_PRT4_PS -SCSI_Noise__ACK__SHIFT EQU 3 -SCSI_Noise__ACK__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__ATN__AG EQU CYREG_PRT4_AG -SCSI_Noise__ATN__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__ATN__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__ATN__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__ATN__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__ATN__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__ATN__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__ATN__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__ATN__DR EQU CYREG_PRT4_DR -SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE7 -SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__ATN__MASK EQU 0x80 -SCSI_Noise__ATN__PC EQU CYREG_PRT4_PC7 -SCSI_Noise__ATN__PORT EQU 4 -SCSI_Noise__ATN__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__ATN__PS EQU CYREG_PRT4_PS -SCSI_Noise__ATN__SHIFT EQU 7 -SCSI_Noise__ATN__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__BSY__AG EQU CYREG_PRT4_AG -SCSI_Noise__BSY__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__BSY__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__BSY__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__BSY__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__BSY__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__BSY__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__BSY__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__BSY__DR EQU CYREG_PRT4_DR -SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE5 -SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__BSY__MASK EQU 0x20 -SCSI_Noise__BSY__PC EQU CYREG_PRT4_PC5 -SCSI_Noise__BSY__PORT EQU 4 -SCSI_Noise__BSY__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__BSY__PS EQU CYREG_PRT4_PS -SCSI_Noise__BSY__SHIFT EQU 5 -SCSI_Noise__BSY__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__RST__AG EQU CYREG_PRT0_AG -SCSI_Noise__RST__AMUX EQU CYREG_PRT0_AMUX -SCSI_Noise__RST__BIE EQU CYREG_PRT0_BIE -SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Noise__RST__BYP EQU CYREG_PRT0_BYP -SCSI_Noise__RST__CTL EQU CYREG_PRT0_CTL -SCSI_Noise__RST__DM0 EQU CYREG_PRT0_DM0 -SCSI_Noise__RST__DM1 EQU CYREG_PRT0_DM1 -SCSI_Noise__RST__DM2 EQU CYREG_PRT0_DM2 -SCSI_Noise__RST__DR EQU CYREG_PRT0_DR -SCSI_Noise__RST__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Noise__RST__INTTYPE EQU CYREG_PICU0_INTTYPE6 -SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Noise__RST__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Noise__RST__MASK EQU 0x40 -SCSI_Noise__RST__PC EQU CYREG_PRT0_PC6 -SCSI_Noise__RST__PORT EQU 0 -SCSI_Noise__RST__PRT EQU CYREG_PRT0_PRT -SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Noise__RST__PS EQU CYREG_PRT0_PS -SCSI_Noise__RST__SHIFT EQU 6 -SCSI_Noise__RST__SLW EQU CYREG_PRT0_SLW -SCSI_Noise__SEL__AG EQU CYREG_PRT0_AG -SCSI_Noise__SEL__AMUX EQU CYREG_PRT0_AMUX -SCSI_Noise__SEL__BIE EQU CYREG_PRT0_BIE -SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Noise__SEL__BYP EQU CYREG_PRT0_BYP -SCSI_Noise__SEL__CTL EQU CYREG_PRT0_CTL -SCSI_Noise__SEL__DM0 EQU CYREG_PRT0_DM0 -SCSI_Noise__SEL__DM1 EQU CYREG_PRT0_DM1 -SCSI_Noise__SEL__DM2 EQU CYREG_PRT0_DM2 -SCSI_Noise__SEL__DR EQU CYREG_PRT0_DR -SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE2 -SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Noise__SEL__MASK EQU 0x04 -SCSI_Noise__SEL__PC EQU CYREG_PRT0_PC2 -SCSI_Noise__SEL__PORT EQU 0 -SCSI_Noise__SEL__PRT EQU CYREG_PRT0_PRT -SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Noise__SEL__PS EQU CYREG_PRT0_PS -SCSI_Noise__SEL__SHIFT EQU 2 -SCSI_Noise__SEL__SLW EQU CYREG_PRT0_SLW +/* TERM_EN */ +TERM_EN__0__INTTYPE EQU CYREG_PICU15_INTTYPE3 +TERM_EN__0__MASK EQU 0x08 +TERM_EN__0__PC EQU CYREG_IO_PC_PRT15_PC3 +TERM_EN__0__PORT EQU 15 +TERM_EN__0__SHIFT EQU 3 +TERM_EN__AG EQU CYREG_PRT15_AG +TERM_EN__AMUX EQU CYREG_PRT15_AMUX +TERM_EN__BIE EQU CYREG_PRT15_BIE +TERM_EN__BIT_MASK EQU CYREG_PRT15_BIT_MASK +TERM_EN__BYP EQU CYREG_PRT15_BYP +TERM_EN__CTL EQU CYREG_PRT15_CTL +TERM_EN__DM0 EQU CYREG_PRT15_DM0 +TERM_EN__DM1 EQU CYREG_PRT15_DM1 +TERM_EN__DM2 EQU CYREG_PRT15_DM2 +TERM_EN__DR EQU CYREG_PRT15_DR +TERM_EN__INP_DIS EQU CYREG_PRT15_INP_DIS +TERM_EN__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +TERM_EN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +TERM_EN__LCD_EN EQU CYREG_PRT15_LCD_EN +TERM_EN__MASK EQU 0x08 +TERM_EN__PORT EQU 15 +TERM_EN__PRT EQU CYREG_PRT15_PRT +TERM_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +TERM_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +TERM_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +TERM_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +TERM_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +TERM_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +TERM_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +TERM_EN__PS EQU CYREG_PRT15_PS +TERM_EN__SHIFT EQU 3 +TERM_EN__SLW EQU CYREG_PRT15_SLW + +/* USBFS */ +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 6 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_PRIOR_NUM EQU 7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_PRIOR_NUM EQU 7 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 /* scsiTarget */ scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 @@ -2415,89 +2579,6 @@ scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST -/* Debug_Timer_Interrupt */ -Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -Debug_Timer_Interrupt__INTC_MASK EQU 0x02 -Debug_Timer_Interrupt__INTC_NUMBER EQU 1 -Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 -Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 -Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 -Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 -Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 -Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 -Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 -Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 -Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 -Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 -Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 -Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 -Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 -Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 -Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 -Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 -Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 -Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 - -/* SCSI_RX_DMA */ -SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 -SCSI_RX_DMA__NUMBEROF_TDS EQU 0 -SCSI_RX_DMA__PRIORITY EQU 2 -SCSI_RX_DMA__TERMIN_EN EQU 0 -SCSI_RX_DMA__TERMIN_SEL EQU 0 -SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 -SCSI_RX_DMA__TERMOUT1_EN EQU 0 -SCSI_RX_DMA__TERMOUT1_SEL EQU 0 - -/* SCSI_RX_DMA_COMPLETE */ -SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 -SCSI_TX_DMA__NUMBEROF_TDS EQU 0 -SCSI_TX_DMA__PRIORITY EQU 2 -SCSI_TX_DMA__TERMIN_EN EQU 0 -SCSI_TX_DMA__TERMIN_SEL EQU 0 -SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 -SCSI_TX_DMA__TERMOUT1_EN EQU 0 -SCSI_TX_DMA__TERMOUT1_SEL EQU 0 - -/* SCSI_TX_DMA_COMPLETE */ -SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 -SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SD_Data_Clk */ -SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 -SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 -SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 -SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Data_Clk__INDEX EQU 0x00 -SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Data_Clk__PM_ACT_MSK EQU 0x01 -SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Data_Clk__PM_STBY_MSK EQU 0x01 - /* timer_clock */ timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 @@ -2509,154 +2590,53 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 -/* SCSI_RST_ISR */ -SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x04 -SCSI_RST_ISR__INTC_NUMBER EQU 2 -SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 -SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 -SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 -SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_Filtered */ -SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Filtered_sts_sts_reg__0__POS EQU 0 -SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 -SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST -SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 -SCSI_Filtered_sts_sts_reg__2__POS EQU 2 -SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 -SCSI_Filtered_sts_sts_reg__3__POS EQU 3 -SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 -SCSI_Filtered_sts_sts_reg__4__POS EQU 4 -SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK -SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST - -/* SCSI_CTL_PHASE */ -SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 -SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK - -/* SCSI_Glitch_Ctl */ -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK - -/* SCSI_Parity_Error */ -SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST -SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK -SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST - /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 12 -CYDEV_CHIP_DIE_PSOC5LP EQU 19 -CYDEV_CHIP_DIE_PSOC5TM EQU 20 -CYDEV_CHIP_DIE_TMA4 EQU 2 +CYDEV_CHIP_DIE_PSOC4A EQU 16 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 CYDEV_CHIP_DIE_UNKNOWN EQU 0 -CYDEV_CHIP_FAMILY_FM0P EQU 4 -CYDEV_CHIP_FAMILY_FM3 EQU 5 -CYDEV_CHIP_FAMILY_FM4 EQU 6 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 CYDEV_CHIP_FAMILY_PSOC3 EQU 1 CYDEV_CHIP_FAMILY_PSOC4 EQU 2 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 12 -CYDEV_CHIP_MEMBER_4C EQU 18 -CYDEV_CHIP_MEMBER_4D EQU 8 -CYDEV_CHIP_MEMBER_4E EQU 4 -CYDEV_CHIP_MEMBER_4F EQU 13 -CYDEV_CHIP_MEMBER_4G EQU 2 -CYDEV_CHIP_MEMBER_4H EQU 11 -CYDEV_CHIP_MEMBER_4I EQU 17 -CYDEV_CHIP_MEMBER_4J EQU 9 -CYDEV_CHIP_MEMBER_4K EQU 10 -CYDEV_CHIP_MEMBER_4L EQU 16 -CYDEV_CHIP_MEMBER_4M EQU 15 -CYDEV_CHIP_MEMBER_4N EQU 6 -CYDEV_CHIP_MEMBER_4O EQU 5 -CYDEV_CHIP_MEMBER_4P EQU 14 -CYDEV_CHIP_MEMBER_4Q EQU 7 -CYDEV_CHIP_MEMBER_4U EQU 3 -CYDEV_CHIP_MEMBER_5A EQU 20 -CYDEV_CHIP_MEMBER_5B EQU 19 -CYDEV_CHIP_MEMBER_FM3 EQU 24 -CYDEV_CHIP_MEMBER_FM4 EQU 25 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23 +CYDEV_CHIP_MEMBER_4A EQU 16 +CYDEV_CHIP_MEMBER_4D EQU 12 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 17 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 15 +CYDEV_CHIP_MEMBER_4I EQU 21 +CYDEV_CHIP_MEMBER_4J EQU 13 +CYDEV_CHIP_MEMBER_4K EQU 14 +CYDEV_CHIP_MEMBER_4L EQU 20 +CYDEV_CHIP_MEMBER_4M EQU 19 +CYDEV_CHIP_MEMBER_4N EQU 9 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 18 +CYDEV_CHIP_MEMBER_4Q EQU 11 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 10 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 22 +CYDEV_CHIP_MEMBER_FM3 EQU 26 +CYDEV_CHIP_MEMBER_FM4 EQU 27 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -2681,7 +2661,6 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 -CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 @@ -2700,12 +2679,16 @@ CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 @@ -2737,7 +2720,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000007E +CYDEV_INTR_RISING EQU 0x0000007F CYDEV_IS_EXPORTING_CODE EQU 0 CYDEV_IS_IMPORTING_CODE EQU 0 CYDEV_PROJ_TYPE EQU 2 diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index a018968..f8955d9 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -1,8 +1,51 @@ +; +; File Name: cyfitterrv.inc +; +; PSoC Creator 4.1 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC INCLUDED_CYFITTERRV_INC EQU 1 GET cydevicerv.inc GET cydevicerv_trm.inc +; Debug_Timer_Interrupt +Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x01 +Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; Debug_Timer_TimerHW +Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 +Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 +Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 +Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 +Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 +Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 +Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 + ; LED1 LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE0 LED1__0__MASK EQU 0x01 @@ -41,438 +84,86 @@ LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ LED1__SLW EQU CYREG_PRT12_SLW -; SD_CS -SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 -SD_CS__0__MASK EQU 0x20 -SD_CS__0__PC EQU CYREG_PRT3_PC5 -SD_CS__0__PORT EQU 3 -SD_CS__0__SHIFT EQU 5 -SD_CS__AG EQU CYREG_PRT3_AG -SD_CS__AMUX EQU CYREG_PRT3_AMUX -SD_CS__BIE EQU CYREG_PRT3_BIE -SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CS__BYP EQU CYREG_PRT3_BYP -SD_CS__CTL EQU CYREG_PRT3_CTL -SD_CS__DM0 EQU CYREG_PRT3_DM0 -SD_CS__DM1 EQU CYREG_PRT3_DM1 -SD_CS__DM2 EQU CYREG_PRT3_DM2 -SD_CS__DR EQU CYREG_PRT3_DR -SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CS__MASK EQU 0x20 -SD_CS__PORT EQU 3 -SD_CS__PRT EQU CYREG_PRT3_PRT -SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CS__PS EQU CYREG_PRT3_PS -SD_CS__SHIFT EQU 5 -SD_CS__SLW EQU CYREG_PRT3_SLW +; SCSI_CLK +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 -; USBFS_arb_int -USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_arb_int__INTC_MASK EQU 0x400000 -USBFS_arb_int__INTC_NUMBER EQU 22 -USBFS_arb_int__INTC_PRIOR_NUM EQU 6 -USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 -USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; SCSI_CTL_PHASE +SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK -; USBFS_bus_reset -USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_bus_reset__INTC_MASK EQU 0x800000 -USBFS_bus_reset__INTC_NUMBER EQU 23 -USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 -USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 -USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; SCSI_Filtered +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK +SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST -; USBFS_Dm -USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 -USBFS_Dm__0__MASK EQU 0x80 -USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 -USBFS_Dm__0__PORT EQU 15 -USBFS_Dm__0__SHIFT EQU 7 -USBFS_Dm__AG EQU CYREG_PRT15_AG -USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dm__BIE EQU CYREG_PRT15_BIE -USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dm__BYP EQU CYREG_PRT15_BYP -USBFS_Dm__CTL EQU CYREG_PRT15_CTL -USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dm__DR EQU CYREG_PRT15_DR -USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dm__MASK EQU 0x80 -USBFS_Dm__PORT EQU 15 -USBFS_Dm__PRT EQU CYREG_PRT15_PRT -USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dm__PS EQU CYREG_PRT15_PS -USBFS_Dm__SHIFT EQU 7 -USBFS_Dm__SLW EQU CYREG_PRT15_SLW - -; USBFS_Dp -USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 -USBFS_Dp__0__MASK EQU 0x40 -USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 -USBFS_Dp__0__PORT EQU 15 -USBFS_Dp__0__SHIFT EQU 6 -USBFS_Dp__AG EQU CYREG_PRT15_AG -USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dp__BIE EQU CYREG_PRT15_BIE -USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dp__BYP EQU CYREG_PRT15_BYP -USBFS_Dp__CTL EQU CYREG_PRT15_CTL -USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dp__DR EQU CYREG_PRT15_DR -USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT -USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dp__MASK EQU 0x40 -USBFS_Dp__PORT EQU 15 -USBFS_Dp__PRT EQU CYREG_PRT15_PRT -USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dp__PS EQU CYREG_PRT15_PS -USBFS_Dp__SHIFT EQU 6 -USBFS_Dp__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 - -; USBFS_dp_int -USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_dp_int__INTC_MASK EQU 0x1000 -USBFS_dp_int__INTC_NUMBER EQU 12 -USBFS_dp_int__INTC_PRIOR_NUM EQU 7 -USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 -USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_0 -USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_0__INTC_MASK EQU 0x1000000 -USBFS_ep_0__INTC_NUMBER EQU 24 -USBFS_ep_0__INTC_PRIOR_NUM EQU 7 -USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 -USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_1 -USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 -USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 -USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_2 -USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 -USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 -USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_3 -USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 -USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 -USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_4 -USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 -USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 -USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_sof_int -USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_sof_int__INTC_MASK EQU 0x200000 -USBFS_sof_int__INTC_NUMBER EQU 21 -USBFS_sof_int__INTC_PRIOR_NUM EQU 7 -USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 -USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_USB -USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG -USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG -USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN -USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR -USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG -USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN -USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR -USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG -USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN -USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR -USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG -USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN -USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR -USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG -USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN -USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR -USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG -USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN -USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR -USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG -USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN -USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR -USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG -USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN -USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR -USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN -USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR -USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR -USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA -USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB -USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA -USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB -USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR -USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA -USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB -USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA -USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB -USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR -USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA -USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB -USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA -USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB -USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR -USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA -USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB -USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA -USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB -USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR -USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA -USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB -USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA -USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB -USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR -USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA -USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB -USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA -USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB -USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR -USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA -USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB -USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA -USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB -USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR -USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA -USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB -USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA -USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB -USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE -USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT -USBFS_USB__CR0 EQU CYREG_USB_CR0 -USBFS_USB__CR1 EQU CYREG_USB_CR1 -USBFS_USB__CWA EQU CYREG_USB_CWA -USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB -USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES -USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB -USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG -USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE -USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE -USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT -USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR -USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 -USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 -USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 -USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 -USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 -USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 -USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 -USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 -USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE -USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 -USBFS_USB__PM_ACT_MSK EQU 0x01 -USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 -USBFS_USB__PM_STBY_MSK EQU 0x01 -USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN -USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR -USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 -USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 -USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 -USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 -USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 -USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 -USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 -USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 -USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 -USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 -USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 -USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 -USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 -USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 -USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 -USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 -USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 -USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 -USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 -USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 -USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 -USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 -USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 -USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 -USBFS_USB__SOF0 EQU CYREG_USB_SOF0 -USBFS_USB__SOF1 EQU CYREG_USB_SOF1 -USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 -USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 - -; SDCard_BSPIM -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST -SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_RxStsReg__4__POS EQU 4 -SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 -SDCard_BSPIM_RxStsReg__5__POS EQU 5 -SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 -SDCard_BSPIM_RxStsReg__6__POS EQU 6 -SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 -SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 -SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 -SDCard_BSPIM_TxStsReg__2__POS EQU 2 -SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 -SDCard_BSPIM_TxStsReg__3__POS EQU 3 -SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_TxStsReg__4__POS EQU 4 -SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST - -; SD_SCK -SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 -SD_SCK__0__MASK EQU 0x08 -SD_SCK__0__PC EQU CYREG_PRT3_PC3 -SD_SCK__0__PORT EQU 3 -SD_SCK__0__SHIFT EQU 3 -SD_SCK__AG EQU CYREG_PRT3_AG -SD_SCK__AMUX EQU CYREG_PRT3_AMUX -SD_SCK__BIE EQU CYREG_PRT3_BIE -SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_SCK__BYP EQU CYREG_PRT3_BYP -SD_SCK__CTL EQU CYREG_PRT3_CTL -SD_SCK__DM0 EQU CYREG_PRT3_DM0 -SD_SCK__DM1 EQU CYREG_PRT3_DM1 -SD_SCK__DM2 EQU CYREG_PRT3_DM2 -SD_SCK__DR EQU CYREG_PRT3_DR -SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_SCK__MASK EQU 0x08 -SD_SCK__PORT EQU 3 -SD_SCK__PRT EQU CYREG_PRT3_PRT -SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_SCK__PS EQU CYREG_PRT3_PS -SD_SCK__SHIFT EQU 3 -SD_SCK__SLW EQU CYREG_PRT3_SLW +; SCSI_Glitch_Ctl +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK ; SCSI_In SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1 @@ -512,8 +203,6 @@ SCSI_In__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT SCSI_In__PS EQU CYREG_PRT6_PS SCSI_In__SHIFT EQU 1 SCSI_In__SLW EQU CYREG_PRT6_SLW - -; SCSI_In_DBx SCSI_In_DBx__0__AG EQU CYREG_PRT6_AG SCSI_In_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_In_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -961,118 +650,287 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT6_PS SCSI_In_DBx__DB7__SHIFT EQU 3 SCSI_In_DBx__DB7__SLW EQU CYREG_PRT6_SLW -; SD_MISO -SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 -SD_MISO__0__MASK EQU 0x04 -SD_MISO__0__PC EQU CYREG_PRT3_PC2 -SD_MISO__0__PORT EQU 3 -SD_MISO__0__SHIFT EQU 2 -SD_MISO__AG EQU CYREG_PRT3_AG -SD_MISO__AMUX EQU CYREG_PRT3_AMUX -SD_MISO__BIE EQU CYREG_PRT3_BIE -SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MISO__BYP EQU CYREG_PRT3_BYP -SD_MISO__CTL EQU CYREG_PRT3_CTL -SD_MISO__DM0 EQU CYREG_PRT3_DM0 -SD_MISO__DM1 EQU CYREG_PRT3_DM1 -SD_MISO__DM2 EQU CYREG_PRT3_DM2 -SD_MISO__DR EQU CYREG_PRT3_DR -SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MISO__MASK EQU 0x04 -SD_MISO__PORT EQU 3 -SD_MISO__PRT EQU CYREG_PRT3_PRT -SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MISO__PS EQU CYREG_PRT3_PS -SD_MISO__SHIFT EQU 2 -SD_MISO__SLW EQU CYREG_PRT3_SLW - -; SD_MOSI -SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 -SD_MOSI__0__MASK EQU 0x10 -SD_MOSI__0__PC EQU CYREG_PRT3_PC4 -SD_MOSI__0__PORT EQU 3 -SD_MOSI__0__SHIFT EQU 4 -SD_MOSI__AG EQU CYREG_PRT3_AG -SD_MOSI__AMUX EQU CYREG_PRT3_AMUX -SD_MOSI__BIE EQU CYREG_PRT3_BIE -SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MOSI__BYP EQU CYREG_PRT3_BYP -SD_MOSI__CTL EQU CYREG_PRT3_CTL -SD_MOSI__DM0 EQU CYREG_PRT3_DM0 -SD_MOSI__DM1 EQU CYREG_PRT3_DM1 -SD_MOSI__DM2 EQU CYREG_PRT3_DM2 -SD_MOSI__DR EQU CYREG_PRT3_DR -SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MOSI__MASK EQU 0x10 -SD_MOSI__PORT EQU 3 -SD_MOSI__PRT EQU CYREG_PRT3_PRT -SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MOSI__PS EQU CYREG_PRT3_PS -SD_MOSI__SHIFT EQU 4 -SD_MOSI__SLW EQU CYREG_PRT3_SLW - -; TERM_EN -TERM_EN__0__INTTYPE EQU CYREG_PICU15_INTTYPE3 -TERM_EN__0__MASK EQU 0x08 -TERM_EN__0__PC EQU CYREG_IO_PC_PRT15_PC3 -TERM_EN__0__PORT EQU 15 -TERM_EN__0__SHIFT EQU 3 -TERM_EN__AG EQU CYREG_PRT15_AG -TERM_EN__AMUX EQU CYREG_PRT15_AMUX -TERM_EN__BIE EQU CYREG_PRT15_BIE -TERM_EN__BIT_MASK EQU CYREG_PRT15_BIT_MASK -TERM_EN__BYP EQU CYREG_PRT15_BYP -TERM_EN__CTL EQU CYREG_PRT15_CTL -TERM_EN__DM0 EQU CYREG_PRT15_DM0 -TERM_EN__DM1 EQU CYREG_PRT15_DM1 -TERM_EN__DM2 EQU CYREG_PRT15_DM2 -TERM_EN__DR EQU CYREG_PRT15_DR -TERM_EN__INP_DIS EQU CYREG_PRT15_INP_DIS -TERM_EN__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -TERM_EN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -TERM_EN__LCD_EN EQU CYREG_PRT15_LCD_EN -TERM_EN__MASK EQU 0x08 -TERM_EN__PORT EQU 15 -TERM_EN__PRT EQU CYREG_PRT15_PRT -TERM_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -TERM_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -TERM_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -TERM_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -TERM_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -TERM_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -TERM_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -TERM_EN__PS EQU CYREG_PRT15_PS -TERM_EN__SHIFT EQU 3 -TERM_EN__SLW EQU CYREG_PRT15_SLW - -; SCSI_CLK -SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 -SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 -SCSI_CLK__INDEX EQU 0x01 -SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SCSI_CLK__PM_ACT_MSK EQU 0x02 -SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SCSI_CLK__PM_STBY_MSK EQU 0x02 +; SCSI_Noise +SCSI_Noise__0__AG EQU CYREG_PRT4_AG +SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__0__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__0__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__0__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT4_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__0__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__0__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__0__MASK EQU 0x80 +SCSI_Noise__0__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__0__PORT EQU 4 +SCSI_Noise__0__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT4_PS +SCSI_Noise__0__SHIFT EQU 7 +SCSI_Noise__0__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__1__AG EQU CYREG_PRT4_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT4_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__1__INTTYPE EQU CYREG_PICU4_INTTYPE5 +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__1__MASK EQU 0x20 +SCSI_Noise__1__PC EQU CYREG_PRT4_PC5 +SCSI_Noise__1__PORT EQU 4 +SCSI_Noise__1__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT4_PS +SCSI_Noise__1__SHIFT EQU 5 +SCSI_Noise__1__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__2__AG EQU CYREG_PRT0_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT0_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__2__INTTYPE EQU CYREG_PICU0_INTTYPE2 +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__2__MASK EQU 0x04 +SCSI_Noise__2__PC EQU CYREG_PRT0_PC2 +SCSI_Noise__2__PORT EQU 0 +SCSI_Noise__2__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT0_PS +SCSI_Noise__2__SHIFT EQU 2 +SCSI_Noise__2__SLW EQU CYREG_PRT0_SLW +SCSI_Noise__3__AG EQU CYREG_PRT0_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT0_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__3__INTTYPE EQU CYREG_PICU0_INTTYPE6 +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__3__MASK EQU 0x40 +SCSI_Noise__3__PC EQU CYREG_PRT0_PC6 +SCSI_Noise__3__PORT EQU 0 +SCSI_Noise__3__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT0_PS +SCSI_Noise__3__SHIFT EQU 6 +SCSI_Noise__3__SLW EQU CYREG_PRT0_SLW +SCSI_Noise__4__AG EQU CYREG_PRT4_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT4_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__4__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__4__MASK EQU 0x08 +SCSI_Noise__4__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__4__PORT EQU 4 +SCSI_Noise__4__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT4_PS +SCSI_Noise__4__SHIFT EQU 3 +SCSI_Noise__4__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT4_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT4_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x08 +SCSI_Noise__ACK__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__ACK__PORT EQU 4 +SCSI_Noise__ACK__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT4_PS +SCSI_Noise__ACK__SHIFT EQU 3 +SCSI_Noise__ACK__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT4_AG +SCSI_Noise__ATN__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__ATN__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__ATN__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__ATN__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT4_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__ATN__MASK EQU 0x80 +SCSI_Noise__ATN__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__ATN__PORT EQU 4 +SCSI_Noise__ATN__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT4_PS +SCSI_Noise__ATN__SHIFT EQU 7 +SCSI_Noise__ATN__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT4_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT4_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE5 +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x20 +SCSI_Noise__BSY__PC EQU CYREG_PRT4_PC5 +SCSI_Noise__BSY__PORT EQU 4 +SCSI_Noise__BSY__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT4_PS +SCSI_Noise__BSY__SHIFT EQU 5 +SCSI_Noise__BSY__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT0_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT0_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__RST__INTTYPE EQU CYREG_PICU0_INTTYPE6 +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__RST__MASK EQU 0x40 +SCSI_Noise__RST__PC EQU CYREG_PRT0_PC6 +SCSI_Noise__RST__PORT EQU 0 +SCSI_Noise__RST__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT0_PS +SCSI_Noise__RST__SHIFT EQU 6 +SCSI_Noise__RST__SLW EQU CYREG_PRT0_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT0_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT0_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE2 +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x04 +SCSI_Noise__SEL__PC EQU CYREG_PRT0_PC2 +SCSI_Noise__SEL__PORT EQU 0 +SCSI_Noise__SEL__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT0_PS +SCSI_Noise__SEL__SHIFT EQU 2 +SCSI_Noise__SEL__SLW EQU CYREG_PRT0_SLW ; SCSI_Out SCSI_Out__0__AG EQU CYREG_PRT6_AG @@ -1521,8 +1379,6 @@ SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT SCSI_Out__SEL__PS EQU CYREG_PRT0_PS SCSI_Out__SEL__SHIFT EQU 3 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW - -; SCSI_Out_Bits SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 @@ -1557,8 +1413,6 @@ SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK - -; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL @@ -1579,8 +1433,6 @@ SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK - -; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -2028,6 +1880,272 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS SCSI_Out_DBx__DB7__SHIFT EQU 5 SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW +; SCSI_Parity_Error +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK +SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST + +; SCSI_RST_ISR +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x02 +SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_RX_DMA +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_SEL_ISR +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_TX_DMA +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SDCard_BSPIM +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST + +; SD_CS +SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SD_CS__0__MASK EQU 0x20 +SD_CS__0__PC EQU CYREG_PRT3_PC5 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 5 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x20 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 5 +SD_CS__SLW EQU CYREG_PRT3_SLW + +; SD_Data_Clk +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 + +; SD_MISO +SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_MISO__0__MASK EQU 0x04 +SD_MISO__0__PC EQU CYREG_PRT3_PC2 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 2 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x04 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 2 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +; SD_MOSI +SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SD_MOSI__0__MASK EQU 0x10 +SD_MOSI__0__PC EQU CYREG_PRT3_PC4 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 4 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x10 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 4 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + ; SD_RX_DMA SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 @@ -2039,8 +2157,6 @@ SD_RX_DMA__TERMOUT0_EN EQU 1 SD_RX_DMA__TERMOUT0_SEL EQU 2 SD_RX_DMA__TERMOUT1_EN EQU 0 SD_RX_DMA__TERMOUT1_SEL EQU 0 - -; SD_RX_DMA_COMPLETE SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 @@ -2050,6 +2166,40 @@ SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; SD_SCK +SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_SCK__0__MASK EQU 0x08 +SD_SCK__0__PC EQU CYREG_PRT3_PC3 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 3 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x08 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 3 +SD_SCK__SLW EQU CYREG_PRT3_SLW + ; SD_TX_DMA SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_TX_DMA__DRQ_NUMBER EQU 3 @@ -2061,8 +2211,6 @@ SD_TX_DMA__TERMOUT0_EN EQU 1 SD_TX_DMA__TERMOUT0_SEL EQU 3 SD_TX_DMA__TERMOUT1_EN EQU 0 SD_TX_DMA__TERMOUT1_SEL EQU 0 - -; SD_TX_DMA_COMPLETE SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 @@ -2072,287 +2220,303 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -; SCSI_Noise -SCSI_Noise__0__AG EQU CYREG_PRT4_AG -SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__0__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__0__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__0__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__0__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__0__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__0__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__0__DR EQU CYREG_PRT4_DR -SCSI_Noise__0__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__0__INTTYPE EQU CYREG_PICU4_INTTYPE7 -SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__0__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__0__MASK EQU 0x80 -SCSI_Noise__0__PC EQU CYREG_PRT4_PC7 -SCSI_Noise__0__PORT EQU 4 -SCSI_Noise__0__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__0__PS EQU CYREG_PRT4_PS -SCSI_Noise__0__SHIFT EQU 7 -SCSI_Noise__0__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__1__AG EQU CYREG_PRT4_AG -SCSI_Noise__1__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__1__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__1__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__1__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__1__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__1__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__1__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__1__DR EQU CYREG_PRT4_DR -SCSI_Noise__1__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__1__INTTYPE EQU CYREG_PICU4_INTTYPE5 -SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__1__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__1__MASK EQU 0x20 -SCSI_Noise__1__PC EQU CYREG_PRT4_PC5 -SCSI_Noise__1__PORT EQU 4 -SCSI_Noise__1__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__1__PS EQU CYREG_PRT4_PS -SCSI_Noise__1__SHIFT EQU 5 -SCSI_Noise__1__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__2__AG EQU CYREG_PRT0_AG -SCSI_Noise__2__AMUX EQU CYREG_PRT0_AMUX -SCSI_Noise__2__BIE EQU CYREG_PRT0_BIE -SCSI_Noise__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Noise__2__BYP EQU CYREG_PRT0_BYP -SCSI_Noise__2__CTL EQU CYREG_PRT0_CTL -SCSI_Noise__2__DM0 EQU CYREG_PRT0_DM0 -SCSI_Noise__2__DM1 EQU CYREG_PRT0_DM1 -SCSI_Noise__2__DM2 EQU CYREG_PRT0_DM2 -SCSI_Noise__2__DR EQU CYREG_PRT0_DR -SCSI_Noise__2__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Noise__2__INTTYPE EQU CYREG_PICU0_INTTYPE2 -SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Noise__2__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Noise__2__MASK EQU 0x04 -SCSI_Noise__2__PC EQU CYREG_PRT0_PC2 -SCSI_Noise__2__PORT EQU 0 -SCSI_Noise__2__PRT EQU CYREG_PRT0_PRT -SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Noise__2__PS EQU CYREG_PRT0_PS -SCSI_Noise__2__SHIFT EQU 2 -SCSI_Noise__2__SLW EQU CYREG_PRT0_SLW -SCSI_Noise__3__AG EQU CYREG_PRT0_AG -SCSI_Noise__3__AMUX EQU CYREG_PRT0_AMUX -SCSI_Noise__3__BIE EQU CYREG_PRT0_BIE -SCSI_Noise__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Noise__3__BYP EQU CYREG_PRT0_BYP -SCSI_Noise__3__CTL EQU CYREG_PRT0_CTL -SCSI_Noise__3__DM0 EQU CYREG_PRT0_DM0 -SCSI_Noise__3__DM1 EQU CYREG_PRT0_DM1 -SCSI_Noise__3__DM2 EQU CYREG_PRT0_DM2 -SCSI_Noise__3__DR EQU CYREG_PRT0_DR -SCSI_Noise__3__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Noise__3__INTTYPE EQU CYREG_PICU0_INTTYPE6 -SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Noise__3__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Noise__3__MASK EQU 0x40 -SCSI_Noise__3__PC EQU CYREG_PRT0_PC6 -SCSI_Noise__3__PORT EQU 0 -SCSI_Noise__3__PRT EQU CYREG_PRT0_PRT -SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Noise__3__PS EQU CYREG_PRT0_PS -SCSI_Noise__3__SHIFT EQU 6 -SCSI_Noise__3__SLW EQU CYREG_PRT0_SLW -SCSI_Noise__4__AG EQU CYREG_PRT4_AG -SCSI_Noise__4__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__4__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__4__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__4__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__4__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__4__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__4__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__4__DR EQU CYREG_PRT4_DR -SCSI_Noise__4__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__4__INTTYPE EQU CYREG_PICU4_INTTYPE3 -SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__4__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__4__MASK EQU 0x08 -SCSI_Noise__4__PC EQU CYREG_PRT4_PC3 -SCSI_Noise__4__PORT EQU 4 -SCSI_Noise__4__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__4__PS EQU CYREG_PRT4_PS -SCSI_Noise__4__SHIFT EQU 3 -SCSI_Noise__4__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__ACK__AG EQU CYREG_PRT4_AG -SCSI_Noise__ACK__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__ACK__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__ACK__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__ACK__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__ACK__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__ACK__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__ACK__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__ACK__DR EQU CYREG_PRT4_DR -SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU4_INTTYPE3 -SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__ACK__MASK EQU 0x08 -SCSI_Noise__ACK__PC EQU CYREG_PRT4_PC3 -SCSI_Noise__ACK__PORT EQU 4 -SCSI_Noise__ACK__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__ACK__PS EQU CYREG_PRT4_PS -SCSI_Noise__ACK__SHIFT EQU 3 -SCSI_Noise__ACK__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__ATN__AG EQU CYREG_PRT4_AG -SCSI_Noise__ATN__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__ATN__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__ATN__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__ATN__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__ATN__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__ATN__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__ATN__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__ATN__DR EQU CYREG_PRT4_DR -SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE7 -SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__ATN__MASK EQU 0x80 -SCSI_Noise__ATN__PC EQU CYREG_PRT4_PC7 -SCSI_Noise__ATN__PORT EQU 4 -SCSI_Noise__ATN__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__ATN__PS EQU CYREG_PRT4_PS -SCSI_Noise__ATN__SHIFT EQU 7 -SCSI_Noise__ATN__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__BSY__AG EQU CYREG_PRT4_AG -SCSI_Noise__BSY__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__BSY__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__BSY__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__BSY__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__BSY__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__BSY__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__BSY__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__BSY__DR EQU CYREG_PRT4_DR -SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE5 -SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__BSY__MASK EQU 0x20 -SCSI_Noise__BSY__PC EQU CYREG_PRT4_PC5 -SCSI_Noise__BSY__PORT EQU 4 -SCSI_Noise__BSY__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__BSY__PS EQU CYREG_PRT4_PS -SCSI_Noise__BSY__SHIFT EQU 5 -SCSI_Noise__BSY__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__RST__AG EQU CYREG_PRT0_AG -SCSI_Noise__RST__AMUX EQU CYREG_PRT0_AMUX -SCSI_Noise__RST__BIE EQU CYREG_PRT0_BIE -SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Noise__RST__BYP EQU CYREG_PRT0_BYP -SCSI_Noise__RST__CTL EQU CYREG_PRT0_CTL -SCSI_Noise__RST__DM0 EQU CYREG_PRT0_DM0 -SCSI_Noise__RST__DM1 EQU CYREG_PRT0_DM1 -SCSI_Noise__RST__DM2 EQU CYREG_PRT0_DM2 -SCSI_Noise__RST__DR EQU CYREG_PRT0_DR -SCSI_Noise__RST__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Noise__RST__INTTYPE EQU CYREG_PICU0_INTTYPE6 -SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Noise__RST__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Noise__RST__MASK EQU 0x40 -SCSI_Noise__RST__PC EQU CYREG_PRT0_PC6 -SCSI_Noise__RST__PORT EQU 0 -SCSI_Noise__RST__PRT EQU CYREG_PRT0_PRT -SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Noise__RST__PS EQU CYREG_PRT0_PS -SCSI_Noise__RST__SHIFT EQU 6 -SCSI_Noise__RST__SLW EQU CYREG_PRT0_SLW -SCSI_Noise__SEL__AG EQU CYREG_PRT0_AG -SCSI_Noise__SEL__AMUX EQU CYREG_PRT0_AMUX -SCSI_Noise__SEL__BIE EQU CYREG_PRT0_BIE -SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Noise__SEL__BYP EQU CYREG_PRT0_BYP -SCSI_Noise__SEL__CTL EQU CYREG_PRT0_CTL -SCSI_Noise__SEL__DM0 EQU CYREG_PRT0_DM0 -SCSI_Noise__SEL__DM1 EQU CYREG_PRT0_DM1 -SCSI_Noise__SEL__DM2 EQU CYREG_PRT0_DM2 -SCSI_Noise__SEL__DR EQU CYREG_PRT0_DR -SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE2 -SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Noise__SEL__MASK EQU 0x04 -SCSI_Noise__SEL__PC EQU CYREG_PRT0_PC2 -SCSI_Noise__SEL__PORT EQU 0 -SCSI_Noise__SEL__PRT EQU CYREG_PRT0_PRT -SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Noise__SEL__PS EQU CYREG_PRT0_PS -SCSI_Noise__SEL__SHIFT EQU 2 -SCSI_Noise__SEL__SLW EQU CYREG_PRT0_SLW +; TERM_EN +TERM_EN__0__INTTYPE EQU CYREG_PICU15_INTTYPE3 +TERM_EN__0__MASK EQU 0x08 +TERM_EN__0__PC EQU CYREG_IO_PC_PRT15_PC3 +TERM_EN__0__PORT EQU 15 +TERM_EN__0__SHIFT EQU 3 +TERM_EN__AG EQU CYREG_PRT15_AG +TERM_EN__AMUX EQU CYREG_PRT15_AMUX +TERM_EN__BIE EQU CYREG_PRT15_BIE +TERM_EN__BIT_MASK EQU CYREG_PRT15_BIT_MASK +TERM_EN__BYP EQU CYREG_PRT15_BYP +TERM_EN__CTL EQU CYREG_PRT15_CTL +TERM_EN__DM0 EQU CYREG_PRT15_DM0 +TERM_EN__DM1 EQU CYREG_PRT15_DM1 +TERM_EN__DM2 EQU CYREG_PRT15_DM2 +TERM_EN__DR EQU CYREG_PRT15_DR +TERM_EN__INP_DIS EQU CYREG_PRT15_INP_DIS +TERM_EN__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +TERM_EN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +TERM_EN__LCD_EN EQU CYREG_PRT15_LCD_EN +TERM_EN__MASK EQU 0x08 +TERM_EN__PORT EQU 15 +TERM_EN__PRT EQU CYREG_PRT15_PRT +TERM_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +TERM_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +TERM_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +TERM_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +TERM_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +TERM_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +TERM_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +TERM_EN__PS EQU CYREG_PRT15_PS +TERM_EN__SHIFT EQU 3 +TERM_EN__SLW EQU CYREG_PRT15_SLW + +; USBFS +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 6 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_PRIOR_NUM EQU 7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_PRIOR_NUM EQU 7 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 ; scsiTarget scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 @@ -2415,89 +2579,6 @@ scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST -; Debug_Timer_Interrupt -Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -Debug_Timer_Interrupt__INTC_MASK EQU 0x02 -Debug_Timer_Interrupt__INTC_NUMBER EQU 1 -Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 -Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 -Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; Debug_Timer_TimerHW -Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 -Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 -Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 -Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 -Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 -Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 -Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 -Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 -Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 -Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 -Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 -Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 -Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 -Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 -Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 -Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 - -; SCSI_RX_DMA -SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 -SCSI_RX_DMA__NUMBEROF_TDS EQU 0 -SCSI_RX_DMA__PRIORITY EQU 2 -SCSI_RX_DMA__TERMIN_EN EQU 0 -SCSI_RX_DMA__TERMIN_SEL EQU 0 -SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 -SCSI_RX_DMA__TERMOUT1_EN EQU 0 -SCSI_RX_DMA__TERMOUT1_SEL EQU 0 - -; SCSI_RX_DMA_COMPLETE -SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_TX_DMA -SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 -SCSI_TX_DMA__NUMBEROF_TDS EQU 0 -SCSI_TX_DMA__PRIORITY EQU 2 -SCSI_TX_DMA__TERMIN_EN EQU 0 -SCSI_TX_DMA__TERMIN_SEL EQU 0 -SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 -SCSI_TX_DMA__TERMOUT1_EN EQU 0 -SCSI_TX_DMA__TERMOUT1_SEL EQU 0 - -; SCSI_TX_DMA_COMPLETE -SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 -SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SD_Data_Clk -SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 -SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 -SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 -SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Data_Clk__INDEX EQU 0x00 -SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Data_Clk__PM_ACT_MSK EQU 0x01 -SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Data_Clk__PM_STBY_MSK EQU 0x01 - ; timer_clock timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 @@ -2509,154 +2590,53 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 -; SCSI_RST_ISR -SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x04 -SCSI_RST_ISR__INTC_NUMBER EQU 2 -SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 -SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_SEL_ISR -SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 -SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 -SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_Filtered -SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Filtered_sts_sts_reg__0__POS EQU 0 -SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 -SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST -SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 -SCSI_Filtered_sts_sts_reg__2__POS EQU 2 -SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 -SCSI_Filtered_sts_sts_reg__3__POS EQU 3 -SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 -SCSI_Filtered_sts_sts_reg__4__POS EQU 4 -SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK -SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST - -; SCSI_CTL_PHASE -SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 -SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK - -; SCSI_Glitch_Ctl -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK - -; SCSI_Parity_Error -SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST -SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK -SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST - ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 12 -CYDEV_CHIP_DIE_PSOC5LP EQU 19 -CYDEV_CHIP_DIE_PSOC5TM EQU 20 -CYDEV_CHIP_DIE_TMA4 EQU 2 +CYDEV_CHIP_DIE_PSOC4A EQU 16 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 CYDEV_CHIP_DIE_UNKNOWN EQU 0 -CYDEV_CHIP_FAMILY_FM0P EQU 4 -CYDEV_CHIP_FAMILY_FM3 EQU 5 -CYDEV_CHIP_FAMILY_FM4 EQU 6 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 CYDEV_CHIP_FAMILY_PSOC3 EQU 1 CYDEV_CHIP_FAMILY_PSOC4 EQU 2 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 12 -CYDEV_CHIP_MEMBER_4C EQU 18 -CYDEV_CHIP_MEMBER_4D EQU 8 -CYDEV_CHIP_MEMBER_4E EQU 4 -CYDEV_CHIP_MEMBER_4F EQU 13 -CYDEV_CHIP_MEMBER_4G EQU 2 -CYDEV_CHIP_MEMBER_4H EQU 11 -CYDEV_CHIP_MEMBER_4I EQU 17 -CYDEV_CHIP_MEMBER_4J EQU 9 -CYDEV_CHIP_MEMBER_4K EQU 10 -CYDEV_CHIP_MEMBER_4L EQU 16 -CYDEV_CHIP_MEMBER_4M EQU 15 -CYDEV_CHIP_MEMBER_4N EQU 6 -CYDEV_CHIP_MEMBER_4O EQU 5 -CYDEV_CHIP_MEMBER_4P EQU 14 -CYDEV_CHIP_MEMBER_4Q EQU 7 -CYDEV_CHIP_MEMBER_4U EQU 3 -CYDEV_CHIP_MEMBER_5A EQU 20 -CYDEV_CHIP_MEMBER_5B EQU 19 -CYDEV_CHIP_MEMBER_FM3 EQU 24 -CYDEV_CHIP_MEMBER_FM4 EQU 25 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23 +CYDEV_CHIP_MEMBER_4A EQU 16 +CYDEV_CHIP_MEMBER_4D EQU 12 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 17 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 15 +CYDEV_CHIP_MEMBER_4I EQU 21 +CYDEV_CHIP_MEMBER_4J EQU 13 +CYDEV_CHIP_MEMBER_4K EQU 14 +CYDEV_CHIP_MEMBER_4L EQU 20 +CYDEV_CHIP_MEMBER_4M EQU 19 +CYDEV_CHIP_MEMBER_4N EQU 9 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 18 +CYDEV_CHIP_MEMBER_4Q EQU 11 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 10 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 22 +CYDEV_CHIP_MEMBER_FM3 EQU 26 +CYDEV_CHIP_MEMBER_FM4 EQU 27 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -2681,7 +2661,6 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 -CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 @@ -2700,12 +2679,16 @@ CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 @@ -2737,7 +2720,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000007E +CYDEV_INTR_RISING EQU 0x0000007F CYDEV_IS_EXPORTING_CODE EQU 0 CYDEV_IS_IMPORTING_CODE EQU 0 CYDEV_PROJ_TYPE EQU 2 diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c index 25c6a2d..335a950 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -1,21 +1,21 @@ /******************************************************************************* * File Name: cymetadata.c * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * This file defines all extra memory spaces that need to be included. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. ********************************************************************************/ -#include "cytypes.h" +#include "stdint.h" #if defined(__GNUC__) || defined(__ARMCC_VERSION) @@ -28,7 +28,7 @@ CY_LOADABLE_META_SECTION #else #error "Unsupported toolchain" #endif -const uint8 cy_meta_loadable[] = { +const uint8_t cy_meta_loadable[] = { 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x10u, 0x05u, @@ -49,6 +49,6 @@ CY_CONFIG_ECC_SECTION #else #error "Unsupported toolchain" #endif -const uint8 cy_meta_configecc[] = { +const uint8_t cy_meta_configecc[] = { 0x00u }; diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index a26a4fb..66447c7 100755 --- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: project.h * -* PSoC Creator 4.0 Update 1 +* PSoC Creator 4.1 * * Description: * It contains references to all generated header files and should not be modified. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyfit index 47d2aca571bf619d983062342d9f208a2a317ff7..ff02c0cdc5c0d568d992b82ba774e6973ce6e693 100644 GIT binary patch literal 255983 zcmZsB1CVC1wr<ZJX1!?Kfv`-FkIiy{PH;lJCo2 zSy7M%1w#V@0)hfkuVazb+Sh=d!~_ER)&T;7`I{?hV`wC4XJ#)VbeRPkX6o)UGDE(W zL0+@;qcB8cWO6Lyhr9bW3y!3f8+j}nxuzQj^%?W@Ry)U<+0*WYoy$9MG11WcJTV$I z9k?J8c>b)C0+=Wom?9dO?6gIaRI>`w9%yD#_0G&SV5a@s`8q3mZ40Y#oxZt z@a1>yJk94gfUfy=eUWlk%i-;Q?)>36bnk8N6Z3fRerr2pw^mxbb|J%_+T5797JspO zkrtEEn61T|gSRx}Sbeehs#cXfhG4QkrtfYly%sQixulAx%bj{T7NXujXWrPgO1(+! zSnJ!|SZ~9cIZf_*>(P>SIlF`UhP5&mv^>%Z>AdU?Z8i zu;;AQL{Z$Tcxunn#D&tqLyFs5okc)BRbF^$XNg)u_9wvCO=3|pd>zKQzlpJaOX+u6 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- + @@ -1908,7 +1908,7 @@ - + @@ -1934,7 +1934,7 @@ - + @@ -1967,7 +1967,7 @@ - + @@ -1993,7 +1993,7 @@ - + @@ -2019,7 +2019,7 @@ - + @@ -2038,7 +2038,7 @@ - + @@ -2064,7 +2064,7 @@ - + @@ -2090,7 +2090,7 @@ - + @@ -2116,7 +2116,7 @@ - + @@ -2170,7 +2170,7 @@ - + @@ -2219,7 +2219,7 @@ - + @@ -2249,7 +2249,7 @@ - + @@ -2328,10 +2328,10 @@ - - - + + + @@ -2344,6 +2344,15 @@ + + + + + + + + + @@ -2362,10 +2371,10 @@ - - - + + + @@ -2378,6 +2387,15 @@ + + + + + + + + + @@ -2396,10 +2414,10 @@ - - - + + + @@ -2412,6 +2430,15 @@ + + + + + + + + + @@ -2430,10 +2457,10 @@ - - - + + + @@ -2446,6 +2473,15 @@ + + + + + + + + + @@ -2468,10 +2504,10 @@ - - - + + + @@ -2484,6 +2520,15 @@ + + + + + + + + + @@ -2502,10 +2547,10 @@ - - - + + + @@ -2518,6 +2563,15 @@ + + + + + + + + + @@ -2536,10 +2590,10 @@ - - - + + + @@ -2552,6 +2606,15 @@ + + + + + + + + + @@ -2570,10 +2633,10 @@ - - - + + + @@ -2586,14 +2649,31 @@ + + + + + + + + + + + + + + + + + @@ -2604,6 +2684,7 @@ + @@ -2614,6 +2695,7 @@ + @@ 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