From 52828268aead9d072c6ae7352ee9b6fe0366e0a4 Mon Sep 17 00:00:00 2001 From: Michael McMaster Date: Mon, 10 Jun 2019 19:52:37 +1000 Subject: [PATCH] Prepare for release --- CHANGELOG | 5 +- software/SCSI2SD/src/config.c | 2 +- .../Generated_Source/PSoC5/cy_em_eeprom.c | 1416 +++++++ .../Generated_Source/PSoC5/cy_em_eeprom.h | 556 +++ .../Generated_Source/PSoC5/cydevice.h | 4 +- .../Generated_Source/PSoC5/cydevice_trm.h | 4 +- .../Generated_Source/PSoC5/cydevicegnu.inc | 4 +- .../PSoC5/cydevicegnu_trm.inc | 4 +- .../Generated_Source/PSoC5/cydeviceiar.inc | 4 +- .../PSoC5/cydeviceiar_trm.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv_trm.inc | 4 +- .../Generated_Source/PSoC5/cyfitter.h | 2136 +++++------ .../Generated_Source/PSoC5/cyfitter_cfg.c | 13 +- .../Generated_Source/PSoC5/cyfitter_cfg.h | 4 +- .../Generated_Source/PSoC5/cyfittergnu.inc | 2134 +++++------ .../Generated_Source/PSoC5/cyfitteriar.inc | 2134 +++++------ .../Generated_Source/PSoC5/cyfitterrv.inc | 2134 +++++------ .../Generated_Source/PSoC5/cymetadata.c | 4 +- .../Generated_Source/PSoC5/project.h | 5 +- .../SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx | 83 +- .../SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr | 17 +- .../SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 254155 -> 255143 bytes .../SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj | 30 +- software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd | 338 +- .../Generated_Source/PSoC5/cyfitter.h | 232 +- .../Generated_Source/PSoC5/cyfitter_cfg.c | 3274 ++++++++--------- .../Generated_Source/PSoC5/cyfittergnu.inc | 232 +- .../Generated_Source/PSoC5/cyfitteriar.inc | 232 +- .../Generated_Source/PSoC5/cyfitterrv.inc | 232 +- .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx | 20 +- .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 259636 -> 252949 bytes software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd | 20 +- .../SCSI2SD.cydsn/TopDesign/TopDesign.cysch | Bin 253892 -> 253563 bytes .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cycdx | 0 .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 257227 -> 257227 bytes .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.svd | 0 .../SCSI2SD.cydsn/TopDesign/TopDesign.cysch | Bin 321028 -> 320681 bytes .../SCSI2SD/v5.5/SCSI2SD.cydsn/SCSI2SD.cycdx | 0 .../SCSI2SD/v5.5/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 254496 -> 254496 bytes .../SCSI2SD/v5.5/SCSI2SD.cydsn/SCSI2SD.svd | 0 41 files changed, 8534 insertions(+), 6751 deletions(-) create mode 100755 software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.c create mode 100755 software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.h mode change 100644 => 100755 software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx mode change 100644 => 100755 software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd mode change 100644 => 100755 software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx mode change 100644 => 100755 software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd mode change 100644 => 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cycdx mode change 100644 => 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.svd mode change 100644 => 100755 software/SCSI2SD/v5.5/SCSI2SD.cydsn/SCSI2SD.cycdx mode change 100644 => 100755 software/SCSI2SD/v5.5/SCSI2SD.cydsn/SCSI2SD.svd diff --git a/CHANGELOG b/CHANGELOG index aa3cd6a..255acb6 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,6 +1,9 @@ -2019XXXX 4.9.X +20190610 4.8.3 - Improve XEBEC controller support - Add Flexible Disk Drive Geometry SCSI MODE page + - Fix SD card hotswap bug + - Add scsi mode page 0 support + - Fix regression for EMU EMAX 20180926 4.8.1 - Fix bug when writing with multiple SCSI devices on the chain diff --git a/software/SCSI2SD/src/config.c b/software/SCSI2SD/src/config.c index f1367d9..7570e31 100755 --- a/software/SCSI2SD/src/config.c +++ b/software/SCSI2SD/src/config.c @@ -31,7 +31,7 @@ #include -static const uint16_t FIRMWARE_VERSION = 0x0482; +static const uint16_t FIRMWARE_VERSION = 0x0483; // 1 flash row static const uint8_t DEFAULT_CONFIG[256] = diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.c new file mode 100755 index 0000000..ce94d9c --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.c @@ -0,0 +1,1416 @@ +/***************************************************************************//** +* \file cy_em_eeprom.c +* \version 2.0 +* +* \brief +* This file provides source code of the API for the Emulated EEPROM library. +* The Emulated EEPROM API allows creating of an emulated EEPROM in flash that +* has the ability to do wear leveling and restore corrupted data from a +* redundant copy. +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include "cytypes.h" +#include + +#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + #include "em_eeprom/cy_em_eeprom.h" +#else + #include "cy_em_eeprom.h" +#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */ + + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*************************************** +* Private Function Prototypes +***************************************/ +static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context); +static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context); +static uint8 CalcChecksum(uint8 rowData[], uint32 len); +static void GetNextRowToWrite(uint32 seqNum, + uint32 * rowToWrPtr, + uint32 * rowToRdPtr, + cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config); +static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, uint32 *rowData, cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, uint32 ramBuffAddr, cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, + uint32 dstAddr, + uint32 rowOffset, + uint32 numBytes, + cy_stc_eeprom_context_t * context); +static uint32 GetAddresses(uint32 *startAddr, uint32 *endAddr, uint32 *offset, uint32 rowNum, uint32 addr, uint32 len); +static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context); + +/** +* \addtogroup group_em_eeprom_functions +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Init +****************************************************************************//** +* +* Initializes the Emulated EEPROM library by filling the context structure. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. +* +* \param context +* The pointer to the EEPROM context structure to be filled by the function. +* \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \note +* The context structure should not be modified by the user after it is filled +* with this function. Modification of context structure may cause the +* unexpected behavior of the Cy_Em_EEPROM API functions which rely on it. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* If the "Redundant Copy" option is used, the function performs a number of +* write operations to the EEPROM to initialize flash rows checksums. Therefore, +* Cy_Em_EEPROM_NumWrites(), when it is called right after Cy_Em_EEPROM_Init(), +* will return a non-zero value that identifies the number of writes performed +* by Cy_Em_EEPROM_Init(). +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + + if((NULL != context) && (NULL != config) && (NULL != ((uint32 *)config->userFlashStartAddr)) && + (config->wearLevelingFactor <= CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR) && (config->eepromSize != 0u)) + { + ret = CheckRanges(config); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Copy the user config structure fields into context */ + context->eepromSize = config->eepromSize; + context->wearLevelingFactor = config->wearLevelingFactor; + context->redundantCopy = config->redundantCopy; + context->blockingWrite = config->blockingWrite; + context->userFlashStartAddr = config->userFlashStartAddr; + /* Store frequently used data for internal use */ + context->numberOfRows = CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(config->eepromSize); + context->wlEndAddr = ((CY_EM_EEPROM_GET_EEPROM_SIZE(context->numberOfRows) * config->wearLevelingFactor) + + config->userFlashStartAddr); + /* Find last written EEPROM row and store it for quick access */ + FindLastWrittenRow(&context->lastWrRowAddr, context); + + if((0u == CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)) && (0u != context->redundantCopy)) + { + /* Call the function only after device reprogramming in case + * if redundant copy is enabled. + */ + ret = FillChecksum(context); + + /* Update the last written EEPROM row for Cy_Em_EEPROM_NumWrites() */ + FindLastWrittenRow(&context->lastWrRowAddr, context); + } + } + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Read +****************************************************************************//** +* +* This function takes the logical EEPROM address, converts it to the actual +* physical address where the data is stored and returns the data to the user. +* +* \param addr +* The logical start address in EEPROM to start reading data from. +* +* \param eepromData +* The pointer to a user array to write data to. +* +* \param size +* The amount of data to read. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \note +* In case if redundant copy option is enabled the function may perform writes +* to EEPROM. This is done in case if the data in the EEPPROM is corrupted and +* the data in redundant copy is valid based on CRC-8 data integrity check. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + uint32 i; + uint32 numBytesToRead; + uint32 curEepromBaseAddr; + uint32 curRowOffset; + uint32 startRowAddr; + uint32 actEepromRowNum; + uint32 curRdEepromRowNum = 0u; + uint32 dataStartEepromRowNum = 0u; + uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + + /* Validate input parameters */ + if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + { + uint32 rdAddr = addr; + uint32 rdSize = size; + /* Get the sequence number of the last written row */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr); + uint32 updateAddrFlag = 0u; + + /* Calculate the number of the row read operations. Currently this only concerns + * the reads from the EEPROM data locations. + */ + uint32 numRowReads = ((((rdAddr + rdSize) - 1u) / CY_EM_EEPROM_EEPROM_DATA_LEN) - + (rdAddr / CY_EM_EEPROM_EEPROM_DATA_LEN)) + 1u; + + /* Get the address of the first row of the currently active EEPROM sector. If + * no wear leveling is used - the EEPROM has only one sector, so use the base + * addr stored in "context->userFlashStartAddr". + */ + curEepromBaseAddr = (((context->lastWrRowAddr - context->userFlashStartAddr) / + (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) * + (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) + + context->userFlashStartAddr; + + /* Find the number of the row that contains the start address of the data */ + for(i = 0u; i < context->numberOfRows; i++) + { + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(rdAddr, i)) + { + dataStartEepromRowNum = i; + curRdEepromRowNum = dataStartEepromRowNum; + break; + } + } + + /* Find the row number of the last written row */ + actEepromRowNum = (context->lastWrRowAddr - curEepromBaseAddr) / CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + /* Check if wear leveling is used */ + if(context->wearLevelingFactor > 1u) + { + uint32 dataEndEepromRowNum = dataStartEepromRowNum + (numRowReads - 1u); + + /* Check if the future validation of the read address is required. */ + updateAddrFlag = (dataStartEepromRowNum > actEepromRowNum) ? 1u : + ((dataEndEepromRowNum > actEepromRowNum) ? 1u : 0u); + } + + /* Copy data from the EEPROM data locations to the user buffer */ + for(i = 0u; i < numRowReads; i++) + { + startRowAddr = curEepromBaseAddr + (curRdEepromRowNum * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + curRowOffset = CY_EM_EEPROM_EEPROM_DATA_LEN + (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN); + + /* Check if there are more reads pending and update the number of the + * remaining bytes to read respectively. + */ + if((i + 1u) < numRowReads) + { + numBytesToRead = CY_EM_EEPROM_EEPROM_DATA_LEN - (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN); + } + else + { + numBytesToRead = rdSize; + } + + /* Check if the read address needs to be updated to point to the correct + * EEPROM sector. + */ + if((0u != updateAddrFlag) && (curRdEepromRowNum > actEepromRowNum)) + { + startRowAddr -= context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + if(startRowAddr < context->userFlashStartAddr) + { + startRowAddr = context->wlEndAddr - + ((context->numberOfRows - curRdEepromRowNum) * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + } + + if(0u != context->redundantCopy) + { + /* Check a checksum of the EEPROM row and if it is bad, check a checksum in + * the corresponding row in redundant copy, otherwise return failure. + */ + ret = CheckCrcAndCopy(startRowAddr, eeData, curRowOffset, numBytesToRead, context); + + if(CY_EM_EEPROM_SUCCESS != ret) + { + break; + } + } + else + { + /* Copy the data to the user buffer */ + (void)memcpy((void *)(eeData), + (void *)(startRowAddr + curRowOffset), + numBytesToRead); + + /* Indicate success to be able to execute next code block */ + ret = CY_EM_EEPROM_SUCCESS; + } + + /* Update variables anticipated in the read operation */ + rdAddr += numBytesToRead; + rdSize -= numBytesToRead; + eeData += numBytesToRead; + curRdEepromRowNum++; + } + + /* This code block will copy the latest data from the EEPROM headers into the + * user buffer. The data previously copied into the user buffer may be updated + * as the EEPROM headers contain more recent data. + * The code block is executed when two following conditions are true: + * 1) The reads from "historic" data locations were successful; + * 2) The user performed at least one write operation to Em_EEPROM (0u != + * seqNum). + */ + if((CY_EM_EEPROM_SUCCESS == ret) && (0u != seqNum)) + { + numRowReads = (context->numberOfRows <= seqNum) ? (context->numberOfRows) : (seqNum); + numRowReads--; + + for(i = (seqNum - numRowReads); i <= seqNum; i++) + { + startRowAddr = GetRowAddrBySeqNum(i, context); + + if (0u != startRowAddr) + { + /* The following variables are introduced to increase code readability. */ + uint32 startAddr = *(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET); + uint32 endAddr = startAddr + (*(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET)); + + /* Check if the current row EEPROM header contains the data requested for read */ + if(0u != CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr, endAddr, addr, addr + size)) + { + uint32 srcOffset = (startAddr > addr) ? (0u) : (addr - startAddr); + uint32 dstOffset = (startAddr > addr) ? (startAddr - addr): (0u); + rdAddr = (startAddr > addr) ? (startAddr) : (addr); + + srcOffset += CY_EM_EEPROM_HEADER_DATA_OFFSET; + + /* Calculate the number of bytes to be read from the current row's EEPROM header */ + numBytesToRead = ((endAddr < (addr + size)) ? endAddr : (addr + size)) - rdAddr; + + /* Calculate the offset in the user buffer from which the data will be updated. */ + eeData = ((uint32)eepromData) + dstOffset; + + /* Check a checksum of the EEPROM row and if it is bad, check a checksum in the + * corresponding row in redundant copy, otherwise return failure. Copy the data + * from the recent EEPROM headers to the user buffer. This will overwrite the + * data copied form EEPROM data locations as the data in EEPROM headers is newer. + */ + if(0u != context->redundantCopy) + { + ret = CheckCrcAndCopy(startRowAddr, eeData, srcOffset, numBytesToRead, context); + + if(CY_EM_EEPROM_SUCCESS != ret) + { + break; + } + } + else + { + (void)memcpy((void *)(eeData), (void *)(startRowAddr + srcOffset), numBytesToRead); + } + } + } + } + } + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Write +****************************************************************************//** +* +* This function takes the logical EEPROM address and converts it to the actual +* physical address and writes data there. If wear leveling is implemented, the +* writing process will use the wear leveling techniques. This is a blocking +* function and it does not return until the write operation is completed. The +* user firmware should not enter Hibernate mode until write is completed. The +* write operation is allowed in Sleep and Deep-Sleep modes. During the flash +* operation, the device should not be reset, including the XRES pin, a software +* reset, and watchdog reset sources. Also, low-voltage detect circuits should +* be configured to generate an interrupt instead of a reset. Otherwise, portions +* of flash may undergo unexpected changes. +* +* \param addr +* The logical start address in EEPROM to start writing data from. +* +* \param eepromData +* Data to write to EEPROM. +* +* \param size +* The amount of data to write to EEPROM. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform write +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* In case when blocking write option is used, if this function is called by +* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase +* flash row operation is finished. If this function is called by the CM0P the +* user code on CM4 is not blocked and the user code on CM0P is blocked until +* erase flash row operation is finished. Plan your task allocation accordingly. +* +* \sideeffect +* In case if non-blocking write option is used and when user flash is used as +* an EEPROM storage care should be taken to prevent the read while write (RWW) +* exception. To prevent the RWW exception the user flash macro that includes +* the EEPROM storage should not be read while the EEPROM write is not completed. +* The read also means the user code execution from the respective flash macro. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + uint32 i; + uint32 wrCnt; + uint32 actEmEepromRowNum; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + uint32 startAddr = 0u; + uint32 endAddr = 0u; + uint32 tmpRowAddr; + uint32 emEepromRowAddr = context->lastWrRowAddr; + uint32 emEepromRowRdAddr; + void * tmpData; + uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + + /* Check if the EEPROM data does not exceed the EEPROM capacity */ + if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + { + uint32 numWrites = ((size - 1u) / CY_EM_EEPROM_HEADER_DATA_LEN) + 1u; + uint32 eeHeaderDataOffset = 0u; + + for(wrCnt = 0u; wrCnt < numWrites; wrCnt++) + { + uint32 skipOperation = 0u; + /* Get the sequence number of the last written row */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + + /* Get the address of the row to be written. The "emEepromRowAddr" may be + * updated with the proper address (if wear leveling is used). The + * "emEepromRowRdAddr" will point to the row address from which the historic + * data will be read into the RAM buffer. + */ + GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + + /* Clear the RAM buffer so to not put junk into flash */ + (void)memset(writeRamBuffer, 0, CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Fill the EM_EEPROM header info for the row in the RAM buffer */ + seqNum++; + writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + writeRamBuffer[CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32] = addr; + tmpData = (void *) eeData; + + /* Check if this is the last row to write */ + if(wrCnt == (numWrites - 1u)) + { + /* Fill in the remaining size value to the EEPROM header. */ + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = size; + } + else + { + /* This is not the last row to write in the current EEPROM write operation. + * Write the maximum possible data size to the EEPROM header. Update the + * size, eeData and addr respectively. + */ + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = CY_EM_EEPROM_HEADER_DATA_LEN; + size -= CY_EM_EEPROM_HEADER_DATA_LEN; + addr += CY_EM_EEPROM_HEADER_DATA_LEN; + eeData += CY_EM_EEPROM_HEADER_DATA_LEN; + } + + /* Write the data to the EEPROM header */ + (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_HEADER_DATA_OFFSET_U32], + tmpData, + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32]); + + if(emEepromRowRdAddr != 0UL) + { + /* Copy the EEPROM historic data for this row from flash to RAM */ + (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + (void *)(emEepromRowRdAddr + CY_EM_EEPROM_EEPROM_DATA_LEN), + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + + /* Check if there is data for this location in other EEPROM headers: + * find out the row with the lowest possible sequence number which + * may contain the data for the current row. + */ + i = (seqNum > context->numberOfRows) ? ((seqNum - (context->numberOfRows)) + 1u) : 1u; + + for(; i <= seqNum; i++) + { + if(i == seqNum) + { + /* The code reached the row that is about to be written. Analyze the recently + * created EEPROM header (stored in the RAM buffer currently): if it contains + * the data for EEPROM data locations in the row that is about to be written. + */ + tmpRowAddr = (uint32) writeRamBuffer; + } + else + { + /* Retrieve the address of the previously written row by its sequence number. + * The pointer will be used to get data from the respective EEPROM header. + */ + tmpRowAddr = GetRowAddrBySeqNum(i, context); + } + + actEmEepromRowNum = CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(emEepromRowAddr, + context->numberOfRows, + context->userFlashStartAddr); + if(0UL != tmpRowAddr) + { + /* Calculate the required addressed for the later EEPROM historic data update */ + skipOperation = GetAddresses( + &startAddr, + &endAddr, + &eeHeaderDataOffset, + actEmEepromRowNum, + *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET), + *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET)); + } + else + { + /* Skip writes to the RAM buffer */ + skipOperation++; + } + + /* Write data to the RAM buffer */ + if(0u == skipOperation) + { + uint32 dataAddr = ((uint32)((uint8 *)&writeRamBuffer)) + startAddr; + + /* Update the address to point to the EEPROM header data and not to + * the start of the row. + */ + tmpRowAddr = tmpRowAddr + CY_EM_EEPROM_HEADER_DATA_OFFSET + eeHeaderDataOffset; + (void)memcpy((void *)(dataAddr), (void *)(tmpRowAddr), endAddr - startAddr); + } + + /* Calculate the checksum if redundant copy is enabled */ + if(0u != context->redundantCopy) + { + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + } + + /* Write the data to the specified flash row */ + ret = WriteRow(emEepromRowAddr, writeRamBuffer, context); + tmpRowAddr = emEepromRowAddr; + + /* Check if redundant copy is used */ + if((0u != context->redundantCopy) && (CY_EM_EEPROM_SUCCESS == ret)) + { + /* Update the row address to point to the row in the redundant EEPROM's copy */ + tmpRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Write the data to the specified flash row */ + ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Store last written row address only when EEPROM and redundant + * copy writes were successful. + */ + context->lastWrRowAddr = emEepromRowAddr; + } + else + { + break; + } + } + } + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Erase +****************************************************************************//** +* +* This function erases the entire contents of the EEPROM. Erased values are all +* zeros. This is a blocking function and it does not return until the write +* operation is completed. The user firmware should not enter Hibernate mode until +* erase is completed. The erase operation is allowed in Sleep and Deep-Sleep modes. +* During the flash operation, the device should not be reset, including the +* XRES pin, a software reset, and watchdog reset sources. Also, low-voltage +* detect circuits should be configured to generate an interrupt instead of a +* reset. Otherwise, portions of flash may undergo unexpected changes. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* For all non PSoC 6 devices the erase operation is performed by clearing +* the EEPROM data using flash write. This affects the flash durability. +* So it is recommended to use this function in utmost case to prolongate +* flash life. +* +* \note +* This function uses a buffer of the flash row size to perform erase +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* In case when blocking write option is used, if this function is called by +* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase +* flash row operation is finished. If this function is called by the CM0P the +* user code on CM4 is not blocked and the user code on CM0P is blocked until +* erase flash row operation is finished. Plan your task allocation accordingly. +* +* \sideeffect +* In case if non-blocking write option is used and when user flash is used as +* an EEPROM storage care should be taken to prevent the read while write (RWW) +* exception. To prevent the RWW exception the user flash macro that includes +* the EEPROM storage should not be read while the EEPROM erase is not completed. +* The read also means the user code execution from the respective flash macro. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context) +{ + uint32 i; + uint32 seqNum; + uint32 emEepromRowAddr = context->lastWrRowAddr; + uint32 emEepromRowRdAddr; + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV] = {0u}; +#if (CY_PSOC6) + uint32 emEepromStoredRowAddr = context->lastWrRowAddr; + uint32 storedSeqNum; +#endif /* (!CY_PSOC6) */ + + /* Get the sequence number of the last written row */ + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + + /* If there were no writes to EEPROM - nothing to erase */ + if(0u != seqNum) + { + /* Calculate the number of row erase operations required */ + uint32 numWrites = context->numberOfRows * context->wearLevelingFactor; + + #if (CY_PSOC6) + GetNextRowToWrite(seqNum, &emEepromStoredRowAddr, &emEepromRowRdAddr, context); + storedSeqNum = seqNum + 1u; + #endif /* (CY_PSOC6) */ + + if(0u != context->redundantCopy) + { + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + + for(i = 0u; i < numWrites; i++) + { + #if (CY_PSOC6) + /* For PSoC 6 the erase operation moves backwards. From last written row + * identified by "seqNum" down to "seqNum" - "numWrites". If "emEepromRowAddr" + * is zero this means that the row identified by "seqNum" was previously + * erased. + */ + if(0u != emEepromRowAddr) + { + ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + } + + seqNum--; + + if(0u == seqNum) + { + /* Exit the loop as there is no more row is EEPROM to be erased */ + break; + } + emEepromRowAddr = GetRowAddrBySeqNum(seqNum, context); + #else + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + /* Get the address of the row to be erased. "emEepromRowAddr" may be updated + * with the proper address (if wear leveling is used). + */ + GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + seqNum++; + writeRamBuffer[0u] = seqNum; + ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + #endif /* (CY_PSOC6) */ + } + + #if (CY_PSOC6) + if(CY_EM_EEPROM_SUCCESS == ret) + { + writeRamBuffer[0u] = storedSeqNum; + + /* Write the previously stored sequence number to the flash row which would be + * written next if the erase wouldn't happen. In this case the write to + * redundant copy can be skipped as it does not add any value. + */ + ret = WriteRow(emEepromStoredRowAddr, writeRamBuffer, context); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + context->lastWrRowAddr = emEepromStoredRowAddr; + } + } + #endif /* (CY_PSOC6) */ + + } + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_NumWrites +****************************************************************************//** +* +* Returns the number of the EEPROM writes completed so far. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* The number of writes performed to the EEPROM. +* +*******************************************************************************/ +uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context) +{ + return(CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)); +} + +/** \} */ + +/** \cond INTERNAL */ + + +/******************************************************************************* +* Function Name: FindLastWrittenRow +****************************************************************************//** +* +* Performs a search of the last written row address of the EEPROM associated +* with the context structure. If there were no writes to the EEPROM the +* function returns the start address of the EEPROM. The row address is returned +* in the input parameter. +* +* \param lastWrRowPtr +* The pointer to a memory where the last written row will be returned. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +*******************************************************************************/ +static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context) +{ + uint32 seqNum = 0u; + uint32 prevSeqNum = 0u; + uint32 numRows; + uint32 emEepromAddr = context->userFlashStartAddr; + + *lastWrRowPtr = emEepromAddr; + + for(numRows = 0u; numRows < (context->numberOfRows * context->wearLevelingFactor); numRows++) + { + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr); + if((0u != seqNum) && (seqNum > prevSeqNum)) + { + /* Some record in EEPROM was found. Store found sequence + * number and row address. + */ + prevSeqNum = seqNum; + *lastWrRowPtr = emEepromAddr; + } + + /* Switch to the next row */ + emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + } +} + + +/******************************************************************************* +* Function Name: GetRowAddrBySeqNum +****************************************************************************//** +* +* Returns the address of the row in EEPROM using its sequence number. +* +* \param seqNum +* The sequence number of the row. +* +* \param context +* The pointer to the EEPROM context structure. +* +* \return +* The address of the row or zero if the row with the sequence number was not +* found. +* +*******************************************************************************/ +static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context) +{ + uint32 emEepromAddr = context->userFlashStartAddr; + + while(CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr) != seqNum) + { + /* Switch to the next row */ + emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + if (CY_EM_EEPROM_ADDR_IN_RANGE != + CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(emEepromAddr, context->wlEndAddr)) + { + emEepromAddr = 0u; + /* Exit the loop as we reached the end of EEPROM */ + break; + } + } + + return (emEepromAddr); +} + + +/******************************************************************************* +* Function Name: GetNextRowToWrite +****************************************************************************//** +* +* Performs a range check of the row that should be written and updates the +* address to the row respectively. The similar actions are done for the read +* address. +* +* \param seqNum +* The sequence number of the last written row. +* +* \param rowToWrPtr +* The address of the last written row (input). The address of the row to be +* written (output). +* +* \param rowToRdPtr +* The address of the row from which the data should be read into the RAM buffer +* in a later write operation. Out parameter. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +*******************************************************************************/ +static void GetNextRowToWrite(uint32 seqNum, + uint32 * rowToWrPtr, + uint32 * rowToRdPtr, + cy_stc_eeprom_context_t * context) +{ + /* Switch to the next row to be written if the current sequence number is + * not zero. + */ + if(0u != seqNum) + { + *rowToWrPtr = (*rowToWrPtr + CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + + /* If the resulting row address is out of EEPROM, then switch to the base + * EEPROM address (Row#0). + */ + if(CY_EM_EEPROM_ADDR_IN_RANGE != + CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(*rowToWrPtr, context->wlEndAddr)) + { + *rowToWrPtr = context->userFlashStartAddr; + } + + *rowToRdPtr = 0u; + + /* Check if the sequence number is larger than the number of rows in the EEPROM. + * If not, do not update the row read address because there is no historic + * data to be read. + */ + if(context->numberOfRows <= seqNum) + { + /* Check if wear leveling is used in EEPROM */ + if(context->wearLevelingFactor > 1u) + { + /* The read row address should be taken from an EEPROM copy that became + * inactive recently. This condition check handles that. + */ + if((*rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW)) < + context->userFlashStartAddr) + { + *rowToRdPtr = context->userFlashStartAddr + + (context->numberOfRows * (context->wearLevelingFactor - 1u) * + CY_EM_EEPROM_FLASH_SIZEOF_ROW) + (*rowToWrPtr - context->userFlashStartAddr); + } + else + { + *rowToRdPtr = *rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + } + else + { + /* If no wear leveling, always read from the same flash row that + * should be written. + */ + *rowToRdPtr = *rowToWrPtr; + } + } +} + + +/******************************************************************************* +* Function Name: CalcChecksum +****************************************************************************//** +* +* Implements CRC-8 that is used in checksum calculation for the redundant copy +* algorithm. +* +* \param rowData +* The row data to be used to calculate the checksum. +* +* \param len +* The length of rowData. +* +* \return +* The calculated value of CRC-8. +* +*******************************************************************************/ +static uint8 CalcChecksum(uint8 rowData[], uint32 len) +{ + uint8 crc = CY_EM_EEPROM_CRC8_SEED; + uint8 i; + uint16 cnt = 0u; + + while(cnt != len) + { + crc ^= rowData[cnt]; + for (i = 0u; i < CY_EM_EEPROM_CRC8_POLYNOM_LEN; i++) + { + crc = CY_EM_EEPROM_CALCULATE_CRC8(crc); + } + cnt++; + } + + return (crc); +} + + +/******************************************************************************* +* Function Name: CheckRanges +****************************************************************************//** +* +* Checks if the EEPROM of the requested size can be placed in flash. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_DATA; + uint32 startAddr = config->userFlashStartAddr; + uint32 endAddr = startAddr + CY_EM_EEPROM_GET_PHYSICAL_SIZE(config->eepromSize, + config->wearLevelingFactor, config->redundantCopy); + + /* Range check if there is enough flash for EEPROM */ + if (CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + return (ret); +} + + +/******************************************************************************* +* Function Name: WriteRow +****************************************************************************//** +* +* Writes one flash row starting from the specified row address. +* +* \param rowAdd +* The address of the flash row. +* +* \param rowData +* The pointer to the data to be written to the row. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, + uint32 *rowData, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; +#if (!CY_PSOC6) + cystatus rc; + uint32 rowId; + #if ((CY_PSOC3) || (CY_PSOC5)) + uint32 arrayId; + #endif /* (CY_PSOC3) */ + + #if (CY_PSOC3) + rowAddr &= CY_EM_EEPROM_CODE_ADDR_MASK; + context = context; /* To avoid compiler warning generation */ + #else + (void)context; /* To avoid compiler warning generation */ + #endif /* ((CY_PSOC3) */ + + /* For non-PSoC 6 devices, the Array ID and Row ID needed to write the row */ + rowId = (rowAddr / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % CY_EM_EEPROM_ROWS_IN_ARRAY; + + /* Write the flash row */ + #if (CY_PSOC4) + rc = CySysFlashWriteRow(rowId, (uint8 *)rowData); + #else + + #ifndef CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT + (void)CySetTemp(); + #endif /* (CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT) */ + + arrayId = rowAddr / CY_FLASH_SIZEOF_ARRAY; + rc = CyWriteRowData((uint8)arrayId, (uint16)rowId, (uint8 *)rowData); + + #if (CY_PSOC5) + CyFlushCache(); + #endif /* (CY_PSOC5) */ + #endif /* (CY_PSOC4) */ + + if(CYRET_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } +#else /* PSoC 6 */ + if(0u != context->blockingWrite) + { + /* Do blocking write */ + if(CY_FLASH_DRV_SUCCESS == Cy_Flash_WriteRow(rowAddr, (const uint32 *)rowData)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + else + { + /* Initiate write */ + if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartWrite(rowAddr, (const uint32 *)rowData)) + { + uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; + cy_en_flashdrv_status_t rc; + + do + { + CyDelay(1u); /* Wait 1ms */ + rc = Cy_Flash_IsWriteComplete(); /* Check if write completed */ + countMs--; + } + while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); + + if(CY_FLASH_DRV_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + } +#endif /* (CY_PSOC6) */ + + return (ret); +} + + +/******************************************************************************* +* Function Name: EraseRow +****************************************************************************//** +* +* Erases one flash row starting from the specified row address. If the redundant +* copy option is enabled the corresponding row in the redundant copy will also +* be erased. +* +* \param rowAdd +* The address of the flash row. +* +* \param ramBuffAddr +* The address of the RAM buffer that contains zeroed data (used only for +* non-PSoC 6 devices). +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, + uint32 ramBuffAddr, + cy_stc_eeprom_context_t * context) +{ + uint32 emEepromRowAddr = rowAddr; + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; +#if (CY_PSOC6) + uint32 i = 1u; + + (void)ramBuffAddr; /* To avoid compiler warning */ + + if(0u != context->redundantCopy) + { + i++; + } + + do + { + if(0u != context->blockingWrite) + { + /* Erase the flash row */ + if(CY_FLASH_DRV_SUCCESS == Cy_Flash_EraseRow(emEepromRowAddr)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + else + { + /* Initiate erase */ + if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartErase(emEepromRowAddr)) + { + uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; + cy_en_flashdrv_status_t rc; + + do + { + CyDelay(1u); /* Wait 1ms */ + rc = Cy_Flash_IsWriteComplete(); /* Check if erase completed */ + countMs--; + } + while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); + + if(CY_FLASH_DRV_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Update the address to point to the redundant copy row */ + emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + } + else + { + break; + } + i--; + } while (0u != i); +#else + /* Write the data to the specified flash row */ + ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + + if((CY_EM_EEPROM_SUCCESS == ret) && (0u != context->redundantCopy)) + { + /* Update the address to point to the redundant copy row */ + emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + context->lastWrRowAddr = rowAddr; + } +#endif /* (CY_PSOC6) */ + + return(ret); +} + + +/******************************************************************************* +* Function Name: CheckCrcAndCopy +****************************************************************************//** +* +* Checks the checksum of the specific row in EEPROM. If the CRC matches - copies +* the data to the "datAddr" from EEPROM. f the CRC does not match checks the +* CRC of the corresponding row in the EEPROM's redundant copy. If the CRC +* matches - copies the data to the "datAddr" from EEPROM redundant copy. If the +* CRC of the redundant copy does not match - returns bad checksum. +* +* \param startAddr +* The address that points to the start of the specified row. +* +* \param datAddr +* The start address of where the row data will be copied if the CRC check +* will succeed. +* +* \param rowOffset +* The offset in the row from which the data should be copied. +* +* \param numBytes +* The number of bytes to be copied. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, + uint32 dstAddr, + uint32 rowOffset, + uint32 numBytes, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + + /* Calculate the row address in the EEPROM's redundant copy */ + uint32 rcStartRowAddr = (startAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Check the row data CRC in the EEPROM */ + if((*(uint32 *)(startAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + ((uint32) CalcChecksum((uint8 *)(startAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + CY_EM_EEPROM_EEPROM_DATA_LEN))) + { + (void)memcpy((void *)(dstAddr), (void *)(startAddr + rowOffset), numBytes); + + ret = CY_EM_EEPROM_SUCCESS; + } + /* Check the row data CRC in the EEPROM's redundant copy */ + else if((*(uint32 *)(rcStartRowAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + ((uint32) CalcChecksum((uint8 *)(rcStartRowAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + CY_EM_EEPROM_EEPROM_DATA_LEN))) + { + /* Copy the redundant copy row to RAM buffer to avoid read while write (RWW) + * flash exception. The RWW occurs while trying to write and read the data from + * same flash macro. + */ + (void)memcpy((void *)(writeRamBuffer), (void *)(rcStartRowAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Restore bad row data from the RAM buffer */ + ret = WriteRow(startAddr, (uint32 *)writeRamBuffer, context); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + (void)memcpy((void *)(dstAddr), (void *)(writeRamBuffer + rowOffset), numBytes); + } + } + else + { + ret = CY_EM_EEPROM_BAD_CHECKSUM; + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: GetAddresses +****************************************************************************//** +* +* Calculates the start and end address of the row's EEPROM data to be updated. +* The start and end are not absolute addresses but a relative addresses in a +* flash row. +* +* \param startAddr +* The pointer the address where the EEPROM data start address will be returned. +* +* \param endAddr +* The pointer the address where the EEPROM data end address will be returned. +* +* \param offset +* The pointer the address where the calculated offset of the EEPROM header data +* will be returned. +* +* \param rowNum +* The row number that is about to be written. +* +* \param addr +* The address of the EEPROM header data in the currently analyzed row that may +* concern to the row about to be written. +* +* \param len +* The length of the EEPROM header data in the currently analyzed row that may +* concern to the row about to be written. +* +* \return +* Zero indicates that the currently analyzed row has the data to be written to +* the active EEPROM row data locations. Non zero value indicates that there is +* no data to be written +* +*******************************************************************************/ +static uint32 GetAddresses(uint32 *startAddr, + uint32 *endAddr, + uint32 *offset, + uint32 rowNum, + uint32 addr, + uint32 len) +{ + uint32 skip = 0u; + + *offset =0u; + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum)) + { + *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN + (addr % CY_EM_EEPROM_EEPROM_DATA_LEN); + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + { + *endAddr = *startAddr + len; + } + else + { + *endAddr = CY_EM_EEPROM_FLASH_SIZEOF_ROW; + } + } + else + { + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + { + *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN; + *endAddr = (*startAddr + len) - (*startAddr - (addr % CY_EM_EEPROM_EEPROM_DATA_LEN)); + *offset = len - (*endAddr - *startAddr); + } + else + { + skip++; + } + } + + return (skip); +} + + +/******************************************************************************* +* Function Name: FillChecksum +****************************************************************************//** +* +* Performs calculation of the checksum on each row in the Em_EEPROM and fills +* the Em_EEPROM headers checksum field with the calculated checksums. +* +* \param context +* The pointer to the EEPROM context structure. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \theory +* In case if redundant copy option is used the Em_EEPROM would return bad +* checksum while trying to read the EEPROM rows which were not yet written by +* the user. E.g. any read after device reprogramming without previous Write() +* operation to the EEPROM would fail. This would happen because the Em_EEPROM +* headers checksum field values (which is zero at the moment) would not be +* equal to the actual data checksum. This function allows to avoid read failure +* after device reprogramming. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context) +{ + uint32 i; + uint32 rdAddr; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + uint32 wrAddr = context->lastWrRowAddr; + uint32 tmpRowAddr; + /* Get the sequence number (number of writes) */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(wrAddr); + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + + for(i = 0u; i < (context->numberOfRows * context->wearLevelingFactor); i++) + { + /* Copy the EEPROM row from Flash to RAM */ + (void)memcpy((void *)&writeRamBuffer[0u], (void *)(wrAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Increment the sequence number */ + seqNum++; + writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + + /* Calculate and fill the checksum to the Em_EEPROM header */ + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + + /* Write the data to the specified flash row */ + ret = WriteRow(wrAddr, writeRamBuffer, context); + + /* Update the row address to point to the relevant row in the redundant + * EEPROM's copy. + */ + tmpRowAddr = (wrAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Write the data to the specified flash row */ + ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + + /* Get the address of the next row to be written. + * "rdAddr" is not used in this function but provided to prevent NULL + * pointer exception in GetNextRowToWrite(). + */ + GetNextRowToWrite(seqNum, &wrAddr, &rdAddr, context); + } + + return(ret); +} + +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.h new file mode 100755 index 0000000..4aef67b --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.h @@ -0,0 +1,556 @@ +/******************************************************************************* +* \file cy_em_eeprom.h +* \version 2.0 +* +* \brief +* This file provides the function prototypes and constants for the Emulated +* EEPROM middleware library. +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** + * \mainpage Cypress Em_EEPROM Middleware Library + * + * The Emulated EEPROM provides an API that allows creating an emulated + * EEPROM in flash that has the ability to do wear leveling and restore + * corrupted data from a redundant copy. The Emulated EEPROM library is designed + * to be used with the Em_EEPROM component. + * + * The Cy_Em_EEPROM API is described in the following sections: + * - \ref group_em_eeprom_macros + * - \ref group_em_eeprom_data_structures + * - \ref group_em_eeprom_enums + * - \ref group_em_eeprom_functions + * + * Features: + * * EEPROM-Like Non-Volatile Storage + * * Easy to use Read and Write API + * * Optional Wear Leveling + * * Optional Redundant Data storage + * + * \section group_em_eeprom_configuration Configuration Considerations + * + * The Em_EEPROM operates on the top of the flash driver. The flash driver has + * some prerequisites for proper operation. Refer to the "Flash System + * Routine (Flash)" section of the PDL API Reference Manual. + * + * Initializing Emulated EEPROM in User flash + * + * To initialize an Emulated EEPROM in the User flash, the EEPROM storage should + * be declared by the user. For the proper operation, the EEPROM storage should + * be aligned to the size of the flash row. An example of the EEPROM storage + * declaration is below (applicable for GCC and MDK compilers): + * + * CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW) + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * The same declaration for the IAR compiler: + * + * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * Note that the name "emEeprom" is shown for reference. Any other name can be + * used instead. Also, note that the Em_EEPROM_PHYSICAL_SIZE constant is + * generated by the PSoC Creator Em_EEPROM component and so it is instance name + * dependent and its prefix should be changed when the name of the component + * changes. If the The Cy_Em_EEPROM middleware library is used without the + * Em_EEPROM component, the user has to provide a proper size for the EEPROM + * storage instead of Em_EEPROM_PHYSICAL_SIZE. The size of the EEPROM storage + * can be calculated using the following equation: + * + * Physical size = EEPROM data size * 2 * wear leveling * (1 + redundant copy) + * + * where, + * "EEPROM data size" - the size of data the user wants to store in the + * EEPROM. The data size must divide evenly to the half of the flash row size. + * "wear leveling" - the wear leveling factor (1-10). + * "redundant copy" - "zero" if a redundant copy is not used, and "one" + * otherwise. + * + * The start address of the storage should be filled to the Emulated EEPROM + * configuration structure and then passed to the Cy_Em_EEPROM_Init(). + * If the Em_EEPROM component is used, the config (Em_EEPROM_config) and + * context structures (Em_EEPROM_context) are defined by the component, so the + * user may just use that structures otherwise both of the structures need to + * be provided by the user. Note that if the "Config Data in Flash" + * option is selected in the component, then the configuration structure should + * be copied to RAM to allow EEPROM storage start address update. The following + * code demonstrates utilization of "Em_EEPROM_config" and "Em_EEPROM_context" + * Em_EEPROM component structures for Cy_Em_EEPROM middleware library + * initialization: + * + * cy_en_em_eeprom_status_t retValue; + * cy_stc_eeprom_config_t config; + * + * memcpy((void *)&config, + (void *)&Em_EEPROM_config, + sizeof(cy_stc_eeprom_config_t)); + * config.userFlashStartAddr = (uint32)emEeprom; + * retValue = Cy_Em_EEPROM_Init(&config, &Em_EEPROM_context); + * + * Initializing EEPROM in Emulated EEPROM flash area + * + * Initializing of the EEPROM storage in the Emulated EEPROM flash area is + * identical to initializing of the EEPROM storage in the User flash with one + * difference. The location of the Emulated EEPROM storage should be specified + * somewhere in the EmulatedEEPROM flash area. If the Em_EEPROM component is + * utilized in the project, then the respective storage + * (Em_EEPROM_em_EepromStorage[]) is automatically declared by the component + * if the "Use Emulated EEPROM" option is set to "Yes". The user just needs to + * fill the start address of the storage to the config structure. If the + * Em_EEPROM component is not used, the user needs to declare the storage + * in the Emulated EEPROM flash area. An example of such declaration is + * following (applicable for GCC and MDK compilers): + * + * CY_SECTION(".cy_em_eeprom") CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW) + * const uint8_t emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * The same declaration for the IAR compiler: + * + * #pragma location = ".cy_em_eeprom" + * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * where, + * Em_EEPROM_PHYSICAL_SIZE - is a constant that is generated by the Em_EEPROM + * component when the component is utilized in the project or it should be + * provided by the user. The equation for the calculation of the constant is + * shown above. + * + * Note that the size of the Emulated EEPROM flash area is limited. Refer to the + * specific device datasheet for the value of the available EEPROM Emulation + * area. + * + * \section group_em_eeprom_more_information More Information + * See the Em_EEPROM Component datasheet. + * + * + * \section group_em_eeprom_MISRA MISRA-C Compliance + * + * The Cy_Em_EEPROM library has the following specific deviations: + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AThe cast should not be performed between a pointer to the object type + * and a different pointer to the object type.The cast from the object type and a different pointer to the object + * was used intentionally because of the performance reasons.
14.2RAll non-null statements shall either have at least one side-effect, + * however executed, or cause control flow to change.To maintain common codebase, some variables, unused for a specific + * device, are casted to void to prevent generation of an unused variable + * compiler warning.
16.7AThe object addressed by the pointer parameter is not modified and so + * the pointer could be of type 'pointer to const'.The warning is generated because of the pointer dereferencing to + * address which makes the MISRA checker think the data is not + * modified.
17.4RThe array indexing shall be the only allowed form of pointer + * arithmetic.The pointer arithmetic used in several places on the Cy_Em_EEPROM + * implementation is safe and preferred because it increases the code + * flexibility.
19.7AA function shall be used in preference to a function-like macro.Macro is used because of performance reasons.
+ * + * \section group_em_eeprom_changelog Changelog + * + * + * + * + * + * + * + *
VersionChangesReason for Change
1.0Initial Version
+ * + * \defgroup group_em_eeprom_macros Macros + * \brief + * This section describes the Emulated EEPROM Macros. + * + * \defgroup group_em_eeprom_functions Functions + * \brief + * This section describes the Emulated EEPROM Function Prototypes. + * + * \defgroup group_em_eeprom_data_structures Data Structures + * \brief + * Describes the data structures defined by the Emulated EEPROM. + * + * \defgroup group_em_eeprom_enums Enumerated types + * \brief + * Describes the enumeration types defined by the Emulated EEPROM. + * + */ + + +#if !defined(CY_EM_EEPROM_H) +#define CY_EM_EEPROM_H + +#include "cytypes.h" +#include +#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + #include + #include "syslib/cy_syslib.h" + #include "flash/cy_flash.h" +#else + #include "CyFlash.h" + #include +#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */ + +/* The C binding of definitions if building with the C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ +#define CY_PSOC6 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + + +/*************************************** +* Data Structure definitions +***************************************/ +/** +* \addtogroup group_em_eeprom_data_structures +* \{ +*/ + +/** EEPROM configuration structure */ +typedef struct +{ + /** The number of bytes to store in EEPROM */ + uint32 eepromSize; + + /** The amount of wear leveling from 1 to 10. 1 means no wear leveling + * is used. + */ + uint32 wearLevelingFactor; + + /** If not zero, a redundant copy of the Em_EEPROM is included. */ + uint8 redundantCopy; + + /** If not zero, a blocking write to flash is used. Otherwise non-blocking + * write is used. This parameter is used only for PSoC 6. + */ + uint8 blockingWrite; + + /** The start address for the EEPROM memory in the user's flash. */ + uint32 userFlashStartAddr; +} cy_stc_eeprom_config_t; + +/** \} group_em_eeprom_data_structures */ + +/** The EEPROM context data structure. It is used to store the specific +* EEPROM context data. +*/ +typedef struct +{ + /** The pointer to the end address of EEPROM including wear leveling overhead + * and excluding redundant copy overhead. + */ + uint32 wlEndAddr; + + /** The number of flash rows allocated for the EEPROM excluding the number of + * rows allocated for wear leveling and redundant copy overhead. + */ + uint32 numberOfRows; + + /** The address of the last written EEPROM row */ + uint32 lastWrRowAddr; + + /** The number of bytes to store in EEPROM */ + uint32 eepromSize; + + /** The amount of wear leveling from 1 to 10. 1 means no wear leveling + * is used. + */ + uint32 wearLevelingFactor; + + /** If not zero, a redundant copy of the Em_EEPROM is included. */ + uint8 redundantCopy; + + /** If not zero, a blocking write to flash is used. Otherwise non-blocking + * write is used. This parameter is used only for PSoC 6. + */ + uint8 blockingWrite; + + /** The start address for the EEPROM memory in the user's flash. */ + uint32 userFlashStartAddr; +} cy_stc_eeprom_context_t; + +#if (CY_PSOC6) + + #define CY_EM_EEPROM_ID (CY_PDL_DRV_ID(0x1BuL)) /**< Em_EEPROM PDL ID */ + /** + * \addtogroup group_em_eeprom_enums + * \{ + * Specifies return values meaning. + */ + /** A prefix for EEPROM function error return-values */ + #define CY_EM_EEPROM_ID_ERROR (uint32_t)(CY_EM_EEPROM_ID | CY_PDL_STATUS_ERROR) + +#else + + /** A prefix for EEPROM function status codes. For non-PSoC6 devices, + * prefix is zero. + */ + #define CY_EM_EEPROM_ID_ERROR (0uL) + +#endif /* (CY_PSOC6) */ + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +/** EEPROM return enumeration type */ +typedef enum +{ + CY_EM_EEPROM_SUCCESS = 0x00uL, /**< The function executed successfully */ + CY_EM_EEPROM_BAD_PARAM = (CY_EM_EEPROM_ID_ERROR + 1uL), /**< The input parameter is invalid */ + CY_EM_EEPROM_BAD_CHECKSUM = (CY_EM_EEPROM_ID_ERROR + 2uL), /**< The data in EEPROM is corrupted */ + CY_EM_EEPROM_BAD_DATA = (CY_EM_EEPROM_ID_ERROR + 3uL), /**< Failed to place the EEPROM in flash */ + CY_EM_EEPROM_WRITE_FAIL = (CY_EM_EEPROM_ID_ERROR + 4uL) /**< Write to EEPROM failed */ +} cy_en_em_eeprom_status_t; + +/** \} group_em_eeprom_enums */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_em_eeprom_functions +* \{ +*/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context); +uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context); +/** \} group_em_eeprom_functions */ + + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_em_eeprom_macros +* \{ +*/ +/** Library major version */ +#define CY_EM_EEPROM_VERSION_MAJOR (2) + +/** Library minor version */ +#define CY_EM_EEPROM_VERSION_MINOR (0) + +/** Defines the maximum data length that can be stored in one flash row */ +#define CY_EM_EEPROM_EEPROM_DATA_LEN (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) + +/** \} group_em_eeprom_macros */ + + +/*************************************** +* Macro definitions +***************************************/ +/** \cond INTERNAL */ + +/* Defines the size of flash row */ +#define CY_EM_EEPROM_FLASH_SIZEOF_ROW (CY_FLASH_SIZEOF_ROW) + +/* Device specific flash constants */ +#if (!CY_PSOC6) + #define CY_EM_EEPROM_FLASH_BASE_ADDR (CYDEV_FLASH_BASE) + #define CY_EM_EEPROM_FLASH_SIZE (CYDEV_FLASH_SIZE) + #define CY_EM_EEPROM_ROWS_IN_ARRAY (CY_FLASH_SIZEOF_ARRAY / CY_EM_EEPROM_FLASH_SIZEOF_ROW) + #if (CY_PSOC3) + #define CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX (0xff0000uL) + #define CY_EM_EEPROM_CODE_ADDR_END \ + (CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX + (CY_EM_EEPROM_FLASH_SIZE - 1u)) + #define CY_EM_EEPROM_CODE_ADDR_MASK (0xffffu) + /* Checks if the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((startAddr) > CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX) && \ + ((endAddr) <= CY_EM_EEPROM_CODE_ADDR_END)) + #else + /* Checks is the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) + #endif /* (CY_PSOC3) */ +#else + #define CY_EM_EEPROM_FLASH_BASE_ADDR (CY_FLASH_BASE) + #define CY_EM_EEPROM_FLASH_SIZE (CY_FLASH_SIZE) + #define CY_EM_EEPROM_EM_EEPROM_BASE_ADDR (CY_EM_EEPROM_BASE) + #define CY_EM_EEPROM_EM_EEPROM_SIZE (CY_EM_EEPROM_SIZE) + #define CY_EM_EEPROM_EM_EEPROM_END_ADDR (CY_EM_EEPROM_EM_EEPROM_BASE_ADDR + CY_EM_EEPROM_EM_EEPROM_SIZE) + /* Checks is the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) || \ + (((startAddr) >= CY_EM_EEPROM_EM_EEPROM_BASE_ADDR) && \ + ((endAddr) <= CY_EM_EEPROM_EM_EEPROM_END_ADDR)))) +#endif /* (!CY_PSOC6) */ + +#define CY_EM_EEPROM_FLASH_END_ADDR (CY_EM_EEPROM_FLASH_BASE_ADDR + CY_EM_EEPROM_FLASH_SIZE) + +/* Defines the length of EEPROM data that can be stored in Em_EEPROM header */ +#define CY_EM_EEPROM_HEADER_DATA_LEN ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) - 16u) + +#define CY_EM_EEPROM_ADDR_IN_RANGE (1u) + +/* Return CY_EM_EEPROM_ADDR_IN_RANGE if addr exceeded the upper range of +* EEPROM. The wear leveling overhead is included in the range but redundant copy +* is excluded. +*/ +#define CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(addr, endEepromAddr) \ + (((addr) >= (endEepromAddr)) ? (0u) : (CY_EM_EEPROM_ADDR_IN_RANGE)) + +/* Check to see if the specified address is present in the EEPROM */ +#define CY_EM_EEPROM_IS_ADDR_IN_RANGE(addr, startEepromAddr, endEepromAddr) \ + (((addr) > (startEepromAddr)) ? \ + (((addr) < (endEepromAddr)) ? (CY_EM_EEPROM_ADDR_IN_RANGE) : (0u)) : (0u)) + +/* Check if the EEPROM address locations from startAddr1 to endAddr1 +* are crossed with EEPROM address locations from startAddr2 to endAddr2. +*/ +#define CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr1, endAddr1 , startAddr2, endAddr2) \ + (((startAddr1) > (startAddr2)) ? (((startAddr1) >= (endAddr2)) ? (0u) : (1u) ) : \ + (((startAddr2) >= (endAddr1)) ? (0u) : (1u))) + +/* Return the pointer to the start of the redundant copy of the EEPROM */ +#define CY_EM_EEPROM_GET_REDNT_COPY_ADDR_BASE(numRows, wearLeveling, eepromStartAddr) \ + ((((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) * (wearLeveling)) + (eepromStartAddr)) + +/* Return the number of the row in EM_EEPROM which contains an address defined by +* rowAddr. + */ +#define CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(rowAddr, maxRows, eepromStartAddr) \ + ((((rowAddr) - (eepromStartAddr)) / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % (maxRows)) + + +/** Returns the size allocated for the EEPROM excluding wear leveling and +* redundant copy overhead. +*/ +#define CY_EM_EEPROM_GET_EEPROM_SIZE(numRows) ((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) + +/* Check if the given address belongs to the EEPROM address of the row +* specified by rowNum. +*/ +#define CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum) \ + (((addr) < ((rowNum) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u))) ? (0u) : \ + (((addr) > ((((rowNum) + 1u) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u)) - 1u)) ? \ + (0u) : (1u))) + +/* CRC-8 constants */ +#define CY_EM_EEPROM_CRC8_POLYNOM ((uint8)(0x31u)) +#define CY_EM_EEPROM_CRC8_POLYNOM_LEN (8u) +#define CY_EM_EEPROM_CRC8_SEED (0xFFu) +#define CY_EM_EEPROM_CRC8_XOR_VAL ((uint8) (0x80u)) + +#define CY_EM_EEPROM_CALCULATE_CRC8(crc) \ + ((CY_EM_EEPROM_CRC8_XOR_VAL == ((crc) & CY_EM_EEPROM_CRC8_XOR_VAL)) ? \ + ((uint8)(((uint8)((uint8)((crc) << 1u))) ^ CY_EM_EEPROM_CRC8_POLYNOM)) : ((uint8)((crc) << 1u))) + +#define CY_EM_EEPROM_GET_SEQ_NUM(addr) (*(uint32*)(addr)) + +/** \endcond */ + +/** +* \addtogroup group_em_eeprom_macros +* \{ +*/ + +/** Calculate the number of flash rows required to create an Em_EEPROM of +* dataSize. +*/ +#define CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) \ + (((dataSize) / (CY_EM_EEPROM_EEPROM_DATA_LEN)) + \ + ((((dataSize) % (CY_EM_EEPROM_EEPROM_DATA_LEN)) != 0u) ? 1U : 0U)) + +/** Returns the size of flash allocated for EEPROM including wear leveling and +* redundant copy overhead. +*/ +#define CY_EM_EEPROM_GET_PHYSICAL_SIZE(dataSize, wearLeveling, redundantCopy) \ + (((CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) * \ + CY_EM_EEPROM_FLASH_SIZEOF_ROW) * \ + (wearLeveling)) * (1uL + (redundantCopy))) + +/** \} group_em_eeprom_macros */ + + +/****************************************************************************** +* Local definitions +*******************************************************************************/ +/** \cond INTERNAL */ + +/* Offsets for 32-bit RAM buffer addressing */ +#define CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) / 4u) +#define CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32 (0u) +#define CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32 (1u) +#define CY_EM_EEPROM_HEADER_LEN_OFFSET_U32 (2u) +#define CY_EM_EEPROM_HEADER_DATA_OFFSET_U32 (3u) +#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32 (CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 - 1u) + +/* The same offsets as above used for direct memory addressing */ +#define CY_EM_EEPROM_EEPROM_DATA_OFFSET (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) +#define CY_EM_EEPROM_HEADER_ADDR_OFFSET (4u) +#define CY_EM_EEPROM_HEADER_LEN_OFFSET (8u) +#define CY_EM_EEPROM_HEADER_DATA_OFFSET (12u) +#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET (CY_EM_EEPROM_EEPROM_DATA_OFFSET - 4u) + +#define CY_EM_EEPROM_U32_DIV (4u) + +/* Maximum wear leveling value */ +#define CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR (10u) + +/* Maximum allowed flash row write/erase operation duration */ +#define CY_EM_EEPROM_MAX_WRITE_DURATION_MS (50u) + +/** \endcond */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* CY_EM_EEPROM_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h index 160bd6a..87d9c0b 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice.h * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h index bff26ed..9ac643d 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice_trm.h * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc index 5db8be3..0a6e4e6 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu.inc * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc index e0ed758..529602b 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu_trm.inc * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc index 6b49c48..33f3ab7 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.1 +; PSoC Creator 4.2 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc index c7c07d0..e128fd3 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar_trm.inc ; -; PSoC Creator 4.1 +; PSoC Creator 4.2 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc index e9f2b78..dcd9ce1 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.1 +; PSoC Creator 4.2 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc index 4a32cab..56680bb 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv_trm.inc ; -; PSoC Creator 4.1 +; PSoC Creator 4.2 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index e5a6d7b..2e5f9a6 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfitter.h * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,34 +19,6 @@ #include "cydevice.h" #include "cydevice_trm.h" -/* Debug_Timer_Interrupt */ -#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define Debug_Timer_Interrupt__INTC_MASK 0x01u -#define Debug_Timer_Interrupt__INTC_NUMBER 0u -#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u -#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0 -#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0 -#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1 -#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0 -#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1 -#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2 -#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 -#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 -#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0 -#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1 -#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 -#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u -#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 -#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u -#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0 -#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1 -#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0 - /* LED1 */ #define LED1__0__INTTYPE CYREG_PICU12_INTTYPE3 #define LED1__0__MASK 0x08u @@ -80,82 +52,450 @@ #define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ #define LED1__SLW CYREG_PRT12_SLW -/* SCSI_CLK */ -#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 -#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 -#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2 -#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u -#define SCSI_CLK__INDEX 0x01u -#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define SCSI_CLK__PM_ACT_MSK 0x02u -#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define SCSI_CLK__PM_STBY_MSK 0x02u +/* SD_CD */ +#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE6 +#define SD_CD__0__MASK 0x40u +#define SD_CD__0__PC CYREG_PRT3_PC6 +#define SD_CD__0__PORT 3u +#define SD_CD__0__SHIFT 6u +#define SD_CD__AG CYREG_PRT3_AG +#define SD_CD__AMUX CYREG_PRT3_AMUX +#define SD_CD__BIE CYREG_PRT3_BIE +#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CD__BYP CYREG_PRT3_BYP +#define SD_CD__CTL CYREG_PRT3_CTL +#define SD_CD__DM0 CYREG_PRT3_DM0 +#define SD_CD__DM1 CYREG_PRT3_DM1 +#define SD_CD__DM2 CYREG_PRT3_DM2 +#define SD_CD__DR CYREG_PRT3_DR +#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CD__MASK 0x40u +#define SD_CD__PORT 3u +#define SD_CD__PRT CYREG_PRT3_PRT +#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CD__PS CYREG_PRT3_PS +#define SD_CD__SHIFT 6u +#define SD_CD__SLW CYREG_PRT3_SLW -/* SCSI_CTL_PHASE */ -#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK +/* SD_CS */ +#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4 +#define SD_CS__0__MASK 0x10u +#define SD_CS__0__PC CYREG_PRT3_PC4 +#define SD_CS__0__PORT 3u +#define SD_CS__0__SHIFT 4u +#define SD_CS__AG CYREG_PRT3_AG +#define SD_CS__AMUX CYREG_PRT3_AMUX +#define SD_CS__BIE CYREG_PRT3_BIE +#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CS__BYP CYREG_PRT3_BYP +#define SD_CS__CTL CYREG_PRT3_CTL +#define SD_CS__DM0 CYREG_PRT3_DM0 +#define SD_CS__DM1 CYREG_PRT3_DM1 +#define SD_CS__DM2 CYREG_PRT3_DM2 +#define SD_CS__DR CYREG_PRT3_DR +#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CS__MASK 0x10u +#define SD_CS__PORT 3u +#define SD_CS__PRT CYREG_PRT3_PRT +#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CS__PS CYREG_PRT3_PS +#define SD_CS__SHIFT 4u +#define SD_CS__SLW CYREG_PRT3_SLW -/* SCSI_Filtered */ -#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u -#define SCSI_Filtered_sts_sts_reg__0__POS 0 -#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u -#define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST -#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u -#define SCSI_Filtered_sts_sts_reg__2__POS 2 -#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u -#define SCSI_Filtered_sts_sts_reg__3__POS 3 -#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u -#define SCSI_Filtered_sts_sts_reg__4__POS 4 -#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST +/* USBFS */ +#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_arb_int__INTC_MASK 0x400000u +#define USBFS_arb_int__INTC_NUMBER 22u +#define USBFS_arb_int__INTC_PRIOR_NUM 6u +#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 +#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_bus_reset__INTC_MASK 0x800000u +#define USBFS_bus_reset__INTC_NUMBER 23u +#define USBFS_bus_reset__INTC_PRIOR_NUM 7u +#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 +#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7 +#define USBFS_Dm__0__MASK 0x80u +#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 +#define USBFS_Dm__0__PORT 15u +#define USBFS_Dm__0__SHIFT 7u +#define USBFS_Dm__AG CYREG_PRT15_AG +#define USBFS_Dm__AMUX CYREG_PRT15_AMUX +#define USBFS_Dm__BIE CYREG_PRT15_BIE +#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dm__BYP CYREG_PRT15_BYP +#define USBFS_Dm__CTL CYREG_PRT15_CTL +#define USBFS_Dm__DM0 CYREG_PRT15_DM0 +#define USBFS_Dm__DM1 CYREG_PRT15_DM1 +#define USBFS_Dm__DM2 CYREG_PRT15_DM2 +#define USBFS_Dm__DR CYREG_PRT15_DR +#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dm__MASK 0x80u +#define USBFS_Dm__PORT 15u +#define USBFS_Dm__PRT CYREG_PRT15_PRT +#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dm__PS CYREG_PRT15_PS +#define USBFS_Dm__SHIFT 7u +#define USBFS_Dm__SLW CYREG_PRT15_SLW +#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6 +#define USBFS_Dp__0__MASK 0x40u +#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 +#define USBFS_Dp__0__PORT 15u +#define USBFS_Dp__0__SHIFT 6u +#define USBFS_Dp__AG CYREG_PRT15_AG +#define USBFS_Dp__AMUX CYREG_PRT15_AMUX +#define USBFS_Dp__BIE CYREG_PRT15_BIE +#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dp__BYP CYREG_PRT15_BYP +#define USBFS_Dp__CTL CYREG_PRT15_CTL +#define USBFS_Dp__DM0 CYREG_PRT15_DM0 +#define USBFS_Dp__DM1 CYREG_PRT15_DM1 +#define USBFS_Dp__DM2 CYREG_PRT15_DM2 +#define USBFS_Dp__DR CYREG_PRT15_DR +#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT +#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dp__MASK 0x40u +#define USBFS_Dp__PORT 15u +#define USBFS_Dp__PRT CYREG_PRT15_PRT +#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dp__PS CYREG_PRT15_PS +#define USBFS_Dp__SHIFT 6u +#define USBFS_Dp__SLW CYREG_PRT15_SLW +#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 +#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_dp_int__INTC_MASK 0x1000u +#define USBFS_dp_int__INTC_NUMBER 12u +#define USBFS_dp_int__INTC_PRIOR_NUM 7u +#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 +#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_0__INTC_MASK 0x1000000u +#define USBFS_ep_0__INTC_NUMBER 24u +#define USBFS_ep_0__INTC_PRIOR_NUM 7u +#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 +#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_1__INTC_MASK 0x80u +#define USBFS_ep_1__INTC_NUMBER 7u +#define USBFS_ep_1__INTC_PRIOR_NUM 7u +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 +#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_2__INTC_MASK 0x100u +#define USBFS_ep_2__INTC_NUMBER 8u +#define USBFS_ep_2__INTC_PRIOR_NUM 7u +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 +#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_3__INTC_MASK 0x200u +#define USBFS_ep_3__INTC_NUMBER 9u +#define USBFS_ep_3__INTC_PRIOR_NUM 7u +#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 +#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_4__INTC_MASK 0x400u +#define USBFS_ep_4__INTC_NUMBER 10u +#define USBFS_ep_4__INTC_PRIOR_NUM 7u +#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 +#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_sof_int__INTC_MASK 0x200000u +#define USBFS_sof_int__INTC_NUMBER 21u +#define USBFS_sof_int__INTC_PRIOR_NUM 7u +#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 +#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG +#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG +#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN +#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR +#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG +#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN +#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR +#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG +#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN +#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR +#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG +#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN +#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR +#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG +#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN +#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR +#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG +#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN +#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR +#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG +#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN +#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR +#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG +#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN +#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR +#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN +#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR +#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR +#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA +#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB +#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA +#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB +#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR +#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA +#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB +#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA +#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB +#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR +#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA +#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB +#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA +#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB +#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR +#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA +#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB +#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA +#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB +#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR +#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA +#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB +#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA +#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB +#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR +#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA +#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB +#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA +#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB +#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR +#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA +#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB +#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA +#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB +#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR +#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA +#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB +#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA +#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB +#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE +#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT +#define USBFS_USB__CR0 CYREG_USB_CR0 +#define USBFS_USB__CR1 CYREG_USB_CR1 +#define USBFS_USB__CWA CYREG_USB_CWA +#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB +#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES +#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB +#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG +#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE +#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE +#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT +#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR +#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 +#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 +#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 +#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 +#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 +#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 +#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 +#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 +#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE +#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 +#define USBFS_USB__PM_ACT_MSK 0x01u +#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 +#define USBFS_USB__PM_STBY_MSK 0x01u +#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN +#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR +#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 +#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 +#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 +#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 +#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 +#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 +#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 +#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 +#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 +#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 +#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 +#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 +#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 +#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 +#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 +#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 +#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 +#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 +#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 +#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 +#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 +#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 +#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 +#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 +#define USBFS_USB__SOF0 CYREG_USB_SOF0 +#define USBFS_USB__SOF1 CYREG_USB_SOF1 +#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN +#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 +#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 -/* SCSI_Glitch_Ctl */ -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK +/* SDCard */ +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST +#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_RxStsReg__4__POS 4 +#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u +#define SDCard_BSPIM_RxStsReg__5__POS 5 +#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u +#define SDCard_BSPIM_RxStsReg__6__POS 6 +#define SDCard_BSPIM_RxStsReg__MASK 0x70u +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK +#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL +#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 +#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u +#define SDCard_BSPIM_TxStsReg__0__POS 0 +#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u +#define SDCard_BSPIM_TxStsReg__1__POS 1 +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u +#define SDCard_BSPIM_TxStsReg__2__POS 2 +#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u +#define SDCard_BSPIM_TxStsReg__3__POS 3 +#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_TxStsReg__4__POS 4 +#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST + +/* SD_SCK */ +#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2 +#define SD_SCK__0__MASK 0x04u +#define SD_SCK__0__PC CYREG_PRT3_PC2 +#define SD_SCK__0__PORT 3u +#define SD_SCK__0__SHIFT 2u +#define SD_SCK__AG CYREG_PRT3_AG +#define SD_SCK__AMUX CYREG_PRT3_AMUX +#define SD_SCK__BIE CYREG_PRT3_BIE +#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_SCK__BYP CYREG_PRT3_BYP +#define SD_SCK__CTL CYREG_PRT3_CTL +#define SD_SCK__DM0 CYREG_PRT3_DM0 +#define SD_SCK__DM1 CYREG_PRT3_DM1 +#define SD_SCK__DM2 CYREG_PRT3_DM2 +#define SD_SCK__DR CYREG_PRT3_DR +#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS +#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN +#define SD_SCK__MASK 0x04u +#define SD_SCK__PORT 3u +#define SD_SCK__PRT CYREG_PRT3_PRT +#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_SCK__PS CYREG_PRT3_PS +#define SD_SCK__SHIFT 2u +#define SD_SCK__SLW CYREG_PRT3_SLW /* SCSI_In */ #define SCSI_In__0__AG CYREG_PRT2_AG @@ -885,285 +1225,152 @@ #define SCSI_In_DBx__DB7__SHIFT 1u #define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW -/* SCSI_Noise */ -#define SCSI_Noise__0__AG CYREG_PRT12_AG -#define SCSI_Noise__0__BIE CYREG_PRT12_BIE -#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK -#define SCSI_Noise__0__BYP CYREG_PRT12_BYP -#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0 -#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1 -#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2 -#define SCSI_Noise__0__DR CYREG_PRT12_DR -#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS -#define SCSI_Noise__0__INTTYPE CYREG_PICU12_INTTYPE5 -#define SCSI_Noise__0__MASK 0x20u -#define SCSI_Noise__0__PC CYREG_PRT12_PC5 -#define SCSI_Noise__0__PORT 12u -#define SCSI_Noise__0__PRT CYREG_PRT12_PRT -#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN -#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 -#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 -#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 -#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 -#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT -#define SCSI_Noise__0__PS CYREG_PRT12_PS -#define SCSI_Noise__0__SHIFT 5u -#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG -#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF -#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN -#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ -#define SCSI_Noise__0__SLW CYREG_PRT12_SLW -#define SCSI_Noise__1__AG CYREG_PRT6_AG -#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__1__BIE CYREG_PRT6_BIE -#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__1__BYP CYREG_PRT6_BYP -#define SCSI_Noise__1__CTL CYREG_PRT6_CTL -#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__1__DR CYREG_PRT6_DR -#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__1__INTTYPE CYREG_PICU6_INTTYPE4 -#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__1__MASK 0x10u -#define SCSI_Noise__1__PC CYREG_PRT6_PC4 -#define SCSI_Noise__1__PORT 6u -#define SCSI_Noise__1__PRT CYREG_PRT6_PRT -#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__1__PS CYREG_PRT6_PS -#define SCSI_Noise__1__SHIFT 4u -#define SCSI_Noise__1__SLW CYREG_PRT6_SLW -#define SCSI_Noise__2__AG CYREG_PRT5_AG -#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX -#define SCSI_Noise__2__BIE CYREG_PRT5_BIE -#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK -#define SCSI_Noise__2__BYP CYREG_PRT5_BYP -#define SCSI_Noise__2__CTL CYREG_PRT5_CTL -#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0 -#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1 -#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2 -#define SCSI_Noise__2__DR CYREG_PRT5_DR -#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS -#define SCSI_Noise__2__INTTYPE CYREG_PICU5_INTTYPE0 -#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG -#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN -#define SCSI_Noise__2__MASK 0x01u -#define SCSI_Noise__2__PC CYREG_PRT5_PC0 -#define SCSI_Noise__2__PORT 5u -#define SCSI_Noise__2__PRT CYREG_PRT5_PRT -#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL -#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN -#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 -#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 -#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 -#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 -#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT -#define SCSI_Noise__2__PS CYREG_PRT5_PS -#define SCSI_Noise__2__SHIFT 0u -#define SCSI_Noise__2__SLW CYREG_PRT5_SLW -#define SCSI_Noise__3__AG CYREG_PRT6_AG -#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__3__BIE CYREG_PRT6_BIE -#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__3__BYP CYREG_PRT6_BYP -#define SCSI_Noise__3__CTL CYREG_PRT6_CTL -#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__3__DR CYREG_PRT6_DR -#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__3__INTTYPE CYREG_PICU6_INTTYPE6 -#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__3__MASK 0x40u -#define SCSI_Noise__3__PC CYREG_PRT6_PC6 -#define SCSI_Noise__3__PORT 6u -#define SCSI_Noise__3__PRT CYREG_PRT6_PRT -#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__3__PS CYREG_PRT6_PS -#define SCSI_Noise__3__SHIFT 6u -#define SCSI_Noise__3__SLW CYREG_PRT6_SLW -#define SCSI_Noise__4__AG CYREG_PRT6_AG -#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__4__BIE CYREG_PRT6_BIE -#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__4__BYP CYREG_PRT6_BYP -#define SCSI_Noise__4__CTL CYREG_PRT6_CTL -#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__4__DR CYREG_PRT6_DR -#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__4__INTTYPE CYREG_PICU6_INTTYPE5 -#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__4__MASK 0x20u -#define SCSI_Noise__4__PC CYREG_PRT6_PC5 -#define SCSI_Noise__4__PORT 6u -#define SCSI_Noise__4__PRT CYREG_PRT6_PRT -#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__4__PS CYREG_PRT6_PS -#define SCSI_Noise__4__SHIFT 5u -#define SCSI_Noise__4__SLW CYREG_PRT6_SLW -#define SCSI_Noise__ACK__AG CYREG_PRT6_AG -#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE -#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP -#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL -#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__ACK__DR CYREG_PRT6_DR -#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__ACK__INTTYPE CYREG_PICU6_INTTYPE5 -#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__ACK__MASK 0x20u -#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5 -#define SCSI_Noise__ACK__PORT 6u -#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT -#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__ACK__PS CYREG_PRT6_PS -#define SCSI_Noise__ACK__SHIFT 5u -#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW -#define SCSI_Noise__ATN__AG CYREG_PRT12_AG -#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE -#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK -#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP -#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0 -#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1 -#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2 -#define SCSI_Noise__ATN__DR CYREG_PRT12_DR -#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS -#define SCSI_Noise__ATN__INTTYPE CYREG_PICU12_INTTYPE5 -#define SCSI_Noise__ATN__MASK 0x20u -#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5 -#define SCSI_Noise__ATN__PORT 12u -#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT -#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN -#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 -#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 -#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 -#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 -#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT -#define SCSI_Noise__ATN__PS CYREG_PRT12_PS -#define SCSI_Noise__ATN__SHIFT 5u -#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG -#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF -#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN -#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ -#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW -#define SCSI_Noise__BSY__AG CYREG_PRT6_AG -#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE -#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP -#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL -#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__BSY__DR CYREG_PRT6_DR -#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__BSY__INTTYPE CYREG_PICU6_INTTYPE4 -#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__BSY__MASK 0x10u -#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4 -#define SCSI_Noise__BSY__PORT 6u -#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT -#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__BSY__PS CYREG_PRT6_PS -#define SCSI_Noise__BSY__SHIFT 4u -#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW -#define SCSI_Noise__RST__AG CYREG_PRT6_AG -#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE -#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP -#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL -#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__RST__DR CYREG_PRT6_DR -#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__RST__INTTYPE CYREG_PICU6_INTTYPE6 -#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__RST__MASK 0x40u -#define SCSI_Noise__RST__PC CYREG_PRT6_PC6 -#define SCSI_Noise__RST__PORT 6u -#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT -#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__RST__PS CYREG_PRT6_PS -#define SCSI_Noise__RST__SHIFT 6u -#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW -#define SCSI_Noise__SEL__AG CYREG_PRT5_AG -#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX -#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE -#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK -#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP -#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL -#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0 -#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1 -#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2 -#define SCSI_Noise__SEL__DR CYREG_PRT5_DR -#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS -#define SCSI_Noise__SEL__INTTYPE CYREG_PICU5_INTTYPE0 -#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG -#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN -#define SCSI_Noise__SEL__MASK 0x01u -#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0 -#define SCSI_Noise__SEL__PORT 5u -#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT -#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL -#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN -#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 -#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 -#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 -#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 -#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT -#define SCSI_Noise__SEL__PS CYREG_PRT5_PS -#define SCSI_Noise__SEL__SHIFT 0u -#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW +/* SD_DAT1 */ +#define SD_DAT1__0__INTTYPE CYREG_PICU3_INTTYPE0 +#define SD_DAT1__0__MASK 0x01u +#define SD_DAT1__0__PC CYREG_PRT3_PC0 +#define SD_DAT1__0__PORT 3u +#define SD_DAT1__0__SHIFT 0u +#define SD_DAT1__AG CYREG_PRT3_AG +#define SD_DAT1__AMUX CYREG_PRT3_AMUX +#define SD_DAT1__BIE CYREG_PRT3_BIE +#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_DAT1__BYP CYREG_PRT3_BYP +#define SD_DAT1__CTL CYREG_PRT3_CTL +#define SD_DAT1__DM0 CYREG_PRT3_DM0 +#define SD_DAT1__DM1 CYREG_PRT3_DM1 +#define SD_DAT1__DM2 CYREG_PRT3_DM2 +#define SD_DAT1__DR CYREG_PRT3_DR +#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS +#define SD_DAT1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN +#define SD_DAT1__MASK 0x01u +#define SD_DAT1__PORT 3u +#define SD_DAT1__PRT CYREG_PRT3_PRT +#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_DAT1__PS CYREG_PRT3_PS +#define SD_DAT1__SHIFT 0u +#define SD_DAT1__SLW CYREG_PRT3_SLW + +/* SD_DAT2 */ +#define SD_DAT2__0__INTTYPE CYREG_PICU3_INTTYPE5 +#define SD_DAT2__0__MASK 0x20u +#define SD_DAT2__0__PC CYREG_PRT3_PC5 +#define SD_DAT2__0__PORT 3u +#define SD_DAT2__0__SHIFT 5u +#define SD_DAT2__AG CYREG_PRT3_AG +#define SD_DAT2__AMUX CYREG_PRT3_AMUX +#define SD_DAT2__BIE CYREG_PRT3_BIE +#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_DAT2__BYP CYREG_PRT3_BYP +#define SD_DAT2__CTL CYREG_PRT3_CTL +#define SD_DAT2__DM0 CYREG_PRT3_DM0 +#define SD_DAT2__DM1 CYREG_PRT3_DM1 +#define SD_DAT2__DM2 CYREG_PRT3_DM2 +#define SD_DAT2__DR CYREG_PRT3_DR +#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS +#define SD_DAT2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN +#define SD_DAT2__MASK 0x20u +#define SD_DAT2__PORT 3u +#define SD_DAT2__PRT CYREG_PRT3_PRT +#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_DAT2__PS CYREG_PRT3_PS +#define SD_DAT2__SHIFT 5u +#define SD_DAT2__SLW CYREG_PRT3_SLW + +/* SD_MISO */ +#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1 +#define SD_MISO__0__MASK 0x02u +#define SD_MISO__0__PC CYREG_PRT3_PC1 +#define SD_MISO__0__PORT 3u +#define SD_MISO__0__SHIFT 1u +#define SD_MISO__AG CYREG_PRT3_AG +#define SD_MISO__AMUX CYREG_PRT3_AMUX +#define SD_MISO__BIE CYREG_PRT3_BIE +#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MISO__BYP CYREG_PRT3_BYP +#define SD_MISO__CTL CYREG_PRT3_CTL +#define SD_MISO__DM0 CYREG_PRT3_DM0 +#define SD_MISO__DM1 CYREG_PRT3_DM1 +#define SD_MISO__DM2 CYREG_PRT3_DM2 +#define SD_MISO__DR CYREG_PRT3_DR +#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MISO__MASK 0x02u +#define SD_MISO__PORT 3u +#define SD_MISO__PRT CYREG_PRT3_PRT +#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MISO__PS CYREG_PRT3_PS +#define SD_MISO__SHIFT 1u +#define SD_MISO__SLW CYREG_PRT3_SLW + +/* SD_MOSI */ +#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3 +#define SD_MOSI__0__MASK 0x08u +#define SD_MOSI__0__PC CYREG_PRT3_PC3 +#define SD_MOSI__0__PORT 3u +#define SD_MOSI__0__SHIFT 3u +#define SD_MOSI__AG CYREG_PRT3_AG +#define SD_MOSI__AMUX CYREG_PRT3_AMUX +#define SD_MOSI__BIE CYREG_PRT3_BIE +#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MOSI__BYP CYREG_PRT3_BYP +#define SD_MOSI__CTL CYREG_PRT3_CTL +#define SD_MOSI__DM0 CYREG_PRT3_DM0 +#define SD_MOSI__DM1 CYREG_PRT3_DM1 +#define SD_MOSI__DM2 CYREG_PRT3_DM2 +#define SD_MOSI__DR CYREG_PRT3_DR +#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MOSI__MASK 0x08u +#define SD_MOSI__PORT 3u +#define SD_MOSI__PRT CYREG_PRT3_PRT +#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MOSI__PS CYREG_PRT3_PS +#define SD_MOSI__SHIFT 3u +#define SD_MOSI__SLW CYREG_PRT3_SLW + +/* SCSI_CLK */ +#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 +#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 +#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2 +#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u +#define SCSI_CLK__INDEX 0x01u +#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SCSI_CLK__PM_ACT_MSK 0x02u +#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SCSI_CLK__PM_STBY_MSK 0x02u /* SCSI_Out */ #define SCSI_Out__0__AG CYREG_PRT4_AG @@ -2229,370 +2436,6 @@ #define SCSI_Out_DBx__DB7__SHIFT 4u #define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW -/* SCSI_Parity_Error */ -#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST -#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST - -/* SCSI_RST_ISR */ -#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RST_ISR__INTC_MASK 0x02u -#define SCSI_RST_ISR__INTC_NUMBER 1u -#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u -#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1 -#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_RX_DMA */ -#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_RX_DMA__DRQ_NUMBER 0u -#define SCSI_RX_DMA__NUMBEROF_TDS 0u -#define SCSI_RX_DMA__PRIORITY 2u -#define SCSI_RX_DMA__TERMIN_EN 0u -#define SCSI_RX_DMA__TERMIN_SEL 0u -#define SCSI_RX_DMA__TERMOUT0_EN 1u -#define SCSI_RX_DMA__TERMOUT0_SEL 0u -#define SCSI_RX_DMA__TERMOUT1_EN 0u -#define SCSI_RX_DMA__TERMOUT1_SEL 0u -#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u -#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u -#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 -#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_SEL_ISR__INTC_MASK 0x08u -#define SCSI_SEL_ISR__INTC_NUMBER 3u -#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u -#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 -#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_TX_DMA__DRQ_NUMBER 1u -#define SCSI_TX_DMA__NUMBEROF_TDS 0u -#define SCSI_TX_DMA__PRIORITY 2u -#define SCSI_TX_DMA__TERMIN_EN 0u -#define SCSI_TX_DMA__TERMIN_SEL 0u -#define SCSI_TX_DMA__TERMOUT0_EN 1u -#define SCSI_TX_DMA__TERMOUT0_SEL 1u -#define SCSI_TX_DMA__TERMOUT1_EN 0u -#define SCSI_TX_DMA__TERMOUT1_SEL 0u -#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u -#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 -#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST -#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u -#define SDCard_BSPIM_RxStsReg__4__POS 4 -#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u -#define SDCard_BSPIM_RxStsReg__5__POS 5 -#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u -#define SDCard_BSPIM_RxStsReg__6__POS 6 -#define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK -#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 -#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u -#define SDCard_BSPIM_TxStsReg__0__POS 0 -#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u -#define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST -#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u -#define SDCard_BSPIM_TxStsReg__2__POS 2 -#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u -#define SDCard_BSPIM_TxStsReg__3__POS 3 -#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u -#define SDCard_BSPIM_TxStsReg__4__POS 4 -#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST - -/* SD_CD */ -#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE6 -#define SD_CD__0__MASK 0x40u -#define SD_CD__0__PC CYREG_PRT3_PC6 -#define SD_CD__0__PORT 3u -#define SD_CD__0__SHIFT 6u -#define SD_CD__AG CYREG_PRT3_AG -#define SD_CD__AMUX CYREG_PRT3_AMUX -#define SD_CD__BIE CYREG_PRT3_BIE -#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_CD__BYP CYREG_PRT3_BYP -#define SD_CD__CTL CYREG_PRT3_CTL -#define SD_CD__DM0 CYREG_PRT3_DM0 -#define SD_CD__DM1 CYREG_PRT3_DM1 -#define SD_CD__DM2 CYREG_PRT3_DM2 -#define SD_CD__DR CYREG_PRT3_DR -#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS -#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN -#define SD_CD__MASK 0x40u -#define SD_CD__PORT 3u -#define SD_CD__PRT CYREG_PRT3_PRT -#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_CD__PS CYREG_PRT3_PS -#define SD_CD__SHIFT 6u -#define SD_CD__SLW CYREG_PRT3_SLW - -/* SD_CS */ -#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4 -#define SD_CS__0__MASK 0x10u -#define SD_CS__0__PC CYREG_PRT3_PC4 -#define SD_CS__0__PORT 3u -#define SD_CS__0__SHIFT 4u -#define SD_CS__AG CYREG_PRT3_AG -#define SD_CS__AMUX CYREG_PRT3_AMUX -#define SD_CS__BIE CYREG_PRT3_BIE -#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_CS__BYP CYREG_PRT3_BYP -#define SD_CS__CTL CYREG_PRT3_CTL -#define SD_CS__DM0 CYREG_PRT3_DM0 -#define SD_CS__DM1 CYREG_PRT3_DM1 -#define SD_CS__DM2 CYREG_PRT3_DM2 -#define SD_CS__DR CYREG_PRT3_DR -#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS -#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN -#define SD_CS__MASK 0x10u -#define SD_CS__PORT 3u -#define SD_CS__PRT CYREG_PRT3_PRT -#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_CS__PS CYREG_PRT3_PS -#define SD_CS__SHIFT 4u -#define SD_CS__SLW CYREG_PRT3_SLW - -/* SD_DAT1 */ -#define SD_DAT1__0__INTTYPE CYREG_PICU3_INTTYPE0 -#define SD_DAT1__0__MASK 0x01u -#define SD_DAT1__0__PC CYREG_PRT3_PC0 -#define SD_DAT1__0__PORT 3u -#define SD_DAT1__0__SHIFT 0u -#define SD_DAT1__AG CYREG_PRT3_AG -#define SD_DAT1__AMUX CYREG_PRT3_AMUX -#define SD_DAT1__BIE CYREG_PRT3_BIE -#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_DAT1__BYP CYREG_PRT3_BYP -#define SD_DAT1__CTL CYREG_PRT3_CTL -#define SD_DAT1__DM0 CYREG_PRT3_DM0 -#define SD_DAT1__DM1 CYREG_PRT3_DM1 -#define SD_DAT1__DM2 CYREG_PRT3_DM2 -#define SD_DAT1__DR CYREG_PRT3_DR -#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS -#define SD_DAT1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN -#define SD_DAT1__MASK 0x01u -#define SD_DAT1__PORT 3u -#define SD_DAT1__PRT CYREG_PRT3_PRT -#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_DAT1__PS CYREG_PRT3_PS -#define SD_DAT1__SHIFT 0u -#define SD_DAT1__SLW CYREG_PRT3_SLW - -/* SD_DAT2 */ -#define SD_DAT2__0__INTTYPE CYREG_PICU3_INTTYPE5 -#define SD_DAT2__0__MASK 0x20u -#define SD_DAT2__0__PC CYREG_PRT3_PC5 -#define SD_DAT2__0__PORT 3u -#define SD_DAT2__0__SHIFT 5u -#define SD_DAT2__AG CYREG_PRT3_AG -#define SD_DAT2__AMUX CYREG_PRT3_AMUX -#define SD_DAT2__BIE CYREG_PRT3_BIE -#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_DAT2__BYP CYREG_PRT3_BYP -#define SD_DAT2__CTL CYREG_PRT3_CTL -#define SD_DAT2__DM0 CYREG_PRT3_DM0 -#define SD_DAT2__DM1 CYREG_PRT3_DM1 -#define SD_DAT2__DM2 CYREG_PRT3_DM2 -#define SD_DAT2__DR CYREG_PRT3_DR -#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS -#define SD_DAT2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN -#define SD_DAT2__MASK 0x20u -#define SD_DAT2__PORT 3u -#define SD_DAT2__PRT CYREG_PRT3_PRT -#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_DAT2__PS CYREG_PRT3_PS -#define SD_DAT2__SHIFT 5u -#define SD_DAT2__SLW CYREG_PRT3_SLW - -/* SD_Data_Clk */ -#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 -#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 -#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 -#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u -#define SD_Data_Clk__INDEX 0x00u -#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define SD_Data_Clk__PM_ACT_MSK 0x01u -#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define SD_Data_Clk__PM_STBY_MSK 0x01u - -/* SD_MISO */ -#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1 -#define SD_MISO__0__MASK 0x02u -#define SD_MISO__0__PC CYREG_PRT3_PC1 -#define SD_MISO__0__PORT 3u -#define SD_MISO__0__SHIFT 1u -#define SD_MISO__AG CYREG_PRT3_AG -#define SD_MISO__AMUX CYREG_PRT3_AMUX -#define SD_MISO__BIE CYREG_PRT3_BIE -#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_MISO__BYP CYREG_PRT3_BYP -#define SD_MISO__CTL CYREG_PRT3_CTL -#define SD_MISO__DM0 CYREG_PRT3_DM0 -#define SD_MISO__DM1 CYREG_PRT3_DM1 -#define SD_MISO__DM2 CYREG_PRT3_DM2 -#define SD_MISO__DR CYREG_PRT3_DR -#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS -#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN -#define SD_MISO__MASK 0x02u -#define SD_MISO__PORT 3u -#define SD_MISO__PRT CYREG_PRT3_PRT -#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_MISO__PS CYREG_PRT3_PS -#define SD_MISO__SHIFT 1u -#define SD_MISO__SLW CYREG_PRT3_SLW - -/* SD_MOSI */ -#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3 -#define SD_MOSI__0__MASK 0x08u -#define SD_MOSI__0__PC CYREG_PRT3_PC3 -#define SD_MOSI__0__PORT 3u -#define SD_MOSI__0__SHIFT 3u -#define SD_MOSI__AG CYREG_PRT3_AG -#define SD_MOSI__AMUX CYREG_PRT3_AMUX -#define SD_MOSI__BIE CYREG_PRT3_BIE -#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_MOSI__BYP CYREG_PRT3_BYP -#define SD_MOSI__CTL CYREG_PRT3_CTL -#define SD_MOSI__DM0 CYREG_PRT3_DM0 -#define SD_MOSI__DM1 CYREG_PRT3_DM1 -#define SD_MOSI__DM2 CYREG_PRT3_DM2 -#define SD_MOSI__DR CYREG_PRT3_DR -#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS -#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN -#define SD_MOSI__MASK 0x08u -#define SD_MOSI__PORT 3u -#define SD_MOSI__PRT CYREG_PRT3_PRT -#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_MOSI__PS CYREG_PRT3_PS -#define SD_MOSI__SHIFT 3u -#define SD_MOSI__SLW CYREG_PRT3_SLW - /* SD_RX_DMA */ #define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_RX_DMA__DRQ_NUMBER 2u @@ -2613,40 +2456,6 @@ #define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -/* SD_SCK */ -#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2 -#define SD_SCK__0__MASK 0x04u -#define SD_SCK__0__PC CYREG_PRT3_PC2 -#define SD_SCK__0__PORT 3u -#define SD_SCK__0__SHIFT 2u -#define SD_SCK__AG CYREG_PRT3_AG -#define SD_SCK__AMUX CYREG_PRT3_AMUX -#define SD_SCK__BIE CYREG_PRT3_BIE -#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_SCK__BYP CYREG_PRT3_BYP -#define SD_SCK__CTL CYREG_PRT3_CTL -#define SD_SCK__DM0 CYREG_PRT3_DM0 -#define SD_SCK__DM1 CYREG_PRT3_DM1 -#define SD_SCK__DM2 CYREG_PRT3_DM2 -#define SD_SCK__DR CYREG_PRT3_DR -#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS -#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN -#define SD_SCK__MASK 0x04u -#define SD_SCK__PORT 3u -#define SD_SCK__PRT CYREG_PRT3_PRT -#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_SCK__PS CYREG_PRT3_PS -#define SD_SCK__SHIFT 2u -#define SD_SCK__SLW CYREG_PRT3_SLW - /* SD_TX_DMA */ #define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_TX_DMA__DRQ_NUMBER 3u @@ -2667,269 +2476,285 @@ #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -/* USBFS */ -#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_arb_int__INTC_MASK 0x400000u -#define USBFS_arb_int__INTC_NUMBER 22u -#define USBFS_arb_int__INTC_PRIOR_NUM 6u -#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 -#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_bus_reset__INTC_MASK 0x800000u -#define USBFS_bus_reset__INTC_NUMBER 23u -#define USBFS_bus_reset__INTC_PRIOR_NUM 7u -#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 -#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7 -#define USBFS_Dm__0__MASK 0x80u -#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 -#define USBFS_Dm__0__PORT 15u -#define USBFS_Dm__0__SHIFT 7u -#define USBFS_Dm__AG CYREG_PRT15_AG -#define USBFS_Dm__AMUX CYREG_PRT15_AMUX -#define USBFS_Dm__BIE CYREG_PRT15_BIE -#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK -#define USBFS_Dm__BYP CYREG_PRT15_BYP -#define USBFS_Dm__CTL CYREG_PRT15_CTL -#define USBFS_Dm__DM0 CYREG_PRT15_DM0 -#define USBFS_Dm__DM1 CYREG_PRT15_DM1 -#define USBFS_Dm__DM2 CYREG_PRT15_DM2 -#define USBFS_Dm__DR CYREG_PRT15_DR -#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS -#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE -#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG -#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN -#define USBFS_Dm__MASK 0x80u -#define USBFS_Dm__PORT 15u -#define USBFS_Dm__PRT CYREG_PRT15_PRT -#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL -#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN -#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 -#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 -#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 -#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 -#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT -#define USBFS_Dm__PS CYREG_PRT15_PS -#define USBFS_Dm__SHIFT 7u -#define USBFS_Dm__SLW CYREG_PRT15_SLW -#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6 -#define USBFS_Dp__0__MASK 0x40u -#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 -#define USBFS_Dp__0__PORT 15u -#define USBFS_Dp__0__SHIFT 6u -#define USBFS_Dp__AG CYREG_PRT15_AG -#define USBFS_Dp__AMUX CYREG_PRT15_AMUX -#define USBFS_Dp__BIE CYREG_PRT15_BIE -#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK -#define USBFS_Dp__BYP CYREG_PRT15_BYP -#define USBFS_Dp__CTL CYREG_PRT15_CTL -#define USBFS_Dp__DM0 CYREG_PRT15_DM0 -#define USBFS_Dp__DM1 CYREG_PRT15_DM1 -#define USBFS_Dp__DM2 CYREG_PRT15_DM2 -#define USBFS_Dp__DR CYREG_PRT15_DR -#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS -#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT -#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE -#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG -#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN -#define USBFS_Dp__MASK 0x40u -#define USBFS_Dp__PORT 15u -#define USBFS_Dp__PRT CYREG_PRT15_PRT -#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL -#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN -#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 -#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 -#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 -#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 -#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT -#define USBFS_Dp__PS CYREG_PRT15_PS -#define USBFS_Dp__SHIFT 6u -#define USBFS_Dp__SLW CYREG_PRT15_SLW -#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 -#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_dp_int__INTC_MASK 0x1000u -#define USBFS_dp_int__INTC_NUMBER 12u -#define USBFS_dp_int__INTC_PRIOR_NUM 7u -#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 -#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_0__INTC_MASK 0x1000000u -#define USBFS_ep_0__INTC_NUMBER 24u -#define USBFS_ep_0__INTC_PRIOR_NUM 7u -#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 -#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x80u -#define USBFS_ep_1__INTC_NUMBER 7u -#define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 -#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x100u -#define USBFS_ep_2__INTC_NUMBER 8u -#define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 -#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_3__INTC_MASK 0x200u -#define USBFS_ep_3__INTC_NUMBER 9u -#define USBFS_ep_3__INTC_PRIOR_NUM 7u -#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 -#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_4__INTC_MASK 0x400u -#define USBFS_ep_4__INTC_NUMBER 10u -#define USBFS_ep_4__INTC_PRIOR_NUM 7u -#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 -#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_sof_int__INTC_MASK 0x200000u -#define USBFS_sof_int__INTC_NUMBER 21u -#define USBFS_sof_int__INTC_PRIOR_NUM 7u -#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 -#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG -#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG -#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN -#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR -#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG -#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN -#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR -#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG -#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN -#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR -#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG -#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN -#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR -#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG -#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN -#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR -#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG -#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN -#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR -#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG -#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN -#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR -#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG -#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN -#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR -#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN -#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR -#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR -#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA -#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB -#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA -#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB -#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR -#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA -#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB -#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA -#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB -#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR -#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA -#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB -#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA -#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB -#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR -#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA -#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB -#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA -#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB -#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR -#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA -#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB -#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA -#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB -#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR -#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA -#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB -#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA -#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB -#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR -#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA -#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB -#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA -#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB -#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR -#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA -#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB -#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA -#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB -#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE -#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT -#define USBFS_USB__CR0 CYREG_USB_CR0 -#define USBFS_USB__CR1 CYREG_USB_CR1 -#define USBFS_USB__CWA CYREG_USB_CWA -#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB -#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES -#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB -#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG -#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE -#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE -#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT -#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR -#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 -#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 -#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 -#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 -#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 -#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 -#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 -#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 -#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE -#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 -#define USBFS_USB__PM_ACT_MSK 0x01u -#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 -#define USBFS_USB__PM_STBY_MSK 0x01u -#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN -#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR -#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 -#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 -#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 -#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 -#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 -#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 -#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 -#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 -#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 -#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 -#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 -#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 -#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 -#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 -#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 -#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 -#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 -#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 -#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 -#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 -#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 -#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 -#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 -#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 -#define USBFS_USB__SOF0 CYREG_USB_SOF0 -#define USBFS_USB__SOF1 CYREG_USB_SOF1 -#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN -#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 -#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 +/* SCSI_Noise */ +#define SCSI_Noise__0__AG CYREG_PRT12_AG +#define SCSI_Noise__0__BIE CYREG_PRT12_BIE +#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_Noise__0__BYP CYREG_PRT12_BYP +#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0 +#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1 +#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2 +#define SCSI_Noise__0__DR CYREG_PRT12_DR +#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_Noise__0__INTTYPE CYREG_PICU12_INTTYPE5 +#define SCSI_Noise__0__MASK 0x20u +#define SCSI_Noise__0__PC CYREG_PRT12_PC5 +#define SCSI_Noise__0__PORT 12u +#define SCSI_Noise__0__PRT CYREG_PRT12_PRT +#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_Noise__0__PS CYREG_PRT12_PS +#define SCSI_Noise__0__SHIFT 5u +#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_Noise__0__SLW CYREG_PRT12_SLW +#define SCSI_Noise__1__AG CYREG_PRT6_AG +#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__1__BIE CYREG_PRT6_BIE +#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__1__BYP CYREG_PRT6_BYP +#define SCSI_Noise__1__CTL CYREG_PRT6_CTL +#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__1__DR CYREG_PRT6_DR +#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__1__INTTYPE CYREG_PICU6_INTTYPE4 +#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__1__MASK 0x10u +#define SCSI_Noise__1__PC CYREG_PRT6_PC4 +#define SCSI_Noise__1__PORT 6u +#define SCSI_Noise__1__PRT CYREG_PRT6_PRT +#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__1__PS CYREG_PRT6_PS +#define SCSI_Noise__1__SHIFT 4u +#define SCSI_Noise__1__SLW CYREG_PRT6_SLW +#define SCSI_Noise__2__AG CYREG_PRT5_AG +#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX +#define SCSI_Noise__2__BIE CYREG_PRT5_BIE +#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Noise__2__BYP CYREG_PRT5_BYP +#define SCSI_Noise__2__CTL CYREG_PRT5_CTL +#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0 +#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1 +#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2 +#define SCSI_Noise__2__DR CYREG_PRT5_DR +#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Noise__2__INTTYPE CYREG_PICU5_INTTYPE0 +#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Noise__2__MASK 0x01u +#define SCSI_Noise__2__PC CYREG_PRT5_PC0 +#define SCSI_Noise__2__PORT 5u +#define SCSI_Noise__2__PRT CYREG_PRT5_PRT +#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Noise__2__PS CYREG_PRT5_PS +#define SCSI_Noise__2__SHIFT 0u +#define SCSI_Noise__2__SLW CYREG_PRT5_SLW +#define SCSI_Noise__3__AG CYREG_PRT6_AG +#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__3__BIE CYREG_PRT6_BIE +#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__3__BYP CYREG_PRT6_BYP +#define SCSI_Noise__3__CTL CYREG_PRT6_CTL +#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__3__DR CYREG_PRT6_DR +#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__3__INTTYPE CYREG_PICU6_INTTYPE6 +#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__3__MASK 0x40u +#define SCSI_Noise__3__PC CYREG_PRT6_PC6 +#define SCSI_Noise__3__PORT 6u +#define SCSI_Noise__3__PRT CYREG_PRT6_PRT +#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__3__PS CYREG_PRT6_PS +#define SCSI_Noise__3__SHIFT 6u +#define SCSI_Noise__3__SLW CYREG_PRT6_SLW +#define SCSI_Noise__4__AG CYREG_PRT6_AG +#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__4__BIE CYREG_PRT6_BIE +#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__4__BYP CYREG_PRT6_BYP +#define SCSI_Noise__4__CTL CYREG_PRT6_CTL +#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__4__DR CYREG_PRT6_DR +#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__4__INTTYPE CYREG_PICU6_INTTYPE5 +#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__4__MASK 0x20u +#define SCSI_Noise__4__PC CYREG_PRT6_PC5 +#define SCSI_Noise__4__PORT 6u +#define SCSI_Noise__4__PRT CYREG_PRT6_PRT +#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__4__PS CYREG_PRT6_PS +#define SCSI_Noise__4__SHIFT 5u +#define SCSI_Noise__4__SLW CYREG_PRT6_SLW +#define SCSI_Noise__ACK__AG CYREG_PRT6_AG +#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE +#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP +#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL +#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__ACK__DR CYREG_PRT6_DR +#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__ACK__INTTYPE CYREG_PICU6_INTTYPE5 +#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__ACK__MASK 0x20u +#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5 +#define SCSI_Noise__ACK__PORT 6u +#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT +#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__ACK__PS CYREG_PRT6_PS +#define SCSI_Noise__ACK__SHIFT 5u +#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW +#define SCSI_Noise__ATN__AG CYREG_PRT12_AG +#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE +#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP +#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0 +#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1 +#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2 +#define SCSI_Noise__ATN__DR CYREG_PRT12_DR +#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_Noise__ATN__INTTYPE CYREG_PICU12_INTTYPE5 +#define SCSI_Noise__ATN__MASK 0x20u +#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5 +#define SCSI_Noise__ATN__PORT 12u +#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT +#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_Noise__ATN__PS CYREG_PRT12_PS +#define SCSI_Noise__ATN__SHIFT 5u +#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW +#define SCSI_Noise__BSY__AG CYREG_PRT6_AG +#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE +#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP +#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL +#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__BSY__DR CYREG_PRT6_DR +#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__BSY__INTTYPE CYREG_PICU6_INTTYPE4 +#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__BSY__MASK 0x10u +#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4 +#define SCSI_Noise__BSY__PORT 6u +#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT +#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__BSY__PS CYREG_PRT6_PS +#define SCSI_Noise__BSY__SHIFT 4u +#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW +#define SCSI_Noise__RST__AG CYREG_PRT6_AG +#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE +#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP +#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL +#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__RST__DR CYREG_PRT6_DR +#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__RST__INTTYPE CYREG_PICU6_INTTYPE6 +#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__RST__MASK 0x40u +#define SCSI_Noise__RST__PC CYREG_PRT6_PC6 +#define SCSI_Noise__RST__PORT 6u +#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT +#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__RST__PS CYREG_PRT6_PS +#define SCSI_Noise__RST__SHIFT 6u +#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW +#define SCSI_Noise__SEL__AG CYREG_PRT5_AG +#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX +#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE +#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP +#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL +#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0 +#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1 +#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2 +#define SCSI_Noise__SEL__DR CYREG_PRT5_DR +#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Noise__SEL__INTTYPE CYREG_PICU5_INTTYPE0 +#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Noise__SEL__MASK 0x01u +#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0 +#define SCSI_Noise__SEL__PORT 5u +#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT +#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Noise__SEL__PS CYREG_PRT5_PS +#define SCSI_Noise__SEL__SHIFT 0u +#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW /* scsiTarget */ #define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0 @@ -2998,6 +2823,83 @@ #define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL #define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB07_ST +/* Debug_Timer */ +#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define Debug_Timer_Interrupt__INTC_MASK 0x01u +#define Debug_Timer_Interrupt__INTC_NUMBER 0u +#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u +#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0 +#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1 +#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0 +#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1 +#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2 +#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 +#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 +#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0 +#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1 +#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 +#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u +#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 +#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u +#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0 +#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1 +#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0 + +/* SCSI_RX_DMA */ +#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_RX_DMA__DRQ_NUMBER 0u +#define SCSI_RX_DMA__NUMBEROF_TDS 0u +#define SCSI_RX_DMA__PRIORITY 2u +#define SCSI_RX_DMA__TERMIN_EN 0u +#define SCSI_RX_DMA__TERMIN_SEL 0u +#define SCSI_RX_DMA__TERMOUT0_EN 1u +#define SCSI_RX_DMA__TERMOUT0_SEL 0u +#define SCSI_RX_DMA__TERMOUT1_EN 0u +#define SCSI_RX_DMA__TERMOUT1_SEL 0u +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u +#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_TX_DMA__DRQ_NUMBER 1u +#define SCSI_TX_DMA__NUMBEROF_TDS 0u +#define SCSI_TX_DMA__PRIORITY 2u +#define SCSI_TX_DMA__TERMIN_EN 0u +#define SCSI_TX_DMA__TERMIN_SEL 0u +#define SCSI_TX_DMA__TERMOUT0_EN 1u +#define SCSI_TX_DMA__TERMOUT0_SEL 1u +#define SCSI_TX_DMA__TERMOUT1_EN 0u +#define SCSI_TX_DMA__TERMOUT1_SEL 0u +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u +#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SD_Data_Clk */ +#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 +#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 +#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 +#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u +#define SD_Data_Clk__INDEX 0x00u +#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SD_Data_Clk__PM_ACT_MSK 0x01u +#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SD_Data_Clk__PM_STBY_MSK 0x01u + /* timer_clock */ #define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0 #define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1 @@ -3009,14 +2911,110 @@ #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2 #define timer_clock__PM_STBY_MSK 0x04u +/* SCSI_RST_ISR */ +#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RST_ISR__INTC_MASK 0x02u +#define SCSI_RST_ISR__INTC_NUMBER 1u +#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u +#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_SEL_ISR__INTC_MASK 0x08u +#define SCSI_SEL_ISR__INTC_NUMBER 3u +#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u +#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_Filtered */ +#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u +#define SCSI_Filtered_sts_sts_reg__0__POS 0 +#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u +#define SCSI_Filtered_sts_sts_reg__1__POS 1 +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST +#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u +#define SCSI_Filtered_sts_sts_reg__2__POS 2 +#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u +#define SCSI_Filtered_sts_sts_reg__3__POS 3 +#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u +#define SCSI_Filtered_sts_sts_reg__4__POS 4 +#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST + +/* SCSI_CTL_PHASE */ +#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK + +/* SCSI_Glitch_Ctl */ +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK + +/* SCSI_Parity_Error */ +#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__0__POS 0 +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST + /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U #define BCLK__BUS_CLK__KHZ 50000U #define BCLK__BUS_CLK__MHZ 50U #define CY_PROJECT_NAME "SCSI2SD" -#define CY_VERSION "PSoC Creator 4.1" +#define CY_VERSION "PSoC Creator 4.2" #define CYDEV_CHIP_DIE_LEOPARD 1u -#define CYDEV_CHIP_DIE_PSOC4A 16u +#define CYDEV_CHIP_DIE_PSOC4A 18u #define CYDEV_CHIP_DIE_PSOC5LP 2u #define CYDEV_CHIP_DIE_PSOC5TM 3u #define CYDEV_CHIP_DIE_TMA4 4u @@ -3032,32 +3030,34 @@ #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 #define CYDEV_CHIP_JTAG_ID 0x2E133069u #define CYDEV_CHIP_MEMBER_3A 1u -#define CYDEV_CHIP_MEMBER_4A 16u -#define CYDEV_CHIP_MEMBER_4D 12u +#define CYDEV_CHIP_MEMBER_4A 18u +#define CYDEV_CHIP_MEMBER_4D 13u #define CYDEV_CHIP_MEMBER_4E 6u -#define CYDEV_CHIP_MEMBER_4F 17u +#define CYDEV_CHIP_MEMBER_4F 19u #define CYDEV_CHIP_MEMBER_4G 4u -#define CYDEV_CHIP_MEMBER_4H 15u -#define CYDEV_CHIP_MEMBER_4I 21u -#define CYDEV_CHIP_MEMBER_4J 13u -#define CYDEV_CHIP_MEMBER_4K 14u -#define CYDEV_CHIP_MEMBER_4L 20u -#define CYDEV_CHIP_MEMBER_4M 19u -#define CYDEV_CHIP_MEMBER_4N 9u +#define CYDEV_CHIP_MEMBER_4H 17u +#define CYDEV_CHIP_MEMBER_4I 23u +#define CYDEV_CHIP_MEMBER_4J 14u +#define CYDEV_CHIP_MEMBER_4K 15u +#define CYDEV_CHIP_MEMBER_4L 22u +#define CYDEV_CHIP_MEMBER_4M 21u +#define CYDEV_CHIP_MEMBER_4N 10u #define CYDEV_CHIP_MEMBER_4O 7u -#define CYDEV_CHIP_MEMBER_4P 18u -#define CYDEV_CHIP_MEMBER_4Q 11u +#define CYDEV_CHIP_MEMBER_4P 20u +#define CYDEV_CHIP_MEMBER_4Q 12u #define CYDEV_CHIP_MEMBER_4R 8u -#define CYDEV_CHIP_MEMBER_4S 10u +#define CYDEV_CHIP_MEMBER_4S 11u +#define CYDEV_CHIP_MEMBER_4T 9u #define CYDEV_CHIP_MEMBER_4U 5u +#define CYDEV_CHIP_MEMBER_4V 16u #define CYDEV_CHIP_MEMBER_5A 3u #define CYDEV_CHIP_MEMBER_5B 2u -#define CYDEV_CHIP_MEMBER_6A 22u -#define CYDEV_CHIP_MEMBER_FM3 26u -#define CYDEV_CHIP_MEMBER_FM4 27u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 23u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 24u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 25u +#define CYDEV_CHIP_MEMBER_6A 24u +#define CYDEV_CHIP_MEMBER_FM3 28u +#define CYDEV_CHIP_MEMBER_FM4 29u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u #define CYDEV_CHIP_MEMBER_UNKNOWN 0u #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED @@ -3083,6 +3083,7 @@ #define CYDEV_CHIP_REVISION_4A_ES0 17u #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u #define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u #define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u @@ -3102,14 +3103,17 @@ #define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u #define CYDEV_CHIP_REVISION_5A_ES0 0u #define CYDEV_CHIP_REVISION_5A_ES1 1u #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u #define CYDEV_CHIP_REVISION_5B_ES0 0u #define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u -#define CYDEV_CHIP_REVISION_6A_NO_UDB 0u -#define CYDEV_CHIP_REVISION_6A_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_6A_ES 17u +#define CYDEV_CHIP_REVISION_6A_NO_UDB 33u +#define CYDEV_CHIP_REVISION_6A_PRODUCTION 33u #define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u #define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u #define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 5800f1e..829dd7b 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -2,7 +2,7 @@ /******************************************************************************* * File Name: cyfitter_cfg.c * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file contains device initialization code. @@ -10,7 +10,7 @@ * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -101,6 +101,7 @@ static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) #define CYCLOCKSTART_32KHZ_ERROR 2u #define CYCLOCKSTART_PLL_ERROR 3u #define CYCLOCKSTART_FLL_ERROR 4u +#define CYCLOCKSTART_WCO_ERROR 5u #ifdef CY_NEED_CYCLOCKSTARTUPERROR @@ -124,12 +125,8 @@ static void CyClockStartupError(uint8 errorCode); CY_CFG_UNUSED static void CyClockStartupError(uint8 errorCode) { - /* To remove the compiler warning if errorCode not used. */ -#if defined(CY_PSOC3) && (CY_PSOC3) + /* To remove the compiler warning if errorCode not used. */ errorCode = errorCode; -#else - (void)errorCode; -#endif /* CY_PSOC3 */ /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ /* we will end up here to allow the customer to implement something to */ @@ -403,7 +400,7 @@ void cyfitter_cfg(void) /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */ - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u)); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x61u : 0x60u)); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Set Flash Cycles based on newly configured 50.00MHz Bus Clock. */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h index 3a40dcb..fea1312 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfitter_cfg.h * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file provides basic startup and mux configuration settings * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 33a4bd8..467e72b 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfittergnu.inc * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,34 +19,6 @@ .include "cydevicegnu.inc" .include "cydevicegnu_trm.inc" -/* Debug_Timer_Interrupt */ -.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set Debug_Timer_Interrupt__INTC_MASK, 0x01 -.set Debug_Timer_Interrupt__INTC_NUMBER, 0 -.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7 -.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 -.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0 -.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1 -.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0 -.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1 -.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2 -.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0 -.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1 -.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0 -.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1 -.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3 -.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01 -.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3 -.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01 -.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0 -.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1 -.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0 - /* LED1 */ .set LED1__0__INTTYPE, CYREG_PICU12_INTTYPE3 .set LED1__0__MASK, 0x08 @@ -80,82 +52,450 @@ .set LED1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ .set LED1__SLW, CYREG_PRT12_SLW -/* SCSI_CLK */ -.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 -.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 -.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2 -.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07 -.set SCSI_CLK__INDEX, 0x01 -.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set SCSI_CLK__PM_ACT_MSK, 0x02 -.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set SCSI_CLK__PM_STBY_MSK, 0x02 +/* SD_CD */ +.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE6 +.set SD_CD__0__MASK, 0x40 +.set SD_CD__0__PC, CYREG_PRT3_PC6 +.set SD_CD__0__PORT, 3 +.set SD_CD__0__SHIFT, 6 +.set SD_CD__AG, CYREG_PRT3_AG +.set SD_CD__AMUX, CYREG_PRT3_AMUX +.set SD_CD__BIE, CYREG_PRT3_BIE +.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CD__BYP, CYREG_PRT3_BYP +.set SD_CD__CTL, CYREG_PRT3_CTL +.set SD_CD__DM0, CYREG_PRT3_DM0 +.set SD_CD__DM1, CYREG_PRT3_DM1 +.set SD_CD__DM2, CYREG_PRT3_DM2 +.set SD_CD__DR, CYREG_PRT3_DR +.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CD__MASK, 0x40 +.set SD_CD__PORT, 3 +.set SD_CD__PRT, CYREG_PRT3_PRT +.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CD__PS, CYREG_PRT3_PS +.set SD_CD__SHIFT, 6 +.set SD_CD__SLW, CYREG_PRT3_SLW -/* SCSI_CTL_PHASE */ -.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK +/* SD_CS */ +.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4 +.set SD_CS__0__MASK, 0x10 +.set SD_CS__0__PC, CYREG_PRT3_PC4 +.set SD_CS__0__PORT, 3 +.set SD_CS__0__SHIFT, 4 +.set SD_CS__AG, CYREG_PRT3_AG +.set SD_CS__AMUX, CYREG_PRT3_AMUX +.set SD_CS__BIE, CYREG_PRT3_BIE +.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CS__BYP, CYREG_PRT3_BYP +.set SD_CS__CTL, CYREG_PRT3_CTL +.set SD_CS__DM0, CYREG_PRT3_DM0 +.set SD_CS__DM1, CYREG_PRT3_DM1 +.set SD_CS__DM2, CYREG_PRT3_DM2 +.set SD_CS__DR, CYREG_PRT3_DR +.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CS__MASK, 0x10 +.set SD_CS__PORT, 3 +.set SD_CS__PRT, CYREG_PRT3_PRT +.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CS__PS, CYREG_PRT3_PS +.set SD_CS__SHIFT, 4 +.set SD_CS__SLW, CYREG_PRT3_SLW -/* SCSI_Filtered */ -.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 -.set SCSI_Filtered_sts_sts_reg__0__POS, 0 -.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 -.set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST -.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 -.set SCSI_Filtered_sts_sts_reg__2__POS, 2 -.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 -.set SCSI_Filtered_sts_sts_reg__3__POS, 3 -.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 -.set SCSI_Filtered_sts_sts_reg__4__POS, 4 -.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST +/* USBFS */ +.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_arb_int__INTC_MASK, 0x400000 +.set USBFS_arb_int__INTC_NUMBER, 22 +.set USBFS_arb_int__INTC_PRIOR_NUM, 6 +.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 +.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_bus_reset__INTC_MASK, 0x800000 +.set USBFS_bus_reset__INTC_NUMBER, 23 +.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 +.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 +.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7 +.set USBFS_Dm__0__MASK, 0x80 +.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 +.set USBFS_Dm__0__PORT, 15 +.set USBFS_Dm__0__SHIFT, 7 +.set USBFS_Dm__AG, CYREG_PRT15_AG +.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dm__BIE, CYREG_PRT15_BIE +.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dm__BYP, CYREG_PRT15_BYP +.set USBFS_Dm__CTL, CYREG_PRT15_CTL +.set USBFS_Dm__DM0, CYREG_PRT15_DM0 +.set USBFS_Dm__DM1, CYREG_PRT15_DM1 +.set USBFS_Dm__DM2, CYREG_PRT15_DM2 +.set USBFS_Dm__DR, CYREG_PRT15_DR +.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dm__MASK, 0x80 +.set USBFS_Dm__PORT, 15 +.set USBFS_Dm__PRT, CYREG_PRT15_PRT +.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dm__PS, CYREG_PRT15_PS +.set USBFS_Dm__SHIFT, 7 +.set USBFS_Dm__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6 +.set USBFS_Dp__0__MASK, 0x40 +.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 +.set USBFS_Dp__0__PORT, 15 +.set USBFS_Dp__0__SHIFT, 6 +.set USBFS_Dp__AG, CYREG_PRT15_AG +.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dp__BIE, CYREG_PRT15_BIE +.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dp__BYP, CYREG_PRT15_BYP +.set USBFS_Dp__CTL, CYREG_PRT15_CTL +.set USBFS_Dp__DM0, CYREG_PRT15_DM0 +.set USBFS_Dp__DM1, CYREG_PRT15_DM1 +.set USBFS_Dp__DM2, CYREG_PRT15_DM2 +.set USBFS_Dp__DR, CYREG_PRT15_DR +.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT +.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dp__MASK, 0x40 +.set USBFS_Dp__PORT, 15 +.set USBFS_Dp__PRT, CYREG_PRT15_PRT +.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dp__PS, CYREG_PRT15_PS +.set USBFS_Dp__SHIFT, 6 +.set USBFS_Dp__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 +.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_dp_int__INTC_MASK, 0x1000 +.set USBFS_dp_int__INTC_NUMBER, 12 +.set USBFS_dp_int__INTC_PRIOR_NUM, 7 +.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 +.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_0__INTC_MASK, 0x1000000 +.set USBFS_ep_0__INTC_NUMBER, 24 +.set USBFS_ep_0__INTC_PRIOR_NUM, 7 +.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 +.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_1__INTC_MASK, 0x80 +.set USBFS_ep_1__INTC_NUMBER, 7 +.set USBFS_ep_1__INTC_PRIOR_NUM, 7 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 +.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_2__INTC_MASK, 0x100 +.set USBFS_ep_2__INTC_NUMBER, 8 +.set USBFS_ep_2__INTC_PRIOR_NUM, 7 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 +.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_3__INTC_MASK, 0x200 +.set USBFS_ep_3__INTC_NUMBER, 9 +.set USBFS_ep_3__INTC_PRIOR_NUM, 7 +.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 +.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_4__INTC_MASK, 0x400 +.set USBFS_ep_4__INTC_NUMBER, 10 +.set USBFS_ep_4__INTC_PRIOR_NUM, 7 +.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 +.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_sof_int__INTC_MASK, 0x200000 +.set USBFS_sof_int__INTC_NUMBER, 21 +.set USBFS_sof_int__INTC_PRIOR_NUM, 7 +.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 +.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG +.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG +.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN +.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR +.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG +.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN +.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR +.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG +.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN +.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR +.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG +.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN +.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR +.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG +.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN +.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR +.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG +.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN +.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR +.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG +.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN +.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR +.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG +.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN +.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR +.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN +.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR +.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR +.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA +.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB +.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA +.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB +.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR +.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA +.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB +.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA +.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB +.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR +.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA +.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB +.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA +.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB +.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR +.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA +.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB +.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA +.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB +.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR +.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA +.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB +.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA +.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB +.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR +.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA +.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB +.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA +.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB +.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR +.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA +.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB +.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA +.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB +.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR +.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA +.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB +.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA +.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB +.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE +.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT +.set USBFS_USB__CR0, CYREG_USB_CR0 +.set USBFS_USB__CR1, CYREG_USB_CR1 +.set USBFS_USB__CWA, CYREG_USB_CWA +.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB +.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES +.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB +.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG +.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE +.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE +.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT +.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR +.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 +.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 +.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 +.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 +.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 +.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 +.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 +.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 +.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE +.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 +.set USBFS_USB__PM_ACT_MSK, 0x01 +.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 +.set USBFS_USB__PM_STBY_MSK, 0x01 +.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN +.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR +.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 +.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 +.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 +.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 +.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 +.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 +.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 +.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 +.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 +.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 +.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 +.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 +.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 +.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 +.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 +.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 +.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 +.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 +.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 +.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 +.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 +.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 +.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 +.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 +.set USBFS_USB__SOF0, CYREG_USB_SOF0 +.set USBFS_USB__SOF1, CYREG_USB_SOF1 +.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN +.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 +.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 -/* SCSI_Glitch_Ctl */ -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK +/* SDCard */ +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST +.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_RxStsReg__4__POS, 4 +.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 +.set SDCard_BSPIM_RxStsReg__5__POS, 5 +.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 +.set SDCard_BSPIM_RxStsReg__6__POS, 6 +.set SDCard_BSPIM_RxStsReg__MASK, 0x70 +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK +.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB08_ST_CTL +.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB08_ST_CTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 +.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 +.set SDCard_BSPIM_TxStsReg__0__POS, 0 +.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 +.set SDCard_BSPIM_TxStsReg__1__POS, 1 +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 +.set SDCard_BSPIM_TxStsReg__2__POS, 2 +.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 +.set SDCard_BSPIM_TxStsReg__3__POS, 3 +.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_TxStsReg__4__POS, 4 +.set SDCard_BSPIM_TxStsReg__MASK, 0x1F +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST + +/* SD_SCK */ +.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2 +.set SD_SCK__0__MASK, 0x04 +.set SD_SCK__0__PC, CYREG_PRT3_PC2 +.set SD_SCK__0__PORT, 3 +.set SD_SCK__0__SHIFT, 2 +.set SD_SCK__AG, CYREG_PRT3_AG +.set SD_SCK__AMUX, CYREG_PRT3_AMUX +.set SD_SCK__BIE, CYREG_PRT3_BIE +.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_SCK__BYP, CYREG_PRT3_BYP +.set SD_SCK__CTL, CYREG_PRT3_CTL +.set SD_SCK__DM0, CYREG_PRT3_DM0 +.set SD_SCK__DM1, CYREG_PRT3_DM1 +.set SD_SCK__DM2, CYREG_PRT3_DM2 +.set SD_SCK__DR, CYREG_PRT3_DR +.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_SCK__MASK, 0x04 +.set SD_SCK__PORT, 3 +.set SD_SCK__PRT, CYREG_PRT3_PRT +.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_SCK__PS, CYREG_PRT3_PS +.set SD_SCK__SHIFT, 2 +.set SD_SCK__SLW, CYREG_PRT3_SLW /* SCSI_In */ .set SCSI_In__0__AG, CYREG_PRT2_AG @@ -885,285 +1225,152 @@ .set SCSI_In_DBx__DB7__SHIFT, 1 .set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW -/* SCSI_Noise */ -.set SCSI_Noise__0__AG, CYREG_PRT12_AG -.set SCSI_Noise__0__BIE, CYREG_PRT12_BIE -.set SCSI_Noise__0__BIT_MASK, CYREG_PRT12_BIT_MASK -.set SCSI_Noise__0__BYP, CYREG_PRT12_BYP -.set SCSI_Noise__0__DM0, CYREG_PRT12_DM0 -.set SCSI_Noise__0__DM1, CYREG_PRT12_DM1 -.set SCSI_Noise__0__DM2, CYREG_PRT12_DM2 -.set SCSI_Noise__0__DR, CYREG_PRT12_DR -.set SCSI_Noise__0__INP_DIS, CYREG_PRT12_INP_DIS -.set SCSI_Noise__0__INTTYPE, CYREG_PICU12_INTTYPE5 -.set SCSI_Noise__0__MASK, 0x20 -.set SCSI_Noise__0__PC, CYREG_PRT12_PC5 -.set SCSI_Noise__0__PORT, 12 -.set SCSI_Noise__0__PRT, CYREG_PRT12_PRT -.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN -.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 -.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 -.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 -.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 -.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT -.set SCSI_Noise__0__PS, CYREG_PRT12_PS -.set SCSI_Noise__0__SHIFT, 5 -.set SCSI_Noise__0__SIO_CFG, CYREG_PRT12_SIO_CFG -.set SCSI_Noise__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF -.set SCSI_Noise__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN -.set SCSI_Noise__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ -.set SCSI_Noise__0__SLW, CYREG_PRT12_SLW -.set SCSI_Noise__1__AG, CYREG_PRT6_AG -.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__1__DR, CYREG_PRT6_DR -.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__1__INTTYPE, CYREG_PICU6_INTTYPE4 -.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__1__MASK, 0x10 -.set SCSI_Noise__1__PC, CYREG_PRT6_PC4 -.set SCSI_Noise__1__PORT, 6 -.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__1__PS, CYREG_PRT6_PS -.set SCSI_Noise__1__SHIFT, 4 -.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__2__AG, CYREG_PRT5_AG -.set SCSI_Noise__2__AMUX, CYREG_PRT5_AMUX -.set SCSI_Noise__2__BIE, CYREG_PRT5_BIE -.set SCSI_Noise__2__BIT_MASK, CYREG_PRT5_BIT_MASK -.set SCSI_Noise__2__BYP, CYREG_PRT5_BYP -.set SCSI_Noise__2__CTL, CYREG_PRT5_CTL -.set SCSI_Noise__2__DM0, CYREG_PRT5_DM0 -.set SCSI_Noise__2__DM1, CYREG_PRT5_DM1 -.set SCSI_Noise__2__DM2, CYREG_PRT5_DM2 -.set SCSI_Noise__2__DR, CYREG_PRT5_DR -.set SCSI_Noise__2__INP_DIS, CYREG_PRT5_INP_DIS -.set SCSI_Noise__2__INTTYPE, CYREG_PICU5_INTTYPE0 -.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG -.set SCSI_Noise__2__LCD_EN, CYREG_PRT5_LCD_EN -.set SCSI_Noise__2__MASK, 0x01 -.set SCSI_Noise__2__PC, CYREG_PRT5_PC0 -.set SCSI_Noise__2__PORT, 5 -.set SCSI_Noise__2__PRT, CYREG_PRT5_PRT -.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL -.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN -.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 -.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 -.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 -.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 -.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT -.set SCSI_Noise__2__PS, CYREG_PRT5_PS -.set SCSI_Noise__2__SHIFT, 0 -.set SCSI_Noise__2__SLW, CYREG_PRT5_SLW -.set SCSI_Noise__3__AG, CYREG_PRT6_AG -.set SCSI_Noise__3__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__3__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__3__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__3__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__3__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__3__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__3__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__3__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__3__DR, CYREG_PRT6_DR -.set SCSI_Noise__3__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__3__INTTYPE, CYREG_PICU6_INTTYPE6 -.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__3__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__3__MASK, 0x40 -.set SCSI_Noise__3__PC, CYREG_PRT6_PC6 -.set SCSI_Noise__3__PORT, 6 -.set SCSI_Noise__3__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__3__PS, CYREG_PRT6_PS -.set SCSI_Noise__3__SHIFT, 6 -.set SCSI_Noise__3__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__4__AG, CYREG_PRT6_AG -.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__4__DR, CYREG_PRT6_DR -.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__4__INTTYPE, CYREG_PICU6_INTTYPE5 -.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__4__MASK, 0x20 -.set SCSI_Noise__4__PC, CYREG_PRT6_PC5 -.set SCSI_Noise__4__PORT, 6 -.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__4__PS, CYREG_PRT6_PS -.set SCSI_Noise__4__SHIFT, 5 -.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG -.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR -.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__ACK__INTTYPE, CYREG_PICU6_INTTYPE5 -.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__ACK__MASK, 0x20 -.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC5 -.set SCSI_Noise__ACK__PORT, 6 -.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS -.set SCSI_Noise__ACK__SHIFT, 5 -.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__ATN__AG, CYREG_PRT12_AG -.set SCSI_Noise__ATN__BIE, CYREG_PRT12_BIE -.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK -.set SCSI_Noise__ATN__BYP, CYREG_PRT12_BYP -.set SCSI_Noise__ATN__DM0, CYREG_PRT12_DM0 -.set SCSI_Noise__ATN__DM1, CYREG_PRT12_DM1 -.set SCSI_Noise__ATN__DM2, CYREG_PRT12_DM2 -.set SCSI_Noise__ATN__DR, CYREG_PRT12_DR -.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT12_INP_DIS -.set SCSI_Noise__ATN__INTTYPE, CYREG_PICU12_INTTYPE5 -.set SCSI_Noise__ATN__MASK, 0x20 -.set SCSI_Noise__ATN__PC, CYREG_PRT12_PC5 -.set SCSI_Noise__ATN__PORT, 12 -.set SCSI_Noise__ATN__PRT, CYREG_PRT12_PRT -.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN -.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 -.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 -.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 -.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 -.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT -.set SCSI_Noise__ATN__PS, CYREG_PRT12_PS -.set SCSI_Noise__ATN__SHIFT, 5 -.set SCSI_Noise__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG -.set SCSI_Noise__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF -.set SCSI_Noise__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN -.set SCSI_Noise__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ -.set SCSI_Noise__ATN__SLW, CYREG_PRT12_SLW -.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG -.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR -.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__BSY__INTTYPE, CYREG_PICU6_INTTYPE4 -.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__BSY__MASK, 0x10 -.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC4 -.set SCSI_Noise__BSY__PORT, 6 -.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS -.set SCSI_Noise__BSY__SHIFT, 4 -.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__RST__AG, CYREG_PRT6_AG -.set SCSI_Noise__RST__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__RST__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__RST__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__RST__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__RST__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__RST__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__RST__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__RST__DR, CYREG_PRT6_DR -.set SCSI_Noise__RST__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__RST__INTTYPE, CYREG_PICU6_INTTYPE6 -.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__RST__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__RST__MASK, 0x40 -.set SCSI_Noise__RST__PC, CYREG_PRT6_PC6 -.set SCSI_Noise__RST__PORT, 6 -.set SCSI_Noise__RST__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__RST__PS, CYREG_PRT6_PS -.set SCSI_Noise__RST__SHIFT, 6 -.set SCSI_Noise__RST__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__SEL__AG, CYREG_PRT5_AG -.set SCSI_Noise__SEL__AMUX, CYREG_PRT5_AMUX -.set SCSI_Noise__SEL__BIE, CYREG_PRT5_BIE -.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK -.set SCSI_Noise__SEL__BYP, CYREG_PRT5_BYP -.set SCSI_Noise__SEL__CTL, CYREG_PRT5_CTL -.set SCSI_Noise__SEL__DM0, CYREG_PRT5_DM0 -.set SCSI_Noise__SEL__DM1, CYREG_PRT5_DM1 -.set SCSI_Noise__SEL__DM2, CYREG_PRT5_DM2 -.set SCSI_Noise__SEL__DR, CYREG_PRT5_DR -.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT5_INP_DIS -.set SCSI_Noise__SEL__INTTYPE, CYREG_PICU5_INTTYPE0 -.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG -.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT5_LCD_EN -.set SCSI_Noise__SEL__MASK, 0x01 -.set SCSI_Noise__SEL__PC, CYREG_PRT5_PC0 -.set SCSI_Noise__SEL__PORT, 5 -.set SCSI_Noise__SEL__PRT, CYREG_PRT5_PRT -.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL -.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN -.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 -.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 -.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 -.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 -.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT -.set SCSI_Noise__SEL__PS, CYREG_PRT5_PS -.set SCSI_Noise__SEL__SHIFT, 0 -.set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW +/* SD_DAT1 */ +.set SD_DAT1__0__INTTYPE, CYREG_PICU3_INTTYPE0 +.set SD_DAT1__0__MASK, 0x01 +.set SD_DAT1__0__PC, CYREG_PRT3_PC0 +.set SD_DAT1__0__PORT, 3 +.set SD_DAT1__0__SHIFT, 0 +.set SD_DAT1__AG, CYREG_PRT3_AG +.set SD_DAT1__AMUX, CYREG_PRT3_AMUX +.set SD_DAT1__BIE, CYREG_PRT3_BIE +.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_DAT1__BYP, CYREG_PRT3_BYP +.set SD_DAT1__CTL, CYREG_PRT3_CTL +.set SD_DAT1__DM0, CYREG_PRT3_DM0 +.set SD_DAT1__DM1, CYREG_PRT3_DM1 +.set SD_DAT1__DM2, CYREG_PRT3_DM2 +.set SD_DAT1__DR, CYREG_PRT3_DR +.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_DAT1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_DAT1__MASK, 0x01 +.set SD_DAT1__PORT, 3 +.set SD_DAT1__PRT, CYREG_PRT3_PRT +.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_DAT1__PS, CYREG_PRT3_PS +.set SD_DAT1__SHIFT, 0 +.set SD_DAT1__SLW, CYREG_PRT3_SLW + +/* SD_DAT2 */ +.set SD_DAT2__0__INTTYPE, CYREG_PICU3_INTTYPE5 +.set SD_DAT2__0__MASK, 0x20 +.set SD_DAT2__0__PC, CYREG_PRT3_PC5 +.set SD_DAT2__0__PORT, 3 +.set SD_DAT2__0__SHIFT, 5 +.set SD_DAT2__AG, CYREG_PRT3_AG +.set SD_DAT2__AMUX, CYREG_PRT3_AMUX +.set SD_DAT2__BIE, CYREG_PRT3_BIE +.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_DAT2__BYP, CYREG_PRT3_BYP +.set SD_DAT2__CTL, CYREG_PRT3_CTL +.set SD_DAT2__DM0, CYREG_PRT3_DM0 +.set SD_DAT2__DM1, CYREG_PRT3_DM1 +.set SD_DAT2__DM2, CYREG_PRT3_DM2 +.set SD_DAT2__DR, CYREG_PRT3_DR +.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_DAT2__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_DAT2__MASK, 0x20 +.set SD_DAT2__PORT, 3 +.set SD_DAT2__PRT, CYREG_PRT3_PRT +.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_DAT2__PS, CYREG_PRT3_PS +.set SD_DAT2__SHIFT, 5 +.set SD_DAT2__SLW, CYREG_PRT3_SLW + +/* SD_MISO */ +.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1 +.set SD_MISO__0__MASK, 0x02 +.set SD_MISO__0__PC, CYREG_PRT3_PC1 +.set SD_MISO__0__PORT, 3 +.set SD_MISO__0__SHIFT, 1 +.set SD_MISO__AG, CYREG_PRT3_AG +.set SD_MISO__AMUX, CYREG_PRT3_AMUX +.set SD_MISO__BIE, CYREG_PRT3_BIE +.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MISO__BYP, CYREG_PRT3_BYP +.set SD_MISO__CTL, CYREG_PRT3_CTL +.set SD_MISO__DM0, CYREG_PRT3_DM0 +.set SD_MISO__DM1, CYREG_PRT3_DM1 +.set SD_MISO__DM2, CYREG_PRT3_DM2 +.set SD_MISO__DR, CYREG_PRT3_DR +.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MISO__MASK, 0x02 +.set SD_MISO__PORT, 3 +.set SD_MISO__PRT, CYREG_PRT3_PRT +.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MISO__PS, CYREG_PRT3_PS +.set SD_MISO__SHIFT, 1 +.set SD_MISO__SLW, CYREG_PRT3_SLW + +/* SD_MOSI */ +.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3 +.set SD_MOSI__0__MASK, 0x08 +.set SD_MOSI__0__PC, CYREG_PRT3_PC3 +.set SD_MOSI__0__PORT, 3 +.set SD_MOSI__0__SHIFT, 3 +.set SD_MOSI__AG, CYREG_PRT3_AG +.set SD_MOSI__AMUX, CYREG_PRT3_AMUX +.set SD_MOSI__BIE, CYREG_PRT3_BIE +.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MOSI__BYP, CYREG_PRT3_BYP +.set SD_MOSI__CTL, CYREG_PRT3_CTL +.set SD_MOSI__DM0, CYREG_PRT3_DM0 +.set SD_MOSI__DM1, CYREG_PRT3_DM1 +.set SD_MOSI__DM2, CYREG_PRT3_DM2 +.set SD_MOSI__DR, CYREG_PRT3_DR +.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MOSI__MASK, 0x08 +.set SD_MOSI__PORT, 3 +.set SD_MOSI__PRT, CYREG_PRT3_PRT +.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MOSI__PS, CYREG_PRT3_PS +.set SD_MOSI__SHIFT, 3 +.set SD_MOSI__SLW, CYREG_PRT3_SLW + +/* SCSI_CLK */ +.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 +.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 +.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2 +.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07 +.set SCSI_CLK__INDEX, 0x01 +.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SCSI_CLK__PM_ACT_MSK, 0x02 +.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SCSI_CLK__PM_STBY_MSK, 0x02 /* SCSI_Out */ .set SCSI_Out__0__AG, CYREG_PRT4_AG @@ -2229,370 +2436,6 @@ .set SCSI_Out_DBx__DB7__SHIFT, 4 .set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW -/* SCSI_Parity_Error */ -.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST -.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST - -/* SCSI_RST_ISR */ -.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RST_ISR__INTC_MASK, 0x02 -.set SCSI_RST_ISR__INTC_NUMBER, 1 -.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 -.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_RX_DMA */ -.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_RX_DMA__DRQ_NUMBER, 0 -.set SCSI_RX_DMA__NUMBEROF_TDS, 0 -.set SCSI_RX_DMA__PRIORITY, 2 -.set SCSI_RX_DMA__TERMIN_EN, 0 -.set SCSI_RX_DMA__TERMIN_SEL, 0 -.set SCSI_RX_DMA__TERMOUT0_EN, 1 -.set SCSI_RX_DMA__TERMOUT0_SEL, 0 -.set SCSI_RX_DMA__TERMOUT1_EN, 0 -.set SCSI_RX_DMA__TERMOUT1_SEL, 0 -.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04 -.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2 -.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 -.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_SEL_ISR__INTC_MASK, 0x08 -.set SCSI_SEL_ISR__INTC_NUMBER, 3 -.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 -.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_TX_DMA__DRQ_NUMBER, 1 -.set SCSI_TX_DMA__NUMBEROF_TDS, 0 -.set SCSI_TX_DMA__PRIORITY, 2 -.set SCSI_TX_DMA__TERMIN_EN, 0 -.set SCSI_TX_DMA__TERMIN_SEL, 0 -.set SCSI_TX_DMA__TERMOUT0_EN, 1 -.set SCSI_TX_DMA__TERMOUT0_SEL, 1 -.set SCSI_TX_DMA__TERMOUT1_EN, 0 -.set SCSI_TX_DMA__TERMOUT1_SEL, 0 -.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 -.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 -.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST -.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 -.set SDCard_BSPIM_RxStsReg__4__POS, 4 -.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 -.set SDCard_BSPIM_RxStsReg__5__POS, 5 -.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 -.set SDCard_BSPIM_RxStsReg__6__POS, 6 -.set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK -.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB08_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB08_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 -.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 -.set SDCard_BSPIM_TxStsReg__0__POS, 0 -.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 -.set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST -.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 -.set SDCard_BSPIM_TxStsReg__2__POS, 2 -.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 -.set SDCard_BSPIM_TxStsReg__3__POS, 3 -.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 -.set SDCard_BSPIM_TxStsReg__4__POS, 4 -.set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST - -/* SD_CD */ -.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE6 -.set SD_CD__0__MASK, 0x40 -.set SD_CD__0__PC, CYREG_PRT3_PC6 -.set SD_CD__0__PORT, 3 -.set SD_CD__0__SHIFT, 6 -.set SD_CD__AG, CYREG_PRT3_AG -.set SD_CD__AMUX, CYREG_PRT3_AMUX -.set SD_CD__BIE, CYREG_PRT3_BIE -.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_CD__BYP, CYREG_PRT3_BYP -.set SD_CD__CTL, CYREG_PRT3_CTL -.set SD_CD__DM0, CYREG_PRT3_DM0 -.set SD_CD__DM1, CYREG_PRT3_DM1 -.set SD_CD__DM2, CYREG_PRT3_DM2 -.set SD_CD__DR, CYREG_PRT3_DR -.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_CD__MASK, 0x40 -.set SD_CD__PORT, 3 -.set SD_CD__PRT, CYREG_PRT3_PRT -.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_CD__PS, CYREG_PRT3_PS -.set SD_CD__SHIFT, 6 -.set SD_CD__SLW, CYREG_PRT3_SLW - -/* SD_CS */ -.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4 -.set SD_CS__0__MASK, 0x10 -.set SD_CS__0__PC, CYREG_PRT3_PC4 -.set SD_CS__0__PORT, 3 -.set SD_CS__0__SHIFT, 4 -.set SD_CS__AG, CYREG_PRT3_AG -.set SD_CS__AMUX, CYREG_PRT3_AMUX -.set SD_CS__BIE, CYREG_PRT3_BIE -.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_CS__BYP, CYREG_PRT3_BYP -.set SD_CS__CTL, CYREG_PRT3_CTL -.set SD_CS__DM0, CYREG_PRT3_DM0 -.set SD_CS__DM1, CYREG_PRT3_DM1 -.set SD_CS__DM2, CYREG_PRT3_DM2 -.set SD_CS__DR, CYREG_PRT3_DR -.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_CS__MASK, 0x10 -.set SD_CS__PORT, 3 -.set SD_CS__PRT, CYREG_PRT3_PRT -.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_CS__PS, CYREG_PRT3_PS -.set SD_CS__SHIFT, 4 -.set SD_CS__SLW, CYREG_PRT3_SLW - -/* SD_DAT1 */ -.set SD_DAT1__0__INTTYPE, CYREG_PICU3_INTTYPE0 -.set SD_DAT1__0__MASK, 0x01 -.set SD_DAT1__0__PC, CYREG_PRT3_PC0 -.set SD_DAT1__0__PORT, 3 -.set SD_DAT1__0__SHIFT, 0 -.set SD_DAT1__AG, CYREG_PRT3_AG -.set SD_DAT1__AMUX, CYREG_PRT3_AMUX -.set SD_DAT1__BIE, CYREG_PRT3_BIE -.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_DAT1__BYP, CYREG_PRT3_BYP -.set SD_DAT1__CTL, CYREG_PRT3_CTL -.set SD_DAT1__DM0, CYREG_PRT3_DM0 -.set SD_DAT1__DM1, CYREG_PRT3_DM1 -.set SD_DAT1__DM2, CYREG_PRT3_DM2 -.set SD_DAT1__DR, CYREG_PRT3_DR -.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_DAT1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_DAT1__MASK, 0x01 -.set SD_DAT1__PORT, 3 -.set SD_DAT1__PRT, CYREG_PRT3_PRT -.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_DAT1__PS, CYREG_PRT3_PS -.set SD_DAT1__SHIFT, 0 -.set SD_DAT1__SLW, CYREG_PRT3_SLW - -/* SD_DAT2 */ -.set SD_DAT2__0__INTTYPE, CYREG_PICU3_INTTYPE5 -.set SD_DAT2__0__MASK, 0x20 -.set SD_DAT2__0__PC, CYREG_PRT3_PC5 -.set SD_DAT2__0__PORT, 3 -.set SD_DAT2__0__SHIFT, 5 -.set SD_DAT2__AG, CYREG_PRT3_AG -.set SD_DAT2__AMUX, CYREG_PRT3_AMUX -.set SD_DAT2__BIE, CYREG_PRT3_BIE -.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_DAT2__BYP, CYREG_PRT3_BYP -.set SD_DAT2__CTL, CYREG_PRT3_CTL -.set SD_DAT2__DM0, CYREG_PRT3_DM0 -.set SD_DAT2__DM1, CYREG_PRT3_DM1 -.set SD_DAT2__DM2, CYREG_PRT3_DM2 -.set SD_DAT2__DR, CYREG_PRT3_DR -.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_DAT2__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_DAT2__MASK, 0x20 -.set SD_DAT2__PORT, 3 -.set SD_DAT2__PRT, CYREG_PRT3_PRT -.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_DAT2__PS, CYREG_PRT3_PS -.set SD_DAT2__SHIFT, 5 -.set SD_DAT2__SLW, CYREG_PRT3_SLW - -/* SD_Data_Clk */ -.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 -.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 -.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 -.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 -.set SD_Data_Clk__INDEX, 0x00 -.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set SD_Data_Clk__PM_ACT_MSK, 0x01 -.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set SD_Data_Clk__PM_STBY_MSK, 0x01 - -/* SD_MISO */ -.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1 -.set SD_MISO__0__MASK, 0x02 -.set SD_MISO__0__PC, CYREG_PRT3_PC1 -.set SD_MISO__0__PORT, 3 -.set SD_MISO__0__SHIFT, 1 -.set SD_MISO__AG, CYREG_PRT3_AG -.set SD_MISO__AMUX, CYREG_PRT3_AMUX -.set SD_MISO__BIE, CYREG_PRT3_BIE -.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_MISO__BYP, CYREG_PRT3_BYP -.set SD_MISO__CTL, CYREG_PRT3_CTL -.set SD_MISO__DM0, CYREG_PRT3_DM0 -.set SD_MISO__DM1, CYREG_PRT3_DM1 -.set SD_MISO__DM2, CYREG_PRT3_DM2 -.set SD_MISO__DR, CYREG_PRT3_DR -.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_MISO__MASK, 0x02 -.set SD_MISO__PORT, 3 -.set SD_MISO__PRT, CYREG_PRT3_PRT -.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_MISO__PS, CYREG_PRT3_PS -.set SD_MISO__SHIFT, 1 -.set SD_MISO__SLW, CYREG_PRT3_SLW - -/* SD_MOSI */ -.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3 -.set SD_MOSI__0__MASK, 0x08 -.set SD_MOSI__0__PC, CYREG_PRT3_PC3 -.set SD_MOSI__0__PORT, 3 -.set SD_MOSI__0__SHIFT, 3 -.set SD_MOSI__AG, CYREG_PRT3_AG -.set SD_MOSI__AMUX, CYREG_PRT3_AMUX -.set SD_MOSI__BIE, CYREG_PRT3_BIE -.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_MOSI__BYP, CYREG_PRT3_BYP -.set SD_MOSI__CTL, CYREG_PRT3_CTL -.set SD_MOSI__DM0, CYREG_PRT3_DM0 -.set SD_MOSI__DM1, CYREG_PRT3_DM1 -.set SD_MOSI__DM2, CYREG_PRT3_DM2 -.set SD_MOSI__DR, CYREG_PRT3_DR -.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_MOSI__MASK, 0x08 -.set SD_MOSI__PORT, 3 -.set SD_MOSI__PRT, CYREG_PRT3_PRT -.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_MOSI__PS, CYREG_PRT3_PS -.set SD_MOSI__SHIFT, 3 -.set SD_MOSI__SLW, CYREG_PRT3_SLW - /* SD_RX_DMA */ .set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_RX_DMA__DRQ_NUMBER, 2 @@ -2613,40 +2456,6 @@ .set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -/* SD_SCK */ -.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2 -.set SD_SCK__0__MASK, 0x04 -.set SD_SCK__0__PC, CYREG_PRT3_PC2 -.set SD_SCK__0__PORT, 3 -.set SD_SCK__0__SHIFT, 2 -.set SD_SCK__AG, CYREG_PRT3_AG -.set SD_SCK__AMUX, CYREG_PRT3_AMUX -.set SD_SCK__BIE, CYREG_PRT3_BIE -.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_SCK__BYP, CYREG_PRT3_BYP -.set SD_SCK__CTL, CYREG_PRT3_CTL -.set SD_SCK__DM0, CYREG_PRT3_DM0 -.set SD_SCK__DM1, CYREG_PRT3_DM1 -.set SD_SCK__DM2, CYREG_PRT3_DM2 -.set SD_SCK__DR, CYREG_PRT3_DR -.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_SCK__MASK, 0x04 -.set SD_SCK__PORT, 3 -.set SD_SCK__PRT, CYREG_PRT3_PRT -.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_SCK__PS, CYREG_PRT3_PS -.set SD_SCK__SHIFT, 2 -.set SD_SCK__SLW, CYREG_PRT3_SLW - /* SD_TX_DMA */ .set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_TX_DMA__DRQ_NUMBER, 3 @@ -2667,269 +2476,285 @@ .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -/* USBFS */ -.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_arb_int__INTC_MASK, 0x400000 -.set USBFS_arb_int__INTC_NUMBER, 22 -.set USBFS_arb_int__INTC_PRIOR_NUM, 6 -.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 -.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_bus_reset__INTC_MASK, 0x800000 -.set USBFS_bus_reset__INTC_NUMBER, 23 -.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 -.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 -.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7 -.set USBFS_Dm__0__MASK, 0x80 -.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 -.set USBFS_Dm__0__PORT, 15 -.set USBFS_Dm__0__SHIFT, 7 -.set USBFS_Dm__AG, CYREG_PRT15_AG -.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX -.set USBFS_Dm__BIE, CYREG_PRT15_BIE -.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK -.set USBFS_Dm__BYP, CYREG_PRT15_BYP -.set USBFS_Dm__CTL, CYREG_PRT15_CTL -.set USBFS_Dm__DM0, CYREG_PRT15_DM0 -.set USBFS_Dm__DM1, CYREG_PRT15_DM1 -.set USBFS_Dm__DM2, CYREG_PRT15_DM2 -.set USBFS_Dm__DR, CYREG_PRT15_DR -.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS -.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE -.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG -.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN -.set USBFS_Dm__MASK, 0x80 -.set USBFS_Dm__PORT, 15 -.set USBFS_Dm__PRT, CYREG_PRT15_PRT -.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL -.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN -.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 -.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 -.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 -.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 -.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT -.set USBFS_Dm__PS, CYREG_PRT15_PS -.set USBFS_Dm__SHIFT, 7 -.set USBFS_Dm__SLW, CYREG_PRT15_SLW -.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6 -.set USBFS_Dp__0__MASK, 0x40 -.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 -.set USBFS_Dp__0__PORT, 15 -.set USBFS_Dp__0__SHIFT, 6 -.set USBFS_Dp__AG, CYREG_PRT15_AG -.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX -.set USBFS_Dp__BIE, CYREG_PRT15_BIE -.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK -.set USBFS_Dp__BYP, CYREG_PRT15_BYP -.set USBFS_Dp__CTL, CYREG_PRT15_CTL -.set USBFS_Dp__DM0, CYREG_PRT15_DM0 -.set USBFS_Dp__DM1, CYREG_PRT15_DM1 -.set USBFS_Dp__DM2, CYREG_PRT15_DM2 -.set USBFS_Dp__DR, CYREG_PRT15_DR -.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS -.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT -.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE -.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG -.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN -.set USBFS_Dp__MASK, 0x40 -.set USBFS_Dp__PORT, 15 -.set USBFS_Dp__PRT, CYREG_PRT15_PRT -.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL -.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN -.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 -.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 -.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 -.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 -.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT -.set USBFS_Dp__PS, CYREG_PRT15_PS -.set USBFS_Dp__SHIFT, 6 -.set USBFS_Dp__SLW, CYREG_PRT15_SLW -.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 -.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_dp_int__INTC_MASK, 0x1000 -.set USBFS_dp_int__INTC_NUMBER, 12 -.set USBFS_dp_int__INTC_PRIOR_NUM, 7 -.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 -.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_0__INTC_MASK, 0x1000000 -.set USBFS_ep_0__INTC_NUMBER, 24 -.set USBFS_ep_0__INTC_PRIOR_NUM, 7 -.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 -.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x80 -.set USBFS_ep_1__INTC_NUMBER, 7 -.set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 -.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x100 -.set USBFS_ep_2__INTC_NUMBER, 8 -.set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 -.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_3__INTC_MASK, 0x200 -.set USBFS_ep_3__INTC_NUMBER, 9 -.set USBFS_ep_3__INTC_PRIOR_NUM, 7 -.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 -.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_4__INTC_MASK, 0x400 -.set USBFS_ep_4__INTC_NUMBER, 10 -.set USBFS_ep_4__INTC_PRIOR_NUM, 7 -.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 -.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_sof_int__INTC_MASK, 0x200000 -.set USBFS_sof_int__INTC_NUMBER, 21 -.set USBFS_sof_int__INTC_PRIOR_NUM, 7 -.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 -.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG -.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG -.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN -.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR -.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG -.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN -.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR -.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG -.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN -.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR -.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG -.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN -.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR -.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG -.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN -.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR -.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG -.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN -.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR -.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG -.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN -.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR -.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG -.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN -.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR -.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN -.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR -.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR -.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA -.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB -.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA -.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB -.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR -.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA -.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB -.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA -.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB -.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR -.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA -.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB -.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA -.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB -.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR -.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA -.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB -.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA -.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB -.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR -.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA -.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB -.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA -.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB -.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR -.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA -.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB -.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA -.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB -.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR -.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA -.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB -.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA -.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB -.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR -.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA -.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB -.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA -.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB -.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE -.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT -.set USBFS_USB__CR0, CYREG_USB_CR0 -.set USBFS_USB__CR1, CYREG_USB_CR1 -.set USBFS_USB__CWA, CYREG_USB_CWA -.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB -.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES -.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB -.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG -.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE -.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE -.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT -.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR -.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 -.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 -.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 -.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 -.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 -.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 -.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 -.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 -.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE -.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 -.set USBFS_USB__PM_ACT_MSK, 0x01 -.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 -.set USBFS_USB__PM_STBY_MSK, 0x01 -.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN -.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR -.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 -.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 -.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 -.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 -.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 -.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 -.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 -.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 -.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 -.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 -.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 -.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 -.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 -.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 -.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 -.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 -.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 -.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 -.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 -.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 -.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 -.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 -.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 -.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 -.set USBFS_USB__SOF0, CYREG_USB_SOF0 -.set USBFS_USB__SOF1, CYREG_USB_SOF1 -.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN -.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 -.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 +/* SCSI_Noise */ +.set SCSI_Noise__0__AG, CYREG_PRT12_AG +.set SCSI_Noise__0__BIE, CYREG_PRT12_BIE +.set SCSI_Noise__0__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_Noise__0__BYP, CYREG_PRT12_BYP +.set SCSI_Noise__0__DM0, CYREG_PRT12_DM0 +.set SCSI_Noise__0__DM1, CYREG_PRT12_DM1 +.set SCSI_Noise__0__DM2, CYREG_PRT12_DM2 +.set SCSI_Noise__0__DR, CYREG_PRT12_DR +.set SCSI_Noise__0__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_Noise__0__INTTYPE, CYREG_PICU12_INTTYPE5 +.set SCSI_Noise__0__MASK, 0x20 +.set SCSI_Noise__0__PC, CYREG_PRT12_PC5 +.set SCSI_Noise__0__PORT, 12 +.set SCSI_Noise__0__PRT, CYREG_PRT12_PRT +.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_Noise__0__PS, CYREG_PRT12_PS +.set SCSI_Noise__0__SHIFT, 5 +.set SCSI_Noise__0__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_Noise__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_Noise__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_Noise__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_Noise__0__SLW, CYREG_PRT12_SLW +.set SCSI_Noise__1__AG, CYREG_PRT6_AG +.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__1__DR, CYREG_PRT6_DR +.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__1__INTTYPE, CYREG_PICU6_INTTYPE4 +.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__1__MASK, 0x10 +.set SCSI_Noise__1__PC, CYREG_PRT6_PC4 +.set SCSI_Noise__1__PORT, 6 +.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__1__PS, CYREG_PRT6_PS +.set SCSI_Noise__1__SHIFT, 4 +.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__2__AG, CYREG_PRT5_AG +.set SCSI_Noise__2__AMUX, CYREG_PRT5_AMUX +.set SCSI_Noise__2__BIE, CYREG_PRT5_BIE +.set SCSI_Noise__2__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Noise__2__BYP, CYREG_PRT5_BYP +.set SCSI_Noise__2__CTL, CYREG_PRT5_CTL +.set SCSI_Noise__2__DM0, CYREG_PRT5_DM0 +.set SCSI_Noise__2__DM1, CYREG_PRT5_DM1 +.set SCSI_Noise__2__DM2, CYREG_PRT5_DM2 +.set SCSI_Noise__2__DR, CYREG_PRT5_DR +.set SCSI_Noise__2__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Noise__2__INTTYPE, CYREG_PICU5_INTTYPE0 +.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Noise__2__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Noise__2__MASK, 0x01 +.set SCSI_Noise__2__PC, CYREG_PRT5_PC0 +.set SCSI_Noise__2__PORT, 5 +.set SCSI_Noise__2__PRT, CYREG_PRT5_PRT +.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Noise__2__PS, CYREG_PRT5_PS +.set SCSI_Noise__2__SHIFT, 0 +.set SCSI_Noise__2__SLW, CYREG_PRT5_SLW +.set SCSI_Noise__3__AG, CYREG_PRT6_AG +.set SCSI_Noise__3__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__3__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__3__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__3__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__3__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__3__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__3__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__3__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__3__DR, CYREG_PRT6_DR +.set SCSI_Noise__3__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__3__INTTYPE, CYREG_PICU6_INTTYPE6 +.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__3__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__3__MASK, 0x40 +.set SCSI_Noise__3__PC, CYREG_PRT6_PC6 +.set SCSI_Noise__3__PORT, 6 +.set SCSI_Noise__3__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__3__PS, CYREG_PRT6_PS +.set SCSI_Noise__3__SHIFT, 6 +.set SCSI_Noise__3__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__4__AG, CYREG_PRT6_AG +.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__4__DR, CYREG_PRT6_DR +.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__4__INTTYPE, CYREG_PICU6_INTTYPE5 +.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__4__MASK, 0x20 +.set SCSI_Noise__4__PC, CYREG_PRT6_PC5 +.set SCSI_Noise__4__PORT, 6 +.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__4__PS, CYREG_PRT6_PS +.set SCSI_Noise__4__SHIFT, 5 +.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG +.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR +.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__ACK__INTTYPE, CYREG_PICU6_INTTYPE5 +.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__ACK__MASK, 0x20 +.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC5 +.set SCSI_Noise__ACK__PORT, 6 +.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS +.set SCSI_Noise__ACK__SHIFT, 5 +.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__ATN__AG, CYREG_PRT12_AG +.set SCSI_Noise__ATN__BIE, CYREG_PRT12_BIE +.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_Noise__ATN__BYP, CYREG_PRT12_BYP +.set SCSI_Noise__ATN__DM0, CYREG_PRT12_DM0 +.set SCSI_Noise__ATN__DM1, CYREG_PRT12_DM1 +.set SCSI_Noise__ATN__DM2, CYREG_PRT12_DM2 +.set SCSI_Noise__ATN__DR, CYREG_PRT12_DR +.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_Noise__ATN__INTTYPE, CYREG_PICU12_INTTYPE5 +.set SCSI_Noise__ATN__MASK, 0x20 +.set SCSI_Noise__ATN__PC, CYREG_PRT12_PC5 +.set SCSI_Noise__ATN__PORT, 12 +.set SCSI_Noise__ATN__PRT, CYREG_PRT12_PRT +.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_Noise__ATN__PS, CYREG_PRT12_PS +.set SCSI_Noise__ATN__SHIFT, 5 +.set SCSI_Noise__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_Noise__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_Noise__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_Noise__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_Noise__ATN__SLW, CYREG_PRT12_SLW +.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG +.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR +.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__BSY__INTTYPE, CYREG_PICU6_INTTYPE4 +.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__BSY__MASK, 0x10 +.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC4 +.set SCSI_Noise__BSY__PORT, 6 +.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS +.set SCSI_Noise__BSY__SHIFT, 4 +.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__RST__AG, CYREG_PRT6_AG +.set SCSI_Noise__RST__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__RST__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__RST__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__RST__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__RST__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__RST__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__RST__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__RST__DR, CYREG_PRT6_DR +.set SCSI_Noise__RST__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__RST__INTTYPE, CYREG_PICU6_INTTYPE6 +.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__RST__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__RST__MASK, 0x40 +.set SCSI_Noise__RST__PC, CYREG_PRT6_PC6 +.set SCSI_Noise__RST__PORT, 6 +.set SCSI_Noise__RST__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__RST__PS, CYREG_PRT6_PS +.set SCSI_Noise__RST__SHIFT, 6 +.set SCSI_Noise__RST__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__SEL__AG, CYREG_PRT5_AG +.set SCSI_Noise__SEL__AMUX, CYREG_PRT5_AMUX +.set SCSI_Noise__SEL__BIE, CYREG_PRT5_BIE +.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Noise__SEL__BYP, CYREG_PRT5_BYP +.set SCSI_Noise__SEL__CTL, CYREG_PRT5_CTL +.set SCSI_Noise__SEL__DM0, CYREG_PRT5_DM0 +.set SCSI_Noise__SEL__DM1, CYREG_PRT5_DM1 +.set SCSI_Noise__SEL__DM2, CYREG_PRT5_DM2 +.set SCSI_Noise__SEL__DR, CYREG_PRT5_DR +.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Noise__SEL__INTTYPE, CYREG_PICU5_INTTYPE0 +.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Noise__SEL__MASK, 0x01 +.set SCSI_Noise__SEL__PC, CYREG_PRT5_PC0 +.set SCSI_Noise__SEL__PORT, 5 +.set SCSI_Noise__SEL__PRT, CYREG_PRT5_PRT +.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Noise__SEL__PS, CYREG_PRT5_PS +.set SCSI_Noise__SEL__SHIFT, 0 +.set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW /* scsiTarget */ .set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0 @@ -2998,6 +2823,83 @@ .set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL .set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB07_ST +/* Debug_Timer */ +.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set Debug_Timer_Interrupt__INTC_MASK, 0x01 +.set Debug_Timer_Interrupt__INTC_NUMBER, 0 +.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7 +.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0 +.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1 +.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0 +.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1 +.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2 +.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0 +.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1 +.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0 +.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1 +.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3 +.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01 +.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3 +.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01 +.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0 +.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1 +.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0 + +/* SCSI_RX_DMA */ +.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_RX_DMA__DRQ_NUMBER, 0 +.set SCSI_RX_DMA__NUMBEROF_TDS, 0 +.set SCSI_RX_DMA__PRIORITY, 2 +.set SCSI_RX_DMA__TERMIN_EN, 0 +.set SCSI_RX_DMA__TERMIN_SEL, 0 +.set SCSI_RX_DMA__TERMOUT0_EN, 1 +.set SCSI_RX_DMA__TERMOUT0_SEL, 0 +.set SCSI_RX_DMA__TERMOUT1_EN, 0 +.set SCSI_RX_DMA__TERMOUT1_SEL, 0 +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04 +.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_TX_DMA__DRQ_NUMBER, 1 +.set SCSI_TX_DMA__NUMBEROF_TDS, 0 +.set SCSI_TX_DMA__PRIORITY, 2 +.set SCSI_TX_DMA__TERMIN_EN, 0 +.set SCSI_TX_DMA__TERMIN_SEL, 0 +.set SCSI_TX_DMA__TERMOUT0_EN, 1 +.set SCSI_TX_DMA__TERMOUT0_SEL, 1 +.set SCSI_TX_DMA__TERMOUT1_EN, 0 +.set SCSI_TX_DMA__TERMOUT1_SEL, 0 +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 +.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SD_Data_Clk */ +.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 +.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 +.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 +.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 +.set SD_Data_Clk__INDEX, 0x00 +.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SD_Data_Clk__PM_ACT_MSK, 0x01 +.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SD_Data_Clk__PM_STBY_MSK, 0x01 + /* timer_clock */ .set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0 .set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1 @@ -3009,12 +2911,108 @@ .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2 .set timer_clock__PM_STBY_MSK, 0x04 +/* SCSI_RST_ISR */ +.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RST_ISR__INTC_MASK, 0x02 +.set SCSI_RST_ISR__INTC_NUMBER, 1 +.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_SEL_ISR__INTC_MASK, 0x08 +.set SCSI_SEL_ISR__INTC_NUMBER, 3 +.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_Filtered */ +.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Filtered_sts_sts_reg__0__POS, 0 +.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 +.set SCSI_Filtered_sts_sts_reg__1__POS, 1 +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST +.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 +.set SCSI_Filtered_sts_sts_reg__2__POS, 2 +.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 +.set SCSI_Filtered_sts_sts_reg__3__POS, 3 +.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 +.set SCSI_Filtered_sts_sts_reg__4__POS, 4 +.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST + +/* SCSI_CTL_PHASE */ +.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK + +/* SCSI_Glitch_Ctl */ +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK + +/* SCSI_Parity_Error */ +.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST + /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 .set BCLK__BUS_CLK__KHZ, 50000 .set BCLK__BUS_CLK__MHZ, 50 .set CYDEV_CHIP_DIE_LEOPARD, 1 -.set CYDEV_CHIP_DIE_PSOC4A, 16 +.set CYDEV_CHIP_DIE_PSOC4A, 18 .set CYDEV_CHIP_DIE_PSOC5LP, 2 .set CYDEV_CHIP_DIE_PSOC5TM, 3 .set CYDEV_CHIP_DIE_TMA4, 4 @@ -3030,32 +3028,34 @@ .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 .set CYDEV_CHIP_JTAG_ID, 0x2E133069 .set CYDEV_CHIP_MEMBER_3A, 1 -.set CYDEV_CHIP_MEMBER_4A, 16 -.set CYDEV_CHIP_MEMBER_4D, 12 +.set CYDEV_CHIP_MEMBER_4A, 18 +.set CYDEV_CHIP_MEMBER_4D, 13 .set CYDEV_CHIP_MEMBER_4E, 6 -.set CYDEV_CHIP_MEMBER_4F, 17 +.set CYDEV_CHIP_MEMBER_4F, 19 .set CYDEV_CHIP_MEMBER_4G, 4 -.set CYDEV_CHIP_MEMBER_4H, 15 -.set CYDEV_CHIP_MEMBER_4I, 21 -.set CYDEV_CHIP_MEMBER_4J, 13 -.set CYDEV_CHIP_MEMBER_4K, 14 -.set CYDEV_CHIP_MEMBER_4L, 20 -.set CYDEV_CHIP_MEMBER_4M, 19 -.set CYDEV_CHIP_MEMBER_4N, 9 +.set CYDEV_CHIP_MEMBER_4H, 17 +.set CYDEV_CHIP_MEMBER_4I, 23 +.set CYDEV_CHIP_MEMBER_4J, 14 +.set CYDEV_CHIP_MEMBER_4K, 15 +.set CYDEV_CHIP_MEMBER_4L, 22 +.set CYDEV_CHIP_MEMBER_4M, 21 +.set CYDEV_CHIP_MEMBER_4N, 10 .set CYDEV_CHIP_MEMBER_4O, 7 -.set CYDEV_CHIP_MEMBER_4P, 18 -.set CYDEV_CHIP_MEMBER_4Q, 11 +.set CYDEV_CHIP_MEMBER_4P, 20 +.set CYDEV_CHIP_MEMBER_4Q, 12 .set CYDEV_CHIP_MEMBER_4R, 8 -.set CYDEV_CHIP_MEMBER_4S, 10 +.set CYDEV_CHIP_MEMBER_4S, 11 +.set CYDEV_CHIP_MEMBER_4T, 9 .set CYDEV_CHIP_MEMBER_4U, 5 +.set CYDEV_CHIP_MEMBER_4V, 16 .set CYDEV_CHIP_MEMBER_5A, 3 .set CYDEV_CHIP_MEMBER_5B, 2 -.set CYDEV_CHIP_MEMBER_6A, 22 -.set CYDEV_CHIP_MEMBER_FM3, 26 -.set CYDEV_CHIP_MEMBER_FM4, 27 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 23 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 24 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 25 +.set CYDEV_CHIP_MEMBER_6A, 24 +.set CYDEV_CHIP_MEMBER_FM3, 28 +.set CYDEV_CHIP_MEMBER_FM4, 29 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 25 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 26 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 27 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED @@ -3081,6 +3081,7 @@ .set CYDEV_CHIP_REVISION_4A_ES0, 17 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 .set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD, 0 .set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0 @@ -3100,14 +3101,17 @@ .set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4T_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4V_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_5A_ES0, 0 .set CYDEV_CHIP_REVISION_5A_ES1, 1 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 .set CYDEV_CHIP_REVISION_5B_ES0, 0 .set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 -.set CYDEV_CHIP_REVISION_6A_NO_UDB, 0 -.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_6A_ES, 17 +.set CYDEV_CHIP_REVISION_6A_NO_UDB, 33 +.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 33 .set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index f222dd3..e118f55 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -1,13 +1,13 @@ ; ; File Name: cyfitteriar.inc ; -; PSoC Creator 4.1 +; PSoC Creator 4.2 ; ; Description: ; ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. @@ -18,34 +18,6 @@ INCLUDE cydeviceiar.inc INCLUDE cydeviceiar_trm.inc -/* Debug_Timer_Interrupt */ -Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -Debug_Timer_Interrupt__INTC_MASK EQU 0x01 -Debug_Timer_Interrupt__INTC_NUMBER EQU 0 -Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 -Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 -Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 -Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 -Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 -Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 -Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 -Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 -Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 -Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 -Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 -Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 -Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 -Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 -Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 -Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 -Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 - /* LED1 */ LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE3 LED1__0__MASK EQU 0x08 @@ -79,82 +51,450 @@ LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ LED1__SLW EQU CYREG_PRT12_SLW -/* SCSI_CLK */ -SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 -SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 -SCSI_CLK__INDEX EQU 0x01 -SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SCSI_CLK__PM_ACT_MSK EQU 0x02 -SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SCSI_CLK__PM_STBY_MSK EQU 0x02 +/* SD_CD */ +SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6 +SD_CD__0__MASK EQU 0x40 +SD_CD__0__PC EQU CYREG_PRT3_PC6 +SD_CD__0__PORT EQU 3 +SD_CD__0__SHIFT EQU 6 +SD_CD__AG EQU CYREG_PRT3_AG +SD_CD__AMUX EQU CYREG_PRT3_AMUX +SD_CD__BIE EQU CYREG_PRT3_BIE +SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CD__BYP EQU CYREG_PRT3_BYP +SD_CD__CTL EQU CYREG_PRT3_CTL +SD_CD__DM0 EQU CYREG_PRT3_DM0 +SD_CD__DM1 EQU CYREG_PRT3_DM1 +SD_CD__DM2 EQU CYREG_PRT3_DM2 +SD_CD__DR EQU CYREG_PRT3_DR +SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CD__MASK EQU 0x40 +SD_CD__PORT EQU 3 +SD_CD__PRT EQU CYREG_PRT3_PRT +SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CD__PS EQU CYREG_PRT3_PS +SD_CD__SHIFT EQU 6 +SD_CD__SLW EQU CYREG_PRT3_SLW -/* SCSI_CTL_PHASE */ -SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 -SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK +/* SD_CS */ +SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SD_CS__0__MASK EQU 0x10 +SD_CS__0__PC EQU CYREG_PRT3_PC4 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 4 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x10 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 4 +SD_CS__SLW EQU CYREG_PRT3_SLW -/* SCSI_Filtered */ -SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Filtered_sts_sts_reg__0__POS EQU 0 -SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 -SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST -SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 -SCSI_Filtered_sts_sts_reg__2__POS EQU 2 -SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 -SCSI_Filtered_sts_sts_reg__3__POS EQU 3 -SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 -SCSI_Filtered_sts_sts_reg__4__POS EQU 4 -SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST +/* USBFS */ +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 6 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_PRIOR_NUM EQU 7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_PRIOR_NUM EQU 7 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 -/* SCSI_Glitch_Ctl */ -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK +/* SDCard */ +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST + +/* SD_SCK */ +SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_SCK__0__MASK EQU 0x04 +SD_SCK__0__PC EQU CYREG_PRT3_PC2 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 2 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x04 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 2 +SD_SCK__SLW EQU CYREG_PRT3_SLW /* SCSI_In */ SCSI_In__0__AG EQU CYREG_PRT2_AG @@ -884,285 +1224,152 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_In_DBx__DB7__SHIFT EQU 1 SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW -/* SCSI_Noise */ -SCSI_Noise__0__AG EQU CYREG_PRT12_AG -SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE -SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK -SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP -SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0 -SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1 -SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2 -SCSI_Noise__0__DR EQU CYREG_PRT12_DR -SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS -SCSI_Noise__0__INTTYPE EQU CYREG_PICU12_INTTYPE5 -SCSI_Noise__0__MASK EQU 0x20 -SCSI_Noise__0__PC EQU CYREG_PRT12_PC5 -SCSI_Noise__0__PORT EQU 12 -SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT -SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN -SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 -SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 -SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 -SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 -SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT -SCSI_Noise__0__PS EQU CYREG_PRT12_PS -SCSI_Noise__0__SHIFT EQU 5 -SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG -SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF -SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN -SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ -SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW -SCSI_Noise__1__AG EQU CYREG_PRT6_AG -SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__1__DR EQU CYREG_PRT6_DR -SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE4 -SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__1__MASK EQU 0x10 -SCSI_Noise__1__PC EQU CYREG_PRT6_PC4 -SCSI_Noise__1__PORT EQU 6 -SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__1__PS EQU CYREG_PRT6_PS -SCSI_Noise__1__SHIFT EQU 4 -SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__2__AG EQU CYREG_PRT5_AG -SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX -SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE -SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP -SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL -SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0 -SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1 -SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2 -SCSI_Noise__2__DR EQU CYREG_PRT5_DR -SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_Noise__2__INTTYPE EQU CYREG_PICU5_INTTYPE0 -SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_Noise__2__MASK EQU 0x01 -SCSI_Noise__2__PC EQU CYREG_PRT5_PC0 -SCSI_Noise__2__PORT EQU 5 -SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT -SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_Noise__2__PS EQU CYREG_PRT5_PS -SCSI_Noise__2__SHIFT EQU 0 -SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW -SCSI_Noise__3__AG EQU CYREG_PRT6_AG -SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__3__DR EQU CYREG_PRT6_DR -SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__3__INTTYPE EQU CYREG_PICU6_INTTYPE6 -SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__3__MASK EQU 0x40 -SCSI_Noise__3__PC EQU CYREG_PRT6_PC6 -SCSI_Noise__3__PORT EQU 6 -SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__3__PS EQU CYREG_PRT6_PS -SCSI_Noise__3__SHIFT EQU 6 -SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__4__AG EQU CYREG_PRT6_AG -SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__4__DR EQU CYREG_PRT6_DR -SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE5 -SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__4__MASK EQU 0x20 -SCSI_Noise__4__PC EQU CYREG_PRT6_PC5 -SCSI_Noise__4__PORT EQU 6 -SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__4__PS EQU CYREG_PRT6_PS -SCSI_Noise__4__SHIFT EQU 5 -SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG -SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR -SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE5 -SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__ACK__MASK EQU 0x20 -SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5 -SCSI_Noise__ACK__PORT EQU 6 -SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS -SCSI_Noise__ACK__SHIFT EQU 5 -SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG -SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE -SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK -SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP -SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0 -SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1 -SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2 -SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR -SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS -SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU12_INTTYPE5 -SCSI_Noise__ATN__MASK EQU 0x20 -SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5 -SCSI_Noise__ATN__PORT EQU 12 -SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT -SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN -SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 -SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 -SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 -SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 -SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT -SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS -SCSI_Noise__ATN__SHIFT EQU 5 -SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG -SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF -SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN -SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ -SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW -SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG -SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR -SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE4 -SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__BSY__MASK EQU 0x10 -SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4 -SCSI_Noise__BSY__PORT EQU 6 -SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS -SCSI_Noise__BSY__SHIFT EQU 4 -SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__RST__AG EQU CYREG_PRT6_AG -SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__RST__DR EQU CYREG_PRT6_DR -SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__RST__INTTYPE EQU CYREG_PICU6_INTTYPE6 -SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__RST__MASK EQU 0x40 -SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6 -SCSI_Noise__RST__PORT EQU 6 -SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__RST__PS EQU CYREG_PRT6_PS -SCSI_Noise__RST__SHIFT EQU 6 -SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG -SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX -SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE -SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP -SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL -SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0 -SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1 -SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2 -SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR -SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU5_INTTYPE0 -SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_Noise__SEL__MASK EQU 0x01 -SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0 -SCSI_Noise__SEL__PORT EQU 5 -SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT -SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS -SCSI_Noise__SEL__SHIFT EQU 0 -SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW +/* SD_DAT1 */ +SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0 +SD_DAT1__0__MASK EQU 0x01 +SD_DAT1__0__PC EQU CYREG_PRT3_PC0 +SD_DAT1__0__PORT EQU 3 +SD_DAT1__0__SHIFT EQU 0 +SD_DAT1__AG EQU CYREG_PRT3_AG +SD_DAT1__AMUX EQU CYREG_PRT3_AMUX +SD_DAT1__BIE EQU CYREG_PRT3_BIE +SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_DAT1__BYP EQU CYREG_PRT3_BYP +SD_DAT1__CTL EQU CYREG_PRT3_CTL +SD_DAT1__DM0 EQU CYREG_PRT3_DM0 +SD_DAT1__DM1 EQU CYREG_PRT3_DM1 +SD_DAT1__DM2 EQU CYREG_PRT3_DM2 +SD_DAT1__DR EQU CYREG_PRT3_DR +SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_DAT1__MASK EQU 0x01 +SD_DAT1__PORT EQU 3 +SD_DAT1__PRT EQU CYREG_PRT3_PRT +SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_DAT1__PS EQU CYREG_PRT3_PS +SD_DAT1__SHIFT EQU 0 +SD_DAT1__SLW EQU CYREG_PRT3_SLW + +/* SD_DAT2 */ +SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SD_DAT2__0__MASK EQU 0x20 +SD_DAT2__0__PC EQU CYREG_PRT3_PC5 +SD_DAT2__0__PORT EQU 3 +SD_DAT2__0__SHIFT EQU 5 +SD_DAT2__AG EQU CYREG_PRT3_AG +SD_DAT2__AMUX EQU CYREG_PRT3_AMUX +SD_DAT2__BIE EQU CYREG_PRT3_BIE +SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_DAT2__BYP EQU CYREG_PRT3_BYP +SD_DAT2__CTL EQU CYREG_PRT3_CTL +SD_DAT2__DM0 EQU CYREG_PRT3_DM0 +SD_DAT2__DM1 EQU CYREG_PRT3_DM1 +SD_DAT2__DM2 EQU CYREG_PRT3_DM2 +SD_DAT2__DR EQU CYREG_PRT3_DR +SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_DAT2__MASK EQU 0x20 +SD_DAT2__PORT EQU 3 +SD_DAT2__PRT EQU CYREG_PRT3_PRT +SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_DAT2__PS EQU CYREG_PRT3_PS +SD_DAT2__SHIFT EQU 5 +SD_DAT2__SLW EQU CYREG_PRT3_SLW + +/* SD_MISO */ +SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 +SD_MISO__0__MASK EQU 0x02 +SD_MISO__0__PC EQU CYREG_PRT3_PC1 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 1 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x02 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 1 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +/* SD_MOSI */ +SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_MOSI__0__MASK EQU 0x08 +SD_MOSI__0__PC EQU CYREG_PRT3_PC3 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 3 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x08 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 3 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + +/* SCSI_CLK */ +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 /* SCSI_Out */ SCSI_Out__0__AG EQU CYREG_PRT4_AG @@ -2228,370 +2435,6 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS SCSI_Out_DBx__DB7__SHIFT EQU 4 SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW -/* SCSI_Parity_Error */ -SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST -SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST - -/* SCSI_RST_ISR */ -SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x02 -SCSI_RST_ISR__INTC_NUMBER EQU 1 -SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 -SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_RX_DMA */ -SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 -SCSI_RX_DMA__NUMBEROF_TDS EQU 0 -SCSI_RX_DMA__PRIORITY EQU 2 -SCSI_RX_DMA__TERMIN_EN EQU 0 -SCSI_RX_DMA__TERMIN_SEL EQU 0 -SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 -SCSI_RX_DMA__TERMOUT1_EN EQU 0 -SCSI_RX_DMA__TERMOUT1_SEL EQU 0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 -SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 -SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 -SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 -SCSI_TX_DMA__NUMBEROF_TDS EQU 0 -SCSI_TX_DMA__PRIORITY EQU 2 -SCSI_TX_DMA__TERMIN_EN EQU 0 -SCSI_TX_DMA__TERMIN_SEL EQU 0 -SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 -SCSI_TX_DMA__TERMOUT1_EN EQU 0 -SCSI_TX_DMA__TERMOUT1_SEL EQU 0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 -SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST -SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_RxStsReg__4__POS EQU 4 -SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 -SDCard_BSPIM_RxStsReg__5__POS EQU 5 -SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 -SDCard_BSPIM_RxStsReg__6__POS EQU 6 -SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 -SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 -SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 -SDCard_BSPIM_TxStsReg__2__POS EQU 2 -SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 -SDCard_BSPIM_TxStsReg__3__POS EQU 3 -SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_TxStsReg__4__POS EQU 4 -SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST - -/* SD_CD */ -SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6 -SD_CD__0__MASK EQU 0x40 -SD_CD__0__PC EQU CYREG_PRT3_PC6 -SD_CD__0__PORT EQU 3 -SD_CD__0__SHIFT EQU 6 -SD_CD__AG EQU CYREG_PRT3_AG -SD_CD__AMUX EQU CYREG_PRT3_AMUX -SD_CD__BIE EQU CYREG_PRT3_BIE -SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CD__BYP EQU CYREG_PRT3_BYP -SD_CD__CTL EQU CYREG_PRT3_CTL -SD_CD__DM0 EQU CYREG_PRT3_DM0 -SD_CD__DM1 EQU CYREG_PRT3_DM1 -SD_CD__DM2 EQU CYREG_PRT3_DM2 -SD_CD__DR EQU CYREG_PRT3_DR -SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CD__MASK EQU 0x40 -SD_CD__PORT EQU 3 -SD_CD__PRT EQU CYREG_PRT3_PRT -SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CD__PS EQU CYREG_PRT3_PS -SD_CD__SHIFT EQU 6 -SD_CD__SLW EQU CYREG_PRT3_SLW - -/* SD_CS */ -SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 -SD_CS__0__MASK EQU 0x10 -SD_CS__0__PC EQU CYREG_PRT3_PC4 -SD_CS__0__PORT EQU 3 -SD_CS__0__SHIFT EQU 4 -SD_CS__AG EQU CYREG_PRT3_AG -SD_CS__AMUX EQU CYREG_PRT3_AMUX -SD_CS__BIE EQU CYREG_PRT3_BIE -SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CS__BYP EQU CYREG_PRT3_BYP -SD_CS__CTL EQU CYREG_PRT3_CTL -SD_CS__DM0 EQU CYREG_PRT3_DM0 -SD_CS__DM1 EQU CYREG_PRT3_DM1 -SD_CS__DM2 EQU CYREG_PRT3_DM2 -SD_CS__DR EQU CYREG_PRT3_DR -SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CS__MASK EQU 0x10 -SD_CS__PORT EQU 3 -SD_CS__PRT EQU CYREG_PRT3_PRT -SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CS__PS EQU CYREG_PRT3_PS -SD_CS__SHIFT EQU 4 -SD_CS__SLW EQU CYREG_PRT3_SLW - -/* SD_DAT1 */ -SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0 -SD_DAT1__0__MASK EQU 0x01 -SD_DAT1__0__PC EQU CYREG_PRT3_PC0 -SD_DAT1__0__PORT EQU 3 -SD_DAT1__0__SHIFT EQU 0 -SD_DAT1__AG EQU CYREG_PRT3_AG -SD_DAT1__AMUX EQU CYREG_PRT3_AMUX -SD_DAT1__BIE EQU CYREG_PRT3_BIE -SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_DAT1__BYP EQU CYREG_PRT3_BYP -SD_DAT1__CTL EQU CYREG_PRT3_CTL -SD_DAT1__DM0 EQU CYREG_PRT3_DM0 -SD_DAT1__DM1 EQU CYREG_PRT3_DM1 -SD_DAT1__DM2 EQU CYREG_PRT3_DM2 -SD_DAT1__DR EQU CYREG_PRT3_DR -SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_DAT1__MASK EQU 0x01 -SD_DAT1__PORT EQU 3 -SD_DAT1__PRT EQU CYREG_PRT3_PRT -SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_DAT1__PS EQU CYREG_PRT3_PS -SD_DAT1__SHIFT EQU 0 -SD_DAT1__SLW EQU CYREG_PRT3_SLW - -/* SD_DAT2 */ -SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 -SD_DAT2__0__MASK EQU 0x20 -SD_DAT2__0__PC EQU CYREG_PRT3_PC5 -SD_DAT2__0__PORT EQU 3 -SD_DAT2__0__SHIFT EQU 5 -SD_DAT2__AG EQU CYREG_PRT3_AG -SD_DAT2__AMUX EQU CYREG_PRT3_AMUX -SD_DAT2__BIE EQU CYREG_PRT3_BIE -SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_DAT2__BYP EQU CYREG_PRT3_BYP -SD_DAT2__CTL EQU CYREG_PRT3_CTL -SD_DAT2__DM0 EQU CYREG_PRT3_DM0 -SD_DAT2__DM1 EQU CYREG_PRT3_DM1 -SD_DAT2__DM2 EQU CYREG_PRT3_DM2 -SD_DAT2__DR EQU CYREG_PRT3_DR -SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_DAT2__MASK EQU 0x20 -SD_DAT2__PORT EQU 3 -SD_DAT2__PRT EQU CYREG_PRT3_PRT -SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_DAT2__PS EQU CYREG_PRT3_PS -SD_DAT2__SHIFT EQU 5 -SD_DAT2__SLW EQU CYREG_PRT3_SLW - -/* SD_Data_Clk */ -SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 -SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 -SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 -SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Data_Clk__INDEX EQU 0x00 -SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Data_Clk__PM_ACT_MSK EQU 0x01 -SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Data_Clk__PM_STBY_MSK EQU 0x01 - -/* SD_MISO */ -SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 -SD_MISO__0__MASK EQU 0x02 -SD_MISO__0__PC EQU CYREG_PRT3_PC1 -SD_MISO__0__PORT EQU 3 -SD_MISO__0__SHIFT EQU 1 -SD_MISO__AG EQU CYREG_PRT3_AG -SD_MISO__AMUX EQU CYREG_PRT3_AMUX -SD_MISO__BIE EQU CYREG_PRT3_BIE -SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MISO__BYP EQU CYREG_PRT3_BYP -SD_MISO__CTL EQU CYREG_PRT3_CTL -SD_MISO__DM0 EQU CYREG_PRT3_DM0 -SD_MISO__DM1 EQU CYREG_PRT3_DM1 -SD_MISO__DM2 EQU CYREG_PRT3_DM2 -SD_MISO__DR EQU CYREG_PRT3_DR -SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MISO__MASK EQU 0x02 -SD_MISO__PORT EQU 3 -SD_MISO__PRT EQU CYREG_PRT3_PRT -SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MISO__PS EQU CYREG_PRT3_PS -SD_MISO__SHIFT EQU 1 -SD_MISO__SLW EQU CYREG_PRT3_SLW - -/* SD_MOSI */ -SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 -SD_MOSI__0__MASK EQU 0x08 -SD_MOSI__0__PC EQU CYREG_PRT3_PC3 -SD_MOSI__0__PORT EQU 3 -SD_MOSI__0__SHIFT EQU 3 -SD_MOSI__AG EQU CYREG_PRT3_AG -SD_MOSI__AMUX EQU CYREG_PRT3_AMUX -SD_MOSI__BIE EQU CYREG_PRT3_BIE -SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MOSI__BYP EQU CYREG_PRT3_BYP -SD_MOSI__CTL EQU CYREG_PRT3_CTL -SD_MOSI__DM0 EQU CYREG_PRT3_DM0 -SD_MOSI__DM1 EQU CYREG_PRT3_DM1 -SD_MOSI__DM2 EQU CYREG_PRT3_DM2 -SD_MOSI__DR EQU CYREG_PRT3_DR -SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MOSI__MASK EQU 0x08 -SD_MOSI__PORT EQU 3 -SD_MOSI__PRT EQU CYREG_PRT3_PRT -SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MOSI__PS EQU CYREG_PRT3_PS -SD_MOSI__SHIFT EQU 3 -SD_MOSI__SLW EQU CYREG_PRT3_SLW - /* SD_RX_DMA */ SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 @@ -2612,40 +2455,6 @@ SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -/* SD_SCK */ -SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 -SD_SCK__0__MASK EQU 0x04 -SD_SCK__0__PC EQU CYREG_PRT3_PC2 -SD_SCK__0__PORT EQU 3 -SD_SCK__0__SHIFT EQU 2 -SD_SCK__AG EQU CYREG_PRT3_AG -SD_SCK__AMUX EQU CYREG_PRT3_AMUX -SD_SCK__BIE EQU CYREG_PRT3_BIE -SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_SCK__BYP EQU CYREG_PRT3_BYP -SD_SCK__CTL EQU CYREG_PRT3_CTL -SD_SCK__DM0 EQU CYREG_PRT3_DM0 -SD_SCK__DM1 EQU CYREG_PRT3_DM1 -SD_SCK__DM2 EQU CYREG_PRT3_DM2 -SD_SCK__DR EQU CYREG_PRT3_DR -SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_SCK__MASK EQU 0x04 -SD_SCK__PORT EQU 3 -SD_SCK__PRT EQU CYREG_PRT3_PRT -SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_SCK__PS EQU CYREG_PRT3_PS -SD_SCK__SHIFT EQU 2 -SD_SCK__SLW EQU CYREG_PRT3_SLW - /* SD_TX_DMA */ SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_TX_DMA__DRQ_NUMBER EQU 3 @@ -2666,269 +2475,285 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -/* USBFS */ -USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_arb_int__INTC_MASK EQU 0x400000 -USBFS_arb_int__INTC_NUMBER EQU 22 -USBFS_arb_int__INTC_PRIOR_NUM EQU 6 -USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 -USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_bus_reset__INTC_MASK EQU 0x800000 -USBFS_bus_reset__INTC_NUMBER EQU 23 -USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 -USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 -USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 -USBFS_Dm__0__MASK EQU 0x80 -USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 -USBFS_Dm__0__PORT EQU 15 -USBFS_Dm__0__SHIFT EQU 7 -USBFS_Dm__AG EQU CYREG_PRT15_AG -USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dm__BIE EQU CYREG_PRT15_BIE -USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dm__BYP EQU CYREG_PRT15_BYP -USBFS_Dm__CTL EQU CYREG_PRT15_CTL -USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dm__DR EQU CYREG_PRT15_DR -USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dm__MASK EQU 0x80 -USBFS_Dm__PORT EQU 15 -USBFS_Dm__PRT EQU CYREG_PRT15_PRT -USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dm__PS EQU CYREG_PRT15_PS -USBFS_Dm__SHIFT EQU 7 -USBFS_Dm__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 -USBFS_Dp__0__MASK EQU 0x40 -USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 -USBFS_Dp__0__PORT EQU 15 -USBFS_Dp__0__SHIFT EQU 6 -USBFS_Dp__AG EQU CYREG_PRT15_AG -USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dp__BIE EQU CYREG_PRT15_BIE -USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dp__BYP EQU CYREG_PRT15_BYP -USBFS_Dp__CTL EQU CYREG_PRT15_CTL -USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dp__DR EQU CYREG_PRT15_DR -USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT -USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dp__MASK EQU 0x40 -USBFS_Dp__PORT EQU 15 -USBFS_Dp__PRT EQU CYREG_PRT15_PRT -USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dp__PS EQU CYREG_PRT15_PS -USBFS_Dp__SHIFT EQU 6 -USBFS_Dp__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 -USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_dp_int__INTC_MASK EQU 0x1000 -USBFS_dp_int__INTC_NUMBER EQU 12 -USBFS_dp_int__INTC_PRIOR_NUM EQU 7 -USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 -USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_0__INTC_MASK EQU 0x1000000 -USBFS_ep_0__INTC_NUMBER EQU 24 -USBFS_ep_0__INTC_PRIOR_NUM EQU 7 -USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 -USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 -USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 -USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 -USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 -USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 -USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 -USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 -USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 -USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_sof_int__INTC_MASK EQU 0x200000 -USBFS_sof_int__INTC_NUMBER EQU 21 -USBFS_sof_int__INTC_PRIOR_NUM EQU 7 -USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 -USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG -USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG -USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN -USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR -USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG -USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN -USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR -USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG -USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN -USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR -USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG -USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN -USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR -USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG -USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN -USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR -USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG -USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN -USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR -USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG -USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN -USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR -USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG -USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN -USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR -USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN -USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR -USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR -USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA -USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB -USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA -USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB -USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR -USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA -USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB -USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA -USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB -USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR -USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA -USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB -USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA -USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB -USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR -USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA -USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB -USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA -USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB -USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR -USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA -USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB -USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA -USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB -USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR -USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA -USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB -USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA -USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB -USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR -USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA -USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB -USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA -USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB -USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR -USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA -USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB -USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA -USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB -USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE -USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT -USBFS_USB__CR0 EQU CYREG_USB_CR0 -USBFS_USB__CR1 EQU CYREG_USB_CR1 -USBFS_USB__CWA EQU CYREG_USB_CWA -USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB -USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES -USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB -USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG -USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE -USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE -USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT -USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR -USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 -USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 -USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 -USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 -USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 -USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 -USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 -USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 -USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE -USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 -USBFS_USB__PM_ACT_MSK EQU 0x01 -USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 -USBFS_USB__PM_STBY_MSK EQU 0x01 -USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN -USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR -USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 -USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 -USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 -USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 -USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 -USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 -USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 -USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 -USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 -USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 -USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 -USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 -USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 -USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 -USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 -USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 -USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 -USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 -USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 -USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 -USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 -USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 -USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 -USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 -USBFS_USB__SOF0 EQU CYREG_USB_SOF0 -USBFS_USB__SOF1 EQU CYREG_USB_SOF1 -USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 -USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 +/* SCSI_Noise */ +SCSI_Noise__0__AG EQU CYREG_PRT12_AG +SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP +SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT12_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Noise__0__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Noise__0__MASK EQU 0x20 +SCSI_Noise__0__PC EQU CYREG_PRT12_PC5 +SCSI_Noise__0__PORT EQU 12 +SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT12_PS +SCSI_Noise__0__SHIFT EQU 5 +SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW +SCSI_Noise__1__AG EQU CYREG_PRT6_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT6_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE4 +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__1__MASK EQU 0x10 +SCSI_Noise__1__PC EQU CYREG_PRT6_PC4 +SCSI_Noise__1__PORT EQU 6 +SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT6_PS +SCSI_Noise__1__SHIFT EQU 4 +SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__2__AG EQU CYREG_PRT5_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT5_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Noise__2__INTTYPE EQU CYREG_PICU5_INTTYPE0 +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Noise__2__MASK EQU 0x01 +SCSI_Noise__2__PC EQU CYREG_PRT5_PC0 +SCSI_Noise__2__PORT EQU 5 +SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT5_PS +SCSI_Noise__2__SHIFT EQU 0 +SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW +SCSI_Noise__3__AG EQU CYREG_PRT6_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT6_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__3__INTTYPE EQU CYREG_PICU6_INTTYPE6 +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__3__MASK EQU 0x40 +SCSI_Noise__3__PC EQU CYREG_PRT6_PC6 +SCSI_Noise__3__PORT EQU 6 +SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT6_PS +SCSI_Noise__3__SHIFT EQU 6 +SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__4__AG EQU CYREG_PRT6_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT6_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__4__MASK EQU 0x20 +SCSI_Noise__4__PC EQU CYREG_PRT6_PC5 +SCSI_Noise__4__PORT EQU 6 +SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT6_PS +SCSI_Noise__4__SHIFT EQU 5 +SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x20 +SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5 +SCSI_Noise__ACK__PORT EQU 6 +SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS +SCSI_Noise__ACK__SHIFT EQU 5 +SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG +SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP +SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Noise__ATN__MASK EQU 0x20 +SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5 +SCSI_Noise__ATN__PORT EQU 12 +SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS +SCSI_Noise__ATN__SHIFT EQU 5 +SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE4 +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x10 +SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4 +SCSI_Noise__BSY__PORT EQU 6 +SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS +SCSI_Noise__BSY__SHIFT EQU 4 +SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT6_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT6_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__RST__INTTYPE EQU CYREG_PICU6_INTTYPE6 +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__RST__MASK EQU 0x40 +SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6 +SCSI_Noise__RST__PORT EQU 6 +SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT6_PS +SCSI_Noise__RST__SHIFT EQU 6 +SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU5_INTTYPE0 +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x01 +SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0 +SCSI_Noise__SEL__PORT EQU 5 +SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS +SCSI_Noise__SEL__SHIFT EQU 0 +SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW /* scsiTarget */ scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 @@ -2997,6 +2822,83 @@ scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST +/* Debug_Timer */ +Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x01 +Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 +Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 +Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 +Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 +Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 +Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 +Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 + +/* SCSI_RX_DMA */ +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SD_Data_Clk */ +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 + /* timer_clock */ timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 @@ -3008,12 +2910,108 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 +/* SCSI_RST_ISR */ +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x02 +SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_Filtered */ +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST + +/* SCSI_CTL_PHASE */ +SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK + +/* SCSI_Glitch_Ctl */ +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK + +/* SCSI_Parity_Error */ +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST + /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 16 +CYDEV_CHIP_DIE_PSOC4A EQU 18 CYDEV_CHIP_DIE_PSOC5LP EQU 2 CYDEV_CHIP_DIE_PSOC5TM EQU 3 CYDEV_CHIP_DIE_TMA4 EQU 4 @@ -3029,32 +3027,34 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 16 -CYDEV_CHIP_MEMBER_4D EQU 12 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 CYDEV_CHIP_MEMBER_4E EQU 6 -CYDEV_CHIP_MEMBER_4F EQU 17 +CYDEV_CHIP_MEMBER_4F EQU 19 CYDEV_CHIP_MEMBER_4G EQU 4 -CYDEV_CHIP_MEMBER_4H EQU 15 -CYDEV_CHIP_MEMBER_4I EQU 21 -CYDEV_CHIP_MEMBER_4J EQU 13 -CYDEV_CHIP_MEMBER_4K EQU 14 -CYDEV_CHIP_MEMBER_4L EQU 20 -CYDEV_CHIP_MEMBER_4M EQU 19 -CYDEV_CHIP_MEMBER_4N EQU 9 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 CYDEV_CHIP_MEMBER_4O EQU 7 -CYDEV_CHIP_MEMBER_4P EQU 18 -CYDEV_CHIP_MEMBER_4Q EQU 11 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 CYDEV_CHIP_MEMBER_4R EQU 8 -CYDEV_CHIP_MEMBER_4S EQU 10 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 CYDEV_CHIP_MEMBER_5A EQU 3 CYDEV_CHIP_MEMBER_5B EQU 2 -CYDEV_CHIP_MEMBER_6A EQU 22 -CYDEV_CHIP_MEMBER_FM3 EQU 26 -CYDEV_CHIP_MEMBER_FM4 EQU 27 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -3080,6 +3080,7 @@ CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 @@ -3099,14 +3100,17 @@ CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 -CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0 -CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 90a305e..5c489df 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -1,13 +1,13 @@ ; ; File Name: cyfitterrv.inc ; -; PSoC Creator 4.1 +; PSoC Creator 4.2 ; ; Description: ; ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. @@ -18,34 +18,6 @@ INCLUDED_CYFITTERRV_INC EQU 1 GET cydevicerv.inc GET cydevicerv_trm.inc -; Debug_Timer_Interrupt -Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -Debug_Timer_Interrupt__INTC_MASK EQU 0x01 -Debug_Timer_Interrupt__INTC_NUMBER EQU 0 -Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 -Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; Debug_Timer_TimerHW -Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 -Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 -Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 -Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 -Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 -Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 -Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 -Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 -Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 -Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 -Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 -Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 -Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 -Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 -Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 -Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 - ; LED1 LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE3 LED1__0__MASK EQU 0x08 @@ -79,82 +51,450 @@ LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ LED1__SLW EQU CYREG_PRT12_SLW -; SCSI_CLK -SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 -SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 -SCSI_CLK__INDEX EQU 0x01 -SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SCSI_CLK__PM_ACT_MSK EQU 0x02 -SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SCSI_CLK__PM_STBY_MSK EQU 0x02 +; SD_CD +SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6 +SD_CD__0__MASK EQU 0x40 +SD_CD__0__PC EQU CYREG_PRT3_PC6 +SD_CD__0__PORT EQU 3 +SD_CD__0__SHIFT EQU 6 +SD_CD__AG EQU CYREG_PRT3_AG +SD_CD__AMUX EQU CYREG_PRT3_AMUX +SD_CD__BIE EQU CYREG_PRT3_BIE +SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CD__BYP EQU CYREG_PRT3_BYP +SD_CD__CTL EQU CYREG_PRT3_CTL +SD_CD__DM0 EQU CYREG_PRT3_DM0 +SD_CD__DM1 EQU CYREG_PRT3_DM1 +SD_CD__DM2 EQU CYREG_PRT3_DM2 +SD_CD__DR EQU CYREG_PRT3_DR +SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CD__MASK EQU 0x40 +SD_CD__PORT EQU 3 +SD_CD__PRT EQU CYREG_PRT3_PRT +SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CD__PS EQU CYREG_PRT3_PS +SD_CD__SHIFT EQU 6 +SD_CD__SLW EQU CYREG_PRT3_SLW -; SCSI_CTL_PHASE -SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 -SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK +; SD_CS +SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SD_CS__0__MASK EQU 0x10 +SD_CS__0__PC EQU CYREG_PRT3_PC4 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 4 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x10 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 4 +SD_CS__SLW EQU CYREG_PRT3_SLW -; SCSI_Filtered -SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Filtered_sts_sts_reg__0__POS EQU 0 -SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 -SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST -SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 -SCSI_Filtered_sts_sts_reg__2__POS EQU 2 -SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 -SCSI_Filtered_sts_sts_reg__3__POS EQU 3 -SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 -SCSI_Filtered_sts_sts_reg__4__POS EQU 4 -SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST +; USBFS +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 6 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_PRIOR_NUM EQU 7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_PRIOR_NUM EQU 7 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 -; SCSI_Glitch_Ctl -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK +; SDCard +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST + +; SD_SCK +SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_SCK__0__MASK EQU 0x04 +SD_SCK__0__PC EQU CYREG_PRT3_PC2 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 2 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x04 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 2 +SD_SCK__SLW EQU CYREG_PRT3_SLW ; SCSI_In SCSI_In__0__AG EQU CYREG_PRT2_AG @@ -884,285 +1224,152 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_In_DBx__DB7__SHIFT EQU 1 SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW -; SCSI_Noise -SCSI_Noise__0__AG EQU CYREG_PRT12_AG -SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE -SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK -SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP -SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0 -SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1 -SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2 -SCSI_Noise__0__DR EQU CYREG_PRT12_DR -SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS -SCSI_Noise__0__INTTYPE EQU CYREG_PICU12_INTTYPE5 -SCSI_Noise__0__MASK EQU 0x20 -SCSI_Noise__0__PC EQU CYREG_PRT12_PC5 -SCSI_Noise__0__PORT EQU 12 -SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT -SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN -SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 -SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 -SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 -SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 -SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT -SCSI_Noise__0__PS EQU CYREG_PRT12_PS -SCSI_Noise__0__SHIFT EQU 5 -SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG -SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF -SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN -SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ -SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW -SCSI_Noise__1__AG EQU CYREG_PRT6_AG -SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__1__DR EQU CYREG_PRT6_DR -SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE4 -SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__1__MASK EQU 0x10 -SCSI_Noise__1__PC EQU CYREG_PRT6_PC4 -SCSI_Noise__1__PORT EQU 6 -SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__1__PS EQU CYREG_PRT6_PS -SCSI_Noise__1__SHIFT EQU 4 -SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__2__AG EQU CYREG_PRT5_AG -SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX -SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE -SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP -SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL -SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0 -SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1 -SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2 -SCSI_Noise__2__DR EQU CYREG_PRT5_DR -SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_Noise__2__INTTYPE EQU CYREG_PICU5_INTTYPE0 -SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_Noise__2__MASK EQU 0x01 -SCSI_Noise__2__PC EQU CYREG_PRT5_PC0 -SCSI_Noise__2__PORT EQU 5 -SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT -SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_Noise__2__PS EQU CYREG_PRT5_PS -SCSI_Noise__2__SHIFT EQU 0 -SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW -SCSI_Noise__3__AG EQU CYREG_PRT6_AG -SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__3__DR EQU CYREG_PRT6_DR -SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__3__INTTYPE EQU CYREG_PICU6_INTTYPE6 -SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__3__MASK EQU 0x40 -SCSI_Noise__3__PC EQU CYREG_PRT6_PC6 -SCSI_Noise__3__PORT EQU 6 -SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__3__PS EQU CYREG_PRT6_PS -SCSI_Noise__3__SHIFT EQU 6 -SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__4__AG EQU CYREG_PRT6_AG -SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__4__DR EQU CYREG_PRT6_DR -SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE5 -SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__4__MASK EQU 0x20 -SCSI_Noise__4__PC EQU CYREG_PRT6_PC5 -SCSI_Noise__4__PORT EQU 6 -SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__4__PS EQU CYREG_PRT6_PS -SCSI_Noise__4__SHIFT EQU 5 -SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG -SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR -SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE5 -SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__ACK__MASK EQU 0x20 -SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5 -SCSI_Noise__ACK__PORT EQU 6 -SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS -SCSI_Noise__ACK__SHIFT EQU 5 -SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG -SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE -SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK -SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP -SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0 -SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1 -SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2 -SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR -SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS -SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU12_INTTYPE5 -SCSI_Noise__ATN__MASK EQU 0x20 -SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5 -SCSI_Noise__ATN__PORT EQU 12 -SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT -SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN -SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 -SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 -SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 -SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 -SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT -SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS -SCSI_Noise__ATN__SHIFT EQU 5 -SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG -SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF -SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN -SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ -SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW -SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG -SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR -SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE4 -SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__BSY__MASK EQU 0x10 -SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4 -SCSI_Noise__BSY__PORT EQU 6 -SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS -SCSI_Noise__BSY__SHIFT EQU 4 -SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__RST__AG EQU CYREG_PRT6_AG -SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__RST__DR EQU CYREG_PRT6_DR -SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__RST__INTTYPE EQU CYREG_PICU6_INTTYPE6 -SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__RST__MASK EQU 0x40 -SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6 -SCSI_Noise__RST__PORT EQU 6 -SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__RST__PS EQU CYREG_PRT6_PS -SCSI_Noise__RST__SHIFT EQU 6 -SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG -SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX -SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE -SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP -SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL -SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0 -SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1 -SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2 -SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR -SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU5_INTTYPE0 -SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_Noise__SEL__MASK EQU 0x01 -SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0 -SCSI_Noise__SEL__PORT EQU 5 -SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT -SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS -SCSI_Noise__SEL__SHIFT EQU 0 -SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW +; SD_DAT1 +SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0 +SD_DAT1__0__MASK EQU 0x01 +SD_DAT1__0__PC EQU CYREG_PRT3_PC0 +SD_DAT1__0__PORT EQU 3 +SD_DAT1__0__SHIFT EQU 0 +SD_DAT1__AG EQU CYREG_PRT3_AG +SD_DAT1__AMUX EQU CYREG_PRT3_AMUX +SD_DAT1__BIE EQU CYREG_PRT3_BIE +SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_DAT1__BYP EQU CYREG_PRT3_BYP +SD_DAT1__CTL EQU CYREG_PRT3_CTL +SD_DAT1__DM0 EQU CYREG_PRT3_DM0 +SD_DAT1__DM1 EQU CYREG_PRT3_DM1 +SD_DAT1__DM2 EQU CYREG_PRT3_DM2 +SD_DAT1__DR EQU CYREG_PRT3_DR +SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_DAT1__MASK EQU 0x01 +SD_DAT1__PORT EQU 3 +SD_DAT1__PRT EQU CYREG_PRT3_PRT +SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_DAT1__PS EQU CYREG_PRT3_PS +SD_DAT1__SHIFT EQU 0 +SD_DAT1__SLW EQU CYREG_PRT3_SLW + +; SD_DAT2 +SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SD_DAT2__0__MASK EQU 0x20 +SD_DAT2__0__PC EQU CYREG_PRT3_PC5 +SD_DAT2__0__PORT EQU 3 +SD_DAT2__0__SHIFT EQU 5 +SD_DAT2__AG EQU CYREG_PRT3_AG +SD_DAT2__AMUX EQU CYREG_PRT3_AMUX +SD_DAT2__BIE EQU CYREG_PRT3_BIE +SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_DAT2__BYP EQU CYREG_PRT3_BYP +SD_DAT2__CTL EQU CYREG_PRT3_CTL +SD_DAT2__DM0 EQU CYREG_PRT3_DM0 +SD_DAT2__DM1 EQU CYREG_PRT3_DM1 +SD_DAT2__DM2 EQU CYREG_PRT3_DM2 +SD_DAT2__DR EQU CYREG_PRT3_DR +SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_DAT2__MASK EQU 0x20 +SD_DAT2__PORT EQU 3 +SD_DAT2__PRT EQU CYREG_PRT3_PRT +SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_DAT2__PS EQU CYREG_PRT3_PS +SD_DAT2__SHIFT EQU 5 +SD_DAT2__SLW EQU CYREG_PRT3_SLW + +; SD_MISO +SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 +SD_MISO__0__MASK EQU 0x02 +SD_MISO__0__PC EQU CYREG_PRT3_PC1 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 1 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x02 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 1 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +; SD_MOSI +SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_MOSI__0__MASK EQU 0x08 +SD_MOSI__0__PC EQU CYREG_PRT3_PC3 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 3 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x08 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 3 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + +; SCSI_CLK +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 ; SCSI_Out SCSI_Out__0__AG EQU CYREG_PRT4_AG @@ -2228,370 +2435,6 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS SCSI_Out_DBx__DB7__SHIFT EQU 4 SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW -; SCSI_Parity_Error -SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST -SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST - -; SCSI_RST_ISR -SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x02 -SCSI_RST_ISR__INTC_NUMBER EQU 1 -SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 -SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_RX_DMA -SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 -SCSI_RX_DMA__NUMBEROF_TDS EQU 0 -SCSI_RX_DMA__PRIORITY EQU 2 -SCSI_RX_DMA__TERMIN_EN EQU 0 -SCSI_RX_DMA__TERMIN_SEL EQU 0 -SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 -SCSI_RX_DMA__TERMOUT1_EN EQU 0 -SCSI_RX_DMA__TERMOUT1_SEL EQU 0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 -SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_SEL_ISR -SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 -SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 -SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_TX_DMA -SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 -SCSI_TX_DMA__NUMBEROF_TDS EQU 0 -SCSI_TX_DMA__PRIORITY EQU 2 -SCSI_TX_DMA__TERMIN_EN EQU 0 -SCSI_TX_DMA__TERMIN_SEL EQU 0 -SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 -SCSI_TX_DMA__TERMOUT1_EN EQU 0 -SCSI_TX_DMA__TERMOUT1_SEL EQU 0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 -SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SDCard_BSPIM -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST -SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_RxStsReg__4__POS EQU 4 -SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 -SDCard_BSPIM_RxStsReg__5__POS EQU 5 -SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 -SDCard_BSPIM_RxStsReg__6__POS EQU 6 -SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 -SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 -SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 -SDCard_BSPIM_TxStsReg__2__POS EQU 2 -SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 -SDCard_BSPIM_TxStsReg__3__POS EQU 3 -SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_TxStsReg__4__POS EQU 4 -SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST - -; SD_CD -SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6 -SD_CD__0__MASK EQU 0x40 -SD_CD__0__PC EQU CYREG_PRT3_PC6 -SD_CD__0__PORT EQU 3 -SD_CD__0__SHIFT EQU 6 -SD_CD__AG EQU CYREG_PRT3_AG -SD_CD__AMUX EQU CYREG_PRT3_AMUX -SD_CD__BIE EQU CYREG_PRT3_BIE -SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CD__BYP EQU CYREG_PRT3_BYP -SD_CD__CTL EQU CYREG_PRT3_CTL -SD_CD__DM0 EQU CYREG_PRT3_DM0 -SD_CD__DM1 EQU CYREG_PRT3_DM1 -SD_CD__DM2 EQU CYREG_PRT3_DM2 -SD_CD__DR EQU CYREG_PRT3_DR -SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CD__MASK EQU 0x40 -SD_CD__PORT EQU 3 -SD_CD__PRT EQU CYREG_PRT3_PRT -SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CD__PS EQU CYREG_PRT3_PS -SD_CD__SHIFT EQU 6 -SD_CD__SLW EQU CYREG_PRT3_SLW - -; SD_CS -SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 -SD_CS__0__MASK EQU 0x10 -SD_CS__0__PC EQU CYREG_PRT3_PC4 -SD_CS__0__PORT EQU 3 -SD_CS__0__SHIFT EQU 4 -SD_CS__AG EQU CYREG_PRT3_AG -SD_CS__AMUX EQU CYREG_PRT3_AMUX -SD_CS__BIE EQU CYREG_PRT3_BIE -SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CS__BYP EQU CYREG_PRT3_BYP -SD_CS__CTL EQU CYREG_PRT3_CTL -SD_CS__DM0 EQU CYREG_PRT3_DM0 -SD_CS__DM1 EQU CYREG_PRT3_DM1 -SD_CS__DM2 EQU CYREG_PRT3_DM2 -SD_CS__DR EQU CYREG_PRT3_DR -SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CS__MASK EQU 0x10 -SD_CS__PORT EQU 3 -SD_CS__PRT EQU CYREG_PRT3_PRT -SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CS__PS EQU CYREG_PRT3_PS -SD_CS__SHIFT EQU 4 -SD_CS__SLW EQU CYREG_PRT3_SLW - -; SD_DAT1 -SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0 -SD_DAT1__0__MASK EQU 0x01 -SD_DAT1__0__PC EQU CYREG_PRT3_PC0 -SD_DAT1__0__PORT EQU 3 -SD_DAT1__0__SHIFT EQU 0 -SD_DAT1__AG EQU CYREG_PRT3_AG -SD_DAT1__AMUX EQU CYREG_PRT3_AMUX -SD_DAT1__BIE EQU CYREG_PRT3_BIE -SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_DAT1__BYP EQU CYREG_PRT3_BYP -SD_DAT1__CTL EQU CYREG_PRT3_CTL -SD_DAT1__DM0 EQU CYREG_PRT3_DM0 -SD_DAT1__DM1 EQU CYREG_PRT3_DM1 -SD_DAT1__DM2 EQU CYREG_PRT3_DM2 -SD_DAT1__DR EQU CYREG_PRT3_DR -SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_DAT1__MASK EQU 0x01 -SD_DAT1__PORT EQU 3 -SD_DAT1__PRT EQU CYREG_PRT3_PRT -SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_DAT1__PS EQU CYREG_PRT3_PS -SD_DAT1__SHIFT EQU 0 -SD_DAT1__SLW EQU CYREG_PRT3_SLW - -; SD_DAT2 -SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 -SD_DAT2__0__MASK EQU 0x20 -SD_DAT2__0__PC EQU CYREG_PRT3_PC5 -SD_DAT2__0__PORT EQU 3 -SD_DAT2__0__SHIFT EQU 5 -SD_DAT2__AG EQU CYREG_PRT3_AG -SD_DAT2__AMUX EQU CYREG_PRT3_AMUX -SD_DAT2__BIE EQU CYREG_PRT3_BIE -SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_DAT2__BYP EQU CYREG_PRT3_BYP -SD_DAT2__CTL EQU CYREG_PRT3_CTL -SD_DAT2__DM0 EQU CYREG_PRT3_DM0 -SD_DAT2__DM1 EQU CYREG_PRT3_DM1 -SD_DAT2__DM2 EQU CYREG_PRT3_DM2 -SD_DAT2__DR EQU CYREG_PRT3_DR -SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_DAT2__MASK EQU 0x20 -SD_DAT2__PORT EQU 3 -SD_DAT2__PRT EQU CYREG_PRT3_PRT -SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_DAT2__PS EQU CYREG_PRT3_PS -SD_DAT2__SHIFT EQU 5 -SD_DAT2__SLW EQU CYREG_PRT3_SLW - -; SD_Data_Clk -SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 -SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 -SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 -SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Data_Clk__INDEX EQU 0x00 -SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Data_Clk__PM_ACT_MSK EQU 0x01 -SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Data_Clk__PM_STBY_MSK EQU 0x01 - -; SD_MISO -SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 -SD_MISO__0__MASK EQU 0x02 -SD_MISO__0__PC EQU CYREG_PRT3_PC1 -SD_MISO__0__PORT EQU 3 -SD_MISO__0__SHIFT EQU 1 -SD_MISO__AG EQU CYREG_PRT3_AG -SD_MISO__AMUX EQU CYREG_PRT3_AMUX -SD_MISO__BIE EQU CYREG_PRT3_BIE -SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MISO__BYP EQU CYREG_PRT3_BYP -SD_MISO__CTL EQU CYREG_PRT3_CTL -SD_MISO__DM0 EQU CYREG_PRT3_DM0 -SD_MISO__DM1 EQU CYREG_PRT3_DM1 -SD_MISO__DM2 EQU CYREG_PRT3_DM2 -SD_MISO__DR EQU CYREG_PRT3_DR -SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MISO__MASK EQU 0x02 -SD_MISO__PORT EQU 3 -SD_MISO__PRT EQU CYREG_PRT3_PRT -SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MISO__PS EQU CYREG_PRT3_PS -SD_MISO__SHIFT EQU 1 -SD_MISO__SLW EQU CYREG_PRT3_SLW - -; SD_MOSI -SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 -SD_MOSI__0__MASK EQU 0x08 -SD_MOSI__0__PC EQU CYREG_PRT3_PC3 -SD_MOSI__0__PORT EQU 3 -SD_MOSI__0__SHIFT EQU 3 -SD_MOSI__AG EQU CYREG_PRT3_AG -SD_MOSI__AMUX EQU CYREG_PRT3_AMUX -SD_MOSI__BIE EQU CYREG_PRT3_BIE -SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MOSI__BYP EQU CYREG_PRT3_BYP -SD_MOSI__CTL EQU CYREG_PRT3_CTL -SD_MOSI__DM0 EQU CYREG_PRT3_DM0 -SD_MOSI__DM1 EQU CYREG_PRT3_DM1 -SD_MOSI__DM2 EQU CYREG_PRT3_DM2 -SD_MOSI__DR EQU CYREG_PRT3_DR -SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MOSI__MASK EQU 0x08 -SD_MOSI__PORT EQU 3 -SD_MOSI__PRT EQU CYREG_PRT3_PRT -SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MOSI__PS EQU CYREG_PRT3_PS -SD_MOSI__SHIFT EQU 3 -SD_MOSI__SLW EQU CYREG_PRT3_SLW - ; SD_RX_DMA SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 @@ -2612,40 +2455,6 @@ SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -; SD_SCK -SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 -SD_SCK__0__MASK EQU 0x04 -SD_SCK__0__PC EQU CYREG_PRT3_PC2 -SD_SCK__0__PORT EQU 3 -SD_SCK__0__SHIFT EQU 2 -SD_SCK__AG EQU CYREG_PRT3_AG -SD_SCK__AMUX EQU CYREG_PRT3_AMUX -SD_SCK__BIE EQU CYREG_PRT3_BIE -SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_SCK__BYP EQU CYREG_PRT3_BYP -SD_SCK__CTL EQU CYREG_PRT3_CTL -SD_SCK__DM0 EQU CYREG_PRT3_DM0 -SD_SCK__DM1 EQU CYREG_PRT3_DM1 -SD_SCK__DM2 EQU CYREG_PRT3_DM2 -SD_SCK__DR EQU CYREG_PRT3_DR -SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_SCK__MASK EQU 0x04 -SD_SCK__PORT EQU 3 -SD_SCK__PRT EQU CYREG_PRT3_PRT -SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_SCK__PS EQU CYREG_PRT3_PS -SD_SCK__SHIFT EQU 2 -SD_SCK__SLW EQU CYREG_PRT3_SLW - ; SD_TX_DMA SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_TX_DMA__DRQ_NUMBER EQU 3 @@ -2666,269 +2475,285 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -; USBFS -USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_arb_int__INTC_MASK EQU 0x400000 -USBFS_arb_int__INTC_NUMBER EQU 22 -USBFS_arb_int__INTC_PRIOR_NUM EQU 6 -USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 -USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_bus_reset__INTC_MASK EQU 0x800000 -USBFS_bus_reset__INTC_NUMBER EQU 23 -USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 -USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 -USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 -USBFS_Dm__0__MASK EQU 0x80 -USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 -USBFS_Dm__0__PORT EQU 15 -USBFS_Dm__0__SHIFT EQU 7 -USBFS_Dm__AG EQU CYREG_PRT15_AG -USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dm__BIE EQU CYREG_PRT15_BIE -USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dm__BYP EQU CYREG_PRT15_BYP -USBFS_Dm__CTL EQU CYREG_PRT15_CTL -USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dm__DR EQU CYREG_PRT15_DR -USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dm__MASK EQU 0x80 -USBFS_Dm__PORT EQU 15 -USBFS_Dm__PRT EQU CYREG_PRT15_PRT -USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dm__PS EQU CYREG_PRT15_PS -USBFS_Dm__SHIFT EQU 7 -USBFS_Dm__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 -USBFS_Dp__0__MASK EQU 0x40 -USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 -USBFS_Dp__0__PORT EQU 15 -USBFS_Dp__0__SHIFT EQU 6 -USBFS_Dp__AG EQU CYREG_PRT15_AG -USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dp__BIE EQU CYREG_PRT15_BIE -USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dp__BYP EQU CYREG_PRT15_BYP -USBFS_Dp__CTL EQU CYREG_PRT15_CTL -USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dp__DR EQU CYREG_PRT15_DR -USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT -USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dp__MASK EQU 0x40 -USBFS_Dp__PORT EQU 15 -USBFS_Dp__PRT EQU CYREG_PRT15_PRT -USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dp__PS EQU CYREG_PRT15_PS -USBFS_Dp__SHIFT EQU 6 -USBFS_Dp__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 -USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_dp_int__INTC_MASK EQU 0x1000 -USBFS_dp_int__INTC_NUMBER EQU 12 -USBFS_dp_int__INTC_PRIOR_NUM EQU 7 -USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 -USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_0__INTC_MASK EQU 0x1000000 -USBFS_ep_0__INTC_NUMBER EQU 24 -USBFS_ep_0__INTC_PRIOR_NUM EQU 7 -USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 -USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 -USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 -USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 -USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 -USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 -USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 -USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 -USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 -USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_sof_int__INTC_MASK EQU 0x200000 -USBFS_sof_int__INTC_NUMBER EQU 21 -USBFS_sof_int__INTC_PRIOR_NUM EQU 7 -USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 -USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG -USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG -USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN -USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR -USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG -USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN -USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR -USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG -USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN -USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR -USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG -USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN -USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR -USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG -USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN -USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR -USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG -USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN -USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR -USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG -USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN -USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR -USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG -USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN -USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR -USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN -USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR -USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR -USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA -USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB -USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA -USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB -USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR -USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA -USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB -USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA -USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB -USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR -USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA -USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB -USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA -USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB -USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR -USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA -USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB -USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA -USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB -USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR -USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA -USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB -USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA -USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB -USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR -USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA -USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB -USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA -USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB -USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR -USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA -USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB -USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA -USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB -USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR -USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA -USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB -USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA -USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB -USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE -USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT -USBFS_USB__CR0 EQU CYREG_USB_CR0 -USBFS_USB__CR1 EQU CYREG_USB_CR1 -USBFS_USB__CWA EQU CYREG_USB_CWA -USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB -USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES -USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB -USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG -USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE -USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE -USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT -USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR -USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 -USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 -USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 -USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 -USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 -USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 -USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 -USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 -USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE -USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 -USBFS_USB__PM_ACT_MSK EQU 0x01 -USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 -USBFS_USB__PM_STBY_MSK EQU 0x01 -USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN -USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR -USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 -USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 -USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 -USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 -USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 -USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 -USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 -USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 -USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 -USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 -USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 -USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 -USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 -USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 -USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 -USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 -USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 -USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 -USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 -USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 -USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 -USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 -USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 -USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 -USBFS_USB__SOF0 EQU CYREG_USB_SOF0 -USBFS_USB__SOF1 EQU CYREG_USB_SOF1 -USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 -USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 +; SCSI_Noise +SCSI_Noise__0__AG EQU CYREG_PRT12_AG +SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP +SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT12_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Noise__0__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Noise__0__MASK EQU 0x20 +SCSI_Noise__0__PC EQU CYREG_PRT12_PC5 +SCSI_Noise__0__PORT EQU 12 +SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT12_PS +SCSI_Noise__0__SHIFT EQU 5 +SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW +SCSI_Noise__1__AG EQU CYREG_PRT6_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT6_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE4 +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__1__MASK EQU 0x10 +SCSI_Noise__1__PC EQU CYREG_PRT6_PC4 +SCSI_Noise__1__PORT EQU 6 +SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT6_PS +SCSI_Noise__1__SHIFT EQU 4 +SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__2__AG EQU CYREG_PRT5_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT5_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Noise__2__INTTYPE EQU CYREG_PICU5_INTTYPE0 +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Noise__2__MASK EQU 0x01 +SCSI_Noise__2__PC EQU CYREG_PRT5_PC0 +SCSI_Noise__2__PORT EQU 5 +SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT5_PS +SCSI_Noise__2__SHIFT EQU 0 +SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW +SCSI_Noise__3__AG EQU CYREG_PRT6_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT6_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__3__INTTYPE EQU CYREG_PICU6_INTTYPE6 +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__3__MASK EQU 0x40 +SCSI_Noise__3__PC EQU CYREG_PRT6_PC6 +SCSI_Noise__3__PORT EQU 6 +SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT6_PS +SCSI_Noise__3__SHIFT EQU 6 +SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__4__AG EQU CYREG_PRT6_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT6_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__4__MASK EQU 0x20 +SCSI_Noise__4__PC EQU CYREG_PRT6_PC5 +SCSI_Noise__4__PORT EQU 6 +SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT6_PS +SCSI_Noise__4__SHIFT EQU 5 +SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x20 +SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5 +SCSI_Noise__ACK__PORT EQU 6 +SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS +SCSI_Noise__ACK__SHIFT EQU 5 +SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG +SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP +SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Noise__ATN__MASK EQU 0x20 +SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5 +SCSI_Noise__ATN__PORT EQU 12 +SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS +SCSI_Noise__ATN__SHIFT EQU 5 +SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE4 +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x10 +SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4 +SCSI_Noise__BSY__PORT EQU 6 +SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS +SCSI_Noise__BSY__SHIFT EQU 4 +SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT6_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT6_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__RST__INTTYPE EQU CYREG_PICU6_INTTYPE6 +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__RST__MASK EQU 0x40 +SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6 +SCSI_Noise__RST__PORT EQU 6 +SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT6_PS +SCSI_Noise__RST__SHIFT EQU 6 +SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU5_INTTYPE0 +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x01 +SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0 +SCSI_Noise__SEL__PORT EQU 5 +SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS +SCSI_Noise__SEL__SHIFT EQU 0 +SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW ; scsiTarget scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 @@ -2997,6 +2822,83 @@ scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST +; Debug_Timer +Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x01 +Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 +Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 +Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 +Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 +Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 +Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 +Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 + +; SCSI_RX_DMA +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_TX_DMA +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SD_Data_Clk +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 + ; timer_clock timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 @@ -3008,12 +2910,108 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 +; SCSI_RST_ISR +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x02 +SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_SEL_ISR +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_Filtered +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST + +; SCSI_CTL_PHASE +SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK + +; SCSI_Glitch_Ctl +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK + +; SCSI_Parity_Error +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST + ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 16 +CYDEV_CHIP_DIE_PSOC4A EQU 18 CYDEV_CHIP_DIE_PSOC5LP EQU 2 CYDEV_CHIP_DIE_PSOC5TM EQU 3 CYDEV_CHIP_DIE_TMA4 EQU 4 @@ -3029,32 +3027,34 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 16 -CYDEV_CHIP_MEMBER_4D EQU 12 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 CYDEV_CHIP_MEMBER_4E EQU 6 -CYDEV_CHIP_MEMBER_4F EQU 17 +CYDEV_CHIP_MEMBER_4F EQU 19 CYDEV_CHIP_MEMBER_4G EQU 4 -CYDEV_CHIP_MEMBER_4H EQU 15 -CYDEV_CHIP_MEMBER_4I EQU 21 -CYDEV_CHIP_MEMBER_4J EQU 13 -CYDEV_CHIP_MEMBER_4K EQU 14 -CYDEV_CHIP_MEMBER_4L EQU 20 -CYDEV_CHIP_MEMBER_4M EQU 19 -CYDEV_CHIP_MEMBER_4N EQU 9 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 CYDEV_CHIP_MEMBER_4O EQU 7 -CYDEV_CHIP_MEMBER_4P EQU 18 -CYDEV_CHIP_MEMBER_4Q EQU 11 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 CYDEV_CHIP_MEMBER_4R EQU 8 -CYDEV_CHIP_MEMBER_4S EQU 10 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 CYDEV_CHIP_MEMBER_5A EQU 3 CYDEV_CHIP_MEMBER_5B EQU 2 -CYDEV_CHIP_MEMBER_6A EQU 22 -CYDEV_CHIP_MEMBER_FM3 EQU 26 -CYDEV_CHIP_MEMBER_FM4 EQU 27 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -3080,6 +3080,7 @@ CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 @@ -3099,14 +3100,17 @@ CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 -CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0 -CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c index e8e92b1..e793f24 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cymetadata.c * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file defines all extra memory spaces that need to be included. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index a6cfaf8..662a1b9 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: project.h * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * It contains references to all generated header files and should not be modified. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -85,6 +85,7 @@ #include "cyPm.h" #include "CySpc.h" #include "cytypes.h" +#include "cy_em_eeprom.h" /*[]*/ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx old mode 100644 new mode 100755 index 510d5c6..1f3c37d --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,12 +1,42 @@ +