Glitch filter configuration options and update to PSoC Creator v3.2

CHANGELOG

@@ -1,4 +1,4 @@
-201507XX		4.4
+20150813		4.4
 	- Added configuration option to allow SCSI2 mode. This option is OFF by
 	default, and should only be enabled when using the SCSI2SD with a SCSI2 host
 	controller. Extra timing delays are added in the default SCSI1/SASI mode to
@@ -12,6 +12,7 @@
 	SCSI2SD now negotiates back to async transfers instead of simply
 	rejecting the message.
 	- Fixed INQUIRY response to commands lacking an allocation length.
+	- Firmware development updated to PSoC Creator 3.2 (from 3.1)
 
 20150614        4.3
 	- Added configurable disk geometry.

readme.txt

@@ -76,9 +76,11 @@ Compatibility
     Amiga 2000 (B2000 rev 6.4 ECS) with DKB RapidFire SCSI 1 card
     Amiga 4000 equipped with CyberStorm PPC using 68pin adapter.
     Atari TT030 System V
+    Atari TT running TOS 3.06 with HDDRIVER software version 9.06
     Atari MEGA STE
         needs J3 TERMPWR jumper
         1GB limit (--blocks=2048000). The OS will fail to read the boot sector if the disk is >= 1GB.
+    Atari Falcon, TOS 4.02, HDDRIVER 9.06 driver
     Sharp X68000
         SASI models supported. See gamesx.com for information on building a custom cable.
         needs J3 TERMPWR jumper

software/SCSI2SD/src/config.c

@@ -32,7 +32,7 @@
 
 #include <string.h>
 
-static const uint16_t FIRMWARE_VERSION = 0x0430;
+static const uint16_t FIRMWARE_VERSION = 0x0440;
 
 // 1 flash row
 static const uint8_t DEFAULT_CONFIG[256] =

software/SCSI2SD/src/scsiPhy.c

@@ -505,12 +505,12 @@ void scsiPhyInit()
 
 	SCSI_SEL_ISR_StartEx(scsiSelectionISR);
 
-/*
 	// Disable the glitch filter for ACK to improve performance.
-	// TODO NEED SOME CONFIG
-	SCSI_Glitch_Ctl_Write(1);
-	CY_SET_REG8(scsiTarget_datapath__D0_REG, 0);
-*/
+	if (getConfigByIndex(0)->flags & CONFIG_DISABLE_GLITCH)
+	{
+		SCSI_Glitch_Ctl_Write(1);
+		CY_SET_REG8(scsiTarget_datapath__D0_REG, 0);
+	}
 
 }
 

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void Debug_Timer_Interrupt_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void Debug_Timer_Interrupt_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(Debug_Timer_Interrupt_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling Debug_Timer_Interrupt_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use Debug_Timer_Interrupt_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress Debug_Timer_Interrupt_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling Debug_Timer_Interrupt_Start
-*   or Debug_Timer_Interrupt_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void Debug_Timer_Interrupt_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 Debug_Timer_Interrupt_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 Debug_Timer_Interrupt_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 Debug_Timer_Interrupt_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void Debug_Timer_Interrupt_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void Debug_Timer_Interrupt_SetPending(void)
 {
@@ -336,7 +379,12 @@ void Debug_Timer_Interrupt_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void SCSI_RST_ISR_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void SCSI_RST_ISR_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(SCSI_RST_ISR_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling SCSI_RST_ISR_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use SCSI_RST_ISR_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress SCSI_RST_ISR_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling SCSI_RST_ISR_Start
-*   or SCSI_RST_ISR_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void SCSI_RST_ISR_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 SCSI_RST_ISR_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 SCSI_RST_ISR_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 SCSI_RST_ISR_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void SCSI_RST_ISR_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void SCSI_RST_ISR_SetPending(void)
 {
@@ -336,7 +379,12 @@ void SCSI_RST_ISR_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void SCSI_RX_DMA_COMPLETE_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(SCSI_RX_DMA_COMPLETE_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use SCSI_RX_DMA_COMPLETE_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
-*   or SCSI_RX_DMA_COMPLETE_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 SCSI_RX_DMA_COMPLETE_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void SCSI_RX_DMA_COMPLETE_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void SCSI_RX_DMA_COMPLETE_SetPending(void)
 {
@@ -336,7 +379,12 @@ void SCSI_RX_DMA_COMPLETE_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void SCSI_SEL_ISR_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void SCSI_SEL_ISR_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(SCSI_SEL_ISR_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling SCSI_SEL_ISR_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use SCSI_SEL_ISR_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress SCSI_SEL_ISR_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling SCSI_SEL_ISR_Start
-*   or SCSI_SEL_ISR_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void SCSI_SEL_ISR_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 SCSI_SEL_ISR_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 SCSI_SEL_ISR_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 SCSI_SEL_ISR_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void SCSI_SEL_ISR_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void SCSI_SEL_ISR_SetPending(void)
 {
@@ -336,7 +379,12 @@ void SCSI_SEL_ISR_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void SCSI_TX_DMA_COMPLETE_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(SCSI_TX_DMA_COMPLETE_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use SCSI_TX_DMA_COMPLETE_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
-*   or SCSI_TX_DMA_COMPLETE_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 SCSI_TX_DMA_COMPLETE_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void SCSI_TX_DMA_COMPLETE_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void SCSI_TX_DMA_COMPLETE_SetPending(void)
 {
@@ -336,7 +379,12 @@ void SCSI_TX_DMA_COMPLETE_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void SD_RX_DMA_COMPLETE_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(SD_RX_DMA_COMPLETE_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use SD_RX_DMA_COMPLETE_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress SD_RX_DMA_COMPLETE_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
-*   or SD_RX_DMA_COMPLETE_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 SD_RX_DMA_COMPLETE_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 SD_RX_DMA_COMPLETE_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 SD_RX_DMA_COMPLETE_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void SD_RX_DMA_COMPLETE_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void SD_RX_DMA_COMPLETE_SetPending(void)
 {
@@ -336,7 +379,12 @@ void SD_RX_DMA_COMPLETE_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void SD_TX_DMA_COMPLETE_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(SD_TX_DMA_COMPLETE_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use SD_TX_DMA_COMPLETE_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress SD_TX_DMA_COMPLETE_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
-*   or SD_TX_DMA_COMPLETE_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 SD_TX_DMA_COMPLETE_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 SD_TX_DMA_COMPLETE_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 SD_TX_DMA_COMPLETE_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void SD_TX_DMA_COMPLETE_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void SD_TX_DMA_COMPLETE_SetPending(void)
 {
@@ -336,7 +379,12 @@ void SD_TX_DMA_COMPLETE_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h

@@ -1,14 +1,14 @@
 /*******************************************************************************
 * FILENAME: cydevice.h
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator  3.1
+* PSoC Creator  3.2
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h

@@ -1,14 +1,14 @@
 /*******************************************************************************
 * FILENAME: cydevice_trm.h
 * 
-* PSoC Creator  3.1
+* PSoC Creator  3.2
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc

@@ -1,14 +1,14 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu.inc
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator  3.1
+* PSoC Creator  3.2
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc

@@ -1,14 +1,14 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu_trm.inc
 * 
-* PSoC Creator  3.1
+* PSoC Creator  3.2
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc

@@ -1,13 +1,13 @@
 ;
 ; FILENAME: cydeviceiar.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator  3.1
+; PSoC Creator  3.2
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions, 
 ; disclaimers, and limitations in the end user license agreement accompanying 
 ; the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc

@@ -1,13 +1,13 @@
 ;
 ; FILENAME: cydeviceiar_trm.inc
 ; 
-; PSoC Creator  3.1
+; PSoC Creator  3.2
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions, 
 ; disclaimers, and limitations in the end user license agreement accompanying 
 ; the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc

@@ -1,13 +1,13 @@
 ;
 ; FILENAME: cydevicerv.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator  3.1
+; PSoC Creator  3.2
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions, 
 ; disclaimers, and limitations in the end user license agreement accompanying 
 ; the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc

@@ -1,13 +1,13 @@
 ;
 ; FILENAME: cydevicerv_trm.inc
 ; 
-; PSoC Creator  3.1
+; PSoC Creator  3.2
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions, 
 ; disclaimers, and limitations in the end user license agreement accompanying 
 ; the software package with which this file was provided.

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h

@@ -1,7 +1,7 @@
 #ifndef INCLUDED_CYFITTER_H
 #define INCLUDED_CYFITTER_H
-#include <cydevice.h>
-#include <cydevice_trm.h>
+#include "cydevice.h"
+#include "cydevice_trm.h"
 
 /* LED1 */
 #define LED1__0__MASK 0x08u
@@ -407,8 +407,8 @@
 #define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL
 #define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL
 #define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_RxStsReg__4__POS 4
 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@@ -416,9 +416,9 @@
 #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
 #define SDCard_BSPIM_RxStsReg__6__POS 6
 #define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
@@ -1875,6 +1875,15 @@
 #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
 #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
 #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@@ -1887,37 +1896,28 @@
 #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
 #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
 
 /* SCSI_Out_Ctl */
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL
 #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK
 
 /* SCSI_Out_DBx */
 #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
@@ -2717,6 +2717,8 @@
 #define scsiTarget_StatusReg__0__POS 0
 #define scsiTarget_StatusReg__1__MASK 0x02u
 #define scsiTarget_StatusReg__1__POS 1
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
 #define scsiTarget_StatusReg__2__MASK 0x04u
 #define scsiTarget_StatusReg__2__POS 2
 #define scsiTarget_StatusReg__3__MASK 0x08u
@@ -2724,9 +2726,13 @@
 #define scsiTarget_StatusReg__4__MASK 0x10u
 #define scsiTarget_StatusReg__4__POS 4
 #define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB02_MSK
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB02_ST
 
 /* Debug_Timer_Interrupt */
 #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -2847,8 +2853,8 @@
 #define SCSI_Filtered_sts_sts_reg__0__POS 0
 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
 #define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST
 #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
 #define SCSI_Filtered_sts_sts_reg__2__POS 2
 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@@ -2856,57 +2862,57 @@
 #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
 #define SCSI_Filtered_sts_sts_reg__4__POS 4
 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST
 
 /* SCSI_CTL_PHASE */
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
 
 /* SCSI_Glitch_Ctl */
 #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
 #define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
 
 /* SCSI_Parity_Error */
 #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
@@ -2915,18 +2921,24 @@
 #define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
 #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
 #define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
+#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
 #define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
 #define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
 
 /* Miscellaneous */
 #define BCLK__BUS_CLK__HZ 50000000U
 #define BCLK__BUS_CLK__KHZ 50000U
 #define BCLK__BUS_CLK__MHZ 50U
-#define CY_VERSION "PSoC Creator  3.1"
+#define CY_PROJECT_NAME "SCSI2SD"
+#define CY_VERSION "PSoC Creator  3.2"
+#define CYDEV_CHIP_DIE_GEN4 2u
 #define CYDEV_CHIP_DIE_LEOPARD 1u
-#define CYDEV_CHIP_DIE_PANTHER 6u
-#define CYDEV_CHIP_DIE_PSOC4A 3u
-#define CYDEV_CHIP_DIE_PSOC5LP 5u
+#define CYDEV_CHIP_DIE_PANTHER 12u
+#define CYDEV_CHIP_DIE_PSOC4A 5u
+#define CYDEV_CHIP_DIE_PSOC5LP 11u
 #define CYDEV_CHIP_DIE_UNKNOWN 0u
 #define CYDEV_CHIP_FAMILY_PSOC3 1u
 #define CYDEV_CHIP_FAMILY_PSOC4 2u
@@ -2935,15 +2947,23 @@
 #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
 #define CYDEV_CHIP_JTAG_ID 0x2E133069u
 #define CYDEV_CHIP_MEMBER_3A 1u
-#define CYDEV_CHIP_MEMBER_4A 3u
-#define CYDEV_CHIP_MEMBER_4D 2u
-#define CYDEV_CHIP_MEMBER_4F 4u
-#define CYDEV_CHIP_MEMBER_5A 6u
-#define CYDEV_CHIP_MEMBER_5B 5u
+#define CYDEV_CHIP_MEMBER_4A 5u
+#define CYDEV_CHIP_MEMBER_4C 9u
+#define CYDEV_CHIP_MEMBER_4D 3u
+#define CYDEV_CHIP_MEMBER_4E 4u
+#define CYDEV_CHIP_MEMBER_4F 6u
+#define CYDEV_CHIP_MEMBER_4G 2u
+#define CYDEV_CHIP_MEMBER_4L 8u
+#define CYDEV_CHIP_MEMBER_4M 7u
+#define CYDEV_CHIP_MEMBER_5A 11u
+#define CYDEV_CHIP_MEMBER_5B 10u
 #define CYDEV_CHIP_MEMBER_UNKNOWN 0u
 #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
 #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
 #define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
+#define CYDEV_CHIP_REV_GEN4_ES 17u
+#define CYDEV_CHIP_REV_GEN4_ES2 33u
+#define CYDEV_CHIP_REV_GEN4_PRODUCTION 17u
 #define CYDEV_CHIP_REV_LEOPARD_ES1 0u
 #define CYDEV_CHIP_REV_LEOPARD_ES2 1u
 #define CYDEV_CHIP_REV_LEOPARD_ES3 3u
@@ -2961,8 +2981,16 @@
 #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
 #define CYDEV_CHIP_REVISION_4A_ES0 17u
 #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
+#define CYDEV_CHIP_REVISION_4G_ES 17u
+#define CYDEV_CHIP_REVISION_4G_ES2 33u
+#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_5A_ES0 0u
 #define CYDEV_CHIP_REVISION_5A_ES1 1u
 #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
@@ -2985,9 +3013,6 @@
 #define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
 #define CYDEV_DEBUG_ENABLE_MASK 0x20u
 #define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
-#define CYDEV_DEBUGGING_DPS_Disable 3
-#define CYDEV_DEBUGGING_DPS_JTAG_4 1
-#define CYDEV_DEBUGGING_DPS_JTAG_5 0
 #define CYDEV_DEBUGGING_DPS_SWD 2
 #define CYDEV_DEBUGGING_DPS_SWD_SWV 6
 #define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
@@ -3000,7 +3025,9 @@
 #define CYDEV_INTR_RISING 0x0000007Eu
 #define CYDEV_PROJ_TYPE 2
 #define CYDEV_PROJ_TYPE_BOOTLOADER 1
+#define CYDEV_PROJ_TYPE_LAUNCHER 5
 #define CYDEV_PROJ_TYPE_LOADABLE 2
+#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
 #define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
 #define CYDEV_PROJ_TYPE_STANDARD 0
 #define CYDEV_PROTECTION_ENABLE 0

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h

@@ -1,12 +1,14 @@
 /*******************************************************************************
 * FILENAME: cyfitter_cfg.h
-* PSoC Creator  3.1
+* 
+* PSoC Creator  3.2
 *
-* Description:
+* DESCRIPTION:
+* This file provides basic startup and mux configration settings
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -15,7 +17,7 @@
 #ifndef CYFITTER_CFG_H
 #define CYFITTER_CFG_H
 
-#include <cytypes.h>
+#include "cytypes.h"
 
 extern void cyfitter_cfg(void);
 

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc

@@ -407,8 +407,8 @@
 .set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL
 .set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL
 .set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_RxStsReg__4__POS, 4
 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@@ -416,9 +416,9 @@
 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
 .set SDCard_BSPIM_RxStsReg__6__POS, 6
 .set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
@@ -1875,6 +1875,15 @@
 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@@ -1887,37 +1896,28 @@
 .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
 .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
 
 /* SCSI_Out_Ctl */
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL
 .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK
 
 /* SCSI_Out_DBx */
 .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
@@ -2717,6 +2717,8 @@
 .set scsiTarget_StatusReg__0__POS, 0
 .set scsiTarget_StatusReg__1__MASK, 0x02
 .set scsiTarget_StatusReg__1__POS, 1
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
 .set scsiTarget_StatusReg__2__MASK, 0x04
 .set scsiTarget_StatusReg__2__POS, 2
 .set scsiTarget_StatusReg__3__MASK, 0x08
@@ -2724,9 +2726,13 @@
 .set scsiTarget_StatusReg__4__MASK, 0x10
 .set scsiTarget_StatusReg__4__POS, 4
 .set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB02_MSK
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB02_ST
 
 /* Debug_Timer_Interrupt */
 .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -2847,8 +2853,8 @@
 .set SCSI_Filtered_sts_sts_reg__0__POS, 0
 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
 .set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB10_11_ST
 .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
 .set SCSI_Filtered_sts_sts_reg__2__POS, 2
 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@@ -2856,57 +2862,57 @@
 .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
 .set SCSI_Filtered_sts_sts_reg__4__POS, 4
 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB07_MSK
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB07_ST
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB10_MSK
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB10_ST
 
 /* SCSI_CTL_PHASE */
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
 
 /* SCSI_Glitch_Ctl */
 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
 
 /* SCSI_Parity_Error */
 .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
@@ -2915,17 +2921,22 @@
 .set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
 .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
 .set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
+.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
 .set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
 .set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
 
 /* Miscellaneous */
 .set BCLK__BUS_CLK__HZ, 50000000
 .set BCLK__BUS_CLK__KHZ, 50000
 .set BCLK__BUS_CLK__MHZ, 50
+.set CYDEV_CHIP_DIE_GEN4, 2
 .set CYDEV_CHIP_DIE_LEOPARD, 1
-.set CYDEV_CHIP_DIE_PANTHER, 6
-.set CYDEV_CHIP_DIE_PSOC4A, 3
-.set CYDEV_CHIP_DIE_PSOC5LP, 5
+.set CYDEV_CHIP_DIE_PANTHER, 12
+.set CYDEV_CHIP_DIE_PSOC4A, 5
+.set CYDEV_CHIP_DIE_PSOC5LP, 11
 .set CYDEV_CHIP_DIE_UNKNOWN, 0
 .set CYDEV_CHIP_FAMILY_PSOC3, 1
 .set CYDEV_CHIP_FAMILY_PSOC4, 2
@@ -2934,15 +2945,23 @@
 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
 .set CYDEV_CHIP_JTAG_ID, 0x2E133069
 .set CYDEV_CHIP_MEMBER_3A, 1
-.set CYDEV_CHIP_MEMBER_4A, 3
-.set CYDEV_CHIP_MEMBER_4D, 2
-.set CYDEV_CHIP_MEMBER_4F, 4
-.set CYDEV_CHIP_MEMBER_5A, 6
-.set CYDEV_CHIP_MEMBER_5B, 5
+.set CYDEV_CHIP_MEMBER_4A, 5
+.set CYDEV_CHIP_MEMBER_4C, 9
+.set CYDEV_CHIP_MEMBER_4D, 3
+.set CYDEV_CHIP_MEMBER_4E, 4
+.set CYDEV_CHIP_MEMBER_4F, 6
+.set CYDEV_CHIP_MEMBER_4G, 2
+.set CYDEV_CHIP_MEMBER_4L, 8
+.set CYDEV_CHIP_MEMBER_4M, 7
+.set CYDEV_CHIP_MEMBER_5A, 11
+.set CYDEV_CHIP_MEMBER_5B, 10
 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0
 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
 .set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
+.set CYDEV_CHIP_REV_GEN4_ES, 17
+.set CYDEV_CHIP_REV_GEN4_ES2, 33
+.set CYDEV_CHIP_REV_GEN4_PRODUCTION, 17
 .set CYDEV_CHIP_REV_LEOPARD_ES1, 0
 .set CYDEV_CHIP_REV_LEOPARD_ES2, 1
 .set CYDEV_CHIP_REV_LEOPARD_ES3, 3
@@ -2960,8 +2979,16 @@
 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
 .set CYDEV_CHIP_REVISION_4A_ES0, 17
 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0
+.set CYDEV_CHIP_REVISION_4G_ES, 17
+.set CYDEV_CHIP_REVISION_4G_ES2, 33
+.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_5A_ES0, 0
 .set CYDEV_CHIP_REVISION_5A_ES1, 1
 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
@@ -2984,9 +3011,6 @@
 .set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
 .set CYDEV_DEBUG_ENABLE_MASK, 0x20
 .set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
-.set CYDEV_DEBUGGING_DPS_Disable, 3
-.set CYDEV_DEBUGGING_DPS_JTAG_4, 1
-.set CYDEV_DEBUGGING_DPS_JTAG_5, 0
 .set CYDEV_DEBUGGING_DPS_SWD, 2
 .set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
 .set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
@@ -2999,7 +3023,9 @@
 .set CYDEV_INTR_RISING, 0x0000007E
 .set CYDEV_PROJ_TYPE, 2
 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1
+.set CYDEV_PROJ_TYPE_LAUNCHER, 5
 .set CYDEV_PROJ_TYPE_LOADABLE, 2
+.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4
 .set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
 .set CYDEV_PROJ_TYPE_STANDARD, 0
 .set CYDEV_PROTECTION_ENABLE, 0

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc

@@ -407,8 +407,8 @@ SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
 SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
 SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
 SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_RxStsReg__4__POS EQU 4
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -416,9 +416,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@@ -1875,6 +1875,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@@ -1887,37 +1896,28 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
 SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
 
 /* SCSI_Out_Ctl */
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
 
 /* SCSI_Out_DBx */
 SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@@ -2717,6 +2717,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0
 scsiTarget_StatusReg__1__MASK EQU 0x02
 scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
 scsiTarget_StatusReg__2__MASK EQU 0x04
 scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08
@@ -2724,9 +2726,13 @@ scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__4__MASK EQU 0x10
 scsiTarget_StatusReg__4__POS EQU 4
 scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST
 
 /* Debug_Timer_Interrupt */
 Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2847,8 +2853,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST
 SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
 SCSI_Filtered_sts_sts_reg__2__POS EQU 2
 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2856,57 +2862,57 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
 SCSI_Filtered_sts_sts_reg__4__POS EQU 4
 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST
 
 /* SCSI_CTL_PHASE */
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
 
 /* SCSI_Glitch_Ctl */
 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
 SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
 
 /* SCSI_Parity_Error */
 SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
@@ -2915,17 +2921,22 @@ SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_AC
 SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
 SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
 SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
 SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
 SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
 
 /* Miscellaneous */
 BCLK__BUS_CLK__HZ EQU 50000000
 BCLK__BUS_CLK__KHZ EQU 50000
 BCLK__BUS_CLK__MHZ EQU 50
+CYDEV_CHIP_DIE_GEN4 EQU 2
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 6
-CYDEV_CHIP_DIE_PSOC4A EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 5
+CYDEV_CHIP_DIE_PANTHER EQU 12
+CYDEV_CHIP_DIE_PSOC4A EQU 5
+CYDEV_CHIP_DIE_PSOC5LP EQU 11
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
@@ -2934,15 +2945,23 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 3
-CYDEV_CHIP_MEMBER_4D EQU 2
-CYDEV_CHIP_MEMBER_4F EQU 4
-CYDEV_CHIP_MEMBER_5A EQU 6
-CYDEV_CHIP_MEMBER_5B EQU 5
+CYDEV_CHIP_MEMBER_4A EQU 5
+CYDEV_CHIP_MEMBER_4C EQU 9
+CYDEV_CHIP_MEMBER_4D EQU 3
+CYDEV_CHIP_MEMBER_4E EQU 4
+CYDEV_CHIP_MEMBER_4F EQU 6
+CYDEV_CHIP_MEMBER_4G EQU 2
+CYDEV_CHIP_MEMBER_4L EQU 8
+CYDEV_CHIP_MEMBER_4M EQU 7
+CYDEV_CHIP_MEMBER_5A EQU 11
+CYDEV_CHIP_MEMBER_5B EQU 10
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
 CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_GEN4_ES EQU 17
+CYDEV_CHIP_REV_GEN4_ES2 EQU 33
+CYDEV_CHIP_REV_GEN4_PRODUCTION EQU 17
 CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
 CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
 CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
@@ -2960,8 +2979,16 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
+CYDEV_CHIP_REVISION_4G_ES EQU 17
+CYDEV_CHIP_REVISION_4G_ES2 EQU 33
+CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
@@ -2984,9 +3011,6 @@ CYDEV_CONFIGURATION_MODE_DMA EQU 2
 CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
 CYDEV_DEBUG_ENABLE_MASK EQU 0x20
 CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
-CYDEV_DEBUGGING_DPS_Disable EQU 3
-CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
-CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
 CYDEV_DEBUGGING_DPS_SWD EQU 2
 CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
 CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
@@ -2999,7 +3023,9 @@ CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
 CYDEV_INTR_RISING EQU 0x0000007E
 CYDEV_PROJ_TYPE EQU 2
 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
+CYDEV_PROJ_TYPE_LAUNCHER EQU 5
 CYDEV_PROJ_TYPE_LOADABLE EQU 2
+CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
 CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
 CYDEV_PROJ_TYPE_STANDARD EQU 0
 CYDEV_PROTECTION_ENABLE EQU 0

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc

@@ -407,8 +407,8 @@ SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
 SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
 SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
 SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_RxStsReg__4__POS EQU 4
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -416,9 +416,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@@ -1875,6 +1875,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@@ -1887,37 +1896,28 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
 SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
 
 ; SCSI_Out_Ctl
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
 
 ; SCSI_Out_DBx
 SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@@ -2717,6 +2717,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0
 scsiTarget_StatusReg__1__MASK EQU 0x02
 scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
 scsiTarget_StatusReg__2__MASK EQU 0x04
 scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08
@@ -2724,9 +2726,13 @@ scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__4__MASK EQU 0x10
 scsiTarget_StatusReg__4__POS EQU 4
 scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST
 
 ; Debug_Timer_Interrupt
 Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2847,8 +2853,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST
 SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
 SCSI_Filtered_sts_sts_reg__2__POS EQU 2
 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2856,57 +2862,57 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
 SCSI_Filtered_sts_sts_reg__4__POS EQU 4
 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST
 
 ; SCSI_CTL_PHASE
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
 
 ; SCSI_Glitch_Ctl
 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
 SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
 
 ; SCSI_Parity_Error
 SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
@@ -2915,17 +2921,22 @@ SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_AC
 SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
 SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
 SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
 SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
 SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
 
 ; Miscellaneous
 BCLK__BUS_CLK__HZ EQU 50000000
 BCLK__BUS_CLK__KHZ EQU 50000
 BCLK__BUS_CLK__MHZ EQU 50
+CYDEV_CHIP_DIE_GEN4 EQU 2
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 6
-CYDEV_CHIP_DIE_PSOC4A EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 5
+CYDEV_CHIP_DIE_PANTHER EQU 12
+CYDEV_CHIP_DIE_PSOC4A EQU 5
+CYDEV_CHIP_DIE_PSOC5LP EQU 11
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
@@ -2934,15 +2945,23 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 3
-CYDEV_CHIP_MEMBER_4D EQU 2
-CYDEV_CHIP_MEMBER_4F EQU 4
-CYDEV_CHIP_MEMBER_5A EQU 6
-CYDEV_CHIP_MEMBER_5B EQU 5
+CYDEV_CHIP_MEMBER_4A EQU 5
+CYDEV_CHIP_MEMBER_4C EQU 9
+CYDEV_CHIP_MEMBER_4D EQU 3
+CYDEV_CHIP_MEMBER_4E EQU 4
+CYDEV_CHIP_MEMBER_4F EQU 6
+CYDEV_CHIP_MEMBER_4G EQU 2
+CYDEV_CHIP_MEMBER_4L EQU 8
+CYDEV_CHIP_MEMBER_4M EQU 7
+CYDEV_CHIP_MEMBER_5A EQU 11
+CYDEV_CHIP_MEMBER_5B EQU 10
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
 CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_GEN4_ES EQU 17
+CYDEV_CHIP_REV_GEN4_ES2 EQU 33
+CYDEV_CHIP_REV_GEN4_PRODUCTION EQU 17
 CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
 CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
 CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
@@ -2960,8 +2979,16 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
+CYDEV_CHIP_REVISION_4G_ES EQU 17
+CYDEV_CHIP_REVISION_4G_ES2 EQU 33
+CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
@@ -2984,9 +3011,6 @@ CYDEV_CONFIGURATION_MODE_DMA EQU 2
 CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
 CYDEV_DEBUG_ENABLE_MASK EQU 0x20
 CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
-CYDEV_DEBUGGING_DPS_Disable EQU 3
-CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
-CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
 CYDEV_DEBUGGING_DPS_SWD EQU 2
 CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
 CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
@@ -2999,7 +3023,9 @@ CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
 CYDEV_INTR_RISING EQU 0x0000007E
 CYDEV_PROJ_TYPE EQU 2
 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
+CYDEV_PROJ_TYPE_LAUNCHER EQU 5
 CYDEV_PROJ_TYPE_LOADABLE EQU 2
+CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
 CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
 CYDEV_PROJ_TYPE_STANDARD EQU 0
 CYDEV_PROTECTION_ENABLE EQU 0

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c

@@ -1,14 +1,14 @@
 /*******************************************************************************
 * FILENAME: cymetadata.c
 * 
-* PSoC Creator  3.1
+* PSoC Creator  3.2
 *
 * DESCRIPTION:
 * This file defines all extra memory spaces that need to be included.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used))
 const uint8 cy_meta_loadable[] = {
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x30u, 0x04u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x40u, 0x04u,
     0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,

software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h

@@ -1,91 +1,91 @@
 /*******************************************************************************
- * File Name: project.h
- * PSoC Creator  3.1
- *
- *  Description:
- *  This file is automatically generated by PSoC Creator and should not 
- *  be edited by hand.
- *
- *
- ********************************************************************************
- * Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
- * You may use this file only in accordance with the license, terms, conditions, 
- * disclaimers, and limitations in the end user license agreement accompanying 
- * the software package with which this file was provided.
- ********************************************************************************/
+* FILENAME: project.h
+* 
+* PSoC Creator  3.2
+*
+* DESCRIPTION:
+* It contains references to all generated header files and should not be modified.
+* This file is automatically generated by PSoC Creator.
+*
+********************************************************************************
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+********************************************************************************/
 
-#include <cyfitter_cfg.h>
-#include <cydevice.h>
-#include <cydevice_trm.h>
-#include <cyfitter.h>
-#include <cydisabledsheets.h>
-#include <SCSI_In_DBx_aliases.h>
-#include <SCSI_Out_DBx_aliases.h>
-#include <SD_Data_Clk.h>
-#include <SD_CD_aliases.h>
-#include <SD_CD.h>
-#include <SD_DAT2_aliases.h>
-#include <SD_DAT2.h>
-#include <SD_DAT1_aliases.h>
-#include <SD_DAT1.h>
-#include <SCSI_CTL_PHASE.h>
-#include <SCSI_In_aliases.h>
-#include <SCSI_Out_aliases.h>
-#include <CFG_EEPROM.h>
-#include <SD_CS_aliases.h>
-#include <SD_CS.h>
-#include <SD_SCK_aliases.h>
-#include <SD_SCK.h>
-#include <SD_MOSI_aliases.h>
-#include <SD_MOSI.h>
-#include <SCSI_CLK.h>
-#include <SCSI_Noise_aliases.h>
-#include <SCSI_RST_ISR.h>
-#include <LED1_aliases.h>
-#include <LED1.h>
-#include <SDCard.h>
-#include <SDCard_PVT.h>
-#include <SD_MISO_aliases.h>
-#include <SD_MISO.h>
-#include <USBFS.h>
-#include <USBFS_audio.h>
-#include <USBFS_cdc.h>
-#include <USBFS_hid.h>
-#include <USBFS_midi.h>
-#include <USBFS_pvt.h>
-#include <Bootloadable_1.h>
-#include <SCSI_Out_Bits.h>
-#include <SCSI_Out_Ctl.h>
-#include <Debug_Timer.h>
-#include <timer_clock.h>
-#include <Debug_Timer_Interrupt.h>
-#include <SCSI_TX_DMA_dma.h>
-#include <SCSI_TX_DMA_COMPLETE.h>
-#include <SD_RX_DMA_dma.h>
-#include <SD_TX_DMA_dma.h>
-#include <SD_RX_DMA_COMPLETE.h>
-#include <SD_TX_DMA_COMPLETE.h>
-#include <SCSI_RX_DMA_dma.h>
-#include <SCSI_RX_DMA_COMPLETE.h>
-#include <SCSI_Parity_Error.h>
-#include <SCSI_Filtered.h>
-#include <SCSI_SEL_ISR.h>
-#include <SCSI_Glitch_Ctl.h>
-#include <USBFS_Dm_aliases.h>
-#include <USBFS_Dm.h>
-#include <USBFS_Dp_aliases.h>
-#include <USBFS_Dp.h>
-#include <core_cm3_psoc5.h>
-#include <core_cm3.h>
-#include <CyDmac.h>
-#include <CyFlash.h>
-#include <CyLib.h>
-#include <cypins.h>
-#include <cyPm.h>
-#include <CySpc.h>
-#include <cytypes.h>
-#include <core_cmFunc.h>
-#include <core_cmInstr.h>
+#include "cyfitter_cfg.h"
+#include "cydevice.h"
+#include "cydevice_trm.h"
+#include "cyfitter.h"
+#include "cydisabledsheets.h"
+#include "SCSI_In_DBx_aliases.h"
+#include "SCSI_Out_DBx_aliases.h"
+#include "SD_Data_Clk.h"
+#include "SD_CD_aliases.h"
+#include "SD_CD.h"
+#include "SD_DAT2_aliases.h"
+#include "SD_DAT2.h"
+#include "SD_DAT1_aliases.h"
+#include "SD_DAT1.h"
+#include "SCSI_CTL_PHASE.h"
+#include "SCSI_In_aliases.h"
+#include "SCSI_Out_aliases.h"
+#include "CFG_EEPROM.h"
+#include "SD_CS_aliases.h"
+#include "SD_CS.h"
+#include "SD_SCK_aliases.h"
+#include "SD_SCK.h"
+#include "SD_MOSI_aliases.h"
+#include "SD_MOSI.h"
+#include "SCSI_CLK.h"
+#include "SCSI_Noise_aliases.h"
+#include "SCSI_RST_ISR.h"
+#include "LED1_aliases.h"
+#include "LED1.h"
+#include "SDCard.h"
+#include "SDCard_PVT.h"
+#include "SD_MISO_aliases.h"
+#include "SD_MISO.h"
+#include "USBFS.h"
+#include "USBFS_audio.h"
+#include "USBFS_cdc.h"
+#include "USBFS_hid.h"
+#include "USBFS_midi.h"
+#include "USBFS_pvt.h"
+#include "Bootloadable_1.h"
+#include "SCSI_Out_Bits.h"
+#include "SCSI_Out_Ctl.h"
+#include "Debug_Timer.h"
+#include "timer_clock.h"
+#include "Debug_Timer_Interrupt.h"
+#include "SCSI_TX_DMA_dma.h"
+#include "SCSI_TX_DMA_COMPLETE.h"
+#include "SD_RX_DMA_dma.h"
+#include "SD_TX_DMA_dma.h"
+#include "SD_RX_DMA_COMPLETE.h"
+#include "SD_TX_DMA_COMPLETE.h"
+#include "SCSI_RX_DMA_dma.h"
+#include "SCSI_RX_DMA_COMPLETE.h"
+#include "SCSI_Parity_Error.h"
+#include "SCSI_Filtered.h"
+#include "SCSI_SEL_ISR.h"
+#include "SCSI_Glitch_Ctl.h"
+#include "USBFS_Dm_aliases.h"
+#include "USBFS_Dm.h"
+#include "USBFS_Dp_aliases.h"
+#include "USBFS_Dp.h"
+#include "core_cm3_psoc5.h"
+#include "core_cm3.h"
+#include "CyDmac.h"
+#include "CyFlash.h"
+#include "CyLib.h"
+#include "cypins.h"
+#include "cyPm.h"
+#include "CySpc.h"
+#include "cytypes.h"
+#include "core_cmFunc.h"
+#include "core_cmInstr.h"
 
 /*[]*/
 

software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx

@@ -98,21 +98,10 @@
   <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />
-  </block>
-  <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Filtered_STATUS_REG" address="0x40006467" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_MASK_REG" address="0x40006487" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006497" bitWidth="8" desc="">
+    <register name="SCSI_Filtered_STATUS_REG" address="0x4000646A" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_MASK_REG" address="0x4000648A" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649A" bitWidth="8" desc="">
       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
         <value name="ENABLED" value="1" desc="Enable counter" />
         <value name="DISABLED" value="0" desc="Disable counter" />
@@ -139,12 +128,21 @@
       </field>
     </register>
   </block>
+  <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" />
+  </block>
+  <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />
-  </block>
   <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -152,7 +150,7 @@
   <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />
+    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />
   </block>
   <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -160,6 +158,8 @@
   <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
     <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -257,6 +257,13 @@
     <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
   </block>
   <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647F" bitWidth="8" desc="" />
+  </block>
+  <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />
+  </block>
+  <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
     <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -264,16 +271,10 @@
     <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   </block>
-  <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000657B" bitWidth="8" desc="" />
-  </block>
-  <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />
 </blockRegMap>

software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd

@@ -453,31 +453,10 @@
         </register>
       </registers>
     </peripheral>
-    <peripheral>
-      <name>SCSI_Glitch_Ctl</name>
-      <description>No description available</description>
-      <baseAddress>0x4000647A</baseAddress>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x0</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <registers>
-        <register>
-          <name>SCSI_Glitch_Ctl_CONTROL_REG</name>
-          <description>No description available</description>
-          <addressOffset>0x0</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-        </register>
-      </registers>
-    </peripheral>
     <peripheral>
       <name>SCSI_Filtered</name>
       <description>No description available</description>
-      <baseAddress>0x40006467</baseAddress>
+      <baseAddress>0x4000646A</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -630,9 +609,9 @@
       </registers>
     </peripheral>
     <peripheral>
-      <name>SCSI_Out_Ctl</name>
+      <name>SCSI_Glitch_Ctl</name>
       <description>No description available</description>
-      <baseAddress>0x4000647C</baseAddress>
+      <baseAddress>0x40006474</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -640,7 +619,7 @@
       </addressBlock>
       <registers>
         <register>
-          <name>SCSI_Out_Ctl_CONTROL_REG</name>
+          <name>SCSI_Glitch_Ctl_CONTROL_REG</name>
           <description>No description available</description>
           <addressOffset>0x0</addressOffset>
           <size>8</size>
@@ -653,7 +632,7 @@
     <peripheral>
       <name>SCSI_CTL_PHASE</name>
       <description>No description available</description>
-      <baseAddress>0x40006471</baseAddress>
+      <baseAddress>0x40006472</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -1155,10 +1134,31 @@
         </register>
       </registers>
     </peripheral>
+    <peripheral>
+      <name>SCSI_Out_Ctl</name>
+      <description>No description available</description>
+      <baseAddress>0x4000647F</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SCSI_Out_Ctl_CONTROL_REG</name>
+          <description>No description available</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+        </register>
+      </registers>
+    </peripheral>
     <peripheral>
       <name>SCSI_Out_Bits</name>
       <description>No description available</description>
-      <baseAddress>0x4000657B</baseAddress>
+      <baseAddress>0x4000647B</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c

@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: CFG_EEPROM.c
-* Version 2.10
+* Version 3.0
 *
-* Description:
-*  Provides the source code to the API for the EEPROM component.
+*  Description:
+*   Provides the source code to the API for the EEPROM component.
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -15,129 +15,129 @@
 #include "CFG_EEPROM.h"
 
 
-#if (CY_PSOC3 || CY_PSOC5LP)
-
-    /*******************************************************************************
-    * Function Name: CFG_EEPROM_Enable
-    ********************************************************************************
-    *
-    * Summary:
-    *  Enable the EEPROM.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    void CFG_EEPROM_Enable(void) 
-    {
-        CyEEPROM_Start();
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CFG_EEPROM_Start
-    ********************************************************************************
-    *
-    * Summary:
-    *  Starts EEPROM.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    void CFG_EEPROM_Start(void) 
-    {
-        /* Enable the EEPROM */
-        CFG_EEPROM_Enable();
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CFG_EEPROM_Stop
-    ********************************************************************************
-    *
-    * Summary:
-    *  Stops and powers down EEPROM.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    void CFG_EEPROM_Stop (void) 
-    {
-        /* Disable EEPROM */
-        CyEEPROM_Stop();
-    }
-
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */
-
-
 /*******************************************************************************
-* Function Name: CFG_EEPROM_EraseSector
+* Function Name: CFG_EEPROM_Enable
 ********************************************************************************
 *
 * Summary:
-*  Erases a sector of memory. This function blocks until the operation is
-*  complete.
+*  Enable the EEPROM block. Also reads the temperature and stores it for
+*  future writes.
 *
 * Parameters:
-*  sectorNumber:  Sector number to erase.
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CFG_EEPROM_Enable(void) 
+{
+    /* Read temperature value */
+    (void)CySetTemp();
+
+    /* Start EEPROM block */
+    CyEEPROM_Start();
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Start
+********************************************************************************
+*
+* Summary:
+*  Starts EEPROM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CFG_EEPROM_Start(void) 
+{
+    CFG_EEPROM_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Stop
+********************************************************************************
+*
+* Summary:
+*  Stops and powers down EEPROM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CFG_EEPROM_Stop (void) 
+{
+    /* Stop and power down EEPROM block */
+    CyEEPROM_Stop();
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_WriteByte
+********************************************************************************
+*
+* Summary:
+*  Writes a byte of data to the EEPROM. This function blocks until
+*  the function is complete. For a reliable write procedure to occur you should
+*  call CFG_EEPROM_UpdateTemperature() function if the temperature of the
+*  silicon has been changed for more than 10C since the component was started.
+*
+* Parameters:
+*  dataByte:  The byte of data to write to the EEPROM
+*  address:   The address of data to be written. The maximum address is dependent
+*             on the EEPROM size.
 *
 * Return:
 *  CYRET_SUCCESS, if the operation was successful.
-*  CYRET_BAD_PARAM, if the parameter sectorNumber out of range.
-*  CYRET_LOCKED, if the spc is being used.
+*  CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
 *  CYRET_UNKNOWN, if there was an SPC error.
 *
 *******************************************************************************/
-cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) 
+cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) 
 {
     cystatus status;
-
-    /* Start the SPC */
+    uint16 rowNumber;
+    uint16 byteNumber;
+    
     CySpcStart();
 
-    if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS)
+    if (address < CY_EEPROM_SIZE)
     {
-        /* See if we can get the SPC. */
-        if(CySpcLock() == CYRET_SUCCESS)
+        rowNumber = address/(uint16)CY_EEPROM_SIZEOF_ROW;
+        byteNumber = address - (rowNumber * ((uint16)CY_EEPROM_SIZEOF_ROW));
+        if(CYRET_SUCCESS == CySpcLock())
         {
-            #if(CY_PSOC5A)
-
+            status = CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, byteNumber, &dataByte, \
+                                                                    CFG_EEPROM_SPC_BYTE_WRITE_SIZE);
+            if (CYRET_STARTED == status)
+            {
                 /* Plan for failure */
                 status = CYRET_UNKNOWN;
 
-                /* Command to load a row of data */
-                if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, 0, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)
+                while(CY_SPC_BUSY)
                 {
-                    while(CY_SPC_BUSY)
-                    {
-                        /* Wait until SPC becomes idle */
-                    }
-
-                    /* SPC is idle now */
-                    if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                    {
-                        status = CYRET_SUCCESS;
-                    }
+                    /* Wait until SPC becomes idle */
                 }
 
-                /* Command to erase a sector */
-                if(status == CYRET_SUCCESS)
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
                 {
-
-            #endif /* (CY_PSOC5A) */
-
-                    if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
+                    status = CYRET_SUCCESS;
+                }
+                /* Command to erase and program the row. */
+                if(CYRET_SUCCESS == status)
+                {
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+                    dieTemperature[1u]) == CYRET_STARTED)
                     {
                         /* Plan for failure */
                         status = CYRET_UNKNOWN;
@@ -157,19 +157,153 @@ cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber)
                     {
                         status = CYRET_UNKNOWN;
                     }
-
-            #if(CY_PSOC5A)
-
                 }
                 else
                 {
                     status = CYRET_UNKNOWN;
                 }
+            }
+            else
+            {
+                if (CYRET_BAD_PARAM != status)
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+            CySpcUnlock();
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
 
-            #endif /* (CY_PSOC5A) */
 
-                /* Unlock the SPC so someone else can use it. */
-                CySpcUnlock();
+    return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_ReadByte
+********************************************************************************
+*
+* Summary:
+*  Reads and returns a byte of data from the on-chip EEPROM memory. Although
+*  the data is present in the CPU memory space, this function provides an
+*  intuitive user interface, addressing the EEPROM memory as a separate block with
+*  the first EERPOM byte address equal to 0x0000.
+*
+* Parameters:
+*  address:   The address of data to be read. The maximum address is limited by the
+*             size of the EEPROM array on a specific device.
+*
+* Return:
+*  Data located at an address.
+*
+*******************************************************************************/
+uint8 CFG_EEPROM_ReadByte(uint16 address) 
+{
+    uint8 retByte;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    /* Request access to EEPROM for reading.
+    This is needed to reserve PHUB for read operation from EEPROM */
+    CyEEPROM_ReadReserve();
+    
+    retByte = *((reg8 *) (CYDEV_EE_BASE + address));
+
+    /* Release EEPROM array */
+    CyEEPROM_ReadRelease();
+    
+    CyExitCriticalSection(interruptState);
+
+    return (retByte);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_UpdateTemperature
+********************************************************************************
+*
+* Summary:
+*  Updates and stores the temperature value. This function should be called
+*  before EEPROM writes if the temperature may have been changed by more than
+*  10 degrees Celsius.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  Status of operation, 0 if operation complete, non-zero value if error
+*  was detected.
+*
+*******************************************************************************/
+uint8 CFG_EEPROM_UpdateTemperature(void) 
+{
+    return ((uint8)CySetTemp());
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_EraseSector
+********************************************************************************
+*
+* Summary:
+*  Erase an EEPROM sector (64 rows). This function blocks until the erase
+*  operation is complete. Using this API helps to erase the EEPROM sector at
+*  a time. This is faster than using individual writes but affects a cycle
+*  recourse of the whole EEPROM row.
+*
+* Parameters:
+*  sectorNumber:  The sector number to erase.
+*
+* Return:
+*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) 
+{
+    cystatus status;
+    
+    CySpcStart();
+
+    if(sectorNumber < (uint8) CFG_EEPROM_SECTORS_NUMBER)
+    {
+        /* See if we can get SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
+            {
+                /* Plan for failure */
+                status = CYRET_UNKNOWN;
+
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                /* SPC is idle now */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+            }
+            else
+            {
+                status = CYRET_UNKNOWN;
+            }
+
+            /* Unlock SPC so that someone else can use it. */
+            CySpcUnlock();
         }
         else
         {
@@ -190,30 +324,33 @@ cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber)
 ********************************************************************************
 *
 * Summary:
-*  Writes a row, CYDEV_EEPROM_ROW_SIZE of data to the EEPROM. This is
-*  a blocking call. It will not return until the function succeeds or fails.
+*  Writes a row (16 bytes) of data to the EEPROM. This function blocks until
+*  the write operation is complete. Compared to functions that write one byte,
+*  this function allows writing a whole row (16 bytes) at a time. For
+*  a reliable write procedure to occur you should call the
+*  CFG_EEPROM_UpdateTemperature() function if the temperature of the
+*  silicon has changed for more than 10C since component was started.
 *
 * Parameters:
-*  rowData:  Address of the data to write to the EEPROM.
-*  rowNumber:  EEPROM row number to program.
+*  rowData:    The address of the data to write to the EEPROM.
+*  rowNumber:  The row number to write.
 *
 * Return:
 *  CYRET_SUCCESS, if the operation was successful.
-*  CYRET_BAD_PARAM, if the parameter rowNumber out of range.
-*  CYRET_LOCKED, if the spc is being used.
+*  CYRET_BAD_PARAM, if the parameter rowNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
 *  CYRET_UNKNOWN, if there was an SPC error.
 *
 *******************************************************************************/
 cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) 
 {
     cystatus status;
-
-    /* Start the SPC */
+    
     CySpcStart();
 
     if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
     {
-        /* See if we can get the SPC. */
+        /* See if we can get SPC. */
         if(CySpcLock() == CYRET_SUCCESS)
         {
             /* Plan for failure */
@@ -236,8 +373,8 @@ cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber)
                 /* Command to erase and program the row. */
                 if(status == CYRET_SUCCESS)
                 {
-                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],
-                    dieTemperature[1]) == CYRET_STARTED)
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+                    dieTemperature[1u]) == CYRET_STARTED)
                     {
                         /* Plan for failure */
                         status = CYRET_UNKNOWN;
@@ -264,7 +401,7 @@ cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber)
                 }
             }
 
-            /* Unlock the SPC so someone else can use it. */
+            /* Unlock SPC so that someone else can use it. */
             CySpcUnlock();
         }
         else
@@ -286,31 +423,44 @@ cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber)
 ********************************************************************************
 *
 * Summary:
-*  Starts the SPC write function. This function does not block, it returns
-*  once the command has begun the SPC write function. This function must be used
-*  in combination with CFG_EEPROM_QueryWrite(). Once this function has
-*  been called the SPC will be locked until CFG_EEPROM_QueryWrite()
-*  returns CYRET_SUCCESS.
+*  Starts a write of a row (16 bytes) of data to the EEPROM.
+*  This function does not block. The function returns once the SPC has begun
+*  writing the data. This function must be used in combination with
+*  CFG_EEPROM_Query(). CFG_EEPROM_Query() must be called
+*  until it returns a status other than CYRET_STARTED. That indicates that the
+*  write has completed. Until CFG_EEPROM_Query() detects that
+*  the write is complete, the SPC is marked as locked to prevent another
+*  SPC operation from being performed. For a reliable write procedure to occur
+*  you should call CFG_EEPROM_UpdateTemperature() API if the temperature
+*  of the silicon has changed for more than 10C since component was started.
 *
 * Parameters:
-*  rowData:  Address of buffer containing a row of data to write to the EEPROM.
-*  rowNumber:  EEPROM row number to program.
+*  rowData:    The address of the data to write to the EEPROM.
+*  rowNumber:  The row number to write.
 *
 * Return:
-*  CYRET_STARTED, if the spc command to write was successfuly started.
-*  CYRET_BAD_PARAM, if the parameter rowNumber out of range.
-*  CYRET_LOCKED, if the spc is being used.
+*  CYRET_STARTED, if the SPC command to write was successfully started.
+*  CYRET_BAD_PARAM, if the parameter rowNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
 *  CYRET_UNKNOWN, if there was an SPC error.
 *
+* Side effects:
+*  After calling this API, the device should not be powered down, reset or switched
+*  to low power modes until EEPROM operation is complete. 
+*  Ignoring this recommendation may lead to data corruption or silicon
+*  unexpected behavior.
+*
 *******************************************************************************/
 cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
 
 {
     cystatus status;
+    
+    CySpcStart();
 
     if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
     {
-        /* See if we can get the SPC. */
+        /* See if we can get SPC. */
         if(CySpcLock() == CYRET_SUCCESS)
         {
             /* Plan for failure */
@@ -333,8 +483,8 @@ cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
                 /* Command to erase and program the row. */
                 if(status == CYRET_SUCCESS)
                 {
-                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],
-                    dieTemperature[1]) == CYRET_STARTED)
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+                    dieTemperature[1u]) == CYRET_STARTED)
                     {
                         status = CYRET_STARTED;
                     }
@@ -364,25 +514,94 @@ cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
 
 
 /*******************************************************************************
-* Function Name: CFG_EEPROM_QueryWrite
+* Function Name: CFG_EEPROM_StartErase
 ********************************************************************************
 *
 * Summary:
-*  Checks the state of write to EEPROM. This function must be called until
-*  the return value is not CYRET_STARTED.
+*  Starts the EEPROM sector erase. This function does not block.
+*  The function returns once the SPC has begun writing the data. This function
+*  must be used in combination with CFG_EEPROM_Query().
+*  CFG_EEPROM_Query() must be called until it returns a status
+*  other than CYRET_STARTED. That indicates the erase has been completed.
+*  Until CFG_EEPROM_Query() detects that the erase is
+*  complete, the SPC is marked as locked to prevent another SPC operation
+*  from being performed.
+*
+* Parameters:
+*  sectorNumber:  The sector number to erase.
+*
+* Return:
+*  CYRET_STARTED, if the SPC command to erase was successfully started.
+*  CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+* Side effects:
+*  After calling this API, the device should not be powered down, reset or switched
+*  to low power modes until EEPROM operation is complete.
+*  Ignoring this recommendation may lead to data corruption or silicon
+*  unexpected behavior.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) 
+{
+    cystatus status;
+    
+    CySpcStart();
+
+    if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS)
+    {
+        /* See if we can get SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Plan for failure */
+            status = CYRET_UNKNOWN;
+
+            /* Command to load a row of data */
+            if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
+            {
+                status = CYRET_SUCCESS;
+            }
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Query
+********************************************************************************
+*
+* Summary:
+*  Checks the status of an earlier call to CFG_EEPROM_StartWrite() or
+*  CFG_EEPROM_StartErase().
+*  This function must be called until it returns a value other than
+*  CYRET_STARTED. Once that occurs, the write or erase has been completed and
+*  the SPC is unlocked.
 *
 * Parameters:
 *  None
 *
 * Return:
-*  CYRET_STARTED, if the spc command is still processing.
-*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_STARTED, if the SPC command is still processing.
+*  CYRET_SUCCESS, if the operation was completed successfully.
 *  CYRET_UNKNOWN, if there was an SPC error.
 *
 *******************************************************************************/
-cystatus CFG_EEPROM_QueryWrite(void) 
+cystatus CFG_EEPROM_Query(void) 
 {
     cystatus status;
+    
+    CySpcStart();
 
     /* Check if SPC is idle */
     if(CY_SPC_IDLE)
@@ -397,7 +616,7 @@ cystatus CFG_EEPROM_QueryWrite(void)
             status = CYRET_UNKNOWN;
         }
 
-        /* Unlock the SPC so someone else can use it. */
+        /* Unlock SPC so that someone else can use it. */
         CySpcUnlock();
     }
     else
@@ -410,42 +629,42 @@ cystatus CFG_EEPROM_QueryWrite(void)
 
 
 /*******************************************************************************
-* Function Name: CFG_EEPROM_ByteWrite
+* Function Name: CFG_EEPROM_ByteWritePos
 ********************************************************************************
 *
 * Summary:
 *  Writes a byte of data to the EEPROM. This is a blocking call. It will not
-*  return until the function succeeds or fails.
+*  return until the write operation succeeds or fails.
 *
 * Parameters:
-*  dataByte:  Byte of data to write to the EEPROM.
-*  rowNumber:  EEPROM row number to program.
-*  byteNumber:  Byte number within the row to program.
+*  dataByte:   The byte of data to write to the EEPROM.
+*  rowNumber:  The EEPROM row number to program.
+*  byteNumber: The byte number within the row to program.
 *
 * Return:
 *  CYRET_SUCCESS, if the operation was successful.
-*  CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber out of range.
-*  CYRET_LOCKED, if the spc is being used.
+*  CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
 *  CYRET_UNKNOWN, if there was an SPC error.
 *
 *******************************************************************************/
-cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
+cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
 
 {
     cystatus status;
 
-    /* Start the SPC */
+    /* Start SPC */
     CySpcStart();
 
     if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW))
     {
-        /* See if we can get the SPC. */
+        /* See if we can get SPC. */
         if(CySpcLock() == CYRET_SUCCESS)
         {
             /* Plan for failure */
             status = CYRET_UNKNOWN;
 
-            /* Command to load a byte of data */
+            /* Command to load byte of data */
             if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\
                                                                 CFG_EEPROM_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED)
             {
@@ -463,8 +682,8 @@ cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber)
                 /* Command to erase and program the row. */
                 if(status == CYRET_SUCCESS)
                 {
-                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],
-                    dieTemperature[1]) == CYRET_STARTED)
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+                    dieTemperature[1u]) == CYRET_STARTED)
                     {
                         /* Plan for failure */
                         status = CYRET_UNKNOWN;
@@ -491,7 +710,7 @@ cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber)
                 }
             }
 
-            /* Unlock the SPC so someone else can use it. */
+            /* Unlock SPC so that someone else can use it. */
             CySpcUnlock();
         }
         else

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h

@@ -1,14 +1,14 @@
 /*******************************************************************************
 * File Name: CFG_EEPROM.h
-* Version 2.10
+* Version 3.0
 *
-* Description:
-*  Provides the function definitions for the EEPROM APIs.
+*  Description:
+*   Provides the function definitions for the EEPROM APIs.
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
 *******************************************************************************/
 
@@ -19,7 +19,7 @@
 #include "CyFlash.h"
 
 #if !defined(CY_PSOC5LP)
-    #error Component EEPROM_v2_10 requires cy_boot v3.0 or later
+    #error Component EEPROM_v3_0 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5LP) */
 
 
@@ -27,33 +27,52 @@
 *        Function Prototypes
 ***************************************/
 
-#if (CY_PSOC3 || CY_PSOC5LP) 
-    void CFG_EEPROM_Enable(void) ;
-    void CFG_EEPROM_Start(void); 
-    void CFG_EEPROM_Stop(void) ;
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */
-
+void CFG_EEPROM_Enable(void) ;
+void CFG_EEPROM_Start(void) ;
+void CFG_EEPROM_Stop (void) ;
+cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) \
+                                            ;
+uint8 CFG_EEPROM_ReadByte(uint16 address) ;
+uint8 CFG_EEPROM_UpdateTemperature(void) ;
 cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ;
 cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ;
 cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
-            ;
-cystatus CFG_EEPROM_QueryWrite(void) ;
-cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
-            ;
+                                                ;
+cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) ;
+cystatus CFG_EEPROM_Query(void) ;
+cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
+                                                ;
 
 
 /****************************************
 *           API Constants
 ****************************************/
 
-#define CFG_EEPROM_EEPROM_SIZE    		CYDEV_EE_SIZE
+#define CFG_EEPROM_EEPROM_SIZE            CYDEV_EE_SIZE
 #define CFG_EEPROM_SPC_BYTE_WRITE_SIZE    (0x01u)
 
+#define CFG_EEPROM_SECTORS_NUMBER         (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
 
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from EEPROM 2.10
-*******************************************************************************/
-#define SPC_BYTE_WRITE_SIZE             (CFG_EEPROM_SPC_BYTE_WRITE_SIZE)
+#define CFG_EEPROM_AHB_REQ_SHIFT          (0x00u)
+#define CFG_EEPROM_AHB_REQ                ((uint8)(0x01u << CFG_EEPROM_AHB_REQ_SHIFT))
+#define CFG_EEPROM_AHB_ACK_SHIFT          (0x01u)
+#define CFG_EEPROM_AHB_ACK_MASK           ((uint8)(0x01u << CFG_EEPROM_AHB_ACK_SHIFT))
+
+
+/***************************************
+* Registers
+***************************************/
+#define CFG_EEPROM_SPC_EE_SCR_REG                 (*(reg8 *) CYREG_SPC_EE_SCR)
+#define CFG_EEPROM_SPC_EE_SCR_PTR                 ( (reg8 *) CYREG_SPC_EE_SCR)
+
+
+
+/***************************************
+* The following code is DEPRECATED and
+* should not be used in new projects.
+***************************************/
+#define CFG_EEPROM_ByteWrite                  CFG_EEPROM_ByteWritePos
+#define CFG_EEPROM_QueryWrite                 CFG_EEPROM_Query
 
 #endif /* CY_EEPROM_CFG_EEPROM_H */
 

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void Debug_Timer_Interrupt_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void Debug_Timer_Interrupt_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(Debug_Timer_Interrupt_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling Debug_Timer_Interrupt_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use Debug_Timer_Interrupt_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress Debug_Timer_Interrupt_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling Debug_Timer_Interrupt_Start
-*   or Debug_Timer_Interrupt_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void Debug_Timer_Interrupt_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 Debug_Timer_Interrupt_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 Debug_Timer_Interrupt_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 Debug_Timer_Interrupt_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void Debug_Timer_Interrupt_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void Debug_Timer_Interrupt_SetPending(void)
 {
@@ -336,7 +379,12 @@ void Debug_Timer_Interrupt_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_CTL_PHASE.c  
-* Version 1.70
+* Version 1.80
 *
 * Description:
 *  This file contains API to enable firmware control of a Control Register.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -16,8 +16,10 @@
 
 #include "SCSI_CTL_PHASE.h"
 
-#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+/* Check for removal by optimization */
+#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED)
 
+    
 /*******************************************************************************
 * Function Name: SCSI_CTL_PHASE_Write
 ********************************************************************************

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_CTL_PHASE.h  
-* Version 1.70
+* Version 1.80
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -19,6 +19,18 @@
 
 #include "cytypes.h"
 
+    
+/***************************************
+*     Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+    uint8 controlState;
+
+} SCSI_CTL_PHASE_BACKUP_STRUCT;
+
 
 /***************************************
 *         Function Prototypes 
@@ -27,6 +39,11 @@
 void    SCSI_CTL_PHASE_Write(uint8 control) ;
 uint8   SCSI_CTL_PHASE_Read(void) ;
 
+void SCSI_CTL_PHASE_SaveConfig(void) ;
+void SCSI_CTL_PHASE_RestoreConfig(void) ;
+void SCSI_CTL_PHASE_Sleep(void) ; 
+void SCSI_CTL_PHASE_Wakeup(void) ;
+
 
 /***************************************
 *            Registers        

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE_PM.c

@@ -0,0 +1,109 @@
+/*******************************************************************************
+* File Name: SCSI_CTL_PHASE_PM.c
+* Version 1.80
+*
+* Description:
+*  This file contains the setup, control, and status commands to support 
+*  the component operation in the low power mode. 
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_CTL_PHASE.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED)
+
+static SCSI_CTL_PHASE_BACKUP_STRUCT  SCSI_CTL_PHASE_backup = {0u};
+
+    
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_SaveConfig
+********************************************************************************
+*
+* Summary:
+*  Saves the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_SaveConfig(void) 
+{
+    SCSI_CTL_PHASE_backup.controlState = SCSI_CTL_PHASE_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_RestoreConfig
+********************************************************************************
+*
+* Summary:
+*  Restores the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_RestoreConfig(void) 
+{
+     SCSI_CTL_PHASE_Control = SCSI_CTL_PHASE_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Sleep
+********************************************************************************
+*
+* Summary:
+*  Prepares the component for entering the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_Sleep(void) 
+{
+    SCSI_CTL_PHASE_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Wakeup
+********************************************************************************
+*
+* Summary:
+*  Restores the component after waking up from the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_Wakeup(void)  
+{
+    SCSI_CTL_PHASE_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Filtered.c  
-* Version 1.80
+* Version 1.90
 *
 * Description:
 *  This file contains API to enable firmware to read the value of a Status 
@@ -9,7 +9,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -103,7 +103,7 @@ void SCSI_Filtered_InterruptDisable(void)
 void SCSI_Filtered_WriteMask(uint8 mask) 
 {
     #if(SCSI_Filtered_INPUTS < 8u)
-    	mask &= (uint8)((((uint8)1u) << SCSI_Filtered_INPUTS) - 1u);
+    	mask &= ((uint8)(1u << SCSI_Filtered_INPUTS) - 1u);
 	#endif /* End SCSI_Filtered_INPUTS < 8u */
     SCSI_Filtered_Status_Mask = mask;
 }

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Filtered.h  
-* Version 1.80
+* Version 1.90
 *
 * Description:
 *  This file containts Status Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -20,6 +20,18 @@
 #include "cytypes.h"
 #include "CyLib.h"
 
+    
+/***************************************
+*     Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+    uint8 statusState;
+
+} SCSI_Filtered_BACKUP_STRUCT;
+
 
 /***************************************
 *        Function Prototypes

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Glitch_Ctl.c  
-* Version 1.70
+* Version 1.80
 *
 * Description:
 *  This file contains API to enable firmware control of a Control Register.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -16,8 +16,10 @@
 
 #include "SCSI_Glitch_Ctl.h"
 
-#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+/* Check for removal by optimization */
+#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED)
 
+    
 /*******************************************************************************
 * Function Name: SCSI_Glitch_Ctl_Write
 ********************************************************************************

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Glitch_Ctl.h  
-* Version 1.70
+* Version 1.80
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -19,6 +19,18 @@
 
 #include "cytypes.h"
 
+    
+/***************************************
+*     Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+    uint8 controlState;
+
+} SCSI_Glitch_Ctl_BACKUP_STRUCT;
+
 
 /***************************************
 *         Function Prototypes 
@@ -27,6 +39,11 @@
 void    SCSI_Glitch_Ctl_Write(uint8 control) ;
 uint8   SCSI_Glitch_Ctl_Read(void) ;
 
+void SCSI_Glitch_Ctl_SaveConfig(void) ;
+void SCSI_Glitch_Ctl_RestoreConfig(void) ;
+void SCSI_Glitch_Ctl_Sleep(void) ; 
+void SCSI_Glitch_Ctl_Wakeup(void) ;
+
 
 /***************************************
 *            Registers        

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl_PM.c

@@ -0,0 +1,109 @@
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl_PM.c
+* Version 1.80
+*
+* Description:
+*  This file contains the setup, control, and status commands to support 
+*  the component operation in the low power mode. 
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Glitch_Ctl.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED)
+
+static SCSI_Glitch_Ctl_BACKUP_STRUCT  SCSI_Glitch_Ctl_backup = {0u};
+
+    
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_SaveConfig
+********************************************************************************
+*
+* Summary:
+*  Saves the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_SaveConfig(void) 
+{
+    SCSI_Glitch_Ctl_backup.controlState = SCSI_Glitch_Ctl_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_RestoreConfig
+********************************************************************************
+*
+* Summary:
+*  Restores the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_RestoreConfig(void) 
+{
+     SCSI_Glitch_Ctl_Control = SCSI_Glitch_Ctl_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Sleep
+********************************************************************************
+*
+* Summary:
+*  Prepares the component for entering the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Sleep(void) 
+{
+    SCSI_Glitch_Ctl_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Wakeup
+********************************************************************************
+*
+* Summary:
+*  Restores the component after waking up from the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Wakeup(void)  
+{
+    SCSI_Glitch_Ctl_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Out_Bits.c  
-* Version 1.70
+* Version 1.80
 *
 * Description:
 *  This file contains API to enable firmware control of a Control Register.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -16,8 +16,10 @@
 
 #include "SCSI_Out_Bits.h"
 
-#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED)
 
+    
 /*******************************************************************************
 * Function Name: SCSI_Out_Bits_Write
 ********************************************************************************

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Out_Bits.h  
-* Version 1.70
+* Version 1.80
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -19,6 +19,18 @@
 
 #include "cytypes.h"
 
+    
+/***************************************
+*     Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+    uint8 controlState;
+
+} SCSI_Out_Bits_BACKUP_STRUCT;
+
 
 /***************************************
 *         Function Prototypes 
@@ -27,6 +39,11 @@
 void    SCSI_Out_Bits_Write(uint8 control) ;
 uint8   SCSI_Out_Bits_Read(void) ;
 
+void SCSI_Out_Bits_SaveConfig(void) ;
+void SCSI_Out_Bits_RestoreConfig(void) ;
+void SCSI_Out_Bits_Sleep(void) ; 
+void SCSI_Out_Bits_Wakeup(void) ;
+
 
 /***************************************
 *            Registers        

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits_PM.c

@@ -0,0 +1,109 @@
+/*******************************************************************************
+* File Name: SCSI_Out_Bits_PM.c
+* Version 1.80
+*
+* Description:
+*  This file contains the setup, control, and status commands to support 
+*  the component operation in the low power mode. 
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Out_Bits.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED)
+
+static SCSI_Out_Bits_BACKUP_STRUCT  SCSI_Out_Bits_backup = {0u};
+
+    
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_SaveConfig
+********************************************************************************
+*
+* Summary:
+*  Saves the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Out_Bits_SaveConfig(void) 
+{
+    SCSI_Out_Bits_backup.controlState = SCSI_Out_Bits_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_RestoreConfig
+********************************************************************************
+*
+* Summary:
+*  Restores the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*
+*******************************************************************************/
+void SCSI_Out_Bits_RestoreConfig(void) 
+{
+     SCSI_Out_Bits_Control = SCSI_Out_Bits_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_Sleep
+********************************************************************************
+*
+* Summary:
+*  Prepares the component for entering the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Out_Bits_Sleep(void) 
+{
+    SCSI_Out_Bits_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_Wakeup
+********************************************************************************
+*
+* Summary:
+*  Restores the component after waking up from the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Out_Bits_Wakeup(void)  
+{
+    SCSI_Out_Bits_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Out_Ctl.c  
-* Version 1.70
+* Version 1.80
 *
 * Description:
 *  This file contains API to enable firmware control of a Control Register.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -16,8 +16,10 @@
 
 #include "SCSI_Out_Ctl.h"
 
-#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED)
 
+    
 /*******************************************************************************
 * Function Name: SCSI_Out_Ctl_Write
 ********************************************************************************

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Out_Ctl.h  
-* Version 1.70
+* Version 1.80
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -19,6 +19,18 @@
 
 #include "cytypes.h"
 
+    
+/***************************************
+*     Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+    uint8 controlState;
+
+} SCSI_Out_Ctl_BACKUP_STRUCT;
+
 
 /***************************************
 *         Function Prototypes 
@@ -27,6 +39,11 @@
 void    SCSI_Out_Ctl_Write(uint8 control) ;
 uint8   SCSI_Out_Ctl_Read(void) ;
 
+void SCSI_Out_Ctl_SaveConfig(void) ;
+void SCSI_Out_Ctl_RestoreConfig(void) ;
+void SCSI_Out_Ctl_Sleep(void) ; 
+void SCSI_Out_Ctl_Wakeup(void) ;
+
 
 /***************************************
 *            Registers        

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl_PM.c

@@ -0,0 +1,109 @@
+/*******************************************************************************
+* File Name: SCSI_Out_Ctl_PM.c
+* Version 1.80
+*
+* Description:
+*  This file contains the setup, control, and status commands to support 
+*  the component operation in the low power mode. 
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Out_Ctl.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED)
+
+static SCSI_Out_Ctl_BACKUP_STRUCT  SCSI_Out_Ctl_backup = {0u};
+
+    
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_SaveConfig
+********************************************************************************
+*
+* Summary:
+*  Saves the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_SaveConfig(void) 
+{
+    SCSI_Out_Ctl_backup.controlState = SCSI_Out_Ctl_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_RestoreConfig
+********************************************************************************
+*
+* Summary:
+*  Restores the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_RestoreConfig(void) 
+{
+     SCSI_Out_Ctl_Control = SCSI_Out_Ctl_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_Sleep
+********************************************************************************
+*
+* Summary:
+*  Prepares the component for entering the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_Sleep(void) 
+{
+    SCSI_Out_Ctl_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_Wakeup
+********************************************************************************
+*
+* Summary:
+*  Restores the component after waking up from the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_Wakeup(void)  
+{
+    SCSI_Out_Ctl_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Parity_Error.c  
-* Version 1.80
+* Version 1.90
 *
 * Description:
 *  This file contains API to enable firmware to read the value of a Status 
@@ -9,7 +9,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -103,7 +103,7 @@ void SCSI_Parity_Error_InterruptDisable(void)
 void SCSI_Parity_Error_WriteMask(uint8 mask) 
 {
     #if(SCSI_Parity_Error_INPUTS < 8u)
-    	mask &= (uint8)((((uint8)1u) << SCSI_Parity_Error_INPUTS) - 1u);
+    	mask &= ((uint8)(1u << SCSI_Parity_Error_INPUTS) - 1u);
 	#endif /* End SCSI_Parity_Error_INPUTS < 8u */
     SCSI_Parity_Error_Status_Mask = mask;
 }

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Parity_Error.h  
-* Version 1.80
+* Version 1.90
 *
 * Description:
 *  This file containts Status Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -20,6 +20,18 @@
 #include "cytypes.h"
 #include "CyLib.h"
 
+    
+/***************************************
+*     Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+    uint8 statusState;
+
+} SCSI_Parity_Error_BACKUP_STRUCT;
+
 
 /***************************************
 *        Function Prototypes

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void SCSI_RST_ISR_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void SCSI_RST_ISR_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(SCSI_RST_ISR_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling SCSI_RST_ISR_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use SCSI_RST_ISR_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress SCSI_RST_ISR_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling SCSI_RST_ISR_Start
-*   or SCSI_RST_ISR_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void SCSI_RST_ISR_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 SCSI_RST_ISR_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 SCSI_RST_ISR_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 SCSI_RST_ISR_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void SCSI_RST_ISR_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void SCSI_RST_ISR_SetPending(void)
 {
@@ -336,7 +379,12 @@ void SCSI_RST_ISR_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void SCSI_RX_DMA_COMPLETE_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(SCSI_RX_DMA_COMPLETE_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use SCSI_RX_DMA_COMPLETE_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
-*   or SCSI_RX_DMA_COMPLETE_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 SCSI_RX_DMA_COMPLETE_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void SCSI_RX_DMA_COMPLETE_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void SCSI_RX_DMA_COMPLETE_SetPending(void)
 {
@@ -336,7 +379,12 @@ void SCSI_RX_DMA_COMPLETE_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void SCSI_SEL_ISR_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void SCSI_SEL_ISR_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(SCSI_SEL_ISR_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling SCSI_SEL_ISR_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use SCSI_SEL_ISR_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress SCSI_SEL_ISR_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling SCSI_SEL_ISR_Start
-*   or SCSI_SEL_ISR_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void SCSI_SEL_ISR_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 SCSI_SEL_ISR_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 SCSI_SEL_ISR_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 SCSI_SEL_ISR_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void SCSI_SEL_ISR_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void SCSI_SEL_ISR_SetPending(void)
 {
@@ -336,7 +379,12 @@ void SCSI_SEL_ISR_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void SCSI_TX_DMA_COMPLETE_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(SCSI_TX_DMA_COMPLETE_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use SCSI_TX_DMA_COMPLETE_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
-*   or SCSI_TX_DMA_COMPLETE_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 SCSI_TX_DMA_COMPLETE_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void SCSI_TX_DMA_COMPLETE_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void SCSI_TX_DMA_COMPLETE_SetPending(void)
 {
@@ -336,7 +379,12 @@ void SCSI_TX_DMA_COMPLETE_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SDCard.c
-* Version 2.40
+* Version 2.50
 *
 * Description:
 *  This file provides all API functionality of the SPI Master component.
@@ -9,7 +9,7 @@
 *  None.
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -18,14 +18,14 @@
 #include "SDCard_PVT.h"
 
 #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
-    volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] = {0u};
+    volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE];
     volatile uint8 SDCard_txBufferFull;
     volatile uint8 SDCard_txBufferRead;
     volatile uint8 SDCard_txBufferWrite;
 #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
 
 #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
-    volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] = {0u};
+    volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE];
     volatile uint8 SDCard_rxBufferFull;
     volatile uint8 SDCard_rxBufferRead;
     volatile uint8 SDCard_rxBufferWrite;
@@ -523,7 +523,7 @@ void SDCard_WriteTxData(uint8 txData)
         if((SDCard_txBufferRead == SDCard_txBufferWrite) &&
            (0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL)))
         {
-            /* Add directly to the TX FIFO */
+            /* Put data element into the TX FIFO */
             CY_SET_REG8(SDCard_TXDATA_PTR, txData);
         }
         else
@@ -553,13 +553,12 @@ void SDCard_WriteTxData(uint8 txData)
         SDCard_EnableTxInt();
 
     #else
-
+        /* Wait until TX FIFO has a place */
         while(0u == (SDCard_TX_STATUS_REG & SDCard_STS_TX_FIFO_NOT_FULL))
         {
-            ; /* Wait for room in FIFO */
         }
 
-        /* Put byte in TX FIFO */
+        /* Put data element into the TX FIFO */
         CY_SET_REG8(SDCard_TXDATA_PTR, txData);
 
     #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SDCard.h
-* Version 2.40
+* Version 2.50
 *
 * Description:
 *  Contains the function prototypes, constants and register definition
@@ -10,7 +10,7 @@
 *  None
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -26,7 +26,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component SPI_Master_v2_40 requires cy_boot v3.0 or later
+    #error Component SPI_Master_v2_50 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 
@@ -71,11 +71,6 @@ typedef struct
 {
     uint8 enableState;
     uint8 cntrPeriod;
-    #if(CY_UDB_V0)
-        uint8 saveSrTxIntMask;
-        uint8 saveSrRxIntMask;
-    #endif /* (CY_UDB_V0) */
-
 } SDCard_BACKUP_STRUCT;
 
 
@@ -123,9 +118,9 @@ CY_ISR_PROTO(SDCard_TX_ISR);
 CY_ISR_PROTO(SDCard_RX_ISR);
 
 
-/**********************************
+/***************************************
 *   Variable with external linkage
-**********************************/
+***************************************/
 
 extern uint8 SDCard_initVar;
 
@@ -181,7 +176,6 @@ extern uint8 SDCard_initVar;
 /***************************************
 *             Registers
 ***************************************/
-
 #if(CY_PSOC3 || CY_PSOC5)
     #define SDCard_TXDATA_REG (* (reg8 *) \
                                                 SDCard_BSPIM_sR8_Dp_u0__F0_REG)
@@ -199,7 +193,7 @@ extern uint8 SDCard_initVar;
                                           SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
         #define SDCard_RXDATA_REG (* (reg16 *) \
                                           SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
-        #define SDCard_RXDATA_PTR         (  (reg16 *) \
+        #define SDCard_RXDATA_PTR (  (reg16 *) \
                                           SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
     #else
         #define SDCard_TXDATA_REG (* (reg8 *) \
@@ -236,9 +230,9 @@ extern uint8 SDCard_initVar;
 #define SDCard_RX_STATUS_PTR          (  (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG)
 
 #define SDCard_CONTROL_REG            (* (reg8 *) \
-                                      SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)
+                                      SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG)
 #define SDCard_CONTROL_PTR            (  (reg8 *) \
-                                      SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)
+                                      SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG)
 
 #define SDCard_TX_STATUS_MASK_REG     (* (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)
 #define SDCard_TX_STATUS_MASK_PTR     (  (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)
@@ -323,14 +317,10 @@ extern uint8 SDCard_initVar;
 
 
 /***************************************
-*       Obsolete definitions
+* The following code is DEPRECATED and 
+* should not be used in new projects.
 ***************************************/
 
-/* Following definitions are for version compatibility.
-*  They are obsolete in SPIM v2_30.
-*  Please do not use it in new projects
-*/
-
 #define SDCard_WriteByte   SDCard_WriteTxData
 #define SDCard_ReadByte    SDCard_ReadRxData
 void  SDCard_SetInterruptMode(uint8 intSrc)       ;
@@ -338,7 +328,6 @@ uint8 SDCard_ReadStatus(void)                     ;
 void  SDCard_EnableInt(void)                      ;
 void  SDCard_DisableInt(void)                     ;
 
-/* Obsolete register names. Not to be used in new designs */
 #define SDCard_TXDATA                 (SDCard_TXDATA_REG)
 #define SDCard_RXDATA                 (SDCard_RXDATA_REG)
 #define SDCard_AUX_CONTROLDP0         (SDCard_AUX_CONTROL_DP0_REG)
@@ -362,11 +351,6 @@ void  SDCard_DisableInt(void)                     ;
                                                 SDCard_INT_ON_RX_OVER      | \
                                                 SDCard_INT_ON_BYTE_COMP)
                                                 
-/* Following definitions are for version Compatibility.
-*  They are obsolete in SPIM v2_40.
-*  Please do not use it in new projects
-*/
-
 #define SDCard_DataWidth                  (SDCard_DATA_WIDTH)
 #define SDCard_InternalClockUsed          (SDCard_INTERNAL_CLOCK)
 #define SDCard_InternalTxInterruptEnabled (SDCard_INTERNAL_TX_INT_ENABLED)

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SDCard_INT.c
-* Version 2.40
+* Version 2.50
 *
 * Description:
 *  This file provides all Interrupt Service Routine (ISR) for the SPI Master
@@ -10,7 +10,7 @@
 *  None.
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -82,9 +82,9 @@ CY_ISR(SDCard_TX_ISR)
                     SDCard_txBufferFull = 0u;
                 }
 
-                /* Move data from the Buffer to the FIFO */
-                CY_SET_REG8(SDCard_TXDATA_PTR,
-                    SDCard_txBuffer[SDCard_txBufferRead]);
+                /* Put data element into the TX FIFO */
+                CY_SET_REG8(SDCard_TXDATA_PTR, 
+                                             SDCard_txBuffer[SDCard_txBufferRead]);
             }
             else
             {

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SDCard_PM.c
-* Version 2.40
+* Version 2.50
 *
 * Description:
 *  This file contains the setup, control and status commands to support
@@ -9,7 +9,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -21,10 +21,6 @@ static SDCard_BACKUP_STRUCT SDCard_backup =
 {
     SDCard_DISABLED,
     SDCard_BITCTR_INIT,
-    #if(CY_UDB_V0)
-        SDCard_TX_INIT_INTERRUPTS_MASK,
-        SDCard_RX_INIT_INTERRUPTS_MASK
-    #endif /* CY_UDB_V0 */
 };
 
 
@@ -33,7 +29,7 @@ static SDCard_BACKUP_STRUCT SDCard_backup =
 ********************************************************************************
 *
 * Summary:
-*  Saves SPIM configuration.
+*  Empty function. Included for consistency with other components.
 *
 * Parameters:
 *  None.
@@ -41,21 +37,10 @@ static SDCard_BACKUP_STRUCT SDCard_backup =
 * Return:
 *  None.
 *
-* Global Variables:
-*  SDCard_backup - modified when non-retention registers are saved.
-*
-* Reentrant:
-*  No.
-*
 *******************************************************************************/
 void SDCard_SaveConfig(void) 
 {
-    /* Store Status Mask registers */
-    #if(CY_UDB_V0)
-       SDCard_backup.cntrPeriod      = SDCard_COUNTER_PERIOD_REG;
-       SDCard_backup.saveSrTxIntMask = SDCard_TX_STATUS_MASK_REG;
-       SDCard_backup.saveSrRxIntMask = SDCard_RX_STATUS_MASK_REG;
-    #endif /* (CY_UDB_V0) */
+
 }
 
 
@@ -64,7 +49,7 @@ void SDCard_SaveConfig(void)
 ********************************************************************************
 *
 * Summary:
-*  Restores SPIM configuration.
+*  Empty function. Included for consistency with other components.
 *
 * Parameters:
 *  None.
@@ -72,23 +57,10 @@ void SDCard_SaveConfig(void)
 * Return:
 *  None.
 *
-* Global Variables:
-*  SDCard_backup - used when non-retention registers are restored.
-*
-* Side Effects:
-*  If this API is called without first calling SaveConfig then in the following
-*  registers will be default values from Customizer:
-*  SDCard_STATUS_MASK_REG and SDCard_COUNTER_PERIOD_REG.
-*
 *******************************************************************************/
 void SDCard_RestoreConfig(void) 
 {
-    /* Restore the data, saved by SaveConfig() function */
-    #if(CY_UDB_V0)
-        SDCard_COUNTER_PERIOD_REG = SDCard_backup.cntrPeriod;
-        SDCard_TX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrTxIntMask);
-        SDCard_RX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrRxIntMask);
-    #endif /* (CY_UDB_V0) */
+
 }
 
 
@@ -118,7 +90,6 @@ void SDCard_Sleep(void)
     SDCard_backup.enableState = ((uint8) SDCard_IS_ENABLED);
 
     SDCard_Stop();
-    SDCard_SaveConfig();
 }
 
 
@@ -152,8 +123,6 @@ void SDCard_Sleep(void)
 *******************************************************************************/
 void SDCard_Wakeup(void) 
 {
-    SDCard_RestoreConfig();
-
     #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
         SDCard_rxBufferFull  = 0u;
         SDCard_rxBufferRead  = 0u;

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: .h
-* Version 2.40
+* Version 2.50
 *
 * Description:
 *  This private header file contains internal definitions for the SPIM
@@ -9,7 +9,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2012-2015, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void SD_RX_DMA_COMPLETE_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(SD_RX_DMA_COMPLETE_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use SD_RX_DMA_COMPLETE_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress SD_RX_DMA_COMPLETE_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
-*   or SD_RX_DMA_COMPLETE_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 SD_RX_DMA_COMPLETE_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 SD_RX_DMA_COMPLETE_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 SD_RX_DMA_COMPLETE_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void SD_RX_DMA_COMPLETE_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void SD_RX_DMA_COMPLETE_SetPending(void)
 {
@@ -336,7 +379,12 @@ void SD_RX_DMA_COMPLETE_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.c

@@ -9,7 +9,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -45,7 +45,10 @@ CY_ISR_PROTO(IntDefaultHandler);
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
 *
 * Parameters:  
 *   None
@@ -75,7 +78,20 @@ void SD_TX_DMA_COMPLETE_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Set up the interrupt and enable it.
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
 *
 * Parameters:  
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -108,6 +124,7 @@ void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address)
 *   Disables and removes the interrupt.
 *
 * Parameters:  
+*   None
 *
 * Return:
 *   None
@@ -156,6 +173,17 @@ CY_ISR(SD_TX_DMA_COMPLETE_Interrupt)
 *   Change the ISR vector for the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
 *   will override any effect this method would have had. To set the vector 
 *   before the component has been started use SD_TX_DMA_COMPLETE_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
 *
 * Parameters:
 *   address: Address of the ISR to set in the interrupt vector table.
@@ -203,14 +231,20 @@ cyisraddress SD_TX_DMA_COMPLETE_GetVector(void)
 ********************************************************************************
 *
 * Summary:
-*   Sets the Priority of the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
-*   or SD_TX_DMA_COMPLETE_StartEx will override any effect this method 
-*   would have had. This method should only be called after 
-*   SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. To set 
-*   the initial priority for the component use the cydwr file in the tool.
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
 *
 * Parameters:
-*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
 *
 * Return:
 *   None
@@ -233,7 +267,9 @@ void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority)
 *   None
 *
 * Return:
-*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
 *
 *******************************************************************************/
 uint8 SD_TX_DMA_COMPLETE_GetPriority(void)
@@ -252,7 +288,9 @@ uint8 SD_TX_DMA_COMPLETE_GetPriority(void)
 ********************************************************************************
 *
 * Summary:
-*   Enables the interrupt.
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
 *
 * Parameters:
 *   None
@@ -294,7 +332,7 @@ uint8 SD_TX_DMA_COMPLETE_GetState(void)
 ********************************************************************************
 *
 * Summary:
-*   Disables the Interrupt.
+*   Disables the Interrupt in the interrupt controller.
 *
 * Parameters:
 *   None
@@ -324,6 +362,11 @@ void SD_TX_DMA_COMPLETE_Disable(void)
 * Return:
 *   None
 *
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
 *******************************************************************************/
 void SD_TX_DMA_COMPLETE_SetPending(void)
 {
@@ -336,7 +379,12 @@ void SD_TX_DMA_COMPLETE_SetPending(void)
 ********************************************************************************
 *
 * Summary:
-*   Clears a pending interrupt.
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
 *
 * Parameters:
 *   None

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.h

@@ -7,7 +7,7 @@
 *
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h

@@ -1,14 +1,14 @@
 /*******************************************************************************
 * FILENAME: cydevice.h
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator  3.1
+* PSoC Creator  3.2
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h

@@ -1,14 +1,14 @@
 /*******************************************************************************
 * FILENAME: cydevice_trm.h
 * 
-* PSoC Creator  3.1
+* PSoC Creator  3.2
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc

@@ -1,14 +1,14 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu.inc
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator  3.1
+* PSoC Creator  3.2
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc

@@ -1,14 +1,14 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu_trm.inc
 * 
-* PSoC Creator  3.1
+* PSoC Creator  3.2
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc

@@ -1,13 +1,13 @@
 ;
 ; FILENAME: cydeviceiar.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator  3.1
+; PSoC Creator  3.2
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions, 
 ; disclaimers, and limitations in the end user license agreement accompanying 
 ; the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc

@@ -1,13 +1,13 @@
 ;
 ; FILENAME: cydeviceiar_trm.inc
 ; 
-; PSoC Creator  3.1
+; PSoC Creator  3.2
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions, 
 ; disclaimers, and limitations in the end user license agreement accompanying 
 ; the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc

@@ -1,13 +1,13 @@
 ;
 ; FILENAME: cydevicerv.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator  3.1
+; PSoC Creator  3.2
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions, 
 ; disclaimers, and limitations in the end user license agreement accompanying 
 ; the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc

@@ -1,13 +1,13 @@
 ;
 ; FILENAME: cydevicerv_trm.inc
 ; 
-; PSoC Creator  3.1
+; PSoC Creator  3.2
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions, 
 ; disclaimers, and limitations in the end user license agreement accompanying 
 ; the software package with which this file was provided.

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h

@@ -1,7 +1,7 @@
 #ifndef INCLUDED_CYFITTER_H
 #define INCLUDED_CYFITTER_H
-#include <cydevice.h>
-#include <cydevice_trm.h>
+#include "cydevice.h"
+#include "cydevice_trm.h"
 
 /* LED1 */
 #define LED1__0__MASK 0x02u
@@ -414,34 +414,34 @@
 #define EXTLED__SLW CYREG_PRT0_SLW
 
 /* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB12_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB12_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB12_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB12_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB12_ST
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_RxStsReg__4__POS 4
 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@@ -449,9 +449,13 @@
 #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
 #define SDCard_BSPIM_RxStsReg__6__POS 6
 #define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
@@ -469,12 +473,12 @@
 #define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
 #define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
 #define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
 #define SDCard_BSPIM_TxStsReg__0__POS 0
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
 #define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
 #define SDCard_BSPIM_TxStsReg__2__POS 2
 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
@@ -482,9 +486,9 @@
 #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_TxStsReg__4__POS 4
 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB11_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB11_ST
 
 /* SD_SCK */
 #define SD_SCK__0__MASK 0x04u
@@ -1842,15 +1846,15 @@
 #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
 #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
 #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@@ -1863,37 +1867,37 @@
 #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
 #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK
 
 /* SCSI_Out_Ctl */
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB04_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB04_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
 #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB04_MSK
 
 /* SCSI_Out_DBx */
 #define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
@@ -2827,8 +2831,8 @@
 #define SCSI_Filtered_sts_sts_reg__0__POS 0
 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
 #define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
 #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
 #define SCSI_Filtered_sts_sts_reg__2__POS 2
 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@@ -2836,81 +2840,79 @@
 #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
 #define SCSI_Filtered_sts_sts_reg__4__POS 4
 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
 
 /* SCSI_CTL_PHASE */
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK
 
 /* SCSI_Glitch_Ctl */
 #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
 #define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK
 
 /* SCSI_Parity_Error */
 #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
 #define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST
 #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST
 
 /* Miscellaneous */
 #define BCLK__BUS_CLK__HZ 50000000U
 #define BCLK__BUS_CLK__KHZ 50000U
 #define BCLK__BUS_CLK__MHZ 50U
-#define CY_VERSION "PSoC Creator  3.1"
+#define CY_PROJECT_NAME "SCSI2SD"
+#define CY_VERSION "PSoC Creator  3.2"
+#define CYDEV_CHIP_DIE_GEN4 2u
 #define CYDEV_CHIP_DIE_LEOPARD 1u
-#define CYDEV_CHIP_DIE_PANTHER 6u
-#define CYDEV_CHIP_DIE_PSOC4A 3u
-#define CYDEV_CHIP_DIE_PSOC5LP 5u
+#define CYDEV_CHIP_DIE_PANTHER 12u
+#define CYDEV_CHIP_DIE_PSOC4A 5u
+#define CYDEV_CHIP_DIE_PSOC5LP 11u
 #define CYDEV_CHIP_DIE_UNKNOWN 0u
 #define CYDEV_CHIP_FAMILY_PSOC3 1u
 #define CYDEV_CHIP_FAMILY_PSOC4 2u
@@ -2919,15 +2921,23 @@
 #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
 #define CYDEV_CHIP_JTAG_ID 0x2E133069u
 #define CYDEV_CHIP_MEMBER_3A 1u
-#define CYDEV_CHIP_MEMBER_4A 3u
-#define CYDEV_CHIP_MEMBER_4D 2u
-#define CYDEV_CHIP_MEMBER_4F 4u
-#define CYDEV_CHIP_MEMBER_5A 6u
-#define CYDEV_CHIP_MEMBER_5B 5u
+#define CYDEV_CHIP_MEMBER_4A 5u
+#define CYDEV_CHIP_MEMBER_4C 9u
+#define CYDEV_CHIP_MEMBER_4D 3u
+#define CYDEV_CHIP_MEMBER_4E 4u
+#define CYDEV_CHIP_MEMBER_4F 6u
+#define CYDEV_CHIP_MEMBER_4G 2u
+#define CYDEV_CHIP_MEMBER_4L 8u
+#define CYDEV_CHIP_MEMBER_4M 7u
+#define CYDEV_CHIP_MEMBER_5A 11u
+#define CYDEV_CHIP_MEMBER_5B 10u
 #define CYDEV_CHIP_MEMBER_UNKNOWN 0u
 #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
 #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
 #define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
+#define CYDEV_CHIP_REV_GEN4_ES 17u
+#define CYDEV_CHIP_REV_GEN4_ES2 33u
+#define CYDEV_CHIP_REV_GEN4_PRODUCTION 17u
 #define CYDEV_CHIP_REV_LEOPARD_ES1 0u
 #define CYDEV_CHIP_REV_LEOPARD_ES2 1u
 #define CYDEV_CHIP_REV_LEOPARD_ES3 3u
@@ -2945,8 +2955,16 @@
 #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
 #define CYDEV_CHIP_REVISION_4A_ES0 17u
 #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
+#define CYDEV_CHIP_REVISION_4G_ES 17u
+#define CYDEV_CHIP_REVISION_4G_ES2 33u
+#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_5A_ES0 0u
 #define CYDEV_CHIP_REVISION_5A_ES1 1u
 #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
@@ -2969,9 +2987,6 @@
 #define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
 #define CYDEV_DEBUG_ENABLE_MASK 0x20u
 #define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
-#define CYDEV_DEBUGGING_DPS_Disable 3
-#define CYDEV_DEBUGGING_DPS_JTAG_4 1
-#define CYDEV_DEBUGGING_DPS_JTAG_5 0
 #define CYDEV_DEBUGGING_DPS_SWD 2
 #define CYDEV_DEBUGGING_DPS_SWD_SWV 6
 #define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
@@ -2984,7 +2999,9 @@
 #define CYDEV_INTR_RISING 0x0000007Eu
 #define CYDEV_PROJ_TYPE 2
 #define CYDEV_PROJ_TYPE_BOOTLOADER 1
+#define CYDEV_PROJ_TYPE_LAUNCHER 5
 #define CYDEV_PROJ_TYPE_LOADABLE 2
+#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
 #define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
 #define CYDEV_PROJ_TYPE_STANDARD 0
 #define CYDEV_PROTECTION_ENABLE 0

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h

@@ -1,12 +1,14 @@
 /*******************************************************************************
 * FILENAME: cyfitter_cfg.h
-* PSoC Creator  3.1
+* 
+* PSoC Creator  3.2
 *
-* Description:
+* DESCRIPTION:
+* This file provides basic startup and mux configration settings
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -15,7 +17,7 @@
 #ifndef CYFITTER_CFG_H
 #define CYFITTER_CFG_H
 
-#include <cytypes.h>
+#include "cytypes.h"
 
 extern void cyfitter_cfg(void);
 

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc

@@ -414,34 +414,34 @@
 .set EXTLED__SLW, CYREG_PRT0_SLW
 
 /* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB12_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB12_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB12_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB12_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB12_ST
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_RxStsReg__4__POS, 4
 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@@ -449,9 +449,13 @@
 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
 .set SDCard_BSPIM_RxStsReg__6__POS, 6
 .set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
@@ -469,12 +473,12 @@
 .set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
 .set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
 .set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
 .set SDCard_BSPIM_TxStsReg__0__POS, 0
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
 .set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
 .set SDCard_BSPIM_TxStsReg__2__POS, 2
 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
@@ -482,9 +486,9 @@
 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_TxStsReg__4__POS, 4
 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB11_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB11_ST
 
 /* SD_SCK */
 .set SD_SCK__0__MASK, 0x04
@@ -1842,15 +1846,15 @@
 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@@ -1863,37 +1867,37 @@
 .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
 .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK
 
 /* SCSI_Out_Ctl */
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB04_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB04_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
 .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB04_MSK
 
 /* SCSI_Out_DBx */
 .set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
@@ -2827,8 +2831,8 @@
 .set SCSI_Filtered_sts_sts_reg__0__POS, 0
 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
 .set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
 .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
 .set SCSI_Filtered_sts_sts_reg__2__POS, 2
 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@@ -2836,80 +2840,77 @@
 .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
 .set SCSI_Filtered_sts_sts_reg__4__POS, 4
 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK
-.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
 
 /* SCSI_CTL_PHASE */
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK
 
 /* SCSI_Glitch_Ctl */
 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK
 
 /* SCSI_Parity_Error */
 .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB10_11_ST
 .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB10_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB10_ST
 
 /* Miscellaneous */
 .set BCLK__BUS_CLK__HZ, 50000000
 .set BCLK__BUS_CLK__KHZ, 50000
 .set BCLK__BUS_CLK__MHZ, 50
+.set CYDEV_CHIP_DIE_GEN4, 2
 .set CYDEV_CHIP_DIE_LEOPARD, 1
-.set CYDEV_CHIP_DIE_PANTHER, 6
-.set CYDEV_CHIP_DIE_PSOC4A, 3
-.set CYDEV_CHIP_DIE_PSOC5LP, 5
+.set CYDEV_CHIP_DIE_PANTHER, 12
+.set CYDEV_CHIP_DIE_PSOC4A, 5
+.set CYDEV_CHIP_DIE_PSOC5LP, 11
 .set CYDEV_CHIP_DIE_UNKNOWN, 0
 .set CYDEV_CHIP_FAMILY_PSOC3, 1
 .set CYDEV_CHIP_FAMILY_PSOC4, 2
@@ -2918,15 +2919,23 @@
 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
 .set CYDEV_CHIP_JTAG_ID, 0x2E133069
 .set CYDEV_CHIP_MEMBER_3A, 1
-.set CYDEV_CHIP_MEMBER_4A, 3
-.set CYDEV_CHIP_MEMBER_4D, 2
-.set CYDEV_CHIP_MEMBER_4F, 4
-.set CYDEV_CHIP_MEMBER_5A, 6
-.set CYDEV_CHIP_MEMBER_5B, 5
+.set CYDEV_CHIP_MEMBER_4A, 5
+.set CYDEV_CHIP_MEMBER_4C, 9
+.set CYDEV_CHIP_MEMBER_4D, 3
+.set CYDEV_CHIP_MEMBER_4E, 4
+.set CYDEV_CHIP_MEMBER_4F, 6
+.set CYDEV_CHIP_MEMBER_4G, 2
+.set CYDEV_CHIP_MEMBER_4L, 8
+.set CYDEV_CHIP_MEMBER_4M, 7
+.set CYDEV_CHIP_MEMBER_5A, 11
+.set CYDEV_CHIP_MEMBER_5B, 10
 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0
 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
 .set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
+.set CYDEV_CHIP_REV_GEN4_ES, 17
+.set CYDEV_CHIP_REV_GEN4_ES2, 33
+.set CYDEV_CHIP_REV_GEN4_PRODUCTION, 17
 .set CYDEV_CHIP_REV_LEOPARD_ES1, 0
 .set CYDEV_CHIP_REV_LEOPARD_ES2, 1
 .set CYDEV_CHIP_REV_LEOPARD_ES3, 3
@@ -2944,8 +2953,16 @@
 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
 .set CYDEV_CHIP_REVISION_4A_ES0, 17
 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0
+.set CYDEV_CHIP_REVISION_4G_ES, 17
+.set CYDEV_CHIP_REVISION_4G_ES2, 33
+.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_5A_ES0, 0
 .set CYDEV_CHIP_REVISION_5A_ES1, 1
 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
@@ -2968,9 +2985,6 @@
 .set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
 .set CYDEV_DEBUG_ENABLE_MASK, 0x20
 .set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
-.set CYDEV_DEBUGGING_DPS_Disable, 3
-.set CYDEV_DEBUGGING_DPS_JTAG_4, 1
-.set CYDEV_DEBUGGING_DPS_JTAG_5, 0
 .set CYDEV_DEBUGGING_DPS_SWD, 2
 .set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
 .set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
@@ -2983,7 +2997,9 @@
 .set CYDEV_INTR_RISING, 0x0000007E
 .set CYDEV_PROJ_TYPE, 2
 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1
+.set CYDEV_PROJ_TYPE_LAUNCHER, 5
 .set CYDEV_PROJ_TYPE_LOADABLE, 2
+.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4
 .set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
 .set CYDEV_PROJ_TYPE_STANDARD, 0
 .set CYDEV_PROTECTION_ENABLE, 0

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc

@@ -414,34 +414,34 @@ EXTLED__SHIFT EQU 0
 EXTLED__SLW EQU CYREG_PRT0_SLW
 
 /* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB12_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB12_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB12_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB12_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB12_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_RxStsReg__4__POS EQU 4
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -449,9 +449,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@@ -469,12 +473,12 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
 SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
 SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
 SDCard_BSPIM_TxStsReg__2__POS EQU 2
 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@@ -482,9 +486,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_TxStsReg__4__POS EQU 4
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
 
 /* SD_SCK */
 SD_SCK__0__MASK EQU 0x04
@@ -1842,15 +1846,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@@ -1863,37 +1867,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
 SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK
 
 /* SCSI_Out_Ctl */
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB04_MSK
 
 /* SCSI_Out_DBx */
 SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
@@ -2827,8 +2831,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
 SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
 SCSI_Filtered_sts_sts_reg__2__POS EQU 2
 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2836,80 +2840,77 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
 SCSI_Filtered_sts_sts_reg__4__POS EQU 4
 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
 
 /* SCSI_CTL_PHASE */
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
 
 /* SCSI_Glitch_Ctl */
 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
 SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK
 
 /* SCSI_Parity_Error */
 SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST
 SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST
 
 /* Miscellaneous */
 BCLK__BUS_CLK__HZ EQU 50000000
 BCLK__BUS_CLK__KHZ EQU 50000
 BCLK__BUS_CLK__MHZ EQU 50
+CYDEV_CHIP_DIE_GEN4 EQU 2
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 6
-CYDEV_CHIP_DIE_PSOC4A EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 5
+CYDEV_CHIP_DIE_PANTHER EQU 12
+CYDEV_CHIP_DIE_PSOC4A EQU 5
+CYDEV_CHIP_DIE_PSOC5LP EQU 11
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
@@ -2918,15 +2919,23 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 3
-CYDEV_CHIP_MEMBER_4D EQU 2
-CYDEV_CHIP_MEMBER_4F EQU 4
-CYDEV_CHIP_MEMBER_5A EQU 6
-CYDEV_CHIP_MEMBER_5B EQU 5
+CYDEV_CHIP_MEMBER_4A EQU 5
+CYDEV_CHIP_MEMBER_4C EQU 9
+CYDEV_CHIP_MEMBER_4D EQU 3
+CYDEV_CHIP_MEMBER_4E EQU 4
+CYDEV_CHIP_MEMBER_4F EQU 6
+CYDEV_CHIP_MEMBER_4G EQU 2
+CYDEV_CHIP_MEMBER_4L EQU 8
+CYDEV_CHIP_MEMBER_4M EQU 7
+CYDEV_CHIP_MEMBER_5A EQU 11
+CYDEV_CHIP_MEMBER_5B EQU 10
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
 CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_GEN4_ES EQU 17
+CYDEV_CHIP_REV_GEN4_ES2 EQU 33
+CYDEV_CHIP_REV_GEN4_PRODUCTION EQU 17
 CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
 CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
 CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
@@ -2944,8 +2953,16 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
+CYDEV_CHIP_REVISION_4G_ES EQU 17
+CYDEV_CHIP_REVISION_4G_ES2 EQU 33
+CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
@@ -2968,9 +2985,6 @@ CYDEV_CONFIGURATION_MODE_DMA EQU 2
 CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
 CYDEV_DEBUG_ENABLE_MASK EQU 0x20
 CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
-CYDEV_DEBUGGING_DPS_Disable EQU 3
-CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
-CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
 CYDEV_DEBUGGING_DPS_SWD EQU 2
 CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
 CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
@@ -2983,7 +2997,9 @@ CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
 CYDEV_INTR_RISING EQU 0x0000007E
 CYDEV_PROJ_TYPE EQU 2
 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
+CYDEV_PROJ_TYPE_LAUNCHER EQU 5
 CYDEV_PROJ_TYPE_LOADABLE EQU 2
+CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
 CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
 CYDEV_PROJ_TYPE_STANDARD EQU 0
 CYDEV_PROTECTION_ENABLE EQU 0

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc

@@ -414,34 +414,34 @@ EXTLED__SHIFT EQU 0
 EXTLED__SLW EQU CYREG_PRT0_SLW
 
 ; SDCard_BSPIM
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB12_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB12_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB12_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB12_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB12_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_RxStsReg__4__POS EQU 4
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -449,9 +449,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@@ -469,12 +473,12 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
 SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
 SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
 SDCard_BSPIM_TxStsReg__2__POS EQU 2
 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@@ -482,9 +486,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_TxStsReg__4__POS EQU 4
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
 
 ; SD_SCK
 SD_SCK__0__MASK EQU 0x04
@@ -1842,15 +1846,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@@ -1863,37 +1867,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
 SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK
 
 ; SCSI_Out_Ctl
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB04_MSK
 
 ; SCSI_Out_DBx
 SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
@@ -2827,8 +2831,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
 SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
 SCSI_Filtered_sts_sts_reg__2__POS EQU 2
 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2836,80 +2840,77 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
 SCSI_Filtered_sts_sts_reg__4__POS EQU 4
 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
 
 ; SCSI_CTL_PHASE
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
 
 ; SCSI_Glitch_Ctl
 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
 SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK
 
 ; SCSI_Parity_Error
 SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST
 SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST
 
 ; Miscellaneous
 BCLK__BUS_CLK__HZ EQU 50000000
 BCLK__BUS_CLK__KHZ EQU 50000
 BCLK__BUS_CLK__MHZ EQU 50
+CYDEV_CHIP_DIE_GEN4 EQU 2
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 6
-CYDEV_CHIP_DIE_PSOC4A EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 5
+CYDEV_CHIP_DIE_PANTHER EQU 12
+CYDEV_CHIP_DIE_PSOC4A EQU 5
+CYDEV_CHIP_DIE_PSOC5LP EQU 11
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
@@ -2918,15 +2919,23 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 3
-CYDEV_CHIP_MEMBER_4D EQU 2
-CYDEV_CHIP_MEMBER_4F EQU 4
-CYDEV_CHIP_MEMBER_5A EQU 6
-CYDEV_CHIP_MEMBER_5B EQU 5
+CYDEV_CHIP_MEMBER_4A EQU 5
+CYDEV_CHIP_MEMBER_4C EQU 9
+CYDEV_CHIP_MEMBER_4D EQU 3
+CYDEV_CHIP_MEMBER_4E EQU 4
+CYDEV_CHIP_MEMBER_4F EQU 6
+CYDEV_CHIP_MEMBER_4G EQU 2
+CYDEV_CHIP_MEMBER_4L EQU 8
+CYDEV_CHIP_MEMBER_4M EQU 7
+CYDEV_CHIP_MEMBER_5A EQU 11
+CYDEV_CHIP_MEMBER_5B EQU 10
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
 CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_GEN4_ES EQU 17
+CYDEV_CHIP_REV_GEN4_ES2 EQU 33
+CYDEV_CHIP_REV_GEN4_PRODUCTION EQU 17
 CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
 CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
 CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
@@ -2944,8 +2953,16 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
+CYDEV_CHIP_REVISION_4G_ES EQU 17
+CYDEV_CHIP_REVISION_4G_ES2 EQU 33
+CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
@@ -2968,9 +2985,6 @@ CYDEV_CONFIGURATION_MODE_DMA EQU 2
 CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
 CYDEV_DEBUG_ENABLE_MASK EQU 0x20
 CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
-CYDEV_DEBUGGING_DPS_Disable EQU 3
-CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
-CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
 CYDEV_DEBUGGING_DPS_SWD EQU 2
 CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
 CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
@@ -2983,7 +2997,9 @@ CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
 CYDEV_INTR_RISING EQU 0x0000007E
 CYDEV_PROJ_TYPE EQU 2
 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
+CYDEV_PROJ_TYPE_LAUNCHER EQU 5
 CYDEV_PROJ_TYPE_LOADABLE EQU 2
+CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
 CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
 CYDEV_PROJ_TYPE_STANDARD EQU 0
 CYDEV_PROTECTION_ENABLE EQU 0

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c

@@ -1,14 +1,14 @@
 /*******************************************************************************
 * FILENAME: cymetadata.c
 * 
-* PSoC Creator  3.1
+* PSoC Creator  3.2
 *
 * DESCRIPTION:
 * This file defines all extra memory spaces that need to be included.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used))
 const uint8 cy_meta_loadable[] = {
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x30u, 0x04u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x40u, 0x04u,
     0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,

software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h

@@ -1,89 +1,89 @@
 /*******************************************************************************
- * File Name: project.h
- * PSoC Creator  3.1
- *
- *  Description:
- *  This file is automatically generated by PSoC Creator and should not 
- *  be edited by hand.
- *
- *
- ********************************************************************************
- * Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
- * You may use this file only in accordance with the license, terms, conditions, 
- * disclaimers, and limitations in the end user license agreement accompanying 
- * the software package with which this file was provided.
- ********************************************************************************/
+* FILENAME: project.h
+* 
+* PSoC Creator  3.2
+*
+* DESCRIPTION:
+* It contains references to all generated header files and should not be modified.
+* This file is automatically generated by PSoC Creator.
+*
+********************************************************************************
+* Copyright (c) 2007-2015 Cypress Semiconductor.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+********************************************************************************/
 
-#include <cyfitter_cfg.h>
-#include <cydevice.h>
-#include <cydevice_trm.h>
-#include <cyfitter.h>
-#include <cydisabledsheets.h>
-#include <SCSI_In_DBx_aliases.h>
-#include <SCSI_Out_DBx_aliases.h>
-#include <SD_Data_Clk.h>
-#include <SD_CD_aliases.h>
-#include <SD_CD.h>
-#include <SCSI_CTL_PHASE.h>
-#include <SCSI_In_aliases.h>
-#include <SCSI_Out_aliases.h>
-#include <CFG_EEPROM.h>
-#include <SD_CS_aliases.h>
-#include <SD_CS.h>
-#include <SD_SCK_aliases.h>
-#include <SD_SCK.h>
-#include <SD_MOSI_aliases.h>
-#include <SD_MOSI.h>
-#include <SCSI_CLK.h>
-#include <SCSI_Noise_aliases.h>
-#include <SCSI_RST_ISR.h>
-#include <LED1_aliases.h>
-#include <LED1.h>
-#include <SDCard.h>
-#include <SDCard_PVT.h>
-#include <SD_MISO_aliases.h>
-#include <SD_MISO.h>
-#include <USBFS.h>
-#include <USBFS_audio.h>
-#include <USBFS_cdc.h>
-#include <USBFS_hid.h>
-#include <USBFS_midi.h>
-#include <USBFS_pvt.h>
-#include <Bootloadable_1.h>
-#include <SCSI_Out_Bits.h>
-#include <SCSI_Out_Ctl.h>
-#include <Debug_Timer.h>
-#include <timer_clock.h>
-#include <Debug_Timer_Interrupt.h>
-#include <SCSI_TX_DMA_dma.h>
-#include <SCSI_TX_DMA_COMPLETE.h>
-#include <SD_RX_DMA_dma.h>
-#include <SD_TX_DMA_dma.h>
-#include <SD_RX_DMA_COMPLETE.h>
-#include <SD_TX_DMA_COMPLETE.h>
-#include <SCSI_RX_DMA_dma.h>
-#include <SCSI_RX_DMA_COMPLETE.h>
-#include <SCSI_Parity_Error.h>
-#include <SCSI_Filtered.h>
-#include <EXTLED_aliases.h>
-#include <EXTLED.h>
-#include <SCSI_SEL_ISR.h>
-#include <SCSI_Glitch_Ctl.h>
-#include <USBFS_Dm_aliases.h>
-#include <USBFS_Dm.h>
-#include <USBFS_Dp_aliases.h>
-#include <USBFS_Dp.h>
-#include <core_cm3_psoc5.h>
-#include <core_cm3.h>
-#include <CyDmac.h>
-#include <CyFlash.h>
-#include <CyLib.h>
-#include <cypins.h>
-#include <cyPm.h>
-#include <CySpc.h>
-#include <cytypes.h>
-#include <core_cmFunc.h>
-#include <core_cmInstr.h>
+#include "cyfitter_cfg.h"
+#include "cydevice.h"
+#include "cydevice_trm.h"
+#include "cyfitter.h"
+#include "cydisabledsheets.h"
+#include "SCSI_In_DBx_aliases.h"
+#include "SCSI_Out_DBx_aliases.h"
+#include "SD_Data_Clk.h"
+#include "SD_CD_aliases.h"
+#include "SD_CD.h"
+#include "SCSI_CTL_PHASE.h"
+#include "SCSI_In_aliases.h"
+#include "SCSI_Out_aliases.h"
+#include "CFG_EEPROM.h"
+#include "SD_CS_aliases.h"
+#include "SD_CS.h"
+#include "SD_SCK_aliases.h"
+#include "SD_SCK.h"
+#include "SD_MOSI_aliases.h"
+#include "SD_MOSI.h"
+#include "SCSI_CLK.h"
+#include "SCSI_Noise_aliases.h"
+#include "SCSI_RST_ISR.h"
+#include "LED1_aliases.h"
+#include "LED1.h"
+#include "SDCard.h"
+#include "SDCard_PVT.h"
+#include "SD_MISO_aliases.h"
+#include "SD_MISO.h"
+#include "USBFS.h"
+#include "USBFS_audio.h"
+#include "USBFS_cdc.h"
+#include "USBFS_hid.h"
+#include "USBFS_midi.h"
+#include "USBFS_pvt.h"
+#include "Bootloadable_1.h"
+#include "SCSI_Out_Bits.h"
+#include "SCSI_Out_Ctl.h"
+#include "Debug_Timer.h"
+#include "timer_clock.h"
+#include "Debug_Timer_Interrupt.h"
+#include "SCSI_TX_DMA_dma.h"
+#include "SCSI_TX_DMA_COMPLETE.h"
+#include "SD_RX_DMA_dma.h"
+#include "SD_TX_DMA_dma.h"
+#include "SD_RX_DMA_COMPLETE.h"
+#include "SD_TX_DMA_COMPLETE.h"
+#include "SCSI_RX_DMA_dma.h"
+#include "SCSI_RX_DMA_COMPLETE.h"
+#include "SCSI_Parity_Error.h"
+#include "SCSI_Filtered.h"
+#include "EXTLED_aliases.h"
+#include "EXTLED.h"
+#include "SCSI_SEL_ISR.h"
+#include "SCSI_Glitch_Ctl.h"
+#include "USBFS_Dm_aliases.h"
+#include "USBFS_Dm.h"
+#include "USBFS_Dp_aliases.h"
+#include "USBFS_Dp.h"
+#include "core_cm3_psoc5.h"
+#include "core_cm3.h"
+#include "CyDmac.h"
+#include "CyFlash.h"
+#include "CyLib.h"
+#include "cypins.h"
+#include "cyPm.h"
+#include "CySpc.h"
+#include "cytypes.h"
+#include "core_cmFunc.h"
+#include "core_cmInstr.h"
 
 /*[]*/
 

software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx

@@ -1,12 +1,13 @@
 <?xml version="1.0" encoding="utf-8"?>
 <blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
+  <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="">
+    <register name="SCSI_Filtered_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_MASK_REG" address="0x4000648B" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="">
       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
         <value name="ENABLED" value="1" desc="Enable counter" />
         <value name="DISABLED" value="0" desc="Disable counter" />
@@ -34,9 +35,9 @@
     </register>
   </block>
   <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006469" bitWidth="8" desc="" />
-    <register name="SCSI_Parity_Error_MASK_REG" address="0x40006489" bitWidth="8" desc="" />
-    <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006499" bitWidth="8" desc="">
+    <register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646A" bitWidth="8" desc="" />
+    <register name="SCSI_Parity_Error_MASK_REG" address="0x4000648A" bitWidth="8" desc="" />
+    <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649A" bitWidth="8" desc="">
       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
         <value name="ENABLED" value="1" desc="Enable counter" />
         <value name="DISABLED" value="0" desc="Disable counter" />
@@ -63,29 +64,29 @@
       </field>
     </register>
   </block>
-  <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />
+    <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006476" bitWidth="8" desc="" />
   </block>
   <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -98,7 +99,7 @@
   <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />
+    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" />
   </block>
   <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -257,10 +258,10 @@
     <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
   </block>
   <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />
+    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006574" bitWidth="8" desc="" />
   </block>
   <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />
+    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006577" bitWidth="8" desc="" />
   </block>
   <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />

software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj

@@ -1802,6 +1802,15 @@
 <PropertyDeltas />
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
 </CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_PHASE_PM.c" persistent=".\Generated_Source\PSoC5\SCSI_CTL_PHASE_PM.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@@ -1982,6 +1991,15 @@
 <PropertyDeltas />
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
 </CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Out_Bits_PM.c" persistent=".\Generated_Source\PSoC5\SCSI_Out_Bits_PM.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@@ -2012,6 +2030,15 @@
 <PropertyDeltas />
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
 </CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Out_Ctl_PM.c" persistent=".\Generated_Source\PSoC5\SCSI_Out_Ctl_PM.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@@ -2351,6 +2378,15 @@
 <PropertyDeltas />
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
 </CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl_PM.c" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctl_PM.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@@ -2437,7 +2473,6 @@
 <GlobalPages />
 <GlobalTools name="Code Generation">
 <GlobalPages>
-<name_val_pair name="General@Application Type" v="Bootloadable" />
 <name_val_pair name="General@Custom Code Gen Options" v="" />
 <name_val_pair name="General@Skip Code Generation" v="False" />
 <name_val_pair name="General@Custom Synthesis Options" v="" />
@@ -2484,7 +2519,6 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Libraries" v="" />
@@ -2492,11 +2526,9 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Link Files" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Debugging Information" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Nano Lib" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Enable printf Float" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
@@ -2519,7 +2551,6 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Additional Libraries" v="" />
@@ -2527,11 +2558,9 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Additional Link Files" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Debugging Information" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Nano Lib" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Enable printf Float" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
@@ -2554,7 +2583,6 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
@@ -2562,11 +2590,9 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Link Files" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Debugging Information" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Nano Lib" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Enable printf Float" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
@@ -2589,7 +2615,6 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Inline Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Libraries" v="" />
@@ -2597,11 +2622,9 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Link Files" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Debugging Information" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Nano Lib" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Enable printf Float" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@Optimization Level" v="Size" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Command Line@Command Line" v="" />
 </name>
@@ -2628,7 +2651,6 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Additional Libraries" v="" />
@@ -2636,11 +2658,9 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Additional Link Files" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Use Debugging Information" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Use Nano Lib" v="True" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Enable printf Float" v="True" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
@@ -2663,7 +2683,6 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Additional Libraries" v="" />
@@ -2671,11 +2690,9 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Additional Link Files" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Use Debugging Information" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Use Nano Lib" v="True" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Enable printf Float" v="True" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
@@ -2698,7 +2715,6 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
@@ -2706,11 +2722,9 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Additional Link Files" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Use Debugging Information" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Use Nano Lib" v="True" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Enable printf Float" v="True" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
@@ -2733,7 +2747,6 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Additional Libraries" v="" />
@@ -2741,11 +2754,9 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Additional Link Files" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Use Debugging Information" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Use Nano Lib" v="True" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Enable printf Float" v="True" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Command Line@Command Line" v="" />
 </name>
@@ -2753,101 +2764,9 @@
 <platform>
 <name v="5bca58cd-5542-421c-b08d-9513dbb687fd">
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Assembly@General@Additional Include Directories" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Assembly@General@Generate List Files" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Assembly@Command Line@Command Line" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@General@Additional Include Directories" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@General@Generate List Files" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@General@Default Char Unsigned" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@General@Generate Debugging Information" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@General@Preprocessor Definitions" v="DEBUG" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@General@Strict Compilation" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@Optimization@Split Sections" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Linker@General@Additional Libraries" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Linker@General@Additional Library Directories" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Linker@General@Generate Map File" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Linker@General@Generate Debugging Information" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Assembly@General@Suppress Warnings" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Assembly@General@Generate List Files" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Assembly@Command Line@Command Line" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@General@Additional Include Directories" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@General@Generate List Files" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@General@Default Char Unsigned" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@General@Generate Debugging Information" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@General@Preprocessor Definitions" v="NDEBUG" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@General@Strict Compilation" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@Optimization@Split Sections" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@Command Line@Command Line" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Linker@General@Additional Libraries" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Linker@General@Additional Library Directories" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Linker@General@Generate Map File" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Linker@General@Generate Debugging Information" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Linker@General@Use Default Libs" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Linker@Command Line@Command Line" v="" />
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Assembly@General@Suppress Warnings" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Assembly@General@Generate List Files" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Assembly@Command Line@Command Line" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Additional Include Directories" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Generate List Files" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Preprocessor Definitions" v="DEBUG" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Strict Compilation" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Optimization@Split Sections" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Generate Debugging Information" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@General@Generate List Files" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@Command Line@Command Line" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Generate List Files" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Preprocessor Definitions" v="NDEBUG" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Strict Compilation" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Split Sections" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Additional Libraries" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Additional Library Directories" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Generate Map File" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@Command Line@Command Line" v="" />
 </name>
 </platform>
 <platform>
@@ -2871,6 +2790,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Additional Libraries" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Additional Library Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Use MicroLib" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Generate Debugging Information" v="True" />
@@ -2895,6 +2815,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Additional Libraries" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Additional Library Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Use MicroLib" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Custom Linker Script" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Generate Debugging Information" v="True" />
@@ -2919,6 +2840,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Use MicroLib" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Debugging Information" v="True" />
@@ -2943,6 +2865,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Libraries" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Library Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Use MicroLib" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />
@@ -2962,11 +2885,9 @@
 </platforms>
 <project_current_platform v="c9323d49-d323-40b8-9b59-cc008d68a989" />
 <project_current_processor v="CortexM3" />
-<component_generation v="PSoC Creator  2.2 Component Pack 6" />
 <last_selected_tab v="Cypress" />
-<component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , 2.1PR) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 3.0) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1) | (e95576e7-780d-474a-b944-018db0492cc9 , 2.1)" />
-<WriteAppVersionLastSavedWith v="3.1.0.1570" />
-<WriteAppMarketingVersionLastSavedWith v=" 3.1" />
+<WriteAppVersionLastSavedWith v="3.2.0.724" />
+<WriteAppMarketingVersionLastSavedWith v=" 3.2" />
 <project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" /><custom_data><CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1"><CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2"><userData /></CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997><properties /></CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111></custom_data></CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
 </CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>
 <top_block v="TopDesign" />
@@ -2980,7 +2901,5 @@
 <ignored_deps />
 </CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
 <boot_component v="cy_boot_v4_20" />
-<BootloaderTag hexFile="" elfFile="" />
-<current_generation v="2" />
-</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
+<current_generation v="2" /><BootloaderTag hexFile="" elfFile="" /></CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
 </CyXmlSerializer>

software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd

@@ -9,7 +9,7 @@
     <peripheral>
       <name>SCSI_Filtered</name>
       <description>No description available</description>
-      <baseAddress>0x40006468</baseAddress>
+      <baseAddress>0x4000646B</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -164,7 +164,7 @@
     <peripheral>
       <name>SCSI_Parity_Error</name>
       <description>No description available</description>
-      <baseAddress>0x40006469</baseAddress>
+      <baseAddress>0x4000646A</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -319,7 +319,7 @@
     <peripheral>
       <name>SCSI_Glitch_Ctl</name>
       <description>No description available</description>
-      <baseAddress>0x4000647A</baseAddress>
+      <baseAddress>0x40006476</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -340,7 +340,7 @@
     <peripheral>
       <name>SCSI_CTL_PHASE</name>
       <description>No description available</description>
-      <baseAddress>0x40006472</baseAddress>
+      <baseAddress>0x40006475</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -1137,7 +1137,7 @@
     <peripheral>
       <name>SCSI_Out_Ctl</name>
       <description>No description available</description>
-      <baseAddress>0x40006478</baseAddress>
+      <baseAddress>0x40006574</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -1158,7 +1158,7 @@
     <peripheral>
       <name>SCSI_Out_Bits</name>
       <description>No description available</description>
-      <baseAddress>0x4000647B</baseAddress>
+      <baseAddress>0x40006577</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>

software/include/scsi2sd.h

@@ -85,7 +85,8 @@ typedef enum
 {
 	CONFIG_ENABLE_UNIT_ATTENTION = 1,
 	CONFIG_ENABLE_PARITY = 2,
-	CONFIG_ENABLE_SCSI2 = 4
+	CONFIG_ENABLE_SCSI2 = 4,
+	CONFIG_DISABLE_GLITCH = 8
 } CONFIG_FLAGS;
 
 typedef enum