From 75de12268f917a22d9074a93488b27ec5657ec6a Mon Sep 17 00:00:00 2001 From: Michael McMaster Date: Thu, 3 Oct 2013 07:07:58 +1000 Subject: [PATCH] Creating new repository to prune history. --- COPYING | 674 + hardware/.gitignore | 5 + hardware/Makefile | 35 + hardware/bracket/3.5_hdd_mount.scad | 208 + hardware/bracket/3.5_hdd_mount.stl | 54616 ++++++++++++++++ hardware/gafrc | 7 + hardware/gerber/scsi2sd.GBL | 27881 ++++++++ hardware/gerber/scsi2sd.GBO | 13 + hardware/gerber/scsi2sd.GBS | 116 + hardware/gerber/scsi2sd.GTL | 45027 +++++++++++++ hardware/gerber/scsi2sd.GTO | 1617 + hardware/gerber/scsi2sd.GTS | 605 + hardware/gerber/scsi2sd.TXT | 206 + hardware/gerber/scsi2sd.outline | 25 + hardware/gerber/scsi2sd.stencil | 490 + hardware/scsi2sd.bom | 23 + hardware/scsi2sd.cmd | 434 + hardware/scsi2sd.net | 77 + hardware/scsi2sd.pcb | 3874 ++ hardware/scsi2sd.sch | 2458 + hardware/symbols/7406.sym | 176 + hardware/symbols/7406.tragesym | 74 + hardware/symbols/CY8C53.sym | 1126 + hardware/symbols/CY8C53.tragesym | 164 + hardware/symbols/DO-41-vert.fp | 10 + hardware/symbols/DO-41.fp | 10 + hardware/symbols/DPAK.fp | 20 + hardware/symbols/FCI-10067847.fp | 66 + hardware/symbols/FCI-10067847.sym | 156 + hardware/symbols/FCI-10067847.tragesym | 73 + hardware/symbols/FTSH-105-01-L-DV-K.fp | 25 + hardware/symbols/HEADER50_2_RA.fp | 64 + hardware/symbols/LD1117.sym | 55 + hardware/symbols/LD1117.tragesym | 64 + hardware/symbols/MOLEX8981.fp | 18 + hardware/symbols/MOLEX8981.sym | 64 + hardware/symbols/MOLEX8981.tragesym | 63 + hardware/symbols/SCDA7A0101.sym | 156 + hardware/symbols/SCDA7A0101.tragesym | 74 + hardware/symbols/SOT23_MOSFET.fp | 30 + hardware/symbols/SOT26_MOSFET.fp | 36 + hardware/symbols/TO220_TRANSISTOR.fp | 19 + hardware/symbols/cap_0402.fp | 11 + hardware/symbols/diode-DO-214AA-SMB.fp | 24 + hardware/symbols/fci-10118192-0001LF.fp | 23 + hardware/symbols/usbmini.sym | 51 + hardware/symbols/wurth-microsd.fp | 28 + hardware/symbols/wurth-microsd.sym | 132 + hardware/symbols/wurth-microsd.tragesym | 70 + parts.ods | Bin 0 -> 20160 bytes readme.txt | 33 + software/SCSI2SD/.gitignore | 1 + software/SCSI2SD/SCSI2SD.cydsn/.gitignore | 7 + .../Generated_Source/PSoC5/Cm3RealView.scat | 64 + .../Generated_Source/PSoC5/Cm3Start.c | 319 + .../Generated_Source/PSoC5/CyBootAsmGnu.s | 120 + .../Generated_Source/PSoC5/CyBootAsmRv.s | 110 + .../Generated_Source/PSoC5/CyDmac.c | 1089 + .../Generated_Source/PSoC5/CyDmac.h | 212 + .../Generated_Source/PSoC5/CyFlash.c | 732 + .../Generated_Source/PSoC5/CyFlash.h | 311 + .../Generated_Source/PSoC5/CyLib.c | 2846 + .../Generated_Source/PSoC5/CyLib.h | 1201 + .../Generated_Source/PSoC5/CySpc.c | 562 + .../Generated_Source/PSoC5/CySpc.h | 159 + .../Generated_Source/PSoC5/LED1.c | 137 + .../Generated_Source/PSoC5/LED1.h | 130 + .../Generated_Source/PSoC5/LED1_aliases.h | 32 + .../Generated_Source/PSoC5/PARITY_EN.c | 137 + .../Generated_Source/PSoC5/PARITY_EN.h | 130 + .../PSoC5/PARITY_EN_aliases.h | 32 + .../Generated_Source/PSoC5/SCSI_ID_aliases.h | 34 + .../Generated_Source/PSoC5/SCSI_In_DBx.c | 144 + .../Generated_Source/PSoC5/SCSI_In_DBx.h | 130 + .../PSoC5/SCSI_In_DBx_aliases.h | 48 + .../Generated_Source/PSoC5/SCSI_In_aliases.h | 52 + .../Generated_Source/PSoC5/SCSI_Out_DBx.c | 144 + .../Generated_Source/PSoC5/SCSI_Out_DBx.h | 130 + .../PSoC5/SCSI_Out_DBx_aliases.h | 48 + .../Generated_Source/PSoC5/SCSI_Out_aliases.h | 52 + .../SCSI2SD.cydsn/Generated_Source/PSoC5/SD.c | 1155 + .../SCSI2SD.cydsn/Generated_Source/PSoC5/SD.h | 389 + .../Generated_Source/PSoC5/SDCard.c | 1155 + .../Generated_Source/PSoC5/SDCard.h | 389 + .../Generated_Source/PSoC5/SDCard_INT.c | 189 + .../Generated_Source/PSoC5/SDCard_PM.c | 180 + .../Generated_Source/PSoC5/SDCard_PVT.h | 53 + .../Generated_Source/PSoC5/SD_CD.c | 137 + .../Generated_Source/PSoC5/SD_CD.h | 130 + .../Generated_Source/PSoC5/SD_CD_aliases.h | 32 + .../Generated_Source/PSoC5/SD_CS.c | 137 + .../Generated_Source/PSoC5/SD_CS.h | 130 + .../Generated_Source/PSoC5/SD_CS_aliases.h | 32 + .../Generated_Source/PSoC5/SD_Clk_Ctl.c | 63 + .../Generated_Source/PSoC5/SD_Clk_Ctl.h | 42 + .../Generated_Source/PSoC5/SD_DAT1.c | 137 + .../Generated_Source/PSoC5/SD_DAT1.h | 130 + .../Generated_Source/PSoC5/SD_DAT1_aliases.h | 32 + .../Generated_Source/PSoC5/SD_DAT2.c | 137 + .../Generated_Source/PSoC5/SD_DAT2.h | 130 + .../Generated_Source/PSoC5/SD_DAT2_aliases.h | 32 + .../Generated_Source/PSoC5/SD_Data_Clk.c | 521 + .../Generated_Source/PSoC5/SD_Data_Clk.h | 124 + .../Generated_Source/PSoC5/SD_INT.c | 189 + .../Generated_Source/PSoC5/SD_Init_Clk.c | 521 + .../Generated_Source/PSoC5/SD_Init_Clk.h | 124 + .../Generated_Source/PSoC5/SD_IntClock.c | 521 + .../Generated_Source/PSoC5/SD_IntClock.h | 124 + .../Generated_Source/PSoC5/SD_MISO.c | 137 + .../Generated_Source/PSoC5/SD_MISO.h | 130 + .../Generated_Source/PSoC5/SD_MISO_aliases.h | 32 + .../Generated_Source/PSoC5/SD_MOSI.c | 137 + .../Generated_Source/PSoC5/SD_MOSI.h | 130 + .../Generated_Source/PSoC5/SD_MOSI_aliases.h | 32 + .../Generated_Source/PSoC5/SD_PM.c | 180 + .../Generated_Source/PSoC5/SD_PVT.h | 53 + .../Generated_Source/PSoC5/SD_SCK.c | 137 + .../Generated_Source/PSoC5/SD_SCK.h | 130 + .../Generated_Source/PSoC5/SD_SCK_aliases.h | 32 + .../Generated_Source/PSoC5/SD_WP.c | 137 + .../Generated_Source/PSoC5/SD_WP.h | 130 + .../Generated_Source/PSoC5/SD_WP_aliases.h | 32 + .../Generated_Source/PSoC5/cm3gcc.ld | 223 + .../Generated_Source/PSoC5/config.hex | 30 + .../Generated_Source/PSoC5/core_cm3.c | 784 + .../Generated_Source/PSoC5/core_cm3.h | 1818 + .../Generated_Source/PSoC5/core_cm3_psoc5.h | 43 + .../Generated_Source/PSoC5/cyPm.c | 2459 + .../Generated_Source/PSoC5/cyPm.h | 779 + .../Generated_Source/PSoC5/cydevice.h | 5359 ++ .../Generated_Source/PSoC5/cydevice_trm.h | 5359 ++ .../Generated_Source/PSoC5/cydevicegnu.inc | 5356 ++ .../PSoC5/cydevicegnu_trm.inc | 5356 ++ .../Generated_Source/PSoC5/cydevicerv.inc | 16039 +++++ .../Generated_Source/PSoC5/cydevicerv_trm.inc | 16039 +++++ .../Generated_Source/PSoC5/cyfitter.h | 1875 + .../Generated_Source/PSoC5/cyfitter_cfg.c | 412 + .../Generated_Source/PSoC5/cyfitter_cfg.h | 28 + .../Generated_Source/PSoC5/cyfittergnu.inc | 1867 + .../Generated_Source/PSoC5/cyfitterrv.inc | 1868 + .../Generated_Source/PSoC5/cypins.h | 295 + .../Generated_Source/PSoC5/cytypes.h | 411 + .../Generated_Source/PSoC5/cyutils.c | 87 + .../Generated_Source/PSoC5/post_link.bat | 19 + .../Generated_Source/PSoC5/project.h | 64 + .../Generated_Source/PSoC5/protect.hex | 5 + software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx | 33 + software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cydwr | Bin 0 -> 121200 bytes software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 0 -> 184817 bytes software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj | 1565 + .../SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyversion | 1 + software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd | 31 + .../SCSI2SD.cydsn/SCSI2SD_PSoC5lib.uvopt | 280 + .../SCSI2SD.cydsn/SCSI2SD_PSoC5lib.uvproj | 1404 + .../SCSI2SD.cydsn/TopDesign/TopDesign.cysch | Bin 0 -> 90538 bytes software/SCSI2SD/SCSI2SD.cydsn/bits.c | 47 + software/SCSI2SD/SCSI2SD.cydsn/bits.h | 27 + software/SCSI2SD/SCSI2SD.cydsn/blinky.c | 31 + software/SCSI2SD/SCSI2SD.cydsn/blinky.h | 25 + software/SCSI2SD/SCSI2SD.cydsn/device.h | 18 + software/SCSI2SD/SCSI2SD.cydsn/diagnostic.c | 132 + software/SCSI2SD/SCSI2SD.cydsn/diagnostic.h | 23 + software/SCSI2SD/SCSI2SD.cydsn/disk.c | 697 + software/SCSI2SD/SCSI2SD.cydsn/disk.h | 59 + software/SCSI2SD/SCSI2SD.cydsn/geometry.c | 168 + software/SCSI2SD/SCSI2SD.cydsn/geometry.h | 51 + software/SCSI2SD/SCSI2SD.cydsn/inquiry.c | 160 + software/SCSI2SD/SCSI2SD.cydsn/inquiry.h | 22 + software/SCSI2SD/SCSI2SD.cydsn/led.h | 25 + software/SCSI2SD/SCSI2SD.cydsn/loopback.c | 122 + software/SCSI2SD/SCSI2SD.cydsn/loopback.h | 30 + software/SCSI2SD/SCSI2SD.cydsn/main.c | 53 + software/SCSI2SD/SCSI2SD.cydsn/mode.c | 322 + software/SCSI2SD/SCSI2SD.cydsn/mode.h | 22 + software/SCSI2SD/SCSI2SD.cydsn/scsi.c | 683 + software/SCSI2SD/SCSI2SD.cydsn/scsi.h | 114 + software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c | 150 + software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h | 41 + software/SCSI2SD/SCSI2SD.cydsn/sense.h | 176 + 179 files changed, 231870 insertions(+) create mode 100644 COPYING create mode 100644 hardware/.gitignore create mode 100644 hardware/Makefile create mode 100644 hardware/bracket/3.5_hdd_mount.scad create mode 100644 hardware/bracket/3.5_hdd_mount.stl create mode 100644 hardware/gafrc create mode 100644 hardware/gerber/scsi2sd.GBL create mode 100644 hardware/gerber/scsi2sd.GBO create mode 100644 hardware/gerber/scsi2sd.GBS create mode 100644 hardware/gerber/scsi2sd.GTL create mode 100644 hardware/gerber/scsi2sd.GTO create mode 100644 hardware/gerber/scsi2sd.GTS create mode 100644 hardware/gerber/scsi2sd.TXT create mode 100644 hardware/gerber/scsi2sd.outline create mode 100644 hardware/gerber/scsi2sd.stencil create mode 100644 hardware/scsi2sd.bom create mode 100644 hardware/scsi2sd.cmd create mode 100644 hardware/scsi2sd.net create mode 100644 hardware/scsi2sd.pcb create mode 100644 hardware/scsi2sd.sch create mode 100644 hardware/symbols/7406.sym create mode 100644 hardware/symbols/7406.tragesym create mode 100644 hardware/symbols/CY8C53.sym create mode 100644 hardware/symbols/CY8C53.tragesym create mode 100644 hardware/symbols/DO-41-vert.fp create mode 100644 hardware/symbols/DO-41.fp create mode 100644 hardware/symbols/DPAK.fp create mode 100644 hardware/symbols/FCI-10067847.fp create mode 100644 hardware/symbols/FCI-10067847.sym create mode 100644 hardware/symbols/FCI-10067847.tragesym create mode 100644 hardware/symbols/FTSH-105-01-L-DV-K.fp create mode 100644 hardware/symbols/HEADER50_2_RA.fp create mode 100644 hardware/symbols/LD1117.sym create mode 100644 hardware/symbols/LD1117.tragesym create mode 100644 hardware/symbols/MOLEX8981.fp create mode 100644 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100755 software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h create mode 100755 software/SCSI2SD/SCSI2SD.cydsn/sense.h diff --git a/COPYING b/COPYING new file mode 100644 index 0000000..94a9ed0 --- /dev/null +++ b/COPYING @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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Limitation of Liability. + + IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS +THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY +GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE +USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF +DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD +PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), +EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF +SUCH DAMAGES. + + 17. Interpretation of Sections 15 and 16. + + If the disclaimer of warranty and limitation of liability provided +above cannot be given local legal effect according to their terms, +reviewing courts shall apply local law that most closely approximates +an absolute waiver of all civil liability in connection with the +Program, unless a warranty or assumption of liability accompanies a +copy of the Program in return for a fee. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/hardware/.gitignore b/hardware/.gitignore new file mode 100644 index 0000000..241aa1f --- /dev/null +++ b/hardware/.gitignore @@ -0,0 +1,5 @@ +*.sch~ +*.bak +*.bak0 +*.pcb.old + diff --git a/hardware/Makefile b/hardware/Makefile new file mode 100644 index 0000000..eaba138 --- /dev/null +++ b/hardware/Makefile @@ -0,0 +1,35 @@ +JUNK =\ + scsi2sd.pcb.bak \ + scsi2sd.pcb.bak0 \ + scsi2sd.pcb.old \ + scsi2sd.sch~ \ + + +SYMBOLS =\ + symbols/7406.sym \ + symbols/CY8C53.sym \ + symbols/FCI-10067847.sym \ + symbols/LD1117.sym \ + symbols/MOLEX8981.sym \ + symbols/SCDA7A0101.sym \ + symbols/wurth-microsd.sym \ + + +all: $(SYMBOLS) scsi2sd.bom scsi2sd.pcb + +symbols/%.sym : symbols/%.tragesym + tragesym $< $@ + +scsi2sd.bom : scsi2sd.sch + gnetlist -g partslist3 -o scsi2sd.bom scsi2sd.sch + +scsi2sd.pcb : scsi2sd.sch + gsch2pcb -d symbols scsi2sd.sch + +clean: + rm $(JUNK) + +realclean: + rm $(JUNK) + rm $(SYMBOLS) + diff --git a/hardware/bracket/3.5_hdd_mount.scad b/hardware/bracket/3.5_hdd_mount.scad new file mode 100644 index 0000000..0b974fa --- /dev/null +++ b/hardware/bracket/3.5_hdd_mount.scad @@ -0,0 +1,208 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + + +$fa = 3; // 4-times as many angles per circle. +$fs = 0.1; // 0.1mm accuracy + + // A* taken from SFF-8301 Specification for Form Factor of 3.5" Disk Drives + + A3 = 101.6; // width + A5 = 3.19; // Distance from side to bottom hole. + A6 = 44.45; // Distance from A7 to second bottom hole. + A7 = 41.28; // Distance from front to bottom holes. + A8 = 28.5; // Distance from front to side holes + A9 = 101.60; // Distance between side holes. + A10 = 6.35; // Height from base to site holes. + A13 = 76.2; // Distance from A7 to third bottom hole. + m3HoleRadius=2.667/2; // M3x0.50 minimum hole size (aluminium or softer material) + holeBulk=4; // Extra around holes + tmp = 10; + wallWidth = 1.3; + screwWidth = 3; + foo = 6; + bar = 4; // PSOC MOUNT + +PCB_DIFF=90.42; // Clearance line of "fat" via is 10mil from edge. +PCB_off = (A3 - PCB_DIFF) / 2; +// from front = A7 + foo = 47.28 +// second = 47.28 + A6 = 91.73. Perfect! +// Height between board and screw: +// screwWidth + 1.6mm pcb only = 3 + 1.6 =4.6. Not a problem! +// Width of PCB vs side hole bulk: 101.6 - 97.5360 = 4.064 +// only 2mm to spare on either side. +// TODO Made a NOTCH in the PCB to handle this! +// notch: A8 +- holeBulk = 28.5 - 4, 28.5 + 4 = 24 -> 33mm. 3mm in. + + + +module hdd_side() +{ + difference() + { + union() + { + cube([A8 + A9 + tmp, wallWidth, A10 + holeBulk]); + + // Bottom mount 1 + translate([A7 - (foo / 2), 0, 0]) + { + cube([foo, foo, screwWidth]); + } + + // Bottom mount 2 + translate([A6 + A7 - (foo / 2), 0, 0]) + { + cube([foo, foo, screwWidth]); + } + + // Bottom mount 3 + translate([A13 + A7 - (foo / 2), 0, 0]) + { + cube([foo, foo, screwWidth]); + } + + // psoc mount 1 + translate([A7 - (foo / 2) + foo, 0, 0]) + { + cube([foo, foo + bar, screwWidth]); + } + + // psoc mount 2 + translate([A6 + A7 - (foo / 2) + foo, 0, 0]) + { + cube([foo, foo + bar, screwWidth]); + } + + // Extra bulk behind side holes + translate([A8, 0, A10]) + { + rotate([270, 0, 0]) + { + cylinder(h=screwWidth, r=holeBulk); + } + } + + translate([A8 + A9, 0, A10]) + { + rotate([270, 0, 0]) + { + cylinder(h=screwWidth, r=holeBulk); + } + } + } + + // Remove excess material from the side + translate([-0.5, -0.5,screwWidth + wallWidth]) + { + cube([A8 - tmp + 0.5, wallWidth + 1, A10 + holeBulk]); + } + translate([A8 + tmp, -0.5, screwWidth + wallWidth]) + { + cube([A9 - (tmp * 2), wallWidth + 1, A10 + holeBulk]); + } + + + // SIDE HOLES + + translate([A8, -0.5, A10]) + { + rotate([270, 0, 0]) + { + cylinder(h=screwWidth + 1, r=m3HoleRadius); + } + } + + translate([A8 + A9, -0.5, A10]) + { + rotate([270, 0, 0]) + { + cylinder(h=screwWidth + 1, r=m3HoleRadius); + } + } + + // BOTTOM HOLES + // Bottom hole 1 + translate([A7, A5, -0.5]) + { + cylinder(h=screwWidth + 1, r = m3HoleRadius); + } + + // Bottom hole 2 + translate([A6 + A7, A5, -0.5]) + { + cylinder(h=screwWidth + 1, r = m3HoleRadius); + } + + // Bottom hole 3 + translate([A13 + A7, A5, -0.5]) + { + cylinder(h=screwWidth + 1, r = m3HoleRadius); + } + + // PSOC hole1 + translate([A7 + foo, PCB_off, -0.5]) + { + cylinder(h=screwWidth + 1, r = m3HoleRadius); + } + // PSOC hole2 + translate([A6 + A7 + foo, PCB_off, -0.5]) + { + cylinder(h=screwWidth + 1, r = m3HoleRadius); + } + } +} + +union() +{ + hdd_side(); + translate([0, A3, 0]) + { + mirror([0, 1, 0]) + { + hdd_side(); + } + } + + cube([wallWidth * 2, A3, wallWidth]); + + translate([A8 + A9 + tmp - wallWidth * 2, 0, 0]) + { + cube([wallWidth * 2, A3, wallWidth]); + } + + // Bottom hole 1 + translate([A7 + foo, foo + bar, 0]) + { + cube([wallWidth * 2, A3 - ((foo + bar) * 2), wallWidth]); + } + + // Bottom hole 2 + translate([A6 + A7 + foo, foo + bar, 0]) + { + cube([wallWidth * 2, A3 - ((foo + bar) * 2), wallWidth]); + } + + + for (i = [0:3]) + { + translate([0, (i * (A3 - wallWidth) / 3), 0]) + { + cube([A8 + A9 + tmp, wallWidth, wallWidth]); + } + } +} diff --git a/hardware/bracket/3.5_hdd_mount.stl b/hardware/bracket/3.5_hdd_mount.stl new file mode 100644 index 0000000..c9b8cd1 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+X238563Y22913D02*Y20157D01* +X234232Y23701D02*Y20945D01* +X229902Y22913D02*Y20157D01* +X225571Y23701D02*Y20945D01* +X221240Y23701D02*Y20945D01* +G54D114*X218091Y12283D02*Y10315D01* +X224390Y63071D02*X225965D01* +X246831D02*X248406D01* +X270453Y7953D02*Y5984D01* +G54D115*X124844Y85950D02*X132944D01* +X124844Y90950D02*X132944D01* +X124844Y95950D02*X132944D01* +X124844Y100950D02*X132944D01* +X124844Y105950D02*X132944D01* +X108844Y85950D02*X116944D01* +X108844Y90950D02*X116944D01* +X108844Y95950D02*X116944D01* +X108844Y100950D02*X116944D01* +X108844Y105950D02*X116944D01* +G54D104*X361800Y99000D02*X363200D01* +X361800Y107000D02*X363200D01* +G54D107*G36* +X340250Y260750D02*Y249250D01* +X351750D01* +Y260750D01* +X340250D01* +G37* +G36* +X325250D02*Y249250D01* +X336750D01* +Y260750D01* +X325250D01* +G37* +G36* +X340250Y245750D02*Y234250D01* +X351750D01* +Y245750D01* +X340250D01* +G37* +G36* +X325250D02*Y234250D01* +X336750D01* +Y245750D01* +X325250D01* +G37* +G54D108*X347500Y224000D02*Y218500D01* +X329500Y224000D02*Y218500D01* +G54D116*X127607Y56000D02*X128394D01* +X144536D02*X145323D01* +X76106Y309000D02*X76893D01* +X59177D02*X59964D01* +X20500Y234894D02*Y234107D01* +Y251823D02*Y251036D01* +M02* diff --git a/hardware/scsi2sd.bom b/hardware/scsi2sd.bom new file mode 100644 index 0000000..8c17c0d --- /dev/null +++ b/hardware/scsi2sd.bom @@ -0,0 +1,23 @@ +.START +..device value footprint quantity refdes +7406 unknown SO14 3 U3 U4 U5 +CAPACITOR 100nF cap_0402 11 C10 C11 C17 C19 C21 C22 C23 C24 C28 C3 C9 +CAPACITOR 10uF SMD_SIMPLE 80 50 8 C1 C12 C13 C14 C2 C4 C5 C7 +CAPACITOR 1uF cap_0402 4 C20 C26 C27 C8 +CY8C53 unknown TQFP100_14 1 U1 +DIODE unknown diode-DO-214AA-SMB 3 D1 D2 D3 +FUSE 1.5A Hold SMD_SIMPLE 120 60 1 F1 +FUSE 500mA Hold SMD_SIMPLE 120 60 1 F2 +HEADER10 unknown FTSH-105-01-L-DV-K 1 J4 +HEADER50 unknown HEADER50_2_RA 1 J2 +JUMPER unknown HEADER2_2 1 J3 +LD1117 unknown DPAK 2 U2 U6 +LED unknown SMD_DIODE 80 50 1 LED1 +MOLEX8981 unknown MOLEX8981 1 J1 +RESISTOR 10K SMD_SIMPLE 80 50 7 R10 R11 R12 R6 R7 R8 R9 +RESISTOR 1600 SMD_SIMPLE 80 50 1 R3 +RESISTOR 22Ω SMD_SIMPLE 80 50 2 R4 R5 +RESISTORPACK_10 unknown SIP10 2 R1 R2 +USB unknown fci-10118192-0001LF 1 J5 +wurth-693071010811 unknown wurth-microsd 1 J6 +.END diff --git a/hardware/scsi2sd.cmd b/hardware/scsi2sd.cmd new file mode 100644 index 0000000..61165e2 --- /dev/null +++ b/hardware/scsi2sd.cmd @@ -0,0 +1,434 @@ +# Pin name action command file + +# Start of element J6 +ChangePinName(J6, 10, \_CD\_) +ChangePinName(J6, 9, GND) +ChangePinName(J6, 8, DAT1) +ChangePinName(J6, 7, DAT0) +ChangePinName(J6, 6, GND) +ChangePinName(J6, 5, CLK) +ChangePinName(J6, 4, Vcc) +ChangePinName(J6, 3, CMD) +ChangePinName(J6, 2, DAT3) +ChangePinName(J6, 1, DAT2) + +# Start of element R2 +ChangePinName(R2, 10, 10) +ChangePinName(R2, 9, 9) +ChangePinName(R2, 8, 8) +ChangePinName(R2, 7, 7) +ChangePinName(R2, 6, 6) +ChangePinName(R2, 1, 1) +ChangePinName(R2, 5, 5) +ChangePinName(R2, 4, 4) +ChangePinName(R2, 3, 3) +ChangePinName(R2, 2, 2) + +# Start of element R1 +ChangePinName(R1, 10, 10) +ChangePinName(R1, 9, 9) +ChangePinName(R1, 8, 8) +ChangePinName(R1, 7, 7) +ChangePinName(R1, 6, 6) +ChangePinName(R1, 1, 1) +ChangePinName(R1, 5, 5) +ChangePinName(R1, 4, 4) +ChangePinName(R1, 3, 3) +ChangePinName(R1, 2, 2) + +# Start of element R5 +ChangePinName(R5, 1, 1) +ChangePinName(R5, 2, 2) + +# Start of element R4 +ChangePinName(R4, 1, 1) +ChangePinName(R4, 2, 2) + +# Start of element J5 +ChangePinName(J5, 5, GND) +ChangePinName(J5, 1, VCC) +ChangePinName(J5, 2, D-) +ChangePinName(J5, 3, D+) +ChangePinName(J5, 4, ID) + +# Start of element D3 +ChangePinName(D3, 1, cathode) +ChangePinName(D3, 2, anode) + +# Start of element F2 +ChangePinName(F2, 2, 2) +ChangePinName(F2, 1, 1) + +# Start of element F1 +ChangePinName(F1, 2, 2) +ChangePinName(F1, 1, 1) + +# Start of element D1 +ChangePinName(D1, 1, cathode) +ChangePinName(D1, 2, anode) + +# Start of element D2 +ChangePinName(D2, 1, cathode) +ChangePinName(D2, 2, anode) + +# Start of element J3 +ChangePinName(J3, 1, 1) +ChangePinName(J3, 2, 2) + +# Start of element C14 +ChangePinName(C14, 2, 2) +ChangePinName(C14, 1, 1) + +# Start of element C4 +ChangePinName(C4, 2, 2) +ChangePinName(C4, 1, 1) + +# Start of element C7 +ChangePinName(C7, 2, 2) +ChangePinName(C7, 1, 1) + +# Start of element U6 +ChangePinName(U6, 3, IN) +ChangePinName(U6, 2, OUT) +ChangePinName(U6, 1, GND) + +# Start of element U2 +ChangePinName(U2, 3, IN) +ChangePinName(U2, 2, OUT) +ChangePinName(U2, 1, GND) + +# Start of element C12 +ChangePinName(C12, 2, 2) +ChangePinName(C12, 1, 1) + +# Start of element C13 +ChangePinName(C13, 2, 2) +ChangePinName(C13, 1, 1) + +# Start of element C5 +ChangePinName(C5, 2, 2) +ChangePinName(C5, 1, 1) + +# Start of element C8 +ChangePinName(C8, 2, 2) +ChangePinName(C8, 1, 1) + +# Start of element U1 +ChangePinName(U1, 76, P0[4]) +ChangePinName(U1, 77, P0[5]) +ChangePinName(U1, 78, P0[6]) +ChangePinName(U1, 79, P0[7]) +ChangePinName(U1, 80, P4[2]) +ChangePinName(U1, 81, P4[3]) +ChangePinName(U1, 82, P4[4]) +ChangePinName(U1, 83, P4[5]) +ChangePinName(U1, 84, P4[6]) +ChangePinName(U1, 85, P4[7]) +ChangePinName(U1, 86, VCCD) +ChangePinName(U1, 87, VSSD) +ChangePinName(U1, 88, VDDD) +ChangePinName(U1, 89, P6[0]) +ChangePinName(U1, 90, P6[1]) +ChangePinName(U1, 91, P6[2]) +ChangePinName(U1, 92, P6[3]) +ChangePinName(U1, 93, P15[4]) +ChangePinName(U1, 94, P15[5]) +ChangePinName(U1, 95, P2[0]) +ChangePinName(U1, 96, P2[1]) +ChangePinName(U1, 97, P2[2]) +ChangePinName(U1, 98, P2[3]) +ChangePinName(U1, 99, P2[4]) +ChangePinName(U1, 100, VDDIO2) +ChangePinName(U1, 51, P3[6]) +ChangePinName(U1, 52, P3[7]) +ChangePinName(U1, 53, P12[0]) +ChangePinName(U1, 54, P12[1]) +ChangePinName(U1, 55, "XO XTAL P15[2],KHZ") +ChangePinName(U1, 56, "XI XTAL P15[3],KHZ") +ChangePinName(U1, 57, NC) +ChangePinName(U1, 58, NC) +ChangePinName(U1, 59, NC) +ChangePinName(U1, 60, NC) +ChangePinName(U1, 61, NC) +ChangePinName(U1, 62, NC) +ChangePinName(U1, 63, VCCA) +ChangePinName(U1, 64, VSSA) +ChangePinName(U1, 65, VDDA) +ChangePinName(U1, 66, VSSD) +ChangePinName(U1, 67, P12[2]) +ChangePinName(U1, 68, P12[3]) +ChangePinName(U1, 69, P4[0]) +ChangePinName(U1, 70, P4[1]) +ChangePinName(U1, 71, P0[0]) +ChangePinName(U1, 72, P0[1]) +ChangePinName(U1, 73, P0[2]) +ChangePinName(U1, 74, P0[3]) +ChangePinName(U1, 75, VDDIO0) +ChangePinName(U1, 50, VDDIO3) +ChangePinName(U1, 49, P3[5]) +ChangePinName(U1, 48, P3[4]) +ChangePinName(U1, 47, P3[3]) +ChangePinName(U1, 46, P3[2]) +ChangePinName(U1, 45, P3[1]) +ChangePinName(U1, 44, P3[0]) +ChangePinName(U1, 43, MHZ XTAL XI) +ChangePinName(U1, 42, MHZ XTAL XO) +ChangePinName(U1, 41, NC) +ChangePinName(U1, 40, NC) +ChangePinName(U1, 39, VCCD) +ChangePinName(U1, 38, VSSD) +ChangePinName(U1, 37, VDDD) +ChangePinName(U1, 36, "SWDCK,USB D-") +ChangePinName(U1, 35, "SWDIO,USB D+") +ChangePinName(U1, 34, P5[7]) +ChangePinName(U1, 33, P5[6]) +ChangePinName(U1, 32, P5[5]) +ChangePinName(U1, 31, P5[4]) +ChangePinName(U1, 30, P12[7]) +ChangePinName(U1, 29, P12[6]) +ChangePinName(U1, 28, P1[7]) +ChangePinName(U1, 27, P1[6]) +ChangePinName(U1, 26, VDDIO1) +ChangePinName(U1, 25, P1[5]) +ChangePinName(U1, 24, P1[4]) +ChangePinName(U1, 23, "SWV,P1[3]") +ChangePinName(U1, 22, P1[2]) +ChangePinName(U1, 21, "SWDCK,P1[1]") +ChangePinName(U1, 20, "SWDIO,P1[0]") +ChangePinName(U1, 19, P5[3]) +ChangePinName(U1, 18, P5[2]) +ChangePinName(U1, 17, P5[1]) +ChangePinName(U1, 16, P5[0]) +ChangePinName(U1, 15, \_XRES\_) +ChangePinName(U1, 14, VSSD) +ChangePinName(U1, 13, VSSD) +ChangePinName(U1, 12, VSSD) +ChangePinName(U1, 11, NC) +ChangePinName(U1, 10, VSSD) +ChangePinName(U1, 9, P6[7]) +ChangePinName(U1, 8, P6[6]) +ChangePinName(U1, 7, P6[5]) +ChangePinName(U1, 6, P6[4]) +ChangePinName(U1, 5, P12[5]) +ChangePinName(U1, 4, P12[4]) +ChangePinName(U1, 3, P2[7]) +ChangePinName(U1, 2, P2[6]) +ChangePinName(U1, 1, P2[5]) + +# Start of element R12 +ChangePinName(R12, 1, 1) +ChangePinName(R12, 2, 2) + +# Start of element R11 +ChangePinName(R11, 1, 1) +ChangePinName(R11, 2, 2) + +# Start of element R10 +ChangePinName(R10, 1, 1) +ChangePinName(R10, 2, 2) + +# Start of element R9 +ChangePinName(R9, 1, 1) +ChangePinName(R9, 2, 2) + +# Start of element R8 +ChangePinName(R8, 1, 1) +ChangePinName(R8, 2, 2) + +# Start of element R7 +ChangePinName(R7, 1, 1) +ChangePinName(R7, 2, 2) + +# Start of element R6 +ChangePinName(R6, 1, 1) +ChangePinName(R6, 2, 2) + +# Start of element C26 +ChangePinName(C26, 2, 2) +ChangePinName(C26, 1, 1) + +# Start of element C20 +ChangePinName(C20, 2, 2) +ChangePinName(C20, 1, 1) + +# Start of element C27 +ChangePinName(C27, 2, 2) +ChangePinName(C27, 1, 1) + +# Start of element C19 +ChangePinName(C19, 2, 2) +ChangePinName(C19, 1, 1) + +# Start of element C24 +ChangePinName(C24, 2, 2) +ChangePinName(C24, 1, 1) + +# Start of element C23 +ChangePinName(C23, 2, 2) +ChangePinName(C23, 1, 1) + +# Start of element C17 +ChangePinName(C17, 2, 2) +ChangePinName(C17, 1, 1) + +# Start of element C21 +ChangePinName(C21, 2, 2) +ChangePinName(C21, 1, 1) + +# Start of element C28 +ChangePinName(C28, 2, 2) +ChangePinName(C28, 1, 1) + +# Start of element R3 +ChangePinName(R3, 1, 1) +ChangePinName(R3, 2, 2) + +# Start of element LED1 +ChangePinName(LED1, 2, K) +ChangePinName(LED1, 1, A) + +# Start of element C11 +ChangePinName(C11, 2, 2) +ChangePinName(C11, 1, 1) + +# Start of element C10 +ChangePinName(C10, 2, 2) +ChangePinName(C10, 1, 1) + +# Start of element C3 +ChangePinName(C3, 2, 2) +ChangePinName(C3, 1, 1) + +# Start of element C9 +ChangePinName(C9, 2, 2) +ChangePinName(C9, 1, 1) + +# Start of element J4 +ChangePinName(J4, 6, 6) +ChangePinName(J4, 7, 7) +ChangePinName(J4, 8, 8) +ChangePinName(J4, 9, 9) +ChangePinName(J4, 10, 10) +ChangePinName(J4, 5, 5) +ChangePinName(J4, 1, 1) +ChangePinName(J4, 4, 4) +ChangePinName(J4, 3, 3) +ChangePinName(J4, 2, 2) + +# Start of element C1 +ChangePinName(C1, 2, 2) +ChangePinName(C1, 1, 1) + +# Start of element U5 +ChangePinName(U5, 8, \_Y3\_) +ChangePinName(U5, 9, A3) +ChangePinName(U5, 10, \_Y4\_) +ChangePinName(U5, 11, A4) +ChangePinName(U5, 12, \_Y5\_) +ChangePinName(U5, 13, A5) +ChangePinName(U5, 14, Vcc) +ChangePinName(U5, 7, GND) +ChangePinName(U5, 6, \_Y2\_) +ChangePinName(U5, 5, A2) +ChangePinName(U5, 4, \_Y1\_) +ChangePinName(U5, 3, A1) +ChangePinName(U5, 2, \_Y0\_) +ChangePinName(U5, 1, A0) + +# Start of element U4 +ChangePinName(U4, 8, \_Y3\_) +ChangePinName(U4, 9, A3) +ChangePinName(U4, 10, \_Y4\_) +ChangePinName(U4, 11, A4) +ChangePinName(U4, 12, \_Y5\_) +ChangePinName(U4, 13, A5) +ChangePinName(U4, 14, Vcc) +ChangePinName(U4, 7, GND) +ChangePinName(U4, 6, \_Y2\_) +ChangePinName(U4, 5, A2) +ChangePinName(U4, 4, \_Y1\_) +ChangePinName(U4, 3, A1) +ChangePinName(U4, 2, \_Y0\_) +ChangePinName(U4, 1, A0) + +# Start of element U3 +ChangePinName(U3, 8, \_Y3\_) +ChangePinName(U3, 9, A3) +ChangePinName(U3, 10, \_Y4\_) +ChangePinName(U3, 11, A4) +ChangePinName(U3, 12, \_Y5\_) +ChangePinName(U3, 13, A5) +ChangePinName(U3, 14, Vcc) +ChangePinName(U3, 7, GND) +ChangePinName(U3, 6, \_Y2\_) +ChangePinName(U3, 5, A2) +ChangePinName(U3, 4, \_Y1\_) +ChangePinName(U3, 3, A1) +ChangePinName(U3, 2, \_Y0\_) +ChangePinName(U3, 1, A0) + +# Start of element C2 +ChangePinName(C2, 2, 2) +ChangePinName(C2, 1, 1) + +# Start of element C22 +ChangePinName(C22, 2, 2) +ChangePinName(C22, 1, 1) + +# Start of element J1 +ChangePinName(J1, 4, +5V) +ChangePinName(J1, 3, GND) +ChangePinName(J1, 2, GND) +ChangePinName(J1, 1, +12V) + +# Start of element J2 +ChangePinName(J2, 50, 50) +ChangePinName(J2, 49, 49) +ChangePinName(J2, 48, 48) +ChangePinName(J2, 47, 47) +ChangePinName(J2, 46, 46) +ChangePinName(J2, 45, 45) +ChangePinName(J2, 44, 44) +ChangePinName(J2, 43, 43) +ChangePinName(J2, 42, 42) +ChangePinName(J2, 41, 41) +ChangePinName(J2, 40, 40) +ChangePinName(J2, 39, 39) +ChangePinName(J2, 38, 38) +ChangePinName(J2, 37, 37) +ChangePinName(J2, 36, 36) +ChangePinName(J2, 35, 35) +ChangePinName(J2, 34, 34) +ChangePinName(J2, 33, 33) +ChangePinName(J2, 32, 32) +ChangePinName(J2, 31, 31) +ChangePinName(J2, 30, 30) +ChangePinName(J2, 29, 29) +ChangePinName(J2, 28, 28) +ChangePinName(J2, 27, 27) +ChangePinName(J2, 26, 26) +ChangePinName(J2, 25, 25) +ChangePinName(J2, 24, 24) +ChangePinName(J2, 23, 23) +ChangePinName(J2, 22, 22) +ChangePinName(J2, 21, 21) +ChangePinName(J2, 20, 20) +ChangePinName(J2, 19, 19) +ChangePinName(J2, 18, 18) +ChangePinName(J2, 17, 17) +ChangePinName(J2, 16, 16) +ChangePinName(J2, 15, 15) +ChangePinName(J2, 14, 14) +ChangePinName(J2, 13, 13) +ChangePinName(J2, 12, 12) +ChangePinName(J2, 11, 11) +ChangePinName(J2, 10, 10) +ChangePinName(J2, 9, 9) +ChangePinName(J2, 8, 8) +ChangePinName(J2, 7, 7) +ChangePinName(J2, 6, 6) +ChangePinName(J2, 5, 5) +ChangePinName(J2, 4, 4) +ChangePinName(J2, 3, 3) +ChangePinName(J2, 2, 2) +ChangePinName(J2, 1, 1) diff --git a/hardware/scsi2sd.net b/hardware/scsi2sd.net new file mode 100644 index 0000000..a77931a --- /dev/null +++ b/hardware/scsi2sd.net @@ -0,0 +1,77 @@ +unnamed_net28 R5-1 J5-2 +unnamed_net27 R4-1 J5-3 +unnamed_net26 J5-4 +unnamed_net25 D3-2 F2-2 +unnamed_net24 J5-1 F2-1 +unnamed_net23 D1-2 J3-1 +drive_5V F1-2 D2-2 J3-2 +unnamed_net22 R1-1 R2-1 C14-2 C7-2 U2-2 +unnamed_net21 U1-55 +unnamed_net20 U1-42 +unnamed_net19 R5-2 U1-36 +unnamed_net18 R4-2 U1-35 +unnamed_net17 U1-25 +unnamed_net16 U1-24 +unnamed_net15 U1-22 +unnamed_net14 U1-11 +SD_DAT2 J6-1 U1-49 R12-1 +\_SD_CS\_ J6-2 U1-48 R11-1 +SD_MOSI J6-3 U1-47 R10-1 +\_SD_CD\_ J6-10 U1-51 R9-1 +SD_SCK J6-5 U1-46 R8-1 +SD_MISO J6-7 U1-45 R7-1 +SD_DAT1 J6-8 U1-44 R6-1 +unnamed_net13 U1-86 U1-39 C20-2 +unnamed_net12 U1-63 C27-2 +unnamed_net11 U1-68 LED1-2 +unnamed_net10 R3-1 LED1-1 +unnamed_net9 U1-23 J4-6 +unnamed_net8 J4-8 +unnamed_net7 U1-15 J4-10 +unnamed_net6 U1-21 J4-4 +unnamed_net5 U1-20 J4-2 +DB0 U1-92 U5-9 +DB2 U1-90 U5-11 +DB4 U1-85 U5-13 +DB1 U1-91 U5-5 +DB3 U1-89 U5-3 +DB5 U1-84 U5-1 +DB6 U1-83 U4-9 +DBP U1-81 U4-11 +BSY U1-79 U4-13 +DB7 U1-82 U4-5 +ATN U1-80 U4-3 +ACK U1-78 U4-1 +RST U1-77 U3-9 +SEL U1-74 U3-11 +REQ U1-72 U3-13 +MSG U1-76 U3-5 +C/D U1-73 U3-3 +I/O U1-71 U3-1 +5V D3-1 U6-3 C12-2 C26-2 U1-65 C24-2 U1-88 C8-2 C19-2 U1-37 C23-2 U1-100 C17-2 U1-75 C21-2 R3-2 U1-26 C9-2 J4-1 C11-2 U5-14 C10-2 U4-14 C3-2 U3-14 D2-1 C4-2 C2-2 +3.3V U6-2 C13-2 R12-2 R11-2 R10-2 R9-2 R8-2 R7-2 R6-2 U1-50 C28-2 J6-4 C22-2 +unnamed_net4 F1-1 J1-4 +unnamed_net3 J1-1 +\_I/O\_ R2-2 U1-19 U3-2 J2-50 +\_REQ\_ R2-3 U1-18 U3-12 J2-48 +\_C/D\_ R2-4 U1-17 U3-4 J2-46 +\_SEL\_ R2-5 U1-16 U3-10 J2-44 +\_MSG\_ R2-6 U1-9 U3-6 J2-42 +\_RST\_ R2-7 U1-8 U3-8 J2-40 +\_ACK\_ R2-8 U1-7 U4-2 J2-38 +\_BSY\_ R2-9 U1-6 U4-12 J2-36 +\_ATN\_ R2-10 U1-5 U4-4 J2-32 +unnamed_net2 D1-1 U2-3 C5-2 C1-2 J2-26 +unnamed_net1 J2-25 +\_DBP\_ R1-2 U1-95 U4-10 J2-18 +\_DB7\_ R1-3 U1-96 U4-6 J2-16 +\_DB6\_ R1-4 U1-97 U4-8 J2-14 +\_DB5\_ R1-5 U1-98 U5-2 J2-12 +\_DB4\_ R1-6 U1-99 U5-12 J2-10 +\_DB3\_ R1-7 U1-1 U5-4 J2-8 +\_DB2\_ R1-8 U1-2 U5-10 J2-6 +\_DB1\_ R1-9 U1-3 U5-6 J2-4 +\_DB0\_ R1-10 U1-4 U5-8 J2-2 +GND J6-9 J6-6 J5-5 C14-1 C4-1 C7-1 U6-1 U2-1 C12-1 C13-1 C5-1 C8-1 U1-87 U1-93 U1-94 U1-52 U1-53 U1-54 U1-56 U1-57 U1-58 U1-59 U1-60 U1-61 U1-62 U1-64 U1-66 U1-67 U1-69 U1-70 U1-43 U1-41 U1-40 U1-38 \ + U1-34 U1-33 U1-32 U1-31 U1-30 U1-29 U1-28 U1-27 U1-14 U1-13 U1-12 U1-10 C26-1 C20-1 C27-1 C19-1 C24-1 C23-1 C17-1 C21-1 C28-1 C11-1 C10-1 C3-1 C9-1 J4-7 J4-9 J4-5 J4-3 C1-1 U5-7 U4-7 U3-7 C2-1 C22-1 \ + J1-3 J1-2 J2-34 J2-30 J2-28 J2-22 J2-24 J2-20 J2-49 J2-47 J2-45 J2-43 J2-41 J2-39 J2-37 J2-35 J2-33 J2-31 J2-29 J2-27 J2-19 J2-17 J2-15 J2-13 J2-11 J2-9 J2-7 J2-5 J2-3 J2-23 J2-21 J2-1 diff --git a/hardware/scsi2sd.pcb b/hardware/scsi2sd.pcb new file mode 100644 index 0000000..283a64c --- /dev/null +++ b/hardware/scsi2sd.pcb @@ -0,0 +1,3874 @@ +# release: pcb 20110918 + +# To read pcb files, the pcb version (or the git source date) must be >= the file version +FileVersion[20070407] + +PCB["" 384000 393500] + +Grid[500.0 0 0 1] +Cursor[234500 70000 0.000000] +PolyArea[200000000.000000] +Thermal[0.500000] +DRC[600 100 600 600 1200 600] +Flags("showdrc,nameonpcb,clearnew,snappin") +Groups("1,c:2,s:3:4:5:6:7:8") +Styles["Signal,1000,2800,1200,800:Power,2500,6000,3500,1000:Fat,5000,25000,12500,1000:Skinny,800,2400,1200,600"] + +Symbol[' ' 1800] +( +) +Symbol['!' 1200] +( + SymbolLine[0 4500 0 5000 800] + SymbolLine[0 1000 0 3500 800] +) +Symbol['"' 1200] +( + SymbolLine[0 1000 0 2000 800] + SymbolLine[1000 1000 1000 2000 800] +) +Symbol['#' 1200] +( + SymbolLine[0 3500 2000 3500 800] + SymbolLine[0 2500 2000 2500 800] + SymbolLine[1500 2000 1500 4000 800] + SymbolLine[500 2000 500 4000 800] +) +Symbol['$' 1200] +( + SymbolLine[1500 1500 2000 2000 800] + SymbolLine[500 1500 1500 1500 800] + SymbolLine[0 2000 500 1500 800] + SymbolLine[0 2000 0 2500 800] + SymbolLine[0 2500 500 3000 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 2000 4000 800] + SymbolLine[1500 4500 2000 4000 800] + SymbolLine[500 4500 1500 4500 800] + SymbolLine[0 4000 500 4500 800] + SymbolLine[1000 1000 1000 5000 800] +) +Symbol['%' 1200] +( + SymbolLine[0 1500 0 2000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1000 1000 800] + SymbolLine[1000 1000 1500 1500 800] + SymbolLine[1500 1500 1500 2000 800] + SymbolLine[1000 2500 1500 2000 800] + SymbolLine[500 2500 1000 2500 800] + SymbolLine[0 2000 500 2500 800] + SymbolLine[0 5000 4000 1000 800] + SymbolLine[3500 5000 4000 4500 800] + SymbolLine[4000 4000 4000 4500 800] + SymbolLine[3500 3500 4000 4000 800] + SymbolLine[3000 3500 3500 3500 800] + SymbolLine[2500 4000 3000 3500 800] + SymbolLine[2500 4000 2500 4500 800] + SymbolLine[2500 4500 3000 5000 800] + SymbolLine[3000 5000 3500 5000 800] +) +Symbol['&' 1200] +( + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 1500 0 2500 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 3500 1500 2000 800] + SymbolLine[500 5000 1000 5000 800] + SymbolLine[1000 5000 2000 4000 800] + SymbolLine[0 2500 2500 5000 800] + SymbolLine[500 1000 1000 1000 800] + SymbolLine[1000 1000 1500 1500 800] + SymbolLine[1500 1500 1500 2000 800] + SymbolLine[0 3500 0 4500 800] +) +Symbol[''' 1200] +( + SymbolLine[0 2000 1000 1000 800] +) +Symbol['(' 1200] +( + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 1500 0 4500 800] +) +Symbol[')' 1200] +( + SymbolLine[0 1000 500 1500 800] + SymbolLine[500 1500 500 4500 800] + SymbolLine[0 5000 500 4500 800] +) +Symbol['*' 1200] +( + SymbolLine[0 2000 2000 4000 800] + SymbolLine[0 4000 2000 2000 800] + SymbolLine[0 3000 2000 3000 800] + SymbolLine[1000 2000 1000 4000 800] +) +Symbol['+' 1200] +( + SymbolLine[0 3000 2000 3000 800] + SymbolLine[1000 2000 1000 4000 800] +) +Symbol[',' 1200] +( + SymbolLine[0 6000 1000 5000 800] +) +Symbol['-' 1200] +( + SymbolLine[0 3000 2000 3000 800] +) +Symbol['.' 1200] +( + SymbolLine[0 5000 500 5000 800] +) +Symbol['/' 1200] +( + SymbolLine[0 4500 3000 1500 800] +) +Symbol['0' 1200] +( + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 1500 0 4500 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4000 2000 2000 800] +) +Symbol['1' 1200] +( + SymbolLine[0 1800 800 1000 800] + SymbolLine[800 1000 800 5000 800] + SymbolLine[0 5000 1500 5000 800] +) +Symbol['2' 1200] +( + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 2000 1000 800] + SymbolLine[2000 1000 2500 1500 800] + SymbolLine[2500 1500 2500 2500 800] + SymbolLine[0 5000 2500 2500 800] + SymbolLine[0 5000 2500 5000 800] +) +Symbol['3' 1200] +( + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 2800 1500 2800 800] + SymbolLine[2000 1500 2000 2300 800] + SymbolLine[2000 3300 2000 4500 800] + SymbolLine[2000 3300 1500 2800 800] + SymbolLine[2000 2300 1500 2800 800] +) +Symbol['4' 1200] +( + SymbolLine[0 3500 2000 1000 800] + SymbolLine[0 3500 2500 3500 800] + SymbolLine[2000 1000 2000 5000 800] +) +Symbol['5' 1200] +( + SymbolLine[0 1000 2000 1000 800] + SymbolLine[0 1000 0 3000 800] + SymbolLine[0 3000 500 2500 800] + SymbolLine[500 2500 1500 2500 800] + SymbolLine[1500 2500 2000 3000 800] + SymbolLine[2000 3000 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4500 500 5000 800] +) +Symbol['6' 1200] +( + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 1500 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[1500 2800 2000 3300 800] + SymbolLine[0 2800 1500 2800 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[2000 3300 2000 4500 800] +) +Symbol['7' 1200] +( + SymbolLine[500 5000 2500 1000 800] + SymbolLine[0 1000 2500 1000 800] +) +Symbol['8' 1200] +( + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 3700 0 4500 800] + SymbolLine[0 3700 700 3000 800] + SymbolLine[700 3000 1300 3000 800] + SymbolLine[1300 3000 2000 3700 800] + SymbolLine[2000 3700 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 2300 700 3000 800] + SymbolLine[0 1500 0 2300 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 2300 800] + SymbolLine[1300 3000 2000 2300 800] +) +Symbol['9' 1200] +( + SymbolLine[500 5000 2000 3000 800] + SymbolLine[2000 1500 2000 3000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 1500 0 2500 800] + SymbolLine[0 2500 500 3000 800] + SymbolLine[500 3000 2000 3000 800] +) +Symbol[':' 1200] +( + SymbolLine[0 2500 500 2500 800] + SymbolLine[0 3500 500 3500 800] +) +Symbol[';' 1200] +( + SymbolLine[0 5000 1000 4000 800] + SymbolLine[1000 2500 1000 3000 800] +) +Symbol['<' 1200] +( + SymbolLine[0 3000 1000 2000 800] + SymbolLine[0 3000 1000 4000 800] +) +Symbol['=' 1200] +( + SymbolLine[0 2500 2000 2500 800] + SymbolLine[0 3500 2000 3500 800] +) +Symbol['>' 1200] +( + SymbolLine[0 2000 1000 3000 800] + SymbolLine[0 4000 1000 3000 800] +) +Symbol['?' 1200] +( + SymbolLine[1000 3000 1000 3500 800] + SymbolLine[1000 4500 1000 5000 800] + SymbolLine[0 1500 0 2000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 2000 800] + SymbolLine[1000 3000 2000 2000 800] +) +Symbol['@' 1200] +( + SymbolLine[0 1000 0 4000 800] + SymbolLine[0 4000 1000 5000 800] + SymbolLine[1000 5000 4000 5000 800] + SymbolLine[5000 3500 5000 1000 800] + SymbolLine[5000 1000 4000 0 800] + SymbolLine[4000 0 1000 0 800] + SymbolLine[1000 0 0 1000 800] + SymbolLine[1500 2000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 3000 3500 800] + SymbolLine[3000 3500 3500 3000 800] + SymbolLine[3500 3000 4000 3500 800] + SymbolLine[3500 3000 3500 1500 800] + SymbolLine[3500 2000 3000 1500 800] + SymbolLine[2000 1500 3000 1500 800] + SymbolLine[2000 1500 1500 2000 800] + SymbolLine[4000 3500 5000 3500 800] +) +Symbol['A' 1200] +( + SymbolLine[0 2000 0 5000 800] + SymbolLine[0 2000 700 1000 800] + SymbolLine[700 1000 1800 1000 800] + SymbolLine[1800 1000 2500 2000 800] + SymbolLine[2500 2000 2500 5000 800] + SymbolLine[0 3000 2500 3000 800] +) +Symbol['B' 1200] +( + SymbolLine[0 5000 2000 5000 800] + SymbolLine[2000 5000 2500 4500 800] + SymbolLine[2500 3300 2500 4500 800] + SymbolLine[2000 2800 2500 3300 800] + SymbolLine[500 2800 2000 2800 800] + SymbolLine[500 1000 500 5000 800] + SymbolLine[0 1000 2000 1000 800] + SymbolLine[2000 1000 2500 1500 800] + SymbolLine[2500 1500 2500 2300 800] + SymbolLine[2000 2800 2500 2300 800] +) +Symbol['C' 1200] +( + SymbolLine[700 5000 2000 5000 800] + SymbolLine[0 4300 700 5000 800] + SymbolLine[0 1700 0 4300 800] + SymbolLine[0 1700 700 1000 800] + SymbolLine[700 1000 2000 1000 800] +) +Symbol['D' 1200] +( + SymbolLine[500 1000 500 5000 800] + SymbolLine[1800 1000 2500 1700 800] + SymbolLine[2500 1700 2500 4300 800] + SymbolLine[1800 5000 2500 4300 800] + SymbolLine[0 5000 1800 5000 800] + SymbolLine[0 1000 1800 1000 800] +) +Symbol['E' 1200] +( + SymbolLine[0 2800 1500 2800 800] + SymbolLine[0 5000 2000 5000 800] + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 1000 2000 1000 800] +) +Symbol['F' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 1000 2000 1000 800] + SymbolLine[0 2800 1500 2800 800] +) +Symbol['G' 1200] +( + SymbolLine[2000 1000 2500 1500 800] + SymbolLine[500 1000 2000 1000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 1500 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 2000 5000 800] + SymbolLine[2000 5000 2500 4500 800] + SymbolLine[2500 3500 2500 4500 800] + SymbolLine[2000 3000 2500 3500 800] + SymbolLine[1000 3000 2000 3000 800] +) +Symbol['H' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[2500 1000 2500 5000 800] + SymbolLine[0 3000 2500 3000 800] +) +Symbol['I' 1200] +( + SymbolLine[0 1000 1000 1000 800] + SymbolLine[500 1000 500 5000 800] + SymbolLine[0 5000 1000 5000 800] +) +Symbol['J' 1200] +( + SymbolLine[700 1000 1500 1000 800] + SymbolLine[1500 1000 1500 4500 800] + SymbolLine[1000 5000 1500 4500 800] + SymbolLine[500 5000 1000 5000 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 4500 0 4000 800] +) +Symbol['K' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 3000 2000 1000 800] + SymbolLine[0 3000 2000 5000 800] +) +Symbol['L' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 5000 2000 5000 800] +) +Symbol['M' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 1000 1500 3000 800] + SymbolLine[1500 3000 3000 1000 800] + SymbolLine[3000 1000 3000 5000 800] +) +Symbol['N' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 1000 2500 5000 800] + SymbolLine[2500 1000 2500 5000 800] +) +Symbol['O' 1200] +( + SymbolLine[0 1500 0 4500 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4500 500 5000 800] +) +Symbol['P' 1200] +( + SymbolLine[500 1000 500 5000 800] + SymbolLine[0 1000 2000 1000 800] + SymbolLine[2000 1000 2500 1500 800] + SymbolLine[2500 1500 2500 2500 800] + SymbolLine[2000 3000 2500 2500 800] + SymbolLine[500 3000 2000 3000 800] +) +Symbol['Q' 1200] +( + SymbolLine[0 1500 0 4500 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 4000 800] 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SymbolLine[1500 3000 2000 3500 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[0 3500 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[0 6000 500 6500 800] + SymbolLine[500 6500 1500 6500 800] + SymbolLine[1500 6500 2000 6000 800] + SymbolLine[2000 3000 2000 6000 800] +) +Symbol['h' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 2000 5000 800] +) +Symbol['i' 1000] +( + SymbolLine[0 2000 0 2100 1000] + SymbolLine[0 3500 0 5000 800] +) +Symbol['j' 1000] +( + SymbolLine[500 2000 500 2100 1000] + SymbolLine[500 3500 500 6000 800] + SymbolLine[0 6500 500 6000 800] +) +Symbol['k' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 3500 1500 5000 800] + SymbolLine[0 3500 1000 2500 800] +) +Symbol['l' 1000] +( + SymbolLine[0 1000 0 4500 800] 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-21653 1102 3000 1402 "P0[3]" "74" "square,edge2"] + Pad[30110 -23622 35008 -23622 1102 3000 1402 "VDDIO0" "75" "square,edge2"] + Pad[23622 -35008 23622 -30110 1102 3000 1402 "P0[4]" "76" "square,octagon"] + Pad[21654 -35008 21654 -30110 1102 3000 1402 "P0[5]" "77" "square,octagon"] + Pad[19685 -35008 19685 -30110 1102 3000 1402 "P0[6]" "78" "square,octagon"] + Pad[17717 -35008 17717 -30110 1102 3000 1402 "P0[7]" "79" "square,octagon"] + Pad[15748 -35008 15748 -30110 1102 3000 1402 "P4[2]" "80" "square,octagon"] + Pad[13780 -35008 13780 -30110 1102 3000 1402 "P4[3]" "81" "square,octagon"] + Pad[11811 -35008 11811 -30110 1102 3000 1402 "P4[4]" "82" "square,octagon"] + Pad[9843 -35008 9843 -30110 1102 3000 1402 "P4[5]" "83" "square,octagon"] + Pad[7874 -35008 7874 -30110 1102 3000 1402 "P4[6]" "84" "square,octagon"] + Pad[5906 -35008 5906 -30110 1102 3000 1402 "P4[7]" "85" "square,octagon"] + Pad[3937 -35008 3937 -30110 1102 3000 1402 "VCCD" "86" "square,octagon"] + Pad[1969 -35008 1969 -30110 1102 3000 1402 "VSSD" "87" "square,octagon"] + Pad[0 -35008 0 -30110 1102 3000 1402 "VDDD" "88" "square,octagon"] + Pad[-1968 -35008 -1968 -30110 1102 3000 1402 "P6[0]" "89" "square,octagon"] + Pad[-3937 -35008 -3937 -30110 1102 3000 1402 "P6[1]" "90" "square,octagon"] + Pad[-5905 -35008 -5905 -30110 1102 3000 1402 "P6[2]" "91" "square,octagon"] + Pad[-7874 -35008 -7874 -30110 1102 3000 1402 "P6[3]" "92" "square,octagon"] + Pad[-9842 -35008 -9842 -30110 1102 3000 1402 "P15[4]" "93" "square,octagon"] + Pad[-11811 -35008 -11811 -30110 1102 3000 1402 "P15[5]" "94" "square,octagon"] + Pad[-13779 -35008 -13779 -30110 1102 3000 1402 "P2[0]" "95" "square,octagon"] + Pad[-15748 -35008 -15748 -30110 1102 3000 1402 "P2[1]" "96" "square,octagon"] + Pad[-17716 -35008 -17716 -30110 1102 3000 1402 "P2[2]" "97" "square,octagon"] + Pad[-19685 -35008 -19685 -30110 1102 3000 1402 "P2[3]" "98" "square,octagon"] + Pad[-21653 -35008 -21653 -30110 1102 3000 1402 "P2[4]" "99" "square,octagon"] + Pad[-23622 -35008 -23622 -30110 1102 3000 1402 "VDDIO2" "100" "square,octagon"] + ElementLine [-24259 -27159 27159 -27159 800] + ElementLine [27159 -27159 27159 27159 800] + ElementLine [27159 27159 -27159 27159 800] + ElementLine [-27159 27159 -27159 -24259 800] + ElementLine [-27159 -24259 -24259 -27159 800] + ElementArc [-24259 -24259 1000 1000 0 360 800] + + ) + +Element["" "cap_0402" "C19" "100nF" 192465 232435 4100 -5970 0 100 ""] +( + Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"] + Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"] + ElementLine [-1737 1837 1806 1837 600] + ElementLine [1806 -5643 1806 1837 600] + ElementLine [-1737 -5643 1806 -5643 600] + ElementLine [-1737 -5643 -1737 1837 600] + + ) + +Element["" "cap_0402" "C17" "100nF" 161035 237128 -3970 -9100 0 100 ""] +( + Pad[-35 3872 -35 3872 1969 1200 2569 "1" "1" "square"] + Pad[-35 -65 -35 -65 1969 1200 2569 "2" "2" "square"] + ElementLine [-1806 -1837 1737 -1837 600] + ElementLine [-1806 -1837 -1806 5643 600] + ElementLine [-1806 5643 1737 5643 600] + ElementLine [1737 -1837 1737 5643 600] + + ) + +Element["" "cap_0402" "C21" "100nF" 221965 240935 -3900 -12470 0 100 ""] +( + Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"] + Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"] + ElementLine [-1737 1837 1806 1837 600] + ElementLine [1806 -5643 1806 1837 600] + ElementLine [-1737 -5643 1806 -5643 600] + ElementLine [-1737 -5643 -1737 1837 600] + + ) + +Element["" "cap_0402" "C28" "100nF" 221965 305872 5537 -4407 0 100 ""] +( + Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"] + Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"] + ElementLine [-1737 1837 1806 1837 600] + ElementLine [1806 -5643 1806 1837 600] + ElementLine [-1737 -5643 1806 -5643 600] + ElementLine [-1737 -5643 -1737 1837 600] + + ) + +Element["" "cap_0402" "C11" "100nF" 153465 187372 8070 -5744 3 100 ""] +( + Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"] + Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"] + ElementLine [-1737 1837 1806 1837 600] + ElementLine [1806 -5643 1806 1837 600] + ElementLine [-1737 -5643 1806 -5643 600] + ElementLine [-1737 -5643 -1737 1837 600] + + ) + +Element["" "cap_0402" "C3" "100nF" 292965 188935 8000 -4000 3 100 ""] +( + Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"] + Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"] + ElementLine [-1737 1837 1806 1837 600] + ElementLine [1806 -5643 1806 1837 600] + ElementLine [-1737 -5643 1806 -5643 600] + ElementLine [-1737 -5643 -1737 1837 600] + + ) + +Element["" "cap_0402" "C9" "100nF" 160965 305935 -8900 -4470 0 100 ""] +( + Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"] + Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"] + ElementLine [-1737 1837 1806 1837 600] + ElementLine [1806 -5643 1806 1837 600] + ElementLine [-1737 -5643 1806 -5643 600] + ElementLine [-1737 -5643 -1737 1837 600] + + ) + +Element["" "cap_0402" "C22" "100nF" 276628 377465 7938 -3069 0 100 ""] +( + Pad[3872 35 3872 35 1969 2000 2569 "1" "1" "square,edge2"] + Pad[-65 35 -65 35 1969 2000 2569 "2" "2" "square"] + ElementLine [-1837 -1737 -1837 1806 600] + ElementLine [-1837 1806 5643 1806 600] + ElementLine [5643 -1737 5643 1806 600] + ElementLine [-1837 -1737 5643 -1737 600] + + ) + +Element["" "cap_0402" "C24" "100nF" 230465 267935 -1400 -12470 0 100 ""] +( + Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"] + Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"] + ElementLine [-1737 1837 1806 1837 600] + ElementLine [1806 -5643 1806 1837 600] + ElementLine [-1737 -5643 1806 -5643 600] + ElementLine [-1737 -5643 -1737 1837 600] + + ) + +Element["" "cap_0402" "C8" "1uF" 193065 321465 8000 -3000 0 100 ""] +( + Pad[3872 35 3872 35 1969 1200 2569 "1" "1" "square,edge2"] + Pad[-65 35 -65 35 1969 1200 2569 "2" "2" "square"] + ElementLine [-1837 1806 -1837 -1737 600] + ElementLine [5643 1806 -1837 1806 600] + ElementLine [5643 -1737 5643 1806 600] + ElementLine [-1837 -1737 5643 -1737 600] + + ) + +Element["" "cap_0402" "C26" "1uF" 236037 268007 2956 -7470 0 100 ""] +( + Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"] + Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"] + ElementLine [-1737 1837 1806 1837 600] + ElementLine [1806 -5643 1806 1837 600] + ElementLine [-1737 -5643 1806 -5643 600] + ElementLine [-1737 -5643 -1737 1837 600] + + ) + +Element["" "cap_0402" "C20" "1uF" 198535 312128 3593 -1163 0 100 ""] +( + Pad[-35 3872 -35 3872 1969 1200 2569 "1" "1" "square"] + Pad[-35 -65 -35 -65 1969 1200 2569 "2" "2" "square"] + ElementLine [-1806 -1837 1737 -1837 600] + ElementLine [-1806 -1837 -1806 5643 600] + ElementLine [-1806 5643 1737 5643 600] + ElementLine [1737 -1837 1737 5643 600] + + ) + +Element["" "cap_0402" "C27" "1uF" 230535 273065 2530 -600 0 100 ""] +( + Pad[-35 3872 -35 3872 1969 1200 2569 "1" "1" "square"] + Pad[-35 -65 -35 -65 1969 1200 2569 "2" "2" "square"] + ElementLine [-1806 -1837 1737 -1837 600] + ElementLine [-1806 -1837 -1806 5643 600] + ElementLine [-1806 5643 1737 5643 600] + ElementLine [1737 -1837 1737 5643 600] + + ) + +Element["lock" "MOLEX8981" "J1" "unknown" 21000 54000 27500 -24000 0 100 "selected"] +( + Pin[0 0 10000 3000 11000 6000 "+5V" "4" "lock,edge2"] + Pin[20000 0 10000 3000 11000 6000 "GND" "3" "lock,edge2,thermal(0X,1X)"] + Pin[40000 0 10000 3000 11000 6000 "GND" "2" "lock,edge2,thermal(0X,1X)"] + Pin[60000 0 10000 3000 11000 6000 "+12V" "1" "lock,edge2"] + Pin[-10000 -10000 11000 3000 11000 10000 "LeftHole" "" "lock,edge2"] + Pin[70000 -10000 11000 3000 11000 10000 "RightHole" "" "lock,edge2"] + Pin[10000 -40000 16000 3000 16000 15700 "BackLeftHole" "" "lock,edge2"] + Pin[50000 -40000 16000 3000 16000 15700 "BackRightHole" "" "lock,edge2"] + ElementLine [-16000 9000 76000 9000 1000] + ElementLine [-16000 9000 -16000 -50000 1000] + ElementLine [-16000 -50000 76000 -50000 1000] + ElementLine [76000 -50000 76000 9000 1000] + + ) + +Element["lock" "HEADER50_2_RA" "J2" "unknown" 362000 44000 -119500 -24500 0 100 ""] +( + Pin[-240000 10000 6000 3000 6600 3800 "1" "1" "lock,edge2,thermal(0X,1X)"] + Pin[-240000 0 6000 3000 6600 3800 "2" "2" "lock,edge2"] + Pin[-230000 10000 6000 3000 6600 3800 "3" "3" "lock,edge2,thermal(0X,1X)"] + Pin[-230000 0 6000 3000 6600 3800 "4" "4" "lock,edge2"] + Pin[-220000 10000 6000 3000 6600 3800 "5" "5" "lock,edge2,thermal(0X,1X)"] + Pin[-220000 0 6000 3000 6600 3800 "6" "6" "lock,edge2"] + Pin[-210000 10000 6000 3000 6600 3800 "7" "7" "lock,edge2,thermal(0X,1X)"] + Pin[-210000 0 6000 3000 6600 3800 "8" "8" "lock,edge2"] + Pin[-200000 10000 6000 3000 6600 3800 "9" "9" "lock,edge2,thermal(0X,1X)"] + Pin[-200000 0 6000 3000 6600 3800 "10" "10" "lock,edge2"] + Pin[-190000 10000 6000 3000 6600 3800 "11" "11" "lock,edge2,thermal(0X,1X)"] + Pin[-190000 0 6000 3000 6600 3800 "12" "12" "lock,edge2"] + Pin[-180000 10000 6000 3000 6600 3800 "13" "13" "lock,edge2,thermal(0X,1X)"] + Pin[-180000 0 6000 3000 6600 3800 "14" "14" "lock,edge2"] + Pin[-170000 10000 6000 3000 6600 3800 "15" "15" "lock,edge2,thermal(0X,1X)"] + Pin[-170000 0 6000 3000 6600 3800 "16" "16" "lock,edge2"] + Pin[-160000 10000 6000 3000 6600 3800 "17" "17" "lock,edge2,thermal(0X,1X)"] + Pin[-160000 0 6000 3000 6600 3800 "18" "18" "lock,edge2"] + Pin[-150000 10000 6000 3000 6600 3800 "19" "19" "lock,edge2,thermal(0X,1X)"] + Pin[-150000 0 6000 3000 6600 3800 "20" "20" "lock,edge2,thermal(0X,1X)"] + Pin[-140000 10000 6000 3000 6600 3800 "21" "21" "lock,edge2,thermal(0X,1X)"] + Pin[-140000 0 6000 3000 6600 3800 "22" "22" "lock,edge2,thermal(0X,1X)"] + Pin[-130000 10000 6000 3000 6600 3800 "23" "23" "lock,edge2,thermal(0X,1X)"] + Pin[-130000 0 6000 3000 6600 3800 "24" "24" "lock,edge2,thermal(0X,1X)"] + Pin[-120000 10000 6000 3000 6600 3800 "25" "25" "lock,edge2"] + Pin[-120000 0 6000 3000 6600 3800 "26" "26" "lock,edge2"] + Pin[-110000 10000 6000 3000 6600 3800 "27" "27" "lock,edge2,thermal(0X,1X)"] + Pin[-110000 0 6000 3000 6600 3800 "28" "28" "lock,edge2,thermal(0X,1X)"] + Pin[-100000 10000 6000 3000 6600 3800 "29" "29" "lock,edge2,thermal(0X,1X)"] + Pin[-100000 0 6000 3000 6600 3800 "30" "30" "lock,edge2,thermal(0X,1X)"] + Pin[-90000 10000 6000 3000 6600 3800 "31" "31" "lock,edge2,thermal(0X,1X)"] + Pin[-90000 0 6000 3000 6600 3800 "32" "32" "lock,edge2"] + Pin[-80000 10000 6000 3000 6600 3800 "33" "33" "lock,edge2,thermal(0X,1X)"] + Pin[-80000 0 6000 3000 6600 3800 "34" "34" "lock,edge2,thermal(0X,1X)"] + Pin[-70000 10000 6000 3000 6600 3800 "35" "35" "lock,edge2,thermal(0X,1X)"] + Pin[-70000 0 6000 3000 6600 3800 "36" "36" "lock,edge2"] + Pin[-60000 10000 6000 3000 6600 3800 "37" "37" "lock,edge2,thermal(0X,1X)"] + Pin[-60000 0 6000 3000 6600 3800 "38" "38" "lock,edge2"] + Pin[-50000 10000 6000 3000 6600 3800 "39" "39" "lock,edge2,thermal(0X,1X)"] + Pin[-50000 0 6000 3000 6600 3800 "40" "40" "lock,edge2"] + Pin[-40000 10000 6000 3000 6600 3800 "41" "41" "lock,edge2,thermal(0X,1X)"] + Pin[-40000 0 6000 3000 6600 3800 "42" "42" "lock,edge2"] + Pin[-30000 10000 6000 3000 6600 3800 "43" "43" "lock,edge2,thermal(0X,1X)"] + Pin[-30000 0 6000 3000 6600 3800 "44" "44" "lock,edge2"] + Pin[-20000 10000 6000 3000 6600 3800 "45" "45" "lock,edge2,thermal(0X,1X)"] + Pin[-20000 0 6000 3000 6600 3800 "46" "46" "lock,edge2"] + Pin[-10000 10000 6000 3000 6600 3800 "47" "47" "lock,edge2,thermal(0X,1X)"] + Pin[-10000 0 6000 3000 6600 3800 "48" "48" "lock,edge2"] + Pin[0 10000 6000 3000 6600 3800 "49" "49" "lock,edge2,thermal(0X,1X)"] + Pin[0 0 6000 3000 6600 3800 "50" "50" "square,lock,edge2"] + ElementLine [-245000 -5000 5000 -5000 1000] + ElementLine [-245000 -5000 -245000 15000 1000] + ElementLine [-245000 15000 5000 15000 1000] + ElementLine [5000 -5000 5000 15000 1000] + ElementLine [-5000 -5000 -5000 5000 1000] + ElementLine [-5000 5000 5000 5000 1000] + ElementLine [5000 -40000 5000 -5000 1000] + ElementLine [-245000 -40000 5000 -40000 1000] + ElementLine [-245000 -40000 -245000 -5000 1000] + + ) + +Element["" "SMD_SIMPLE-80-50" "C5" "10uF" 339500 199000 -11300 -2600 0 100 ""] +( + Pad[-700 0 700 0 4500 3000 5100 "1" "1" "square"] + Pad[-700 -8000 700 -8000 4500 3000 5100 "2" "2" "square"] + ElementLine [-4400 3700 4400 3700 800] + ElementLine [4400 -11700 4400 3700 800] + ElementLine [-4400 -11700 4400 -11700 800] + ElementLine [-4400 -11700 -4400 3700 800] + + ) + +Element["" "SMD_SIMPLE-80-50" "C2" "10uF" 74500 163500 -12800 400 0 100 ""] +( + Pad[-700 0 700 0 4500 3000 5100 "1" "1" "square"] + Pad[-700 8000 700 8000 4500 3000 5100 "2" "2" "square"] + ElementLine [-4400 -3700 4400 -3700 800] + ElementLine [-4400 -3700 -4400 11700 800] + ElementLine [-4400 11700 4400 11700 800] + ElementLine [4400 -3700 4400 11700 800] + + ) + +Element["" "SMD_SIMPLE-80-50" "C7" "10uF" 306000 127500 7200 -2600 0 100 ""] +( + Pad[-700 0 700 0 4500 3000 5100 "1" "1" "square"] + Pad[-700 8000 700 8000 4500 3000 5100 "2" "2" "square"] + ElementLine [-4400 -3700 4400 -3700 800] + ElementLine [-4400 -3700 -4400 11700 800] + ElementLine [-4400 11700 4400 11700 800] + ElementLine [4400 -3700 4400 11700 800] + + ) + +Element["" "HEADER2_2" "J3" "unknown" 41000 80000 -7500 16500 0 100 ""] +( + Pin[0 0 6000 4400 6600 3800 "1" "1" "square"] + Pin[0 10000 6000 4200 6600 3800 "2" "2" ""] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [-5000 -5000 -5000 15000 1000] + ElementLine [-5000 15000 5000 15000 1000] + ElementLine [5000 -5000 5000 15000 1000] + ElementLine [-5000 -5000 -5000 5000 1000] + ElementLine [-5000 5000 5000 5000 1000] + + ) + +Element["" "cap_0402" "C10" "100nF" 231465 187372 8070 -6244 3 100 ""] +( + Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"] + Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"] + ElementLine [-1737 1837 1806 1837 600] + ElementLine [1806 -5643 1806 1837 600] + ElementLine [-1737 -5643 1806 -5643 600] + ElementLine [-1737 -5643 -1737 1837 600] + + ) + +Element["" "SO14" "U4" "unknown" 211000 181000 10500 -21500 0 100 ""] +( + Pad[15000 -13500 15000 -7000 2000 1800 3000 "A0" "1" "square"] + Pad[10000 -13500 10000 -7000 2000 1800 3000 "_Y0_" "2" "square"] + Pad[5000 -13500 5000 -7000 2000 1800 3000 "A1" "3" "square"] + Pad[0 -13500 0 -7000 2000 1800 3000 "_Y1_" "4" "square"] + Pad[-5000 -13500 -5000 -7000 2000 1800 3000 "A2" "5" "square"] + Pad[-10000 -13500 -10000 -7000 2000 1800 3000 "_Y2_" "6" "square"] + Pad[-15000 -13500 -15000 -7000 2000 1800 3000 "GND" "7" "square"] + Pad[-15000 7000 -15000 13500 2000 1800 3000 "_Y3_" "8" "square,edge2"] + Pad[-10000 7000 -10000 13500 2000 1800 3000 "A3" "9" "square,edge2"] + Pad[-5000 7000 -5000 13500 2000 1800 3000 "_Y4_" "10" "square,edge2"] + Pad[0 7000 0 13500 2000 1800 3000 "A4" "11" "square,edge2"] + Pad[5000 7000 5000 13500 2000 1800 3000 "_Y5_" "12" "square,edge2"] + Pad[10000 7000 10000 13500 2000 1800 3000 "A5" "13" "square,edge2"] + Pad[15000 7000 15000 13500 2000 1800 3000 "Vcc" "14" "square,edge2"] + ElementLine [-17000 -15500 17000 -15500 1000] + ElementLine [-17000 -15500 -17000 15500 1000] + ElementLine [-17000 15500 17000 15500 1000] + ElementLine [17000 -15500 17000 -2500 1000] + ElementLine [17000 2500 17000 15500 1000] + ElementArc [17000 0 2500 2500 270 180 1000] + + ) + +Element["" "SMD_SIMPLE-80-50" "C4" "10uF" 135000 239000 1700 -11600 0 100 ""] +( + Pad[0 -700 0 700 4500 3000 5100 "1" "1" "square"] + Pad[8000 -700 8000 700 4500 3000 5100 "2" "2" "square"] + ElementLine [-3700 -4400 -3700 4400 800] + ElementLine [-3700 4400 11700 4400 800] + ElementLine [11700 -4400 11700 4400 800] + ElementLine [-3700 -4400 11700 -4400 800] + + ) + +Element["" "SMD_SIMPLE-80-50" "C13" "10uF" 315000 293500 -4300 -20100 0 100 ""] +( + Pad[-700 0 700 0 4500 3000 5100 "1" "1" "square"] + Pad[-700 -8000 700 -8000 4500 3000 5100 "2" "2" "square"] + ElementLine [-4400 3700 4400 3700 800] + ElementLine [4400 -11700 4400 3700 800] + ElementLine [-4400 -11700 4400 -11700 800] + ElementLine [-4400 -11700 -4400 3700 800] + + ) + +Element["" "DPAK" "U6" "unknown" 348750 250250 -13500 -14500 0 100 ""] +( + Pad[-10750 8250 -10750 8250 26500 0 27500 "OUT" "2" "square,nopaste"] + Pad[-3250 750 -3250 750 11500 2000 12500 "OUT" "2" "square,edge2"] + Pad[-18250 750 -18250 750 11500 2000 12500 "OUT" "2" "square"] + Pad[-3250 15750 -3250 15750 11500 2000 12500 "OUT" "2" "square,edge2"] + Pad[-18250 15750 -18250 15750 11500 2000 12500 "OUT" "2" "square"] + Pad[-1750 31750 -1750 37250 6500 3200 7500 "IN" "3" "square,edge2"] + Pad[-19750 31750 -19750 37250 6500 3200 7500 "GND" "1" "square,edge2"] + ElementLine [5000 -7500 5000 44500 1000] + ElementLine [-26500 44500 5000 44500 1000] + ElementLine [-26500 -7500 -26500 44500 1000] + ElementLine [-26500 -7500 5000 -7500 1000] + ElementLine [-10500 28500 -10500 32500 1000] + + ) + +Element["" "SIP10" "R2" "unknown" 307000 147500 6500 -3500 0 100 ""] +( + Pin[0 0 6000 3000 6600 2800 "1" "1" "square,edge2,thermal(0X)"] + Pin[-10000 0 6000 3000 6600 2800 "2" "2" "edge2"] + Pin[-20000 0 6000 3000 6600 2800 "3" "3" "edge2"] + Pin[-30000 0 6000 3000 6600 2800 "4" "4" "edge2"] + Pin[-40000 0 6000 3000 6600 2800 "5" "5" "edge2"] + Pin[-50000 0 6000 3000 6600 2800 "6" "6" "edge2"] + Pin[-60000 0 6000 3000 6600 2800 "7" "7" "edge2"] + Pin[-70000 0 6000 3000 6600 2800 "8" "8" "edge2"] + Pin[-80000 0 6000 3000 6600 2800 "9" "9" "edge2"] + Pin[-90000 0 6000 3000 6600 2800 "10" "10" "edge2"] + ElementLine [-90000 -5000 0 -5000 2000] + ElementLine [-90000 5000 0 5000 2000] + ElementLine [-5000 -5000 -5000 5000 1000] + ElementArc [0 0 5000 5000 90 180 2000] + ElementArc [-90000 0 5000 5000 270 180 2000] + + ) + +Element["" "SMD_SIMPLE-80-50" "R5" "22Ω" 168500 330000 -11300 -3600 0 100 ""] +( + Pad[0 -700 0 700 4500 3000 5100 "1" "1" "square"] + Pad[8000 -700 8000 700 4500 3000 5100 "2" "2" "square"] + ElementLine [-3700 -4400 -3700 4400 800] + ElementLine [-3700 4400 11700 4400 800] + ElementLine [11700 -4400 11700 4400 800] + ElementLine [-3700 -4400 11700 -4400 800] + + ) + +Element["" "SMD_SIMPLE-80-50" "R4" "22Ω" 168439 319248 -12300 -3100 0 100 ""] +( + Pad[0 -700 0 700 4500 3000 5100 "1" "1" "square"] + Pad[8000 -700 8000 700 4500 3000 5100 "2" "2" "square"] + ElementLine [-3700 -4400 -3700 4400 800] + ElementLine [-3700 4400 11700 4400 800] + ElementLine [11700 4400 11700 -4400 800] + ElementLine [11700 -4400 -3700 -4400 800] + + ) + +Element["lock" "fci-10118192-0001LF" "J5" "unknown" 172788 382869 -24200 -8668 0 100 ""] +( + Pad[-63 -8271 -63 -4531 1575 1200 2175 "D+" "3" "square,lock"] + Pad[5055 -8271 5055 -4531 1575 1200 2175 "GND" "5" "square,lock"] + Pad[-5181 -8271 -5181 -4531 1575 1200 2175 "VCC" "1" "square,lock"] + Pad[2496 -8271 2496 -4531 1575 1200 2175 "ID" "4" "square,lock"] + Pad[-2622 -8271 -2622 -4531 1575 1200 2175 "D-" "2" "square,lock"] + Pad[-13252 -5909 -11284 -5909 6299 1200 6899 "" "6" "square,lock"] + Pad[11157 -5909 13126 -5909 6299 1200 6899 "" "7" "square,lock,edge2"] + Pad[-15024 3934 -15024 4328 7087 1200 7687 "" "8" "square,lock,edge2"] + Pad[-4788 4131 -4788 4131 7480 1200 8080 "" "9" "square,lock"] + Pad[4661 4131 4661 4131 7480 1200 8080 "" "10" "square,lock,edge2"] + Pad[14897 3934 14897 4328 7087 1200 7687 "" "11" "square,lock,edge2"] + ElementLine [-18567 9840 18441 9840 600] + ElementLine [-15024 9840 -15024 8462 600] + ElementLine [-15024 -3 -15024 -2168 600] + ElementLine [15094 9840 15094 8462 600] + ElementLine [15094 -3 15094 -2168 600] + ElementLine [-7741 -7877 -6559 -7877 600] + ElementLine [6236 -7877 7614 -7877 600] + + ) + +Element["" "SMD_SIMPLE-120-60" "F2" "500mA Hold" 157000 360000 7000 -3000 0 100 ""] +( + Pad[0 -500 0 500 6000 3000 6600 "1" "1" "square"] + Pad[-12000 -500 -12000 500 6000 3000 6600 "2" "2" "square"] + ElementLine [4500 -5000 4500 5000 800] + ElementLine [-16500 -5000 4500 -5000 800] + ElementLine [-16500 -5000 -16500 5000 800] + ElementLine [-16500 5000 4500 5000 800] + + ) + +Element["" "SMD_SIMPLE-120-60" "F1" "1.5A_Hold" 21000 72500 -12500 -3000 0 100 ""] +( + Pad[-500 0 500 0 6000 3000 6600 "1" "1" "square"] + Pad[-500 12000 500 12000 6000 3000 6600 "2" "2" "square"] + ElementLine [-5000 -4500 5000 -4500 800] + ElementLine [-5000 -4500 -5000 16500 800] + ElementLine [-5000 16500 5000 16500 800] + ElementLine [5000 -4500 5000 16500 800] + + ) + +Element["" "SMD_SIMPLE-80-50" "R12" "10K" 344500 322000 -2600 14800 1 100 ""] +( + Pad[-700 0 700 0 4500 3000 5100 "1" "1" "square"] + Pad[-700 -8000 700 -8000 4500 3000 5100 "2" "2" "square"] + ElementLine [-4400 3700 4400 3700 800] + ElementLine [4400 -11700 4400 3700 800] + ElementLine [-4400 -11700 4400 -11700 800] + ElementLine [-4400 -11700 -4400 3700 800] + + ) + +Element["" "SMD_SIMPLE-80-50" "R11" "10K" 334000 322000 -2600 13800 1 100 ""] +( + Pad[-700 0 700 0 4500 3000 5100 "1" "1" "square"] + Pad[-700 -8000 700 -8000 4500 3000 5100 "2" "2" "square"] + ElementLine [-4400 3700 4400 3700 800] + ElementLine [4400 -11700 4400 3700 800] + ElementLine [-4400 -11700 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Connect("J2-19") + Connect("J2-20") + Connect("J2-21") + Connect("J2-22") + Connect("J2-23") + Connect("J2-24") + Connect("J2-27") + Connect("J2-28") + Connect("J2-29") + Connect("J2-30") + Connect("J2-31") + Connect("J2-33") + Connect("J2-34") + Connect("J2-35") + Connect("J2-37") + Connect("J2-39") + Connect("J2-41") + Connect("J2-43") + Connect("J2-45") + Connect("J2-47") + Connect("J2-49") + Connect("J4-3") + Connect("J4-5") + Connect("J4-7") + Connect("J4-9") + Connect("J5-5") + Connect("J6-6") + Connect("J6-9") + Connect("U1-10") + Connect("U1-12") + Connect("U1-13") + Connect("U1-14") + Connect("U1-27") + Connect("U1-28") + Connect("U1-29") + Connect("U1-30") + Connect("U1-31") + Connect("U1-32") + Connect("U1-33") + Connect("U1-34") + Connect("U1-38") + Connect("U1-40") + Connect("U1-41") + Connect("U1-43") + Connect("U1-52") + Connect("U1-53") + Connect("U1-54") + Connect("U1-56") + Connect("U1-57") + Connect("U1-58") + Connect("U1-59") + Connect("U1-60") + Connect("U1-61") + Connect("U1-62") + Connect("U1-64") + Connect("U1-66") + Connect("U1-67") + Connect("U1-69") + Connect("U1-70") + Connect("U1-87") + Connect("U1-93") + Connect("U1-94") + Connect("U2-1") + Connect("U3-7") + Connect("U4-7") + Connect("U5-7") + Connect("U6-1") + ) + Net("I/O" "(unknown)") + ( + Connect("U1-71") + Connect("U3-1") + ) + Net("MSG" "(unknown)") + ( + Connect("U1-76") + Connect("U3-5") + ) + Net("REQ" "(unknown)") + ( + Connect("U1-72") + Connect("U3-13") + ) + Net("RST" "(unknown)") + ( + Connect("U1-77") + Connect("U3-9") + ) + Net("SD_DAT1" "(unknown)") + ( + Connect("J6-8") + Connect("R6-1") + Connect("U1-44") + ) + Net("SD_DAT2" "(unknown)") + ( + Connect("J6-1") + Connect("R12-1") + Connect("U1-49") + ) + Net("SD_MISO" "(unknown)") + ( + Connect("J6-7") + Connect("R7-1") + Connect("U1-45") + ) + Net("SD_MOSI" "(unknown)") + ( + Connect("J6-3") + Connect("R10-1") + Connect("U1-47") + ) + Net("SD_SCK" "(unknown)") + ( + Connect("J6-5") + Connect("R8-1") + Connect("U1-46") + ) + Net("SEL" "(unknown)") + ( + Connect("U1-74") + Connect("U3-11") + ) + Net("unnamed_net1" "(unknown)") + ( + Connect("J2-25") + ) + Net("unnamed_net2" "(unknown)") + ( + Connect("C1-2") + Connect("C5-2") + Connect("D1-1") + Connect("J2-26") + Connect("U2-3") + ) + Net("unnamed_net3" "(unknown)") + ( + Connect("J1-1") + ) + Net("unnamed_net4" "(unknown)") + ( + Connect("F1-1") + Connect("J1-4") + ) + Net("unnamed_net5" "(unknown)") + ( + Connect("J4-2") + Connect("U1-20") + ) + Net("unnamed_net6" "(unknown)") + ( + Connect("J4-4") + Connect("U1-21") + ) + Net("unnamed_net7" "(unknown)") + ( + Connect("J4-10") + Connect("U1-15") + ) + Net("unnamed_net8" "(unknown)") + ( + Connect("J4-8") + ) + Net("unnamed_net9" "(unknown)") + ( + Connect("J4-6") + Connect("U1-23") + ) + Net("unnamed_net10" "(unknown)") + ( + Connect("LED1-1") + Connect("R3-1") + ) + Net("unnamed_net11" "(unknown)") + ( + Connect("LED1-2") + Connect("U1-68") + ) + Net("unnamed_net12" "(unknown)") + ( + Connect("C27-2") + Connect("U1-63") + ) + Net("unnamed_net13" "(unknown)") + ( + Connect("C20-2") + Connect("U1-39") + Connect("U1-86") + ) + Net("unnamed_net14" "(unknown)") + ( + Connect("U1-11") + ) + Net("unnamed_net15" "(unknown)") + ( + Connect("U1-22") + ) + Net("unnamed_net16" "(unknown)") + ( + Connect("U1-24") + ) + Net("unnamed_net17" "(unknown)") + ( + Connect("U1-25") + ) + Net("unnamed_net18" "(unknown)") + ( + Connect("R4-2") + Connect("U1-35") + ) + Net("unnamed_net19" "(unknown)") + ( + Connect("R5-2") + Connect("U1-36") + ) + Net("unnamed_net20" "(unknown)") + ( + Connect("U1-42") + ) + Net("unnamed_net21" "(unknown)") + ( + Connect("U1-55") + ) + Net("unnamed_net22" "(unknown)") + ( + Connect("C7-2") + Connect("C14-2") + Connect("R1-1") + Connect("R2-1") + Connect("U2-2") + ) + Net("unnamed_net23" "(unknown)") + ( + Connect("D1-2") + Connect("J3-1") + ) + Net("unnamed_net24" "(unknown)") + ( + Connect("F2-1") + Connect("J5-1") + ) + Net("unnamed_net25" "(unknown)") + ( + Connect("D3-2") + Connect("F2-2") + ) + Net("unnamed_net26" "(unknown)") + ( + Connect("J5-4") + ) + Net("unnamed_net27" "(unknown)") + ( + Connect("J5-3") + Connect("R4-1") + ) + Net("unnamed_net28" "(unknown)") + ( + Connect("J5-2") + Connect("R5-1") + ) +) diff --git a/hardware/scsi2sd.sch b/hardware/scsi2sd.sch new file mode 100644 index 0000000..1457b8f --- /dev/null +++ b/hardware/scsi2sd.sch @@ -0,0 +1,2458 @@ +v 20110115 2 +C 30400 39400 1 0 0 header50-1.sym +{ +T 30650 50100 5 10 0 0 0 0 1 +device=HEADER50 +T 31000 49500 1 10 1 1 0 0 1 +refdes=J2 +T 30400 39400 5 10 0 0 0 0 1 +footprint=HEADER50_2_RA +} +C 31700 53400 1 180 0 MOLEX8981.sym +{ +T 30500 52700 5 10 1 1 180 6 1 +refdes=J1 +T 31300 51000 5 10 0 0 180 0 1 +device=MOLEX8981 +T 31300 50800 5 10 0 0 180 0 1 +footprint=MOLEX8981 +} +C 32100 51800 1 0 0 gnd-1.sym +{ +T 32100 51800 5 10 0 0 0 0 1 +net=GND:1 +} +C 29800 43700 1 0 0 gnd-1.sym +{ +T 29800 43700 5 10 0 0 0 0 1 +net=GND:1 +} +N 30400 44800 30400 49200 1 +N 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10 1 1 0 0 1 +device=USB +T 49500 45150 5 10 0 0 0 0 1 +footprint=fci-10118192-0001LF +} +N 53400 33200 50400 33200 4 +N 54100 33500 50400 33500 4 +C 50400 32800 1 0 0 nc-right-1.sym +{ +T 50500 33300 5 10 0 0 0 0 1 +value=NoConnection +T 50500 33500 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 50500 32300 1 0 1 gnd-1.sym +{ +T 50500 32300 5 10 0 0 0 6 1 +net=GND:1 +} +C 53500 33700 1 90 0 resistor-1.sym +{ +T 53100 34000 5 10 0 0 90 0 1 +device=RESISTOR +T 53200 33900 5 10 1 1 90 0 1 +refdes=R4 +T 53500 33700 5 10 0 0 90 0 1 +footprint=SMD_SIMPLE 80 50 +T 53700 33900 5 10 1 1 90 0 1 +value=22Ω +T 53500 33700 5 10 0 0 0 0 1 +description=1% precision required. +} +C 54200 33700 1 90 0 resistor-1.sym +{ +T 53800 34000 5 10 0 0 90 0 1 +device=RESISTOR +T 53900 33900 5 10 1 1 90 0 1 +refdes=R5 +T 54200 33700 5 10 0 0 90 0 1 +footprint=SMD_SIMPLE 80 50 +T 54400 33900 5 10 1 1 90 0 1 +value=22Ω +T 54200 33700 5 10 0 0 0 0 1 +documentation=1% precision required. +} +N 53400 33700 53400 33200 4 +N 54100 33700 54100 33500 4 +N 51600 33800 51300 33800 4 +N 33700 38300 33700 35100 4 +N 33300 35100 33900 35100 4 +N 35800 35700 35000 35700 4 +{ +T 35000 35700 5 10 1 1 0 0 1 +netname=\_DB7\_ +} +C 35800 35700 1 270 0 busripper-1.sym +{ +T 36200 35700 5 8 0 0 270 0 1 +device=none +} +N 35800 37800 35000 37800 4 +{ +T 35000 37800 5 10 1 1 0 0 1 +netname=\_DB0\_ +} +C 35800 37800 1 270 0 busripper-1.sym +{ +T 36200 37800 5 8 0 0 270 0 1 +device=none +} +N 35000 37500 35800 37500 4 +{ +T 35000 37500 5 10 1 1 0 0 1 +netname=\_DB1\_ +} +C 35800 37500 1 270 0 busripper-1.sym +{ +T 36200 37500 5 8 0 0 270 0 1 +device=none +} +N 35000 37200 35800 37200 4 +{ +T 35000 37200 5 10 1 1 0 0 1 +netname=\_DB2\_ +} +C 35800 37200 1 270 0 busripper-1.sym +{ +T 36200 37200 5 8 0 0 270 0 1 +device=none +} +N 35000 36900 35800 36900 4 +{ +T 35000 36900 5 10 1 1 0 0 1 +netname=\_DB3\_ +} +C 35800 36900 1 270 0 busripper-1.sym +{ +T 36200 36900 5 8 0 0 270 0 1 +device=none +} +N 35000 36600 35800 36600 4 +{ +T 35000 36600 5 10 1 1 0 0 1 +netname=\_DB4\_ +} +C 35800 36600 1 270 0 busripper-1.sym +{ +T 36200 36600 5 8 0 0 270 0 1 +device=none +} +N 35000 36300 35800 36300 4 +{ +T 35000 36300 5 10 1 1 0 0 1 +netname=\_DB5\_ +} +C 35800 36300 1 270 0 busripper-1.sym +{ +T 36200 36300 5 8 0 0 270 0 1 +device=none +} +N 35000 36000 35800 36000 4 +{ +T 35000 36000 5 10 1 1 0 0 1 +netname=\_DB6\_ +} +C 35800 36000 1 270 0 busripper-1.sym +{ +T 36200 36000 5 8 0 0 270 0 1 +device=none +} +N 35000 34600 35800 34600 4 +{ +T 35000 34600 5 10 1 1 0 0 1 +netname=\_ATN\_ +} +C 35800 34600 1 270 0 busripper-1.sym +{ +T 36200 34600 5 8 0 0 270 0 1 +device=none +} +N 35000 34300 35800 34300 4 +{ +T 35000 34300 5 10 1 1 0 0 1 +netname=\_BSY\_ +} +C 35800 34300 1 270 0 busripper-1.sym +{ +T 36200 34300 5 8 0 0 270 0 1 +device=none +} +N 35000 34000 35800 34000 4 +{ +T 35000 34000 5 10 1 1 0 0 1 +netname=\_ACK\_ +} +C 35800 34000 1 270 0 busripper-1.sym +{ +T 36200 34000 5 8 0 0 270 0 1 +device=none +} +N 35000 33700 35800 33700 4 +{ +T 35000 33700 5 10 1 1 0 0 1 +netname=\_RST\_ +} +C 35800 33700 1 270 0 busripper-1.sym +{ +T 36200 33700 5 8 0 0 270 0 1 +device=none +} +N 35000 33400 35800 33400 4 +{ +T 35000 33400 5 10 1 1 0 0 1 +netname=\_MSG\_ +} +C 35800 33400 1 270 0 busripper-1.sym +{ +T 36200 33400 5 8 0 0 270 0 1 +device=none +} +N 35000 33100 35800 33100 4 +{ +T 35000 33100 5 10 1 1 0 0 1 +netname=\_SEL\_ +} +C 35800 33100 1 270 0 busripper-1.sym +{ +T 36200 33100 5 8 0 0 270 0 1 +device=none +} +N 35000 32800 35800 32800 4 +{ +T 35000 32800 5 10 1 1 0 0 1 +netname=\_C/D\_ +} +C 35800 32800 1 270 0 busripper-1.sym +{ +T 36200 32800 5 8 0 0 270 0 1 +device=none +} +N 35000 32500 35800 32500 4 +{ +T 35000 32500 5 10 1 1 0 0 1 +netname=\_REQ\_ +} +C 35800 32500 1 270 0 busripper-1.sym +{ +T 36200 32500 5 8 0 0 270 0 1 +device=none +} +C 35000 35300 1 90 0 resistorpack10-1.sym +{ +T 33800 35400 5 10 0 0 90 0 1 +device=RESISTORPACK_10 +T 33800 35400 5 10 1 1 90 0 1 +refdes=R1 +T 35000 35300 5 10 0 0 0 0 1 +footprint=SIP10 +} +C 35000 32100 1 90 0 resistorpack10-1.sym +{ +T 33800 32200 5 10 0 0 90 0 1 +device=RESISTORPACK_10 +T 33800 32200 5 10 1 1 90 0 1 +refdes=R2 +T 35000 32100 5 10 0 0 0 0 1 +footprint=SIP10 +} +N 35000 35400 35800 35400 4 +{ +T 35000 35400 5 10 1 1 0 0 1 +netname=\_DBP\_ +} +C 35800 35400 1 270 0 busripper-1.sym +{ +T 36200 35400 5 8 0 0 270 0 1 +device=none +} +N 35000 32200 35800 32200 4 +{ +T 35000 32200 5 10 1 1 0 0 1 +netname=\_I/O\_ +} +C 35800 32200 1 270 0 busripper-1.sym +{ +T 36200 32200 5 8 0 0 270 0 1 +device=none +} +C 68100 32500 1 0 0 gnd-1.sym +C 68400 31300 1 0 0 gnd-1.sym +N 68200 32800 68500 32800 4 +C 68400 30700 1 0 0 wurth-microsd.sym +{ +T 69800 35300 5 10 1 1 0 6 1 +refdes=J6 +T 68800 35500 5 10 0 0 0 0 1 +device=wurth-693071010811 +T 68800 35700 5 10 0 0 0 0 1 +footprint=wurth-microsd +} +C 65100 37800 1 90 0 gnd-1.sym diff --git a/hardware/symbols/7406.sym b/hardware/symbols/7406.sym new file mode 100644 index 0000000..f12b0bc --- /dev/null +++ b/hardware/symbols/7406.sym @@ -0,0 +1,176 @@ +v 20060113 1 +P 100 2900 400 2900 1 0 0 +{ +T 300 2950 5 8 1 1 0 6 1 +pinnumber=1 +T 300 2850 5 8 0 1 0 8 1 +pinseq=1 +T 450 2900 9 8 1 1 0 0 1 +pinlabel=A0 +T 450 2900 5 8 0 1 0 2 1 +pintype=in +} +P 100 2500 400 2500 1 0 0 +{ +T 300 2550 5 8 1 1 0 6 1 +pinnumber=2 +T 300 2450 5 8 0 1 0 8 1 +pinseq=2 +T 450 2500 9 8 1 1 0 0 1 +pinlabel=\_Y0\_ +T 450 2500 5 8 0 1 0 2 1 +pintype=out +} +P 100 2100 400 2100 1 0 0 +{ +T 300 2150 5 8 1 1 0 6 1 +pinnumber=3 +T 300 2050 5 8 0 1 0 8 1 +pinseq=3 +T 450 2100 9 8 1 1 0 0 1 +pinlabel=A1 +T 450 2100 5 8 0 1 0 2 1 +pintype=in +} +P 100 1700 400 1700 1 0 0 +{ +T 300 1750 5 8 1 1 0 6 1 +pinnumber=4 +T 300 1650 5 8 0 1 0 8 1 +pinseq=4 +T 450 1700 9 8 1 1 0 0 1 +pinlabel=\_Y1\_ +T 450 1700 5 8 0 1 0 2 1 +pintype=out +} +P 100 1300 400 1300 1 0 0 +{ +T 300 1350 5 8 1 1 0 6 1 +pinnumber=5 +T 300 1250 5 8 0 1 0 8 1 +pinseq=5 +T 450 1300 9 8 1 1 0 0 1 +pinlabel=A2 +T 450 1300 5 8 0 1 0 2 1 +pintype=in +} +P 100 900 400 900 1 0 0 +{ +T 300 950 5 8 1 1 0 6 1 +pinnumber=6 +T 300 850 5 8 0 1 0 8 1 +pinseq=6 +T 450 900 9 8 1 1 0 0 1 +pinlabel=\_Y2\_ +T 450 900 5 8 0 1 0 2 1 +pintype=out +} +P 100 500 400 500 1 0 0 +{ +T 300 550 5 8 1 1 0 6 1 +pinnumber=7 +T 300 450 5 8 0 1 0 8 1 +pinseq=7 +T 450 500 9 8 1 1 0 0 1 +pinlabel=GND +T 450 500 5 8 0 1 0 2 1 +pintype=pwr +} +P 1700 2900 1400 2900 1 0 0 +{ +T 1500 2950 5 8 1 1 0 0 1 +pinnumber=14 +T 1500 2850 5 8 0 1 0 2 1 +pinseq=8 +T 1350 2900 9 8 1 1 0 6 1 +pinlabel=Vcc +T 1350 2900 5 8 0 1 0 8 1 +pintype=pwr +} +P 1700 2500 1400 2500 1 0 0 +{ +T 1500 2550 5 8 1 1 0 0 1 +pinnumber=13 +T 1500 2450 5 8 0 1 0 2 1 +pinseq=9 +T 1350 2500 9 8 1 1 0 6 1 +pinlabel=A5 +T 1350 2500 5 8 0 1 0 8 1 +pintype=in +} +P 1700 2100 1400 2100 1 0 0 +{ +T 1500 2150 5 8 1 1 0 0 1 +pinnumber=12 +T 1500 2050 5 8 0 1 0 2 1 +pinseq=10 +T 1350 2100 9 8 1 1 0 6 1 +pinlabel=\_Y5\_ +T 1350 2100 5 8 0 1 0 8 1 +pintype=out +} +P 1700 1700 1400 1700 1 0 0 +{ +T 1500 1750 5 8 1 1 0 0 1 +pinnumber=11 +T 1500 1650 5 8 0 1 0 2 1 +pinseq=11 +T 1350 1700 9 8 1 1 0 6 1 +pinlabel=A4 +T 1350 1700 5 8 0 1 0 8 1 +pintype=in +} +P 1700 1300 1400 1300 1 0 0 +{ +T 1500 1350 5 8 1 1 0 0 1 +pinnumber=10 +T 1500 1250 5 8 0 1 0 2 1 +pinseq=12 +T 1350 1300 9 8 1 1 0 6 1 +pinlabel=\_Y4\_ +T 1350 1300 5 8 0 1 0 8 1 +pintype=out +} +P 1700 900 1400 900 1 0 0 +{ +T 1500 950 5 8 1 1 0 0 1 +pinnumber=9 +T 1500 850 5 8 0 1 0 2 1 +pinseq=13 +T 1350 900 9 8 1 1 0 6 1 +pinlabel=A3 +T 1350 900 5 8 0 1 0 8 1 +pintype=in +} +P 1700 500 1400 500 1 0 0 +{ +T 1500 550 5 8 1 1 0 0 1 +pinnumber=8 +T 1500 450 5 8 0 1 0 2 1 +pinseq=14 +T 1350 500 9 8 1 1 0 6 1 +pinlabel=\_Y3\_ +T 1350 500 5 8 0 1 0 8 1 +pintype=out +} +B 400 100 1000 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1400 3400 8 10 1 1 0 6 1 +refdes=U? +T 400 3400 9 10 1 0 0 0 1 +7406 +T 400 3600 5 10 0 0 0 0 1 +device=7406 +T 400 3800 5 10 0 0 0 0 1 +footprint=SO14 +T 400 4000 5 10 0 0 0 0 1 +author=Michael McMaster +T 400 4200 5 10 0 0 0 0 1 +documentation=http://www.nxp.com/products/logic/buffers_inverters_drivers/N74F06D.html +T 400 4400 5 10 0 0 0 0 1 +description=Hex Inverter (Open Drain) +T 400 4600 5 10 0 0 0 0 1 +numslots=0 +T 400 4800 5 10 0 0 0 0 1 +dist-license=gpl3+ +T 400 5000 5 10 0 0 0 0 1 +use-license=gpl3+ diff --git a/hardware/symbols/7406.tragesym b/hardware/symbols/7406.tragesym new file mode 100644 index 0000000..e9d1d82 --- /dev/null +++ b/hardware/symbols/7406.tragesym @@ -0,0 +1,74 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)". That's useful for micro controller port labels +# rotate_labels rotates the pintext of top and bottom pins +# this is useful for large symbols like FPGAs with more than 100 pins +# sort_labels will sort the pins by it's labels +# useful for address ports, busses, ... +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1000 +pinwidthvertical=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# name is only some graphical text, not an attribute +# version specifies a gschem version. +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20060113 1 +name=7406 +device=7406 +refdes=U? +footprint=SO14 +description=Hex Inverter (Open Drain) +documentation=http://www.nxp.com/products/logic/buffers_inverters_drivers/N74F06D.html +author=Michael McMaster +dist-license=gpl3+ +use-license=gpl3+ +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# ---------------------------------------- +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets. +# net specifies the name of the net. Vcc or GND for example. +# label represents the pinlabel. +# negation lines can be added with "\_" example: \_enable\_ +# if you want to write a "\" use "\\" as escape sequence +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 in line l A0 +2 out line l \_Y0\_ +3 in line l A1 +4 out line l \_Y1\_ +5 in line l A2 +6 out line l \_Y2\_ +7 pwr line l GND GND +14 pwr line r Vcc +13 in line r A5 +12 out line r \_Y5\_ +11 in line r A4 +10 out line r \_Y4\_ +9 in line r A3 +8 out line r \_Y3\_ + diff --git a/hardware/symbols/CY8C53.sym b/hardware/symbols/CY8C53.sym new file mode 100644 index 0000000..e3e8510 --- /dev/null +++ b/hardware/symbols/CY8C53.sym @@ -0,0 +1,1126 @@ +v 20060113 1 +P 100 17900 400 17900 1 0 0 +{ +T 300 17950 5 8 1 1 0 6 1 +pinnumber=1 +T 300 17850 5 8 0 1 0 8 1 +pinseq=1 +T 450 17900 9 8 1 1 0 0 1 +pinlabel=P2[5] +T 450 17900 5 8 0 1 0 2 1 +pintype=io +} +P 100 17200 400 17200 1 0 0 +{ +T 300 17250 5 8 1 1 0 6 1 +pinnumber=2 +T 300 17150 5 8 0 1 0 8 1 +pinseq=2 +T 450 17200 9 8 1 1 0 0 1 +pinlabel=P2[6] +T 450 17200 5 8 0 1 0 2 1 +pintype=io +} +P 100 16500 400 16500 1 0 0 +{ +T 300 16550 5 8 1 1 0 6 1 +pinnumber=3 +T 300 16450 5 8 0 1 0 8 1 +pinseq=3 +T 450 16500 9 8 1 1 0 0 1 +pinlabel=P2[7] +T 450 16500 5 8 0 1 0 2 1 +pintype=io +} +P 100 15800 400 15800 1 0 0 +{ +T 300 15850 5 8 1 1 0 6 1 +pinnumber=4 +T 300 15750 5 8 0 1 0 8 1 +pinseq=4 +T 450 15800 9 8 1 1 0 0 1 +pinlabel=P12[4] +T 450 15800 5 8 0 1 0 2 1 +pintype=io +} +P 100 15100 400 15100 1 0 0 +{ +T 300 15150 5 8 1 1 0 6 1 +pinnumber=5 +T 300 15050 5 8 0 1 0 8 1 +pinseq=5 +T 450 15100 9 8 1 1 0 0 1 +pinlabel=P12[5] +T 450 15100 5 8 0 1 0 2 1 +pintype=io +} +P 100 14400 400 14400 1 0 0 +{ +T 300 14450 5 8 1 1 0 6 1 +pinnumber=6 +T 300 14350 5 8 0 1 0 8 1 +pinseq=6 +T 450 14400 9 8 1 1 0 0 1 +pinlabel=P6[4] +T 450 14400 5 8 0 1 0 2 1 +pintype=io +} +P 100 13700 400 13700 1 0 0 +{ +T 300 13750 5 8 1 1 0 6 1 +pinnumber=7 +T 300 13650 5 8 0 1 0 8 1 +pinseq=7 +T 450 13700 9 8 1 1 0 0 1 +pinlabel=P6[5] +T 450 13700 5 8 0 1 0 2 1 +pintype=io +} +P 100 13000 400 13000 1 0 0 +{ +T 300 13050 5 8 1 1 0 6 1 +pinnumber=8 +T 300 12950 5 8 0 1 0 8 1 +pinseq=8 +T 450 13000 9 8 1 1 0 0 1 +pinlabel=P6[6] +T 450 13000 5 8 0 1 0 2 1 +pintype=io +} +P 100 12300 400 12300 1 0 0 +{ +T 300 12350 5 8 1 1 0 6 1 +pinnumber=9 +T 300 12250 5 8 0 1 0 8 1 +pinseq=9 +T 450 12300 9 8 1 1 0 0 1 +pinlabel=P6[7] +T 450 12300 5 8 0 1 0 2 1 +pintype=io +} +P 100 11600 400 11600 1 0 0 +{ +T 300 11650 5 8 1 1 0 6 1 +pinnumber=10 +T 300 11550 5 8 0 1 0 8 1 +pinseq=10 +T 450 11600 9 8 1 1 0 0 1 +pinlabel=VSSD +T 450 11600 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 10900 400 10900 1 0 0 +{ +T 300 10950 5 8 1 1 0 6 1 +pinnumber=11 +T 300 10850 5 8 0 1 0 8 1 +pinseq=11 +T 450 10900 9 8 1 1 0 0 1 +pinlabel=NC +T 450 10900 5 8 0 1 0 2 1 +pintype=io +} +P 100 10200 400 10200 1 0 0 +{ +T 300 10250 5 8 1 1 0 6 1 +pinnumber=12 +T 300 10150 5 8 0 1 0 8 1 +pinseq=12 +T 450 10200 9 8 1 1 0 0 1 +pinlabel=VSSD +T 450 10200 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 9500 400 9500 1 0 0 +{ +T 300 9550 5 8 1 1 0 6 1 +pinnumber=13 +T 300 9450 5 8 0 1 0 8 1 +pinseq=13 +T 450 9500 9 8 1 1 0 0 1 +pinlabel=VSSD +T 450 9500 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 8800 400 8800 1 0 0 +{ +T 300 8850 5 8 1 1 0 6 1 +pinnumber=14 +T 300 8750 5 8 0 1 0 8 1 +pinseq=14 +T 450 8800 9 8 1 1 0 0 1 +pinlabel=VSSD +T 450 8800 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 8100 400 8100 1 0 0 +{ +T 300 8150 5 8 1 1 0 6 1 +pinnumber=15 +T 300 8050 5 8 0 1 0 8 1 +pinseq=15 +T 450 8100 9 8 1 1 0 0 1 +pinlabel=\_XRES\_ +T 450 8100 5 8 0 1 0 2 1 +pintype=in +} +P 100 7400 400 7400 1 0 0 +{ +T 300 7450 5 8 1 1 0 6 1 +pinnumber=16 +T 300 7350 5 8 0 1 0 8 1 +pinseq=16 +T 450 7400 9 8 1 1 0 0 1 +pinlabel=P5[0] +T 450 7400 5 8 0 1 0 2 1 +pintype=io +} +P 100 6700 400 6700 1 0 0 +{ +T 300 6750 5 8 1 1 0 6 1 +pinnumber=17 +T 300 6650 5 8 0 1 0 8 1 +pinseq=17 +T 450 6700 9 8 1 1 0 0 1 +pinlabel=P5[1] +T 450 6700 5 8 0 1 0 2 1 +pintype=io +} +P 100 6000 400 6000 1 0 0 +{ +T 300 6050 5 8 1 1 0 6 1 +pinnumber=18 +T 300 5950 5 8 0 1 0 8 1 +pinseq=18 +T 450 6000 9 8 1 1 0 0 1 +pinlabel=P5[2] +T 450 6000 5 8 0 1 0 2 1 +pintype=io +} +P 100 5300 400 5300 1 0 0 +{ +T 300 5350 5 8 1 1 0 6 1 +pinnumber=19 +T 300 5250 5 8 0 1 0 8 1 +pinseq=19 +T 450 5300 9 8 1 1 0 0 1 +pinlabel=P5[3] +T 450 5300 5 8 0 1 0 2 1 +pintype=io +} +P 100 4600 400 4600 1 0 0 +{ +T 300 4650 5 8 1 1 0 6 1 +pinnumber=20 +T 300 4550 5 8 0 1 0 8 1 +pinseq=20 +T 450 4600 9 8 1 1 0 0 1 +pinlabel=SWDIO,P1[0] +T 450 4600 5 8 0 1 0 2 1 +pintype=io +} +P 100 3900 400 3900 1 0 0 +{ +T 300 3950 5 8 1 1 0 6 1 +pinnumber=21 +T 300 3850 5 8 0 1 0 8 1 +pinseq=21 +T 450 3900 9 8 1 1 0 0 1 +pinlabel=SWDCK,P1[1] +T 450 3900 5 8 0 1 0 2 1 +pintype=io +} +P 100 3200 400 3200 1 0 0 +{ +T 300 3250 5 8 1 1 0 6 1 +pinnumber=22 +T 300 3150 5 8 0 1 0 8 1 +pinseq=22 +T 450 3200 9 8 1 1 0 0 1 +pinlabel=P1[2] +T 450 3200 5 8 0 1 0 2 1 +pintype=io +} +P 100 2500 400 2500 1 0 0 +{ +T 300 2550 5 8 1 1 0 6 1 +pinnumber=23 +T 300 2450 5 8 0 1 0 8 1 +pinseq=23 +T 450 2500 9 8 1 1 0 0 1 +pinlabel=SWV,P1[3] +T 450 2500 5 8 0 1 0 2 1 +pintype=io +} +P 100 1800 400 1800 1 0 0 +{ +T 300 1850 5 8 1 1 0 6 1 +pinnumber=24 +T 300 1750 5 8 0 1 0 8 1 +pinseq=24 +T 450 1800 9 8 1 1 0 0 1 +pinlabel=P1[4] +T 450 1800 5 8 0 1 0 2 1 +pintype=io +} +P 100 1100 400 1100 1 0 0 +{ +T 300 1150 5 8 1 1 0 6 1 +pinnumber=25 +T 300 1050 5 8 0 1 0 8 1 +pinseq=25 +T 450 1100 9 8 1 1 0 0 1 +pinlabel=P1[5] +T 450 1100 5 8 0 1 0 2 1 +pintype=io +} +P 1000 100 1000 400 1 0 0 +{ +T 950 300 5 8 1 1 90 6 1 +pinnumber=26 +T 1050 300 5 8 0 1 90 8 1 +pinseq=26 +T 1000 450 9 8 1 1 90 0 1 +pinlabel=VDDIO1 +T 1000 450 5 8 0 1 90 2 1 +pintype=pwr +} +P 1700 100 1700 400 1 0 0 +{ +T 1650 300 5 8 1 1 90 6 1 +pinnumber=27 +T 1750 300 5 8 0 1 90 8 1 +pinseq=27 +T 1700 450 9 8 1 1 90 0 1 +pinlabel=P1[6] +T 1700 450 5 8 0 1 90 2 1 +pintype=io +} +P 2400 100 2400 400 1 0 0 +{ +T 2350 300 5 8 1 1 90 6 1 +pinnumber=28 +T 2450 300 5 8 0 1 90 8 1 +pinseq=28 +T 2400 450 9 8 1 1 90 0 1 +pinlabel=P1[7] +T 2400 450 5 8 0 1 90 2 1 +pintype=io +} +P 3100 100 3100 400 1 0 0 +{ +T 3050 300 5 8 1 1 90 6 1 +pinnumber=29 +T 3150 300 5 8 0 1 90 8 1 +pinseq=29 +T 3100 450 9 8 1 1 90 0 1 +pinlabel=P12[6] +T 3100 450 5 8 0 1 90 2 1 +pintype=io +} +P 3800 100 3800 400 1 0 0 +{ +T 3750 300 5 8 1 1 90 6 1 +pinnumber=30 +T 3850 300 5 8 0 1 90 8 1 +pinseq=30 +T 3800 450 9 8 1 1 90 0 1 +pinlabel=P12[7] +T 3800 450 5 8 0 1 90 2 1 +pintype=io +} +P 4500 100 4500 400 1 0 0 +{ +T 4450 300 5 8 1 1 90 6 1 +pinnumber=31 +T 4550 300 5 8 0 1 90 8 1 +pinseq=31 +T 4500 450 9 8 1 1 90 0 1 +pinlabel=P5[4] +T 4500 450 5 8 0 1 90 2 1 +pintype=io +} +P 5200 100 5200 400 1 0 0 +{ +T 5150 300 5 8 1 1 90 6 1 +pinnumber=32 +T 5250 300 5 8 0 1 90 8 1 +pinseq=32 +T 5200 450 9 8 1 1 90 0 1 +pinlabel=P5[5] +T 5200 450 5 8 0 1 90 2 1 +pintype=io +} +P 5900 100 5900 400 1 0 0 +{ +T 5850 300 5 8 1 1 90 6 1 +pinnumber=33 +T 5950 300 5 8 0 1 90 8 1 +pinseq=33 +T 5900 450 9 8 1 1 90 0 1 +pinlabel=P5[6] +T 5900 450 5 8 0 1 90 2 1 +pintype=io +} +P 6600 100 6600 400 1 0 0 +{ +T 6550 300 5 8 1 1 90 6 1 +pinnumber=34 +T 6650 300 5 8 0 1 90 8 1 +pinseq=34 +T 6600 450 9 8 1 1 90 0 1 +pinlabel=P5[7] +T 6600 450 5 8 0 1 90 2 1 +pintype=io +} +P 7300 100 7300 400 1 0 0 +{ +T 7250 300 5 8 1 1 90 6 1 +pinnumber=35 +T 7350 300 5 8 0 1 90 8 1 +pinseq=35 +T 7300 450 9 8 1 1 90 0 1 +pinlabel=SWDIO,USB D+ +T 7300 450 5 8 0 1 90 2 1 +pintype=io +} +P 8000 100 8000 400 1 0 0 +{ +T 7950 300 5 8 1 1 90 6 1 +pinnumber=36 +T 8050 300 5 8 0 1 90 8 1 +pinseq=36 +T 8000 450 9 8 1 1 90 0 1 +pinlabel=SWDCK,USB D- +T 8000 450 5 8 0 1 90 2 1 +pintype=io +} +P 8700 100 8700 400 1 0 0 +{ +T 8650 300 5 8 1 1 90 6 1 +pinnumber=37 +T 8750 300 5 8 0 1 90 8 1 +pinseq=37 +T 8700 450 9 8 1 1 90 0 1 +pinlabel=VDDD +T 8700 450 5 8 0 1 90 2 1 +pintype=pwr +} +P 9400 100 9400 400 1 0 0 +{ +T 9350 300 5 8 1 1 90 6 1 +pinnumber=38 +T 9450 300 5 8 0 1 90 8 1 +pinseq=38 +T 9400 450 9 8 1 1 90 0 1 +pinlabel=VSSD +T 9400 450 5 8 0 1 90 2 1 +pintype=pwr +} +P 10100 100 10100 400 1 0 0 +{ +T 10050 300 5 8 1 1 90 6 1 +pinnumber=39 +T 10150 300 5 8 0 1 90 8 1 +pinseq=39 +T 10100 450 9 8 1 1 90 0 1 +pinlabel=VCCD +T 10100 450 5 8 0 1 90 2 1 +pintype=pwr +} +P 10800 100 10800 400 1 0 0 +{ +T 10750 300 5 8 1 1 90 6 1 +pinnumber=40 +T 10850 300 5 8 0 1 90 8 1 +pinseq=40 +T 10800 450 9 8 1 1 90 0 1 +pinlabel=NC +T 10800 450 5 8 0 1 90 2 1 +pintype=io +} +P 11500 100 11500 400 1 0 0 +{ +T 11450 300 5 8 1 1 90 6 1 +pinnumber=41 +T 11550 300 5 8 0 1 90 8 1 +pinseq=41 +T 11500 450 9 8 1 1 90 0 1 +pinlabel=NC +T 11500 450 5 8 0 1 90 2 1 +pintype=io +} +P 12200 100 12200 400 1 0 0 +{ +T 12150 300 5 8 1 1 90 6 1 +pinnumber=42 +T 12250 300 5 8 0 1 90 8 1 +pinseq=42 +T 12200 525 9 8 1 1 90 0 1 +pinlabel=MHZ XTAL XO +T 12200 525 5 8 0 1 90 2 1 +pintype=clk +} +L 12200 500 12275 400 3 0 0 0 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14300 18550 5 8 0 1 90 8 1 +pintype=io +} +P 15000 18900 15000 18600 1 0 0 +{ +T 14950 18700 5 8 1 1 90 0 1 +pinnumber=80 +T 15050 18700 5 8 0 1 90 2 1 +pinseq=96 +T 15000 18550 9 8 1 1 90 6 1 +pinlabel=P4[2] +T 15000 18550 5 8 0 1 90 8 1 +pintype=io +} +P 15700 18900 15700 18600 1 0 0 +{ +T 15650 18700 5 8 1 1 90 0 1 +pinnumber=79 +T 15750 18700 5 8 0 1 90 2 1 +pinseq=97 +T 15700 18550 9 8 1 1 90 6 1 +pinlabel=P0[7] +T 15700 18550 5 8 0 1 90 8 1 +pintype=io +} +P 16400 18900 16400 18600 1 0 0 +{ +T 16350 18700 5 8 1 1 90 0 1 +pinnumber=78 +T 16450 18700 5 8 0 1 90 2 1 +pinseq=98 +T 16400 18550 9 8 1 1 90 6 1 +pinlabel=P0[6] +T 16400 18550 5 8 0 1 90 8 1 +pintype=io +} +P 17100 18900 17100 18600 1 0 0 +{ +T 17050 18700 5 8 1 1 90 0 1 +pinnumber=77 +T 17150 18700 5 8 0 1 90 2 1 +pinseq=99 +T 17100 18550 9 8 1 1 90 6 1 +pinlabel=P0[5] +T 17100 18550 5 8 0 1 90 8 1 +pintype=io +} +P 17800 18900 17800 18600 1 0 0 +{ +T 17750 18700 5 8 1 1 90 0 1 +pinnumber=76 +T 17850 18700 5 8 0 1 90 2 1 +pinseq=100 +T 17800 18550 9 8 1 1 90 6 1 +pinlabel=P0[4] +T 17800 18550 5 8 0 1 90 8 1 +pintype=io +} +B 400 400 18000 18200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 18400 18700 8 10 1 1 0 6 1 +refdes=U? +T 9200 9400 9 10 1 0 0 0 1 +CY8C53 +T 9200 9700 5 10 0 0 0 0 1 +device=CY8C53 +T 9200 9900 5 10 0 0 0 0 1 +footprint=TQFP100_14 +T 9200 10100 5 10 0 0 0 0 1 +author=Michael McMaster +T 9200 10300 5 10 0 0 0 0 1 +documentation=http://www.cypress.com/?id=2233 +T 9200 10500 5 10 0 0 0 0 1 +description=Cypress PSoC5 CY8C53 +T 9200 10700 5 10 0 0 0 0 1 +numslots=0 +T 9200 10900 5 10 0 0 0 0 1 +dist-license=gpl3+ +T 9200 11100 5 10 0 0 0 0 1 +use-license=gpl3+ diff --git a/hardware/symbols/CY8C53.tragesym b/hardware/symbols/CY8C53.tragesym new file mode 100644 index 0000000..f8d4915 --- /dev/null +++ b/hardware/symbols/CY8C53.tragesym @@ -0,0 +1,164 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)". That's useful for micro controller port labels +# rotate_labels rotates the pintext of top and bottom pins +# this is useful for large symbols like FPGAs with more than 100 pins +# sort_labels will sort the pins by it's labels +# useful for address ports, busses, ... +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=18000 +pinwidthvertical=700 +pinwidthhorizontal=700 + +[geda_attr] +# name will be printed in the top of the symbol +# name is only some graphical text, not an attribute +# version specifies a gschem version. +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20060113 1 +name=CY8C53 +device=CY8C53 +refdes=U? +footprint=TQFP100_14 +description=Cypress PSoC5 CY8C53 +documentation=http://www.cypress.com/?id=2233 +author=Michael McMaster +dist-license=gpl3+ +use-license=gpl3+ +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# ---------------------------------------- +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets. +# net specifies the name of the net. Vcc or GND for example. +# label represents the pinlabel. +# negation lines can be added with "\_" example: \_enable\_ +# if you want to write a "\" use "\\" as escape sequence +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 io line l P2[5] +2 io line l P2[6] +3 io line l P2[7] +4 io line l P12[4] +5 io line l P12[5] +6 io line l P6[4] +7 io line l P6[5] +8 io line l P6[6] +9 io line l P6[7] +10 pwr line l GND VSSD +11 io line l NC +12 pwr line l GND VSSD +13 pwr line l GND VSSD +14 pwr line l GND VSSD +15 in line l \_XRES\_ +16 io line l P5[0] +17 io line l P5[1] +18 io line l P5[2] +19 io line l P5[3] +20 io line l SWDIO,P1[0] +21 io line l SWDCK,P1[1] +22 io line l P1[2] +23 io line l SWV,P1[3] +24 io line l P1[4] +25 io line l P1[5] + + +26 pwr line b VDDIO1 +27 io line b P1[6] +28 io line b P1[7] +29 io line b P12[6] +30 io line b P12[7] +31 io line b P5[4] +32 io line b P5[5] +33 io line b P5[6] +34 io line b P5[7] +35 io line b SWDIO,USB D+ +36 io line b SWDCK,USB D- +37 pwr line b VDDD +38 pwr line b GND VSSD +39 pwr line b VCCD +40 io line b NC +41 io line b NC +42 clk clk b MHZ XTAL XO +43 clk clk b MHZ XTAL XI +44 io line b P3[0] +45 io line b P3[1] +46 io line b P3[2] +47 io line b P3[3] +48 io line b P3[4] +49 io line b P3[5] +50 pwr line b VDDIO3 + +75 pwr line r VDDIO0 +74 io line r P0[3] +73 io line r P0[2] +72 io line r P0[1] +71 io line r P0[0] +70 io line r P4[1] +69 io line r P4[0] +68 io line r P12[3] +67 io line r P12[2] +66 pwr line r GND VSSD +65 pwr line r VDDA +64 pwr line r GND VSSA +63 pwr line r VCCA +62 io line r NC +61 io line r NC +60 io line r NC +59 io line r NC +58 io line r NC +57 io line r NC +56 io line r P15[3],KHZ XTAL XI +55 io line r P15[2],KHZ XTAL XO +54 io line r P12[1] +53 io line r P12[0] +52 io line r P3[7] +51 io line r P3[6] + +100 pwr line t VDDIO2 +99 io line t P2[4] +98 io line t P2[3] +97 io line t P2[2] +96 io line t P2[1] +95 io line t P2[0] +94 io line t P15[5] +93 io line t P15[4] +92 io line t P6[3] +91 io line t P6[2] +90 io line t P6[1] +89 io line t P6[0] +88 pwr line t VDDD +87 pwr line t GND VSSD +86 pwr line t VCCD +85 io line t P4[7] +84 io line t P4[6] +83 io line t P4[5] +82 io line t P4[4] +81 io line t P4[3] +80 io line t P4[2] +79 io line t P0[7] +78 io line t P0[6] +77 io line t P0[5] +76 io line t P0[4] + diff --git a/hardware/symbols/DO-41-vert.fp b/hardware/symbols/DO-41-vert.fp new file mode 100644 index 0000000..c36323c --- /dev/null +++ b/hardware/symbols/DO-41-vert.fp @@ -0,0 +1,10 @@ +Element[0x00000000 "DIO__DO-41-vertical.fp" "D?" "" 172500 127500 -9900 +6050 0 100 0x00000000] +( + Pin[-6200 0 9500 2000 10700 4200 "" "1" 0x0101] + Pin[6200 0 9500 2000 10700 4200 "" "2" 0x01] + ElementLine [-11450 -5300 6200 -5300 1000] + ElementLine [-11450 5300 6200 5300 1000] + ElementLine [-11450 -5300 -11450 5300 1000] + ElementArc [6200 0 5300 5300 90 180 1000] + ) diff --git a/hardware/symbols/DO-41.fp b/hardware/symbols/DO-41.fp new file mode 100644 index 0000000..abd27d5 --- /dev/null +++ b/hardware/symbols/DO-41.fp @@ -0,0 +1,10 @@ +Element[0x00000000 "DO-41" "D?" "" 172500 127500 -9900 6050 0 100 0x00000000] +( + Pin[-21250 0 9500 2000 10700 4200 "" "1" 0x0101] + Pin[21250 0 9500 2000 10700 4200 "" "2" 0x01] + ElementLine [-9850 -5050 9850 -5050 1000] + ElementLine [9850 -5050 9850 5050 1000] + ElementLine [9850 5050 -9850 5050 1000] + ElementLine [-9850 5050 -9850 -5050 1000] + ElementLine [-6800 -5050 -6800 5050 1000] + ) diff --git a/hardware/symbols/DPAK.fp b/hardware/symbols/DPAK.fp new file mode 100644 index 0000000..6422904 --- /dev/null +++ b/hardware/symbols/DPAK.fp @@ -0,0 +1,20 @@ + +Element["" "" "" "" 12750 8250 0 0 0 100 ""] +( + Pad[8250 10750 8250 10750 26500 2000 27500 "2" "2" "square,nopaste"] + + Pad[750 3250 750 3250 11500 2000 12500 "2_1" "2" "square"] + Pad[750 18250 750 18250 11500 2000 12500 "2_2" "2" "square"] + Pad[15750 3250 15750 3250 11500 2000 12500 "2_3" "2" "square,edge2"] + Pad[15750 18250 15750 18250 11500 2000 12500 "2_4" "2" "square,edge2"] + + Pad[31750 1750 37250 1750 6500 2000 7500 "3" "3" "square,edge2"] + Pad[31750 19750 37250 19750 6500 2000 7500 "1" "1" "square,edge2"] + ElementLine [-7500 -5000 44500 -5000 1000] + ElementLine [44500 -5000 44500 26500 1000] + ElementLine [44500 26500 -7500 26500 1000] + ElementLine [-7500 26500 -7500 -5000 1000] + ElementLine [28500 10500 32500 10500 1000] + + ) + diff --git a/hardware/symbols/FCI-10067847.fp b/hardware/symbols/FCI-10067847.fp new file mode 100644 index 0000000..32c2824 --- /dev/null +++ b/hardware/symbols/FCI-10067847.fp @@ -0,0 +1,66 @@ + +Element["" "FCI SD Card 10067847" "" "" 88425 50698 0 0 0 100 ""] +( + Pin[-56138 64233 7906 2 6906 5906 "" "" ""] + Pin[39138 64233 7906 2 6906 5906 "" "" ""] + Pad[-62044 53997 -62044 57934 4724 2 4725 "GND_SHIELD" "12" "square,edge2"] + Pad[28311 -32027 28311 -30451 4330 2 4331 "PIN9" "9" "square"] + Pad[-60074 -32224 -60074 -30254 3937 2 3938 "WP" "10" "square"] + Pad[-46886 -32026 -46886 -30452 4331 2 4332 "PIN8" "8" "square"] + Pad[-40192 -32026 -40192 -30452 4331 2 4332 "PIN7" "7" "square"] + Pad[-30744 -32027 -30744 -30451 4330 2 4331 "PIN6" "6" "square"] + Pad[-20902 -32026 -20902 -30452 4331 2 4332 "PIN5" "5" "square"] + Pad[-11059 -32027 -11059 -30451 4330 2 4331 "PIN4" "4" "square"] + Pad[8626 -32027 8626 -30451 4330 2 4331 "PIN2" "2" "square"] + Pad[2130 -32224 2130 -30254 3937 2 3938 "CD" "11" "square"] + Pad[-4366 -32027 -4366 -30451 4330 2 4331 "PIN3" "3" "square"] + Pad[18468 -32026 18468 -30452 4331 2 4332 "PIN1" "1" "square"] + Pad[48193 49272 48193 53210 4724 2 4725 "GND_SHIELD" "13" "square,edge2"] + ElementLine [50162 -29074 50162 45730 800] + ElementLine [50162 83918 50162 56843 800] + ElementLine [-63666 50697 -63666 -29082 800] + ElementLine [-63666 83918 -63666 61701 800] + ElementLine [-56592 -29082 -50304 -29082 800] + ElementLine [31841 -29074 31833 -29082 800] + ElementLine [50162 -29074 31841 -29074 800] + ElementLine [50162 83918 -63618 83918 800] + ElementLine [-49051 -7814 30476 -7814 800] + ElementLine [30476 -7814 30476 12265 800] + ElementLine [30476 12265 -49051 12265 800] + ElementLine [-49051 12265 -49051 -7814 800] + ElementLine [-46767 -4716 -46767 10218 800] + ElementLine [-46767 10218 28296 10218 800] + ElementLine [28296 10218 28296 -5895 800] + ElementLine [28296 -5895 -44016 -5895 800] + ElementLine [-44016 -5895 -44016 7860 800] + ElementLine [-44016 7860 25545 7860 800] + ElementLine [25545 7860 25545 -3930 800] + ElementLine [25545 -3930 -41658 -3930 800] + ElementLine [-41658 -3930 -41658 5502 800] + ElementLine [-41658 5502 23187 5502 800] + ElementLine [23187 5502 23187 -1965 800] + ElementLine [23187 -1965 -38907 -1965 800] + ElementLine [-38907 -1965 -38907 3537 800] + ElementLine [-38907 3537 20829 3537 800] + ElementLine [20829 3537 20829 0 800] + ElementLine [20829 0 -36942 0 800] + ElementLine [-36942 0 -36942 1965 800] + ElementLine [-36942 1965 18471 1965 800] + ElementLine [18471 1965 18864 1572 800] + ElementLine [-66375 7146 -61650 7146 800] + ElementLine [-61650 7146 -61650 31782 800] + ElementLine [-61650 31782 -61701 31833 800] + ElementLine [-61701 31833 -66417 31833 800] + ElementLine [-66417 31833 -66417 7188 800] + ElementLine [-66417 7188 -66375 7146 800] + ElementLine [-65631 8253 -62487 11397 800] + ElementLine [-62487 11397 -65631 14541 800] + ElementLine [-65631 14541 -62487 17685 800] + ElementLine [-62487 17685 -65631 20829 800] + ElementLine [-65631 20829 -62487 23973 800] + ElementLine [-62487 23973 -65631 27117 800] + ElementLine [-65631 27117 -62487 30261 800] + ElementLine [-62487 30261 -62880 30261 800] + ElementLine [-62880 30261 -64452 31833 800] + + ) diff --git a/hardware/symbols/FCI-10067847.sym b/hardware/symbols/FCI-10067847.sym new file mode 100644 index 0000000..e93a9fa --- /dev/null +++ b/hardware/symbols/FCI-10067847.sym @@ -0,0 +1,156 @@ +v 20060113 1 +P 100 4900 400 4900 1 0 0 +{ +T 300 4950 5 8 1 1 0 6 1 +pinnumber=9 +T 300 4850 5 8 0 1 0 8 1 +pinseq=1 +T 450 4900 9 8 1 1 0 0 1 +pinlabel=DAT2 +T 450 4900 5 8 0 1 0 2 1 +pintype=io +} +P 100 4500 400 4500 1 0 0 +{ +T 300 4550 5 8 1 1 0 6 1 +pinnumber=1 +T 300 4450 5 8 0 1 0 8 1 +pinseq=2 +T 450 4500 9 8 1 1 0 0 1 +pinlabel=DAT3,\_CS\_ +T 450 4500 5 8 0 1 0 2 1 +pintype=io +} +P 100 4100 400 4100 1 0 0 +{ +T 300 4150 5 8 1 1 0 6 1 +pinnumber=2 +T 300 4050 5 8 0 1 0 8 1 +pinseq=3 +T 450 4100 9 8 1 1 0 0 1 +pinlabel=CMD/DI,MOSI +T 450 4100 5 8 0 1 0 2 1 +pintype=io +} +P 100 3700 400 3700 1 0 0 +{ +T 300 3750 5 8 1 1 0 6 1 +pinnumber=3 +T 300 3650 5 8 0 1 0 8 1 +pinseq=4 +T 450 3700 9 8 1 1 0 0 1 +pinlabel=GND +T 450 3700 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 3300 400 3300 1 0 0 +{ +T 300 3350 5 8 1 1 0 6 1 +pinnumber=4 +T 300 3250 5 8 0 1 0 8 1 +pinseq=5 +T 450 3300 9 8 1 1 0 0 1 +pinlabel=Vcc +T 450 3300 5 8 0 1 0 2 1 +pintype=io +} +P 100 2900 400 2900 1 0 0 +{ +T 300 2950 5 8 1 1 0 6 1 +pinnumber=5 +T 300 2850 5 8 0 1 0 8 1 +pinseq=6 +T 450 2900 9 8 1 1 0 0 1 +pinlabel=SCK +T 450 2900 5 8 0 1 0 2 1 +pintype=io +} +P 100 2500 400 2500 1 0 0 +{ +T 300 2550 5 8 1 1 0 6 1 +pinnumber=6 +T 300 2450 5 8 0 1 0 8 1 +pinseq=7 +T 450 2500 9 8 1 1 0 0 1 +pinlabel=GND +T 450 2500 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 2100 400 2100 1 0 0 +{ +T 300 2150 5 8 1 1 0 6 1 +pinnumber=7 +T 300 2050 5 8 0 1 0 8 1 +pinseq=8 +T 450 2100 9 8 1 1 0 0 1 +pinlabel=DAT0/DO,MISO +T 450 2100 5 8 0 1 0 2 1 +pintype=io +} +P 100 1700 400 1700 1 0 0 +{ +T 300 1750 5 8 1 1 0 6 1 +pinnumber=8 +T 300 1650 5 8 0 1 0 8 1 +pinseq=9 +T 450 1700 9 8 1 1 0 0 1 +pinlabel=DAT1/IRQ +T 450 1700 5 8 0 1 0 2 1 +pintype=io +} +P 100 1300 400 1300 1 0 0 +{ +T 300 1350 5 8 1 1 0 6 1 +pinnumber=11 +T 300 1250 5 8 0 1 0 8 1 +pinseq=10 +T 450 1300 9 8 1 1 0 0 1 +pinlabel=\_CD\_ +T 450 1300 5 8 0 1 0 2 1 +pintype=out +} +P 100 900 400 900 1 0 0 +{ +T 300 950 5 8 1 1 0 6 1 +pinnumber=12 +T 300 850 5 8 0 1 0 8 1 +pinseq=11 +T 450 900 9 8 1 1 0 0 1 +pinlabel=GND +T 450 900 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 500 400 500 1 0 0 +{ +T 300 550 5 8 1 1 0 6 1 +pinnumber=10 +T 300 450 5 8 0 1 0 8 1 +pinseq=12 +T 450 500 9 8 1 1 0 0 1 +pinlabel=\_WP\_ +T 450 500 5 8 0 1 0 2 1 +pintype=out +} +B 400 100 1000 5200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1400 5400 8 10 1 1 0 6 1 +refdes=J? +T 400 5400 9 10 1 0 0 0 1 +FCI-10067847-001RLF +T 400 5600 5 10 0 0 0 0 1 +device=FCI-10067847-001RLF +T 400 5800 5 10 0 0 0 0 1 +footprint=FCI-10067847-001RLF +T 400 6000 5 10 0 0 0 0 1 +author=Michael McMaster +T 400 6200 5 10 0 0 0 0 1 +documentation=http://www.alps.com/WebObjects/catalog.woa/E/HTML/Connector/SDMemoryCard/SCDA/SCDA7A0101.html +T 400 6400 5 10 0 0 0 0 1 +description=FCI SD Card 10067847-001RLF +T 400 6600 5 10 0 0 0 0 1 +numslots=0 +T 400 6800 5 10 0 0 0 0 1 +dist-license=gpl3+ +T 400 7000 5 10 0 0 0 0 1 +use-license=gpl3+ +T 400 7200 5 10 0 0 0 0 1 +net=GND:13 diff --git a/hardware/symbols/FCI-10067847.tragesym b/hardware/symbols/FCI-10067847.tragesym new file mode 100644 index 0000000..ab89639 --- /dev/null +++ b/hardware/symbols/FCI-10067847.tragesym @@ -0,0 +1,73 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)". That's useful for micro controller port labels +# rotate_labels rotates the pintext of top and bottom pins +# this is useful for large symbols like FPGAs with more than 100 pins +# sort_labels will sort the pins by it's labels +# useful for address ports, busses, ... +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1000 +pinwidthvertical=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# name is only some graphical text, not an attribute +# version specifies a gschem version. +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20060113 1 +name=FCI-10067847-001RLF +device=FCI-10067847-001RLF +refdes=J? +footprint=FCI-10067847-001RLF +description=FCI SD Card 10067847-001RLF +documentation=http://www.alps.com/WebObjects/catalog.woa/E/HTML/Connector/SDMemoryCard/SCDA/SCDA7A0101.html +author=Michael McMaster +dist-license=gpl3+ +use-license=gpl3+ +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# ---------------------------------------- +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets. +# net specifies the name of the net. Vcc or GND for example. +# label represents the pinlabel. +# negation lines can be added with "\_" example: \_enable\_ +# if you want to write a "\" use "\\" as escape sequence +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +9 io line l DAT2 +1 io line l DAT3,\_CS\_ +2 io line l CMD/DI,MOSI +3 PWR line l GND GND +4 io line l Vcc +5 io line l SCK +6 PWR line l GND GND +7 io line l DAT0/DO,MISO +8 io line l DAT1/IRQ +11 out line l \_CD\_ +12 pwr line l GND GND +10 out line l \_WP\_ +13 pwr none r GND GND + diff --git a/hardware/symbols/FTSH-105-01-L-DV-K.fp b/hardware/symbols/FTSH-105-01-L-DV-K.fp new file mode 100644 index 0000000..f33b74a --- /dev/null +++ b/hardware/symbols/FTSH-105-01-L-DV-K.fp @@ -0,0 +1,25 @@ + +Element["" "" "" "" 12500 1700 0 0 0 100 ""] +( + Pad[20550 356 20550 8456 2900 1200 4100 "" "10" ""] + Pad[15550 356 15550 8456 2900 1200 4100 "" "8" ""] + Pad[10550 356 10550 8456 2900 1200 4100 "" "6" ""] + Pad[5550 356 5550 8456 2900 1200 4100 "" "4" ""] + Pad[550 356 550 8456 2900 1200 4100 "" "2" ""] + Pad[20550 16356 20550 24456 2900 1200 4100 "" "9" "edge2"] + Pad[15550 16356 15550 24456 2900 1200 4100 "" "7" "edge2"] + Pad[10550 16356 10550 24456 2900 1200 4100 "" "5" "edge2"] + Pad[5550 16356 5550 24456 2900 1200 4100 "" "3" "edge2"] + Pad[550 16356 550 24456 2900 1200 4100 "" "1" "edge2"] + ElementLine [33000 19406 33000 5606 1000] + ElementLine [-12000 5606 -12000 19406 1000] + ElementLine [-12000 5606 -2906 5606 1000] + ElementLine [-2906 5606 -2900 5600 1000] + ElementLine [33000 5700 24200 5700 1000] + ElementLine [-12000 19400 -2900 19400 1000] + ElementLine [33000 19400 24300 19400 1000] + ElementLine [-2900 19400 -2900 14000 1000] + ElementLine [-2900 14000 24300 14000 1000] + ElementLine [24300 14000 24300 19400 1000] + + ) diff --git a/hardware/symbols/HEADER50_2_RA.fp b/hardware/symbols/HEADER50_2_RA.fp new file mode 100644 index 0000000..89127d3 --- /dev/null +++ b/hardware/symbols/HEADER50_2_RA.fp @@ -0,0 +1,64 @@ +Element(0x00 "Right-angle Header connector, ribbon cable numbering" "" "HEADER50_2" 260 0 3 100 0x00) +( + Pin(150 2450 60 38 "1" 0x01) + Pin(50 2450 60 38 "2" 0x01) + Pin(150 2350 60 38 "3" 0x01) + Pin(50 2350 60 38 "4" 0x01) + Pin(150 2250 60 38 "5" 0x01) + Pin(50 2250 60 38 "6" 0x01) + Pin(150 2150 60 38 "7" 0x01) + Pin(50 2150 60 38 "8" 0x01) + Pin(150 2050 60 38 "9" 0x01) + Pin(50 2050 60 38 "10" 0x01) + Pin(150 1950 60 38 "11" 0x01) + Pin(50 1950 60 38 "12" 0x01) + Pin(150 1850 60 38 "13" 0x01) + Pin(50 1850 60 38 "14" 0x01) + Pin(150 1750 60 38 "15" 0x01) + Pin(50 1750 60 38 "16" 0x01) + Pin(150 1650 60 38 "17" 0x01) + Pin(50 1650 60 38 "18" 0x01) + Pin(150 1550 60 38 "19" 0x01) + Pin(50 1550 60 38 "20" 0x01) + Pin(150 1450 60 38 "21" 0x01) + Pin(50 1450 60 38 "22" 0x01) + Pin(150 1350 60 38 "23" 0x01) + Pin(50 1350 60 38 "24" 0x01) + Pin(150 1250 60 38 "25" 0x01) + Pin(50 1250 60 38 "26" 0x01) + Pin(150 1150 60 38 "27" 0x01) + Pin(50 1150 60 38 "28" 0x01) + Pin(150 1050 60 38 "29" 0x01) + Pin(50 1050 60 38 "30" 0x01) + Pin(150 950 60 38 "31" 0x01) + Pin(50 950 60 38 "32" 0x01) + Pin(150 850 60 38 "33" 0x01) + Pin(50 850 60 38 "34" 0x01) + Pin(150 750 60 38 "35" 0x01) + Pin(50 750 60 38 "36" 0x01) + Pin(150 650 60 38 "37" 0x01) + Pin(50 650 60 38 "38" 0x01) + Pin(150 550 60 38 "39" 0x01) + Pin(50 550 60 38 "40" 0x01) + Pin(150 450 60 38 "41" 0x01) + Pin(50 450 60 38 "42" 0x01) + Pin(150 350 60 38 "43" 0x01) + Pin(50 350 60 38 "44" 0x01) + Pin(150 250 60 38 "45" 0x01) + Pin(50 250 60 38 "46" 0x01) + Pin(150 150 60 38 "47" 0x01) + Pin(50 150 60 38 "48" 0x01) + Pin(150 50 60 38 "49" 0x01) + Pin(50 50 60 38 "50" 0x101) + ElementLine(0 0 0 2500 10) + ElementLine(0 2500 200 2500 10) + ElementLine(200 2500 200 0 10) + ElementLine(200 0 0 0 10) + ElementLine(0 100 100 100 10) + ElementLine(100 100 100 0 10) + ElementLine(-350 0 0 0 10) + ElementLine(-350 0 -350 2500 10) + ElementLine(-350 2500 0 2500 10) + Mark(50 50) + +) diff --git a/hardware/symbols/LD1117.sym b/hardware/symbols/LD1117.sym new file mode 100644 index 0000000..8f9b12b --- /dev/null +++ b/hardware/symbols/LD1117.sym @@ -0,0 +1,55 @@ +v 20060113 1 +P 900 100 900 400 1 0 0 +{ +T 850 300 5 8 1 1 90 6 1 +pinnumber=1 +T 950 300 5 8 0 1 90 8 1 +pinseq=1 +T 900 450 9 8 1 1 90 0 1 +pinlabel=GND +T 900 450 5 8 0 1 90 2 1 +pintype=pwr +} +P 1700 800 1400 800 1 0 0 +{ +T 1500 850 5 8 1 1 0 0 1 +pinnumber=2 +T 1500 750 5 8 0 1 0 2 1 +pinseq=2 +T 1350 800 9 8 1 1 0 6 1 +pinlabel=OUT +T 1350 800 5 8 0 1 0 8 1 +pintype=pwr +} +P 100 800 400 800 1 0 0 +{ +T 300 850 5 8 1 1 0 6 1 +pinnumber=3 +T 300 750 5 8 0 1 0 8 1 +pinseq=3 +T 450 800 9 8 1 1 0 0 1 +pinlabel=IN +T 450 800 5 8 0 1 0 2 1 +pintype=pwr +} +B 400 400 1000 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1400 1300 8 10 1 1 0 6 1 +refdes=U? +T 400 1300 9 10 1 0 0 0 1 +LD1117 +T 400 1500 5 10 0 0 0 0 1 +device=LD1117 +T 400 1700 5 10 0 0 0 0 1 +footprint=DPAK +T 400 1900 5 10 0 0 0 0 1 +author=Michael McMaster +T 400 2100 5 10 0 0 0 0 1 +documentation=http://www.st.com/web/en/resource/technical/document/datasheet/CD00000544.pdf +T 400 2300 5 10 0 0 0 0 1 +description=LDO Regulator, fixed +T 400 2500 5 10 0 0 0 0 1 +numslots=0 +T 400 2700 5 10 0 0 0 0 1 +dist-license=gpl3+ +T 400 2900 5 10 0 0 0 0 1 +use-license=gpl3+ diff --git a/hardware/symbols/LD1117.tragesym b/hardware/symbols/LD1117.tragesym new file mode 100644 index 0000000..cdcf107 --- /dev/null +++ b/hardware/symbols/LD1117.tragesym @@ -0,0 +1,64 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)". That's useful for micro controller port labels +# rotate_labels rotates the pintext of top and bottom pins +# this is useful for large symbols like FPGAs with more than 100 pins +# sort_labels will sort the pins by it's labels +# useful for address ports, busses, ... +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1000 +pinwidthvertical=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# name is only some graphical text, not an attribute +# version specifies a gschem version. +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20060113 1 +name=LD1117 +device=LD1117 +refdes=U? +footprint=DPAK +description=LDO Regulator, fixed +documentation=http://www.st.com/web/en/resource/technical/document/datasheet/CD00000544.pdf +author=Michael McMaster +dist-license=gpl3+ +use-license=gpl3+ +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# ---------------------------------------- +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets. +# net specifies the name of the net. Vcc or GND for example. +# label represents the pinlabel. +# negation lines can be added with "\_" example: \_enable\_ +# if you want to write a "\" use "\\" as escape sequence +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 pwr line b GND GND +2 pwr line r OUT +3 pwr line l IN + + diff --git a/hardware/symbols/MOLEX8981.fp b/hardware/symbols/MOLEX8981.fp new file mode 100644 index 0000000..862a706 --- /dev/null +++ b/hardware/symbols/MOLEX8981.fp @@ -0,0 +1,18 @@ +Element ["" "Molex 15-24-4441" "" "" 10000 10000 8000 8000 0 100 ""] ( + Pin [0 0 10000 3000 11000 6000 "Pin4" "4" ""] + Pin [20000 0 10000 3000 11000 6000 "Pin3" "3" ""] + Pin [40000 0 10000 3000 11000 6000 "Pin2" "2" ""] + Pin [60000 0 10000 3000 11000 6000 "Pin1" "1" ""] + Pin [-10000 -10000 11000 3000 11000 10000 "LeftHole" "" "hole"] + Pin [70000 -10000 11000 3000 11000 10000 "RightHole" "" "hole"] + + Pin [10000 -40000 16000 3000 16000 15700 "BackLeftHole" "" "hole"] + Pin [50000 -40000 16000 3000 16000 15700 "BackRightHole" "" "hole"] + + ElementLine[-16000 9000 76000 9000 1000] + ElementLine[-16000 9000 -16000 -50000 1000] + ElementLine[-16000 -50000 76000 -50000 1000] + ElementLine[76000 -50000 76000 9000 1000] +) + + diff --git a/hardware/symbols/MOLEX8981.sym b/hardware/symbols/MOLEX8981.sym new file mode 100644 index 0000000..34f965a --- /dev/null +++ b/hardware/symbols/MOLEX8981.sym @@ -0,0 +1,64 @@ +v 20060113 1 +P 100 1700 400 1700 1 0 0 +{ +T 300 1750 5 8 1 1 0 6 1 +pinnumber=1 +T 300 1650 5 8 0 1 0 8 1 +pinseq=1 +T 450 1700 9 8 1 1 0 0 1 +pinlabel=+12V +T 450 1700 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 1300 400 1300 1 0 0 +{ +T 300 1350 5 8 1 1 0 6 1 +pinnumber=2 +T 300 1250 5 8 0 1 0 8 1 +pinseq=2 +T 450 1300 9 8 1 1 0 0 1 +pinlabel=GND +T 450 1300 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 900 400 900 1 0 0 +{ +T 300 950 5 8 1 1 0 6 1 +pinnumber=3 +T 300 850 5 8 0 1 0 8 1 +pinseq=3 +T 450 900 9 8 1 1 0 0 1 +pinlabel=GND +T 450 900 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 500 400 500 1 0 0 +{ +T 300 550 5 8 1 1 0 6 1 +pinnumber=4 +T 300 450 5 8 0 1 0 8 1 +pinseq=4 +T 450 500 9 8 1 1 0 0 1 +pinlabel=+5V +T 450 500 5 8 0 1 0 2 1 +pintype=pwr +} +B 400 100 500 2000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 900 2200 8 10 1 1 0 6 1 +refdes=J? +T 400 2200 9 10 1 0 0 0 1 +MOLEX8981 +T 400 2400 5 10 0 0 0 0 1 +device=MOLEX8981 +T 400 2600 5 10 0 0 0 0 1 +footprint=MOLEX +T 400 2800 5 10 0 0 0 0 1 +author=Michael McMaster +T 400 3000 5 10 0 0 0 0 1 +description=Disk drive power connector +T 400 3200 5 10 0 0 0 0 1 +numslots=0 +T 400 3400 5 10 0 0 0 0 1 +dist-license=gpl3+ +T 400 3600 5 10 0 0 0 0 1 +use-license=gpl3+ diff --git a/hardware/symbols/MOLEX8981.tragesym b/hardware/symbols/MOLEX8981.tragesym new file mode 100644 index 0000000..e90c617 --- /dev/null +++ b/hardware/symbols/MOLEX8981.tragesym @@ -0,0 +1,63 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)". That's useful for micro controller port labels +# rotate_labels rotates the pintext of top and bottom pins +# this is useful for large symbols like FPGAs with more than 100 pins +# sort_labels will sort the pins by it's labels +# useful for address ports, busses, ... +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=500 +pinwidthvertical=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# name is only some graphical text, not an attribute +# version specifies a gschem version. +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20060113 1 +name=MOLEX8981 +device=MOLEX8981 +refdes=J? +footprint=MOLEX +description=Disk drive power connector +documentation= +author=Michael McMaster +dist-license=gpl3+ +use-license=gpl3+ +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# ---------------------------------------- +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets. +# net specifies the name of the net. Vcc or GND for example. +# label represents the pinlabel. +# negation lines can be added with "\_" example: \_enable\_ +# if you want to write a "\" use "\\" as escape sequence +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 pwr line l +12V +2 pwr line l GND +3 pwr line l GND +4 pwr line l +5V diff --git a/hardware/symbols/SCDA7A0101.sym b/hardware/symbols/SCDA7A0101.sym new file mode 100644 index 0000000..47be15d --- /dev/null +++ b/hardware/symbols/SCDA7A0101.sym @@ -0,0 +1,156 @@ +v 20060113 1 +P 100 4900 400 4900 1 0 0 +{ +T 300 4950 5 8 1 1 0 6 1 +pinnumber=9 +T 300 4850 5 8 0 1 0 8 1 +pinseq=1 +T 450 4900 9 8 1 1 0 0 1 +pinlabel=DAT2 +T 450 4900 5 8 0 1 0 2 1 +pintype=io +} +P 100 4500 400 4500 1 0 0 +{ +T 300 4550 5 8 1 1 0 6 1 +pinnumber=1 +T 300 4450 5 8 0 1 0 8 1 +pinseq=2 +T 450 4500 9 8 1 1 0 0 1 +pinlabel=DAT3,\_CS\_ +T 450 4500 5 8 0 1 0 2 1 +pintype=io +} +P 100 4100 400 4100 1 0 0 +{ +T 300 4150 5 8 1 1 0 6 1 +pinnumber=2 +T 300 4050 5 8 0 1 0 8 1 +pinseq=3 +T 450 4100 9 8 1 1 0 0 1 +pinlabel=CMD/DI,MOSI +T 450 4100 5 8 0 1 0 2 1 +pintype=io +} +P 100 3700 400 3700 1 0 0 +{ +T 300 3750 5 8 1 1 0 6 1 +pinnumber=3 +T 300 3650 5 8 0 1 0 8 1 +pinseq=4 +T 450 3700 9 8 1 1 0 0 1 +pinlabel=GND +T 450 3700 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 3300 400 3300 1 0 0 +{ +T 300 3350 5 8 1 1 0 6 1 +pinnumber=4 +T 300 3250 5 8 0 1 0 8 1 +pinseq=5 +T 450 3300 9 8 1 1 0 0 1 +pinlabel=Vcc +T 450 3300 5 8 0 1 0 2 1 +pintype=io +} +P 100 2900 400 2900 1 0 0 +{ +T 300 2950 5 8 1 1 0 6 1 +pinnumber=5 +T 300 2850 5 8 0 1 0 8 1 +pinseq=6 +T 450 2900 9 8 1 1 0 0 1 +pinlabel=SCK +T 450 2900 5 8 0 1 0 2 1 +pintype=io +} +P 100 2500 400 2500 1 0 0 +{ +T 300 2550 5 8 1 1 0 6 1 +pinnumber=6 +T 300 2450 5 8 0 1 0 8 1 +pinseq=7 +T 450 2500 9 8 1 1 0 0 1 +pinlabel=GND +T 450 2500 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 2100 400 2100 1 0 0 +{ +T 300 2150 5 8 1 1 0 6 1 +pinnumber=7 +T 300 2050 5 8 0 1 0 8 1 +pinseq=8 +T 450 2100 9 8 1 1 0 0 1 +pinlabel=DAT0/DO,MISO +T 450 2100 5 8 0 1 0 2 1 +pintype=io +} +P 100 1700 400 1700 1 0 0 +{ +T 300 1750 5 8 1 1 0 6 1 +pinnumber=8 +T 300 1650 5 8 0 1 0 8 1 +pinseq=9 +T 450 1700 9 8 1 1 0 0 1 +pinlabel=DAT1/IRQ +T 450 1700 5 8 0 1 0 2 1 +pintype=io +} +P 100 1300 400 1300 1 0 0 +{ +T 300 1350 5 8 1 1 0 6 1 +pinnumber=10 +T 300 1250 5 8 0 1 0 8 1 +pinseq=10 +T 450 1300 9 8 1 1 0 0 1 +pinlabel=\_CD\_ +T 450 1300 5 8 0 1 0 2 1 +pintype=out +} +P 100 900 400 900 1 0 0 +{ +T 300 950 5 8 1 1 0 6 1 +pinnumber=11 +T 300 850 5 8 0 1 0 8 1 +pinseq=11 +T 450 900 9 8 1 1 0 0 1 +pinlabel=GND +T 450 900 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 500 400 500 1 0 0 +{ +T 300 550 5 8 1 1 0 6 1 +pinnumber=12 +T 300 450 5 8 0 1 0 8 1 +pinseq=12 +T 450 500 9 8 1 1 0 0 1 +pinlabel=\_WP\_ +T 450 500 5 8 0 1 0 2 1 +pintype=out +} +B 400 100 1000 5200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1400 5400 8 10 1 1 0 6 1 +refdes=J? +T 400 5400 9 10 1 0 0 0 1 +SCDA7A0101 +T 400 5600 5 10 0 0 0 0 1 +device=SCDA7A0101 +T 400 5800 5 10 0 0 0 0 1 +footprint=SCDA7A0101 +T 400 6000 5 10 0 0 0 0 1 +author=Michael McMaster +T 400 6200 5 10 0 0 0 0 1 +documentation=http://www.alps.com/WebObjects/catalog.woa/E/HTML/Connector/SDMemoryCard/SCDA/SCDA7A0101.html +T 400 6400 5 10 0 0 0 0 1 +description=SD Memory Card Connector +T 400 6600 5 10 0 0 0 0 1 +numslots=0 +T 400 6800 5 10 0 0 0 0 1 +dist-license=gpl3+ +T 400 7000 5 10 0 0 0 0 1 +use-license=gpl3+ +T 400 7200 5 10 0 0 0 0 1 +net=GND:13,14 diff --git a/hardware/symbols/SCDA7A0101.tragesym b/hardware/symbols/SCDA7A0101.tragesym new file mode 100644 index 0000000..4e590dd --- /dev/null +++ b/hardware/symbols/SCDA7A0101.tragesym @@ -0,0 +1,74 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)". That's useful for micro controller port labels +# rotate_labels rotates the pintext of top and bottom pins +# this is useful for large symbols like FPGAs with more than 100 pins +# sort_labels will sort the pins by it's labels +# useful for address ports, busses, ... +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1000 +pinwidthvertical=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# name is only some graphical text, not an attribute +# version specifies a gschem version. +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20060113 1 +name=SCDA7A0101 +device=SCDA7A0101 +refdes=J? +footprint=SCDA7A0101 +description=SD Memory Card Connector +documentation=http://www.alps.com/WebObjects/catalog.woa/E/HTML/Connector/SDMemoryCard/SCDA/SCDA7A0101.html +author=Michael McMaster +dist-license=gpl3+ +use-license=gpl3+ +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# ---------------------------------------- +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets. +# net specifies the name of the net. Vcc or GND for example. +# label represents the pinlabel. +# negation lines can be added with "\_" example: \_enable\_ +# if you want to write a "\" use "\\" as escape sequence +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +9 io line l DAT2 +1 io line l DAT3,\_CS\_ +2 io line l CMD/DI,MOSI +3 PWR line l GND GND +4 io line l Vcc +5 io line l SCK +6 PWR line l GND GND +7 io line l DAT0/DO,MISO +8 io line l DAT1/IRQ +10 out line l \_CD\_ +11 pwr line l GND GND +12 out line l \_WP\_ +13 pwr none r GND GND +14 pwr none r GND GND + diff --git a/hardware/symbols/SOT23_MOSFET.fp b/hardware/symbols/SOT23_MOSFET.fp new file mode 100644 index 0000000..e5679d7 --- /dev/null +++ b/hardware/symbols/SOT23_MOSFET.fp @@ -0,0 +1,30 @@ + # 78 for SOT23 + # 82 for SOT23 + # 41 for SOT23 + # 34 for SOT23, 24 for SOT25 +Element(0x00 "SMT transistor, 3 pins" "" "SOT23" 148 0 3 100 0x00) +( + ElementLine(0 0 0 139 10) + ElementLine(0 139 128 139 10) + ElementLine(128 139 128 0 10) + ElementLine(128 0 0 0 10) + # 1st side, 1st pin + Pad(25 107 + 25 113 + 34 + "1" "G" 0x100) + # 1st side, 2nd pin + # 1st side, 3rd pin + Pad(103 107 + 103 113 + 34 + "2" "S" 0x100) + # 2nd side, 3rd pin + # 2nd side, 2nd pin + Pad(64 25 + 64 31 + 34 + "3" "D" 0x100) + # 2nd side, 1st pin + Mark(25 110) +) diff --git a/hardware/symbols/SOT26_MOSFET.fp b/hardware/symbols/SOT26_MOSFET.fp new file mode 100644 index 0000000..9a9358f --- /dev/null +++ b/hardware/symbols/SOT26_MOSFET.fp @@ -0,0 +1,36 @@ + # 78 for SOT23 + # 82 for SOT23 + # 41 for SOT23 + # 34 for SOT23, 24 for SOT25 +Element(0x00 "SMT transistor, 6 pins" "" "SOT26" 138 0 3 100 0x00) +( + ElementLine(0 0 0 139 10) + ElementLine(0 139 118 139 10) + ElementLine(118 139 118 0 10) + ElementLine(118 0 0 0 10) + # 1st side, 1st pin + Pad(20 102 + 20 118 + 24 "1" "D" 0x100) + # 1st side, 2nd pin + Pad(59 102 + 59 118 + 24 "2" "D" 0x100) + # 1st side, 3rd pin + Pad(98 102 + 98 118 + 24 "3" "G" 0x100) + # 2nd side, 3rd pin + Pad(98 20 + 98 36 + 24 "4" "S" 0x100) + # 2nd side, 2nd pin + Pad(59 20 + 59 36 + 24 "5" "D" 0x100) + # 2nd side, 1st pin + Pad(20 20 + 20 36 + 24 "6" "D" 0x100) + Mark(20 110) +) diff --git a/hardware/symbols/TO220_TRANSISTOR.fp b/hardware/symbols/TO220_TRANSISTOR.fp new file mode 100644 index 0000000..0bf5eb9 --- /dev/null +++ b/hardware/symbols/TO220_TRANSISTOR.fp @@ -0,0 +1,19 @@ + Element(0x00 "Transistor" "" "TO220W" 0 10 0 100 0x00) +( + Pin(100 200 90 60 "1" "B" 0x101) + Pin(200 200 90 60 "2" "C" 0x01) + Pin(300 200 90 60 "3" "E" 0x01) + # Gehaeuse + ElementLine( 0 80 400 80 20) + ElementLine(400 80 400 260 20) + ElementLine(400 260 0 260 20) + ElementLine( 0 260 0 80 20) + # Kuehlfahne icl. Bohrung + ElementLine( 0 80 400 80 20) + ElementLine(400 80 400 140 20) + ElementLine(400 140 0 140 20) + ElementLine( 0 140 0 80 20) + ElementLine(130 80 130 140 10) + ElementLine(270 80 270 140 10) + Mark(100 200) +) diff --git a/hardware/symbols/cap_0402.fp b/hardware/symbols/cap_0402.fp new file mode 100644 index 0000000..da98f0a --- /dev/null +++ b/hardware/symbols/cap_0402.fp @@ -0,0 +1,11 @@ + +Element["" "" "" "" 2137 2037 0 0 0 100 ""] +( + Pad[3872 35 3872 35 1969 1200 2569 "1" "1" "square,edge2"] + Pad[-65 35 -65 35 1969 1200 2569 "2" "2" "square"] + ElementLine [-1837 1806 -1837 -1737 600] + ElementLine [5643 1806 -1837 1806 600] + ElementLine [5643 -1737 5643 1806 600] + ElementLine [-1837 -1737 5643 -1737 600] + + ) diff --git a/hardware/symbols/diode-DO-214AA-SMB.fp b/hardware/symbols/diode-DO-214AA-SMB.fp new file mode 100644 index 0000000..de93706 --- /dev/null +++ b/hardware/symbols/diode-DO-214AA-SMB.fp @@ -0,0 +1,24 @@ + +Element["" "" "" "" 235039 155118 0 0 0 100 ""] +( + Pad[197 -591 984 -591 9055 2000 10055 "cathode" "1" "square"] + Pad[17126 -591 17913 -591 9055 2000 10055 "anode" "2" "square,edge2"] + ElementLine [-5118 -9843 -5118 9055 1000] + ElementLine [-5118 9055 23622 9055 1000] + ElementLine [23622 9055 23622 -9843 1000] + ElementLine [23622 -9843 -5118 -9843 1000] + ElementLine [-394 -9843 -394 -5906 1000] + ElementLine [-394 -5906 394 -5906 1000] + ElementLine [394 -5906 394 -9055 1000] + ElementLine [-394 9055 -394 5118 1000] + ElementLine [-394 5118 394 5118 1000] + ElementLine [394 5118 394 8268 1000] + ElementLine [10236 3937 7874 6299 1000] + ElementLine [7874 6299 10630 9055 1000] + ElementLine [10630 9055 10630 4331 1000] + ElementLine [10630 4331 10236 3937 1000] + ElementLine [10630 6299 16535 6299 1000] + ElementLine [7087 3543 7087 9055 1000] + ElementLine [4724 6299 7874 6299 1000] + + ) diff --git a/hardware/symbols/fci-10118192-0001LF.fp b/hardware/symbols/fci-10118192-0001LF.fp new file mode 100644 index 0000000..c67a01a --- /dev/null +++ b/hardware/symbols/fci-10118192-0001LF.fp @@ -0,0 +1,23 @@ + +Element["" "" "" "" 275009 222794 0 0 0 100 ""] +( + Pad[-63 -8271 -63 -4531 1575 1200 2175 "3" "3" "square"] + Pad[5055 -8271 5055 -4531 1575 1200 2175 "5" "5" "square"] + Pad[-5181 -8271 -5181 -4531 1575 1200 2175 "1" "1" "square"] + Pad[2496 -8271 2496 -4531 1575 1200 2175 "4" "4" "square"] + Pad[-2622 -8271 -2622 -4531 1575 1200 2175 "2" "2" "square"] + Pad[-13252 -5909 -11284 -5909 6299 1200 6899 "" "6" "square"] + Pad[11157 -5909 13126 -5909 6299 1200 6899 "" "7" "square,edge2"] + Pad[-15024 3934 -15024 4328 7087 1200 7687 "" "8" "square,edge2"] + Pad[-4788 4131 -4788 4131 7480 1200 8080 "" "9" "square"] + Pad[4661 4131 4661 4131 7480 1200 8080 "" "10" "square,edge2"] + Pad[14897 3934 14897 4328 7087 1200 7687 "" "11" "square,edge2"] + ElementLine [-18567 9840 18441 9840 600] + ElementLine [-15024 9840 -15024 8462 600] + ElementLine [-15024 -3 -15024 -2168 600] + ElementLine [15094 9840 15094 8462 600] + ElementLine [15094 -3 15094 -2168 600] + ElementLine [-7741 -7877 -6559 -7877 600] + ElementLine [6236 -7877 7614 -7877 600] + + ) diff --git a/hardware/symbols/usbmini.sym b/hardware/symbols/usbmini.sym new file mode 100644 index 0000000..6191177 --- /dev/null +++ b/hardware/symbols/usbmini.sym @@ -0,0 +1,51 @@ +v 20070818 1 +T 100 100 0 1 0 0 0 0 1 +gedasymbols::url=http://www.gedasymbols.org/user/sean_depagnier/symbols/usbmini.sym +T 700 1600 8 10 1 1 0 0 1 +refdes=CONN? +T 100 1600 9 10 1 1 0 0 1 +device=USB +T 400 12650 8 10 0 0 0 0 1 +footprint=usbminib +B 100 0 800 1500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1300 400 900 400 1 0 0 +{ +T 1100 490 5 10 1 1 0 0 1 +pinnumber=4 +T 600 380 5 10 1 1 0 0 1 +pinlabel=ID +} +P 1300 700 900 700 1 0 0 +{ +T 1100 730 5 10 1 1 0 0 1 +pinnumber=3 +T 600 720 5 10 1 1 0 0 1 +pinlabel=D+ +} +P 1300 1000 900 1000 1 0 0 +{ +T 1100 1070 5 10 1 1 0 0 1 +pinnumber=2 +T 600 1060 5 10 1 1 0 0 1 +pinlabel=D- +} +P 1300 1300 900 1300 1 0 0 +{ +T 1100 1310 5 10 1 1 0 0 1 +pinnumber=1 +T 400 1300 5 10 1 1 0 0 1 +pinlabel=VCC +} +T 400 12450 8 10 0 0 0 0 1 +T 400 13650 8 10 0 0 0 0 1 +T 400 13850 8 10 0 0 0 0 1 +numslots=0 +T 400 14050 8 10 0 0 0 0 1 +author=Sean D'Epagnier +P 1300 100 900 100 1 0 0 +{ +T 1100 190 5 10 1 1 0 0 1 +pinnumber=5 +T 400 80 5 10 1 1 0 0 1 +pinlabel=GND +} diff --git a/hardware/symbols/wurth-microsd.fp b/hardware/symbols/wurth-microsd.fp new file mode 100644 index 0000000..b729c4e --- /dev/null +++ b/hardware/symbols/wurth-microsd.fp @@ -0,0 +1,28 @@ + +Element["" "" "" "" 58000 53000 0 0 0 100 ""] +( + Pad[-7555 -17555 -7555 -14799 3150 1200 3750 "1" "1" "square"] + Pad[-3224 -15980 -3224 -13224 3150 1200 3750 "2" "2" "square"] + Pad[1106 -17555 1106 -14799 3150 1200 3750 "3" "3" "square"] + Pad[5437 -18343 5437 -15587 3150 1200 3750 "4" "4" "square"] + Pad[9768 -17555 9768 -14799 3150 1200 3750 "5" "5" "square"] + Pad[14098 -18343 14098 -15587 3150 1200 3750 "6" "6" "square"] + Pad[18429 -17555 18429 -14799 3150 1200 3750 "7" "7" "square"] + Pad[22760 -17555 22760 -14799 3150 1200 3750 "8" "8" "square"] + Pad[25909 -28185 25909 -26217 5512 1200 6112 "9" "9" "square"] + Pad[18035 24571 19610 24571 5512 1200 6112 "10" "10" "square,edge2"] + Pad[-4406 24571 -2831 24571 5512 1200 6112 "10" "10" "square"] + Pad[-26453 -32516 -26453 -30547 5512 1200 6112 "9" "9" "square"] + ElementLine [-19000 -31500 -11000 -31500 600] + ElementLine [-11000 -31500 -11000 -26500 600] + ElementLine [-11000 -26500 19500 -26500 600] + ElementLine [19500 -26500 22000 -29000 600] + ElementLine [-19000 -31500 -19000 -34000 600] + ElementLine [-19000 -34000 -22500 -34000 600] + ElementLine [-28000 -27000 -28000 26000 600] + ElementLine [-28000 26000 -9000 26000 600] + ElementLine [1000 26000 14000 26000 600] + ElementLine [23500 26000 27500 26000 600] + ElementLine [27500 26000 27500 -22000 600] + + ) diff --git a/hardware/symbols/wurth-microsd.sym b/hardware/symbols/wurth-microsd.sym new file mode 100644 index 0000000..6dddefa --- /dev/null +++ b/hardware/symbols/wurth-microsd.sym @@ -0,0 +1,132 @@ +v 20060113 1 +P 100 4100 400 4100 1 0 0 +{ +T 300 4150 5 8 1 1 0 6 1 +pinnumber=1 +T 300 4050 5 8 0 1 0 8 1 +pinseq=1 +T 450 4100 9 8 1 1 0 0 1 +pinlabel=DAT2 +T 450 4100 5 8 0 1 0 2 1 +pintype=io +} +P 100 3700 400 3700 1 0 0 +{ +T 300 3750 5 8 1 1 0 6 1 +pinnumber=2 +T 300 3650 5 8 0 1 0 8 1 +pinseq=2 +T 450 3700 9 8 1 1 0 0 1 +pinlabel=DAT3 +T 450 3700 5 8 0 1 0 2 1 +pintype=io +} +P 100 3300 400 3300 1 0 0 +{ +T 300 3350 5 8 1 1 0 6 1 +pinnumber=3 +T 300 3250 5 8 0 1 0 8 1 +pinseq=3 +T 450 3300 9 8 1 1 0 0 1 +pinlabel=CMD +T 450 3300 5 8 0 1 0 2 1 +pintype=io +} +P 100 2900 400 2900 1 0 0 +{ +T 300 2950 5 8 1 1 0 6 1 +pinnumber=4 +T 300 2850 5 8 0 1 0 8 1 +pinseq=4 +T 450 2900 9 8 1 1 0 0 1 +pinlabel=Vcc +T 450 2900 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 2500 400 2500 1 0 0 +{ +T 300 2550 5 8 1 1 0 6 1 +pinnumber=5 +T 300 2450 5 8 0 1 0 8 1 +pinseq=5 +T 450 2500 9 8 1 1 0 0 1 +pinlabel=CLK +T 450 2500 5 8 0 1 0 2 1 +pintype=clk +} +P 100 2100 400 2100 1 0 0 +{ +T 300 2150 5 8 1 1 0 6 1 +pinnumber=6 +T 300 2050 5 8 0 1 0 8 1 +pinseq=6 +T 450 2100 9 8 1 1 0 0 1 +pinlabel=GND +T 450 2100 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 1700 400 1700 1 0 0 +{ +T 300 1750 5 8 1 1 0 6 1 +pinnumber=7 +T 300 1650 5 8 0 1 0 8 1 +pinseq=7 +T 450 1700 9 8 1 1 0 0 1 +pinlabel=DAT0 +T 450 1700 5 8 0 1 0 2 1 +pintype=io +} +P 100 1300 400 1300 1 0 0 +{ +T 300 1350 5 8 1 1 0 6 1 +pinnumber=8 +T 300 1250 5 8 0 1 0 8 1 +pinseq=8 +T 450 1300 9 8 1 1 0 0 1 +pinlabel=DAT1 +T 450 1300 5 8 0 1 0 2 1 +pintype=io +} +P 100 900 400 900 1 0 0 +{ +T 300 950 5 8 1 1 0 6 1 +pinnumber=9 +T 300 850 5 8 0 1 0 8 1 +pinseq=9 +T 450 900 9 8 1 1 0 0 1 +pinlabel=GND +T 450 900 5 8 0 1 0 2 1 +pintype=io +} +P 100 500 400 500 1 0 0 +{ +T 300 550 5 8 1 1 0 6 1 +pinnumber=10 +T 300 450 5 8 0 1 0 8 1 +pinseq=10 +T 450 500 9 8 1 1 0 0 1 +pinlabel=\_CD\_ +T 450 500 5 8 0 1 0 2 1 +pintype=pwr +} +B 400 100 1000 4400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1400 4600 8 10 1 1 0 6 1 +refdes=J? +T 400 4600 9 10 1 0 0 0 1 +wurth-microsd +T 400 4800 5 10 0 0 0 0 1 +device=wurth-693071010811 +T 400 5000 5 10 0 0 0 0 1 +footprint=wurth-microsd +T 400 5200 5 10 0 0 0 0 1 +author=Michael McMaster +T 400 5400 5 10 0 0 0 0 1 +documentation=http://www.digikey.com/product-detail/en/693071010811/732-3819-1-ND/3124603 +T 400 5600 5 10 0 0 0 0 1 +description=Wurth MicroSD socket 693071010811 +T 400 5800 5 10 0 0 0 0 1 +numslots=0 +T 400 6000 5 10 0 0 0 0 1 +dist-license=gpl3+ +T 400 6200 5 10 0 0 0 0 1 +use-license=gpl3+ diff --git a/hardware/symbols/wurth-microsd.tragesym b/hardware/symbols/wurth-microsd.tragesym new file mode 100644 index 0000000..d8ef516 --- /dev/null +++ b/hardware/symbols/wurth-microsd.tragesym @@ -0,0 +1,70 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)". That's useful for micro controller port labels +# rotate_labels rotates the pintext of top and bottom pins +# this is useful for large symbols like FPGAs with more than 100 pins +# sort_labels will sort the pins by it's labels +# useful for address ports, busses, ... +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1000 +pinwidthvertical=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# name is only some graphical text, not an attribute +# version specifies a gschem version. +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20060113 1 +name=wurth-microsd +device=wurth-693071010811 +refdes=J? +footprint=wurth-microsd +description=Wurth MicroSD socket 693071010811 +documentation=http://www.digikey.com/product-detail/en/693071010811/732-3819-1-ND/3124603 +author=Michael McMaster +dist-license=gpl3+ +use-license=gpl3+ +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# ---------------------------------------- +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets. +# net specifies the name of the net. Vcc or GND for example. +# label represents the pinlabel. +# negation lines can be added with "\_" example: \_enable\_ +# if you want to write a "\" use "\\" as escape sequence +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 io line l DAT2 +2 io line l DAT3 +3 io line l CMD +4 pwr line l Vcc +5 clk line l CLK +6 pwr line l GND GND +7 io line l DAT0 +8 io line l DAT1 +9 io line l GND GND +10 pwr line l \_CD\_ + diff --git a/parts.ods b/parts.ods new file mode 100644 index 0000000000000000000000000000000000000000..7ee3910f1cc9b2dffe299db65c258308e0389bec GIT binary patch literal 20160 zcmaHSWmFwYw=M1jcXxMpcXxLuxP{~Xc z#?gVv!@-=<(ZtopmC@13!ol3p%-!C?!Hv*c<8^*%j2sBv`Dr!8YwI~I(W9{dKCKw70c=9M@=8%Za6y-o^X=;*) zlkgP&0CtE8wOt(q(1zJsPnyw!)_8i^ym3DD`4vby+^;lD@T8&doUX;?~x@ zUC-ZNo!P#3989jYZSZ{AKW%vE{_y{J$=$-$p=88ms~(_Q{IETbMfgzf2d)rR`5;UaT}tl)k6PXY*>%Pv#1J#QDFPDJuTl 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zw_hs^zjbWgzqq$cs{*#1<}0){eSP&C!R4PUOvySFPA_-|J5H~%pq@?gn3UuOM= zxonN=?HvO)1|0b6-={cdUiexEx2-`>UY@TN(7Bp!#Tlp9BtHG~>gidgwqiH_mb)eu zul^rZVO1x)B0vB2(M5bZ$Nw!f__mw7{r+G5Q(xmj6_5SNN>xWT28Ks6_$nUIYKh#$ zyv(%J;u5{0l(e&x&*n872(-MnX-z$M!$F^wwMgUC&aC+dOxq$@^*_xLy0@=ya#-M! zRj=k>dA!ce_4kNPIPZtaWKRrSyT0tN5B<)uPaY=h&7$4opCY z4=j1TU_#}01>5esRx1~5;!4~Ww6}em!o)_0UQVA=EhWt|yZpS58c+KiXnAnq+egO} z_FisYWRvhgyYKvsdmTK>p2j`cyWw3-^ZlBs8CCC+t4c2){diw_O2QnYcmA(-TUY*n z{!j1xf5}Jdx0Jc$IGkIY{%gYXEuZ8=-PePgYu__2u>$MuW_Y~~JH7@OVsIb@WI5;O zrDdj<7J(10DK^qC$S)`@0G?J;s*id^4O|nDflXg=Nn%N9aZ+LtiTXT26jqNh&N%ur2se$Kt}opNwZ+3$PFY!SJ92hFQbJW(opEmzBAePlPKa!5tG$soCw+cz{X_n`d_1e@9F-G~mh5$% zaU%TH@$e1*m_YI4bTg$-0hsk%SwQi_$Rxsm`|K!C93lYhBq?-V=%+&=bc6tzxXy}# znF5Po%FtZVI35goL2z`(;62bqD#T?`k zlUQ@~-7(#RT!P{@2ULb4Kspw43Q$T^+$MoaM+8`i#Uw-tOROo^v6zA=afvmB*8?+j z5G63g6j*iu`2bdosw2DuWI1Co1xJaDFCl?SU<8= CY_DMA_NUMBEROF_CHANNELS) + { + dmaIndex = CY_DMA_INVALID_CHANNEL; + } + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + + return(dmaIndex); +} + + +/******************************************************************************* +* Function Name: CyDmaChFree +******************************************************************************** +* +* Summary: +* Frees a channel allocated by DmaChAlloc(). +* +* Parameters: +* uint8 chHandle: +* The handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChFree(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + uint8 interruptState; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Clear the bit mask that keeps track of ownership. */ + CyDmaChannels &= ~(((uint32) 1u) << chHandle); + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChEnable +******************************************************************************** +* +* Summary: +* Enables the DMA channel. A software or hardware request still must happen +* before the channel is executed. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 preserveTds: +* Preserves the original TD state when the TD has completed. This parameter +* applies to all TDs in the channel. +* +* 0 - When a TD is completed, the DMAC leaves the TD configuration values in +* their current state, and does not restore them to their original state. +* +* 1 - When a TD is completed, the DMAC restores the original configuration +* values of the TD. +* +* When preserveTds is set, the TD slot that equals the channel number becomes +* RESERVED and that becomes where the working registers exist. So, for example, +* if you are using CH06 and preserveTds is set, you are not allowed to use TD +* slot 6. That is reclaimed by the DMA engine for its private use. +* +* Note Do not chain back to a completed TD if the preserveTds for the channel +* is set to 0. When a TD has completed preserveTds for the channel set to 0, +* the transfer count will be at 0. If a TD with a transfer count of 0 is +* started, the TD will transfer an indefinite amount of data. +* +* Take extra precautions when using the hardware request (DRQ) option when the +* preserveTds is set to 0, as you might be requesting the wrong data. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] = + (CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~0x20u))) | ((0u != preserveTds) ? 0x21u : 0x01u); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChDisable +******************************************************************************** +* +* Summary: +* Disables the DMA channel. Once this function is called, CyDmaChStatus() may +* be called to determine when the channel is disabled and which TDs were being +* executed. +* +* If it is currently executing it will allow the current burst to finish +* naturally. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChDisable(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~0x21u)); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaClearPendingDrq +******************************************************************************** +* +* Summary: +* Clears pending DMA data request. +* +* Parameters: +* uint8 chHandle: +* Handle to the dma channel. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaClearPendingDrq(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].action[0] |= CY_DMA_CPU_TERM_CHAIN; + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] |= 0x01u; + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChPriority +******************************************************************************** +* +* Summary: +* Sets the priority of a DMA channel. You can use this function when you want +* to change the priority at run time. If the priority remains the same for a +* DMA channel, then you can configure the priority in the .cydwr file. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 priority: +* Priority to set the channel to, 0 - 7. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) +{ + uint8 value; + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + value = CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~(0x0Eu))); + + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] = value | ((uint8) ((priority & 0x7u) << 0x01u)); + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetExtendedAddress +******************************************************************************** +* +* Summary: +* Sets the high 16 bits of the source and destination addresses for the DMA +* channel (valid for all TDs in the chain). +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint16 source: +* Upper 16 bit address of the DMA transfer source. +* +* uint16 destination: +* Upper 16 bit address of the DMA transfer destination. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \ + +{ + cystatus status = CYRET_BAD_PARAM; + + #if(CY_PSOC5) + + /* 0x1FFF8000-0x1FFFFFFF needs to use alias at 0x20008000-0x2000FFFF */ + if(source == 0x1FFFu) + { + source = 0x2000u; + } + + if(destination == 0x1FFFu) + { + destination = 0x2000u; + } + + #endif /* (CY_PSOC5) */ + + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /* Set source address */ + reg16 *convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0]; + CY_SET_REG16(convert, source); + + /* Set destination address */ + CY_SET_REG16((reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2], destination); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetInitialTd +******************************************************************************** +* +* Summary: +* Sets the initial TD to be executed for the channel when the CyDmaChEnable() +* function is called. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). +* +* uint8 startTd: +* The index of TD to set as the first TD associated with the channel. Zero is +* a valid TD index. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1u] = startTd; + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetRequest +******************************************************************************** +* +* Summary: +* Allows the caller to terminate a chain of TDs, terminate one TD, or create a +* direct request to start the DMA channel. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 request: +* One of the following constants. Each of the constants is a three-bit value. +* +* CPU_REQ - Create a direct request to start the DMA channel +* CPU_TERM_TD - Terminate one TD +* CPU_TERM_CHAIN - Terminate a chain of TDs +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] |= (request & (CPU_REQ | CPU_TERM_TD | CPU_TERM_CHAIN)); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChGetRequest +******************************************************************************** +* +* Summary: +* This function allows the caller of CyDmaChSetRequest() to determine if the +* request was completed. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* Return: +* Returns a three-bit field, corresponding to the three bits of the request, +* which describes the state of the previously posted request. If the value is +* zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle is +* invalid. +* +*******************************************************************************/ +cystatus CyDmaChGetRequest(uint8 chHandle) +{ + cystatus status = CY_DMA_INVALID_CHANNEL; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & + (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN)); + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChStatus +******************************************************************************** +* +* Summary: +* Determines the status of the DMA channel. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 * currentTd: +* The address to store the index of the current TD. Can be NULL if the value +* is not needed. +* +* uint8 * state: +* The address to store the state of the channel. Can be NULL if the value is +* not needed. +* +* STATUS_TD_ACTIVE +* 0: Channel is not currently being serviced by DMAC +* 1: Channel is currently being serviced by DMAC +* +* STATUS_CHAIN_ACTIVE +* 0: TD chain is inactive; either no DMA requests have triggered a new chain +* or the previous chain has completed. +* 1: TD chain has been triggered by a DMA request +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +* Theory: +* The caller can check on the activity of the Current TD and the Chain. +* +*******************************************************************************/ +cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + if(NULL != currentTd) + { + *currentTd = CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1] & 0x7Fu; + } + + if(NULL != state) + { + *state= CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[0]; + } + + status = CYRET_SUCCESS; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetConfiguration +******************************************************************************** +* +* Summary: +* Sets configuration information of the channel. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). +* +* uint8 burstCount: +* Specifies the size of bursts (1 to 127) the data transfer should be divided +* into. If this value is zero then the whole transfer is done in one burst. +* +* uint8 requestPerBurst: +* The whole of the data can be split into multiple bursts, if this is +* required to complete the transaction: +* 0: All subsequent bursts after the first burst will be automatically +* requested and carried out +* 1: All subsequent bursts after the first burst must also be individually +* requested. +* +* uint8 tdDone0: +* Selects one of the TERMOUT0 interrupt lines to signal completion. The line +* connected to the nrq terminal will determine the TERMOUT0_SEL definition and +* should be used as supplied by cyfitter.h +* +* uint8 tdDone1: +* Selects one of the TERMOUT1 interrupt lines to signal completion. The line +* connected to the nrq terminal will determine the TERMOUT1_SEL definition and +* should be used as supplied by cyfitter.h +* +* uint8 tdStop: +* Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD +* should terminate. The signal connected to the trq terminal will determine +* which TERMIN (termination request) is used. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, + uint8 tdDone0, uint8 tdDone1, uint8 tdStop) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBurst & 0x1u) << 7u)); + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[1] = ((uint8)((tdDone1 & 0xFu) << 4u)) | (tdDone0 & 0xFu); + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[2] = 0x0Fu & tdStop; + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[3] = 0u; /* burstcount_remain. */ + + status = CYRET_SUCCESS; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdAllocate +******************************************************************************** +* +* Summary: +* Allocates a TD for use with an allocated DMA channel. +* +* Parameters: +* None +* +* Return: +* Zero-based index of the TD to be used by the caller. Since there are 128 TDs +* minus the reserved TDs (0 to 23), the value returned would range from 24 to +* 127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs +* available. +* +*******************************************************************************/ +uint8 CyDmaTdAllocate(void) +{ + uint8 interruptState; + uint8 element = CY_DMA_INVALID_TD; + + /* Enter critical section! */ + interruptState = CyEnterCriticalSection(); + + if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS) + { + /* Get pointer to the Next available. */ + element = CyDmaTdFreeIndex; + + /* Decrement the count. */ + CyDmaTdCurrentNumber--; + + /* Update the next available pointer. */ + CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0]; + } + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + + return(element); +} + + +/******************************************************************************* +* Function Name: CyDmaTdFree +******************************************************************************** +* +* Summary: +* Returns a TD to the free list. +* +* Parameters: +* uint8 tdHandle: +* The TD handle returned by the CyDmaTdAllocate(). +* +* Return: +* None +* +*******************************************************************************/ +void CyDmaTdFree(uint8 tdHandle) +{ + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* Enter critical section! */ + uint8 interruptState = CyEnterCriticalSection(); + + /* Get pointer to the Next available. */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex; + + /* Set new Next Available. */ + CyDmaTdFreeIndex = tdHandle; + + /* Keep track of how many left. */ + CyDmaTdCurrentNumber++; + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + } +} + + +/******************************************************************************* +* Function Name: CyDmaTdFreeCount +******************************************************************************** +* +* Summary: +* Returns the number of free TDs available to be allocated. +* +* Parameters: +* None +* +* Return: +* The number of free TDs. +* +*******************************************************************************/ +uint8 CyDmaTdFreeCount(void) +{ + return(CyDmaTdCurrentNumber - CY_DMA_NUMBEROF_CHANNELS); +} + + +/******************************************************************************* +* Function Name: CyDmaTdSetConfiguration +******************************************************************************** +* +* Summary: +* Configures the TD. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 transferCount: +* The size of the data transfer (in bytes) for this TD. A size of zero will +* cause the transfer to continue indefinitely. This parameter is limited to +* 4095 bytes; the TD is not initialized at all when a higher value is passed. +* +* uint8 nextTd: +* Zero based index of the next Transfer Descriptor in the TD chain. Zero is a +* valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain. +* DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No +* further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and +* PSoC 5LP silicons. +* +* uint8 configuration: +* Stores the Bit field of configuration bits. +* +* CY_DMA_TD_SWAP_EN - Perform endian swap +* +* CY_DMA_TD_SWAP_SIZE4 - Swap size = 4 bytes +* +* CY_DMA_TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger +* automatically when the current TD completes. +* +* CY_DMA_TD_TERMIN_EN - Terminate this TD if a positive edge on the trq +* input line occurs. The positive edge must occur +* during a burst. That is the only time the DMAC +* will listen for it. +* +* DMA__TD_TERMOUT_EN - When this TD completes, the TERMOUT signal will +* generate a pulse. Note that this option is +* instance specific with the instance name followed +* by two underscores. In this example, the instance +* name is DMA. +* +* CY_DMA_TD_INC_DST_ADR - Increment DST_ADR according to the size of each +* data transaction in the burst. +* +* CY_DMA_TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each +* data transaction in the burst. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle or transferCount is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) \ + +{ + cystatus status = CYRET_BAD_PARAM; + + if((tdHandle < CY_DMA_NUMBEROF_TDS) && (0u == (0xF000u & transferCount))) + { + /* Set 12 bits transfer count. */ + reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u]; + CY_SET_REG16(convert, transferCount); + + /* Set Next TD pointer. */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u] = nextTd; + + /* Configure the TD */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u] = configuration; + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdGetConfiguration +******************************************************************************** +* +* Summary: +* Retrieves the configuration of the TD. If a NULL pointer is passed as a +* parameter, that parameter is skipped. You may request only the values you are +* interested in. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 * transferCount: +* The address to store the size of the data transfer (in bytes) for this TD. +* A size of zero could indicate that the TD has completed its transfer, or +* that the TD is doing an indefinite transfer. +* +* uint8 * nextTd: +* The address to store the index of the next TD in the TD chain. +* +* uint8 * configuration: +* The address to store the Bit field of configuration bits. +* See CyDmaTdSetConfiguration() function description. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +* Side Effects: +* If a TD has a transfer count of N and is executed, the transfer count becomes +* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a +* request for indefinite transfer. Be careful when requesting a TD with a +* transfer count of zero. +* +*******************************************************************************/ +cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) \ + +{ + cystatus status = CYRET_BAD_PARAM; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* If we have a pointer */ + if(NULL != transferCount) + { + /* Get the 12 bits of the transfer count */ + reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0]; + *transferCount = 0x0FFFu & CY_GET_REG16(convert); + } + + /* If we have a pointer */ + if(NULL != nextTd) + { + /* Get the Next TD pointer */ + *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u]; + } + + /* If we have a pointer */ + if(NULL != configuration) + { + /* Get the configuration the TD */ + *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u]; + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdSetAddress +******************************************************************************** +* +* Summary: +* Sets the lower 16 bits of the source and destination addresses for this TD +* only. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 source: +* The lower 16 address bits of the source of the data transfer. +* +* uint16 destination: +* The lower 16 address bits of the destination of the data transfer. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) +{ + cystatus status = CYRET_BAD_PARAM; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* Set source address */ + reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0]; + CY_SET_REG16(convert, source); + + /* Set destination address */ + CY_SET_REG16((reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2], destination); + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdGetAddress +******************************************************************************** +* +* Summary: +* Retrieves the lower 16 bits of the source and/or destination addresses for +* this TD only. If NULL is passed for a pointer parameter, that value is +* skipped. You may request only the values of interest. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 * source: +* The address to store the lower 16 address bits of the source of the data +* transfer. +* +* uint16 * destination: +* The address to store the lower 16 address bits of the destination of the +* data transfer. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) +{ + cystatus status = CYRET_BAD_PARAM; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* If we have a pointer. */ + if(NULL != source) + { + /* Get source address */ + reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0]; + *source = CY_GET_REG16(convert); + } + + /* If we have a pointer. */ + if(NULL != destination) + { + /* Get Destination address. */ + *destination = CY_GET_REG16((reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2]); + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChRoundRobin +******************************************************************************** +* +* Summary: +* Either enables or disables the Round-Robin scheduling enforcement algorithm. +* Within a priority level a Round-Robin fairness algorithm is enforced. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize(). +* +* uint8 enableRR: +* 0: Disable Round-Robin fairness algorithm +* 1: Enable Round-Robin fairness algorithm +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] = + (CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~CY_DMA_ROUND_ROBIN_ENABLE))) | + ((0u != enableRR) ? CY_DMA_ROUND_ROBIN_ENABLE : ((uint8)(~CY_DMA_ROUND_ROBIN_ENABLE))); + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h new file mode 100644 index 0000000..82b5b1b --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h @@ -0,0 +1,212 @@ +/******************************************************************************* +* File Name: CyDmac.h +* Version 3.40 +* +* Description: +* Provides the function definitions for the DMA Controller. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYDMAC_H) +#define CY_BOOT_CYDMAC_H + + +#include "cytypes.h" +#include "cyfitter.h" +#include "cydevice_trm.h" +#include "CyLib.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +/* DMA Controller functions. */ +void CyDmacConfigure(void) ; +uint8 CyDmacError(void) ; +void CyDmacClearError(uint8 error) ; +uint32 CyDmacErrorAddress(void) ; + +/* Channel specific functions. */ +uint8 CyDmaChAlloc(void) ; +cystatus CyDmaChFree(uint8 chHandle) ; +cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ; +cystatus CyDmaChDisable(uint8 chHandle) ; +cystatus CyDmaClearPendingDrq(uint8 chHandle) ; +cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ; +cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination); +cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ; +cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ; +cystatus CyDmaChGetRequest(uint8 chHandle) ; +cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ; +cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0, uint8 tdDone1, uint8 tdStop) ; +cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ; + +/* Transfer Descriptor functions. */ +uint8 CyDmaTdAllocate(void) ; +void CyDmaTdFree(uint8 tdHandle) ; +uint8 CyDmaTdFreeCount(void) ; +cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) ; +cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) ; +cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ; +cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ; + + +/*************************************** +* Data Struct Definitions +***************************************/ + +typedef struct dmac_ch_struct +{ + volatile uint8 basic_cfg[4]; + volatile uint8 action[4]; + volatile uint8 basic_status[4]; + volatile uint8 reserved[4]; + +} dmac_ch; + + +typedef struct dmac_cfgmem_struct +{ + volatile uint8 CFG0[4]; + volatile uint8 CFG1[4]; + +} dmac_cfgmem; + + +typedef struct dmac_tdmem_struct +{ + volatile uint8 TD0[4]; + volatile uint8 TD1[4]; + +} dmac_tdmem; + + +typedef struct dmac_tdmem2_struct +{ + volatile uint16 xfercnt; + volatile uint8 next_td_ptr; + volatile uint8 flags; + volatile uint16 src_adr; + volatile uint16 dst_adr; +} dmac_tdmem2; + + +/*************************************** +* API Constants +***************************************/ + +#define CY_DMA_INVALID_CHANNEL 0xFFu /* Invalid Channel ID */ +#define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */ +#define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */ + +#if(CY_PSOC3 || CY_PSOC5LP) + #define CY_DMA_DISABLE_TD 0xFEu +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +#define CY_DMA_TD_SIZE 0x08u + +/* The "u" was removed as workaround for Keil compiler bug */ +#define CY_DMA_TD_SWAP_EN 0x80 +#define CY_DMA_TD_SWAP_SIZE4 0x40 +#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20 +#define CY_DMA_TD_TERMIN_EN 0x10 +#define CY_DMA_TD_TERMOUT1_EN 0x08 +#define CY_DMA_TD_TERMOUT0_EN 0x04 +#define CY_DMA_TD_INC_DST_ADR 0x02 +#define CY_DMA_TD_INC_SRC_ADR 0x01 + +#define CY_DMA_NUMBEROF_TDS 128u +#define CY_DMA_NUMBEROF_CHANNELS ((uint8)(CYDEV_DMA_CHANNELS_AVAILABLE)) + +/* Action register bits */ +#define CY_DMA_CPU_REQ ((uint8)(1u << 0u)) +#define CY_DMA_CPU_TERM_TD ((uint8)(1u << 1u)) +#define CY_DMA_CPU_TERM_CHAIN ((uint8)(1u << 2u)) + +/* Basic Status register bits */ +#define CY_DMA_STATUS_CHAIN_ACTIVE ((uint8)(1u << 0u)) +#define CY_DMA_STATUS_TD_ACTIVE ((uint8)(1u << 1u)) + +/* DMA controller register error bits */ +#define CY_DMA_BUS_TIMEOUT (1u << 1u) +#define CY_DMA_UNPOP_ACC (1u << 2u) +#define CY_DMA_PERIPH_ERR (1u << 3u) + +/* Round robin bits */ +#define CY_DMA_ROUND_ROBIN_ENABLE ((uint8)(1u << 4u)) + + +/*************************************** +* Registers +***************************************/ + +#define CY_DMA_CFG_REG (*(reg32 *) CYREG_PHUB_CFG) +#define CY_DMA_CFG_PTR ( (reg32 *) CYREG_PHUB_CFG) + +#define CY_DMA_ERR_REG (*(reg32 *) CYREG_PHUB_ERR) +#define CY_DMA_ERR_PTR ( (reg32 *) CYREG_PHUB_ERR) + +#define CY_DMA_ERR_ADR_REG (*(reg32 *) CYREG_PHUB_ERR_ADR) +#define CY_DMA_ERR_ADR_PTR ( (reg32 *) CYREG_PHUB_ERR_ADR) + +#define CY_DMA_CH_STRUCT_REG (*(dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) +#define CY_DMA_CH_STRUCT_PTR ( (dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) + +#define CY_DMA_CFGMEM_STRUCT_REG (*(dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) +#define CY_DMA_CFGMEM_STRUCT_PTR ( (dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) + +#define CY_DMA_TDMEM_STRUCT_REG (*(dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) +#define CY_DMA_TDMEM_STRUCT_PTR ( (dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 +*******************************************************************************/ +#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL) +#define DMA_INVALID_TD (CY_DMA_INVALID_TD) +#define DMA_END_CHAIN_TD (CY_DMA_END_CHAIN_TD) +#define DMAC_TD_SIZE (CY_DMA_TD_SIZE) +#define TD_SWAP_EN (CY_DMA_TD_SWAP_EN) +#define TD_SWAP_SIZE4 (CY_DMA_TD_SWAP_SIZE4) +#define TD_AUTO_EXEC_NEXT (CY_DMA_TD_AUTO_EXEC_NEXT) +#define TD_TERMIN_EN (CY_DMA_TD_TERMIN_EN) +#define TD_TERMOUT1_EN (CY_DMA_TD_TERMOUT1_EN) +#define TD_TERMOUT0_EN (CY_DMA_TD_TERMOUT0_EN) +#define TD_INC_DST_ADR (CY_DMA_TD_INC_DST_ADR) +#define TD_INC_SRC_ADR (CY_DMA_TD_INC_SRC_ADR) +#define NUMBEROF_TDS (CY_DMA_NUMBEROF_TDS) +#define NUMBEROF_CHANNELS (CY_DMA_NUMBEROF_CHANNELS) +#define CPU_REQ (CY_DMA_CPU_REQ) +#define CPU_TERM_TD (CY_DMA_CPU_TERM_TD) +#define CPU_TERM_CHAIN (CY_DMA_CPU_TERM_CHAIN) +#define STATUS_CHAIN_ACTIVE (CY_DMA_STATUS_CHAIN_ACTIVE) +#define STATUS_TD_ACTIVE (CY_DMA_STATUS_TD_ACTIVE) +#define DMAC_BUS_TIMEOUT (CY_DMA_BUS_TIMEOUT) +#define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC) +#define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR) +#define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE) +#if(CY_PSOC3 || CY_PSOC5LP) + #define DMA_DISABLE_TD (CY_DMA_DISABLE_TD) +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +#define DMAC_CFG (CY_DMA_CFG_PTR) +#define DMAC_ERR (CY_DMA_ERR_PTR) +#define DMAC_ERR_ADR (CY_DMA_ERR_ADR_PTR) +#define DMAC_CH (CY_DMA_CH_STRUCT_PTR) +#define DMAC_CFGMEM (CY_DMA_CFGMEM_STRUCT_PTR) +#define DMAC_TDMEM (CY_DMA_TDMEM_STRUCT_PTR) + +#endif /* (CY_BOOT_CYDMAC_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c new file mode 100644 index 0000000..217f44a --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c @@ -0,0 +1,732 @@ +/******************************************************************************* +* File Name: CyFlash.c +* Version 3.40 +* +* Description: +* Provides an API for the FLASH/EEPROM. +* +* Note: +* This code is endian agnostic. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyFlash.h" + + +/******************************************************************************* +* Holds die temperature, updated by CySetTemp(). Used for flash writting. +* The first byte is the sign of the temperature (0 = negative, 1 = positive). +* The second byte is the magnitude. +*******************************************************************************/ +uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; + +#if(CYDEV_ECC_ENABLE == 0) + static uint8 * rowBuffer = 0; +#endif /* (CYDEV_ECC_ENABLE == 0) */ + + +static cystatus CySetTempInt(void); + + +/******************************************************************************* +* Function Name: CyFlash_Start +******************************************************************************** +* +* Summary: +* Enable the EEPROM/Flash. +* +* Note: For PSoC 5, this will enable both Flash and EEPROM. For PSoC 3 and +* PSOC 5LP this will enable only Flash. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyFlash_Start(void) +{ + #if(CY_PSOC5A) + + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_EE_MASK; + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_EE_MASK; + + #endif /* (CY_PSOC5A) */ + + #if(CY_PSOC3 || CY_PSOC5LP) + + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK; + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK; + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + CyDelayUs(CY_FLASH_EE_STARTUP_DELAY); +} + + +/******************************************************************************* +* Function Name: CyFlash_Stop +******************************************************************************** +* +* Summary: +* Disable the EEPROM/Flash. +* +* Note: +* PSoC 5: disable both Flash and EEPROM. +* PSoC 3 and PSOC 5LP: disable only Flash. Use CyEEPROM_Stop() to stop EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* This setting is ignored as long as the CPU is currently running. This will +* only take effect when the CPU is later disabled. +* +*******************************************************************************/ +void CyFlash_Stop(void) +{ + #if (CY_PSOC5A) + + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_EE_MASK)); + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_EE_MASK)); + + #endif /* (CY_PSOC5A) */ + + #if (CY_PSOC3 || CY_PSOC5LP) + + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK)); + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK)); + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ +} + + +/******************************************************************************* +* Function Name: CySetTempInt +******************************************************************************** +* +* Summary: +* Sends a command to the SPC to read the die temperature. Sets a global value +* used by the Write functions. This function must be called once before +* executing a series of Flash writing functions. +* +* Parameters: +* None +* +* Return: +* status: +* CYRET_SUCCESS - if successful +* CYRET_LOCKED - if Flash writing already in use +* CYRET_UNKNOWN - if there was an SPC error +* +*******************************************************************************/ +static cystatus CySetTempInt(void) +{ + cystatus status; + + /* Make sure SPC is powered */ + CySpcStart(); + + /* Plan for failure. */ + status = CYRET_UNKNOWN; + + if(CySpcLock() == CYRET_SUCCESS) + { + /* Write the command. */ + #if(CY_PSOC5A) + if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES, CY_TEMP_TIMER_PERIOD, CY_TEMP_CLK_DIV_SELECT)) + #else + if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES)) + #endif /* (CY_PSOC5A) */ + { + do + { + if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE) + { + status = CYRET_SUCCESS; + + while(CY_SPC_BUSY) + { + /* Spin until idle. */ + CyDelayUs(1u); + } + break; + } + + } while(CY_SPC_BUSY); + } + + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CySetTemp +******************************************************************************** +* +* Summary: +* This is a wraparound for CySetTempInt(). It is used to return second +* successful read of temperature value. +* +* Parameters: +* None +* +* Return: +* status: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if Flash writing already in use +* CYRET_UNKNOWN if there was an SPC error. +* +* uint8 dieTemperature[2]: +* Holds die temperature for the flash writting algorithm. The first byte is +* the sign of the temperature (0 = negative, 1 = positive). The second byte is +* the magnitude. +* +*******************************************************************************/ +cystatus CySetTemp(void) +{ + cystatus status = CySetTempInt(); + + if(status == CYRET_SUCCESS) + { + status = CySetTempInt(); + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CySetFlashEEBuffer +******************************************************************************** +* +* Summary: +* Sets the user supplied temporary buffer to store SPC data while performing +* flash and EEPROM commands. This buffer is only necessary when Flash ECC is +* disabled. +* +* Parameters: +* buffer: +* Address of block of memory to store temporary memory. The size of the block +* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE. +* +* Return: +* status: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if the buffer is NULL +* +*******************************************************************************/ +cystatus CySetFlashEEBuffer(uint8 * buffer) +{ + cystatus status = CYRET_SUCCESS; + + CySpcStart(); + + #if(CYDEV_ECC_ENABLE == 0) + + if(NULL == buffer) + { + status = CYRET_BAD_PARAM; + } + else if(CySpcLock() != CYRET_SUCCESS) + { + status = CYRET_LOCKED; + } + else + { + rowBuffer = buffer; + CySpcUnlock(); + } + + #else + + /* To supress the warning */ + buffer = buffer; + + #endif /* (CYDEV_ECC_ENABLE == 0u) */ + + return(status); +} + + +#if(CYDEV_ECC_ENABLE == 1) + + /******************************************************************************* + * Function Name: CyWriteRowData + ******************************************************************************** + * + * Summary: + * Sends a command to the SPC to load and program a row of data in flash. + * + * Parameters: + * arrayID: + * ID of the array to write. + * rowAddress: + * rowAddress of flash row to program. + * rowData: + * Array of bytes to write. + * + * Return: + * status: + * CYRET_SUCCESS if successful. + * CYRET_LOCKED if the SPC is already in use. + * CYRET_CANCELED if command not accepted + * CYRET_UNKNOWN if there was an SPC error. + * + *******************************************************************************/ + cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) + { + uint16 rowSize; + cystatus status; + + rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE; + status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize); + + return(status); + } + +#else + + /******************************************************************************* + * Function Name: CyWriteRowData + ******************************************************************************** + * + * Summary: + * Sends a command to the SPC to load and program a row of data in flash. + * + * Parameters: + * arrayID : ID of the array to write. + * rowAddress : rowAddress of flash row to program. + * rowData : Array of bytes to write. + * + * Return: + * status: + * CYRET_SUCCESS if successful. + * CYRET_LOCKED if the SPC is already in use. + * CYRET_CANCELED if command not accepted + * CYRET_UNKNOWN if there was an SPC error. + * + *******************************************************************************/ + cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) + { + uint8 i; + uint32 offset; + uint16 rowSize; + cystatus status; + + rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? \ + CYDEV_EEPROM_ROW_SIZE : \ + (CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE); + + if(rowSize != CYDEV_EEPROM_ROW_SIZE) + { + /* Save the ECC area. */ + offset = CYDEV_ECC_BASE + ((uint32) arrayId * CYDEV_ECC_SECTOR_SIZE) + + ((uint32) rowAddress * CYDEV_ECC_ROW_SIZE); + + for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++) + { + *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); + } + } + + /* Copy the rowdata to the temporary buffer. */ + #if(CY_PSOC3) + (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE); + #else + (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE); + #endif /* (CY_PSOC3) */ + + status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize); + + return(status); + } + +#endif /* (CYDEV_ECC_ENABLE == 0u) */ + + +#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + + /******************************************************************************* + * Function Name: CyWriteRowConfig + ******************************************************************************** + * + * Summary: + * Sends a command to the SPC to load and program a row of config data in flash. + * This function is only valid for Flash array IDs (not for EEPROM). + * + * Parameters: + * arrayId: + * ID of the array to write + * rowAddress: + * Address of the sector to erase. + * rowECC: + * Array of bytes to write. + * + * Return: + * status: + * CYRET_SUCCESS if successful. + * CYRET_LOCKED if the SPC is already in use. + * CYRET_CANCELED if command not accepted + * CYRET_UNKNOWN if there was an SPC error. + * + *******************************************************************************/ + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) + { + uint32 offset; + uint16 i; + cystatus status; + + /* Read the existing flash data. */ + offset = ((uint32) arrayId * CYDEV_FLS_SECTOR_SIZE) + + ((uint32) rowAddress * CYDEV_FLS_ROW_SIZE); + + #if (CYDEV_FLS_BASE != 0u) + offset += CYDEV_FLS_BASE; + #endif + + for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++) + { + rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); + } + + #if(CY_PSOC3) + (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (void *)((uint32)rowECC), (int16) CYDEV_ECC_ROW_SIZE); + #else + (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (const void *) rowECC, CYDEV_ECC_ROW_SIZE); + #endif /* (CY_PSOC3) */ + + status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE); + + return (status); + } + +#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + + + +/******************************************************************************* +* Function Name: CyWriteRowFull +******************************************************************************** +* Summary: +* Sends a command to the SPC to load and program a row of data in flash. +* rowData array is expected to contain Flash and ECC data if needed. +* +* Parameters: +* arrayId: FLASH or EEPROM array id. +* rowData: pointer to a row of data to write. +* rowNumber: Zero based number of the row. +* rowSize: Size of the row. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if the SPC is already in use. +* CYRET_CANCELED if command not accepted +* CYRET_UNKNOWN if there was an SPC error. +* +*******************************************************************************/ +cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \ + +{ + cystatus status; + + if(CySpcLock() == CYRET_SUCCESS) + { + /* Load row data into SPC internal latch */ + status = CySpcLoadRow(arrayId, rowData, rowSize); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Wait for SPC to finish and get SPC status */ + CyDelayUs(1u); + } + + /* Hide SPC status */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + + if(CYRET_SUCCESS == status) + { + /* Erase and program flash with the data from SPC interval latch */ + status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Wait for SPC to finish and get SPC status */ + CyDelayUs(1u); + } + + /* Hide SPC status */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + } + } + + } + + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyFlash_SetWaitCycles +******************************************************************************** +* +* Summary: +* Sets the number of clock cycles the cache will wait before it samples data +* coming back from Flash. This function must be called before increasing CPU +* clock frequency. It can optionally be called after lowering CPU clock +* frequency in order to improve CPU performance. +* +* Parameters: +* uint8 freq: +* Frequency of operation in Megahertz. +* +* Return: +* None +* +*******************************************************************************/ +void CyFlash_SetWaitCycles(uint8 freq) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /*************************************************************************** + * The number of clock cycles the cache will wait before it samples data + * coming back from Flash must be equal or greater to to the CPU frequency + * outlined in clock cycles. + ***************************************************************************/ + + #if (CY_PSOC3) + + if (freq <= 22u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else if (freq <= 44u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + + #endif /* (CY_PSOC3) */ + + + #if (CY_PSOC5A) + + if (freq <= 16u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else if (freq <= 33u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else if (freq <= 50u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + + #endif /* (CY_PSOC5A) */ + + + #if (CY_PSOC5LP) + + if (freq <= 16u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else if (freq <= 33u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else if (freq <= 50u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + + #endif /* (CY_PSOC5LP) */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +#if (CY_PSOC3 || CY_PSOC5LP) + + /******************************************************************************* + * Function Name: CyEEPROM_Start + ******************************************************************************** + * + * Summary: + * Enable the EEPROM. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CyEEPROM_Start(void) + { + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK; + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK; + } + + + /******************************************************************************* + * Function Name: CyEEPROM_Stop + ******************************************************************************** + * + * Summary: + * Disable the EEPROM. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CyEEPROM_Stop (void) + { + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK)); + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK)); + } + +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: CyEEPROM_ReadReserve +******************************************************************************** +* +* Summary: +* Request access to the EEPROM for reading and wait until access is available. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_ReadReserve(void) +{ + /* Make a request for PHUB to have access */ + *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ; + + while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK)) + { + /* Wait for acknowledgement from PHUB */ + } +} + + +/******************************************************************************* +* Function Name: CyEEPROM_ReadRelease +******************************************************************************** +* +* Summary: +* Release the read reservation of the EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_ReadRelease(void) +{ + *CY_FLASH_EE_SCR_PTR |= 0x00u; +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h new file mode 100644 index 0000000..a44e27d --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h @@ -0,0 +1,311 @@ +/******************************************************************************* +* File Name: CyFlash.h +* Version 3.40 +* +* Description: +* Provides the function definitions for the FLASH/EEPROM. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYFLASH_H) +#define CY_BOOT_CYFLASH_H + +#include "cydevice_trm.h" +#include "cytypes.h" +#include "CyLib.h" +#include "CySpc.h" + +#define CY_FLASH_DIE_TEMP_DATA_SIZE (2u) /* Die temperature data size */ + +extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; + + +/*************************************** +* API Constants +***************************************/ + +#define CY_FLASH_BASE (CYDEV_FLASH_BASE) +#define CY_FLASH_SIZE (CYDEV_FLS_SIZE) +#define CY_FLASH_SIZEOF_ARRAY (CYDEV_FLS_SECTOR_SIZE) +#define CY_FLASH_SIZEOF_ROW (CYDEV_FLS_ROW_SIZE) +#define CY_FLASH_SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) +#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE) +#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE) + +#define CY_EEPROM_BASE (CYDEV_EE_BASE) +#define CY_EEPROM_SIZE (CYDEV_EE_SIZE) +#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE) +#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE) +#define CY_EEPROM_NUMBER_ROWS (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE) +#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY) + + +#if !defined(CYDEV_FLS_BASE) + #define CYDEV_FLS_BASE CYDEV_FLASH_BASE +#endif /* !defined(CYDEV_FLS_BASE) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/* Flash Functions */ +void CyFlash_Start(void); +void CyFlash_Stop(void); +cystatus CySetTemp(void); +cystatus CySetFlashEEBuffer(uint8 * buffer); +cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, uint16 rowSize) \ + ; +cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData); + +#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \ + ; +#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + +void CyFlash_SetWaitCycles(uint8 freq) ; + +/* EEPROM Functions */ +#if (CY_PSOC3 || CY_PSOC5LP) + void CyEEPROM_Start(void) ; + void CyEEPROM_Stop(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void CyEEPROM_ReadReserve(void) ; +void CyEEPROM_ReadRelease(void) ; + + +/*************************************** +* Registers +***************************************/ + +#if (CY_PSOC5A) + + /* Active Power Mode Configuration Register 0 */ + #define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG0) + #define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) + + /* Alternate Active Power Mode Configuration Register 0 */ + #define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG0) + #define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) + +#endif /* (CY_PSOC5A) */ + + +#if (CY_PSOC3 || CY_PSOC5LP) + + /* Active Power Mode Configuration Register 12 */ + #define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12) + #define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12) + + /* Alternate Active Power Mode Configuration Register 12 */ + #define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12) + #define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12) + +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/* Cache Control Register */ +#if (CY_PSOC3) + + #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CR ) + #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CR ) + +#else + + #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) + #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) + +#endif /* (CY_PSOC3) */ + + +/* EEPROM Status & Control Register */ +#define CY_FLASH_EE_SCR_REG (* (reg8 *) CYREG_SPC_EE_SCR) +#define CY_FLASH_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR) + + + +/*************************************** +* Register Constants +***************************************/ + +/* Power Mode Masks */ +#if(CY_PSOC5A) + + #define CY_FLASH_PM_FLASH_EE_MASK (0x80u) + +#endif /* (CY_PSOC5A) */ + +#if (CY_PSOC3 || CY_PSOC5LP) + + #define CY_FLASH_PM_EE_MASK (0x10u) + #define CY_FLASH_PM_FLASH_MASK (0x01u) + +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/* Frequency Constants */ +#if (CY_PSOC3) + + #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u) + #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u) + #define CY_FLASH_GREATER_44MHz (0x03u) + +#endif /* (CY_PSOC3) */ + +#if (CY_PSOC5A) + + #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u) + #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u) + #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u) + #define CY_FLASH_GREATER_51MHz (0x00u) + +#endif /* (CY_PSOC5A) */ + +#if (CY_PSOC5LP) + + #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u) + #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u) + #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u) + #define CY_FLASH_GREATER_51MHz (0x00u) + +#endif /* (CY_PSOC5LP) */ + +#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u) +#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT))) +#define CY_FLASH_EE_STARTUP_DELAY (5u) + +#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u) +#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u) + + + +/* Default values for getting temperature. */ + +#define CY_TEMP_NUMBER_OF_SAMPLES (0x1u) +#define CY_TEMP_TIMER_PERIOD (0xFFFu) +#define CY_TEMP_CLK_DIV_SELECT (0x4u) +#define CY_TEMP_NUM_SAMPLES (1 << (CY_TEMP_NUMBER_OF_SAMPLES)) +#define CY_SPC_CLK_PERIOD (120u) /* nS */ +#define CY_SYS_ns_PER_TICK (1000u) +#define CY_FRM_EXEC_TIME (1000u) /* nS */ + +#define CY_GET_TEMP_TIME ((1 << (CY_TEMP_NUM_SAMPLES + 1)) * \ + (CY_SPC_CLK_PERIOD * CY_TEMP_CLK_DIV_SELECT) * \ + CY_TEMP_TIMER_PERIOD + CY_FRM_EXEC_TIME) + +#define CY_TEMP_MAX_WAIT ((CY_GET_TEMP_TIME) / CY_SYS_ns_PER_TICK) /* In system ticks. */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 +*******************************************************************************/ +#define FLASH_SIZE (CY_FLASH_SIZE) +#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY) +#define FLASH_NUMBER_ROWS (CY_FLASH_NUMBER_ROWS) +#define FLASH_NUMBER_SECTORS (CY_FLASH_NUMBER_ARRAYS) +#define EEPROM_SIZE (CY_EEPROM_SIZE) +#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY) +#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS) +#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS) +#define CY_EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS) +#define CY_EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 +*******************************************************************************/ +#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR) + +#define TEMP_NUMBER_OF_SAMPLES (CY_TEMP_NUMBER_OF_SAMPLES) +#define TEMP_TIMER_PERIOD (CY_TEMP_TIMER_PERIOD) +#define TEMP_CLK_DIV_SELECT (CY_TEMP_CLK_DIV_SELECT) +#define NUM_SAMPLES (CY_TEMP_NUM_SAMPLES) +#define SPC_CLK_PERIOD (CY_SPC_CLK_PERIOD) +#define FRM_EXEC_TIME (CY_FRM_EXEC_TIME) +#define GET_TEMP_TIME (CY_GET_TEMP_TIME) +#define TEMP_MAX_WAIT (CY_TEMP_MAX_WAIT) + +#define ECC_ADDR (0x80u) + + +#if (CY_PSOC5A) + + #define PM_ACT_EEFLASH (CY_FLASH_PM_ACT_EEFLASH_PTR) + #define PM_STBY_EEFLASH (CY_FLASH_PM_ALTACT_EEFLASH_PTR) + +#endif /* (CY_PSOC5A) */ + +#if (CY_PSOC3 || CY_PSOC5LP) + + #define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) + #define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) + + #define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) + #define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) + +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +#if(CY_PSOC5A) + + #define PM_FLASH_EE_MASK (CY_FLASH_PM_FLASH_EE_MASK) + +#endif /* (CY_PSOC5A) */ + +#if (CY_PSOC3 || CY_PSOC5LP) + + #define PM_EE_MASK (CY_FLASH_PM_EE_MASK) + #define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK) + +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +#define FLASH_CYCLES_MASK_SHIFT (CY_FLASH_CYCLES_MASK_SHIFT) +#define FLASH_CYCLES_MASK (CY_FLASH_CYCLES_MASK) + + +#if (CY_PSOC3) + + #define LESSER_OR_EQUAL_22MHz (CY_FLASH_LESSER_OR_EQUAL_22MHz) + #define LESSER_OR_EQUAL_44MHz (CY_FLASH_LESSER_OR_EQUAL_44MHz) + #define GREATER_44MHz (CY_FLASH_GREATER_44MHz) + +#endif /* (CY_PSOC3) */ + +#if (CY_PSOC5A) + + #define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz) + #define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz) + #define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz) + #define GREATER_51MHz (CY_FLASH_GREATER_51MHz) + +#endif /* (CY_PSOC5A) */ + +#if (CY_PSOC5LP) + + #define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz) + #define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz) + #define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz) + #define LESSER_OR_EQUAL_67MHz (CY_FLASH_LESSER_OR_EQUAL_67MHz) + #define GREATER_67MHz (CY_FLASH_GREATER_67MHz) + #define GREATER_51MHz (CY_FLASH_GREATER_51MHz) + +#endif /* (CY_PSOC5LP) */ + +#define AHUB_EE_REQ_ACK_PTR (CY_FLASH_EE_SCR_PTR) + + +#endif /* (CY_BOOT_CYFLASH_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c new file mode 100644 index 0000000..4f56380 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c @@ -0,0 +1,2846 @@ +/******************************************************************************* +* File Name: CyLib.c +* Version 3.40 +* +* Description: +* Provides system API for the clocking, interrupts and watchdog timer. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyLib.h" + + +/******************************************************************************* +* The CyResetStatus variable is used to obtain value of RESET_SR0 register after +* a device reset. +*******************************************************************************/ +uint8 CYXDATA CyResetStatus; + + +#if(!CY_PSOC5A) + + /* Variable Vdda */ + #if(CYDEV_VARIABLE_VDDA == 1) + + uint8 CyScPumpEnabled = (uint8)(CYDEV_VDDA_MV < 2700); + + #endif /* (CYDEV_VARIABLE_VDDA == 1) */ + +#endif /* (!CY_PSOC5A) */ + + +/* Do not use these definitions directly in your application */ +uint32 cydelay_freq_hz = BCLK__BUS_CLK__HZ; +uint32 cydelay_freq_khz = (BCLK__BUS_CLK__HZ + 999u) / 1000u; +uint8 cydelay_freq_mhz = (uint8)((BCLK__BUS_CLK__HZ + 999999u) / 1000000u); +uint32 cydelay_32k_ms = 32768u * ((BCLK__BUS_CLK__HZ + 999u) / 1000u); + + +/* Function Prototypes */ +static uint8 CyUSB_PowerOnCheck(void) ; +static void CyIMO_SetTrimValue(uint8 freq) ; +static void CyBusClk_Internal_SetDivider(uint16 divider); + + +/******************************************************************************* +* Function Name: CyPLL_OUT_Start +******************************************************************************** +* +* Summary: +* Enables the PLL. Optionally waits for it to become stable. +* Waits at least 250 us or until it is detected that the PLL is stable. +* +* Parameters: +* wait: +* 0: Return immediately after configuration +* 1: Wait for PLL lock or timeout. +* +* Return: +* Status +* CYRET_SUCCESS - Completed successfully +* CYRET_TIMEOUT - Timeout occurred without detecting a stable clock. +* If the input source of the clock is jittery, then the lock indication +* may not occur. However, after the timeout has expired the generated PLL +* clock can still be used. +* +* Side Effects: +* If wait is enabled: This function wses the Fast Time Wheel to time the wait. +* Any other use of the Fast Time Wheel will be stopped during the period of +* this function and then restored. This function also uses the 100 KHz ILO. +* If not enabled, this function will enable the 100 KHz ILO for the period of +* this function. +* +* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or +* Once Per Second interrupt may be made by interrupt routines during the period +* of this function execution. The current operation of the ILO, Central Time +* Wheel and Once Per Second interrupt are maintained during the operation of +* this function provided the reading of the Power Manager Interrupt Status +* Register is only done using the CyPmReadStatus() function. +* +*******************************************************************************/ +cystatus CyPLL_OUT_Start(uint8 wait) +{ + cystatus status = CYRET_SUCCESS; + + uint8 iloEnableState; + uint8 pmTwCfg0State; + uint8 pmTwCfg2State; + + + /* Enables the PLL circuit */ + CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE; + + if(wait != 0u) + { + /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ + iloEnableState = SLOWCLK_ILO_CR0; + pmTwCfg0State = CY_PM_TW_CFG0_REG; + pmTwCfg2State = CY_PM_TW_CFG2_REG; + + CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL); + + status = CYRET_TIMEOUT; + + + while(CyPmReadStatus(CY_PM_FTW_INT) != CY_PM_FTW_INT) + { + /* Wait for the interrupt status */ + if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) + { + if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) + { + status = CYRET_SUCCESS; + break; + } + } + } + + + /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ + if(0u == (iloEnableState & ILO_CONTROL_100KHZ_ON)) + { + CyILO_Stop100K(); + } + CY_PM_TW_CFG0_REG = pmTwCfg0State; + CY_PM_TW_CFG2_REG = pmTwCfg2State; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_Stop +******************************************************************************** +* +* Summary: +* Disables the PLL. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyPLL_OUT_Stop(void) +{ + CY_CLK_PLL_CFG0_REG &= ((uint8)(~CY_CLK_PLL_ENABLE)); +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_SetPQ +******************************************************************************** +* +* Summary: +* Sets the P and Q dividers and the charge pump current. +* The Frequency Out will be P/Q * Frequency In. +* The PLL must be disabled before calling this function. +* +* Parameters: +* uint8 pDiv: +* Valid range [8 - 255]. +* +* uint8 qDiv: +* Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz. + +* uint8 current: +* Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and +* datasheet for more information. +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) +{ + /* Halt CPU in debug mode if PLL is enabled */ + CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); + + if((pDiv >= CY_CLK_PLL_MIN_P_VALUE ) && + (qDiv <= CY_CLK_PLL_MAX_Q_VALUE ) && (qDiv >= CY_CLK_PLL_MIN_Q_VALUE ) && + (current >= CY_CLK_PLL_MIN_CUR_VALUE) && (current <= CY_CLK_PLL_MAX_CUR_VALUE)) + { + /* Set new values */ + CY_CLK_PLL_P_REG = pDiv; + CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u)); + CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) | + ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION)); + } + else + { + /*********************************************************************** + * Halt CPU in debug mode if: + * - P divider is less than required + * - Q divider is out of range + * - pump current is out of range + ***********************************************************************/ + CYASSERT(0u != 0u); + } + +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_SetSource +******************************************************************************** +* +* Summary: +* Sets the input clock source to the PLL. The PLL must be disabled before +* calling this function. +* +* Parameters: +* source: One of the three available PLL clock sources +* 0 : IMO +* 1 : MHz Crystal +* 2 : DSI +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyPLL_OUT_SetSource(uint8 source) +{ + /* Halt CPU in debug mode if PLL is enabled */ + CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); + + switch(source) + { + case CY_PLL_SOURCE_IMO: + case CY_PLL_SOURCE_XTAL: + case CY_PLL_SOURCE_DSI: + CY_LIB_CLKDIST_CR_REG = ((CY_LIB_CLKDIST_CR_REG & CY_LIB_CLKDIST_CR_PLL_SCR_MASK) | source); + break; + + default: + CYASSERT(0u != 0u); + break; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_Start +******************************************************************************** +* +* Summary: +* Enables the IMO. Optionally waits at least 6 us for it to settle. +* +* Parameters: +* uint8 wait: +* 0: Return immediately after configuration +* 1: Wait for at least 6 us for the IMO to settle. +* +* Return: +* None +* +* Side Effects: +* If wait is enabled: This function wses the Fast Time Wheel to time the wait. +* Any other use of the Fast Time Wheel will be stopped during the period of +* this function and then restored. This function also uses the 100 KHz ILO. +* If not enabled, this function will enable the 100 KHz ILO for the period of +* this function. +* +* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or +* Once Per Second interrupt may be made by interrupt routines during the period +* of this function execution. The current operation of the ILO, Central Time +* Wheel and Once Per Second interrupt are maintained during the operation of +* this function provided the reading of the Power Manager Interrupt Status +* Register is only done using the CyPmReadStatus() function. +* +*******************************************************************************/ +void CyIMO_Start(uint8 wait) +{ + uint8 pmFtwCfg2Reg; + uint8 pmFtwCfg0Reg; + uint8 iloControlReg; + + /* Set the bit to enable the clock. */ + PM_ACT_CFG0 |= IMO_PM_ENABLE; + + /* Wait for 6 us */ + if(0u != wait) + { + /* Need to turn on the 100KHz ILO if it happens to not already be running.*/ + iloControlReg = SLOWCLK_ILO_CR0; + + if(0u == (iloControlReg & ILO_CONTROL_100KHZ_ON)) + { + CyILO_Start100K(); + } + + /* Use ILO 100 KHz */ + pmFtwCfg2Reg = PM_TW_CFG2; + pmFtwCfg0Reg = PM_TW_CFG0; + + /* FTW_EN (bit 0) must be clear to change the period*/ + PM_TW_CFG2 &= FTW_CLEAR_FTW_BITS; + + /* Set the FTW interval of 1 100KHz ILO clocks + Should result in status getting set at a (100/1)KHz rate*/ + PM_TW_CFG0 = 0u; + + /* Enable FTW, but not the interrupt */ + PM_TW_CFG2 = FTW_ENABLE; + + /* Read FTW value */ + while (CyPmReadStatus(CY_PM_FTW_INT) == 0u) + { + /* Wait for the interrupt status */ + } + + /* Reset the clock */ + if(0u == (iloControlReg & ILO_CONTROL_100KHZ_ON)) + { + CyILO_Stop100K(); + } + + /* Restore the FTW */ + PM_TW_CFG0 = pmFtwCfg0Reg; + PM_TW_CFG2 = pmFtwCfg2Reg; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_Stop +******************************************************************************** +* +* Summary: +* Disables the IMO. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyIMO_Stop(void) +{ + /* Clear the bit to disable the clock. */ + PM_ACT_CFG0 &= ((uint8)(~IMO_PM_ENABLE)); +} + + +/******************************************************************************* +* Function Name: CyUSB_PowerOnCheck +******************************************************************************** +* +* Summary: +* Returns the USB power status value. A private function to cy_boot. +* +* Parameters: +* None +* +* Return: +* uint8: one if the USB is enabled, 0 if not enabled. +* +*******************************************************************************/ +static uint8 CyUSB_PowerOnCheck(void) +{ + uint8 poweredOn = 0u; + + /* Check whether device is in Active or AltActiv and if USB is powered on */ + if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) && + (0u != (CY_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) || + (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) && + (0u != (CY_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED)))) + { + poweredOn = 1u; + } + + return (poweredOn); +} + + +/******************************************************************************* +* Function Name: CyIMO_SetTrimValue +******************************************************************************** +* +* Summary: +* Sets the IMO factory trim values. +* +* Parameters: +* uint8 freq - frequency for which trims must be set +* +* Return: +* None +* +*******************************************************************************/ +static void CyIMO_SetTrimValue(uint8 freq) +{ + uint8 usb_power_on = CyUSB_PowerOnCheck(); + + /* If USB is powered */ + if(usb_power_on == 1u) + { + /* Unlock USB write */ + CY_USB_CR1 &= ((uint8)(~CLOCK_USB_ENABLE)); + } + switch(freq) + { + case CY_IMO_FREQ_3MHZ: + IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_3MHZ_PTR); + break; + + case CY_IMO_FREQ_6MHZ: + IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_6MHZ_PTR); + break; + + case CY_IMO_FREQ_12MHZ: + IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_12MHZ_PTR); + break; + + case CY_IMO_FREQ_24MHZ: + IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_24MHZ_PTR); + break; + + case CY_IMO_FREQ_48MHZ: + IMO_TR1 = CY_GET_XTND_REG8(FLSHID_MFG_CFG_IMO_TR1_PTR); + break; + + /* The IMO frequencies above 48 MHz are not supported by PSoC5 */ + #if(!CY_PSOC5A) + + case CY_IMO_FREQ_62MHZ: + IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_67MHZ_PTR); + break; + + #endif /* (!CY_PSOC5A) */ + + case CY_IMO_FREQ_USB: + IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_USB_PTR); + + /* If USB is powered */ + if(usb_power_on == 1u) + { + /* Lock the USB Oscillator */ + CY_USB_CR1 |= CLOCK_USB_ENABLE; + } + break; + + default: + CYASSERT(0u != 0u); + break; + } + +} + + +/******************************************************************************* +* Function Name: CyIMO_SetFreq +******************************************************************************** +* +* Summary: +* Sets the frequency of the IMO. Changes may be made while the IMO is running. +* +* Parameters: +* freq: Frequency of IMO operation +* CY_IMO_FREQ_3MHZ to set 3 MHz +* CY_IMO_FREQ_6MHZ to set 6 MHz +* CY_IMO_FREQ_12MHZ to set 12 MHz +* CY_IMO_FREQ_24MHZ to set 24 MHz +* CY_IMO_FREQ_48MHZ to set 48 MHz +* CY_IMO_FREQ_62MHZ to set 62 MHz (unsupported by PSoC 5) +* CY_IMO_FREQ_USB to set 24 MHz (Trimmed for USB operation) +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +* When the USB setting is chosen, the USB clock locking circuit is enabled. +* Otherwise this circuit is disabled. The USB block must be powered before +* selecting the USB setting. +* +*******************************************************************************/ +void CyIMO_SetFreq(uint8 freq) +{ + uint8 currentFreq; + uint8 nextFreq; + + /*************************************************************************** + * When changing the IMO frequency the Trim values must also be set + * accordingly.This requires reading the current frequency. If the new + * frequency is faster, then set the new trim and then change the frequency, + * otherwise change the frequency and then set the new trim values. + ***************************************************************************/ + + currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK)); + + /* Check if the requested frequency is USB. */ + nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq; + + switch (currentFreq) + { + case 0u: + currentFreq = CY_IMO_FREQ_12MHZ; + break; + + case 1u: + currentFreq = CY_IMO_FREQ_6MHZ; + break; + + case 2u: + currentFreq = CY_IMO_FREQ_24MHZ; + break; + + case 3u: + currentFreq = CY_IMO_FREQ_3MHZ; + break; + + case 4u: + currentFreq = CY_IMO_FREQ_48MHZ; + break; + + /* The IMO frequencies above 48 MHz are not supported by PSoC5 */ + #if(!CY_PSOC5A) + + case 5u: + currentFreq = CY_IMO_FREQ_62MHZ; + break; + + #endif /* (!CY_PSOC5A) */ + + default: + CYASSERT(0u != 0u); + break; + } + + if (nextFreq >= currentFreq) + { + /* Set the new trim first */ + CyIMO_SetTrimValue(freq); + } + + /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */ + switch(freq) + { + case CY_IMO_FREQ_3MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CLOCK_IMO_3MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_6MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CLOCK_IMO_6MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_12MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CLOCK_IMO_12MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_24MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CLOCK_IMO_24MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_48MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CLOCK_IMO_48MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET)); + break; + + /* The IMO frequencies above 48 MHz are not supported by PSoC5 */ + #if(!CY_PSOC5A) + + case CY_IMO_FREQ_62MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CLOCK_IMO_62MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET)); + break; + + #endif /* (!CY_PSOC5A) */ + + case CY_IMO_FREQ_USB: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CLOCK_IMO_24MHZ_VALUE) | FASTCLK_IMO_USBCLK_ON_SET; + break; + + default: + CYASSERT(0u != 0u); + break; + } + + /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */ + if (freq == CY_IMO_FREQ_USB) + { + CyIMO_EnableDoubler(); + } + else + { + CyIMO_DisableDoubler(); + } + + if (nextFreq < currentFreq) + { + /* Set the new trim after setting the frequency */ + CyIMO_SetTrimValue(freq); + } +} + + +/******************************************************************************* +* Function Name: CyIMO_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the clock output from the IMO block. +* +* The output from the IMO is by default the IMO itself. Optionally the MHz +* Crystal or a DSI input can be the source of the IMO output instead. +* +* Parameters: +* source, CY_IMO_SOURCE_DSI to set the DSI as source. +* CY_IMO_SOURCE_XTAL to set the MHz as source. +* CY_IMO_SOURCE_IMO to set the IMO itself. +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyIMO_SetSource(uint8 source) +{ + switch(source) + { + case CY_IMO_SOURCE_DSI: + CY_LIB_CLKDIST_CR_REG &= ((uint8)(~CY_LIB_CLKDIST_CR_IMO2X)); + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; + break; + + case CY_IMO_SOURCE_XTAL: + CY_LIB_CLKDIST_CR_REG |= CY_LIB_CLKDIST_CR_IMO2X; + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; + break; + + case CY_IMO_SOURCE_IMO: + CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO)); + break; + + default: + /* Incorrect source value */ + CYASSERT(0u != 0u); + break; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_EnableDoubler +******************************************************************************** +* +* Summary: +* Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz +* input to a 48 MHz output for use by the USB block. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyIMO_EnableDoubler(void) +{ + /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */ + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER; +} + + +/******************************************************************************* +* Function Name: CyIMO_DisableDoubler +******************************************************************************** +* +* Summary: +* Disables the IMO doubler. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyIMO_DisableDoubler(void) +{ + CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_DOUBLER)); +} + + +/******************************************************************************* +* Function Name: CyMasterClk_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the master clock. +* +* Parameters: +* source: One of the four available Master clock sources. +* CY_MASTER_SOURCE_IMO +* CY_MASTER_SOURCE_PLL +* CY_MASTER_SOURCE_XTAL +* CY_MASTER_SOURCE_DSI +* +* Return: +* None +* +* Side Effects: +* The current source and the new source must both be running and stable before +* calling this function. +* +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyMasterClk_SetSource(uint8 source) +{ + #if(CY_PSOC5A) + + uint8 masterReg0; + + /* Read the current setting */ + masterReg0 = CY_LIB_CLKDIST_MSTR0_REG; + + /* Write a non-zero period to the master mux clock divider */ + if (masterReg0 == 0x00u) + { + CY_LIB_CLKDIST_MSTR0_REG = 3u; + } + + #endif /* (CY_PSOC5A) */ + + CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) | + (source & ((uint8)(~MASTER_CLK_SRC_CLEAR))); + + #if(CY_PSOC5A) + + /* Restore zero period (if desired) to the master mux clock divider */ + if (masterReg0 == 0x00u) + { + CY_LIB_CLKDIST_MSTR0_REG = 0u; + } + + #endif /* (CY_PSOC5A) */ +} + + +/******************************************************************************* +* Function Name: CyMasterClk_SetDivider +******************************************************************************** +* +* Summary: +* Sets the divider value used to generate Master Clock. +* +* Parameters: +* uint8 divider: +* Valid range [0-255]. The clock will be divided by this value + 1. +* For example to divide by 2 this parameter should be set to 1. +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +* When changing the Master or Bus clock divider value from div-by-n to div-by-1 +* the first clock cycle output after the div-by-1 can be up to 4 ns shorter +* than the final/expected div-by-1 period. +* +*******************************************************************************/ +void CyMasterClk_SetDivider(uint8 divider) +{ + CY_LIB_CLKDIST_MSTR0_REG = divider; +} + + +/******************************************************************************* +* Function Name: CyBusClk_Internal_SetDivider +******************************************************************************** +* +* Summary: +* Function used by CyBusClk_SetDivider(). For internal use only. +* +* Parameters: +* divider: Valid range [0-65535]. +* The clock will be divided by this value + 1. +* For example to divide by 2 this parameter should be set to 1. +* +* Return: +* None +* +*******************************************************************************/ +static void CyBusClk_Internal_SetDivider(uint16 divider) +{ + /* Mask bits to enable shadow loads */ + CY_LIB_CLKDIST_AMASK_REG &= CY_LIB_CLKDIST_AMASK_MASK; + CY_LIB_CLKDIST_DMASK_REG = CY_LIB_CLKDIST_DMASK_MASK; + + /* Enable mask bits to enable shadow loads */ + CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK; + + /* Update Shadow Divider Value Register with the new divider */ + CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider); + CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider); + + + /*************************************************************************** + * Copy shadow value defined in Shadow Divider Value Register + * (CY_LIB_CLKDIST_WRK_LSB_REG and CY_LIB_CLKDIST_WRK_MSB_REG) to all + * dividers selected in Analog and Digital Clock Mask Registers + * (CY_LIB_CLKDIST_AMASK_REG and CY_LIB_CLKDIST_DMASK_REG). + ***************************************************************************/ + CY_LIB_CLKDIST_LD_REG |= CY_LIB_CLKDIST_LD_LOAD; +} + + +/******************************************************************************* +* Function Name: CyBusClk_SetDivider +******************************************************************************** +* +* Summary: +* Sets the divider value used to generate Bus Clock. +* +* Parameters: +* divider: Valid range [0-65535]. The clock will be divided by this value + 1. +* For example to divide by 2 this parameter should be set to 1. +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyBusClk_SetDivider(uint16 divider) +{ + uint8 masterClkDiv; + uint16 busClkDiv; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Work around to set the bus clock divider value */ + busClkDiv = ((uint16)(((uint16)(CY_LIB_CLKDIST_BCFG_MSB_REG)) << 8u)) | CY_LIB_CLKDIST_BCFG_LSB_REG; + + if ((divider == 0u) || (busClkDiv == 0u)) + { + /* Save away the master clock divider value */ + masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG; + + if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV) + { + /* Set master clock divider to 7 */ + CyMasterClk_SetDivider(CY_LIB_CLKDIST_MASTERCLK_DIV); + } + + if (divider == 0u) + { + /* Set the SSS bit and the divider register desired value */ + CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS; + CyBusClk_Internal_SetDivider(divider); + } + else + { + CyBusClk_Internal_SetDivider(divider); + CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS)); + } + + /* Restore the master clock */ + CyMasterClk_SetDivider(masterClkDiv); + } + else + { + CyBusClk_Internal_SetDivider(divider); + } + + CyExitCriticalSection(interruptState); +} + + +#if(CY_PSOC3) + + /******************************************************************************* + * Function Name: CyCpuClk_SetDivider + ******************************************************************************** + * + * Summary: + * Sets the divider value used to generate the CPU Clock. Only applicable for + * PSoC 3 parts. + * + * Parameters: + * divider: Valid range [0-15]. The clock will be divided by this value + 1. + * For example to divide by 2 this parameter should be set to 1. + * + * Return: + * None + * + * Side Effects: + * If as result of this function execution the CPU clock frequency is increased + * then the number of clock cycles the cache will wait before it samples data + * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() + * with appropriate parameter. It can be optionally called if CPU clock + * frequency is lowered in order to improve CPU performance. + * See CyFlash_SetWaitCycles() description for more information. + * + *******************************************************************************/ + void CyCpuClk_SetDivider(uint8 divider) + { + CLKDIST_MSTR1 = (CLKDIST_MSTR1 & CLKDIST_MSTR1_DIV_CLEAR) | + ((uint8)(divider << CLKDIST_DIV_POSITION)); + } + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyUsbClk_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the USB clock. +* +* Parameters: +* source: One of the four available USB clock sources +* USB_CLK_IMO2X - IMO 2x +* USB_CLK_IMO - IMO +* USB_CLK_PLL - PLL +* USB_CLK_DSI - DSI +* +* Return: +* None +* +*******************************************************************************/ +void CyUsbClk_SetSource(uint8 source) +{ + CLKDIST_UCFG = (CLKDIST_UCFG & ((uint8)(~USB_CLKDIST_CONFIG_MASK))) | + (USB_CLKDIST_CONFIG_MASK & source); +} + + +/******************************************************************************* +* Function Name: CyILO_Start1K +******************************************************************************** +* +* Summary: +* Enables the ILO 1 KHz oscillator. +* +* Note The ILO 1 KHz oscillator is always enabled by default, regardless of the +* selection in the Clock Editor. Therefore, this API is only needed if the +* oscillator was turned off manually. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Start1K(void) +{ + /* Set the bit 1 of ILO RS */ + SLOWCLK_ILO_CR0 |= ILO_CONTROL_1KHZ_ON; +} + + +/******************************************************************************* +* Function Name: CyILO_Stop1K +******************************************************************************** +* +* Summary: +* Disables the ILO 1 KHz oscillator. +* +* Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power +* mode APIs are expected to be used. For more information, refer to the Power +* Management section of this document. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality. +* +*******************************************************************************/ +void CyILO_Stop1K(void) +{ + /* Clear the bit 1 of ILO RS */ + SLOWCLK_ILO_CR0 &= ((uint8)(~ILO_CONTROL_1KHZ_ON)); +} + + +/******************************************************************************* +* Function Name: CyILO_Start100K +******************************************************************************** +* +* Summary: +* Enables the ILO 100 KHz oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Start100K(void) +{ + /* Set the bit 2 of ILO RS */ + SLOWCLK_ILO_CR0 |= ILO_CONTROL_100KHZ_ON; +} + + +/******************************************************************************* +* Function Name: CyILO_Stop100K +******************************************************************************** +* +* Summary: +* Disables the ILO 100 KHz oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Stop100K(void) +{ + /* Clear the bit 2 of ILO RS */ + SLOWCLK_ILO_CR0 &= ((uint8)(~ILO_CONTROL_100KHZ_ON)); +} + + +/******************************************************************************* +* Function Name: CyILO_Enable33K +******************************************************************************** +* +* Summary: +* Enables the ILO 33 KHz divider. +* +* Note that the 33 KHz clock is generated from the 100 KHz oscillator, +* so it must also be running in order to generate the 33 KHz output. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Enable33K(void) +{ + /* Set the bit 5 of ILO RS */ + SLOWCLK_ILO_CR0 |= ILO_CONTROL_33KHZ_ON; +} + + +/******************************************************************************* +* Function Name: CyILO_Disable33K +******************************************************************************** +* +* Summary: +* Disables the ILO 33 KHz divider. +* +* Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this +* API does not disable the 100 KHz clock. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Disable33K(void) +{ + /* Clear the bit 5 of ILO RS */ + SLOWCLK_ILO_CR0 &= ((uint8)(~ILO_CONTROL_33KHZ_ON)); +} + + +/******************************************************************************* +* Function Name: CyILO_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the clock output from the ILO block. +* +* Parameters: +* source: One of the three available ILO output sources +* Value Define Source +* 0 CY_ILO_SOURCE_100K ILO 100 KHz +* 1 CY_ILO_SOURCE_33K ILO 33 KHz +* 2 CY_ILO_SOURCE_1K ILO 1 KHz +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_SetSource(uint8 source) +{ + CLKDIST_CR = (CLKDIST_CR & CY_ILO_SOURCE_BITS_CLEAR) | + (((uint8) (source << 2u)) & ((uint8)(~CY_ILO_SOURCE_BITS_CLEAR))); +} + + +/******************************************************************************* +* Function Name: CyILO_SetPowerMode +******************************************************************************** +* +* Summary: +* Sets the power mode used by the ILO during power down. Allows for lower power +* down power usage resulting in a slower startup time. +* +* Parameters: +* uint8 mode +* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down +* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down +* +* Return: +* Prevous power mode state. +* +*******************************************************************************/ +uint8 CyILO_SetPowerMode(uint8 mode) +{ + uint8 state; + + /* Get current state. */ + state = SLOWCLK_ILO_CR0; + + /* Set the the oscillator power mode. */ + if(mode != CY_ILO_FAST_START) + { + SLOWCLK_ILO_CR0 = (state | ILO_CONTROL_PD_MODE); + } + else + { + SLOWCLK_ILO_CR0 = (state & ((uint8)(~ILO_CONTROL_PD_MODE))); + } + + /* Return the old mode. */ + return ((state & ILO_CONTROL_PD_MODE) >> ILO_CONTROL_PD_POSITION); +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_Start +******************************************************************************** +* +* Summary: +* Enables the 32 KHz Crystal Oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_32KHZ_Start(void) +{ + volatile uint16 i; + + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_STARTUP; + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + + #if(CY_PSOC3) + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN; + #endif /* (CY_PSOC3) */ + + /* Enable operation of the 32K Crystal Oscillator */ + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN; + + for (i = 1000u; i > 0u; i--) + { + if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT)) + { + /* Ready - switch to the hign power mode */ + (void) CyXTAL_32KHZ_SetPowerMode(0u); + + break; + } + CyDelayUs(1u); + } +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_Stop +******************************************************************************** +* +* Summary: +* Disables the 32KHz Crystal Oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_32KHZ_Stop(void) +{ + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_POWERDOWN; + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | CY_CLK_XTAL32_CFG_LP_DEFAULT; + CY_CLK_XTAL32_CR_REG &= ((uint8)(~(CY_CLK_XTAL32_CR_EN | CY_CLK_XTAL32_CR_LPM))); + + #if(CY_PSOC3) + CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_PDBEN)); + #endif /* (CY_PSOC3) */ +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_ReadStatus +******************************************************************************** +* +* Summary: +* Returns status of the 32 KHz oscillator. +* +* Parameters: +* None +* +* Return: +* Value Define Source +* 20 CY_XTAL32K_ANA_STAT Analog measurement +* 1: Stable +* 0: Not stable +* +*******************************************************************************/ +uint8 CyXTAL_32KHZ_ReadStatus(void) +{ + return(CY_CLK_XTAL32_CR_REG & CY_XTAL32K_ANA_STAT); +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_SetPowerMode +******************************************************************************** +* +* Summary: +* Sets the power mode for the 32 KHz oscillator used during sleep mode. +* Allows for lower power during sleep when there are fewer sources of noise. +* During active mode the oscillator is always run in high power mode. +* +* Parameters: +* uint8 mode +* 0: High power mode +* 1: Low power mode during sleep +* +* Return: +* Previous power mode. +* +*******************************************************************************/ +uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) +{ + uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u; + + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + + if(1u == mode) + { + /* Low power mode during Sleep */ + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_LOW_POWER; + CyDelayUs(10u); + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | CY_CLK_XTAL32_CFG_LP_LOWPOWER; + CyDelayUs(20u); + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM; + } + else + { + /* High power mode */ + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_HIGH_POWER; + CyDelayUs(10u); + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | CY_CLK_XTAL32_CFG_LP_DEFAULT; + CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM)); + } + + return(state); +} + + +/******************************************************************************* +* Function Name: CyXTAL_Start +******************************************************************************** +* +* Summary: +* Enables the megahertz crystal. +* +* PSoC3: +* Waits until the XERR bit is low (no error) for a millisecond or until the +* number of milliseconds specified by the wait parameter has expired. +* +* PSoC5: +* Waits for CY_CLK_XMHZ_MIN_TIMEOUT milliseconds (or number of milliseconds +* specified by parameter if it is greater than CY_CLK_XMHZ_MIN_TIMEOUT. The +* XERR bit status is not checked. +* +* Parameters: +* wait: Valid range [0-255]. +* This is the timeout value in milliseconds. +* The appropriate value is crystal specific. +* +* Return: +* CYRET_SUCCESS - Completed successfully +* CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR. +* +* Side Effects and Restrictions: +* If wait is enabled (non-zero wait). Uses the Fast Timewheel to time the wait. +* Any other use of the Fast Timewheel (FTW) will be stopped during the period +* of this function and then restored. +* +* Uses the 100KHz ILO. If not enabled, this function will enable the 100KHz +* ILO for the period of this function. No changes to the setup of the ILO, +* Fast Timewheel, Central Timewheel or Once Per Second interrupt may be made +* by interrupt routines during the period of this function. +* +* The current operation of the ILO, Central Timewheel and Once Per Second +* interrupt are maintained during the operation of this function provided the +* reading of the Power Manager Interrupt Status Register is only done using the +* CyPmReadStatus() function. +* +*******************************************************************************/ +cystatus CyXTAL_Start(uint8 wait) +{ + cystatus status = CYRET_SUCCESS; + + #if(CY_PSOC5A) + volatile uint8 timeout = (wait < CY_CLK_XMHZ_MIN_TIMEOUT) ? CY_CLK_XMHZ_MIN_TIMEOUT : wait; + #else + volatile uint8 timeout = wait; + #endif /* (CY_PSOC5A) */ + + volatile uint8 count; + uint8 iloEnableState; + uint8 pmTwCfg0Tmp; + uint8 pmTwCfg2Tmp; + + + /* Enables the MHz crystal oscillator circuit */ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE; + + + if(wait > 0u) + { + /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ + iloEnableState = SLOWCLK_ILO_CR0; + pmTwCfg0Tmp = CY_PM_TW_CFG0_REG; + pmTwCfg2Tmp = CY_PM_TW_CFG2_REG; + + /* Set 250 us interval */ + CyPmFtwSetInterval(CY_CLK_XMHZ_FTW_INTERVAL); + status = CYRET_TIMEOUT; + + + for( ; timeout > 0u; timeout--) + { + #if(!CY_PSOC5A) + + /* Read XERR bit to clear it */ + (void) CY_CLK_XMHZ_CSR_REG; + + #endif /* (!CY_PSOC5A) */ + + + /* Wait for a millisecond - 4 x 250 us */ + for(count = 4u; count > 0u; count--) + { + while(!(CY_PM_FTW_INT == CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for the FTW interrupt event */ + } + } + + + #if(!CY_PSOC5A) + + /******************************************************************* + * High output indicates oscillator failure. + * Only can be used after start-up interval (1 ms) is completed. + *******************************************************************/ + if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) + { + status = CYRET_SUCCESS; + break; + } + + #endif /* (!CY_PSOC5A) */ + } + + + /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ + if(0u == (iloEnableState & ILO_CONTROL_100KHZ_ON)) + { + CyILO_Stop100K(); + } + CY_PM_TW_CFG0_REG = pmTwCfg0Tmp; + CY_PM_TW_CFG2_REG = pmTwCfg2Tmp; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyXTAL_Stop +******************************************************************************** +* +* Summary: +* Disables the megahertz crystal oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_Stop(void) +{ + /* Disable the the oscillator. */ + FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE)); +} + + +#if(!CY_PSOC5A) + + /******************************************************************************* + * Function Name: CyXTAL_EnableErrStatus + ******************************************************************************** + * + * Summary: + * Enables the generation of the XERR status bit for the megahertz crystal. + * This function is not available for PSoC5. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CyXTAL_EnableErrStatus(void) + { + /* If oscillator has insufficient amplitude, XERR bit will be high. */ + CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB)); + } + + + /******************************************************************************* + * Function Name: CyXTAL_DisableErrStatus + ******************************************************************************** + * + * Summary: + * Disables the generation of the XERR status bit for the megahertz crystal. + * This function is not available for PSoC5. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CyXTAL_DisableErrStatus(void) + { + /* If oscillator has insufficient amplitude, XERR bit will be high. */ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB; + } + + + /******************************************************************************* + * Function Name: CyXTAL_ReadStatus + ******************************************************************************** + * + * Summary: + * Reads the XERR status bit for the megahertz crystal. This status bit is a + * sticky clear on read value. This function is not available for PSoC5. + * + * Parameters: + * None + * + * Return: + * Status + * 0: No error + * 1: Error + * + *******************************************************************************/ + uint8 CyXTAL_ReadStatus(void) + { + /*************************************************************************** + * High output indicates oscillator failure. Only use this after start-up + * interval is completed. This can be used for status and failure recovery. + ***************************************************************************/ + return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u); + } + + + /******************************************************************************* + * Function Name: CyXTAL_EnableFaultRecovery + ******************************************************************************** + * + * Summary: + * Enables the fault recovery circuit which will switch to the IMO in the case + * of a fault in the megahertz crystal circuit. The crystal must be up and + * running with the XERR bit at 0, before calling this function to prevent + * immediate fault switchover. This function is not available for PSoC5. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CyXTAL_EnableFaultRecovery(void) + { + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT; + } + + + /******************************************************************************* + * Function Name: CyXTAL_DisableFaultRecovery + ******************************************************************************** + * + * Summary: + * Disables the fault recovery circuit which will switch to the IMO in the case + * of a fault in the megahertz crystal circuit. This function is not available + * for PSoC5. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CyXTAL_DisableFaultRecovery(void) + { + CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT)); + } + +#endif /* (!CY_PSOC5A) */ + +/******************************************************************************* +* Function Name: CyXTAL_SetStartup +******************************************************************************** +* +* Summary: +* Sets the startup settings for the crystal. Logic model outputs a frequency +* (setting + 4) MHz when enabled. +* +* This is artificial as the actual frequency is determined by an attached +* external crystal. +* +* Parameters: +* setting: Valid range [0-31]. +* Value is dependent on the frequency and quality of the crystal being used. +* Refer to the device TRM and datasheet for more information. +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_SetStartup(uint8 setting) +{ + CY_CLK_XMHZ_CFG0_REG = (CY_CLK_XMHZ_CFG0_REG & ((uint8)(~CY_CLK_XMHZ_CFG0_XCFG_MASK))) | + (setting & CY_CLK_XMHZ_CFG0_XCFG_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + /******************************************************************************* + * Function Name: CyXTAL_SetFbVoltage + ******************************************************************************** + * + * Summary: + * Sets the feedback reference voltage to use for the crystal circuit. + * This function is only available for PSoC3 and PSoC 5LP. + * + * Parameters: + * setting: Valid range [0-15]. + * Refer to the device TRM and datasheet for more information. + * + * Return: + * None + * + *******************************************************************************/ + void CyXTAL_SetFbVoltage(uint8 setting) + { + CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) | + (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK)); + } + + + /******************************************************************************* + * Function Name: CyXTAL_SetWdVoltage + ******************************************************************************** + * + * Summary: + * Sets the reference voltage used by the watchdog to detect a failure in the + * crystal circuit. This function is only available for PSoC3 and PSoC 5LP. + * + * Parameters: + * setting: Valid range [0-7]. + * Refer to the device TRM and datasheet for more information. + * + * Return: + * None + * + *******************************************************************************/ + void CyXTAL_SetWdVoltage(uint8 setting) + { + CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) | + (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK)); + } + +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: CyHalt +******************************************************************************** +* +* Summary: +* Halts the CPU. +* +* Parameters: +* uint8 reason: Value to be used during debugging. +* +* Return: +* None +* +*******************************************************************************/ +void CyHalt(uint8 reason) CYREENTRANT +{ + if(0u != reason) + { + /* To remove unreferenced local variable warning */ + } + + #if defined (__ARMCC_VERSION) + __breakpoint(0x0); + #elif defined(__GNUC__) + __asm(" bkpt 1"); + #elif defined(__C51__) + CYDEV_HALT_CPU; + #endif /* (__ARMCC_VERSION) */ +} + + +/******************************************************************************* +* Function Name: CySoftwareReset +******************************************************************************** +* +* Summary: +* Forces a software reset of the device. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySoftwareReset(void) +{ + /* Perform software reset */ + *RESET_CR2 = 0x1u; +} + + +/******************************************************************************* +* Function Name: CyDelay +******************************************************************************** +* +* Summary: +* Blocks for milliseconds. +* +* Note: +* CyDelay has been implemented with the instruction cache assumed enabled. When +* instruction cache is disabled on PSoC5, CyDelay will be two times larger. For +* example, with instruction cache disabled CyDelay(100) would result in about +* 200 ms delay instead of 100 ms. +* +* Parameters: +* milliseconds: number of milliseconds to delay. +* +* Return: +* None +* +*******************************************************************************/ +void CyDelay(uint32 milliseconds) CYREENTRANT +{ + while (milliseconds > 32768u) + { + /*********************************************************************** + * This loop prevents overflow.At 100MHz, milliseconds * delay_freq_khz + * overflows at about 42 seconds. + ***********************************************************************/ + CyDelayCycles(cydelay_32k_ms); + milliseconds = ((uint32)(milliseconds - 32768u)); + } + + CyDelayCycles(milliseconds * cydelay_freq_khz); +} + + +#if(!CY_PSOC3) + + /* For PSoC3 devices function is defined in CyBootAsmKeil.a51 file */ + + /******************************************************************************* + * Function Name: CyDelayUs + ******************************************************************************** + * + * Summary: + * Blocks for microseconds. + * + * Note: + * CyDelay has been implemented with the instruction cache assumed enabled. + * When instruction cache is disabled on PSoC5, CyDelayUs will be two times + * larger. Ex: With instruction cache disabled CyDelayUs(100) would result + * in about 200us delay instead of 100us. + * + * Parameters: + * uint16 microseconds: number of microseconds to delay. + * + * Return: + * None + * + * Side Effects: + * CyDelayUS has been implemented with the instruction cache assumed enabled. + * When instruction cache is disabled on PSoC 5, CyDelayUs will be two times + * larger. For example, with instruction cache disabled CyDelayUs(100) would + * result in about 200 us delay instead of 100 us. + * + * If the bus clock frequency is a small non-integer number, the actual delay + * can be up to twice as long as the nominal value. The actual delay cannot be + * shorter than the nominal one. + *******************************************************************************/ + void CyDelayUs(uint16 microseconds) CYREENTRANT + { + CyDelayCycles((uint32)microseconds * cydelay_freq_mhz); + } + +#endif /* (!CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyDelayFreq +******************************************************************************** +* +* Summary: +* Sets clock frequency for CyDelay. +* +* Parameters: +* freq: Frequency of bus clock in Hertz. +* +* Return: +* None +* +*******************************************************************************/ +void CyDelayFreq(uint32 freq) CYREENTRANT +{ + if (freq != 0u) + { + cydelay_freq_hz = freq; + } + else + { + cydelay_freq_hz = BCLK__BUS_CLK__HZ; + } + + cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u); + cydelay_freq_khz = (cydelay_freq_hz + 999u) / 1000u; + cydelay_32k_ms = 32768u * cydelay_freq_khz; +} + + +/******************************************************************************* +* Function Name: CyWdtStart +******************************************************************************** +* +* Summary: +* Enables the watchdog timer. +* +* The timer is configured for the specified count interval, the central +* timewheel is cleared, the setting for low power mode is configured and the +* watchdog timer is enabled. +* +* Once enabled the watchdog cannot be disabled. The watchdog counts each time +* the Central Time Wheel (CTW) reaches the period specified. The watchdog must +* be cleared using the CyWdtClear() function before three ticks of the watchdog +* timer occur. The CTW is free running, so this will occur after between 2 and +* 3 timer periods elapse. +* +* PSoC5: The watchdog timer should not be used during sleep modes. Since the +* WDT cannot be disabled after it is enabled, the WDT timeout period can be +* set to be greater than the sleep wakeup period, then feed the dog on each +* wakeup from Sleep. +* +* Parameters: +* ticks: One of the four available timer periods. Once WDT enabled, the + interval cannot be changed. +* CYWDT_2_TICKS - 4 - 6 ms +* CYWDT_16_TICKS - 32 - 48 ms +* CYWDT_128_TICKS - 256 - 384 ms +* CYWDT_1024_TICKS - 2.048 - 3.072 s +* +* lpMode: Low power mode configuration. This parameter is ignored for PSoC 5. +* The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed. +* +* CYWDT_LPMODE_NOCHANGE - No Change +* CYWDT_LPMODE_MAXINTER - Switch to longest timer mode during low power +* mode +* CYWDT_LPMODE_DISABLED - Disable WDT during low power mode +* +* Return: +* None +* +* Side Effects: +* PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the +* ILO 1 kHz could break the active WDT functionality. +* +*******************************************************************************/ +void CyWdtStart(uint8 ticks, uint8 lpMode) +{ + #if(CY_PSOC5A) + CyILO_Start1K(); + #endif /* (CY_PSOC5A) */ + + /* Set WDT interval */ + CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_INTERVAL_MASK); + + /* Reset CTW to ensure that first watchdog period is full */ + CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET; + CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET)); + + #if(!CY_PSOC5A) + + /* Setting the low power mode */ + CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) | + (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK))); + #else + + if(0u != lpMode) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (!CY_PSOC5A) */ + + /* Enables the watchdog reset */ + CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN; +} + + +/******************************************************************************* +* Function Name: CyWdtClear +******************************************************************************** +* +* Summary: +* Clears (feeds) the watchdog timer. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyWdtClear(void) +{ + #if(CY_PSOC5A) + + /* PSoC5 ES1 watchdog time clear requires workaround */ + uint8 wdtCfg = CY_WDT_CFG_REG; + CY_WDT_CR_REG = CY_WDT_CR_FEED; + CY_WDT_CFG_REG = CY_WDT_CFG_CLEAR_ALL; + CY_WDT_CFG_REG = wdtCfg; + + #else + + CY_WDT_CR_REG = CY_WDT_CR_FEED; + + #endif /* (CY_PSOC5A) */ +} + + + +/******************************************************************************* +* Function Name: CyVdLvDigitEnable +******************************************************************************** +* +* Summary: +* Enables the digital low voltage monitors to generate interrupt on Vddd +* archives specified threshold and optionally resets device. +* +* Parameters: +* reset: Option to reset device at a specified Vddd threshold: +* 0 - Device is not reset. +* 1 - Device is reset. +* This option is applicable for PSoC 3/PSoC 5LP devices only. +* +* threshold: Sets the trip level for the voltage monitor. +* Values from 1.70 V to 5.45 V(for PSoC 3/PSoC 5LP) and from 2.45 V to 5.45 V +* (for PSoC 5TM) are accepted with the approximately 250 mV interval. +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvDigitEnable(uint8 reset, uint8 threshold) +{ + *CY_INT_CLEAR_PTR = 0x01u; + + #if(!CY_PSOC5A) + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + #endif /*(!CY_PSOC5A)*/ + + CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) | + (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK))); + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN; + + /* Timeout to eliminate glitches on the LVI/HVI when enabling */ + CyDelayUs(1u); + + (void)CY_VD_PERSISTENT_STATUS_REG; + + #if(!CY_PSOC5A) + if(0u != reset) + { + CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN; + } + else + { + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + } + #else + + if(0u != reset) + { + /* To remove unreferenced local variable warning */ + } + + #endif /*(!CY_PSOC5A)*/ + + *CY_INT_CLR_PEND_PTR = 0x01u; + *CY_INT_ENABLE_PTR = 0x01u; +} + + +/******************************************************************************* +* Function Name: CyVdLvAnalogEnable +******************************************************************************** +* +* Summary: +* Enables the analog low voltage monitors to generate interrupt on Vdda +* archives specified threshold and optionally resets device. +* +* Parameters: +* reset: Option to reset device at a specified Vdda threshold: +* 0 - Device is not reset. +* 1 - Device is reset. +* This option is applicable for PSoC 3/PSoC 5LP devices only. +* +* threshold: Sets the trip level for the voltage monitor. +* Values from 1.70 V to 5.45 V(for PSoC 3/PSoC 5LP) and from 2.45 V to 5.45 V +* (for PSoC 5TM) are accepted with the approximately 250 mV interval. +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) +{ + *CY_INT_CLEAR_PTR = 0x01u; + + #if(!CY_PSOC5A) + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + #endif /*(!CY_PSOC5A)*/ + + CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu); + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN; + + /* Timeout to eliminate glitches on the LVI/HVI when enabling */ + CyDelayUs(1u); + + (void)CY_VD_PERSISTENT_STATUS_REG; + + #if(!CY_PSOC5A) + if(0u != reset) + { + CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN; + } + else + { + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + } + #else + + if(0u != reset) + { + /* To remove unreferenced local variable warning */ + } + + #endif /*(!CY_PSOC5A)*/ + + *CY_INT_CLR_PEND_PTR = 0x01u; + *CY_INT_ENABLE_PTR = 0x01u; +} + + +/******************************************************************************* +* Function Name: CyVdLvDigitDisable +******************************************************************************** +* +* Summary: +* Disables the digital low voltage monitor (interrupt and device reset are +* disabled). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvDigitDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN)); + + #if(!CY_PSOC5A) + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + #endif /*(!CY_PSOC5A)*/ + + while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdLvAnalogDisable +******************************************************************************** +* +* Summary: +* Disables the analog low voltage monitor +* (interrupt and device reset are disabled). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvAnalogDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN)); + + #if(!CY_PSOC5A) + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + #endif /*(!CY_PSOC5A)*/ + + while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdHvAnalogEnable +******************************************************************************** +* +* Summary: +* Enables the analog high voltage monitors to generate interrupt on +* Vdda archives 5.75 V threshold and optionally resets device. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdHvAnalogEnable(void) +{ + *CY_INT_CLEAR_PTR = 0x01u; + + #if(!CY_PSOC5A) + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + #endif /*(!CY_PSOC5A)*/ + + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN; + + /* Timeout to eliminate glitches on the LVI/HVI when enabling */ + CyDelayUs(1u); + + (void) CY_VD_PERSISTENT_STATUS_REG; + + *CY_INT_CLR_PEND_PTR = 0x01u; + *CY_INT_ENABLE_PTR = 0x01u; +} + + +/******************************************************************************* +* Function Name: CyVdHvAnalogDisable +******************************************************************************** +* +* Summary: +* Disables the analog low voltage monitor +* (interrupt and device reset are disabled). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdHvAnalogDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN)); +} + + +/******************************************************************************* +* Function Name: CyVdStickyStatus +******************************************************************************** +* +* Summary: +* Manages the Reset and Voltage Detection Status Register 0. +* This register has the interrupt status for the HVIA, LVID and LVIA. +* This hardware register clears on read. +* +* Parameters: +* mask: Bits in the shadow register to clear. +* Value Define Bit To Clear +* 0x01 CY_VD_LVID LVID +* 0x02 CY_VD_LVIA LVIA +* 0x04 CY_VD_HVIA HVIA +* +* Return: +* Status. Same enumerated bit values as used for the mask parameter. +* +*******************************************************************************/ +uint8 CyVdStickyStatus(uint8 mask) +{ + uint8 status; + + status = CY_VD_PERSISTENT_STATUS_REG; + CY_VD_PERSISTENT_STATUS_REG &= ((uint8)(~mask)); + + return(status); +} + + +/******************************************************************************* +* Function Name: CyVdRealTimeStatus +******************************************************************************** +* +* Summary: +* Returns the real time voltage detection status. +* +* Parameters: +* None +* +* Return: +* Status. Same enumerated bit values as used for the mask parameter. +* +*******************************************************************************/ +uint8 CyVdRealTimeStatus(void) +{ + uint8 interruptState; + uint8 vdFlagsState; + + interruptState = CyEnterCriticalSection(); + vdFlagsState = CY_VD_RT_STATUS_REG; + CyExitCriticalSection(interruptState); + + return(vdFlagsState); +} + + +/******************************************************************************* +* Function Name: CyDisableInts +******************************************************************************** +* +* Summary: +* Disables the interrupt enable for each interrupt. +* +* Parameters: +* None +* +* Return: +* 32 bit mask of previously enabled interrupts. +* +*******************************************************************************/ +uint32 CyDisableInts(void) +{ + uint32 intState; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if(CY_PSOC3) + + /* Get the current interrupt state. */ + intState = ((uint32) CY_GET_REG8(CY_INT_CLR_EN0_PTR)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN1_PTR)) << 8u)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN2_PTR)) << 16u)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN3_PTR)) << 24u)); + + + /* Disable all of the interrupts. */ + CY_SET_REG8(CY_INT_CLR_EN0_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN1_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN2_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN3_PTR, 0xFFu); + + #else + + /* Get the current interrupt state. */ + intState = CY_GET_REG32(CY_INT_CLEAR_PTR); + + /* Disable all of the interrupts. */ + CY_SET_REG32(CY_INT_CLEAR_PTR, 0xFFFFFFFFu); + + #endif /* (CY_PSOC3) */ + + CyExitCriticalSection(interruptState); + + return (intState); +} + + +/******************************************************************************* +* Function Name: CyEnableInts +******************************************************************************** +* +* Summary: +* Enables interrupts to a given state. +* +* Parameters: +* uint32 mask: 32 bit mask of interrupts to enable. +* +* Return: +* None +* +*******************************************************************************/ +void CyEnableInts(uint32 mask) +{ + + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if(CY_PSOC3) + + /* Set interrupts as enabled. */ + CY_SET_REG8(CY_INT_SET_EN3_PTR, ((uint8) (mask >> 24u))); + CY_SET_REG8(CY_INT_SET_EN2_PTR, ((uint8) (mask >> 16u))); + CY_SET_REG8(CY_INT_SET_EN1_PTR, ((uint8) (mask >> 8u ))); + CY_SET_REG8(CY_INT_SET_EN0_PTR, ((uint8) (mask ))); + + #else + + CY_SET_REG32(CY_INT_ENABLE_PTR, mask); + + #endif /* (CY_PSOC3) */ + + CyExitCriticalSection(interruptState); + +} + +#if(CY_PSOC5) + + /******************************************************************************* + * Function Name: CyFlushCache + ******************************************************************************** + * Summary: + * Flushes the PSoC 5/5LP cache by invalidating all entries. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CyFlushCache(void) + { + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /* Fill instruction prefectch unit to insure data integrity */ + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + + /* All entries in the cache are invalidated on the next clock cycle. */ + CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH; + + + /*********************************************************************** + * The prefetch unit could/would be filled with the instructions that + * succeed the flush. Since a flush is desired then theoretically those + * instructions might be considered stale/invalid. + ***********************************************************************/ + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CyIntSetSysVector + ******************************************************************************** + * Summary: + * Sets the interrupt vector of the specified system interrupt number. System + * interrupts are present only for the ARM platform. These interrupts are for + * SysTick, PendSV and others. + * + * Parameters: + * number: Interrupt number, valid range [0-15]. + address: Pointer to an interrupt service routine. + * + * Return: + * The old ISR vector at this location. + * + *******************************************************************************/ + cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + + CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; + + /* Set new Interrupt service routine. */ + ramVectorTable[number & CY_INT_SYS_NUMBER_MASK] = address; + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetSysVector + ******************************************************************************** + * + * Summary: + * Gets the interrupt vector of the specified system interrupt number. System + * interrupts are present only for the ARM platform. These interrupts are for + * SysTick, PendSV and others. + * + * Parameters: + * number: The interrupt number, valid range [0-15]. + * + * Return: + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetSysVector(uint8 number) + { + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); + + return ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; + } + + + /******************************************************************************* + * Function Name: CyIntSetVector + ******************************************************************************** + * + * Summary: + * Sets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * address: Pointer to an interrupt service routine + * + * Return: + * Previous interrupt vector value. + * + *******************************************************************************/ + cyisraddress CyIntSetVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]; + + /* Set new Interrupt service routine. */ + ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)] = address; + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetVector + ******************************************************************************** + * + * Summary: + * Gets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetVector(uint8 number) + { + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + CYASSERT(number <= CY_INT_NUMBER_MAX); + + return (ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]); + } + + + /******************************************************************************* + * Function Name: CyIntSetPriority + ******************************************************************************** + * + * Summary: + * Sets the Priority of the Interrupt. + * + * Parameters: + * priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * number: The number of the interrupt, 0 - 31. + * + * Return: + * None + * + *******************************************************************************/ + void CyIntSetPriority(uint8 number, uint8 priority) + { + CYASSERT(priority <= CY_INT_PRIORITY_MAX); + CYASSERT(number <= CY_INT_NUMBER_MAX); + CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = (priority & CY_INT_PRIORITY_MASK)<< 5; + } + + + /******************************************************************************* + * Function Name: CyIntGetPriority + ******************************************************************************** + * + * Summary: + * Gets the Priority of the Interrupt. + * + * Parameters: + * number: The number of the interrupt, 0 - 31. + * + * Return: + * Priority of the interrupt. 0 - 7, 0 being the highest. + * + *******************************************************************************/ + uint8 CyIntGetPriority(uint8 number) + { + uint8 priority; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; + + return (priority); + } + + + /******************************************************************************* + * Function Name: CyIntGetState + ******************************************************************************** + * + * Summary: + * Gets the enable state of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * Enable status: 1 if enabled, 0 if disabled + * + *******************************************************************************/ + uint8 CyIntGetState(uint8 number) + { + reg32 * stateReg; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Get a pointer to the Interrupt enable register. */ + stateReg = CY_INT_ENABLE_PTR; + + /* Get the state of the interrupt. */ + return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u)); + } + + +#else /* PSoC3 */ + + + /******************************************************************************* + * Function Name: CyIntSetVector + ******************************************************************************** + * + * Summary: + * Sets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * address: Pointer to an interrupt service routine + * + * Return: + * Previous interrupt vector value. + * + *******************************************************************************/ + cyisraddress CyIntSetVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = (cyisraddress) \ + CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]); + + /* Set new Interrupt service routine. */ + CY_SET_REG16(&CY_INT_VECT_TABLE[number], (uint16) address); + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetVector + ******************************************************************************** + * + * Summary: + * Gets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetVector(uint8 number) + { + CYASSERT(number <= CY_INT_NUMBER_MAX); + + return ((cyisraddress) \ + CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK])); + } + + + /******************************************************************************* + * Function Name: CyIntSetPriority + ******************************************************************************** + * + * Summary: + * Sets the Priority of the Interrupt. + * + * Parameters: + * priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * number: The number of the interrupt, 0 - 31. + * + * Return: + * None + * + *******************************************************************************/ + void CyIntSetPriority(uint8 number, uint8 priority) + { + CYASSERT(priority <= CY_INT_PRIORITY_MAX); + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = + (priority & CY_INT_PRIORITY_MASK) << 5; + } + + + /******************************************************************************* + * Function Name: CyIntGetPriority + ******************************************************************************** + * + * Summary: + * Gets the Priority of the Interrupt. + * + * Parameters: + * number: The number of the interrupt, 0 - 31. + * + * Return: + * Priority of the interrupt. 0 - 7, 0 being the highest. + * + *******************************************************************************/ + uint8 CyIntGetPriority(uint8 number) + { + uint8 priority; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; + + return (priority); + } + + + /******************************************************************************* + * Function Name: CyIntGetState + ******************************************************************************** + * + * Summary: + * Gets the enable state of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * Enable status: 1 if enabled, 0 if disabled + * + *******************************************************************************/ + uint8 CyIntGetState(uint8 number) + { + reg8 * stateReg; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Get a pointer to the Interrupt enable register. */ + stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u); + + /* Get the state of the interrupt. */ + return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u))); + } + + +#endif /* (CY_PSOC5) */ + + +#if(!CY_PSOC5A) + + #if(CYDEV_VARIABLE_VDDA == 1) + + + /******************************************************************************* + * Function Name: CySetScPumps + ******************************************************************************** + * + * Summary: + * If 1 is passed as a parameter: + * - if any of the SC blocks are used - enable pumps for the SC blocks and + * start boost clock. + * - For the each enabled SC block set boost clock index and enable boost clock. + * + * If non-1 value is passed as a parameter: + * - If all SC blocks are not used - disable pumps for the SC blocks and + * stop boost clock. + * - For the each enabled SC block clear boost clock index and disable boost + * clock. + * + * The global variable CyScPumpEnabled is updated to be equal to passed + * parameter. + * + * Parameters: + * uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block. + * 1 - Enable + * 0 - Disable + * + * Return: + * None + * + *******************************************************************************/ + void CySetScPumps(uint8 enable) + { + + if(1u == enable) + { + /* The SC pumps should be enabled */ + CyScPumpEnabled = 1u; + + + /* Enable pumps if any of SC blocks are used */ + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAPS_MASK)) + { + + CY_LIB_SC_MISC_REG |= CY_LIB_SC_MISC_PUMP_FORCE; + + CyScBoostClk_Start(); + } + + + /* Set positive pump for each enabled SC block: set clock index and enable it */ + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP0_EN)) + { + CY_LIB_SC0_BST_REG = (CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC0_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP1_EN)) + { + CY_LIB_SC1_BST_REG = (CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC1_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP2_EN)) + { + CY_LIB_SC2_BST_REG = (CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC2_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP3_EN)) + { + CY_LIB_SC3_BST_REG = (CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC3_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + } + else + { + /* The SC pumps should be disabled */ + CyScPumpEnabled = 0u; + + /* Disable pumps for all SC blocks and stop boost clock */ + CY_LIB_SC_MISC_REG &= ((uint8)(~CY_LIB_SC_MISC_PUMP_FORCE)); + CyScBoostClk_Stop(); + + /* Disable boost clock and clear clock index for each SC block */ + CY_LIB_SC0_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC0_BST_REG = CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + + CY_LIB_SC1_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC1_BST_REG = CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + + CY_LIB_SC2_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC2_BST_REG = CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + + CY_LIB_SC3_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC3_BST_REG = CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + } + } + + #endif /* (CYDEV_VARIABLE_VDDA == 1) */ + +#endif /* (!CY_PSOC5A) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h new file mode 100644 index 0000000..cefca8d --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h @@ -0,0 +1,1201 @@ +/******************************************************************************* +* File Name: CyLib.h +* Version 3.40 +* +* Description: +* Provides the function definitions for the system, clocking, interrupts and +* watchdog timer API. +* +* Note: +* Documentation of the API's in this file is located in the System Reference +* Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYLIB_H) +#define CY_BOOT_CYLIB_H + +#include +#include +#include + +#include "cytypes.h" +#include "cyfitter.h" +#include "cydevice_trm.h" +#include "cyPm.h" + +#if(CY_PSOC3) + #include +#endif /* (CY_PSOC3) */ + + +#if(!CY_PSOC5A) + + #if(CYDEV_VARIABLE_VDDA == 1) + + #include "CyScBoostClk.h" + + #endif /* (CYDEV_VARIABLE_VDDA == 1) */ + +#endif /* (!CY_PSOC5A) */ + + +/* Global variable with preserved reset status */ +extern uint8 CYXDATA CyResetStatus; + + +#if(!CY_PSOC5A) + + /* Variable Vdda */ + #if(CYDEV_VARIABLE_VDDA == 1) + + extern uint8 CyScPumpEnabled; + + #endif /* (CYDEV_VARIABLE_VDDA == 1) */ + +#endif /* (!CY_PSOC5A) */ + + +/* Do not use these definitions directly in your application */ +extern uint32 cydelay_freq_hz; +extern uint32 cydelay_freq_khz; +extern uint8 cydelay_freq_mhz; +extern uint32 cydelay_32k_ms; + + +/*************************************** +* Function Prototypes +***************************************/ +cystatus CyPLL_OUT_Start(uint8 wait) ; +void CyPLL_OUT_Stop(void) ; +void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) ; +void CyPLL_OUT_SetSource(uint8 source) ; + +void CyIMO_Start(uint8 wait) ; +void CyIMO_Stop(void) ; +void CyIMO_SetFreq(uint8 freq) ; +void CyIMO_SetSource(uint8 source) ; +void CyIMO_EnableDoubler(void) ; +void CyIMO_DisableDoubler(void) ; + +void CyMasterClk_SetSource(uint8 source) ; +void CyMasterClk_SetDivider(uint8 divider) ; +void CyBusClk_SetDivider(uint16 divider) ; + +#if(CY_PSOC3) + void CyCpuClk_SetDivider(uint8 divider) ; +#endif /* (CY_PSOC3) */ + +void CyUsbClk_SetSource(uint8 source) ; + +void CyILO_Start1K(void) ; +void CyILO_Stop1K(void) ; +void CyILO_Start100K(void) ; +void CyILO_Stop100K(void) ; +void CyILO_Enable33K(void) ; +void CyILO_Disable33K(void) ; +void CyILO_SetSource(uint8 source) ; +uint8 CyILO_SetPowerMode(uint8 mode) ; + +uint8 CyXTAL_32KHZ_ReadStatus(void) ; +uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) ; +void CyXTAL_32KHZ_Start(void) ; +void CyXTAL_32KHZ_Stop(void) ; + +cystatus CyXTAL_Start(uint8 wait) ; +void CyXTAL_Stop(void) ; +void CyXTAL_SetStartup(uint8 setting) ; +#if(!CY_PSOC5A) + void CyXTAL_EnableErrStatus(void) ; + void CyXTAL_DisableErrStatus(void) ; + uint8 CyXTAL_ReadStatus(void) ; + void CyXTAL_EnableFaultRecovery(void) ; + void CyXTAL_DisableFaultRecovery(void) ; +#endif /* (!CY_PSOC5A) */ + +#if(CY_PSOC3 || CY_PSOC5LP) + void CyXTAL_SetFbVoltage(uint8 setting) ; + void CyXTAL_SetWdVoltage(uint8 setting) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void CyWdtStart(uint8 ticks, uint8 lpMode) ; +void CyWdtClear(void) ; + +/* System Function Prototypes */ +void CyDelay(uint32 milliseconds) CYREENTRANT; +void CyDelayUs(uint16 microseconds); +void CyDelayFreq(uint32 freq) CYREENTRANT; +void CyDelayCycles(uint32 cycles); + +void CySoftwareReset(void) ; + +uint8 CyEnterCriticalSection(void); +void CyExitCriticalSection(uint8 savedIntrStatus); +void CyHalt(uint8 reason) CYREENTRANT; + + +/* Interrupt Function Prototypes */ +#if(CY_PSOC5) + cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) ; + cyisraddress CyIntGetSysVector(uint8 number) ; +#endif /* (CY_PSOC5) */ + +cyisraddress CyIntSetVector(uint8 number, cyisraddress address) ; +cyisraddress CyIntGetVector(uint8 number) ; + +void CyIntSetPriority(uint8 number, uint8 priority) ; +uint8 CyIntGetPriority(uint8 number) ; + +uint8 CyIntGetState(uint8 number) ; + +uint32 CyDisableInts(void) ; +void CyEnableInts(uint32 mask) ; + + +#if(CY_PSOC5) + void CyFlushCache(void); +#endif /* (CY_PSOC5) */ + + +/* Voltage Detection Function Prototypes */ +void CyVdLvDigitEnable(uint8 reset, uint8 threshold) ; +void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) ; +void CyVdLvDigitDisable(void) ; +void CyVdLvAnalogDisable(void) ; +void CyVdHvAnalogEnable(void) ; +void CyVdHvAnalogDisable(void) ; +uint8 CyVdStickyStatus(uint8 mask) ; +uint8 CyVdRealTimeStatus(void) ; + +#if(!CY_PSOC5A) + + void CySetScPumps(uint8 enable) ; + +#endif /* (!CY_PSOC5A) */ + + +/*************************************** +* API Constants +***************************************/ + + +/******************************************************************************* +* PLL API Constants +*******************************************************************************/ +#define CY_CLK_PLL_ENABLE (0x01u) +#define CY_CLK_PLL_LOCK_STATUS (0x01u) + +#define CY_CLK_PLL_FTW_INTERVAL (24u) + +#define CY_CLK_PLL_MAX_Q_VALUE (16u) +#define CY_CLK_PLL_MIN_Q_VALUE (1u) +#define CY_CLK_PLL_MIN_P_VALUE (8u) +#define CY_CLK_PLL_MIN_CUR_VALUE (1u) +#define CY_CLK_PLL_MAX_CUR_VALUE (7u) + +#define CY_CLK_PLL_CURRENT_POSITION (4u) +#define CY_CLK_PLL_CURRENT_MASK (0x8Fu) + + +/******************************************************************************* +* External 32kHz Crystal Oscillator API Constants +*******************************************************************************/ +#define CY_XTAL32K_ANA_STAT (0x20u) + + +#define CY_CLK_XTAL32_CR_LPM (0x02u) +#define CY_CLK_XTAL32_CR_EN (0x01u) +#if(CY_PSOC3) + #define CY_CLK_XTAL32_CR_PDBEN (0x04u) +#endif /* (CY_PSOC3) */ + +#define CY_CLK_XTAL32_TR_MASK (0x07u) +#define CY_CLK_XTAL32_TR_STARTUP (0x03u) +#define CY_CLK_XTAL32_TR_HIGH_POWER (0x06u) +#define CY_CLK_XTAL32_TR_LOW_POWER (0x01u) +#define CY_CLK_XTAL32_TR_POWERDOWN (0x00u) + +#define CY_CLK_XTAL32_TST_DEFAULT (0xF3u) + +#define CY_CLK_XTAL32_CFG_LP_DEFAULT (0x04u) +#define CY_CLK_XTAL32_CFG_LP_LOWPOWER (0x08u) +#define CY_CLK_XTAL32_CFG_LP_MASK (0x0Cu) + +#define CY_CLK_XTAL32_CFG_LP_ALLOW (0x80u) + + +/******************************************************************************* +* External MHz Crystal Oscillator API Constants +*******************************************************************************/ +#define CY_CLK_XMHZ_FTW_INTERVAL (24u) +#define CY_CLK_XMHZ_MIN_TIMEOUT (130u) + +#define CY_CLK_XMHZ_CSR_ENABLE (0x01u) +#define CY_CLK_XMHZ_CSR_XERR (0x80u) +#define CY_CLK_XMHZ_CSR_XFB (0x04u) +#define CY_CLK_XMHZ_CSR_XPROT (0x40u) + +#define CY_CLK_XMHZ_CFG0_XCFG_MASK (0x1Fu) +#define CY_CLK_XMHZ_CFG1_VREF_FB_MASK (0x0Fu) +#define CY_CLK_XMHZ_CFG1_VREF_WD_MASK (0x70u) + + +/******************************************************************************* +* Watchdog Timer API Constants +*******************************************************************************/ +#define CYWDT_2_TICKS (0x0u) /* 4 - 6 ms */ +#define CYWDT_16_TICKS (0x1u) /* 32 - 48 ms */ +#define CYWDT_128_TICKS (0x2u) /* 256 - 384 ms */ +#define CYWDT_1024_TICKS (0x3u) /* 2048 - 3072 ms */ + +#define CYWDT_LPMODE_NOCHANGE (0x00u) +#define CYWDT_LPMODE_MAXINTER (0x01u) +#define CYWDT_LPMODE_DISABLED (0x03u) + +#define CY_WDT_CFG_INTERVAL_MASK (0x03u) +#define CY_WDT_CFG_CTW_RESET (0x80u) +#define CY_WDT_CFG_LPMODE_SHIFT (5u) +#define CY_WDT_CFG_LPMODE_MASK (0x60u) +#define CY_WDT_CFG_WDR_EN (0x10u) +#define CY_WDT_CFG_CLEAR_ALL (0x00u) +#define CY_WDT_CR_FEED (0x01u) + + +/******************************************************************************* +* Voltage Detection API Constants +*******************************************************************************/ + +#define CY_VD_LVID_EN (0x01u) +#define CY_VD_LVIA_EN (0x02u) +#define CY_VD_HVIA_EN (0x04u) + +#define CY_VD_PRESD_EN (0x40u) +#define CY_VD_PRESA_EN (0x80u) + +#define CY_VD_LVID (0x01u) +#define CY_VD_LVIA (0x02u) +#define CY_VD_HVIA (0x04u) + +#define CY_VD_LVI_TRIP_LVID_MASK (0x0Fu) + + +/******************************************************************************* +* Variable VDDA +*******************************************************************************/ +#if(!CY_PSOC5A) + + #if(CYDEV_VARIABLE_VDDA == 1) + + /* Active Power Mode Configuration Register 9 */ + #define CY_LIB_ACT_CFG9_SWCAP0_EN (0x01u) + #define CY_LIB_ACT_CFG9_SWCAP1_EN (0x02u) + #define CY_LIB_ACT_CFG9_SWCAP2_EN (0x04u) + #define CY_LIB_ACT_CFG9_SWCAP3_EN (0x08u) + #define CY_LIB_ACT_CFG9_SWCAPS_MASK (0x0Fu) + + /* Switched Cap Miscellaneous Control Register */ + #define CY_LIB_SC_MISC_PUMP_FORCE (0x20u) + + /* Switched Capacitor 0 Boost Clock Selection Register */ + #define CY_LIB_SC_BST_CLK_EN (0x08u) + #define CY_LIB_SC_BST_CLK_INDEX_MASK (0xF8u) + + #endif /* (CYDEV_VARIABLE_VDDA == 1) */ + +#endif /* (!CY_PSOC5A) */ + + +/******************************************************************************* +* Clock Distribution Constants +*******************************************************************************/ +#define CY_LIB_CLKDIST_AMASK_MASK (0xF0u) +#define CY_LIB_CLKDIST_DMASK_MASK (0x00u) +#define CY_LIB_CLKDIST_LD_LOAD (0x01u) +#define CY_LIB_CLKDIST_BCFG2_MASK (0x80u) /* Enable shadow loads */ +#define CY_LIB_CLKDIST_MASTERCLK_DIV (7u) +#define CY_LIB_CLKDIST_BCFG2_SSS (0x40u) /* Sync source is same frequency */ +#define CY_LIB_CLKDIST_MSTR1_SRC_MASK (0xFCu) +#define CY_LIB_FASTCLK_IMO_DOUBLER (0x10u) +#define CY_LIB_FASTCLK_IMO_IMO (0x20u) +#define CY_LIB_CLKDIST_CR_IMO2X (0x40u) +#define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u) + +#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK (0xFCu) + +#define ILO_CONTROL_PD_MODE (0x10u) + +#define CY_ILO_SOURCE_100K (0u) +#define CY_ILO_SOURCE_33K (1u) +#define CY_ILO_SOURCE_1K (2u) + +#define CY_ILO_FAST_START (0u) +#define CY_ILO_SLOW_START (1u) + +#define CY_ILO_SOURCE_BITS_CLEAR (0xF3u) +#define CY_ILO_SOURCE_1K_SET (0x08u) +#define CY_ILO_SOURCE_33K_SET (0x04u) +#define CY_ILO_SOURCE_100K_SET (0x00u) + + +#define CY_MASTER_SOURCE_IMO (0u) +#define CY_MASTER_SOURCE_PLL (1u) +#define CY_MASTER_SOURCE_XTAL (2u) +#define CY_MASTER_SOURCE_DSI (3u) + +#define CY_IMO_SOURCE_IMO (0u) +#define CY_IMO_SOURCE_XTAL (1u) +#define CY_IMO_SOURCE_DSI (2u) +#define IMO_PM_ENABLE (0x10u) /* Enable IMO clock source. */ +#define FASTCLK_IMO_USBCLK_ON_SET (0x40u) + +#define CLOCK_IMO_3MHZ_VALUE (0x03u) +#define CLOCK_IMO_6MHZ_VALUE (0x01u) +#define CLOCK_IMO_12MHZ_VALUE (0x00u) +#define CLOCK_IMO_24MHZ_VALUE (0x02u) +#define CLOCK_IMO_48MHZ_VALUE (0x04u) +#define CLOCK_IMO_62MHZ_VALUE (0x05u) +#define CLOCK_IMO_74MHZ_VALUE (0x06u) + +/* CyIMO_SetFreq() */ +#define CY_IMO_FREQ_3MHZ (0u) +#define CY_IMO_FREQ_6MHZ (1u) +#define CY_IMO_FREQ_12MHZ (2u) +#define CY_IMO_FREQ_24MHZ (3u) +#define CY_IMO_FREQ_48MHZ (4u) +#if(!CY_PSOC5A) + #define CY_IMO_FREQ_62MHZ (5u) +#endif /* (!CY_PSOC5A) */ +#define CY_IMO_FREQ_USB (8u) + + +#define SFR_USER_CPUCLK_DIV_MASK (0x0Fu) +#define CLKDIST_DIV_POSITION (4u) +#define CLKDIST_MSTR1_DIV_CLEAR (0x0Fu) +#define CLOCK_USB_ENABLE (0x02u) +#define CLOCK_IMO_OUT_X2 (0x10u) +#define CLOCK_IMO_OUT_X1 ((uint8)(~CLOCK_IMO_OUT_X2)) +#define CY_PLL_SOURCE_IMO (0u) +#define CY_PLL_SOURCE_XTAL (1u) +#define CY_PLL_SOURCE_DSI (2u) + +#define CLOCK_IMO2X_ECO ((uint8)(~CLOCK_IMO2X_DSI)) + +#define ILO_CONTROL_PD_POSITION (4u) +#define ILO_CONTROL_1KHZ_ON (0x02u) +#define ILO_CONTROL_100KHZ_ON (0x04u) +#define ILO_CONTROL_33KHZ_ON (0x20u) + +#define USB_CLKDIST_CONFIG_MASK (0x03u) +#define USB_CLK_IMO2X (0x00u) +#define USB_CLK_IMO (0x01u) +#define USB_CLK_PLL (0x02u) +#define USB_CLK_DSI (0x03u) +#define USB_CLK_DIV2_ON (0x04u) +#define USB_CLK_STOP_FLAG (0x00u) +#define USB_CLK_START_FLAG (0x01u) + +#define FTW_CLEAR_ALL_BITS (0x00u) /* To clear all bits of PM_TW_CFG2 */ +#define FTW_CLEAR_FTW_BITS (0xFCu) /* To clear FTW bits of PM_TW_CFG2 */ +#define FTW_ENABLE (0x01u) /* To enable FTW, no interrupt */ + +#define CY_ACT_USB_ENABLED (0x01u) +#define CY_ALT_ACT_USB_ENABLED (0x01u) + + +/*************************************** +* Registers +***************************************/ + + +/******************************************************************************* +* PLL Registers +*******************************************************************************/ + +/* PLL Configuration Register 0 */ +#define CY_CLK_PLL_CFG0_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG0) +#define CY_CLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0) + +/* PLL Configuration Register 1 */ +#define CY_CLK_PLL_CFG1_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG1) +#define CY_CLK_PLL_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG1) + +/* PLL Status Register */ +#define CY_CLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR) +#define CY_CLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR) + +/* PLL Q-Counter Configuration Register */ +#define CY_CLK_PLL_Q_REG (*(reg8 *) CYREG_FASTCLK_PLL_Q) +#define CY_CLK_PLL_Q_PTR ( (reg8 *) CYREG_FASTCLK_PLL_Q) + +/* PLL P-Counter Configuration Register */ +#define CY_CLK_PLL_P_REG (*(reg8 *) CYREG_FASTCLK_PLL_P) +#define CY_CLK_PLL_P_PTR ( (reg8 *) CYREG_FASTCLK_PLL_P) + + +/******************************************************************************* +* External MHz Crystal Oscillator Registers +*******************************************************************************/ + +/* External MHz Crystal Oscillator Status and Control Register */ +#define CY_CLK_XMHZ_CSR_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR) +#define CY_CLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR) + +/* External MHz Crystal Oscillator Configuration Register 0 */ +#define CY_CLK_XMHZ_CFG0_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0) +#define CY_CLK_XMHZ_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0) + +/* External MHz Crystal Oscillator Configuration Register 1 */ +#define CY_CLK_XMHZ_CFG1_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1) +#define CY_CLK_XMHZ_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1) + + +/******************************************************************************* +* External 32kHz Crystal Oscillator Registers +*******************************************************************************/ + +/* 32 kHz Watch Crystal Oscillator Trim Register */ +#define CY_CLK_XTAL32_TR_REG (*(reg8 *) CYREG_X32_TR) +#define CY_CLK_XTAL32_TR_PTR ( (reg8 *) CYREG_X32_TR) + +/* External 32kHz Crystal Oscillator Test Register */ +#define CY_CLK_XTAL32_TST_REG (*(reg8 *) CYREG_SLOWCLK_X32_TST) +#define CY_CLK_XTAL32_TST_PTR ( (reg8 *) CYREG_SLOWCLK_X32_TST) + +/* External 32kHz Crystal Oscillator Control Register */ +#define CY_CLK_XTAL32_CR_REG (*(reg8 *) CYREG_SLOWCLK_X32_CR) +#define CY_CLK_XTAL32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR) + +/* External 32kHz Crystal Oscillator Configuration Register */ +#define CY_CLK_XTAL32_CFG_REG (*(reg8 *) CYREG_SLOWCLK_X32_CFG) +#define CY_CLK_XTAL32_CFG_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CFG) + + +/******************************************************************************* +* Watchdog Timer Registers +*******************************************************************************/ + +/* Watchdog Timer Configuration Register */ +#define CY_WDT_CFG_REG (*(reg8 *) CYREG_PM_WDT_CFG) +#define CY_WDT_CFG_PTR ( (reg8 *) CYREG_PM_WDT_CFG) + +/* Watchdog Timer Control Register */ +#define CY_WDT_CR_REG (*(reg8 *) CYREG_PM_WDT_CR) +#define CY_WDT_CR_PTR ( (reg8 *) CYREG_PM_WDT_CR) + + +/******************************************************************************* +* LVI/HVI Registers +*******************************************************************************/ + +#define CY_VD_LVI_TRIP_REG (* (reg8 *) CYDEV_RESET_CR0) +#define CY_VD_LVI_TRIP_PTR ( (reg8 *) CYDEV_RESET_CR0) + +#define CY_VD_LVI_HVI_CONTROL_REG (* (reg8 *) CYDEV_RESET_CR1) +#define CY_VD_LVI_HVI_CONTROL_PTR ( (reg8 *) CYDEV_RESET_CR1) + +#define CY_VD_PRES_CONTROL_REG (* (reg8 *) CYDEV_RESET_CR3) +#define CY_VD_PRES_CONTROL_PTR ( (reg8 *) CYDEV_RESET_CR3) + +#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYDEV_RESET_SR0) +#define CY_VD_PERSISTENT_STATUS_PTR ( (reg8 *) CYDEV_RESET_SR0) + +#define CY_VD_RT_STATUS_REG (* (reg8 *) CYDEV_RESET_SR2) +#define CY_VD_RT_STATUS_PTR ( (reg8 *) CYDEV_RESET_SR2) + + +/******************************************************************************* +* Variable VDDA +*******************************************************************************/ +#if(!CY_PSOC5A) + + #if(CYDEV_VARIABLE_VDDA == 1) + + /* Active Power Mode Configuration Register 9 */ + #define CY_LIB_ACT_CFG9_REG (* (reg8 *) CYREG_PM_ACT_CFG9 ) + #define CY_LIB_ACT_CFG9_PTR ( (reg8 *) CYREG_PM_ACT_CFG9 ) + + /* Switched Capacitor 0 Boost Clock Selection Register */ + #define CY_LIB_SC0_BST_REG (* (reg8 *) CYREG_SC0_BST ) + #define CY_LIB_SC0_BST_PTR ( (reg8 *) CYREG_SC0_BST ) + + /* Switched Capacitor 1 Boost Clock Selection Register */ + #define CY_LIB_SC1_BST_REG (* (reg8 *) CYREG_SC1_BST ) + #define CY_LIB_SC1_BST_PTR ( (reg8 *) CYREG_SC1_BST ) + + /* Switched Capacitor 2 Boost Clock Selection Register */ + #define CY_LIB_SC2_BST_REG (* (reg8 *) CYREG_SC2_BST ) + #define CY_LIB_SC2_BST_PTR ( (reg8 *) CYREG_SC2_BST ) + + /* Switched Capacitor 3 Boost Clock Selection Register */ + #define CY_LIB_SC3_BST_REG (* (reg8 *) CYREG_SC3_BST ) + #define CY_LIB_SC3_BST_PTR ( (reg8 *) CYREG_SC3_BST ) + + /* Switched Cap Miscellaneous Control Register */ + #define CY_LIB_SC_MISC_REG (* (reg8 *) CYREG_SC_MISC ) + #define CY_LIB_SC_MISC_PTR ( (reg8 *) CYREG_SC_MISC ) + + #endif /* (CYDEV_VARIABLE_VDDA == 1) */ + +#endif /* (!CY_PSOC5A) */ + + +/******************************************************************************* +* Clock Distribution Registers +*******************************************************************************/ + +/* Analog Clock Mask Register */ +#define CY_LIB_CLKDIST_AMASK_REG (* (reg8 *) CYREG_CLKDIST_AMASK ) +#define CY_LIB_CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK ) + +/* Digital Clock Mask Register */ +#define CY_LIB_CLKDIST_DMASK_REG (*(reg8 *) CYREG_CLKDIST_DMASK) +#define CY_LIB_CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) + +/* CLK_BUS Configuration Register */ +#define CY_LIB_CLKDIST_BCFG2_REG (*(reg8 *) CYREG_CLKDIST_BCFG2) +#define CY_LIB_CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) + +/* LSB Shadow Divider Value Register */ +#define CY_LIB_CLKDIST_WRK_LSB_REG (*(reg8 *) CYREG_CLKDIST_WRK0) +#define CY_LIB_CLKDIST_WRK_LSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) + +/* MSB Shadow Divider Value Register */ +#define CY_LIB_CLKDIST_WRK_MSB_REG (*(reg8 *) CYREG_CLKDIST_WRK1) +#define CY_LIB_CLKDIST_WRK_MSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK1) + +/* LOAD Register */ +#define CY_LIB_CLKDIST_LD_REG (*(reg8 *) CYREG_CLKDIST_LD) +#define CY_LIB_CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) + +/* CLK_BUS LSB Divider Value Register */ +#define CY_LIB_CLKDIST_BCFG_LSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG0) +#define CY_LIB_CLKDIST_BCFG_LSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) + +/* CLK_BUS MSB Divider Value Register */ +#define CY_LIB_CLKDIST_BCFG_MSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG1) +#define CY_LIB_CLKDIST_BCFG_MSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1) + +/* Master clock (clk_sync_d) Divider Value Register */ +#define CY_LIB_CLKDIST_MSTR0_REG (*(reg8 *) CYREG_CLKDIST_MSTR0) +#define CY_LIB_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) + +/* Master (clk_sync_d) Configuration Register/CPU Divider Value */ +#define CY_LIB_CLKDIST_MSTR1_REG (*(reg8 *) CYREG_CLKDIST_MSTR1) +#define CY_LIB_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) + +/* Internal Main Oscillator Control Register */ +#define CY_LIB_FASTCLK_IMO_CR_REG (*(reg8 *) CYREG_FASTCLK_IMO_CR) +#define CY_LIB_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) + +/* Configuration Register CR */ +#define CY_LIB_CLKDIST_CR_REG (*(reg8 *) CYREG_CLKDIST_CR) +#define CY_LIB_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) + + +#define SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define SLOWCLK_ILO_CR0 (*(reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) +#define CLKDIST_UCFG (*(reg8 *) CYREG_CLKDIST_UCFG) + +#define PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0) +#define PM_TW_CFG0 (*(reg8 *) CYREG_PM_TW_CFG0) + +#define PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2) +#define PM_TW_CFG2 (*(reg8 *) CYREG_PM_TW_CFG2) + +#define CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) +#define CLKDIST_MSTR1 (*(reg8 *) CYREG_CLKDIST_MSTR1) + + + +#define SFR_USER_CPUCLK_DIV_PTR ((void far *) CYREG_SFR_USER_CPUCLK_DIV) + +#define CLOCK_CONTROL ( (reg8 *) CYREG_CLKDIST_CR) +#define IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1) +#define IMO_TR1 (*(reg8 *) CYREG_IMO_TR1) +#define CY_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 ) +#define CY_USB_CR1 (*(reg8 *) CYREG_USB_CR1 ) + +#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) +#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0) +#define PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) +#define PM_STBY_CFG0 (*(reg8 *) CYREG_PM_STBY_CFG0) +#define PM_AVAIL_CR2_PTR ( (reg8 *) CYREG_PM_AVAIL_CR2) +#define PM_AVAIL_CR2 (*(reg8 *) CYREG_PM_AVAIL_CR2) + + +/* Active Power Mode Configuration Register 5 */ +#define CY_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 ) + +/* Standby Power Mode Configuration Register 5 */ +#define CY_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 ) +#define CY_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 ) + + +#if(CY_PSOC3) + #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define FLSHID_MFG_CFG_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) + #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define FLSHID_CUST_TABLES_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #else + #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define FLSHID_MFG_CFG_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) + #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define FLSHID_CUST_TABLES_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB) +#endif /* (CY_PSOC3) */ + + +#define USB_CLKDIST_CONFIG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) +#define USB_CLKDIST_CONFIG (*(reg8 *) CYREG_CLKDIST_UCFG) + + +/******************************************************************************* +* Interrupt Registers +*******************************************************************************/ + +#if(CY_PSOC5) + + /* Interrupt Vector Table Offset */ + #define CY_INT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) + + /* Interrupt Priority 0-31 */ + #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_NVIC_PRI_0) + #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_NVIC_PRI_0) + + /* Interrupt Enable Set 0-31 */ + #define CY_INT_ENABLE_REG (* (reg32 *) CYREG_NVIC_SETENA0) + #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_NVIC_SETENA0) + + /* Interrupt Enable Clear 0-31 */ + #define CY_INT_CLEAR_REG (* (reg32 *) CYREG_NVIC_CLRENA0) + #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_NVIC_CLRENA0) + + /* Interrupt Pending Set 0-31 */ + #define CY_INT_SET_PEND_REG (* (reg32 *) CYREG_NVIC_SETPEND0) + #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_NVIC_SETPEND0) + + /* Interrupt Pending Clear 0-31 */ + #define CY_INT_CLR_PEND_REG (* (reg32 *) CYREG_NVIC_CLRPEND0) + #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_NVIC_CLRPEND0) + + /* Cache Control Register */ + #define CY_CACHE_CONTROL_REG (* (reg16 *) CYREG_CACHE_CC_CTL ) + #define CY_CACHE_CONTROL_PTR ( (reg16 *) CYREG_CACHE_CC_CTL ) + +#elif (CY_PSOC3) + + /* Interrupt Address Vector registers */ + #define CY_INT_VECT_TABLE ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE) + + /* Interrrupt Controller Priority Registers */ + #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_INTC_PRIOR0) + #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_INTC_PRIOR0) + + /* Interrrupt Controller Set Enable Registers */ + #define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0) + #define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0) + + #define CY_INT_SET_EN0_REG (* (reg8 *) CYREG_INTC_SET_EN0) + #define CY_INT_SET_EN0_PTR ( (reg8 *) CYREG_INTC_SET_EN0) + + #define CY_INT_SET_EN1_REG (* (reg8 *) CYREG_INTC_SET_EN1) + #define CY_INT_SET_EN1_PTR ( (reg8 *) CYREG_INTC_SET_EN1) + + #define CY_INT_SET_EN2_REG (* (reg8 *) CYREG_INTC_SET_EN2) + #define CY_INT_SET_EN2_PTR ( (reg8 *) CYREG_INTC_SET_EN2) + + #define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3) + #define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3) + + /* Interrrupt Controller Clear Enable Registers */ + #define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0) + #define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) + + #define CY_INT_CLR_EN0_REG (* (reg8 *) CYREG_INTC_CLR_EN0) + #define CY_INT_CLR_EN0_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) + + #define CY_INT_CLR_EN1_REG (* (reg8 *) CYREG_INTC_CLR_EN1) + #define CY_INT_CLR_EN1_PTR ( (reg8 *) CYREG_INTC_CLR_EN1) + + #define CY_INT_CLR_EN2_REG (* (reg8 *) CYREG_INTC_CLR_EN2) + #define CY_INT_CLR_EN2_PTR ( (reg8 *) CYREG_INTC_CLR_EN2) + + #define CY_INT_CLR_EN3_REG (* (reg8 *) CYREG_INTC_CLR_EN3) + #define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3) + + + /* Interrrupt Controller Set Pend Registers */ + #define CY_INT_SET_PEND_REG (* (reg8 *) CYREG_INTC_SET_PD0) + #define CY_INT_SET_PEND_PTR ( (reg8 *) CYREG_INTC_SET_PD0) + + /* Interrrupt Controller Clear Pend Registers */ + #define CY_INT_CLR_PEND_REG (* (reg8 *) CYREG_INTC_CLR_PD0) + #define CY_INT_CLR_PEND_PTR ( (reg8 *) CYREG_INTC_CLR_PD0) + + + /* Access Interrupt Controller Registers based on interrupt number */ + #define CY_INT_SET_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_CLR_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_CLR_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_SET_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Macro Name: CyAssert +******************************************************************************** +* Summary: +* Macro that evaluates the expression and if it is false (evaluates to 0) then +* the processor is halted. +* +* This macro is evaluated unless NDEBUG is defined. +* +* If NDEBUG is defined, then no code is generated for this macro. NDEBUG is +* defined by default for a Release build setting and not defined for a Debug +* build setting. +* +* Parameters: +* expr: Logical expression. Asserts if false. +* +* Return: +* None +* +*******************************************************************************/ +#if !defined(NDEBUG) + #define CYASSERT(x) { \ + if(!(x)) \ + { \ + CyHalt((uint8) 0u); \ + } \ + } +#else + #define CYASSERT(x) +#endif /* !defined(NDEBUG) */ + + +/* Reset register fields of RESET_SR0 (CyResetStatus) */ +#define CY_RESET_LVID (0x01u) +#define CY_RESET_LVIA (0x02u) +#define CY_RESET_HVIA (0x04u) +#define CY_RESET_WD (0x08u) +#define CY_RESET_SW (0x20u) +#define CY_RESET_GPIO0 (0x40u) +#define CY_RESET_GPIO1 (0x80u) + + +/* Interrrupt Controller Configuration and Status Register */ +#if(CY_PSOC3) + #define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN) + #define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */ + #define INTERRUPT_DISABLE_IRQ {*INTERRUPT_CSR |= DISABLE_IRQ_SET;} + #define INTERRUPT_ENABLE_IRQ {*INTERRUPT_CSR = (uint8)(~DISABLE_IRQ_SET);} +#endif /* (CY_PSOC3) */ + + +#if defined(__ARMCC_VERSION) + #define CyGlobalIntEnable {__enable_irq();} + #define CyGlobalIntDisable {__disable_irq();} +#elif defined(__GNUC__) + #define CyGlobalIntEnable {__asm("CPSIE i");} + #define CyGlobalIntDisable {__asm("CPSID i");} +#elif defined(__C51__) + #define CyGlobalIntEnable {\ + EA = 1u; \ + INTERRUPT_ENABLE_IRQ\ + } + + #define CyGlobalIntDisable {\ + INTERRUPT_DISABLE_IRQ; \ + CY_NOP; \ + EA = 0u;\ + } +#endif /* (__ARMCC_VERSION) */ + + +#ifdef CYREG_MLOGIC_CPU_SCR_CPU_SCR + #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x01u) +#else + #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR, 0x01u) +#endif /* (CYREG_MLOGIC_CPU_SCR_CPU_SCR) */ + + +#ifdef CYREG_MLOGIC_REV_ID_REV_ID + #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID_REV_ID)) +#else + #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID)) +#endif /* (CYREG_MLOGIC_REV_ID_REV_ID) */ + +#define RESET_CR2 ((reg8 *) CYREG_RESET_CR2) + + +/******************************************************************************* +* System API constants +*******************************************************************************/ +#define CY_CACHE_CONTROL_FLUSH (0x0004u) + + +/******************************************************************************* +* Interrupt API constants +*******************************************************************************/ +#if(CY_PSOC5) + + #define CY_INT_IRQ_BASE (16u) + +#elif (CY_PSOC3) + + #define CY_INT_IRQ_BASE (0u) + +#endif /* (CY_PSOC5) */ + +/* Valid range of interrupt 0-31 */ +#define CY_INT_NUMBER_MAX (31u) + +/* Valid range of system interrupt 0-15 */ +#define CY_INT_SYS_NUMBER_MAX (15u) + +/* Valid range of system priority 0-7 */ +#define CY_INT_PRIORITY_MAX (7u) + +/* Mask to get valid range of interrupt 0-31 */ +#define CY_INT_NUMBER_MASK (0x1Fu) + +/* Mask to get valid range of system priority 0-7 */ +#define CY_INT_PRIORITY_MASK (0x7u) + +/* Mask to get valid range of system interrupt 0-15 */ +#define CY_INT_SYS_NUMBER_MASK (0xFu) + + +/******************************************************************************* +* Interrupt Macros +*******************************************************************************/ + +#if(CY_PSOC5) + + /******************************************************************************* + * Macro Name: CyIntEnable + ******************************************************************************** + * + * Summary: + * Enables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntEnable(number) CY_SET_REG32(CY_INT_ENABLE_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + /******************************************************************************* + * Macro Name: CyIntDisable + ******************************************************************************** + * + * Summary: + * Disables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntDisable(number) CY_SET_REG32(CY_INT_CLEAR_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntSetPending + ******************************************************************************** + * + * Summary: + * Forces the specified interrupt number to be pending. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntSetPending(number) CY_SET_REG32(CY_INT_SET_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntClearPending + ******************************************************************************** + * + * Summary: + * Clears any pending interrupt for the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntClearPending(number) CY_SET_REG32(CY_INT_CLR_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + +#else /* PSoC3 */ + + + /******************************************************************************* + * Macro Name: CyIntEnable + ******************************************************************************** + * + * Summary: + * Enables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntEnable(number) CY_SET_REG8(CY_INT_SET_EN_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntDisable + ******************************************************************************** + * + * Summary: + * Disables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntDisable(number) CY_SET_REG8(CY_INT_CLR_EN_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntSetPending + ******************************************************************************** + * + * Summary: + * Forces the specified interrupt number to be pending. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntSetPending(number) CY_SET_REG8(CY_INT_SET_PEND_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntClearPending + ******************************************************************************** + * Summary: + * Clears any pending interrupt for the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntClearPending(number) CY_SET_REG8(CY_INT_CLR_PEND_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used. +*******************************************************************************/ +#define CYGlobalIntEnable CyGlobalIntEnable +#define CYGlobalIntDisable CyGlobalIntDisable + +#define cymemset(s,c,n) memset((s),(c),(n)) +#define cymemcpy(d,s,n) memcpy((d),(s),(n)) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 +*******************************************************************************/ +#define MFGCFG_X32_TR_PTR (CY_CLK_XTAL32_TR_PTR) +#define MFGCFG_X32_TR (CY_CLK_XTAL32_TR_REG) +#define SLOWCLK_X32_TST_PTR (CY_CLK_XTAL32_TST_PTR) +#define SLOWCLK_X32_TST (CY_CLK_XTAL32_TST_REG) +#define SLOWCLK_X32_CR_PTR (CY_CLK_XTAL32_CR_PTR) +#define SLOWCLK_X32_CR (CY_CLK_XTAL32_CR_REG) +#define SLOWCLK_X32_CFG_PTR (CY_CLK_XTAL32_CFG_PTR) +#define SLOWCLK_X32_CFG (CY_CLK_XTAL32_CFG_REG) + +#define X32_CONTROL_ANA_STAT (CY_CLK_XTAL32_CR_ANA_STAT) +#define X32_CONTROL_DIG_STAT (0x10u) +#define X32_CONTROL_LPM (CY_CLK_XTAL32_CR_LPM) +#define X32_CONTROL_LPM_POSITION (1u) +#define X32_CONTROL_X32EN (CY_CLK_XTAL32_CR_EN) +#if(CY_PSOC3 || CY_PSOC5LP) + #define X32_CONTROL_PDBEN (CY_CLK_XTAL32_CR_PDBEN) +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ +#define X32_TR_DPMODE (CY_CLK_XTAL32_TR_STARTUP) +#define X32_TR_CLEAR (CY_CLK_XTAL32_TR_POWERDOWN) +#define X32_TR_HPMODE (CY_CLK_XTAL32_TR_HIGH_POWER) +#define X32_TR_LPMODE (CY_CLK_XTAL32_TR_LOW_POWER) +#define X32_TST_SETALL (CY_CLK_XTAL32_TST_DEFAULT) +#define X32_CFG_LP_BITS_MASK (CY_CLK_XTAL32_CFG_LP_MASK) +#define X32_CFG_LP_DEFAULT (CY_CLK_XTAL32_CFG_LP_DEFAULT) +#define X32_CFG_LOWPOWERMODE (0x80u) +#define X32_CFG_LP_LOWPOWER (0x8u) +#define CY_X32_HIGHPOWER_MODE (0u) +#define CY_X32_LOWPOWER_MODE (1u) +#define CY_XTAL32K_DIG_STAT (0x10u) +#define CY_XTAL32K_STAT_FIELDS (0x30u) +#define CY_XTAL32K_DIG_STAT_UNSTABLE (0u) +#define CY_XTAL32K_ANA_STAT_UNSTABLE (0x0u) +#define CY_XTAL32K_STATUS (0x20u) + +#define FASTCLK_XMHZ_CSR_PTR (CY_CLK_XMHZ_CSR_PTR) +#define FASTCLK_XMHZ_CSR (CY_CLK_XMHZ_CSR_REG) +#define FASTCLK_XMHZ_CFG0_PTR (CY_CLK_XMHZ_CFG0_PTR) +#define FASTCLK_XMHZ_CFG0 (CY_CLK_XMHZ_CFG0_REG) +#define FASTCLK_XMHZ_CFG1_PTR (CY_CLK_XMHZ_CFG1_PTR) +#define FASTCLK_XMHZ_CFG1 (CY_CLK_XMHZ_CFG1_REG) +#define FASTCLK_XMHZ_GAINMASK (CY_CLK_XMHZ_CFG0_XCFG_MASK) +#define FASTCLK_XMHZ_VREFMASK (CY_CLK_XMHZ_CFG1_VREF_FB_MASK) +#define FASTCLK_XMHZ_VREF_WD_MASK (CY_CLK_XMHZ_CFG1_VREF_WD_MASK) +#define XMHZ_CONTROL_ENABLE (CY_CLK_XMHZ_CSR_ENABLE) +#define X32_CONTROL_XERR_MASK (CY_CLK_XMHZ_CSR_XERR) +#define X32_CONTROL_XERR_DIS (CY_CLK_XMHZ_CSR_XFB) +#define X32_CONTROL_XERR_POSITION (7u) +#define X32_CONTROL_FAULT_RECOVER (CY_CLK_XMHZ_CSR_XPROT) + +#define CYWDT_CFG (CY_WDT_CFG_PTR) +#define CYWDT_CR (CY_WDT_CR_PTR) + +#define CYWDT_TICKS_MASK (CY_WDT_CFG_INTERVAL_MASK) +#define CYWDT_RESET (CY_WDT_CFG_CTW_RESET) +#define CYWDT_LPMODE_SHIFT (CY_WDT_CFG_LPMODE_SHIFT) +#define CYWDT_LPMODE_MASK (CY_WDT_CFG_LPMODE_MASK) +#define CYWDT_ENABLE_BIT (CY_WDT_CFG_WDR_EN) + +#define FASTCLK_PLL_CFG0_PTR (CY_CLK_PLL_CFG0_PTR) +#define FASTCLK_PLL_CFG0 (CY_CLK_PLL_CFG0_REG) +#define FASTCLK_PLL_SR_PTR (CY_CLK_PLL_SR_PTR) +#define FASTCLK_PLL_SR (CY_CLK_PLL_SR_REG) + +#define MAX_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MAX_Q_VALUE) +#define MIN_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MIN_Q_VALUE) +#define MIN_FASTCLK_PLL_P_VALUE (CY_CLK_PLL_MIN_P_VALUE) +#define MIN_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MIN_CUR_VALUE) +#define MAX_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MAX_CUR_VALUE) + +#define PLL_CONTROL_ENABLE (CY_CLK_PLL_ENABLE) +#define PLL_STATUS_LOCK (CY_CLK_PLL_LOCK_STATUS) +#define PLL_STATUS_ENABLED (CY_CLK_PLL_ENABLE) +#define PLL_CURRENT_POSITION (CY_CLK_PLL_CURRENT_POSITION) +#define PLL_VCO_GAIN_2 (2u) + +#define FASTCLK_PLL_Q_PTR (CY_CLK_PLL_Q_PTR) +#define FASTCLK_PLL_Q (CY_CLK_PLL_Q_REG) +#define FASTCLK_PLL_P_PTR (CY_CLK_PLL_P_PTR) +#define FASTCLK_PLL_P (CY_CLK_PLL_P_REG) +#define FASTCLK_PLL_CFG1_PTR (CY_CLK_PLL_CFG1_REG) +#define FASTCLK_PLL_CFG1 (CY_CLK_PLL_CFG1_REG) + +#define CY_VD_PRESISTENT_STATUS_REG (CY_VD_PERSISTENT_STATUS_REG) +#define CY_VD_PRESISTENT_STATUS_PTR (CY_VD_PERSISTENT_STATUS_PTR) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.20 +*******************************************************************************/ + +#if(CY_PSOC5) + + #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) + + #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) + #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) + #define CYINT_ENABLE (CY_INT_ENABLE_PTR) + #define CYINT_CLEAR (CY_INT_CLEAR_PTR) + #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) + #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) + #define CACHE_CC_CTL (CY_CACHE_CONTROL_PTR) + +#elif (CY_PSOC3) + + #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) + + #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) + #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) + #define CYINT_ENABLE (CY_INT_ENABLE_PTR) + #define CYINT_CLEAR (CY_INT_CLEAR_PTR) + #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) + #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 +*******************************************************************************/ +#define BUS_AMASK_CLEAR (0xF0u) +#define BUS_DMASK_CLEAR (0x00u) +#define CLKDIST_LD_LOAD_SET (0x01u) +#define CLKDIST_WRK0_MASK_SET (0x80u) /* Enable shadow loads */ +#define MASTERCLK_DIVIDER_VALUE (7u) +#define CLKDIST_BCFG2_SSS_SET (0x40u) /* Sync source is same frequency */ +#define MASTER_CLK_SRC_CLEAR (0xFCu) +#define IMO_DOUBLER_ENABLE (0x10u) +#define CLOCK_IMO_IMO (0x20u) +#define CLOCK_IMO2X_XTAL (0x40u) +#define CLOCK_IMO_RANGE_CLEAR (0xF8u) +#define CLOCK_CONTROL_DIST_MASK (0xFCu) + + +#define CLKDIST_AMASK (*(reg8 *) CYREG_CLKDIST_AMASK) +#define CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK) +#define CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) +#define CLKDIST_DMASK (*(reg8 *) CYREG_CLKDIST_DMASK) +#define CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) +#define CLKDIST_BCFG2 (*(reg8 *) CYREG_CLKDIST_BCFG2) +#define CLKDIST_WRK0_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) +#define CLKDIST_WRK0 (*(reg8 *) CYREG_CLKDIST_WRK0) +#define CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) +#define CLKDIST_LD (*(reg8 *) CYREG_CLKDIST_LD) +#define CLKDIST_BCFG0_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) +#define CLKDIST_BCFG0 (*(reg8 *) CYREG_CLKDIST_BCFG0) +#define CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) +#define CLKDIST_MSTR0 (*(reg8 *) CYREG_CLKDIST_MSTR0) +#define FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) +#define FASTCLK_IMO_CR (*(reg8 *) CYREG_FASTCLK_IMO_CR) +#define CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) +#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR) + +#endif /* (CY_BOOT_CYLIB_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c new file mode 100644 index 0000000..759f7a7 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c @@ -0,0 +1,562 @@ +/******************************************************************************* +* File Name: CySpc.c +* Version 3.40 +* +* Description: +* Provides an API for the System Performance Component. +* The SPC functions are not meant to be called directly by the user +* application. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CySpc.h" + +#define CY_SPC_KEY_ONE (0xB6u) +#define CY_SPC_KEY_TWO(x) ((uint8) (((uint16) 0xD3u) + ((uint16) (x)))) + +/* Command Codes */ +#define CY_SPC_CMD_LD_BYTE (0x00u) +#define CY_SPC_CMD_LD_MULTI_BYTE (0x01u) +#define CY_SPC_CMD_LD_ROW (0x02u) +#define CY_SPC_CMD_RD_BYTE (0x03u) +#define CY_SPC_CMD_RD_MULTI_BYTE (0x04u) +#define CY_SPC_CMD_WR_ROW (0x05u) +#define CY_SPC_CMD_WR_USER_NVL (0x06u) +#define CY_SPC_CMD_PRG_ROW (0x07u) +#define CY_SPC_CMD_ER_SECTOR (0x08u) +#define CY_SPC_CMD_ER_ALL (0x09u) +#define CY_SPC_CMD_RD_HIDDEN (0x0Au) +#define CY_SPC_CMD_PRG_PROTECT (0x0Bu) +#define CY_SPC_CMD_CHECKSUM (0x0Cu) +#define CY_SPC_CMD_DWNLD_ALGORITHM (0x0Du) +#define CY_SPC_CMD_GET_TEMP (0x0Eu) +#define CY_SPC_CMD_GET_ADC (0x0Fu) +#define CY_SPC_CMD_RD_NVL_VOLATILE (0x10u) +#define CY_SPC_CMD_SETUP_TS (0x11u) +#define CY_SPC_CMD_DISABLE_TS (0x12u) +#define CY_SPC_CMD_ER_ROW (0x13u) + +/* Enable bit in Active and Alternate Active mode templates */ +#define PM_SPC_PM_EN (0x08u) + +/* Gate calls to the SPC. */ +uint8 SpcLockState = CY_SPC_UNLOCKED; + + +#if(CY_PSOC5LP) + + /*************************************************************************** + * The wait-state pipeline must be enabled prior to accessing the SPC + * register interface regardless of CPU frequency. The CySpcLock() saves + * current wait-state pipeline state and enables it. The CySpcUnlock() + * function, which must be called after SPC transaction, restores original + * state. + ***************************************************************************/ + static uint8 spcWaitPipeBypass = 0u; + +#endif /* (CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: CySpcStart +******************************************************************************** +* Summary: +* Starts the SPC. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySpcStart(void) +{ + /* Save current global interrupt enable and disable it */ + uint8 interruptState = CyEnterCriticalSection(); + + CY_SPC_PM_ACT_REG |= PM_SPC_PM_EN; + CY_SPC_PM_STBY_REG |= PM_SPC_PM_EN; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcStop +******************************************************************************** +* Summary: +* Stops the SPC. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySpcStop(void) +{ + /* Save current global interrupt enable and disable it */ + uint8 interruptState = CyEnterCriticalSection(); + + CY_SPC_PM_ACT_REG &= ((uint8)(~PM_SPC_PM_EN)); + CY_SPC_PM_STBY_REG &= ((uint8)(~PM_SPC_PM_EN)); + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcReadData +******************************************************************************** +* Summary: +* Reads data from the SPC. +* +* Parameters: +* uint8 buffer: +* Address to store data read. +* +* uint8 size: +* Number of bytes to read from the SPC. +* +* Return: +* uint8: +* The number of bytes read from the SPC. +* +*******************************************************************************/ +uint8 CySpcReadData(uint8 buffer[], uint8 size) +{ + uint8 i; + + for(i = 0u; i < size; i++) + { + while(!CY_SPC_DATA_READY) + { + CyDelayUs(1u); + } + buffer[i] = CY_SPC_CPU_DATA_REG; + } + + return(i); +} + + +/******************************************************************************* +* Function Name: CySpcLoadMultiByte +******************************************************************************** +* Summary: +* Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array. +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint16 address: +* Flash/eeprom addrress +* +* uint8* buffer: +* Data to load to the row latch +* +* uint16 number: +* Number bytes to load. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* CYRET_BAD_PARAM +* +*******************************************************************************/ +cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size) +{ + cystatus status = CYRET_STARTED; + uint8 i; + + /*************************************************************************** + * Check if number is correct for array. Number must be less than + * 32 for Flash or less than 16 for EEPROM. + ***************************************************************************/ + if(((array < CY_SPC_LAST_FLASH_ARRAYID) && (size < 32u)) || + ((array > CY_SPC_LAST_FLASH_ARRAYID) && (size < 16u))) + { + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_MULTI_BYTE); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_MULTI_BYTE; + + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = 1u & HI8(address); + CY_SPC_CPU_DATA_REG = LO8(address); + CY_SPC_CPU_DATA_REG = ((uint8)(size - 1u)); + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLoadRow +******************************************************************************** +* Summary: +* Loads a row of data into the row latch of a Flash/EEPROM array. +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint8* buffer: +* Data to be loaded to the row latch +* +* uint8 size: +* The number of data bytes that the SPC expects to be written. Depends on the +* type of the array and, if the array is Flash, whether ECC is being enabled +* or not. There are following values: flash row latch size with ECC enabled, +* flash row latch size with ECC disabled and EEPROM row latch size. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size) +{ + cystatus status = CYRET_STARTED; + uint16 i; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcWriteRow +******************************************************************************** +* Summary: +* Erases then programs a row in Flash/EEPROM with data in row latch. +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint16 address: +* flash/eeprom addrress +* +* uint8 tempPolarity: +* temperature polarity. +* 1: the Temp Magnitude is interpreted as a positive value +* 0: the Temp Magnitude is interpreted as a negative value +* +* uint8 tempMagnitude: +* temperature magnitude. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_WR_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_WR_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = HI8(address); + CY_SPC_CPU_DATA_REG = LO8(address); + CY_SPC_CPU_DATA_REG = tempPolarity; + CY_SPC_CPU_DATA_REG = tempMagnitude; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcEraseSector +******************************************************************************** +* Summary: +* Erases all data in the addressed sector (block of 64 rows). +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint8 sectorNumber: +* Zero based sector number within Flash/EEPROM array +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_SECTOR); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_SECTOR; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = sectorNumber; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcGetTemp +******************************************************************************** +* Summary: +* Returns the internal die temperature +* +* Parameters: +* uint8 numSamples: +* Number of samples. Valid values are 1-5, resulting in 2 - 32 samples +* respectively. +* +* uint16 timerPeriod: +* Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits +* of 16 bit values are ignored. +* +* uint8 clkDivSelect: +* ADC ACLK clock divide value. Valid values are 2 - 225. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +#if(CY_PSOC5A) +cystatus CySpcGetTemp(uint8 numSamples, uint16 timerPeriod, uint8 clkDivSelect) +#else +cystatus CySpcGetTemp(uint8 numSamples) +#endif /* (CY_PSOC5A) */ +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_GET_TEMP); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_GET_TEMP; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = numSamples; + + #if(CY_PSOC5A) + CY_SPC_CPU_DATA_REG = HI8(timerPeriod); + CY_SPC_CPU_DATA_REG = LO8(timerPeriod); + CY_SPC_CPU_DATA_REG = clkDivSelect; + #endif /* (CY_PSOC5A) */ + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLock +******************************************************************************** +* Summary: +* Locks the SPC so it can not be used by someone else: +* - Saves wait-pipeline enable state and enable pipeline (PSoC5) +* +* Parameters: +* Note +* +* Return: +* CYRET_SUCCESS - if the resource was free. +* CYRET_LOCKED - if the SPC is in use. +* +*******************************************************************************/ +cystatus CySpcLock(void) +{ + cystatus status = CYRET_LOCKED; + uint8 interruptState; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + if(CY_SPC_UNLOCKED == SpcLockState) + { + SpcLockState = CY_SPC_LOCKED; + status = CYRET_SUCCESS; + + #if(CY_PSOC5LP) + + if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS)) + { + /* Enable pipeline registers */ + CY_SPC_CPU_WAITPIPE_REG &= ((uint32)(~CY_SPC_CPU_WAITPIPE_BYPASS)); + + /* At least 2 NOP instructions are recommended */ + CY_NOP; + CY_NOP; + CY_NOP; + + spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS; + } + + #endif /* (CY_PSOC5LP) */ + } + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcUnlock +******************************************************************************** +* Summary: +* Unlocks the SPC so it can be used by someone else: +* - Restores wait-pipeline enable state (PSoC5) +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySpcUnlock(void) +{ + uint8 interruptState; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Release the SPC object */ + SpcLockState = CY_SPC_UNLOCKED; + + #if(CY_PSOC5LP) + + if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass) + { + /* Force to bypass pipeline registers */ + CY_SPC_CPU_WAITPIPE_REG |= CY_SPC_CPU_WAITPIPE_BYPASS; + + /* At least 2 NOP instructions are recommended */ + CY_NOP; + CY_NOP; + CY_NOP; + + spcWaitPipeBypass = 0u; + } + + #endif /* (CY_PSOC5LP) */ + + /* Exit critical section */ + CyExitCriticalSection(interruptState); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h new file mode 100644 index 0000000..eb3683e --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h @@ -0,0 +1,159 @@ +/******************************************************************************* +* File Name: CySpc.c +* Version 3.40 +* +* Description: +* Provides definitions for the System Performance Component API. +* The SPC functions are not meant to be called directly by the user +* application. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYSPC_H) +#define CY_BOOT_CYSPC_H + +#include "cytypes.h" +#include "CyLib.h" +#include "cydevice_trm.h" + + +/*************************************** +* Global Variables +***************************************/ +extern uint8 SpcLockState; + + +/*************************************** +* Function Prototypes +***************************************/ +void CySpcStart(void); +void CySpcStop(void); +uint8 CySpcReadData(uint8 buffer[], uint8 size); +cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size) ; +cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size); +cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude) ; +cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber); + +#if(CY_PSOC5A) + cystatus CySpcGetTemp(uint8 numSamples, uint16 timerPeriod, uint8 clkDivSelect); +#else + cystatus CySpcGetTemp(uint8 numSamples); +#endif /* (CY_PSOC5A) */ + + +cystatus CySpcLock(void); +void CySpcUnlock(void); + + +/*************************************** +* API Constants +***************************************/ + +#define CY_SPC_LOCKED (0x01u) +#define CY_SPC_UNLOCKED (0x00u) + +/******************************************************************************* +* The Array ID indicates the unique ID of the SONOS array being accessed: +* - 0x00-0x3E : Flash Arrays +* - 0x3F : Selects all Flash arrays simultaneously +* - 0x40-0x7F : Embedded EEPROM Arrays +*******************************************************************************/ +#define CY_SPC_FIRST_FLASH_ARRAYID (0x00u) +#define CY_SPC_LAST_FLASH_ARRAYID (0x3Fu) +#define CY_SPC_FIRST_EE_ARRAYID (0x40u) +#define CY_SPC_LAST_EE_ARRAYID (0x7Fu) + + +#define CY_SPC_STATUS_DATA_READY_MASK (0x01u) +#define CY_SPC_STATUS_IDLE_MASK (0x02u) +#define CY_SPC_STATUS_CODE_MASK (0xFCu) +#define CY_SPC_STATUS_CODE_SHIFT (0x02u) + +/* Status codes for the SPC. */ +#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */ +#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */ +#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */ +#define CY_SPC_STATUS_ARRAY_ASLEEP (0x03u) /* Addressed Array is Asleep */ +#define CY_SPC_STATUS_EXTERN_ACCESS (0x04u) /* External Access Failure (SPC is not in external access mode) */ +#define CY_SPC_STATUS_INVALID_NUMBER (0x05u) /* Invalid 'N' Value for given command */ +#define CY_SPC_STATUS_TEST_MODE (0x06u) /* Test Mode Failure (SPC is not in test mode) */ +#define CY_SPC_STATUS_ALG_CSUM (0x07u) /* Smart Write Algorithm Checksum Failure */ +#define CY_SPC_STATUS_PARAM_CSUM (0x08u) /* Smart Write Parameter Checksum Failure */ +#define CY_SPC_STATUS_PROTECTION (0x09u) /* Protection Check Failure */ +#define CY_SPC_STATUS_ADDRESS_PARAM (0x0Au) /* Invalid Address parameter for the given command */ +#define CY_SPC_STATUS_COMMAND_CODE (0x0Bu) /* Invalid Command Code */ +#define CY_SPC_STATUS_ROW_ID (0x0Cu) /* Invalid Row ID parameter for given command */ +#define CY_SPC_STATUS_TADC_INPUT (0x0Du) /* Invalid input value for Get Temp & Get ADC commands */ +#define CY_SPC_STATUS_BUSY (0xFFu) /* SPC is busy */ + +#if(CY_PSOC5LP) + + /* Wait-state pipeline */ + #define CY_SPC_CPU_WAITPIPE_BYPASS ((uint32)0x01u) + +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Registers +***************************************/ + +/* SPC CPU Data Register */ +#define CY_SPC_CPU_DATA_REG (* (reg8 *) CYREG_SPC_CPU_DATA ) +#define CY_SPC_CPU_DATA_PTR ( (reg8 *) CYREG_SPC_CPU_DATA ) + +/* SPC Status Register */ +#define CY_SPC_STATUS_REG (* (reg8 *) CYREG_SPC_SR ) +#define CY_SPC_STATUS_PTR ( (reg8 *) CYREG_SPC_SR ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_SPC_PM_ACT_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) +#define CY_SPC_PM_ACT_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) + +/* Standby Power Mode Configuration Register 0 */ +#define CY_SPC_PM_STBY_REG (* (reg8 *) CYREG_PM_STBY_CFG0 ) +#define CY_SPC_PM_STBY_PTR ( (reg8 *) CYREG_PM_STBY_CFG0 ) + +#if(CY_PSOC5LP) + + /* Wait State Pipeline */ + #define CY_SPC_CPU_WAITPIPE_REG (* (reg32 *) CYREG_PANTHER_WAITPIPE ) + #define CY_SPC_CPU_WAITPIPE_PTR ( (reg32 *) CYREG_PANTHER_WAITPIPE ) + +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Macros +***************************************/ +#define CY_SPC_IDLE (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) +#define CY_SPC_BUSY (0u == (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) +#define CY_SPC_DATA_READY (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_DATA_READY_MASK)) + +/* SPC must be in idle state in order to obtain correct status */ +#define CY_SPC_READ_STATUS (CY_SPC_IDLE ? \ + ((uint8)(CY_SPC_STATUS_REG >> CY_SPC_STATUS_CODE_SHIFT)) : \ + ((uint8) CY_SPC_STATUS_BUSY)) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 +*******************************************************************************/ +#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID) +#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID) +#define FIRST_EE_ARRAYID (CY_SPC_FIRST_EE_ARRAYID) +#define LAST_EE_ARRAYID (CY_SPC_LAST_EE_ARRAYID) +#define SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) +#define SIZEOF_FLASH_ROW (CYDEV_FLS_ROW_SIZE) +#define SIZEOF_EEPROM_ROW (CYDEV_EEPROM_ROW_SIZE) + + +#endif /* (CY_BOOT_CYSPC_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c new file mode 100644 index 0000000..a70ea8e --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: LED1.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "LED1.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: LED1_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void LED1_Write(uint8 value) +{ + uint8 staticBits = (LED1_DR & (uint8)(~LED1_MASK)); + LED1_DR = staticBits | ((uint8)(value << LED1_SHIFT) & LED1_MASK); +} + + +/******************************************************************************* +* Function Name: LED1_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void LED1_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(LED1_0, mode); +} + + +/******************************************************************************* +* Function Name: LED1_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro LED1_ReadPS calls this function. +* +*******************************************************************************/ +uint8 LED1_Read(void) +{ + return (LED1_PS & LED1_MASK) >> LED1_SHIFT; +} + + +/******************************************************************************* +* Function Name: LED1_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 LED1_ReadDataReg(void) +{ + return (LED1_DR & LED1_MASK) >> LED1_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(LED1_INTSTAT) + + /******************************************************************************* + * Function Name: LED1_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 LED1_ClearInterrupt(void) + { + return (LED1_INTSTAT & LED1_MASK) >> LED1_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h new file mode 100644 index 0000000..7eb7d8d --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: LED1.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED1_H) /* Pins LED1_H */ +#define CY_PINS_LED1_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "LED1_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void LED1_Write(uint8 value) ; +void LED1_SetDriveMode(uint8 mode) ; +uint8 LED1_ReadDataReg(void) ; +uint8 LED1_Read(void) ; +uint8 LED1_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define LED1_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define LED1_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define LED1_DM_RES_UP PIN_DM_RES_UP +#define LED1_DM_RES_DWN PIN_DM_RES_DWN +#define LED1_DM_OD_LO PIN_DM_OD_LO +#define LED1_DM_OD_HI PIN_DM_OD_HI +#define LED1_DM_STRONG PIN_DM_STRONG +#define LED1_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define LED1_MASK LED1__MASK +#define LED1_SHIFT LED1__SHIFT +#define LED1_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define LED1_PS (* (reg8 *) LED1__PS) +/* Data Register */ +#define LED1_DR (* (reg8 *) LED1__DR) +/* Port Number */ +#define LED1_PRT_NUM (* (reg8 *) LED1__PRT) +/* Connect to Analog Globals */ +#define LED1_AG (* (reg8 *) LED1__AG) +/* Analog MUX bux enable */ +#define LED1_AMUX (* (reg8 *) LED1__AMUX) +/* Bidirectional Enable */ +#define LED1_BIE (* (reg8 *) LED1__BIE) +/* Bit-mask for Aliased Register Access */ +#define LED1_BIT_MASK (* (reg8 *) LED1__BIT_MASK) +/* Bypass Enable */ +#define LED1_BYP (* (reg8 *) LED1__BYP) +/* Port wide control signals */ +#define LED1_CTL (* (reg8 *) LED1__CTL) +/* Drive Modes */ +#define LED1_DM0 (* (reg8 *) LED1__DM0) +#define LED1_DM1 (* (reg8 *) LED1__DM1) +#define LED1_DM2 (* (reg8 *) LED1__DM2) +/* Input Buffer Disable Override */ +#define LED1_INP_DIS (* (reg8 *) LED1__INP_DIS) +/* LCD Common or Segment Drive */ +#define LED1_LCD_COM_SEG (* (reg8 *) LED1__LCD_COM_SEG) +/* Enable Segment LCD */ +#define LED1_LCD_EN (* (reg8 *) LED1__LCD_EN) +/* Slew Rate Control */ +#define LED1_SLW (* (reg8 *) LED1__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define LED1_PRTDSI__CAPS_SEL (* (reg8 *) LED1__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define LED1_PRTDSI__DBL_SYNC_IN (* (reg8 *) LED1__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define LED1_PRTDSI__OE_SEL0 (* (reg8 *) LED1__PRTDSI__OE_SEL0) +#define LED1_PRTDSI__OE_SEL1 (* (reg8 *) LED1__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define LED1_PRTDSI__OUT_SEL0 (* (reg8 *) LED1__PRTDSI__OUT_SEL0) +#define LED1_PRTDSI__OUT_SEL1 (* (reg8 *) LED1__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define LED1_PRTDSI__SYNC_OUT (* (reg8 *) LED1__PRTDSI__SYNC_OUT) + + +#if defined(LED1__INTSTAT) /* Interrupt Registers */ + + #define LED1_INTSTAT (* (reg8 *) LED1__INTSTAT) + #define LED1_SNAP (* (reg8 *) LED1__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_LED1_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h new file mode 100644 index 0000000..040612f --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: LED1.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED1_ALIASES_H) /* Pins LED1_ALIASES_H */ +#define CY_PINS_LED1_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define LED1_0 LED1__0__PC + +#endif /* End Pins LED1_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.c new file mode 100644 index 0000000..d5642c3 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: PARITY_EN.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "PARITY_EN.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + PARITY_EN__PORT == 15 && ((PARITY_EN__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: PARITY_EN_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void PARITY_EN_Write(uint8 value) +{ + uint8 staticBits = (PARITY_EN_DR & (uint8)(~PARITY_EN_MASK)); + PARITY_EN_DR = staticBits | ((uint8)(value << PARITY_EN_SHIFT) & PARITY_EN_MASK); +} + + +/******************************************************************************* +* Function Name: PARITY_EN_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void PARITY_EN_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(PARITY_EN_0, mode); +} + + +/******************************************************************************* +* Function Name: PARITY_EN_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro PARITY_EN_ReadPS calls this function. +* +*******************************************************************************/ +uint8 PARITY_EN_Read(void) +{ + return (PARITY_EN_PS & PARITY_EN_MASK) >> PARITY_EN_SHIFT; +} + + +/******************************************************************************* +* Function Name: PARITY_EN_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 PARITY_EN_ReadDataReg(void) +{ + return (PARITY_EN_DR & PARITY_EN_MASK) >> PARITY_EN_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(PARITY_EN_INTSTAT) + + /******************************************************************************* + * Function Name: PARITY_EN_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 PARITY_EN_ClearInterrupt(void) + { + return (PARITY_EN_INTSTAT & PARITY_EN_MASK) >> PARITY_EN_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.h new file mode 100644 index 0000000..75953b0 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: PARITY_EN.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_PARITY_EN_H) /* Pins PARITY_EN_H */ +#define CY_PINS_PARITY_EN_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "PARITY_EN_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + PARITY_EN__PORT == 15 && ((PARITY_EN__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void PARITY_EN_Write(uint8 value) ; +void PARITY_EN_SetDriveMode(uint8 mode) ; +uint8 PARITY_EN_ReadDataReg(void) ; +uint8 PARITY_EN_Read(void) ; +uint8 PARITY_EN_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define PARITY_EN_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define PARITY_EN_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define PARITY_EN_DM_RES_UP PIN_DM_RES_UP +#define PARITY_EN_DM_RES_DWN PIN_DM_RES_DWN +#define PARITY_EN_DM_OD_LO PIN_DM_OD_LO +#define PARITY_EN_DM_OD_HI PIN_DM_OD_HI +#define PARITY_EN_DM_STRONG PIN_DM_STRONG +#define PARITY_EN_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define PARITY_EN_MASK PARITY_EN__MASK +#define PARITY_EN_SHIFT PARITY_EN__SHIFT +#define PARITY_EN_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define PARITY_EN_PS (* (reg8 *) PARITY_EN__PS) +/* Data Register */ +#define PARITY_EN_DR (* (reg8 *) PARITY_EN__DR) +/* Port Number */ +#define PARITY_EN_PRT_NUM (* (reg8 *) PARITY_EN__PRT) +/* Connect to Analog Globals */ +#define PARITY_EN_AG (* (reg8 *) PARITY_EN__AG) +/* Analog MUX bux enable */ +#define PARITY_EN_AMUX (* (reg8 *) PARITY_EN__AMUX) +/* Bidirectional Enable */ +#define PARITY_EN_BIE (* (reg8 *) PARITY_EN__BIE) +/* Bit-mask for Aliased Register Access */ +#define PARITY_EN_BIT_MASK (* (reg8 *) PARITY_EN__BIT_MASK) +/* Bypass Enable */ +#define PARITY_EN_BYP (* (reg8 *) PARITY_EN__BYP) +/* Port wide control signals */ +#define PARITY_EN_CTL (* (reg8 *) PARITY_EN__CTL) +/* Drive Modes */ +#define PARITY_EN_DM0 (* (reg8 *) PARITY_EN__DM0) +#define PARITY_EN_DM1 (* (reg8 *) PARITY_EN__DM1) +#define PARITY_EN_DM2 (* (reg8 *) PARITY_EN__DM2) +/* Input Buffer Disable Override */ +#define PARITY_EN_INP_DIS (* (reg8 *) PARITY_EN__INP_DIS) +/* LCD Common or Segment Drive */ +#define PARITY_EN_LCD_COM_SEG (* (reg8 *) PARITY_EN__LCD_COM_SEG) +/* Enable Segment LCD */ +#define PARITY_EN_LCD_EN (* (reg8 *) PARITY_EN__LCD_EN) +/* Slew Rate Control */ +#define PARITY_EN_SLW (* (reg8 *) PARITY_EN__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define PARITY_EN_PRTDSI__CAPS_SEL (* (reg8 *) PARITY_EN__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define PARITY_EN_PRTDSI__DBL_SYNC_IN (* (reg8 *) PARITY_EN__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define PARITY_EN_PRTDSI__OE_SEL0 (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL0) +#define PARITY_EN_PRTDSI__OE_SEL1 (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define PARITY_EN_PRTDSI__OUT_SEL0 (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL0) +#define PARITY_EN_PRTDSI__OUT_SEL1 (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define PARITY_EN_PRTDSI__SYNC_OUT (* (reg8 *) PARITY_EN__PRTDSI__SYNC_OUT) + + +#if defined(PARITY_EN__INTSTAT) /* Interrupt Registers */ + + #define PARITY_EN_INTSTAT (* (reg8 *) PARITY_EN__INTSTAT) + #define PARITY_EN_SNAP (* (reg8 *) PARITY_EN__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_PARITY_EN_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN_aliases.h new file mode 100644 index 0000000..04919da --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: PARITY_EN.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_PARITY_EN_ALIASES_H) /* Pins PARITY_EN_ALIASES_H */ +#define CY_PINS_PARITY_EN_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define PARITY_EN_0 PARITY_EN__0__PC + +#endif /* End Pins PARITY_EN_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ID_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ID_aliases.h new file mode 100644 index 0000000..0cdbb60 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ID_aliases.h @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: SCSI_ID.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_ID_ALIASES_H) /* Pins SCSI_ID_ALIASES_H */ +#define CY_PINS_SCSI_ID_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_ID_0 SCSI_ID__0__PC +#define SCSI_ID_1 SCSI_ID__1__PC +#define SCSI_ID_2 SCSI_ID__2__PC + +#endif /* End Pins SCSI_ID_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx.c new file mode 100644 index 0000000..5d14607 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx.c @@ -0,0 +1,144 @@ +/******************************************************************************* +* File Name: SCSI_In_DBx.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SCSI_In_DBx.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SCSI_In_DBx__PORT == 15 && ((SCSI_In_DBx__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SCSI_In_DBx_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_In_DBx_Write(uint8 value) +{ + uint8 staticBits = (SCSI_In_DBx_DR & (uint8)(~SCSI_In_DBx_MASK)); + SCSI_In_DBx_DR = staticBits | ((uint8)(value << SCSI_In_DBx_SHIFT) & SCSI_In_DBx_MASK); +} + + +/******************************************************************************* +* Function Name: SCSI_In_DBx_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_In_DBx_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SCSI_In_DBx_0, mode); + CyPins_SetPinDriveMode(SCSI_In_DBx_1, mode); + CyPins_SetPinDriveMode(SCSI_In_DBx_2, mode); + CyPins_SetPinDriveMode(SCSI_In_DBx_3, mode); + CyPins_SetPinDriveMode(SCSI_In_DBx_4, mode); + CyPins_SetPinDriveMode(SCSI_In_DBx_5, mode); + CyPins_SetPinDriveMode(SCSI_In_DBx_6, mode); + CyPins_SetPinDriveMode(SCSI_In_DBx_7, mode); +} + + +/******************************************************************************* +* Function Name: SCSI_In_DBx_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SCSI_In_DBx_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SCSI_In_DBx_Read(void) +{ + return (SCSI_In_DBx_PS & SCSI_In_DBx_MASK) >> SCSI_In_DBx_SHIFT; +} + + +/******************************************************************************* +* Function Name: SCSI_In_DBx_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SCSI_In_DBx_ReadDataReg(void) +{ + return (SCSI_In_DBx_DR & SCSI_In_DBx_MASK) >> SCSI_In_DBx_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SCSI_In_DBx_INTSTAT) + + /******************************************************************************* + * Function Name: SCSI_In_DBx_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SCSI_In_DBx_ClearInterrupt(void) + { + return (SCSI_In_DBx_INTSTAT & SCSI_In_DBx_MASK) >> SCSI_In_DBx_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx.h new file mode 100644 index 0000000..23ee284 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SCSI_In_DBx.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_In_DBx_H) /* Pins SCSI_In_DBx_H */ +#define CY_PINS_SCSI_In_DBx_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SCSI_In_DBx_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SCSI_In_DBx__PORT == 15 && ((SCSI_In_DBx__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_In_DBx_Write(uint8 value) ; +void SCSI_In_DBx_SetDriveMode(uint8 mode) ; +uint8 SCSI_In_DBx_ReadDataReg(void) ; +uint8 SCSI_In_DBx_Read(void) ; +uint8 SCSI_In_DBx_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SCSI_In_DBx_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SCSI_In_DBx_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SCSI_In_DBx_DM_RES_UP PIN_DM_RES_UP +#define SCSI_In_DBx_DM_RES_DWN PIN_DM_RES_DWN +#define SCSI_In_DBx_DM_OD_LO PIN_DM_OD_LO +#define SCSI_In_DBx_DM_OD_HI PIN_DM_OD_HI +#define SCSI_In_DBx_DM_STRONG PIN_DM_STRONG +#define SCSI_In_DBx_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SCSI_In_DBx_MASK SCSI_In_DBx__MASK +#define SCSI_In_DBx_SHIFT SCSI_In_DBx__SHIFT +#define SCSI_In_DBx_WIDTH 8u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SCSI_In_DBx_PS (* (reg8 *) SCSI_In_DBx__PS) +/* Data Register */ +#define SCSI_In_DBx_DR (* (reg8 *) SCSI_In_DBx__DR) +/* Port Number */ +#define SCSI_In_DBx_PRT_NUM (* (reg8 *) SCSI_In_DBx__PRT) +/* Connect to Analog Globals */ +#define SCSI_In_DBx_AG (* (reg8 *) SCSI_In_DBx__AG) +/* Analog MUX bux enable */ +#define SCSI_In_DBx_AMUX (* (reg8 *) SCSI_In_DBx__AMUX) +/* Bidirectional Enable */ +#define SCSI_In_DBx_BIE (* (reg8 *) SCSI_In_DBx__BIE) +/* Bit-mask for Aliased Register Access */ +#define SCSI_In_DBx_BIT_MASK (* (reg8 *) SCSI_In_DBx__BIT_MASK) +/* Bypass Enable */ +#define SCSI_In_DBx_BYP (* (reg8 *) SCSI_In_DBx__BYP) +/* Port wide control signals */ +#define SCSI_In_DBx_CTL (* (reg8 *) SCSI_In_DBx__CTL) +/* Drive Modes */ +#define SCSI_In_DBx_DM0 (* (reg8 *) SCSI_In_DBx__DM0) +#define SCSI_In_DBx_DM1 (* (reg8 *) SCSI_In_DBx__DM1) +#define SCSI_In_DBx_DM2 (* (reg8 *) SCSI_In_DBx__DM2) +/* Input Buffer Disable Override */ +#define SCSI_In_DBx_INP_DIS (* (reg8 *) SCSI_In_DBx__INP_DIS) +/* LCD Common or Segment Drive */ +#define SCSI_In_DBx_LCD_COM_SEG (* (reg8 *) SCSI_In_DBx__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SCSI_In_DBx_LCD_EN (* (reg8 *) SCSI_In_DBx__LCD_EN) +/* Slew Rate Control */ +#define SCSI_In_DBx_SLW (* (reg8 *) SCSI_In_DBx__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SCSI_In_DBx_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_In_DBx__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SCSI_In_DBx_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_In_DBx__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SCSI_In_DBx_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_In_DBx__PRTDSI__OE_SEL0) +#define SCSI_In_DBx_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_In_DBx__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SCSI_In_DBx_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_In_DBx__PRTDSI__OUT_SEL0) +#define SCSI_In_DBx_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_In_DBx__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SCSI_In_DBx_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_In_DBx__PRTDSI__SYNC_OUT) + + +#if defined(SCSI_In_DBx__INTSTAT) /* Interrupt Registers */ + + #define SCSI_In_DBx_INTSTAT (* (reg8 *) SCSI_In_DBx__INTSTAT) + #define SCSI_In_DBx_SNAP (* (reg8 *) SCSI_In_DBx__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SCSI_In_DBx_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h new file mode 100644 index 0000000..6feb8e8 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h @@ -0,0 +1,48 @@ +/******************************************************************************* +* File Name: SCSI_In_DBx.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_In_DBx_ALIASES_H) /* Pins SCSI_In_DBx_ALIASES_H */ +#define CY_PINS_SCSI_In_DBx_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_In_DBx_0 SCSI_In_DBx__0__PC +#define SCSI_In_DBx_1 SCSI_In_DBx__1__PC +#define SCSI_In_DBx_2 SCSI_In_DBx__2__PC +#define SCSI_In_DBx_3 SCSI_In_DBx__3__PC +#define SCSI_In_DBx_4 SCSI_In_DBx__4__PC +#define SCSI_In_DBx_5 SCSI_In_DBx__5__PC +#define SCSI_In_DBx_6 SCSI_In_DBx__6__PC +#define SCSI_In_DBx_7 SCSI_In_DBx__7__PC + +#define SCSI_In_DBx_SCSI_Out_DB0 SCSI_In_DBx__SCSI_Out_DB0__PC +#define SCSI_In_DBx_SCSI_Out_DB1 SCSI_In_DBx__SCSI_Out_DB1__PC +#define SCSI_In_DBx_SCSI_Out_DB2 SCSI_In_DBx__SCSI_Out_DB2__PC +#define SCSI_In_DBx_SCSI_Out_DB3 SCSI_In_DBx__SCSI_Out_DB3__PC +#define SCSI_In_DBx_SCSI_Out_DB4 SCSI_In_DBx__SCSI_Out_DB4__PC +#define SCSI_In_DBx_SCSI_Out_DB5 SCSI_In_DBx__SCSI_Out_DB5__PC +#define SCSI_In_DBx_SCSI_Out_DB6 SCSI_In_DBx__SCSI_Out_DB6__PC +#define SCSI_In_DBx_SCSI_Out_DB7 SCSI_In_DBx__SCSI_Out_DB7__PC + +#endif /* End Pins SCSI_In_DBx_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h new file mode 100644 index 0000000..4243a84 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* File Name: SCSI_In.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_In_ALIASES_H) /* Pins SCSI_In_ALIASES_H */ +#define CY_PINS_SCSI_In_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_In_0 SCSI_In__0__PC +#define SCSI_In_1 SCSI_In__1__PC +#define SCSI_In_2 SCSI_In__2__PC +#define SCSI_In_3 SCSI_In__3__PC +#define SCSI_In_4 SCSI_In__4__PC +#define SCSI_In_5 SCSI_In__5__PC +#define SCSI_In_6 SCSI_In__6__PC +#define SCSI_In_7 SCSI_In__7__PC +#define SCSI_In_8 SCSI_In__8__PC +#define SCSI_In_9 SCSI_In__9__PC + +#define SCSI_In_DBP SCSI_In__DBP__PC +#define SCSI_In_ATN SCSI_In__ATN__PC +#define SCSI_In_BSY SCSI_In__BSY__PC +#define SCSI_In_ACK SCSI_In__ACK__PC +#define SCSI_In_RST SCSI_In__RST__PC +#define SCSI_In_MSG SCSI_In__MSG__PC +#define SCSI_In_SEL SCSI_In__SEL__PC +#define SCSI_In_CD SCSI_In__CD__PC +#define SCSI_In_REQ SCSI_In__REQ__PC +#define SCSI_In_IO SCSI_In__IO__PC + +#endif /* End Pins SCSI_In_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx.c new file mode 100644 index 0000000..e673f31 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx.c @@ -0,0 +1,144 @@ +/******************************************************************************* +* File Name: SCSI_Out_DBx.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SCSI_Out_DBx.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SCSI_Out_DBx__PORT == 15 && ((SCSI_Out_DBx__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SCSI_Out_DBx_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_DBx_Write(uint8 value) +{ + uint8 staticBits = (SCSI_Out_DBx_DR & (uint8)(~SCSI_Out_DBx_MASK)); + SCSI_Out_DBx_DR = staticBits | ((uint8)(value << SCSI_Out_DBx_SHIFT) & SCSI_Out_DBx_MASK); +} + + +/******************************************************************************* +* Function Name: SCSI_Out_DBx_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_DBx_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SCSI_Out_DBx_0, mode); + CyPins_SetPinDriveMode(SCSI_Out_DBx_1, mode); + CyPins_SetPinDriveMode(SCSI_Out_DBx_2, mode); + CyPins_SetPinDriveMode(SCSI_Out_DBx_3, mode); + CyPins_SetPinDriveMode(SCSI_Out_DBx_4, mode); + CyPins_SetPinDriveMode(SCSI_Out_DBx_5, mode); + CyPins_SetPinDriveMode(SCSI_Out_DBx_6, mode); + CyPins_SetPinDriveMode(SCSI_Out_DBx_7, mode); +} + + +/******************************************************************************* +* Function Name: SCSI_Out_DBx_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SCSI_Out_DBx_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SCSI_Out_DBx_Read(void) +{ + return (SCSI_Out_DBx_PS & SCSI_Out_DBx_MASK) >> SCSI_Out_DBx_SHIFT; +} + + +/******************************************************************************* +* Function Name: SCSI_Out_DBx_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SCSI_Out_DBx_ReadDataReg(void) +{ + return (SCSI_Out_DBx_DR & SCSI_Out_DBx_MASK) >> SCSI_Out_DBx_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SCSI_Out_DBx_INTSTAT) + + /******************************************************************************* + * Function Name: SCSI_Out_DBx_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SCSI_Out_DBx_ClearInterrupt(void) + { + return (SCSI_Out_DBx_INTSTAT & SCSI_Out_DBx_MASK) >> SCSI_Out_DBx_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx.h new file mode 100644 index 0000000..41bd7a9 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SCSI_Out_DBx.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Out_DBx_H) /* Pins SCSI_Out_DBx_H */ +#define CY_PINS_SCSI_Out_DBx_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SCSI_Out_DBx_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SCSI_Out_DBx__PORT == 15 && ((SCSI_Out_DBx__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_Out_DBx_Write(uint8 value) ; +void SCSI_Out_DBx_SetDriveMode(uint8 mode) ; +uint8 SCSI_Out_DBx_ReadDataReg(void) ; +uint8 SCSI_Out_DBx_Read(void) ; +uint8 SCSI_Out_DBx_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SCSI_Out_DBx_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SCSI_Out_DBx_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SCSI_Out_DBx_DM_RES_UP PIN_DM_RES_UP +#define SCSI_Out_DBx_DM_RES_DWN PIN_DM_RES_DWN +#define SCSI_Out_DBx_DM_OD_LO PIN_DM_OD_LO +#define SCSI_Out_DBx_DM_OD_HI PIN_DM_OD_HI +#define SCSI_Out_DBx_DM_STRONG PIN_DM_STRONG +#define SCSI_Out_DBx_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SCSI_Out_DBx_MASK SCSI_Out_DBx__MASK +#define SCSI_Out_DBx_SHIFT SCSI_Out_DBx__SHIFT +#define SCSI_Out_DBx_WIDTH 8u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SCSI_Out_DBx_PS (* (reg8 *) SCSI_Out_DBx__PS) +/* Data Register */ +#define SCSI_Out_DBx_DR (* (reg8 *) SCSI_Out_DBx__DR) +/* Port Number */ +#define SCSI_Out_DBx_PRT_NUM (* (reg8 *) SCSI_Out_DBx__PRT) +/* Connect to Analog Globals */ +#define SCSI_Out_DBx_AG (* (reg8 *) SCSI_Out_DBx__AG) +/* Analog MUX bux enable */ +#define SCSI_Out_DBx_AMUX (* (reg8 *) SCSI_Out_DBx__AMUX) +/* Bidirectional Enable */ +#define SCSI_Out_DBx_BIE (* (reg8 *) SCSI_Out_DBx__BIE) +/* Bit-mask for Aliased Register Access */ +#define SCSI_Out_DBx_BIT_MASK (* (reg8 *) SCSI_Out_DBx__BIT_MASK) +/* Bypass Enable */ +#define SCSI_Out_DBx_BYP (* (reg8 *) SCSI_Out_DBx__BYP) +/* Port wide control signals */ +#define SCSI_Out_DBx_CTL (* (reg8 *) SCSI_Out_DBx__CTL) +/* Drive Modes */ +#define SCSI_Out_DBx_DM0 (* (reg8 *) SCSI_Out_DBx__DM0) +#define SCSI_Out_DBx_DM1 (* (reg8 *) SCSI_Out_DBx__DM1) +#define SCSI_Out_DBx_DM2 (* (reg8 *) SCSI_Out_DBx__DM2) +/* Input Buffer Disable Override */ +#define SCSI_Out_DBx_INP_DIS (* (reg8 *) SCSI_Out_DBx__INP_DIS) +/* LCD Common or Segment Drive */ +#define SCSI_Out_DBx_LCD_COM_SEG (* (reg8 *) SCSI_Out_DBx__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SCSI_Out_DBx_LCD_EN (* (reg8 *) SCSI_Out_DBx__LCD_EN) +/* Slew Rate Control */ +#define SCSI_Out_DBx_SLW (* (reg8 *) SCSI_Out_DBx__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SCSI_Out_DBx_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_Out_DBx__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SCSI_Out_DBx_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_Out_DBx__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SCSI_Out_DBx_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OE_SEL0) +#define SCSI_Out_DBx_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SCSI_Out_DBx_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OUT_SEL0) +#define SCSI_Out_DBx_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SCSI_Out_DBx_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_Out_DBx__PRTDSI__SYNC_OUT) + + +#if defined(SCSI_Out_DBx__INTSTAT) /* Interrupt Registers */ + + #define SCSI_Out_DBx_INTSTAT (* (reg8 *) SCSI_Out_DBx__INTSTAT) + #define SCSI_Out_DBx_SNAP (* (reg8 *) SCSI_Out_DBx__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SCSI_Out_DBx_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h new file mode 100644 index 0000000..26cf8de --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h @@ -0,0 +1,48 @@ +/******************************************************************************* +* File Name: SCSI_Out_DBx.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Out_DBx_ALIASES_H) /* Pins SCSI_Out_DBx_ALIASES_H */ +#define CY_PINS_SCSI_Out_DBx_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_Out_DBx_0 SCSI_Out_DBx__0__PC +#define SCSI_Out_DBx_1 SCSI_Out_DBx__1__PC +#define SCSI_Out_DBx_2 SCSI_Out_DBx__2__PC +#define SCSI_Out_DBx_3 SCSI_Out_DBx__3__PC +#define SCSI_Out_DBx_4 SCSI_Out_DBx__4__PC +#define SCSI_Out_DBx_5 SCSI_Out_DBx__5__PC +#define SCSI_Out_DBx_6 SCSI_Out_DBx__6__PC +#define SCSI_Out_DBx_7 SCSI_Out_DBx__7__PC + +#define SCSI_Out_DBx_SCSI_Out_DB0 SCSI_Out_DBx__SCSI_Out_DB0__PC +#define SCSI_Out_DBx_SCSI_Out_DB1 SCSI_Out_DBx__SCSI_Out_DB1__PC +#define SCSI_Out_DBx_SCSI_Out_DB2 SCSI_Out_DBx__SCSI_Out_DB2__PC +#define SCSI_Out_DBx_SCSI_Out_DB3 SCSI_Out_DBx__SCSI_Out_DB3__PC +#define SCSI_Out_DBx_SCSI_Out_DB4 SCSI_Out_DBx__SCSI_Out_DB4__PC +#define SCSI_Out_DBx_SCSI_Out_DB5 SCSI_Out_DBx__SCSI_Out_DB5__PC +#define SCSI_Out_DBx_SCSI_Out_DB6 SCSI_Out_DBx__SCSI_Out_DB6__PC +#define SCSI_Out_DBx_SCSI_Out_DB7 SCSI_Out_DBx__SCSI_Out_DB7__PC + +#endif /* End Pins SCSI_Out_DBx_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h new file mode 100644 index 0000000..cc35e5b --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* File Name: SCSI_Out.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Out_ALIASES_H) /* Pins SCSI_Out_ALIASES_H */ +#define CY_PINS_SCSI_Out_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_Out_0 SCSI_Out__0__PC +#define SCSI_Out_1 SCSI_Out__1__PC +#define SCSI_Out_2 SCSI_Out__2__PC +#define SCSI_Out_3 SCSI_Out__3__PC +#define SCSI_Out_4 SCSI_Out__4__PC +#define SCSI_Out_5 SCSI_Out__5__PC +#define SCSI_Out_6 SCSI_Out__6__PC +#define SCSI_Out_7 SCSI_Out__7__PC +#define SCSI_Out_8 SCSI_Out__8__PC +#define SCSI_Out_9 SCSI_Out__9__PC + +#define SCSI_Out_DBP SCSI_Out__DBP__PC +#define SCSI_Out_ATN SCSI_Out__ATN__PC +#define SCSI_Out_BSY SCSI_Out__BSY__PC +#define SCSI_Out_ACK SCSI_Out__ACK__PC +#define SCSI_Out_RST SCSI_Out__RST__PC +#define SCSI_Out_MSG SCSI_Out__MSG__PC +#define SCSI_Out_SEL SCSI_Out__SEL__PC +#define SCSI_Out_CD SCSI_Out__CD__PC +#define SCSI_Out_REQ SCSI_Out__REQ__PC +#define SCSI_Out_IO SCSI_Out__IO__PC + +#endif /* End Pins SCSI_Out_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.c new file mode 100644 index 0000000..c1d6394 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.c @@ -0,0 +1,1155 @@ +/******************************************************************************* +* File Name: SD.c +* Version 2.40 +* +* Description: +* This file provides all API functionality of the SPI Master component. +* +* Note: +* None. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SD_PVT.h" + +#if(SD_TX_SOFTWARE_BUF_ENABLED) + volatile uint8 SD_txBuffer[SD_TX_BUFFER_SIZE] = {0u}; + volatile uint8 SD_txBufferFull; + volatile uint8 SD_txBufferRead; + volatile uint8 SD_txBufferWrite; +#endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */ + +#if(SD_RX_SOFTWARE_BUF_ENABLED) + volatile uint8 SD_rxBuffer[SD_RX_BUFFER_SIZE] = {0u}; + volatile uint8 SD_rxBufferFull; + volatile uint8 SD_rxBufferRead; + volatile uint8 SD_rxBufferWrite; +#endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */ + +uint8 SD_initVar = 0u; + +volatile uint8 SD_swStatusTx; +volatile uint8 SD_swStatusRx; + + +/******************************************************************************* +* Function Name: SD_Init +******************************************************************************** +* +* Summary: +* Inits/Restores default SPIM configuration provided with customizer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* When this function is called it initializes all of the necessary parameters +* for execution. i.e. setting the initial interrupt mask, configuring the +* interrupt service routine, configuring the bit-counter parameters and +* clearing the FIFO and Status Register. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SD_Init(void) +{ + /* Initialize the Bit counter */ + SD_COUNTER_PERIOD_REG = SD_BITCTR_INIT; + + /* Init TX ISR */ + #if(0u != SD_INTERNAL_TX_INT_ENABLED) + CyIntDisable (SD_TX_ISR_NUMBER); + CyIntSetPriority (SD_TX_ISR_NUMBER, SD_TX_ISR_PRIORITY); + (void) CyIntSetVector(SD_TX_ISR_NUMBER, &SD_TX_ISR); + #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */ + + /* Init RX ISR */ + #if(0u != SD_INTERNAL_RX_INT_ENABLED) + CyIntDisable (SD_RX_ISR_NUMBER); + CyIntSetPriority (SD_RX_ISR_NUMBER, SD_RX_ISR_PRIORITY); + (void) CyIntSetVector(SD_RX_ISR_NUMBER, &SD_RX_ISR); + #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */ + + /* Clear any stray data from the RX and TX FIFO */ + SD_ClearFIFO(); + + #if(SD_RX_SOFTWARE_BUF_ENABLED) + SD_rxBufferFull = 0u; + SD_rxBufferRead = 0u; + SD_rxBufferWrite = 0u; + #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */ + + #if(SD_TX_SOFTWARE_BUF_ENABLED) + SD_txBufferFull = 0u; + SD_txBufferRead = 0u; + SD_txBufferWrite = 0u; + #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */ + + (void) SD_ReadTxStatus(); /* Clear Tx status and swStatusTx */ + (void) SD_ReadRxStatus(); /* Clear Rx status and swStatusRx */ + + /* Configure TX and RX interrupt mask */ + SD_TX_STATUS_MASK_REG = SD_TX_INIT_INTERRUPTS_MASK; + SD_RX_STATUS_MASK_REG = SD_RX_INIT_INTERRUPTS_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Enable +******************************************************************************** +* +* Summary: +* Enable SPIM component. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SD_Enable(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + SD_COUNTER_CONTROL_REG |= SD_CNTR_ENABLE; + SD_TX_STATUS_ACTL_REG |= SD_INT_ENABLE; + SD_RX_STATUS_ACTL_REG |= SD_INT_ENABLE; + CyExitCriticalSection(enableInterrupts); + + #if(0u != SD_INTERNAL_CLOCK) + SD_IntClock_Enable(); + #endif /* (0u != SD_INTERNAL_CLOCK) */ + + SD_EnableTxInt(); + SD_EnableRxInt(); +} + + +/******************************************************************************* +* Function Name: SD_Start +******************************************************************************** +* +* Summary: +* Initialize and Enable the SPI Master component. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SD_initVar - used to check initial configuration, modified on +* first function call. +* +* Theory: +* Enable the clock input to enable operation. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SD_Start(void) +{ + if(0u == SD_initVar) + { + SD_Init(); + SD_initVar = 1u; + } + + SD_Enable(); +} + + +/******************************************************************************* +* Function Name: SD_Stop +******************************************************************************** +* +* Summary: +* Disable the SPI Master component. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the clock input to enable operation. +* +*******************************************************************************/ +void SD_Stop(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + SD_TX_STATUS_ACTL_REG &= ((uint8) ~SD_INT_ENABLE); + SD_RX_STATUS_ACTL_REG &= ((uint8) ~SD_INT_ENABLE); + CyExitCriticalSection(enableInterrupts); + + #if(0u != SD_INTERNAL_CLOCK) + SD_IntClock_Disable(); + #endif /* (0u != SD_INTERNAL_CLOCK) */ + + SD_DisableTxInt(); + SD_DisableRxInt(); +} + + +/******************************************************************************* +* Function Name: SD_EnableTxInt +******************************************************************************** +* +* Summary: +* Enable internal Tx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal Tx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SD_EnableTxInt(void) +{ + #if(0u != SD_INTERNAL_TX_INT_ENABLED) + CyIntEnable(SD_TX_ISR_NUMBER); + #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SD_EnableRxInt +******************************************************************************** +* +* Summary: +* Enable internal Rx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal Rx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SD_EnableRxInt(void) +{ + #if(0u != SD_INTERNAL_RX_INT_ENABLED) + CyIntEnable(SD_RX_ISR_NUMBER); + #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SD_DisableTxInt +******************************************************************************** +* +* Summary: +* Disable internal Tx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal Tx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SD_DisableTxInt(void) +{ + #if(0u != SD_INTERNAL_TX_INT_ENABLED) + CyIntDisable(SD_TX_ISR_NUMBER); + #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SD_DisableRxInt +******************************************************************************** +* +* Summary: +* Disable internal Rx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal Rx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SD_DisableRxInt(void) +{ + #if(0u != SD_INTERNAL_RX_INT_ENABLED) + CyIntDisable(SD_RX_ISR_NUMBER); + #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SD_SetTxInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void SD_SetTxInterruptMode(uint8 intSrc) +{ + SD_TX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: SD_SetRxInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void SD_SetRxInterruptMode(uint8 intSrc) +{ + SD_RX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: SD_ReadTxStatus +******************************************************************************** +* +* Summary: +* Read the Tx status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the Tx status register. +* +* Global variables: +* SD_swStatusTx - used to store in software status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the Tx status register for error +* detection and flow control. +* +* Side Effects: +* Clear Tx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SD_ReadTxStatus(void) +{ + uint8 tmpStatus; + + #if(SD_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + SD_DisableTxInt(); + + tmpStatus = SD_GET_STATUS_TX(SD_swStatusTx); + SD_swStatusTx = 0u; + + SD_EnableTxInt(); + + #else + + tmpStatus = SD_TX_STATUS_REG; + + #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: SD_ReadRxStatus +******************************************************************************** +* +* Summary: +* Read the Rx status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the Rx status register. +* +* Global variables: +* SD_swStatusRx - used to store in software Rx status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the Rx status register for error +* detection and flow control. +* +* Side Effects: +* Clear Rx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SD_ReadRxStatus(void) +{ + uint8 tmpStatus; + + #if(SD_RX_SOFTWARE_BUF_ENABLED) + /* Disable RX interrupt to protect global veriables */ + SD_DisableRxInt(); + + tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx); + SD_swStatusRx = 0u; + + SD_EnableRxInt(); + + #else + + tmpStatus = SD_RX_STATUS_REG; + + #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: SD_WriteTxData +******************************************************************************** +* +* Summary: +* Write a byte of data to be sent across the SPI. +* +* Parameters: +* txDataByte: The data value to send across the SPI. +* +* Return: +* None. +* +* Global variables: +* SD_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer, modified every function +* call if TX Software Buffer is used. +* SD_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer. +* SD_txBuffer[SD_TX_BUFFER_SIZE] - used to store +* data to sending, modified every function call if TX Software Buffer is used. +* +* Theory: +* Allows the user to transmit any byte of data in a single transfer. +* +* Side Effects: +* If this function is called again before the previous byte is finished then +* the next byte will be appended to the transfer with no time between +* the byte transfers. Clear Tx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SD_WriteTxData(uint8 txData) +{ + #if(SD_TX_SOFTWARE_BUF_ENABLED) + + uint8 tempStatus; + uint8 tmpTxBufferRead; + + /* Block if TX buffer is FULL: don't overwrite */ + do + { + tmpTxBufferRead = SD_txBufferRead; + if(0u == tmpTxBufferRead) + { + tmpTxBufferRead = (SD_TX_BUFFER_SIZE - 1u); + } + else + { + tmpTxBufferRead--; + } + + }while(tmpTxBufferRead == SD_txBufferWrite); + + /* Disable TX interrupt to protect global veriables */ + SD_DisableTxInt(); + + tempStatus = SD_GET_STATUS_TX(SD_swStatusTx); + SD_swStatusTx = tempStatus; + + + if((SD_txBufferRead == SD_txBufferWrite) && + (0u != (SD_swStatusTx & SD_STS_TX_FIFO_NOT_FULL))) + { + /* Add directly to the TX FIFO */ + CY_SET_REG8(SD_TXDATA_PTR, txData); + } + else + { + /* Add to the TX software buffer */ + SD_txBufferWrite++; + if(SD_txBufferWrite >= SD_TX_BUFFER_SIZE) + { + SD_txBufferWrite = 0u; + } + + if(SD_txBufferWrite == SD_txBufferRead) + { + SD_txBufferRead++; + if(SD_txBufferRead >= SD_TX_BUFFER_SIZE) + { + SD_txBufferRead = 0u; + } + SD_txBufferFull = 1u; + } + + SD_txBuffer[SD_txBufferWrite] = txData; + + SD_TX_STATUS_MASK_REG |= SD_STS_TX_FIFO_NOT_FULL; + } + + SD_EnableTxInt(); + + #else + + while(0u == (SD_TX_STATUS_REG & SD_STS_TX_FIFO_NOT_FULL)) + { + ; /* Wait for room in FIFO */ + } + + /* Put byte in TX FIFO */ + CY_SET_REG8(SD_TXDATA_PTR, txData); + + #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SD_ReadRxData +******************************************************************************** +* +* Summary: +* Read the next byte of data received across the SPI. +* +* Parameters: +* None. +* +* Return: +* The next byte of data read from the FIFO. +* +* Global variables: +* SD_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer. +* SD_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified every function +* call if RX Software Buffer is used. +* SD_rxBuffer[SD_RX_BUFFER_SIZE] - used to store +* received data. +* +* Theory: +* Allows the user to read a byte of data received. +* +* Side Effects: +* Will return invalid data if the FIFO is empty. The user should Call +* GetRxBufferSize() and if it returns a non-zero value then it is safe to call +* ReadByte() function. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SD_ReadRxData(void) +{ + uint8 rxData; + + #if(SD_RX_SOFTWARE_BUF_ENABLED) + + /* Disable RX interrupt to protect global veriables */ + SD_DisableRxInt(); + + if(SD_rxBufferRead != SD_rxBufferWrite) + { + if(0u == SD_rxBufferFull) + { + SD_rxBufferRead++; + if(SD_rxBufferRead >= SD_RX_BUFFER_SIZE) + { + SD_rxBufferRead = 0u; + } + } + else + { + SD_rxBufferFull = 0u; + } + } + + rxData = SD_rxBuffer[SD_rxBufferRead]; + + SD_EnableRxInt(); + + #else + + rxData = CY_GET_REG8(SD_RXDATA_PTR); + + #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */ + + return(rxData); +} + + +/******************************************************************************* +* Function Name: SD_GetRxBufferSize +******************************************************************************** +* +* Summary: +* Returns the number of bytes/words of data currently held in the RX buffer. +* If RX Software Buffer not used then function return 0 if FIFO empty or 1 if +* FIFO not empty. In another case function return size of RX Software Buffer. +* +* Parameters: +* None. +* +* Return: +* Integer count of the number of bytes/words in the RX buffer. +* +* Global variables: +* SD_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer. +* SD_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +uint8 SD_GetRxBufferSize(void) +{ + uint8 size; + + #if(SD_RX_SOFTWARE_BUF_ENABLED) + + /* Disable RX interrupt to protect global veriables */ + SD_DisableRxInt(); + + if(SD_rxBufferRead == SD_rxBufferWrite) + { + size = 0u; + } + else if(SD_rxBufferRead < SD_rxBufferWrite) + { + size = (SD_rxBufferWrite - SD_rxBufferRead); + } + else + { + size = (SD_RX_BUFFER_SIZE - SD_rxBufferRead) + SD_rxBufferWrite; + } + + SD_EnableRxInt(); + + #else + + /* We can only know if there is data in the RX FIFO */ + size = (0u != (SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY)) ? 1u : 0u; + + #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */ + + return(size); +} + + +/******************************************************************************* +* Function Name: SD_GetTxBufferSize +******************************************************************************** +* +* Summary: +* Returns the number of bytes/words of data currently held in the TX buffer. +* If TX Software Buffer not used then function return 0 - if FIFO empty, 1 - if +* FIFO not full, 4 - if FIFO full. In another case function return size of TX +* Software Buffer. +* +* Parameters: +* None. +* +* Return: +* Integer count of the number of bytes/words in the TX buffer. +* +* Global variables: +* SD_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer. +* SD_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +uint8 SD_GetTxBufferSize(void) +{ + uint8 size; + + #if(SD_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + SD_DisableTxInt(); + + if(SD_txBufferRead == SD_txBufferWrite) + { + size = 0u; + } + else if(SD_txBufferRead < SD_txBufferWrite) + { + size = (SD_txBufferWrite - SD_txBufferRead); + } + else + { + size = (SD_TX_BUFFER_SIZE - SD_txBufferRead) + SD_txBufferWrite; + } + + SD_EnableTxInt(); + + #else + + size = SD_TX_STATUS_REG; + + if(0u != (size & SD_STS_TX_FIFO_EMPTY)) + { + size = 0u; + } + else if(0u != (size & SD_STS_TX_FIFO_NOT_FULL)) + { + size = 1u; + } + else + { + size = SD_FIFO_SIZE; + } + + #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */ + + return(size); +} + + +/******************************************************************************* +* Function Name: SD_ClearRxBuffer +******************************************************************************** +* +* Summary: +* Clear the RX RAM buffer by setting the read and write pointers both to zero. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SD_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer, modified every function +* call - resets to zero. +* SD_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified every function call - +* resets to zero. +* +* Theory: +* Setting the pointers to zero makes the system believe there is no data to +* read and writing will resume at address 0 overwriting any data that may have +* remained in the RAM. +* +* Side Effects: +* Any received data not read from the RAM buffer will be lost when overwritten. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SD_ClearRxBuffer(void) +{ + /* Clear Hardware RX FIFO */ + while(0u !=(SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY)) + { + (void) CY_GET_REG8(SD_RXDATA_PTR); + } + + #if(SD_RX_SOFTWARE_BUF_ENABLED) + /* Disable RX interrupt to protect global veriables */ + SD_DisableRxInt(); + + SD_rxBufferFull = 0u; + SD_rxBufferRead = 0u; + SD_rxBufferWrite = 0u; + + SD_EnableRxInt(); + #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SD_ClearTxBuffer +******************************************************************************** +* +* Summary: +* Clear the TX RAM buffer by setting the read and write pointers both to zero. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SD_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer, modified every function +* call - resets to zero. +* SD_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer, modified every function call - +* resets to zero. +* +* Theory: +* Setting the pointers to zero makes the system believe there is no data to +* read and writing will resume at address 0 overwriting any data that may have +* remained in the RAM. +* +* Side Effects: +* Any data not yet transmitted from the RAM buffer will be lost when +* overwritten. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SD_ClearTxBuffer(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + /* Clear TX FIFO */ + SD_AUX_CONTROL_DP0_REG |= ((uint8) SD_TX_FIFO_CLR); + SD_AUX_CONTROL_DP0_REG &= ((uint8) ~SD_TX_FIFO_CLR); + + #if(SD_USE_SECOND_DATAPATH) + /* Clear TX FIFO for 2nd Datapath */ + SD_AUX_CONTROL_DP1_REG |= ((uint8) SD_TX_FIFO_CLR); + SD_AUX_CONTROL_DP1_REG &= ((uint8) ~SD_TX_FIFO_CLR); + #endif /* (SD_USE_SECOND_DATAPATH) */ + CyExitCriticalSection(enableInterrupts); + + #if(SD_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + SD_DisableTxInt(); + + SD_txBufferFull = 0u; + SD_txBufferRead = 0u; + SD_txBufferWrite = 0u; + + /* Buffer is EMPTY: disable TX FIFO NOT FULL interrupt */ + SD_TX_STATUS_MASK_REG &= ((uint8) ~SD_STS_TX_FIFO_NOT_FULL); + + SD_EnableTxInt(); + #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */ +} + + +#if(0u != SD_BIDIRECTIONAL_MODE) + /******************************************************************************* + * Function Name: SD_TxEnable + ******************************************************************************** + * + * Summary: + * If the SPI master is configured to use a single bi-directional pin then this + * will set the bi-directional pin to transmit. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + void SD_TxEnable(void) + { + SD_CONTROL_REG |= SD_CTRL_TX_SIGNAL_EN; + } + + + /******************************************************************************* + * Function Name: SD_TxDisable + ******************************************************************************** + * + * Summary: + * If the SPI master is configured to use a single bi-directional pin then this + * will set the bi-directional pin to receive. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + void SD_TxDisable(void) + { + SD_CONTROL_REG &= ((uint8) ~SD_CTRL_TX_SIGNAL_EN); + } + +#endif /* (0u != SD_BIDIRECTIONAL_MODE) */ + + +/******************************************************************************* +* Function Name: SD_PutArray +******************************************************************************** +* +* Summary: +* Write available data from ROM/RAM to the TX buffer while space is available +* in the TX buffer. Keep trying until all data is passed to the TX buffer. +* +* Parameters: +* *buffer: Pointer to the location in RAM containing the data to send +* byteCount: The number of bytes to move to the transmit buffer. +* +* Return: +* None. +* +* Side Effects: +* Will stay in this routine until all data has been sent. May get locked in +* this loop if data is not being initiated by the master if there is not +* enough room in the TX FIFO. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SD_PutArray(const uint8 buffer[], uint8 byteCount) + +{ + uint8 bufIndex; + + bufIndex = 0u; + + while(byteCount > 0u) + { + SD_WriteTxData(buffer[bufIndex]); + bufIndex++; + byteCount--; + } +} + + +/******************************************************************************* +* Function Name: SD_ClearFIFO +******************************************************************************** +* +* Summary: +* Clear the RX and TX FIFO's of all data for a fresh start. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +void SD_ClearFIFO(void) +{ + uint8 enableInterrupts; + + /* Clear Hardware RX FIFO */ + while(0u !=(SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY)) + { + (void) CY_GET_REG8(SD_RXDATA_PTR); + } + + enableInterrupts = CyEnterCriticalSection(); + /* Clear TX FIFO */ + SD_AUX_CONTROL_DP0_REG |= ((uint8) SD_TX_FIFO_CLR); + SD_AUX_CONTROL_DP0_REG &= ((uint8) ~SD_TX_FIFO_CLR); + + #if(SD_USE_SECOND_DATAPATH) + /* Clear TX FIFO for 2nd Datapath */ + SD_AUX_CONTROL_DP1_REG |= ((uint8) SD_TX_FIFO_CLR); + SD_AUX_CONTROL_DP1_REG &= ((uint8) ~SD_TX_FIFO_CLR); + #endif /* (SD_USE_SECOND_DATAPATH) */ + CyExitCriticalSection(enableInterrupts); +} + + +/* Following functions are for version Compatibility, they are obsolete. +* Please do not use it in new projects. +*/ + + +/******************************************************************************* +* Function Name: SD_EnableInt +******************************************************************************** +* +* Summary: +* Enable internal interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SD_EnableInt(void) +{ + SD_EnableRxInt(); + SD_EnableTxInt(); +} + + +/******************************************************************************* +* Function Name: SD_DisableInt +******************************************************************************** +* +* Summary: +* Disable internal interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SD_DisableInt(void) +{ + SD_DisableTxInt(); + SD_DisableRxInt(); +} + + +/******************************************************************************* +* Function Name: SD_SetInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void SD_SetInterruptMode(uint8 intSrc) +{ + SD_TX_STATUS_MASK_REG = (intSrc & ((uint8) ~SD_STS_SPI_IDLE)); + SD_RX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: SD_ReadStatus +******************************************************************************** +* +* Summary: +* Read the status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the status register. +* +* Global variables: +* SD_swStatus - used to store in software status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the status register for error detection +* and flow control. +* +* Side Effects: +* Clear status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SD_ReadStatus(void) +{ + uint8 tmpStatus; + + #if(SD_TX_SOFTWARE_BUF_ENABLED || SD_RX_SOFTWARE_BUF_ENABLED) + + SD_DisableInt(); + + tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx); + tmpStatus |= SD_GET_STATUS_TX(SD_swStatusTx); + tmpStatus &= ((uint8) ~SD_STS_SPI_IDLE); + + SD_swStatusTx = 0u; + SD_swStatusRx = 0u; + + SD_EnableInt(); + + #else + + tmpStatus = SD_RX_STATUS_REG; + tmpStatus |= SD_TX_STATUS_REG; + tmpStatus &= ((uint8) ~SD_STS_SPI_IDLE); + + #endif /* (SD_TX_SOFTWARE_BUF_ENABLED || SD_RX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.h new file mode 100644 index 0000000..0f99abf --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.h @@ -0,0 +1,389 @@ +/******************************************************************************* +* File Name: SD.h +* Version 2.40 +* +* Description: +* Contains the function prototypes, constants and register definition +* of the SPI Master Component. +* +* Note: +* None +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SPIM_SD_H) +#define CY_SPIM_SD_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "CyLib.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component SPI_Master_v2_40 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +#define SD_INTERNAL_CLOCK (0u) + +#if(0u != SD_INTERNAL_CLOCK) + #include "SD_IntClock.h" +#endif /* (0u != SD_INTERNAL_CLOCK) */ + +#define SD_MODE (1u) +#define SD_DATA_WIDTH (8u) +#define SD_MODE_USE_ZERO (1u) +#define SD_BIDIRECTIONAL_MODE (0u) + +/* Internal interrupt handling */ +#define SD_TX_BUFFER_SIZE (4u) +#define SD_RX_BUFFER_SIZE (4u) +#define SD_INTERNAL_TX_INT_ENABLED (0u) +#define SD_INTERNAL_RX_INT_ENABLED (0u) + +#define SD_SINGLE_REG_SIZE (8u) +#define SD_USE_SECOND_DATAPATH (SD_DATA_WIDTH > SD_SINGLE_REG_SIZE) + +#define SD_FIFO_SIZE (4u) +#define SD_TX_SOFTWARE_BUF_ENABLED ((0u != SD_INTERNAL_TX_INT_ENABLED) && \ + (SD_TX_BUFFER_SIZE > SD_FIFO_SIZE)) + +#define SD_RX_SOFTWARE_BUF_ENABLED ((0u != SD_INTERNAL_RX_INT_ENABLED) && \ + (SD_RX_BUFFER_SIZE > SD_FIFO_SIZE)) + + +/*************************************** +* Data Struct Definition +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 enableState; + uint8 cntrPeriod; + #if(CY_UDB_V0) + uint8 saveSrTxIntMask; + uint8 saveSrRxIntMask; + #endif /* (CY_UDB_V0) */ + +} SD_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_Init(void) ; +void SD_Enable(void) ; +void SD_Start(void) ; +void SD_Stop(void) ; + +void SD_EnableTxInt(void) ; +void SD_EnableRxInt(void) ; +void SD_DisableTxInt(void) ; +void SD_DisableRxInt(void) ; + +void SD_Sleep(void) ; +void SD_Wakeup(void) ; +void SD_SaveConfig(void) ; +void SD_RestoreConfig(void) ; + +void SD_SetTxInterruptMode(uint8 intSrc) ; +void SD_SetRxInterruptMode(uint8 intSrc) ; +uint8 SD_ReadTxStatus(void) ; +uint8 SD_ReadRxStatus(void) ; +void SD_WriteTxData(uint8 txData) \ + ; +uint8 SD_ReadRxData(void) \ + ; +uint8 SD_GetRxBufferSize(void) ; +uint8 SD_GetTxBufferSize(void) ; +void SD_ClearRxBuffer(void) ; +void SD_ClearTxBuffer(void) ; +void SD_ClearFIFO(void) ; +void SD_PutArray(const uint8 buffer[], uint8 byteCount) \ + ; + +#if(0u != SD_BIDIRECTIONAL_MODE) + void SD_TxEnable(void) ; + void SD_TxDisable(void) ; +#endif /* (0u != SD_BIDIRECTIONAL_MODE) */ + +CY_ISR_PROTO(SD_TX_ISR); +CY_ISR_PROTO(SD_RX_ISR); + + +/********************************** +* Variable with external linkage +**********************************/ + +extern uint8 SD_initVar; + + +/*************************************** +* API Constants +***************************************/ + +#define SD_TX_ISR_NUMBER ((uint8) (SD_TxInternalInterrupt__INTC_NUMBER)) +#define SD_RX_ISR_NUMBER ((uint8) (SD_RxInternalInterrupt__INTC_NUMBER)) + +#define SD_TX_ISR_PRIORITY ((uint8) (SD_TxInternalInterrupt__INTC_PRIOR_NUM)) +#define SD_RX_ISR_PRIORITY ((uint8) (SD_RxInternalInterrupt__INTC_PRIOR_NUM)) + + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define SD_INT_ON_SPI_DONE ((uint8) (0u << SD_STS_SPI_DONE_SHIFT)) +#define SD_INT_ON_TX_EMPTY ((uint8) (0u << SD_STS_TX_FIFO_EMPTY_SHIFT)) +#define SD_INT_ON_TX_NOT_FULL ((uint8) (0u << \ + SD_STS_TX_FIFO_NOT_FULL_SHIFT)) +#define SD_INT_ON_BYTE_COMP ((uint8) (0u << SD_STS_BYTE_COMPLETE_SHIFT)) +#define SD_INT_ON_SPI_IDLE ((uint8) (0u << SD_STS_SPI_IDLE_SHIFT)) + +/* Disable TX_NOT_FULL if software buffer is used */ +#define SD_INT_ON_TX_NOT_FULL_DEF ((SD_TX_SOFTWARE_BUF_ENABLED) ? \ + (0u) : (SD_INT_ON_TX_NOT_FULL)) + +/* TX interrupt mask */ +#define SD_TX_INIT_INTERRUPTS_MASK (SD_INT_ON_SPI_DONE | \ + SD_INT_ON_TX_EMPTY | \ + SD_INT_ON_TX_NOT_FULL_DEF | \ + SD_INT_ON_BYTE_COMP | \ + SD_INT_ON_SPI_IDLE) + +#define SD_INT_ON_RX_FULL ((uint8) (0u << \ + SD_STS_RX_FIFO_FULL_SHIFT)) +#define SD_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \ + SD_STS_RX_FIFO_NOT_EMPTY_SHIFT)) +#define SD_INT_ON_RX_OVER ((uint8) (0u << \ + SD_STS_RX_FIFO_OVERRUN_SHIFT)) + +/* RX interrupt mask */ +#define SD_RX_INIT_INTERRUPTS_MASK (SD_INT_ON_RX_FULL | \ + SD_INT_ON_RX_NOT_EMPTY | \ + SD_INT_ON_RX_OVER) +/* Nubmer of bits to receive/transmit */ +#define SD_BITCTR_INIT (((uint8) (SD_DATA_WIDTH << 1u)) - 1u) + + +/*************************************** +* Registers +***************************************/ + +#if(CY_PSOC3 || CY_PSOC5) + #define SD_TXDATA_REG (* (reg8 *) \ + SD_BSPIM_sR8_Dp_u0__F0_REG) + #define SD_TXDATA_PTR ( (reg8 *) \ + SD_BSPIM_sR8_Dp_u0__F0_REG) + #define SD_RXDATA_REG (* (reg8 *) \ + SD_BSPIM_sR8_Dp_u0__F1_REG) + #define SD_RXDATA_PTR ( (reg8 *) \ + SD_BSPIM_sR8_Dp_u0__F1_REG) +#else /* PSOC4 */ + #if(SD_USE_SECOND_DATAPATH) + #define SD_TXDATA_REG (* (reg16 *) \ + SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG) + #define SD_TXDATA_PTR ( (reg16 *) \ + SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG) + #define SD_RXDATA_REG (* (reg16 *) \ + SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG) + #define SD_RXDATA_PTR ( (reg16 *) \ + SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG) + #else + #define SD_TXDATA_REG (* (reg8 *) \ + SD_BSPIM_sR8_Dp_u0__F0_REG) + #define SD_TXDATA_PTR ( (reg8 *) \ + SD_BSPIM_sR8_Dp_u0__F0_REG) + #define SD_RXDATA_REG (* (reg8 *) \ + SD_BSPIM_sR8_Dp_u0__F1_REG) + #define SD_RXDATA_PTR ( (reg8 *) \ + SD_BSPIM_sR8_Dp_u0__F1_REG) + #endif /* (SD_USE_SECOND_DATAPATH) */ +#endif /* (CY_PSOC3 || CY_PSOC5) */ + +#define SD_AUX_CONTROL_DP0_REG (* (reg8 *) \ + SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG) +#define SD_AUX_CONTROL_DP0_PTR ( (reg8 *) \ + SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG) + +#if(SD_USE_SECOND_DATAPATH) + #define SD_AUX_CONTROL_DP1_REG (* (reg8 *) \ + SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG) + #define SD_AUX_CONTROL_DP1_PTR ( (reg8 *) \ + SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG) +#endif /* (SD_USE_SECOND_DATAPATH) */ + +#define SD_COUNTER_PERIOD_REG (* (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG) +#define SD_COUNTER_PERIOD_PTR ( (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG) +#define SD_COUNTER_CONTROL_REG (* (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG) +#define SD_COUNTER_CONTROL_PTR ( (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG) + +#define SD_TX_STATUS_REG (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG) +#define SD_TX_STATUS_PTR ( (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG) +#define SD_RX_STATUS_REG (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG) +#define SD_RX_STATUS_PTR ( (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG) + +#define SD_CONTROL_REG (* (reg8 *) \ + SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG) +#define SD_CONTROL_PTR ( (reg8 *) \ + SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG) + +#define SD_TX_STATUS_MASK_REG (* (reg8 *) SD_BSPIM_TxStsReg__MASK_REG) +#define SD_TX_STATUS_MASK_PTR ( (reg8 *) SD_BSPIM_TxStsReg__MASK_REG) +#define SD_RX_STATUS_MASK_REG (* (reg8 *) SD_BSPIM_RxStsReg__MASK_REG) +#define SD_RX_STATUS_MASK_PTR ( (reg8 *) SD_BSPIM_RxStsReg__MASK_REG) + +#define SD_TX_STATUS_ACTL_REG (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG) +#define SD_TX_STATUS_ACTL_PTR ( (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG) +#define SD_RX_STATUS_ACTL_REG (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG) +#define SD_RX_STATUS_ACTL_PTR ( (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG) + +#if(SD_USE_SECOND_DATAPATH) + #define SD_AUX_CONTROLDP1 (SD_AUX_CONTROL_DP1_REG) +#endif /* (SD_USE_SECOND_DATAPATH) */ + + +/*************************************** +* Register Constants +***************************************/ + +/* Status Register Definitions */ +#define SD_STS_SPI_DONE_SHIFT (0x00u) +#define SD_STS_TX_FIFO_EMPTY_SHIFT (0x01u) +#define SD_STS_TX_FIFO_NOT_FULL_SHIFT (0x02u) +#define SD_STS_BYTE_COMPLETE_SHIFT (0x03u) +#define SD_STS_SPI_IDLE_SHIFT (0x04u) +#define SD_STS_RX_FIFO_FULL_SHIFT (0x04u) +#define SD_STS_RX_FIFO_NOT_EMPTY_SHIFT (0x05u) +#define SD_STS_RX_FIFO_OVERRUN_SHIFT (0x06u) + +#define SD_STS_SPI_DONE ((uint8) (0x01u << SD_STS_SPI_DONE_SHIFT)) +#define SD_STS_TX_FIFO_EMPTY ((uint8) (0x01u << SD_STS_TX_FIFO_EMPTY_SHIFT)) +#define SD_STS_TX_FIFO_NOT_FULL ((uint8) (0x01u << SD_STS_TX_FIFO_NOT_FULL_SHIFT)) +#define SD_STS_BYTE_COMPLETE ((uint8) (0x01u << SD_STS_BYTE_COMPLETE_SHIFT)) +#define SD_STS_SPI_IDLE ((uint8) (0x01u << SD_STS_SPI_IDLE_SHIFT)) +#define SD_STS_RX_FIFO_FULL ((uint8) (0x01u << SD_STS_RX_FIFO_FULL_SHIFT)) +#define SD_STS_RX_FIFO_NOT_EMPTY ((uint8) (0x01u << SD_STS_RX_FIFO_NOT_EMPTY_SHIFT)) +#define SD_STS_RX_FIFO_OVERRUN ((uint8) (0x01u << SD_STS_RX_FIFO_OVERRUN_SHIFT)) + +/* TX and RX masks for clear on read bits */ +#define SD_TX_STS_CLR_ON_RD_BYTES_MASK (0x09u) +#define SD_RX_STS_CLR_ON_RD_BYTES_MASK (0x40u) + +/* StatusI Register Interrupt Enable Control Bits */ +/* As defined by the Register map for the AUX Control Register */ +#define SD_INT_ENABLE (0x10u) /* Enable interrupt from statusi */ +#define SD_TX_FIFO_CLR (0x01u) /* F0 - TX FIFO */ +#define SD_RX_FIFO_CLR (0x02u) /* F1 - RX FIFO */ +#define SD_FIFO_CLR (SD_TX_FIFO_CLR | SD_RX_FIFO_CLR) + +/* Bit Counter (7-bit) Control Register Bit Definitions */ +/* As defined by the Register map for the AUX Control Register */ +#define SD_CNTR_ENABLE (0x20u) /* Enable CNT7 */ + +/* Bi-Directional mode control bit */ +#define SD_CTRL_TX_SIGNAL_EN (0x01u) + +/* Datapath Auxillary Control Register definitions */ +#define SD_AUX_CTRL_FIFO0_CLR (0x01u) +#define SD_AUX_CTRL_FIFO1_CLR (0x02u) +#define SD_AUX_CTRL_FIFO0_LVL (0x04u) +#define SD_AUX_CTRL_FIFO1_LVL (0x08u) +#define SD_STATUS_ACTL_INT_EN_MASK (0x10u) + +/* Component disabled */ +#define SD_DISABLED (0u) + + +/*************************************** +* Macros +***************************************/ + +/* Returns true if componentn enabled */ +#define SD_IS_ENABLED (0u != (SD_TX_STATUS_ACTL_REG & SD_INT_ENABLE)) + +/* Retuns TX status register */ +#define SD_GET_STATUS_TX(swTxSts) ( (uint8)(SD_TX_STATUS_REG | \ + ((swTxSts) & SD_TX_STS_CLR_ON_RD_BYTES_MASK)) ) +/* Retuns RX status register */ +#define SD_GET_STATUS_RX(swRxSts) ( (uint8)(SD_RX_STATUS_REG | \ + ((swRxSts) & SD_RX_STS_CLR_ON_RD_BYTES_MASK)) ) + + +/*************************************** +* Obsolete definitions +***************************************/ + +/* Following definitions are for version compatibility. +* They are obsolete in SPIM v2_30. +* Please do not use it in new projects +*/ + +#define SD_WriteByte SD_WriteTxData +#define SD_ReadByte SD_ReadRxData +void SD_SetInterruptMode(uint8 intSrc) ; +uint8 SD_ReadStatus(void) ; +void SD_EnableInt(void) ; +void SD_DisableInt(void) ; + +/* Obsolete register names. Not to be used in new designs */ +#define SD_TXDATA (SD_TXDATA_REG) +#define SD_RXDATA (SD_RXDATA_REG) +#define SD_AUX_CONTROLDP0 (SD_AUX_CONTROL_DP0_REG) +#define SD_TXBUFFERREAD (SD_txBufferRead) +#define SD_TXBUFFERWRITE (SD_txBufferWrite) +#define SD_RXBUFFERREAD (SD_rxBufferRead) +#define SD_RXBUFFERWRITE (SD_rxBufferWrite) + +#define SD_COUNTER_PERIOD (SD_COUNTER_PERIOD_REG) +#define SD_COUNTER_CONTROL (SD_COUNTER_CONTROL_REG) +#define SD_STATUS (SD_TX_STATUS_REG) +#define SD_CONTROL (SD_CONTROL_REG) +#define SD_STATUS_MASK (SD_TX_STATUS_MASK_REG) +#define SD_STATUS_ACTL (SD_TX_STATUS_ACTL_REG) + +#define SD_INIT_INTERRUPTS_MASK (SD_INT_ON_SPI_DONE | \ + SD_INT_ON_TX_EMPTY | \ + SD_INT_ON_TX_NOT_FULL_DEF | \ + SD_INT_ON_RX_FULL | \ + SD_INT_ON_RX_NOT_EMPTY | \ + SD_INT_ON_RX_OVER | \ + SD_INT_ON_BYTE_COMP) + +/* Following definitions are for version Compatibility. +* They are obsolete in SPIM v2_40. +* Please do not use it in new projects +*/ + +#define SD_DataWidth (SD_DATA_WIDTH) +#define SD_InternalClockUsed (SD_INTERNAL_CLOCK) +#define SD_InternalTxInterruptEnabled (SD_INTERNAL_TX_INT_ENABLED) +#define SD_InternalRxInterruptEnabled (SD_INTERNAL_RX_INT_ENABLED) +#define SD_ModeUseZero (SD_MODE_USE_ZERO) +#define SD_BidirectionalMode (SD_BIDIRECTIONAL_MODE) +#define SD_Mode (SD_MODE) +#define SD_DATAWIDHT (SD_DATA_WIDTH) +#define SD_InternalInterruptEnabled (0u) + +#define SD_TXBUFFERSIZE (SD_TX_BUFFER_SIZE) +#define SD_RXBUFFERSIZE (SD_RX_BUFFER_SIZE) + +#define SD_TXBUFFER SD_txBuffer +#define SD_RXBUFFER SD_rxBuffer + +#endif /* (CY_SPIM_SD_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c new file mode 100644 index 0000000..3ac6cea --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c @@ -0,0 +1,1155 @@ +/******************************************************************************* +* File Name: SDCard.c +* Version 2.40 +* +* Description: +* This file provides all API functionality of the SPI Master component. +* +* Note: +* None. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SDCard_PVT.h" + +#if(SDCard_TX_SOFTWARE_BUF_ENABLED) + volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] = {0u}; + volatile uint8 SDCard_txBufferFull; + volatile uint8 SDCard_txBufferRead; + volatile uint8 SDCard_txBufferWrite; +#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + +#if(SDCard_RX_SOFTWARE_BUF_ENABLED) + volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] = {0u}; + volatile uint8 SDCard_rxBufferFull; + volatile uint8 SDCard_rxBufferRead; + volatile uint8 SDCard_rxBufferWrite; +#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + +uint8 SDCard_initVar = 0u; + +volatile uint8 SDCard_swStatusTx; +volatile uint8 SDCard_swStatusRx; + + +/******************************************************************************* +* Function Name: SDCard_Init +******************************************************************************** +* +* Summary: +* Inits/Restores default SPIM configuration provided with customizer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* When this function is called it initializes all of the necessary parameters +* for execution. i.e. setting the initial interrupt mask, configuring the +* interrupt service routine, configuring the bit-counter parameters and +* clearing the FIFO and Status Register. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_Init(void) +{ + /* Initialize the Bit counter */ + SDCard_COUNTER_PERIOD_REG = SDCard_BITCTR_INIT; + + /* Init TX ISR */ + #if(0u != SDCard_INTERNAL_TX_INT_ENABLED) + CyIntDisable (SDCard_TX_ISR_NUMBER); + CyIntSetPriority (SDCard_TX_ISR_NUMBER, SDCard_TX_ISR_PRIORITY); + (void) CyIntSetVector(SDCard_TX_ISR_NUMBER, &SDCard_TX_ISR); + #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */ + + /* Init RX ISR */ + #if(0u != SDCard_INTERNAL_RX_INT_ENABLED) + CyIntDisable (SDCard_RX_ISR_NUMBER); + CyIntSetPriority (SDCard_RX_ISR_NUMBER, SDCard_RX_ISR_PRIORITY); + (void) CyIntSetVector(SDCard_RX_ISR_NUMBER, &SDCard_RX_ISR); + #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */ + + /* Clear any stray data from the RX and TX FIFO */ + SDCard_ClearFIFO(); + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + SDCard_rxBufferFull = 0u; + SDCard_rxBufferRead = 0u; + SDCard_rxBufferWrite = 0u; + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + SDCard_txBufferFull = 0u; + SDCard_txBufferRead = 0u; + SDCard_txBufferWrite = 0u; + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + (void) SDCard_ReadTxStatus(); /* Clear Tx status and swStatusTx */ + (void) SDCard_ReadRxStatus(); /* Clear Rx status and swStatusRx */ + + /* Configure TX and RX interrupt mask */ + SDCard_TX_STATUS_MASK_REG = SDCard_TX_INIT_INTERRUPTS_MASK; + SDCard_RX_STATUS_MASK_REG = SDCard_RX_INIT_INTERRUPTS_MASK; +} + + +/******************************************************************************* +* Function Name: SDCard_Enable +******************************************************************************** +* +* Summary: +* Enable SPIM component. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SDCard_Enable(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + SDCard_COUNTER_CONTROL_REG |= SDCard_CNTR_ENABLE; + SDCard_TX_STATUS_ACTL_REG |= SDCard_INT_ENABLE; + SDCard_RX_STATUS_ACTL_REG |= SDCard_INT_ENABLE; + CyExitCriticalSection(enableInterrupts); + + #if(0u != SDCard_INTERNAL_CLOCK) + SDCard_IntClock_Enable(); + #endif /* (0u != SDCard_INTERNAL_CLOCK) */ + + SDCard_EnableTxInt(); + SDCard_EnableRxInt(); +} + + +/******************************************************************************* +* Function Name: SDCard_Start +******************************************************************************** +* +* Summary: +* Initialize and Enable the SPI Master component. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_initVar - used to check initial configuration, modified on +* first function call. +* +* Theory: +* Enable the clock input to enable operation. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_Start(void) +{ + if(0u == SDCard_initVar) + { + SDCard_Init(); + SDCard_initVar = 1u; + } + + SDCard_Enable(); +} + + +/******************************************************************************* +* Function Name: SDCard_Stop +******************************************************************************** +* +* Summary: +* Disable the SPI Master component. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the clock input to enable operation. +* +*******************************************************************************/ +void SDCard_Stop(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + SDCard_TX_STATUS_ACTL_REG &= ((uint8) ~SDCard_INT_ENABLE); + SDCard_RX_STATUS_ACTL_REG &= ((uint8) ~SDCard_INT_ENABLE); + CyExitCriticalSection(enableInterrupts); + + #if(0u != SDCard_INTERNAL_CLOCK) + SDCard_IntClock_Disable(); + #endif /* (0u != SDCard_INTERNAL_CLOCK) */ + + SDCard_DisableTxInt(); + SDCard_DisableRxInt(); +} + + +/******************************************************************************* +* Function Name: SDCard_EnableTxInt +******************************************************************************** +* +* Summary: +* Enable internal Tx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal Tx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_EnableTxInt(void) +{ + #if(0u != SDCard_INTERNAL_TX_INT_ENABLED) + CyIntEnable(SDCard_TX_ISR_NUMBER); + #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_EnableRxInt +******************************************************************************** +* +* Summary: +* Enable internal Rx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal Rx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_EnableRxInt(void) +{ + #if(0u != SDCard_INTERNAL_RX_INT_ENABLED) + CyIntEnable(SDCard_RX_ISR_NUMBER); + #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_DisableTxInt +******************************************************************************** +* +* Summary: +* Disable internal Tx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal Tx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_DisableTxInt(void) +{ + #if(0u != SDCard_INTERNAL_TX_INT_ENABLED) + CyIntDisable(SDCard_TX_ISR_NUMBER); + #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_DisableRxInt +******************************************************************************** +* +* Summary: +* Disable internal Rx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal Rx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_DisableRxInt(void) +{ + #if(0u != SDCard_INTERNAL_RX_INT_ENABLED) + CyIntDisable(SDCard_RX_ISR_NUMBER); + #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_SetTxInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void SDCard_SetTxInterruptMode(uint8 intSrc) +{ + SDCard_TX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: SDCard_SetRxInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void SDCard_SetRxInterruptMode(uint8 intSrc) +{ + SDCard_RX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: SDCard_ReadTxStatus +******************************************************************************** +* +* Summary: +* Read the Tx status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the Tx status register. +* +* Global variables: +* SDCard_swStatusTx - used to store in software status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the Tx status register for error +* detection and flow control. +* +* Side Effects: +* Clear Tx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SDCard_ReadTxStatus(void) +{ + uint8 tmpStatus; + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + SDCard_DisableTxInt(); + + tmpStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx); + SDCard_swStatusTx = 0u; + + SDCard_EnableTxInt(); + + #else + + tmpStatus = SDCard_TX_STATUS_REG; + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: SDCard_ReadRxStatus +******************************************************************************** +* +* Summary: +* Read the Rx status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the Rx status register. +* +* Global variables: +* SDCard_swStatusRx - used to store in software Rx status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the Rx status register for error +* detection and flow control. +* +* Side Effects: +* Clear Rx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SDCard_ReadRxStatus(void) +{ + uint8 tmpStatus; + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + /* Disable RX interrupt to protect global veriables */ + SDCard_DisableRxInt(); + + tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx); + SDCard_swStatusRx = 0u; + + SDCard_EnableRxInt(); + + #else + + tmpStatus = SDCard_RX_STATUS_REG; + + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: SDCard_WriteTxData +******************************************************************************** +* +* Summary: +* Write a byte of data to be sent across the SPI. +* +* Parameters: +* txDataByte: The data value to send across the SPI. +* +* Return: +* None. +* +* Global variables: +* SDCard_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer, modified every function +* call if TX Software Buffer is used. +* SDCard_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer. +* SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] - used to store +* data to sending, modified every function call if TX Software Buffer is used. +* +* Theory: +* Allows the user to transmit any byte of data in a single transfer. +* +* Side Effects: +* If this function is called again before the previous byte is finished then +* the next byte will be appended to the transfer with no time between +* the byte transfers. Clear Tx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_WriteTxData(uint8 txData) +{ + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + + uint8 tempStatus; + uint8 tmpTxBufferRead; + + /* Block if TX buffer is FULL: don't overwrite */ + do + { + tmpTxBufferRead = SDCard_txBufferRead; + if(0u == tmpTxBufferRead) + { + tmpTxBufferRead = (SDCard_TX_BUFFER_SIZE - 1u); + } + else + { + tmpTxBufferRead--; + } + + }while(tmpTxBufferRead == SDCard_txBufferWrite); + + /* Disable TX interrupt to protect global veriables */ + SDCard_DisableTxInt(); + + tempStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx); + SDCard_swStatusTx = tempStatus; + + + if((SDCard_txBufferRead == SDCard_txBufferWrite) && + (0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL))) + { + /* Add directly to the TX FIFO */ + CY_SET_REG8(SDCard_TXDATA_PTR, txData); + } + else + { + /* Add to the TX software buffer */ + SDCard_txBufferWrite++; + if(SDCard_txBufferWrite >= SDCard_TX_BUFFER_SIZE) + { + SDCard_txBufferWrite = 0u; + } + + if(SDCard_txBufferWrite == SDCard_txBufferRead) + { + SDCard_txBufferRead++; + if(SDCard_txBufferRead >= SDCard_TX_BUFFER_SIZE) + { + SDCard_txBufferRead = 0u; + } + SDCard_txBufferFull = 1u; + } + + SDCard_txBuffer[SDCard_txBufferWrite] = txData; + + SDCard_TX_STATUS_MASK_REG |= SDCard_STS_TX_FIFO_NOT_FULL; + } + + SDCard_EnableTxInt(); + + #else + + while(0u == (SDCard_TX_STATUS_REG & SDCard_STS_TX_FIFO_NOT_FULL)) + { + ; /* Wait for room in FIFO */ + } + + /* Put byte in TX FIFO */ + CY_SET_REG8(SDCard_TXDATA_PTR, txData); + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_ReadRxData +******************************************************************************** +* +* Summary: +* Read the next byte of data received across the SPI. +* +* Parameters: +* None. +* +* Return: +* The next byte of data read from the FIFO. +* +* Global variables: +* SDCard_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer. +* SDCard_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified every function +* call if RX Software Buffer is used. +* SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] - used to store +* received data. +* +* Theory: +* Allows the user to read a byte of data received. +* +* Side Effects: +* Will return invalid data if the FIFO is empty. The user should Call +* GetRxBufferSize() and if it returns a non-zero value then it is safe to call +* ReadByte() function. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SDCard_ReadRxData(void) +{ + uint8 rxData; + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + + /* Disable RX interrupt to protect global veriables */ + SDCard_DisableRxInt(); + + if(SDCard_rxBufferRead != SDCard_rxBufferWrite) + { + if(0u == SDCard_rxBufferFull) + { + SDCard_rxBufferRead++; + if(SDCard_rxBufferRead >= SDCard_RX_BUFFER_SIZE) + { + SDCard_rxBufferRead = 0u; + } + } + else + { + SDCard_rxBufferFull = 0u; + } + } + + rxData = SDCard_rxBuffer[SDCard_rxBufferRead]; + + SDCard_EnableRxInt(); + + #else + + rxData = CY_GET_REG8(SDCard_RXDATA_PTR); + + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + return(rxData); +} + + +/******************************************************************************* +* Function Name: SDCard_GetRxBufferSize +******************************************************************************** +* +* Summary: +* Returns the number of bytes/words of data currently held in the RX buffer. +* If RX Software Buffer not used then function return 0 if FIFO empty or 1 if +* FIFO not empty. In another case function return size of RX Software Buffer. +* +* Parameters: +* None. +* +* Return: +* Integer count of the number of bytes/words in the RX buffer. +* +* Global variables: +* SDCard_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer. +* SDCard_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +uint8 SDCard_GetRxBufferSize(void) +{ + uint8 size; + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + + /* Disable RX interrupt to protect global veriables */ + SDCard_DisableRxInt(); + + if(SDCard_rxBufferRead == SDCard_rxBufferWrite) + { + size = 0u; + } + else if(SDCard_rxBufferRead < SDCard_rxBufferWrite) + { + size = (SDCard_rxBufferWrite - SDCard_rxBufferRead); + } + else + { + size = (SDCard_RX_BUFFER_SIZE - SDCard_rxBufferRead) + SDCard_rxBufferWrite; + } + + SDCard_EnableRxInt(); + + #else + + /* We can only know if there is data in the RX FIFO */ + size = (0u != (SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY)) ? 1u : 0u; + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + return(size); +} + + +/******************************************************************************* +* Function Name: SDCard_GetTxBufferSize +******************************************************************************** +* +* Summary: +* Returns the number of bytes/words of data currently held in the TX buffer. +* If TX Software Buffer not used then function return 0 - if FIFO empty, 1 - if +* FIFO not full, 4 - if FIFO full. In another case function return size of TX +* Software Buffer. +* +* Parameters: +* None. +* +* Return: +* Integer count of the number of bytes/words in the TX buffer. +* +* Global variables: +* SDCard_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer. +* SDCard_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +uint8 SDCard_GetTxBufferSize(void) +{ + uint8 size; + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + SDCard_DisableTxInt(); + + if(SDCard_txBufferRead == SDCard_txBufferWrite) + { + size = 0u; + } + else if(SDCard_txBufferRead < SDCard_txBufferWrite) + { + size = (SDCard_txBufferWrite - SDCard_txBufferRead); + } + else + { + size = (SDCard_TX_BUFFER_SIZE - SDCard_txBufferRead) + SDCard_txBufferWrite; + } + + SDCard_EnableTxInt(); + + #else + + size = SDCard_TX_STATUS_REG; + + if(0u != (size & SDCard_STS_TX_FIFO_EMPTY)) + { + size = 0u; + } + else if(0u != (size & SDCard_STS_TX_FIFO_NOT_FULL)) + { + size = 1u; + } + else + { + size = SDCard_FIFO_SIZE; + } + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + return(size); +} + + +/******************************************************************************* +* Function Name: SDCard_ClearRxBuffer +******************************************************************************** +* +* Summary: +* Clear the RX RAM buffer by setting the read and write pointers both to zero. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer, modified every function +* call - resets to zero. +* SDCard_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified every function call - +* resets to zero. +* +* Theory: +* Setting the pointers to zero makes the system believe there is no data to +* read and writing will resume at address 0 overwriting any data that may have +* remained in the RAM. +* +* Side Effects: +* Any received data not read from the RAM buffer will be lost when overwritten. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_ClearRxBuffer(void) +{ + /* Clear Hardware RX FIFO */ + while(0u !=(SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY)) + { + (void) CY_GET_REG8(SDCard_RXDATA_PTR); + } + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + /* Disable RX interrupt to protect global veriables */ + SDCard_DisableRxInt(); + + SDCard_rxBufferFull = 0u; + SDCard_rxBufferRead = 0u; + SDCard_rxBufferWrite = 0u; + + SDCard_EnableRxInt(); + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_ClearTxBuffer +******************************************************************************** +* +* Summary: +* Clear the TX RAM buffer by setting the read and write pointers both to zero. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer, modified every function +* call - resets to zero. +* SDCard_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer, modified every function call - +* resets to zero. +* +* Theory: +* Setting the pointers to zero makes the system believe there is no data to +* read and writing will resume at address 0 overwriting any data that may have +* remained in the RAM. +* +* Side Effects: +* Any data not yet transmitted from the RAM buffer will be lost when +* overwritten. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_ClearTxBuffer(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + /* Clear TX FIFO */ + SDCard_AUX_CONTROL_DP0_REG |= ((uint8) SDCard_TX_FIFO_CLR); + SDCard_AUX_CONTROL_DP0_REG &= ((uint8) ~SDCard_TX_FIFO_CLR); + + #if(SDCard_USE_SECOND_DATAPATH) + /* Clear TX FIFO for 2nd Datapath */ + SDCard_AUX_CONTROL_DP1_REG |= ((uint8) SDCard_TX_FIFO_CLR); + SDCard_AUX_CONTROL_DP1_REG &= ((uint8) ~SDCard_TX_FIFO_CLR); + #endif /* (SDCard_USE_SECOND_DATAPATH) */ + CyExitCriticalSection(enableInterrupts); + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + SDCard_DisableTxInt(); + + SDCard_txBufferFull = 0u; + SDCard_txBufferRead = 0u; + SDCard_txBufferWrite = 0u; + + /* Buffer is EMPTY: disable TX FIFO NOT FULL interrupt */ + SDCard_TX_STATUS_MASK_REG &= ((uint8) ~SDCard_STS_TX_FIFO_NOT_FULL); + + SDCard_EnableTxInt(); + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ +} + + +#if(0u != SDCard_BIDIRECTIONAL_MODE) + /******************************************************************************* + * Function Name: SDCard_TxEnable + ******************************************************************************** + * + * Summary: + * If the SPI master is configured to use a single bi-directional pin then this + * will set the bi-directional pin to transmit. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + void SDCard_TxEnable(void) + { + SDCard_CONTROL_REG |= SDCard_CTRL_TX_SIGNAL_EN; + } + + + /******************************************************************************* + * Function Name: SDCard_TxDisable + ******************************************************************************** + * + * Summary: + * If the SPI master is configured to use a single bi-directional pin then this + * will set the bi-directional pin to receive. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + void SDCard_TxDisable(void) + { + SDCard_CONTROL_REG &= ((uint8) ~SDCard_CTRL_TX_SIGNAL_EN); + } + +#endif /* (0u != SDCard_BIDIRECTIONAL_MODE) */ + + +/******************************************************************************* +* Function Name: SDCard_PutArray +******************************************************************************** +* +* Summary: +* Write available data from ROM/RAM to the TX buffer while space is available +* in the TX buffer. Keep trying until all data is passed to the TX buffer. +* +* Parameters: +* *buffer: Pointer to the location in RAM containing the data to send +* byteCount: The number of bytes to move to the transmit buffer. +* +* Return: +* None. +* +* Side Effects: +* Will stay in this routine until all data has been sent. May get locked in +* this loop if data is not being initiated by the master if there is not +* enough room in the TX FIFO. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_PutArray(const uint8 buffer[], uint8 byteCount) + +{ + uint8 bufIndex; + + bufIndex = 0u; + + while(byteCount > 0u) + { + SDCard_WriteTxData(buffer[bufIndex]); + bufIndex++; + byteCount--; + } +} + + +/******************************************************************************* +* Function Name: SDCard_ClearFIFO +******************************************************************************** +* +* Summary: +* Clear the RX and TX FIFO's of all data for a fresh start. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +void SDCard_ClearFIFO(void) +{ + uint8 enableInterrupts; + + /* Clear Hardware RX FIFO */ + while(0u !=(SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY)) + { + (void) CY_GET_REG8(SDCard_RXDATA_PTR); + } + + enableInterrupts = CyEnterCriticalSection(); + /* Clear TX FIFO */ + SDCard_AUX_CONTROL_DP0_REG |= ((uint8) SDCard_TX_FIFO_CLR); + SDCard_AUX_CONTROL_DP0_REG &= ((uint8) ~SDCard_TX_FIFO_CLR); + + #if(SDCard_USE_SECOND_DATAPATH) + /* Clear TX FIFO for 2nd Datapath */ + SDCard_AUX_CONTROL_DP1_REG |= ((uint8) SDCard_TX_FIFO_CLR); + SDCard_AUX_CONTROL_DP1_REG &= ((uint8) ~SDCard_TX_FIFO_CLR); + #endif /* (SDCard_USE_SECOND_DATAPATH) */ + CyExitCriticalSection(enableInterrupts); +} + + +/* Following functions are for version Compatibility, they are obsolete. +* Please do not use it in new projects. +*/ + + +/******************************************************************************* +* Function Name: SDCard_EnableInt +******************************************************************************** +* +* Summary: +* Enable internal interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_EnableInt(void) +{ + SDCard_EnableRxInt(); + SDCard_EnableTxInt(); +} + + +/******************************************************************************* +* Function Name: SDCard_DisableInt +******************************************************************************** +* +* Summary: +* Disable internal interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_DisableInt(void) +{ + SDCard_DisableTxInt(); + SDCard_DisableRxInt(); +} + + +/******************************************************************************* +* Function Name: SDCard_SetInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void SDCard_SetInterruptMode(uint8 intSrc) +{ + SDCard_TX_STATUS_MASK_REG = (intSrc & ((uint8) ~SDCard_STS_SPI_IDLE)); + SDCard_RX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: SDCard_ReadStatus +******************************************************************************** +* +* Summary: +* Read the status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the status register. +* +* Global variables: +* SDCard_swStatus - used to store in software status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the status register for error detection +* and flow control. +* +* Side Effects: +* Clear status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SDCard_ReadStatus(void) +{ + uint8 tmpStatus; + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED || SDCard_RX_SOFTWARE_BUF_ENABLED) + + SDCard_DisableInt(); + + tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx); + tmpStatus |= SDCard_GET_STATUS_TX(SDCard_swStatusTx); + tmpStatus &= ((uint8) ~SDCard_STS_SPI_IDLE); + + SDCard_swStatusTx = 0u; + SDCard_swStatusRx = 0u; + + SDCard_EnableInt(); + + #else + + tmpStatus = SDCard_RX_STATUS_REG; + tmpStatus |= SDCard_TX_STATUS_REG; + tmpStatus &= ((uint8) ~SDCard_STS_SPI_IDLE); + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED || SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h new file mode 100644 index 0000000..1c1f875 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h @@ -0,0 +1,389 @@ +/******************************************************************************* +* File Name: SDCard.h +* Version 2.40 +* +* Description: +* Contains the function prototypes, constants and register definition +* of the SPI Master Component. +* +* Note: +* None +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SPIM_SDCard_H) +#define CY_SPIM_SDCard_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "CyLib.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component SPI_Master_v2_40 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +#define SDCard_INTERNAL_CLOCK (0u) + +#if(0u != SDCard_INTERNAL_CLOCK) + #include "SDCard_IntClock.h" +#endif /* (0u != SDCard_INTERNAL_CLOCK) */ + +#define SDCard_MODE (1u) +#define SDCard_DATA_WIDTH (8u) +#define SDCard_MODE_USE_ZERO (1u) +#define SDCard_BIDIRECTIONAL_MODE (0u) + +/* Internal interrupt handling */ +#define SDCard_TX_BUFFER_SIZE (4u) +#define SDCard_RX_BUFFER_SIZE (4u) +#define SDCard_INTERNAL_TX_INT_ENABLED (1u) +#define SDCard_INTERNAL_RX_INT_ENABLED (1u) + +#define SDCard_SINGLE_REG_SIZE (8u) +#define SDCard_USE_SECOND_DATAPATH (SDCard_DATA_WIDTH > SDCard_SINGLE_REG_SIZE) + +#define SDCard_FIFO_SIZE (4u) +#define SDCard_TX_SOFTWARE_BUF_ENABLED ((0u != SDCard_INTERNAL_TX_INT_ENABLED) && \ + (SDCard_TX_BUFFER_SIZE > SDCard_FIFO_SIZE)) + +#define SDCard_RX_SOFTWARE_BUF_ENABLED ((0u != SDCard_INTERNAL_RX_INT_ENABLED) && \ + (SDCard_RX_BUFFER_SIZE > SDCard_FIFO_SIZE)) + + +/*************************************** +* Data Struct Definition +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 enableState; + uint8 cntrPeriod; + #if(CY_UDB_V0) + uint8 saveSrTxIntMask; + uint8 saveSrRxIntMask; + #endif /* (CY_UDB_V0) */ + +} SDCard_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +void SDCard_Init(void) ; +void SDCard_Enable(void) ; +void SDCard_Start(void) ; +void SDCard_Stop(void) ; + +void SDCard_EnableTxInt(void) ; +void SDCard_EnableRxInt(void) ; +void SDCard_DisableTxInt(void) ; +void SDCard_DisableRxInt(void) ; + +void SDCard_Sleep(void) ; +void SDCard_Wakeup(void) ; +void SDCard_SaveConfig(void) ; +void SDCard_RestoreConfig(void) ; + +void SDCard_SetTxInterruptMode(uint8 intSrc) ; +void SDCard_SetRxInterruptMode(uint8 intSrc) ; +uint8 SDCard_ReadTxStatus(void) ; +uint8 SDCard_ReadRxStatus(void) ; +void SDCard_WriteTxData(uint8 txData) \ + ; +uint8 SDCard_ReadRxData(void) \ + ; +uint8 SDCard_GetRxBufferSize(void) ; +uint8 SDCard_GetTxBufferSize(void) ; +void SDCard_ClearRxBuffer(void) ; +void SDCard_ClearTxBuffer(void) ; +void SDCard_ClearFIFO(void) ; +void SDCard_PutArray(const uint8 buffer[], uint8 byteCount) \ + ; + +#if(0u != SDCard_BIDIRECTIONAL_MODE) + void SDCard_TxEnable(void) ; + void SDCard_TxDisable(void) ; +#endif /* (0u != SDCard_BIDIRECTIONAL_MODE) */ + +CY_ISR_PROTO(SDCard_TX_ISR); +CY_ISR_PROTO(SDCard_RX_ISR); + + +/********************************** +* Variable with external linkage +**********************************/ + +extern uint8 SDCard_initVar; + + +/*************************************** +* API Constants +***************************************/ + +#define SDCard_TX_ISR_NUMBER ((uint8) (SDCard_TxInternalInterrupt__INTC_NUMBER)) +#define SDCard_RX_ISR_NUMBER ((uint8) (SDCard_RxInternalInterrupt__INTC_NUMBER)) + +#define SDCard_TX_ISR_PRIORITY ((uint8) (SDCard_TxInternalInterrupt__INTC_PRIOR_NUM)) +#define SDCard_RX_ISR_PRIORITY ((uint8) (SDCard_RxInternalInterrupt__INTC_PRIOR_NUM)) + + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define SDCard_INT_ON_SPI_DONE ((uint8) (0u << SDCard_STS_SPI_DONE_SHIFT)) +#define SDCard_INT_ON_TX_EMPTY ((uint8) (0u << SDCard_STS_TX_FIFO_EMPTY_SHIFT)) +#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \ + SDCard_STS_TX_FIFO_NOT_FULL_SHIFT)) +#define SDCard_INT_ON_BYTE_COMP ((uint8) (0u << SDCard_STS_BYTE_COMPLETE_SHIFT)) +#define SDCard_INT_ON_SPI_IDLE ((uint8) (0u << SDCard_STS_SPI_IDLE_SHIFT)) + +/* Disable TX_NOT_FULL if software buffer is used */ +#define SDCard_INT_ON_TX_NOT_FULL_DEF ((SDCard_TX_SOFTWARE_BUF_ENABLED) ? \ + (0u) : (SDCard_INT_ON_TX_NOT_FULL)) + +/* TX interrupt mask */ +#define SDCard_TX_INIT_INTERRUPTS_MASK (SDCard_INT_ON_SPI_DONE | \ + SDCard_INT_ON_TX_EMPTY | \ + SDCard_INT_ON_TX_NOT_FULL_DEF | \ + SDCard_INT_ON_BYTE_COMP | \ + SDCard_INT_ON_SPI_IDLE) + +#define SDCard_INT_ON_RX_FULL ((uint8) (0u << \ + SDCard_STS_RX_FIFO_FULL_SHIFT)) +#define SDCard_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \ + SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT)) +#define SDCard_INT_ON_RX_OVER ((uint8) (0u << \ + SDCard_STS_RX_FIFO_OVERRUN_SHIFT)) + +/* RX interrupt mask */ +#define SDCard_RX_INIT_INTERRUPTS_MASK (SDCard_INT_ON_RX_FULL | \ + SDCard_INT_ON_RX_NOT_EMPTY | \ + SDCard_INT_ON_RX_OVER) +/* Nubmer of bits to receive/transmit */ +#define SDCard_BITCTR_INIT (((uint8) (SDCard_DATA_WIDTH << 1u)) - 1u) + + +/*************************************** +* Registers +***************************************/ + +#if(CY_PSOC3 || CY_PSOC5) + #define SDCard_TXDATA_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F0_REG) + #define SDCard_TXDATA_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F0_REG) + #define SDCard_RXDATA_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F1_REG) + #define SDCard_RXDATA_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F1_REG) +#else /* PSOC4 */ + #if(SDCard_USE_SECOND_DATAPATH) + #define SDCard_TXDATA_REG (* (reg16 *) \ + SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG) + #define SDCard_TXDATA_PTR ( (reg16 *) \ + SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG) + #define SDCard_RXDATA_REG (* (reg16 *) \ + SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG) + #define SDCard_RXDATA_PTR ( (reg16 *) \ + SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG) + #else + #define SDCard_TXDATA_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F0_REG) + #define SDCard_TXDATA_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F0_REG) + #define SDCard_RXDATA_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F1_REG) + #define SDCard_RXDATA_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F1_REG) + #endif /* (SDCard_USE_SECOND_DATAPATH) */ +#endif /* (CY_PSOC3 || CY_PSOC5) */ + +#define SDCard_AUX_CONTROL_DP0_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG) +#define SDCard_AUX_CONTROL_DP0_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG) + +#if(SDCard_USE_SECOND_DATAPATH) + #define SDCard_AUX_CONTROL_DP1_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG) + #define SDCard_AUX_CONTROL_DP1_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG) +#endif /* (SDCard_USE_SECOND_DATAPATH) */ + +#define SDCard_COUNTER_PERIOD_REG (* (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG) +#define SDCard_COUNTER_PERIOD_PTR ( (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG) +#define SDCard_COUNTER_CONTROL_REG (* (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG) +#define SDCard_COUNTER_CONTROL_PTR ( (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG) + +#define SDCard_TX_STATUS_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG) +#define SDCard_TX_STATUS_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG) +#define SDCard_RX_STATUS_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG) +#define SDCard_RX_STATUS_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG) + +#define SDCard_CONTROL_REG (* (reg8 *) \ + SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG) +#define SDCard_CONTROL_PTR ( (reg8 *) \ + SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG) + +#define SDCard_TX_STATUS_MASK_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG) +#define SDCard_TX_STATUS_MASK_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG) +#define SDCard_RX_STATUS_MASK_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG) +#define SDCard_RX_STATUS_MASK_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG) + +#define SDCard_TX_STATUS_ACTL_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG) +#define SDCard_TX_STATUS_ACTL_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG) +#define SDCard_RX_STATUS_ACTL_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG) +#define SDCard_RX_STATUS_ACTL_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG) + +#if(SDCard_USE_SECOND_DATAPATH) + #define SDCard_AUX_CONTROLDP1 (SDCard_AUX_CONTROL_DP1_REG) +#endif /* (SDCard_USE_SECOND_DATAPATH) */ + + +/*************************************** +* Register Constants +***************************************/ + +/* Status Register Definitions */ +#define SDCard_STS_SPI_DONE_SHIFT (0x00u) +#define SDCard_STS_TX_FIFO_EMPTY_SHIFT (0x01u) +#define SDCard_STS_TX_FIFO_NOT_FULL_SHIFT (0x02u) +#define SDCard_STS_BYTE_COMPLETE_SHIFT (0x03u) +#define SDCard_STS_SPI_IDLE_SHIFT (0x04u) +#define SDCard_STS_RX_FIFO_FULL_SHIFT (0x04u) +#define SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT (0x05u) +#define SDCard_STS_RX_FIFO_OVERRUN_SHIFT (0x06u) + +#define SDCard_STS_SPI_DONE ((uint8) (0x01u << SDCard_STS_SPI_DONE_SHIFT)) +#define SDCard_STS_TX_FIFO_EMPTY ((uint8) (0x01u << SDCard_STS_TX_FIFO_EMPTY_SHIFT)) +#define SDCard_STS_TX_FIFO_NOT_FULL ((uint8) (0x01u << SDCard_STS_TX_FIFO_NOT_FULL_SHIFT)) +#define SDCard_STS_BYTE_COMPLETE ((uint8) (0x01u << SDCard_STS_BYTE_COMPLETE_SHIFT)) +#define SDCard_STS_SPI_IDLE ((uint8) (0x01u << SDCard_STS_SPI_IDLE_SHIFT)) +#define SDCard_STS_RX_FIFO_FULL ((uint8) (0x01u << SDCard_STS_RX_FIFO_FULL_SHIFT)) +#define SDCard_STS_RX_FIFO_NOT_EMPTY ((uint8) (0x01u << SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT)) +#define SDCard_STS_RX_FIFO_OVERRUN ((uint8) (0x01u << SDCard_STS_RX_FIFO_OVERRUN_SHIFT)) + +/* TX and RX masks for clear on read bits */ +#define SDCard_TX_STS_CLR_ON_RD_BYTES_MASK (0x09u) +#define SDCard_RX_STS_CLR_ON_RD_BYTES_MASK (0x40u) + +/* StatusI Register Interrupt Enable Control Bits */ +/* As defined by the Register map for the AUX Control Register */ +#define SDCard_INT_ENABLE (0x10u) /* Enable interrupt from statusi */ +#define SDCard_TX_FIFO_CLR (0x01u) /* F0 - TX FIFO */ +#define SDCard_RX_FIFO_CLR (0x02u) /* F1 - RX FIFO */ +#define SDCard_FIFO_CLR (SDCard_TX_FIFO_CLR | SDCard_RX_FIFO_CLR) + +/* Bit Counter (7-bit) Control Register Bit Definitions */ +/* As defined by the Register map for the AUX Control Register */ +#define SDCard_CNTR_ENABLE (0x20u) /* Enable CNT7 */ + +/* Bi-Directional mode control bit */ +#define SDCard_CTRL_TX_SIGNAL_EN (0x01u) + +/* Datapath Auxillary Control Register definitions */ +#define SDCard_AUX_CTRL_FIFO0_CLR (0x01u) +#define SDCard_AUX_CTRL_FIFO1_CLR (0x02u) +#define SDCard_AUX_CTRL_FIFO0_LVL (0x04u) +#define SDCard_AUX_CTRL_FIFO1_LVL (0x08u) +#define SDCard_STATUS_ACTL_INT_EN_MASK (0x10u) + +/* Component disabled */ +#define SDCard_DISABLED (0u) + + +/*************************************** +* Macros +***************************************/ + +/* Returns true if componentn enabled */ +#define SDCard_IS_ENABLED (0u != (SDCard_TX_STATUS_ACTL_REG & SDCard_INT_ENABLE)) + +/* Retuns TX status register */ +#define SDCard_GET_STATUS_TX(swTxSts) ( (uint8)(SDCard_TX_STATUS_REG | \ + ((swTxSts) & SDCard_TX_STS_CLR_ON_RD_BYTES_MASK)) ) +/* Retuns RX status register */ +#define SDCard_GET_STATUS_RX(swRxSts) ( (uint8)(SDCard_RX_STATUS_REG | \ + ((swRxSts) & SDCard_RX_STS_CLR_ON_RD_BYTES_MASK)) ) + + +/*************************************** +* Obsolete definitions +***************************************/ + +/* Following definitions are for version compatibility. +* They are obsolete in SPIM v2_30. +* Please do not use it in new projects +*/ + +#define SDCard_WriteByte SDCard_WriteTxData +#define SDCard_ReadByte SDCard_ReadRxData +void SDCard_SetInterruptMode(uint8 intSrc) ; +uint8 SDCard_ReadStatus(void) ; +void SDCard_EnableInt(void) ; +void SDCard_DisableInt(void) ; + +/* Obsolete register names. Not to be used in new designs */ +#define SDCard_TXDATA (SDCard_TXDATA_REG) +#define SDCard_RXDATA (SDCard_RXDATA_REG) +#define SDCard_AUX_CONTROLDP0 (SDCard_AUX_CONTROL_DP0_REG) +#define SDCard_TXBUFFERREAD (SDCard_txBufferRead) +#define SDCard_TXBUFFERWRITE (SDCard_txBufferWrite) +#define SDCard_RXBUFFERREAD (SDCard_rxBufferRead) +#define SDCard_RXBUFFERWRITE (SDCard_rxBufferWrite) + +#define SDCard_COUNTER_PERIOD (SDCard_COUNTER_PERIOD_REG) +#define SDCard_COUNTER_CONTROL (SDCard_COUNTER_CONTROL_REG) +#define SDCard_STATUS (SDCard_TX_STATUS_REG) +#define SDCard_CONTROL (SDCard_CONTROL_REG) +#define SDCard_STATUS_MASK (SDCard_TX_STATUS_MASK_REG) +#define SDCard_STATUS_ACTL (SDCard_TX_STATUS_ACTL_REG) + +#define SDCard_INIT_INTERRUPTS_MASK (SDCard_INT_ON_SPI_DONE | \ + SDCard_INT_ON_TX_EMPTY | \ + SDCard_INT_ON_TX_NOT_FULL_DEF | \ + SDCard_INT_ON_RX_FULL | \ + SDCard_INT_ON_RX_NOT_EMPTY | \ + SDCard_INT_ON_RX_OVER | \ + SDCard_INT_ON_BYTE_COMP) + +/* Following definitions are for version Compatibility. +* They are obsolete in SPIM v2_40. +* Please do not use it in new projects +*/ + +#define SDCard_DataWidth (SDCard_DATA_WIDTH) +#define SDCard_InternalClockUsed (SDCard_INTERNAL_CLOCK) +#define SDCard_InternalTxInterruptEnabled (SDCard_INTERNAL_TX_INT_ENABLED) +#define SDCard_InternalRxInterruptEnabled (SDCard_INTERNAL_RX_INT_ENABLED) +#define SDCard_ModeUseZero (SDCard_MODE_USE_ZERO) +#define SDCard_BidirectionalMode (SDCard_BIDIRECTIONAL_MODE) +#define SDCard_Mode (SDCard_MODE) +#define SDCard_DATAWIDHT (SDCard_DATA_WIDTH) +#define SDCard_InternalInterruptEnabled (0u) + +#define SDCard_TXBUFFERSIZE (SDCard_TX_BUFFER_SIZE) +#define SDCard_RXBUFFERSIZE (SDCard_RX_BUFFER_SIZE) + +#define SDCard_TXBUFFER SDCard_txBuffer +#define SDCard_RXBUFFER SDCard_rxBuffer + +#endif /* (CY_SPIM_SDCard_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c new file mode 100644 index 0000000..d2e68ea --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c @@ -0,0 +1,189 @@ +/******************************************************************************* +* File Name: SDCard_INT.c +* Version 2.40 +* +* Description: +* This file provides all Interrupt Service Routine (ISR) for the SPI Master +* component. +* +* Note: +* None. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SDCard_PVT.h" + +/* User code required at start of ISR */ +/* `#START SDCard_ISR_START_DEF` */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: SDCard_TX_ISR +******************************************************************************** +* +* Summary: +* Interrupt Service Routine for TX portion of the SPI Master. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer. +* SDCard_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer, modified when exist data to +* sending and FIFO Not Full. +* SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] - used to store +* data to sending. +* All described above Global variables are used when Software Buffer is used. +* +*******************************************************************************/ +CY_ISR(SDCard_TX_ISR) +{ + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + uint8 tmpStatus; + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at start of ISR */ + /* `#START SDCard_TX_ISR_START` */ + + /* `#END` */ + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + /* Check if TX data buffer is not empty and there is space in TX FIFO */ + while(SDCard_txBufferRead != SDCard_txBufferWrite) + { + tmpStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx); + SDCard_swStatusTx = tmpStatus; + + if(0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL)) + { + if(0u == SDCard_txBufferFull) + { + SDCard_txBufferRead++; + + if(SDCard_txBufferRead >= SDCard_TX_BUFFER_SIZE) + { + SDCard_txBufferRead = 0u; + } + } + else + { + SDCard_txBufferFull = 0u; + } + + /* Move data from the Buffer to the FIFO */ + CY_SET_REG8(SDCard_TXDATA_PTR, + SDCard_txBuffer[SDCard_txBufferRead]); + } + else + { + break; + } + } + + if(SDCard_txBufferRead == SDCard_txBufferWrite) + { + /* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */ + SDCard_TX_STATUS_MASK_REG &= ((uint8) ~SDCard_STS_TX_FIFO_NOT_FULL); + } + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at end of ISR (Optional) */ + /* `#START SDCard_TX_ISR_END` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SDCard_RX_ISR +******************************************************************************** +* +* Summary: +* Interrupt Service Routine for RX portion of the SPI Master. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer modified when FIFO contains +* new data. +* SDCard_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified when overflow occurred. +* SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] - used to store +* received data, modified when FIFO contains new data. +* All described above Global variables are used when Software Buffer is used. +* +*******************************************************************************/ +CY_ISR(SDCard_RX_ISR) +{ + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + uint8 tmpStatus; + uint8 rxData; + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at start of ISR */ + /* `#START SDCard_RX_ISR_START` */ + + /* `#END` */ + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + + tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx); + SDCard_swStatusRx = tmpStatus; + + /* Check if RX data FIFO has some data to be moved into the RX Buffer */ + while(0u != (SDCard_swStatusRx & SDCard_STS_RX_FIFO_NOT_EMPTY)) + { + rxData = CY_GET_REG8(SDCard_RXDATA_PTR); + + /* Set next pointer. */ + SDCard_rxBufferWrite++; + if(SDCard_rxBufferWrite >= SDCard_RX_BUFFER_SIZE) + { + SDCard_rxBufferWrite = 0u; + } + + if(SDCard_rxBufferWrite == SDCard_rxBufferRead) + { + SDCard_rxBufferRead++; + if(SDCard_rxBufferRead >= SDCard_RX_BUFFER_SIZE) + { + SDCard_rxBufferRead = 0u; + } + + SDCard_rxBufferFull = 1u; + } + + /* Move data from the FIFO to the Buffer */ + SDCard_rxBuffer[SDCard_rxBufferWrite] = rxData; + + tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx); + SDCard_swStatusRx = tmpStatus; + } + + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at end of ISR (Optional) */ + /* `#START SDCard_RX_ISR_END` */ + + /* `#END` */ +} + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c new file mode 100644 index 0000000..8819841 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c @@ -0,0 +1,180 @@ +/******************************************************************************* +* File Name: SDCard_PM.c +* Version 2.40 +* +* Description: +* This file contains the setup, control and status commands to support +* component operations in low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SDCard_PVT.h" + +static SDCard_BACKUP_STRUCT SDCard_backup = +{ + SDCard_DISABLED, + SDCard_BITCTR_INIT, + #if(CY_UDB_V0) + SDCard_TX_INIT_INTERRUPTS_MASK, + SDCard_RX_INIT_INTERRUPTS_MASK + #endif /* CY_UDB_V0 */ +}; + + +/******************************************************************************* +* Function Name: SDCard_SaveConfig +******************************************************************************** +* +* Summary: +* Saves SPIM configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SDCard_backup - modified when non-retention registers are saved. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_SaveConfig(void) +{ + /* Store Status Mask registers */ + #if(CY_UDB_V0) + SDCard_backup.cntrPeriod = SDCard_COUNTER_PERIOD_REG; + SDCard_backup.saveSrTxIntMask = SDCard_TX_STATUS_MASK_REG; + SDCard_backup.saveSrRxIntMask = SDCard_RX_STATUS_MASK_REG; + #endif /* (CY_UDB_V0) */ +} + + +/******************************************************************************* +* Function Name: SDCard_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores SPIM configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SDCard_backup - used when non-retention registers are restored. +* +* Side Effects: +* If this API is called without first calling SaveConfig then in the following +* registers will be default values from Customizer: +* SDCard_STATUS_MASK_REG and SDCard_COUNTER_PERIOD_REG. +* +*******************************************************************************/ +void SDCard_RestoreConfig(void) +{ + /* Restore the data, saved by SaveConfig() function */ + #if(CY_UDB_V0) + SDCard_COUNTER_PERIOD_REG = SDCard_backup.cntrPeriod; + SDCard_TX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrTxIntMask); + SDCard_RX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrRxIntMask); + #endif /* (CY_UDB_V0) */ +} + + +/******************************************************************************* +* Function Name: SDCard_Sleep +******************************************************************************** +* +* Summary: +* Prepare SPIM Component goes to sleep. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SDCard_backup - modified when non-retention registers are saved. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_Sleep(void) +{ + /* Save components enable state */ + SDCard_backup.enableState = ((uint8) SDCard_IS_ENABLED); + + SDCard_Stop(); + SDCard_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: SDCard_Wakeup +******************************************************************************** +* +* Summary: +* Prepare SPIM Component to wake up. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SDCard_backup - used when non-retention registers are restored. +* SDCard_txBufferWrite - modified every function call - resets to +* zero. +* SDCard_txBufferRead - modified every function call - resets to +* zero. +* SDCard_rxBufferWrite - modified every function call - resets to +* zero. +* SDCard_rxBufferRead - modified every function call - resets to +* zero. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_Wakeup(void) +{ + SDCard_RestoreConfig(); + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + SDCard_rxBufferFull = 0u; + SDCard_rxBufferRead = 0u; + SDCard_rxBufferWrite = 0u; + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + SDCard_txBufferFull = 0u; + SDCard_txBufferRead = 0u; + SDCard_txBufferWrite = 0u; + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + /* Clear any data from the RX and TX FIFO */ + SDCard_ClearFIFO(); + + /* Restore components block enable state */ + if(0u != SDCard_backup.enableState) + { + SDCard_Enable(); + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h new file mode 100644 index 0000000..7618531 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: .h +* Version 2.40 +* +* Description: +* This private header file contains internal definitions for the SPIM +* component. Do not use these definitions directly in your application. +* +* Note: +* +******************************************************************************** +* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SPIM_PVT_SDCard_H) +#define CY_SPIM_PVT_SDCard_H + +#include "SDCard.h" + + +/********************************** +* Functions with external linkage +**********************************/ + + +/********************************** +* Variables with external linkage +**********************************/ + +extern volatile uint8 SDCard_swStatusTx; +extern volatile uint8 SDCard_swStatusRx; + +#if(SDCard_TX_SOFTWARE_BUF_ENABLED) + extern volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE]; + extern volatile uint8 SDCard_txBufferRead; + extern volatile uint8 SDCard_txBufferWrite; + extern volatile uint8 SDCard_txBufferFull; +#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + +#if(SDCard_RX_SOFTWARE_BUF_ENABLED) + extern volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE]; + extern volatile uint8 SDCard_rxBufferRead; + extern volatile uint8 SDCard_rxBufferWrite; + extern volatile uint8 SDCard_rxBufferFull; +#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + +#endif /* CY_SPIM_PVT_SDCard_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c new file mode 100644 index 0000000..1824609 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SD_CD.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_CD.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_CD_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_CD_Write(uint8 value) +{ + uint8 staticBits = (SD_CD_DR & (uint8)(~SD_CD_MASK)); + SD_CD_DR = staticBits | ((uint8)(value << SD_CD_SHIFT) & SD_CD_MASK); +} + + +/******************************************************************************* +* Function Name: SD_CD_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_CD_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_CD_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_CD_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_CD_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_CD_Read(void) +{ + return (SD_CD_PS & SD_CD_MASK) >> SD_CD_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_CD_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_CD_ReadDataReg(void) +{ + return (SD_CD_DR & SD_CD_MASK) >> SD_CD_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_CD_INTSTAT) + + /******************************************************************************* + * Function Name: SD_CD_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_CD_ClearInterrupt(void) + { + return (SD_CD_INTSTAT & SD_CD_MASK) >> SD_CD_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h new file mode 100644 index 0000000..fca729e --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_CD.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_CD_H) /* Pins SD_CD_H */ +#define CY_PINS_SD_CD_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_CD_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_CD_Write(uint8 value) ; +void SD_CD_SetDriveMode(uint8 mode) ; +uint8 SD_CD_ReadDataReg(void) ; +uint8 SD_CD_Read(void) ; +uint8 SD_CD_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_CD_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_CD_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_CD_DM_RES_UP PIN_DM_RES_UP +#define SD_CD_DM_RES_DWN PIN_DM_RES_DWN +#define SD_CD_DM_OD_LO PIN_DM_OD_LO +#define SD_CD_DM_OD_HI PIN_DM_OD_HI +#define SD_CD_DM_STRONG PIN_DM_STRONG +#define SD_CD_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_CD_MASK SD_CD__MASK +#define SD_CD_SHIFT SD_CD__SHIFT +#define SD_CD_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_CD_PS (* (reg8 *) SD_CD__PS) +/* Data Register */ +#define SD_CD_DR (* (reg8 *) SD_CD__DR) +/* Port Number */ +#define SD_CD_PRT_NUM (* (reg8 *) SD_CD__PRT) +/* Connect to Analog Globals */ +#define SD_CD_AG (* (reg8 *) SD_CD__AG) +/* Analog MUX bux enable */ +#define SD_CD_AMUX (* (reg8 *) SD_CD__AMUX) +/* Bidirectional Enable */ +#define SD_CD_BIE (* (reg8 *) SD_CD__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_CD_BIT_MASK (* (reg8 *) SD_CD__BIT_MASK) +/* Bypass Enable */ +#define SD_CD_BYP (* (reg8 *) SD_CD__BYP) +/* Port wide control signals */ +#define SD_CD_CTL (* (reg8 *) SD_CD__CTL) +/* Drive Modes */ +#define SD_CD_DM0 (* (reg8 *) SD_CD__DM0) +#define SD_CD_DM1 (* (reg8 *) SD_CD__DM1) +#define SD_CD_DM2 (* (reg8 *) SD_CD__DM2) +/* Input Buffer Disable Override */ +#define SD_CD_INP_DIS (* (reg8 *) SD_CD__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_CD_LCD_COM_SEG (* (reg8 *) SD_CD__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_CD_LCD_EN (* (reg8 *) SD_CD__LCD_EN) +/* Slew Rate Control */ +#define SD_CD_SLW (* (reg8 *) SD_CD__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_CD_PRTDSI__CAPS_SEL (* (reg8 *) SD_CD__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_CD_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_CD__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_CD_PRTDSI__OE_SEL0 (* (reg8 *) SD_CD__PRTDSI__OE_SEL0) +#define SD_CD_PRTDSI__OE_SEL1 (* (reg8 *) SD_CD__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_CD_PRTDSI__OUT_SEL0 (* (reg8 *) SD_CD__PRTDSI__OUT_SEL0) +#define SD_CD_PRTDSI__OUT_SEL1 (* (reg8 *) SD_CD__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_CD_PRTDSI__SYNC_OUT (* (reg8 *) SD_CD__PRTDSI__SYNC_OUT) + + +#if defined(SD_CD__INTSTAT) /* Interrupt Registers */ + + #define SD_CD_INTSTAT (* (reg8 *) SD_CD__INTSTAT) + #define SD_CD_SNAP (* (reg8 *) SD_CD__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_CD_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h new file mode 100644 index 0000000..782cb81 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: SD_CD.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_CD_ALIASES_H) /* Pins SD_CD_ALIASES_H */ +#define CY_PINS_SD_CD_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_CD_0 SD_CD__0__PC + +#endif /* End Pins SD_CD_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c new file mode 100644 index 0000000..37a6919 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SD_CS.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_CS.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_CS_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_CS_Write(uint8 value) +{ + uint8 staticBits = (SD_CS_DR & (uint8)(~SD_CS_MASK)); + SD_CS_DR = staticBits | ((uint8)(value << SD_CS_SHIFT) & SD_CS_MASK); +} + + +/******************************************************************************* +* Function Name: SD_CS_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_CS_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_CS_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_CS_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_CS_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_CS_Read(void) +{ + return (SD_CS_PS & SD_CS_MASK) >> SD_CS_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_CS_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_CS_ReadDataReg(void) +{ + return (SD_CS_DR & SD_CS_MASK) >> SD_CS_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_CS_INTSTAT) + + /******************************************************************************* + * Function Name: SD_CS_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_CS_ClearInterrupt(void) + { + return (SD_CS_INTSTAT & SD_CS_MASK) >> SD_CS_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h new file mode 100644 index 0000000..aa66de1 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_CS.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_CS_H) /* Pins SD_CS_H */ +#define CY_PINS_SD_CS_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_CS_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_CS_Write(uint8 value) ; +void SD_CS_SetDriveMode(uint8 mode) ; +uint8 SD_CS_ReadDataReg(void) ; +uint8 SD_CS_Read(void) ; +uint8 SD_CS_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_CS_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_CS_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_CS_DM_RES_UP PIN_DM_RES_UP +#define SD_CS_DM_RES_DWN PIN_DM_RES_DWN +#define SD_CS_DM_OD_LO PIN_DM_OD_LO +#define SD_CS_DM_OD_HI PIN_DM_OD_HI +#define SD_CS_DM_STRONG PIN_DM_STRONG +#define SD_CS_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_CS_MASK SD_CS__MASK +#define SD_CS_SHIFT SD_CS__SHIFT +#define SD_CS_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_CS_PS (* (reg8 *) SD_CS__PS) +/* Data Register */ +#define SD_CS_DR (* (reg8 *) SD_CS__DR) +/* Port Number */ +#define SD_CS_PRT_NUM (* (reg8 *) SD_CS__PRT) +/* Connect to Analog Globals */ +#define SD_CS_AG (* (reg8 *) SD_CS__AG) +/* Analog MUX bux enable */ +#define SD_CS_AMUX (* (reg8 *) SD_CS__AMUX) +/* Bidirectional Enable */ +#define SD_CS_BIE (* (reg8 *) SD_CS__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_CS_BIT_MASK (* (reg8 *) SD_CS__BIT_MASK) +/* Bypass Enable */ +#define SD_CS_BYP (* (reg8 *) SD_CS__BYP) +/* Port wide control signals */ +#define SD_CS_CTL (* (reg8 *) SD_CS__CTL) +/* Drive Modes */ +#define SD_CS_DM0 (* (reg8 *) SD_CS__DM0) +#define SD_CS_DM1 (* (reg8 *) SD_CS__DM1) +#define SD_CS_DM2 (* (reg8 *) SD_CS__DM2) +/* Input Buffer Disable Override */ +#define SD_CS_INP_DIS (* (reg8 *) SD_CS__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_CS_LCD_COM_SEG (* (reg8 *) SD_CS__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_CS_LCD_EN (* (reg8 *) SD_CS__LCD_EN) +/* Slew Rate Control */ +#define SD_CS_SLW (* (reg8 *) SD_CS__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_CS_PRTDSI__CAPS_SEL (* (reg8 *) SD_CS__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_CS_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_CS__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_CS_PRTDSI__OE_SEL0 (* (reg8 *) SD_CS__PRTDSI__OE_SEL0) +#define SD_CS_PRTDSI__OE_SEL1 (* (reg8 *) SD_CS__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_CS_PRTDSI__OUT_SEL0 (* (reg8 *) SD_CS__PRTDSI__OUT_SEL0) +#define SD_CS_PRTDSI__OUT_SEL1 (* (reg8 *) SD_CS__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_CS_PRTDSI__SYNC_OUT (* (reg8 *) SD_CS__PRTDSI__SYNC_OUT) + + +#if defined(SD_CS__INTSTAT) /* Interrupt Registers */ + + #define SD_CS_INTSTAT (* (reg8 *) SD_CS__INTSTAT) + #define SD_CS_SNAP (* (reg8 *) SD_CS__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_CS_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h new file mode 100644 index 0000000..d6c29cc --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: SD_CS.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_CS_ALIASES_H) /* Pins SD_CS_ALIASES_H */ +#define CY_PINS_SD_CS_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_CS_0 SD_CS__0__PC + +#endif /* End Pins SD_CS_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c new file mode 100644 index 0000000..6553ced --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c @@ -0,0 +1,63 @@ +/******************************************************************************* +* File Name: SD_Clk_Ctl.c +* Version 1.70 +* +* Description: +* This file contains API to enable firmware control of a Control Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SD_Clk_Ctl.h" + +#if !defined(SD_Clk_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Function Name: SD_Clk_Ctl_Write +******************************************************************************** +* +* Summary: +* Write a byte to the Control Register. +* +* Parameters: +* control: The value to be assigned to the Control Register. +* +* Return: +* None. +* +*******************************************************************************/ +void SD_Clk_Ctl_Write(uint8 control) +{ + SD_Clk_Ctl_Control = control; +} + + +/******************************************************************************* +* Function Name: SD_Clk_Ctl_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Control Register. +* +* Parameters: +* None. +* +* Return: +* Returns the current value in the Control Register. +* +*******************************************************************************/ +uint8 SD_Clk_Ctl_Read(void) +{ + return SD_Clk_Ctl_Control; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h new file mode 100644 index 0000000..7c6d263 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: SD_Clk_Ctl.h +* Version 1.70 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CONTROL_REG_SD_Clk_Ctl_H) /* CY_CONTROL_REG_SD_Clk_Ctl_H */ +#define CY_CONTROL_REG_SD_Clk_Ctl_H + +#include "cytypes.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_Clk_Ctl_Write(uint8 control) ; +uint8 SD_Clk_Ctl_Read(void) ; + + +/*************************************** +* Registers +***************************************/ + +/* Control Register */ +#define SD_Clk_Ctl_Control (* (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG ) +#define SD_Clk_Ctl_Control_PTR ( (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG ) + +#endif /* End CY_CONTROL_REG_SD_Clk_Ctl_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.c new file mode 100644 index 0000000..534aa57 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SD_DAT1.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_DAT1.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_DAT1__PORT == 15 && ((SD_DAT1__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_DAT1_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_DAT1_Write(uint8 value) +{ + uint8 staticBits = (SD_DAT1_DR & (uint8)(~SD_DAT1_MASK)); + SD_DAT1_DR = staticBits | ((uint8)(value << SD_DAT1_SHIFT) & SD_DAT1_MASK); +} + + +/******************************************************************************* +* Function Name: SD_DAT1_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_DAT1_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_DAT1_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_DAT1_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_DAT1_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_DAT1_Read(void) +{ + return (SD_DAT1_PS & SD_DAT1_MASK) >> SD_DAT1_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_DAT1_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_DAT1_ReadDataReg(void) +{ + return (SD_DAT1_DR & SD_DAT1_MASK) >> SD_DAT1_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_DAT1_INTSTAT) + + /******************************************************************************* + * Function Name: SD_DAT1_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_DAT1_ClearInterrupt(void) + { + return (SD_DAT1_INTSTAT & SD_DAT1_MASK) >> SD_DAT1_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.h new file mode 100644 index 0000000..d7e2253 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_DAT1.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_DAT1_H) /* Pins SD_DAT1_H */ +#define CY_PINS_SD_DAT1_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_DAT1_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_DAT1__PORT == 15 && ((SD_DAT1__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_DAT1_Write(uint8 value) ; +void SD_DAT1_SetDriveMode(uint8 mode) ; +uint8 SD_DAT1_ReadDataReg(void) ; +uint8 SD_DAT1_Read(void) ; +uint8 SD_DAT1_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_DAT1_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_DAT1_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_DAT1_DM_RES_UP PIN_DM_RES_UP +#define SD_DAT1_DM_RES_DWN PIN_DM_RES_DWN +#define SD_DAT1_DM_OD_LO PIN_DM_OD_LO +#define SD_DAT1_DM_OD_HI PIN_DM_OD_HI +#define SD_DAT1_DM_STRONG PIN_DM_STRONG +#define SD_DAT1_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_DAT1_MASK SD_DAT1__MASK +#define SD_DAT1_SHIFT SD_DAT1__SHIFT +#define SD_DAT1_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_DAT1_PS (* (reg8 *) SD_DAT1__PS) +/* Data Register */ +#define SD_DAT1_DR (* (reg8 *) SD_DAT1__DR) +/* Port Number */ +#define SD_DAT1_PRT_NUM (* (reg8 *) SD_DAT1__PRT) +/* Connect to Analog Globals */ +#define SD_DAT1_AG (* (reg8 *) SD_DAT1__AG) +/* Analog MUX bux enable */ +#define SD_DAT1_AMUX (* (reg8 *) SD_DAT1__AMUX) +/* Bidirectional Enable */ +#define SD_DAT1_BIE (* (reg8 *) SD_DAT1__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_DAT1_BIT_MASK (* (reg8 *) SD_DAT1__BIT_MASK) +/* Bypass Enable */ +#define SD_DAT1_BYP (* (reg8 *) SD_DAT1__BYP) +/* Port wide control signals */ +#define SD_DAT1_CTL (* (reg8 *) SD_DAT1__CTL) +/* Drive Modes */ +#define SD_DAT1_DM0 (* (reg8 *) SD_DAT1__DM0) +#define SD_DAT1_DM1 (* (reg8 *) SD_DAT1__DM1) +#define SD_DAT1_DM2 (* (reg8 *) SD_DAT1__DM2) +/* Input Buffer Disable Override */ +#define SD_DAT1_INP_DIS (* (reg8 *) SD_DAT1__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_DAT1_LCD_COM_SEG (* (reg8 *) SD_DAT1__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_DAT1_LCD_EN (* (reg8 *) SD_DAT1__LCD_EN) +/* Slew Rate Control */ +#define SD_DAT1_SLW (* (reg8 *) SD_DAT1__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_DAT1_PRTDSI__CAPS_SEL (* (reg8 *) SD_DAT1__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_DAT1_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_DAT1__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_DAT1_PRTDSI__OE_SEL0 (* (reg8 *) SD_DAT1__PRTDSI__OE_SEL0) +#define SD_DAT1_PRTDSI__OE_SEL1 (* (reg8 *) SD_DAT1__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_DAT1_PRTDSI__OUT_SEL0 (* (reg8 *) SD_DAT1__PRTDSI__OUT_SEL0) +#define SD_DAT1_PRTDSI__OUT_SEL1 (* (reg8 *) SD_DAT1__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_DAT1_PRTDSI__SYNC_OUT (* (reg8 *) SD_DAT1__PRTDSI__SYNC_OUT) + + +#if defined(SD_DAT1__INTSTAT) /* Interrupt Registers */ + + #define SD_DAT1_INTSTAT (* (reg8 *) SD_DAT1__INTSTAT) + #define SD_DAT1_SNAP (* (reg8 *) SD_DAT1__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_DAT1_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1_aliases.h new file mode 100644 index 0000000..a26e0de --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: SD_DAT1.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_DAT1_ALIASES_H) /* Pins SD_DAT1_ALIASES_H */ +#define CY_PINS_SD_DAT1_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_DAT1_0 SD_DAT1__0__PC + +#endif /* End Pins SD_DAT1_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.c new file mode 100644 index 0000000..8dfc6ae --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SD_DAT2.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_DAT2.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_DAT2__PORT == 15 && ((SD_DAT2__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_DAT2_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_DAT2_Write(uint8 value) +{ + uint8 staticBits = (SD_DAT2_DR & (uint8)(~SD_DAT2_MASK)); + SD_DAT2_DR = staticBits | ((uint8)(value << SD_DAT2_SHIFT) & SD_DAT2_MASK); +} + + +/******************************************************************************* +* Function Name: SD_DAT2_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_DAT2_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_DAT2_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_DAT2_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_DAT2_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_DAT2_Read(void) +{ + return (SD_DAT2_PS & SD_DAT2_MASK) >> SD_DAT2_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_DAT2_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_DAT2_ReadDataReg(void) +{ + return (SD_DAT2_DR & SD_DAT2_MASK) >> SD_DAT2_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_DAT2_INTSTAT) + + /******************************************************************************* + * Function Name: SD_DAT2_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_DAT2_ClearInterrupt(void) + { + return (SD_DAT2_INTSTAT & SD_DAT2_MASK) >> SD_DAT2_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.h new file mode 100644 index 0000000..bfb3017 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_DAT2.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_DAT2_H) /* Pins SD_DAT2_H */ +#define CY_PINS_SD_DAT2_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_DAT2_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_DAT2__PORT == 15 && ((SD_DAT2__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_DAT2_Write(uint8 value) ; +void SD_DAT2_SetDriveMode(uint8 mode) ; +uint8 SD_DAT2_ReadDataReg(void) ; +uint8 SD_DAT2_Read(void) ; +uint8 SD_DAT2_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_DAT2_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_DAT2_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_DAT2_DM_RES_UP PIN_DM_RES_UP +#define SD_DAT2_DM_RES_DWN PIN_DM_RES_DWN +#define SD_DAT2_DM_OD_LO PIN_DM_OD_LO +#define SD_DAT2_DM_OD_HI PIN_DM_OD_HI +#define SD_DAT2_DM_STRONG PIN_DM_STRONG +#define SD_DAT2_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_DAT2_MASK SD_DAT2__MASK +#define SD_DAT2_SHIFT SD_DAT2__SHIFT +#define SD_DAT2_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_DAT2_PS (* (reg8 *) SD_DAT2__PS) +/* Data Register */ +#define SD_DAT2_DR (* (reg8 *) SD_DAT2__DR) +/* Port Number */ +#define SD_DAT2_PRT_NUM (* (reg8 *) SD_DAT2__PRT) +/* Connect to Analog Globals */ +#define SD_DAT2_AG (* (reg8 *) SD_DAT2__AG) +/* Analog MUX bux enable */ +#define SD_DAT2_AMUX (* (reg8 *) SD_DAT2__AMUX) +/* Bidirectional Enable */ +#define SD_DAT2_BIE (* (reg8 *) SD_DAT2__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_DAT2_BIT_MASK (* (reg8 *) SD_DAT2__BIT_MASK) +/* Bypass Enable */ +#define SD_DAT2_BYP (* (reg8 *) SD_DAT2__BYP) +/* Port wide control signals */ +#define SD_DAT2_CTL (* (reg8 *) SD_DAT2__CTL) +/* Drive Modes */ +#define SD_DAT2_DM0 (* (reg8 *) SD_DAT2__DM0) +#define SD_DAT2_DM1 (* (reg8 *) SD_DAT2__DM1) +#define SD_DAT2_DM2 (* (reg8 *) SD_DAT2__DM2) +/* Input Buffer Disable Override */ +#define SD_DAT2_INP_DIS (* (reg8 *) SD_DAT2__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_DAT2_LCD_COM_SEG (* (reg8 *) SD_DAT2__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_DAT2_LCD_EN (* (reg8 *) SD_DAT2__LCD_EN) +/* Slew Rate Control */ +#define SD_DAT2_SLW (* (reg8 *) SD_DAT2__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_DAT2_PRTDSI__CAPS_SEL (* (reg8 *) SD_DAT2__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_DAT2_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_DAT2__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_DAT2_PRTDSI__OE_SEL0 (* (reg8 *) SD_DAT2__PRTDSI__OE_SEL0) +#define SD_DAT2_PRTDSI__OE_SEL1 (* (reg8 *) SD_DAT2__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_DAT2_PRTDSI__OUT_SEL0 (* (reg8 *) SD_DAT2__PRTDSI__OUT_SEL0) +#define SD_DAT2_PRTDSI__OUT_SEL1 (* (reg8 *) SD_DAT2__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_DAT2_PRTDSI__SYNC_OUT (* (reg8 *) SD_DAT2__PRTDSI__SYNC_OUT) + + +#if defined(SD_DAT2__INTSTAT) /* Interrupt Registers */ + + #define SD_DAT2_INTSTAT (* (reg8 *) SD_DAT2__INTSTAT) + #define SD_DAT2_SNAP (* (reg8 *) SD_DAT2__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_DAT2_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2_aliases.h new file mode 100644 index 0000000..5f26214 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: SD_DAT2.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_DAT2_ALIASES_H) /* Pins SD_DAT2_ALIASES_H */ +#define CY_PINS_SD_DAT2_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_DAT2_0 SD_DAT2__0__PC + +#endif /* End Pins SD_DAT2_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c new file mode 100644 index 0000000..77538c6 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c @@ -0,0 +1,521 @@ +/******************************************************************************* +* File Name: SD_Data_Clk.c +* Version 2.0 +* +* Description: +* This file provides the source code to the API for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "SD_Data_Clk.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_Data_Clk_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_Start(void) +{ + /* Set the bit to enable the clock. */ + SD_Data_Clk_CLKEN |= SD_Data_Clk_CLKEN_MASK; + SD_Data_Clk_CLKSTBY |= SD_Data_Clk_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_Stop(void) +{ + /* Clear the bit to disable the clock. */ + SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK); + SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_Data_Clk_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_StopBlock(void) +{ + if ((SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_Data_Clk__CFG3) + CLK_DIST_AMASK = SD_Data_Clk_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_Data_Clk_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_Data_Clk__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(SD_Data_Clk_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK); + SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(SD_Data_Clk_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: SD_Data_Clk_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_StandbyPower(uint8 state) +{ + if(state == 0u) + { + SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK); + } + else + { + SD_Data_Clk_CLKSTBY |= SD_Data_Clk_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = SD_Data_Clk_GetSourceRegister(); + uint16 oldDivider = SD_Data_Clk_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider); + SD_Data_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + SD_Data_Clk_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_Data_Clk__CFG3) + CLK_DIST_AMASK = SD_Data_Clk_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_Data_Clk_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_Data_Clk__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((SD_Data_Clk_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider); + SD_Data_Clk_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 SD_Data_Clk_GetDividerRegister(void) +{ + return CY_GET_REG16(SD_Data_Clk_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_SetModeRegister(uint8 modeBitMask) +{ + SD_Data_Clk_MOD_SRC |= modeBitMask & (uint8)SD_Data_Clk_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_ClearModeRegister(uint8 modeBitMask) +{ + SD_Data_Clk_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_Data_Clk_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 SD_Data_Clk_GetModeRegister(void) +{ + return SD_Data_Clk_MOD_SRC & (uint8)(SD_Data_Clk_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = SD_Data_Clk_GetDividerRegister(); + uint8 oldSrc = SD_Data_Clk_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + SD_Data_Clk_MOD_SRC |= CYCLK_SSS; + SD_Data_Clk_MOD_SRC = + (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + SD_Data_Clk_MOD_SRC = + (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource; + SD_Data_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + SD_Data_Clk_MOD_SRC = + (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 SD_Data_Clk_GetSourceRegister(void) +{ + return SD_Data_Clk_MOD_SRC & SD_Data_Clk_SRC_SEL_MSK; +} + + +#if defined(SD_Data_Clk__CFG3) + + +/******************************************************************************* +* Function Name: SD_Data_Clk_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_SetPhaseRegister(uint8 clkPhase) +{ + SD_Data_Clk_PHASE = clkPhase & SD_Data_Clk_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 SD_Data_Clk_GetPhaseRegister(void) +{ + return SD_Data_Clk_PHASE & SD_Data_Clk_PHASE_MASK; +} + +#endif /* SD_Data_Clk__CFG3 */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h new file mode 100644 index 0000000..0ecaab6 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* File Name: SD_Data_Clk.h +* Version 2.0 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_SD_Data_Clk_H) +#define CY_CLOCK_SD_Data_Clk_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_0 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_Data_Clk_Start(void) ; +void SD_Data_Clk_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void SD_Data_Clk_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void SD_Data_Clk_StandbyPower(uint8 state) ; +void SD_Data_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 SD_Data_Clk_GetDividerRegister(void) ; +void SD_Data_Clk_SetModeRegister(uint8 modeBitMask) ; +void SD_Data_Clk_ClearModeRegister(uint8 modeBitMask) ; +uint8 SD_Data_Clk_GetModeRegister(void) ; +void SD_Data_Clk_SetSourceRegister(uint8 clkSource) ; +uint8 SD_Data_Clk_GetSourceRegister(void) ; +#if defined(SD_Data_Clk__CFG3) +void SD_Data_Clk_SetPhaseRegister(uint8 clkPhase) ; +uint8 SD_Data_Clk_GetPhaseRegister(void) ; +#endif /* defined(SD_Data_Clk__CFG3) */ + +#define SD_Data_Clk_Enable() SD_Data_Clk_Start() +#define SD_Data_Clk_Disable() SD_Data_Clk_Stop() +#define SD_Data_Clk_SetDivider(clkDivider) SD_Data_Clk_SetDividerRegister(clkDivider, 1) +#define SD_Data_Clk_SetDividerValue(clkDivider) SD_Data_Clk_SetDividerRegister((clkDivider) - 1, 1) +#define SD_Data_Clk_SetMode(clkMode) SD_Data_Clk_SetModeRegister(clkMode) +#define SD_Data_Clk_SetSource(clkSource) SD_Data_Clk_SetSourceRegister(clkSource) +#if defined(SD_Data_Clk__CFG3) +#define SD_Data_Clk_SetPhase(clkPhase) SD_Data_Clk_SetPhaseRegister(clkPhase) +#define SD_Data_Clk_SetPhaseValue(clkPhase) SD_Data_Clk_SetPhaseRegister((clkPhase) + 1) +#endif /* defined(SD_Data_Clk__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define SD_Data_Clk_CLKEN (* (reg8 *) SD_Data_Clk__PM_ACT_CFG) +#define SD_Data_Clk_CLKEN_PTR ((reg8 *) SD_Data_Clk__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define SD_Data_Clk_CLKSTBY (* (reg8 *) SD_Data_Clk__PM_STBY_CFG) +#define SD_Data_Clk_CLKSTBY_PTR ((reg8 *) SD_Data_Clk__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define SD_Data_Clk_DIV_LSB (* (reg8 *) SD_Data_Clk__CFG0) +#define SD_Data_Clk_DIV_LSB_PTR ((reg8 *) SD_Data_Clk__CFG0) +#define SD_Data_Clk_DIV_PTR ((reg16 *) SD_Data_Clk__CFG0) + +/* Clock MSB divider configuration register. */ +#define SD_Data_Clk_DIV_MSB (* (reg8 *) SD_Data_Clk__CFG1) +#define SD_Data_Clk_DIV_MSB_PTR ((reg8 *) SD_Data_Clk__CFG1) + +/* Mode and source configuration register */ +#define SD_Data_Clk_MOD_SRC (* (reg8 *) SD_Data_Clk__CFG2) +#define SD_Data_Clk_MOD_SRC_PTR ((reg8 *) SD_Data_Clk__CFG2) + +#if defined(SD_Data_Clk__CFG3) +/* Analog clock phase configuration register */ +#define SD_Data_Clk_PHASE (* (reg8 *) SD_Data_Clk__CFG3) +#define SD_Data_Clk_PHASE_PTR ((reg8 *) SD_Data_Clk__CFG3) +#endif /* defined(SD_Data_Clk__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define SD_Data_Clk_CLKEN_MASK SD_Data_Clk__PM_ACT_MSK +#define SD_Data_Clk_CLKSTBY_MASK SD_Data_Clk__PM_STBY_MSK + +/* CFG2 field masks */ +#define SD_Data_Clk_SRC_SEL_MSK SD_Data_Clk__CFG2_SRC_SEL_MASK +#define SD_Data_Clk_MODE_MASK (~(SD_Data_Clk_SRC_SEL_MSK)) + +#if defined(SD_Data_Clk__CFG3) +/* CFG3 phase mask */ +#define SD_Data_Clk_PHASE_MASK SD_Data_Clk__CFG3_PHASE_DLY_MASK +#endif /* defined(SD_Data_Clk__CFG3) */ + +#endif /* CY_CLOCK_SD_Data_Clk_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_INT.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_INT.c new file mode 100644 index 0000000..b9bb216 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_INT.c @@ -0,0 +1,189 @@ +/******************************************************************************* +* File Name: SD_INT.c +* Version 2.40 +* +* Description: +* This file provides all Interrupt Service Routine (ISR) for the SPI Master +* component. +* +* Note: +* None. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SD_PVT.h" + +/* User code required at start of ISR */ +/* `#START SD_ISR_START_DEF` */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: SD_TX_ISR +******************************************************************************** +* +* Summary: +* Interrupt Service Routine for TX portion of the SPI Master. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SD_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer. +* SD_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer, modified when exist data to +* sending and FIFO Not Full. +* SD_txBuffer[SD_TX_BUFFER_SIZE] - used to store +* data to sending. +* All described above Global variables are used when Software Buffer is used. +* +*******************************************************************************/ +CY_ISR(SD_TX_ISR) +{ + #if(SD_TX_SOFTWARE_BUF_ENABLED) + uint8 tmpStatus; + #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at start of ISR */ + /* `#START SD_TX_ISR_START` */ + + /* `#END` */ + + #if(SD_TX_SOFTWARE_BUF_ENABLED) + /* Check if TX data buffer is not empty and there is space in TX FIFO */ + while(SD_txBufferRead != SD_txBufferWrite) + { + tmpStatus = SD_GET_STATUS_TX(SD_swStatusTx); + SD_swStatusTx = tmpStatus; + + if(0u != (SD_swStatusTx & SD_STS_TX_FIFO_NOT_FULL)) + { + if(0u == SD_txBufferFull) + { + SD_txBufferRead++; + + if(SD_txBufferRead >= SD_TX_BUFFER_SIZE) + { + SD_txBufferRead = 0u; + } + } + else + { + SD_txBufferFull = 0u; + } + + /* Move data from the Buffer to the FIFO */ + CY_SET_REG8(SD_TXDATA_PTR, + SD_txBuffer[SD_txBufferRead]); + } + else + { + break; + } + } + + if(SD_txBufferRead == SD_txBufferWrite) + { + /* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */ + SD_TX_STATUS_MASK_REG &= ((uint8) ~SD_STS_TX_FIFO_NOT_FULL); + } + + #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at end of ISR (Optional) */ + /* `#START SD_TX_ISR_END` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SD_RX_ISR +******************************************************************************** +* +* Summary: +* Interrupt Service Routine for RX portion of the SPI Master. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SD_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer modified when FIFO contains +* new data. +* SD_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified when overflow occurred. +* SD_rxBuffer[SD_RX_BUFFER_SIZE] - used to store +* received data, modified when FIFO contains new data. +* All described above Global variables are used when Software Buffer is used. +* +*******************************************************************************/ +CY_ISR(SD_RX_ISR) +{ + #if(SD_RX_SOFTWARE_BUF_ENABLED) + uint8 tmpStatus; + uint8 rxData; + #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at start of ISR */ + /* `#START SD_RX_ISR_START` */ + + /* `#END` */ + + #if(SD_RX_SOFTWARE_BUF_ENABLED) + + tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx); + SD_swStatusRx = tmpStatus; + + /* Check if RX data FIFO has some data to be moved into the RX Buffer */ + while(0u != (SD_swStatusRx & SD_STS_RX_FIFO_NOT_EMPTY)) + { + rxData = CY_GET_REG8(SD_RXDATA_PTR); + + /* Set next pointer. */ + SD_rxBufferWrite++; + if(SD_rxBufferWrite >= SD_RX_BUFFER_SIZE) + { + SD_rxBufferWrite = 0u; + } + + if(SD_rxBufferWrite == SD_rxBufferRead) + { + SD_rxBufferRead++; + if(SD_rxBufferRead >= SD_RX_BUFFER_SIZE) + { + SD_rxBufferRead = 0u; + } + + SD_rxBufferFull = 1u; + } + + /* Move data from the FIFO to the Buffer */ + SD_rxBuffer[SD_rxBufferWrite] = rxData; + + tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx); + SD_swStatusRx = tmpStatus; + } + + #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at end of ISR (Optional) */ + /* `#START SD_RX_ISR_END` */ + + /* `#END` */ +} + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c new file mode 100644 index 0000000..c893ef0 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c @@ -0,0 +1,521 @@ +/******************************************************************************* +* File Name: SD_Init_Clk.c +* Version 2.0 +* +* Description: +* This file provides the source code to the API for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "SD_Init_Clk.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_Init_Clk_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_Start(void) +{ + /* Set the bit to enable the clock. */ + SD_Init_Clk_CLKEN |= SD_Init_Clk_CLKEN_MASK; + SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_Stop(void) +{ + /* Clear the bit to disable the clock. */ + SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK); + SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_Init_Clk_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_StopBlock(void) +{ + if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_Init_Clk__CFG3) + CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_Init_Clk__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(SD_Init_Clk_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK); + SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(SD_Init_Clk_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: SD_Init_Clk_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_StandbyPower(uint8 state) +{ + if(state == 0u) + { + SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK); + } + else + { + SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = SD_Init_Clk_GetSourceRegister(); + uint16 oldDivider = SD_Init_Clk_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider); + SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + SD_Init_Clk_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_Init_Clk__CFG3) + CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_Init_Clk__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((SD_Init_Clk_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider); + SD_Init_Clk_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 SD_Init_Clk_GetDividerRegister(void) +{ + return CY_GET_REG16(SD_Init_Clk_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) +{ + SD_Init_Clk_MOD_SRC |= modeBitMask & (uint8)SD_Init_Clk_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) +{ + SD_Init_Clk_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_Init_Clk_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 SD_Init_Clk_GetModeRegister(void) +{ + return SD_Init_Clk_MOD_SRC & (uint8)(SD_Init_Clk_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = SD_Init_Clk_GetDividerRegister(); + uint8 oldSrc = SD_Init_Clk_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + SD_Init_Clk_MOD_SRC |= CYCLK_SSS; + SD_Init_Clk_MOD_SRC = + (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + SD_Init_Clk_MOD_SRC = + (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource; + SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + SD_Init_Clk_MOD_SRC = + (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 SD_Init_Clk_GetSourceRegister(void) +{ + return SD_Init_Clk_MOD_SRC & SD_Init_Clk_SRC_SEL_MSK; +} + + +#if defined(SD_Init_Clk__CFG3) + + +/******************************************************************************* +* Function Name: SD_Init_Clk_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) +{ + SD_Init_Clk_PHASE = clkPhase & SD_Init_Clk_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 SD_Init_Clk_GetPhaseRegister(void) +{ + return SD_Init_Clk_PHASE & SD_Init_Clk_PHASE_MASK; +} + +#endif /* SD_Init_Clk__CFG3 */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h new file mode 100644 index 0000000..04adc2a --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* File Name: SD_Init_Clk.h +* Version 2.0 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_SD_Init_Clk_H) +#define CY_CLOCK_SD_Init_Clk_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_0 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_Init_Clk_Start(void) ; +void SD_Init_Clk_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void SD_Init_Clk_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void SD_Init_Clk_StandbyPower(uint8 state) ; +void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 SD_Init_Clk_GetDividerRegister(void) ; +void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) ; +void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) ; +uint8 SD_Init_Clk_GetModeRegister(void) ; +void SD_Init_Clk_SetSourceRegister(uint8 clkSource) ; +uint8 SD_Init_Clk_GetSourceRegister(void) ; +#if defined(SD_Init_Clk__CFG3) +void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) ; +uint8 SD_Init_Clk_GetPhaseRegister(void) ; +#endif /* defined(SD_Init_Clk__CFG3) */ + +#define SD_Init_Clk_Enable() SD_Init_Clk_Start() +#define SD_Init_Clk_Disable() SD_Init_Clk_Stop() +#define SD_Init_Clk_SetDivider(clkDivider) SD_Init_Clk_SetDividerRegister(clkDivider, 1) +#define SD_Init_Clk_SetDividerValue(clkDivider) SD_Init_Clk_SetDividerRegister((clkDivider) - 1, 1) +#define SD_Init_Clk_SetMode(clkMode) SD_Init_Clk_SetModeRegister(clkMode) +#define SD_Init_Clk_SetSource(clkSource) SD_Init_Clk_SetSourceRegister(clkSource) +#if defined(SD_Init_Clk__CFG3) +#define SD_Init_Clk_SetPhase(clkPhase) SD_Init_Clk_SetPhaseRegister(clkPhase) +#define SD_Init_Clk_SetPhaseValue(clkPhase) SD_Init_Clk_SetPhaseRegister((clkPhase) + 1) +#endif /* defined(SD_Init_Clk__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define SD_Init_Clk_CLKEN (* (reg8 *) SD_Init_Clk__PM_ACT_CFG) +#define SD_Init_Clk_CLKEN_PTR ((reg8 *) SD_Init_Clk__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define SD_Init_Clk_CLKSTBY (* (reg8 *) SD_Init_Clk__PM_STBY_CFG) +#define SD_Init_Clk_CLKSTBY_PTR ((reg8 *) SD_Init_Clk__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define SD_Init_Clk_DIV_LSB (* (reg8 *) SD_Init_Clk__CFG0) +#define SD_Init_Clk_DIV_LSB_PTR ((reg8 *) SD_Init_Clk__CFG0) +#define SD_Init_Clk_DIV_PTR ((reg16 *) SD_Init_Clk__CFG0) + +/* Clock MSB divider configuration register. */ +#define SD_Init_Clk_DIV_MSB (* (reg8 *) SD_Init_Clk__CFG1) +#define SD_Init_Clk_DIV_MSB_PTR ((reg8 *) SD_Init_Clk__CFG1) + +/* Mode and source configuration register */ +#define SD_Init_Clk_MOD_SRC (* (reg8 *) SD_Init_Clk__CFG2) +#define SD_Init_Clk_MOD_SRC_PTR ((reg8 *) SD_Init_Clk__CFG2) + +#if defined(SD_Init_Clk__CFG3) +/* Analog clock phase configuration register */ +#define SD_Init_Clk_PHASE (* (reg8 *) SD_Init_Clk__CFG3) +#define SD_Init_Clk_PHASE_PTR ((reg8 *) SD_Init_Clk__CFG3) +#endif /* defined(SD_Init_Clk__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define SD_Init_Clk_CLKEN_MASK SD_Init_Clk__PM_ACT_MSK +#define SD_Init_Clk_CLKSTBY_MASK SD_Init_Clk__PM_STBY_MSK + +/* CFG2 field masks */ +#define SD_Init_Clk_SRC_SEL_MSK SD_Init_Clk__CFG2_SRC_SEL_MASK +#define SD_Init_Clk_MODE_MASK (~(SD_Init_Clk_SRC_SEL_MSK)) + +#if defined(SD_Init_Clk__CFG3) +/* CFG3 phase mask */ +#define SD_Init_Clk_PHASE_MASK SD_Init_Clk__CFG3_PHASE_DLY_MASK +#endif /* defined(SD_Init_Clk__CFG3) */ + +#endif /* CY_CLOCK_SD_Init_Clk_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.c new file mode 100644 index 0000000..8848744 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.c @@ -0,0 +1,521 @@ +/******************************************************************************* +* File Name: SD_IntClock.c +* Version 2.0 +* +* Description: +* This file provides the source code to the API for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "SD_IntClock.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_IntClock_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_IntClock_Start(void) +{ + /* Set the bit to enable the clock. */ + SD_IntClock_CLKEN |= SD_IntClock_CLKEN_MASK; + SD_IntClock_CLKSTBY |= SD_IntClock_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: SD_IntClock_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_IntClock_Stop(void) +{ + /* Clear the bit to disable the clock. */ + SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK); + SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_IntClock_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_IntClock_StopBlock(void) +{ + if ((SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_IntClock__CFG3) + CLK_DIST_AMASK = SD_IntClock_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_IntClock_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_IntClock__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(SD_IntClock_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK); + SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(SD_IntClock_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: SD_IntClock_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_IntClock_StandbyPower(uint8 state) +{ + if(state == 0u) + { + SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK); + } + else + { + SD_IntClock_CLKSTBY |= SD_IntClock_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: SD_IntClock_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_IntClock_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = SD_IntClock_GetSourceRegister(); + uint16 oldDivider = SD_IntClock_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider); + SD_IntClock_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + SD_IntClock_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_IntClock__CFG3) + CLK_DIST_AMASK = SD_IntClock_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_IntClock_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_IntClock__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((SD_IntClock_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider); + SD_IntClock_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: SD_IntClock_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 SD_IntClock_GetDividerRegister(void) +{ + return CY_GET_REG16(SD_IntClock_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: SD_IntClock_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_IntClock_SetModeRegister(uint8 modeBitMask) +{ + SD_IntClock_MOD_SRC |= modeBitMask & (uint8)SD_IntClock_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_IntClock_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_IntClock_ClearModeRegister(uint8 modeBitMask) +{ + SD_IntClock_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_IntClock_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: SD_IntClock_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 SD_IntClock_GetModeRegister(void) +{ + return SD_IntClock_MOD_SRC & (uint8)(SD_IntClock_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: SD_IntClock_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_IntClock_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = SD_IntClock_GetDividerRegister(); + uint8 oldSrc = SD_IntClock_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + SD_IntClock_MOD_SRC |= CYCLK_SSS; + SD_IntClock_MOD_SRC = + (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + SD_IntClock_MOD_SRC = + (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource; + SD_IntClock_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + SD_IntClock_MOD_SRC = + (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: SD_IntClock_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 SD_IntClock_GetSourceRegister(void) +{ + return SD_IntClock_MOD_SRC & SD_IntClock_SRC_SEL_MSK; +} + + +#if defined(SD_IntClock__CFG3) + + +/******************************************************************************* +* Function Name: SD_IntClock_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_IntClock_SetPhaseRegister(uint8 clkPhase) +{ + SD_IntClock_PHASE = clkPhase & SD_IntClock_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_IntClock_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 SD_IntClock_GetPhaseRegister(void) +{ + return SD_IntClock_PHASE & SD_IntClock_PHASE_MASK; +} + +#endif /* SD_IntClock__CFG3 */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.h new file mode 100644 index 0000000..df76982 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* File Name: SD_IntClock.h +* Version 2.0 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_SD_IntClock_H) +#define CY_CLOCK_SD_IntClock_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_0 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_IntClock_Start(void) ; +void SD_IntClock_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void SD_IntClock_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void SD_IntClock_StandbyPower(uint8 state) ; +void SD_IntClock_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 SD_IntClock_GetDividerRegister(void) ; +void SD_IntClock_SetModeRegister(uint8 modeBitMask) ; +void SD_IntClock_ClearModeRegister(uint8 modeBitMask) ; +uint8 SD_IntClock_GetModeRegister(void) ; +void SD_IntClock_SetSourceRegister(uint8 clkSource) ; +uint8 SD_IntClock_GetSourceRegister(void) ; +#if defined(SD_IntClock__CFG3) +void SD_IntClock_SetPhaseRegister(uint8 clkPhase) ; +uint8 SD_IntClock_GetPhaseRegister(void) ; +#endif /* defined(SD_IntClock__CFG3) */ + +#define SD_IntClock_Enable() SD_IntClock_Start() +#define SD_IntClock_Disable() SD_IntClock_Stop() +#define SD_IntClock_SetDivider(clkDivider) SD_IntClock_SetDividerRegister(clkDivider, 1) +#define SD_IntClock_SetDividerValue(clkDivider) SD_IntClock_SetDividerRegister((clkDivider) - 1, 1) +#define SD_IntClock_SetMode(clkMode) SD_IntClock_SetModeRegister(clkMode) +#define SD_IntClock_SetSource(clkSource) SD_IntClock_SetSourceRegister(clkSource) +#if defined(SD_IntClock__CFG3) +#define SD_IntClock_SetPhase(clkPhase) SD_IntClock_SetPhaseRegister(clkPhase) +#define SD_IntClock_SetPhaseValue(clkPhase) SD_IntClock_SetPhaseRegister((clkPhase) + 1) +#endif /* defined(SD_IntClock__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define SD_IntClock_CLKEN (* (reg8 *) SD_IntClock__PM_ACT_CFG) +#define SD_IntClock_CLKEN_PTR ((reg8 *) SD_IntClock__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define SD_IntClock_CLKSTBY (* (reg8 *) SD_IntClock__PM_STBY_CFG) +#define SD_IntClock_CLKSTBY_PTR ((reg8 *) SD_IntClock__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define SD_IntClock_DIV_LSB (* (reg8 *) SD_IntClock__CFG0) +#define SD_IntClock_DIV_LSB_PTR ((reg8 *) SD_IntClock__CFG0) +#define SD_IntClock_DIV_PTR ((reg16 *) SD_IntClock__CFG0) + +/* Clock MSB divider configuration register. */ +#define SD_IntClock_DIV_MSB (* (reg8 *) SD_IntClock__CFG1) +#define SD_IntClock_DIV_MSB_PTR ((reg8 *) SD_IntClock__CFG1) + +/* Mode and source configuration register */ +#define SD_IntClock_MOD_SRC (* (reg8 *) SD_IntClock__CFG2) +#define SD_IntClock_MOD_SRC_PTR ((reg8 *) SD_IntClock__CFG2) + +#if defined(SD_IntClock__CFG3) +/* Analog clock phase configuration register */ +#define SD_IntClock_PHASE (* (reg8 *) SD_IntClock__CFG3) +#define SD_IntClock_PHASE_PTR ((reg8 *) SD_IntClock__CFG3) +#endif /* defined(SD_IntClock__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define SD_IntClock_CLKEN_MASK SD_IntClock__PM_ACT_MSK +#define SD_IntClock_CLKSTBY_MASK SD_IntClock__PM_STBY_MSK + +/* CFG2 field masks */ +#define SD_IntClock_SRC_SEL_MSK SD_IntClock__CFG2_SRC_SEL_MASK +#define SD_IntClock_MODE_MASK (~(SD_IntClock_SRC_SEL_MSK)) + +#if defined(SD_IntClock__CFG3) +/* CFG3 phase mask */ +#define SD_IntClock_PHASE_MASK SD_IntClock__CFG3_PHASE_DLY_MASK +#endif /* defined(SD_IntClock__CFG3) */ + +#endif /* CY_CLOCK_SD_IntClock_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c new file mode 100644 index 0000000..5a3ec62 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SD_MISO.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_MISO.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_MISO_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_MISO_Write(uint8 value) +{ + uint8 staticBits = (SD_MISO_DR & (uint8)(~SD_MISO_MASK)); + SD_MISO_DR = staticBits | ((uint8)(value << SD_MISO_SHIFT) & SD_MISO_MASK); +} + + +/******************************************************************************* +* Function Name: SD_MISO_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_MISO_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_MISO_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_MISO_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_MISO_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_MISO_Read(void) +{ + return (SD_MISO_PS & SD_MISO_MASK) >> SD_MISO_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_MISO_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_MISO_ReadDataReg(void) +{ + return (SD_MISO_DR & SD_MISO_MASK) >> SD_MISO_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_MISO_INTSTAT) + + /******************************************************************************* + * Function Name: SD_MISO_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_MISO_ClearInterrupt(void) + { + return (SD_MISO_INTSTAT & SD_MISO_MASK) >> SD_MISO_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h new file mode 100644 index 0000000..e36fa07 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_MISO.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_MISO_H) /* Pins SD_MISO_H */ +#define CY_PINS_SD_MISO_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_MISO_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_MISO_Write(uint8 value) ; +void SD_MISO_SetDriveMode(uint8 mode) ; +uint8 SD_MISO_ReadDataReg(void) ; +uint8 SD_MISO_Read(void) ; +uint8 SD_MISO_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_MISO_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_MISO_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_MISO_DM_RES_UP PIN_DM_RES_UP +#define SD_MISO_DM_RES_DWN PIN_DM_RES_DWN +#define SD_MISO_DM_OD_LO PIN_DM_OD_LO +#define SD_MISO_DM_OD_HI PIN_DM_OD_HI +#define SD_MISO_DM_STRONG PIN_DM_STRONG +#define SD_MISO_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_MISO_MASK SD_MISO__MASK +#define SD_MISO_SHIFT SD_MISO__SHIFT +#define SD_MISO_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_MISO_PS (* (reg8 *) SD_MISO__PS) +/* Data Register */ +#define SD_MISO_DR (* (reg8 *) SD_MISO__DR) +/* Port Number */ +#define SD_MISO_PRT_NUM (* (reg8 *) SD_MISO__PRT) +/* Connect to Analog Globals */ +#define SD_MISO_AG (* (reg8 *) SD_MISO__AG) +/* Analog MUX bux enable */ +#define SD_MISO_AMUX (* (reg8 *) SD_MISO__AMUX) +/* Bidirectional Enable */ +#define SD_MISO_BIE (* (reg8 *) SD_MISO__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_MISO_BIT_MASK (* (reg8 *) SD_MISO__BIT_MASK) +/* Bypass Enable */ +#define SD_MISO_BYP (* (reg8 *) SD_MISO__BYP) +/* Port wide control signals */ +#define SD_MISO_CTL (* (reg8 *) SD_MISO__CTL) +/* Drive Modes */ +#define SD_MISO_DM0 (* (reg8 *) SD_MISO__DM0) +#define SD_MISO_DM1 (* (reg8 *) SD_MISO__DM1) +#define SD_MISO_DM2 (* (reg8 *) SD_MISO__DM2) +/* Input Buffer Disable Override */ +#define SD_MISO_INP_DIS (* (reg8 *) SD_MISO__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_MISO_LCD_COM_SEG (* (reg8 *) SD_MISO__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_MISO_LCD_EN (* (reg8 *) SD_MISO__LCD_EN) +/* Slew Rate Control */ +#define SD_MISO_SLW (* (reg8 *) SD_MISO__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_MISO_PRTDSI__CAPS_SEL (* (reg8 *) SD_MISO__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_MISO_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_MISO__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_MISO_PRTDSI__OE_SEL0 (* (reg8 *) SD_MISO__PRTDSI__OE_SEL0) +#define SD_MISO_PRTDSI__OE_SEL1 (* (reg8 *) SD_MISO__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_MISO_PRTDSI__OUT_SEL0 (* (reg8 *) SD_MISO__PRTDSI__OUT_SEL0) +#define SD_MISO_PRTDSI__OUT_SEL1 (* (reg8 *) SD_MISO__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_MISO_PRTDSI__SYNC_OUT (* (reg8 *) SD_MISO__PRTDSI__SYNC_OUT) + + +#if defined(SD_MISO__INTSTAT) /* Interrupt Registers */ + + #define SD_MISO_INTSTAT (* (reg8 *) SD_MISO__INTSTAT) + #define SD_MISO_SNAP (* (reg8 *) SD_MISO__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_MISO_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h new file mode 100644 index 0000000..78313af --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: SD_MISO.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_MISO_ALIASES_H) /* Pins SD_MISO_ALIASES_H */ +#define CY_PINS_SD_MISO_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_MISO_0 SD_MISO__0__PC + +#endif /* End Pins SD_MISO_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c new file mode 100644 index 0000000..7986406 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SD_MOSI.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_MOSI.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_MOSI_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_MOSI_Write(uint8 value) +{ + uint8 staticBits = (SD_MOSI_DR & (uint8)(~SD_MOSI_MASK)); + SD_MOSI_DR = staticBits | ((uint8)(value << SD_MOSI_SHIFT) & SD_MOSI_MASK); +} + + +/******************************************************************************* +* Function Name: SD_MOSI_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_MOSI_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_MOSI_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_MOSI_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_MOSI_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_MOSI_Read(void) +{ + return (SD_MOSI_PS & SD_MOSI_MASK) >> SD_MOSI_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_MOSI_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_MOSI_ReadDataReg(void) +{ + return (SD_MOSI_DR & SD_MOSI_MASK) >> SD_MOSI_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_MOSI_INTSTAT) + + /******************************************************************************* + * Function Name: SD_MOSI_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_MOSI_ClearInterrupt(void) + { + return (SD_MOSI_INTSTAT & SD_MOSI_MASK) >> SD_MOSI_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h new file mode 100644 index 0000000..54a0ded --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_MOSI.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_MOSI_H) /* Pins SD_MOSI_H */ +#define CY_PINS_SD_MOSI_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_MOSI_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_MOSI_Write(uint8 value) ; +void SD_MOSI_SetDriveMode(uint8 mode) ; +uint8 SD_MOSI_ReadDataReg(void) ; +uint8 SD_MOSI_Read(void) ; +uint8 SD_MOSI_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_MOSI_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_MOSI_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_MOSI_DM_RES_UP PIN_DM_RES_UP +#define SD_MOSI_DM_RES_DWN PIN_DM_RES_DWN +#define SD_MOSI_DM_OD_LO PIN_DM_OD_LO +#define SD_MOSI_DM_OD_HI PIN_DM_OD_HI +#define SD_MOSI_DM_STRONG PIN_DM_STRONG +#define SD_MOSI_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_MOSI_MASK SD_MOSI__MASK +#define SD_MOSI_SHIFT SD_MOSI__SHIFT +#define SD_MOSI_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_MOSI_PS (* (reg8 *) SD_MOSI__PS) +/* Data Register */ +#define SD_MOSI_DR (* (reg8 *) SD_MOSI__DR) +/* Port Number */ +#define SD_MOSI_PRT_NUM (* (reg8 *) SD_MOSI__PRT) +/* Connect to Analog Globals */ +#define SD_MOSI_AG (* (reg8 *) SD_MOSI__AG) +/* Analog MUX bux enable */ +#define SD_MOSI_AMUX (* (reg8 *) SD_MOSI__AMUX) +/* Bidirectional Enable */ +#define SD_MOSI_BIE (* (reg8 *) SD_MOSI__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_MOSI_BIT_MASK (* (reg8 *) SD_MOSI__BIT_MASK) +/* Bypass Enable */ +#define SD_MOSI_BYP (* (reg8 *) SD_MOSI__BYP) +/* Port wide control signals */ +#define SD_MOSI_CTL (* (reg8 *) SD_MOSI__CTL) +/* Drive Modes */ +#define SD_MOSI_DM0 (* (reg8 *) SD_MOSI__DM0) +#define SD_MOSI_DM1 (* (reg8 *) SD_MOSI__DM1) +#define SD_MOSI_DM2 (* (reg8 *) SD_MOSI__DM2) +/* Input Buffer Disable Override */ +#define SD_MOSI_INP_DIS (* (reg8 *) SD_MOSI__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_MOSI_LCD_COM_SEG (* (reg8 *) SD_MOSI__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_MOSI_LCD_EN (* (reg8 *) SD_MOSI__LCD_EN) +/* Slew Rate Control */ +#define SD_MOSI_SLW (* (reg8 *) SD_MOSI__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_MOSI_PRTDSI__CAPS_SEL (* (reg8 *) SD_MOSI__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_MOSI_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_MOSI__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_MOSI_PRTDSI__OE_SEL0 (* (reg8 *) SD_MOSI__PRTDSI__OE_SEL0) +#define SD_MOSI_PRTDSI__OE_SEL1 (* (reg8 *) SD_MOSI__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_MOSI_PRTDSI__OUT_SEL0 (* (reg8 *) SD_MOSI__PRTDSI__OUT_SEL0) +#define SD_MOSI_PRTDSI__OUT_SEL1 (* (reg8 *) SD_MOSI__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_MOSI_PRTDSI__SYNC_OUT (* (reg8 *) SD_MOSI__PRTDSI__SYNC_OUT) + + +#if defined(SD_MOSI__INTSTAT) /* Interrupt Registers */ + + #define SD_MOSI_INTSTAT (* (reg8 *) SD_MOSI__INTSTAT) + #define SD_MOSI_SNAP (* (reg8 *) SD_MOSI__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_MOSI_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h new file mode 100644 index 0000000..1cf2c44 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: SD_MOSI.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_MOSI_ALIASES_H) /* Pins SD_MOSI_ALIASES_H */ +#define CY_PINS_SD_MOSI_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_MOSI_0 SD_MOSI__0__PC + +#endif /* End Pins SD_MOSI_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PM.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PM.c new file mode 100644 index 0000000..d2388e6 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PM.c @@ -0,0 +1,180 @@ +/******************************************************************************* +* File Name: SD_PM.c +* Version 2.40 +* +* Description: +* This file contains the setup, control and status commands to support +* component operations in low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SD_PVT.h" + +static SD_BACKUP_STRUCT SD_backup = +{ + SD_DISABLED, + SD_BITCTR_INIT, + #if(CY_UDB_V0) + SD_TX_INIT_INTERRUPTS_MASK, + SD_RX_INIT_INTERRUPTS_MASK + #endif /* CY_UDB_V0 */ +}; + + +/******************************************************************************* +* Function Name: SD_SaveConfig +******************************************************************************** +* +* Summary: +* Saves SPIM configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SD_backup - modified when non-retention registers are saved. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SD_SaveConfig(void) +{ + /* Store Status Mask registers */ + #if(CY_UDB_V0) + SD_backup.cntrPeriod = SD_COUNTER_PERIOD_REG; + SD_backup.saveSrTxIntMask = SD_TX_STATUS_MASK_REG; + SD_backup.saveSrRxIntMask = SD_RX_STATUS_MASK_REG; + #endif /* (CY_UDB_V0) */ +} + + +/******************************************************************************* +* Function Name: SD_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores SPIM configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SD_backup - used when non-retention registers are restored. +* +* Side Effects: +* If this API is called without first calling SaveConfig then in the following +* registers will be default values from Customizer: +* SD_STATUS_MASK_REG and SD_COUNTER_PERIOD_REG. +* +*******************************************************************************/ +void SD_RestoreConfig(void) +{ + /* Restore the data, saved by SaveConfig() function */ + #if(CY_UDB_V0) + SD_COUNTER_PERIOD_REG = SD_backup.cntrPeriod; + SD_TX_STATUS_MASK_REG = ((uint8) SD_backup.saveSrTxIntMask); + SD_RX_STATUS_MASK_REG = ((uint8) SD_backup.saveSrRxIntMask); + #endif /* (CY_UDB_V0) */ +} + + +/******************************************************************************* +* Function Name: SD_Sleep +******************************************************************************** +* +* Summary: +* Prepare SPIM Component goes to sleep. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SD_backup - modified when non-retention registers are saved. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SD_Sleep(void) +{ + /* Save components enable state */ + SD_backup.enableState = ((uint8) SD_IS_ENABLED); + + SD_Stop(); + SD_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: SD_Wakeup +******************************************************************************** +* +* Summary: +* Prepare SPIM Component to wake up. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SD_backup - used when non-retention registers are restored. +* SD_txBufferWrite - modified every function call - resets to +* zero. +* SD_txBufferRead - modified every function call - resets to +* zero. +* SD_rxBufferWrite - modified every function call - resets to +* zero. +* SD_rxBufferRead - modified every function call - resets to +* zero. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SD_Wakeup(void) +{ + SD_RestoreConfig(); + + #if(SD_RX_SOFTWARE_BUF_ENABLED) + SD_rxBufferFull = 0u; + SD_rxBufferRead = 0u; + SD_rxBufferWrite = 0u; + #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */ + + #if(SD_TX_SOFTWARE_BUF_ENABLED) + SD_txBufferFull = 0u; + SD_txBufferRead = 0u; + SD_txBufferWrite = 0u; + #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */ + + /* Clear any data from the RX and TX FIFO */ + SD_ClearFIFO(); + + /* Restore components block enable state */ + if(0u != SD_backup.enableState) + { + SD_Enable(); + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PVT.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PVT.h new file mode 100644 index 0000000..cadc78e --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PVT.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: .h +* Version 2.40 +* +* Description: +* This private header file contains internal definitions for the SPIM +* component. Do not use these definitions directly in your application. +* +* Note: +* +******************************************************************************** +* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SPIM_PVT_SD_H) +#define CY_SPIM_PVT_SD_H + +#include "SD.h" + + +/********************************** +* Functions with external linkage +**********************************/ + + +/********************************** +* Variables with external linkage +**********************************/ + +extern volatile uint8 SD_swStatusTx; +extern volatile uint8 SD_swStatusRx; + +#if(SD_TX_SOFTWARE_BUF_ENABLED) + extern volatile uint8 SD_txBuffer[SD_TX_BUFFER_SIZE]; + extern volatile uint8 SD_txBufferRead; + extern volatile uint8 SD_txBufferWrite; + extern volatile uint8 SD_txBufferFull; +#endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */ + +#if(SD_RX_SOFTWARE_BUF_ENABLED) + extern volatile uint8 SD_rxBuffer[SD_RX_BUFFER_SIZE]; + extern volatile uint8 SD_rxBufferRead; + extern volatile uint8 SD_rxBufferWrite; + extern volatile uint8 SD_rxBufferFull; +#endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */ + +#endif /* CY_SPIM_PVT_SD_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c new file mode 100644 index 0000000..d592236 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SD_SCK.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_SCK.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_SCK_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_SCK_Write(uint8 value) +{ + uint8 staticBits = (SD_SCK_DR & (uint8)(~SD_SCK_MASK)); + SD_SCK_DR = staticBits | ((uint8)(value << SD_SCK_SHIFT) & SD_SCK_MASK); +} + + +/******************************************************************************* +* Function Name: SD_SCK_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_SCK_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_SCK_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_SCK_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_SCK_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_SCK_Read(void) +{ + return (SD_SCK_PS & SD_SCK_MASK) >> SD_SCK_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_SCK_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_SCK_ReadDataReg(void) +{ + return (SD_SCK_DR & SD_SCK_MASK) >> SD_SCK_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_SCK_INTSTAT) + + /******************************************************************************* + * Function Name: SD_SCK_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_SCK_ClearInterrupt(void) + { + return (SD_SCK_INTSTAT & SD_SCK_MASK) >> SD_SCK_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h new file mode 100644 index 0000000..a4a9351 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_SCK.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_SCK_H) /* Pins SD_SCK_H */ +#define CY_PINS_SD_SCK_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_SCK_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_SCK_Write(uint8 value) ; +void SD_SCK_SetDriveMode(uint8 mode) ; +uint8 SD_SCK_ReadDataReg(void) ; +uint8 SD_SCK_Read(void) ; +uint8 SD_SCK_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_SCK_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_SCK_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_SCK_DM_RES_UP PIN_DM_RES_UP +#define SD_SCK_DM_RES_DWN PIN_DM_RES_DWN +#define SD_SCK_DM_OD_LO PIN_DM_OD_LO +#define SD_SCK_DM_OD_HI PIN_DM_OD_HI +#define SD_SCK_DM_STRONG PIN_DM_STRONG +#define SD_SCK_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_SCK_MASK SD_SCK__MASK +#define SD_SCK_SHIFT SD_SCK__SHIFT +#define SD_SCK_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_SCK_PS (* (reg8 *) SD_SCK__PS) +/* Data Register */ +#define SD_SCK_DR (* (reg8 *) SD_SCK__DR) +/* Port Number */ +#define SD_SCK_PRT_NUM (* (reg8 *) SD_SCK__PRT) +/* Connect to Analog Globals */ +#define SD_SCK_AG (* (reg8 *) SD_SCK__AG) +/* Analog MUX bux enable */ +#define SD_SCK_AMUX (* (reg8 *) SD_SCK__AMUX) +/* Bidirectional Enable */ +#define SD_SCK_BIE (* (reg8 *) SD_SCK__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_SCK_BIT_MASK (* (reg8 *) SD_SCK__BIT_MASK) +/* Bypass Enable */ +#define SD_SCK_BYP (* (reg8 *) SD_SCK__BYP) +/* Port wide control signals */ +#define SD_SCK_CTL (* (reg8 *) SD_SCK__CTL) +/* Drive Modes */ +#define SD_SCK_DM0 (* (reg8 *) SD_SCK__DM0) +#define SD_SCK_DM1 (* (reg8 *) SD_SCK__DM1) +#define SD_SCK_DM2 (* (reg8 *) SD_SCK__DM2) +/* Input Buffer Disable Override */ +#define SD_SCK_INP_DIS (* (reg8 *) SD_SCK__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_SCK_LCD_COM_SEG (* (reg8 *) SD_SCK__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_SCK_LCD_EN (* (reg8 *) SD_SCK__LCD_EN) +/* Slew Rate Control */ +#define SD_SCK_SLW (* (reg8 *) SD_SCK__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_SCK_PRTDSI__CAPS_SEL (* (reg8 *) SD_SCK__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_SCK_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_SCK__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_SCK_PRTDSI__OE_SEL0 (* (reg8 *) SD_SCK__PRTDSI__OE_SEL0) +#define SD_SCK_PRTDSI__OE_SEL1 (* (reg8 *) SD_SCK__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_SCK_PRTDSI__OUT_SEL0 (* (reg8 *) SD_SCK__PRTDSI__OUT_SEL0) +#define SD_SCK_PRTDSI__OUT_SEL1 (* (reg8 *) SD_SCK__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_SCK_PRTDSI__SYNC_OUT (* (reg8 *) SD_SCK__PRTDSI__SYNC_OUT) + + +#if defined(SD_SCK__INTSTAT) /* Interrupt Registers */ + + #define SD_SCK_INTSTAT (* (reg8 *) SD_SCK__INTSTAT) + #define SD_SCK_SNAP (* (reg8 *) SD_SCK__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_SCK_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h new file mode 100644 index 0000000..93890ac --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: SD_SCK.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_SCK_ALIASES_H) /* Pins SD_SCK_ALIASES_H */ +#define CY_PINS_SD_SCK_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_SCK_0 SD_SCK__0__PC + +#endif /* End Pins SD_SCK_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_WP.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_WP.c new file mode 100644 index 0000000..136473c --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_WP.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SD_WP.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_WP.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_WP__PORT == 15 && ((SD_WP__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_WP_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_WP_Write(uint8 value) +{ + uint8 staticBits = (SD_WP_DR & (uint8)(~SD_WP_MASK)); + SD_WP_DR = staticBits | ((uint8)(value << SD_WP_SHIFT) & SD_WP_MASK); +} + + +/******************************************************************************* +* Function Name: SD_WP_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_WP_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_WP_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_WP_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_WP_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_WP_Read(void) +{ + return (SD_WP_PS & SD_WP_MASK) >> SD_WP_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_WP_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_WP_ReadDataReg(void) +{ + return (SD_WP_DR & SD_WP_MASK) >> SD_WP_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_WP_INTSTAT) + + /******************************************************************************* + * Function Name: SD_WP_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_WP_ClearInterrupt(void) + { + return (SD_WP_INTSTAT & SD_WP_MASK) >> SD_WP_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_WP.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_WP.h new file mode 100644 index 0000000..368e2f6 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_WP.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_WP.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_WP_H) /* Pins SD_WP_H */ +#define CY_PINS_SD_WP_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_WP_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_WP__PORT == 15 && ((SD_WP__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_WP_Write(uint8 value) ; +void SD_WP_SetDriveMode(uint8 mode) ; +uint8 SD_WP_ReadDataReg(void) ; +uint8 SD_WP_Read(void) ; +uint8 SD_WP_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_WP_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_WP_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_WP_DM_RES_UP PIN_DM_RES_UP +#define SD_WP_DM_RES_DWN PIN_DM_RES_DWN +#define SD_WP_DM_OD_LO PIN_DM_OD_LO +#define SD_WP_DM_OD_HI PIN_DM_OD_HI +#define SD_WP_DM_STRONG PIN_DM_STRONG +#define SD_WP_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_WP_MASK SD_WP__MASK +#define SD_WP_SHIFT SD_WP__SHIFT +#define SD_WP_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_WP_PS (* (reg8 *) SD_WP__PS) +/* Data Register */ +#define SD_WP_DR (* (reg8 *) SD_WP__DR) +/* Port Number */ +#define SD_WP_PRT_NUM (* (reg8 *) SD_WP__PRT) +/* Connect to Analog Globals */ +#define SD_WP_AG (* (reg8 *) SD_WP__AG) +/* Analog MUX bux enable */ +#define SD_WP_AMUX (* (reg8 *) SD_WP__AMUX) +/* Bidirectional Enable */ +#define SD_WP_BIE (* (reg8 *) SD_WP__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_WP_BIT_MASK (* (reg8 *) SD_WP__BIT_MASK) +/* Bypass Enable */ +#define SD_WP_BYP (* (reg8 *) SD_WP__BYP) +/* Port wide control signals */ +#define SD_WP_CTL (* (reg8 *) SD_WP__CTL) +/* Drive Modes */ +#define SD_WP_DM0 (* (reg8 *) SD_WP__DM0) +#define SD_WP_DM1 (* (reg8 *) SD_WP__DM1) +#define SD_WP_DM2 (* (reg8 *) SD_WP__DM2) +/* Input Buffer Disable Override */ +#define SD_WP_INP_DIS (* (reg8 *) SD_WP__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_WP_LCD_COM_SEG (* (reg8 *) SD_WP__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_WP_LCD_EN (* (reg8 *) SD_WP__LCD_EN) +/* Slew Rate Control */ +#define SD_WP_SLW (* (reg8 *) SD_WP__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_WP_PRTDSI__CAPS_SEL (* (reg8 *) SD_WP__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_WP_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_WP__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_WP_PRTDSI__OE_SEL0 (* (reg8 *) SD_WP__PRTDSI__OE_SEL0) +#define SD_WP_PRTDSI__OE_SEL1 (* (reg8 *) SD_WP__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_WP_PRTDSI__OUT_SEL0 (* (reg8 *) SD_WP__PRTDSI__OUT_SEL0) +#define SD_WP_PRTDSI__OUT_SEL1 (* (reg8 *) SD_WP__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_WP_PRTDSI__SYNC_OUT (* (reg8 *) SD_WP__PRTDSI__SYNC_OUT) + + +#if defined(SD_WP__INTSTAT) /* Interrupt Registers */ + + #define SD_WP_INTSTAT (* (reg8 *) SD_WP__INTSTAT) + #define SD_WP_SNAP (* (reg8 *) SD_WP__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_WP_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_WP_aliases.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_WP_aliases.h new file mode 100644 index 0000000..9a14d37 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_WP_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: SD_WP.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_WP_ALIASES_H) /* Pins SD_WP_ALIASES_H */ +#define CY_PINS_SD_WP_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_WP_0 SD_WP__0__PC + +#endif /* End Pins SD_WP_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld new file mode 100644 index 0000000..fb5ad88 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld @@ -0,0 +1,223 @@ +/* Linker script for ARM M-profile Simulator + * + * Version: Sourcery G++ Lite 2010q1-188 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(__cs3_reset) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro) + +MEMORY +{ + rom (rx) : ORIGIN = 0, LENGTH = (262144 - 0) + ram (rwx) : ORIGIN = 0x20000000 - (65536 / 2), LENGTH = (65536 - 0x4000 - 0x1000) +} + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(__cs3_reset Reset) +EXTERN(__cs3_start_asm __cs3_start_asm_generic_m) +/* Bring in the interrupt routines & vector */ +INCLUDE micro-names.inc +EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) + +/* Provide fall-back values */ +PROVIDE(__cs3_heap_start = _end); +PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20); +PROVIDE(__cs3_stack = 0x20000000 + (65536 / 2)); +PROVIDE(__cs3_heap_end = __cs3_stack - 0x4000); + + +SECTIONS +{ + + .text : + { + CREATE_OBJECT_SYMBOLS + PROVIDE(__cs3_interrupt_vector = RomVectors); + *(.romvectors) + *(.cs3.interrupt_vector) + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cs3_interrupt_vector, "No interrupt vector"); + + PROVIDE(__cs3_reset = Reset); + *(.cs3.reset) + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cs3_reset, "No reset code"); + + /* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */ + *(.dma_init) + ASSERT(0 + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash"); + + *(.text.cs3.init) + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */ + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + } >rom + .eh_frame_hdr : ALIGN (4) + { + KEEP (*(.eh_frame_hdr)) + } >rom + .eh_frame : ALIGN (4) + { + KEEP (*(.eh_frame)) + } >rom + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + __exidx_end = .; + .rodata : ALIGN (4) + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cs3_regions = .; + LONG (0) + LONG (__cs3_region_init_ram) + LONG (__cs3_region_start_data) + LONG (__cs3_region_init_size_ram) + LONG (__cs3_region_zero_size_ram) + __cs3_regions_end = .; + + . = ALIGN (8); + _etext = .; + } >rom + + .ramvectors (NOLOAD) : ALIGN(8) + { + __cs3_region_start_ram = .; + *(.cs3.region-head.ram) + ASSERT (. == __cs3_region_start_ram, ".cs3.region-head.ram not permitted"); + KEEP(*(.ramvectors)) + } + + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } + + .data : ALIGN(8) + { + __cs3_region_start_data = .; + + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN (8); + *(.ram) + _edata = .; + } >ram AT>rom + .bss : ALIGN(8) + { + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + *(.ram.b) + _end = .; + __end = .; + } >ram AT>rom + + __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram); + __cs3_region_size_ram = LENGTH(ram); + __cs3_region_init_ram = LOADADDR (.data); + __cs3_region_init_size_ram = _edata - ADDR (.data); + __cs3_region_zero_size_ram = _end - _edata; + + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/config.hex b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/config.hex new file mode 100644 index 0000000..c281d8f --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/config.hex @@ -0,0 +1,30 @@ +:20000000065200400165004034060140220701404314014043150140031601403F1701409B +:2000200003400140024101400242014002430140064801400D49014004500140015101405F +:2000400014FF18081CE12CFF34F06430870F81A1830E844785618698878288818A408BCF3F +:200060008C048D4C9001914C924094889661974C98E299449A089B089C419D10A041A11029 +:20008000A441A508A720A840A944AC10AD4CB110B361B4C0B50FB63FB780B880B902BA2077 +:2000A000BB0CBE40BF40D409D604D80BD90BDB0BDC99DD90DF01008401200A6A102A1302EE +:2000C00019201B80209421042244281029602A042B40302832013380381439425810590AE3 +:2000E0005A80628063407801C007C20FC40FCA0FCC0FCE0FD60FD809DE0102010404050176 +:20010000060807060A040E30120314101504160C1703182019031A0C1B041C0320032403E8 +:20012000280329052B022E483002324033073401363C3B083E1154405604580B590B5B0B91 +:200140005C995D905F0180E084208501860387028A088EE0900892109486950197049A01A1 +:200160009D06A210A645A902AB01B018B107B2E0B407B902BE05D808D908DB04DC99DF01A8 +:2001800000040180024003080404058007840A6A0C060D040E081028120113021501170833 +:2001A000184019821B181D041E882108278028042C0431083210378838043C0460806250DE +:2001C00063206C0278017F01848089018B408D048E0490049108926A9302944097409801B7 +:2001E0009A519B0E9D02A028A508A640B704C0FFC27FC43FCA24CC56CE42D80FDE11E020BD +:20020000E250E480EC1056085B045D90008401210A68102A13021B402018210122902308A9 +:20022000280229202A043028314032013814394240444104480449084B40500252555E8092 +:20024000610864016702682869416A427140730278019004910892089542966298029920F9 +:200260009C019D4A9E049F02A040A42AA680A740A812AF40C00FC20EC40FCA0ECC0FCE0F51 +:20028000D007D20CD610D812DE0130103640CC309C10A6409C10A6409C10A6402320270820 +:2002A0009C10AE40C860EE400B205004578084108B188C048F809B089C10B720C210D460F6 +:2002C000E64001010B0111011B01000FC02902461F172028802000D000D6600090D64000B2 +:2002E00000D0FF067FD2800400D60000C0000100C0040400C002080000219F8E000F00F0DE +:20030000000FFF01002200080000404063024000050EFDBC3DFFFFFF2200F008040000005B +:2003200000000228040B0B0B909900010000C00040011011C00100114001400100000000CE +:2003400000000000000000000000000000FFFF00000000000800300008000000000000005F +:200360000000000010000000FF000000000000010200F10E0E000C000000000000FCFC005A +:2003800000000000F0000FF00000000000010000F00F0F000000000100000000000000005E +:00000001FF diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.c new file mode 100644 index 0000000..56fddc5 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.c @@ -0,0 +1,784 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +__ASM void __CLREX(void) +{ + clrex +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); + __ASM("bx lr"); +} + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) __attribute__( ( naked ) ); +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n\t" + "BX lr \n\t" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) __attribute__( ( naked ) ); +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n\t" + "BX lr \n\t" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.h new file mode 100644 index 0000000..d97a0f4 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.h @@ -0,0 +1,1818 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include /* Include standard types */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI() { __ASM ("wfi"); } +static __INLINE void __WFE() { __ASM ("wfe"); } +static __INLINE void __SEV() { __ASM ("sev"); } +static __INLINE void __CLREX() { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP() { __ASM volatile ("nop"); } +static __INLINE void __WFI() { __ASM volatile ("wfi"); } +static __INLINE void __WFE() { __ASM volatile ("wfe"); } +static __INLINE void __SEV() { __ASM volatile ("sev"); } +static __INLINE void __ISB() { __ASM volatile ("isb"); } +static __INLINE void __DSB() { __ASM volatile ("dsb"); } +static __INLINE void __DMB() { __ASM volatile ("dmb"); } +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h new file mode 100644 index 0000000..f81e29f --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h @@ -0,0 +1,43 @@ +/******************************************************************************* +* File Name: core_cm3_psoc5.h +* Version 3.40 +* +* Description: +* Provides important type information for the PSoC5. This includes types +* necessary for core_cm3.h. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#if !defined(__CORE_CM3_PSOC5_H__) +#define __CORE_CM3_PSOC5_H__ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1 /*!< 15 Cortex-M3 System Tick Interrupt */ +/****** PSoC5 Peripheral Interrupt Numbers *******************************************************/ + /* Not relevant. All peripheral interrupts are defined by the user */ +} IRQn_Type; + +#include + +#endif /* __CORE_CM3_PSOC5_H__ */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c new file mode 100644 index 0000000..91a7604 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c @@ -0,0 +1,2459 @@ +/******************************************************************************* +* File Name: cyPm.c +* Version 3.40 +* +* Description: +* Provides an API for the power management. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cyPm.h" + + +/******************************************************************* +* Place your includes, defines and code here. Do not use merge +* region below unless any component datasheet suggest to do so. +*******************************************************************/ +/* `#START CY_PM_HEADER_INCLUDE` */ + +/* `#END` */ + + +static CY_PM_BACKUP_STRUCT cyPmBackup; +static CY_PM_CLOCK_BACKUP_STRUCT cyPmClockBackup; + +/* Convertion table between register's values and frequency in MHz */ +static const uint8 CYCODE cyPmImoFreqReg2Mhz[7u] = {12u, 6u, 24u, 3u, 48u, 62u, 74u}; + +/* Function Prototypes */ +static void CyPmHibSaveSet(void); +static void CyPmHibRestore(void) ; + +static void CyPmSlpSaveSet(void) ; +static void CyPmSlpRestore(void) ; + +static void CyPmHibSlpSaveSet(void) ; +static void CyPmHibSlpRestore(void) ; + +static void CyPmHviLviSaveDisable(void) ; +static void CyPmHviLviRestore(void) ; + +#if(CY_PSOC5A) + + /*************************************************************************** + * The PICU interupt event is not allowed to act as wakeup source for PSoC 5. + * To prevent accidental wakeup all the PICU interrupts are disabled before + * Sleep and Hibernate low power modes entry. In case of Sleep mode registers + * values must be restored on wakeup, but in case of Hibernate low power mode + * there is no sense in saving/restoring registers values as the only wakeup + * source for this mode is external reset (XRES). For more information refer + * to the PSoC 5 device TRM. + ***************************************************************************/ + + static void CyPmSavePicuInterrupts(void); + static void CyPmDisablePicuInterrupts(void) ; + static void CyPmRestorePicuInterrupts(void) ; + +#endif /* (CY_PSOC5A) */ + + +/******************************************************************************* +* Function Name: CyPmSaveClocks +******************************************************************************** +* +* Summary: +* This function is called in preparation for entering sleep or hibernate low +* power modes. Saves all state of the clocking system that does not persist +* during sleep/hibernate or that needs to be altered in preparation for +* sleep/hibernate. Shutdowns all the digital and analog clock dividers for the +* active power mode configuration. +* +* Switches the master clock over to the IMO and shuts down the PLL and MHz +* Crystal. The IMO frequency is set to either 12 MHz or 48 MHz to match the +* Design-Wide Resources System Editor "Enable Fast IMO During Startup" setting. +* The ILO and 32 KHz oscillators are not impacted. The current Flash wait state +* setting is saved and the Flash wait state setting is set for the current IMO +* speed. +* +* Note If the Master Clock source is routed through the DSI inputs, then it +* must be set manually to another source before using the +* CyPmSaveClocks()/CyPmRestoreClocks() functions. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* All peripheral clocks are going to be off after this API method call. +* +*******************************************************************************/ +void CyPmSaveClocks(void) +{ + /* Digital and analog clocks - save enable state and disable them all */ + cyPmClockBackup.enClkA = CY_PM_ACT_CFG1_REG & CY_PM_ACT_EN_CLK_A_MASK; + cyPmClockBackup.enClkD = CY_PM_ACT_CFG2_REG; + CY_PM_ACT_CFG1_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_A_MASK)); + CY_PM_ACT_CFG2_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_D_MASK)); + + /* Save current flash wait cycles and set the maximum value */ + cyPmClockBackup.flashWaitCycles = CY_PM_CACHE_CR_CYCLES_MASK & CY_PM_CACHE_CR_REG; + CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); + + /* IMO - save current IMO MHz OSC frequency and USB mode is on bit */ + cyPmClockBackup.imoFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + cyPmClockBackup.imoUsbClk = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_USB; + + /* IMO doubler - save enable state */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) + { + /* IMO doubler enabled - save and disable */ + cyPmClockBackup.imo2x = CY_PM_ENABLED; + } + else + { + /* IMO doubler disabled */ + cyPmClockBackup.imo2x = CY_PM_DISABLED; + } + + /* IMO - set appropriate frequency for LPM */ + CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM); + + /* IMO - save enable state and enable without wait to settle */ + if(0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)) + { + /* IMO - save enabled state */ + cyPmClockBackup.imoEnable = CY_PM_ENABLED; + } + else + { + /* IMO - save disabled state */ + cyPmClockBackup.imoEnable = CY_PM_DISABLED; + + /* IMO - enable */ + CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); + } + + /* IMO - save the current IMOCLK source and set to IMO if not yet */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_XCLKEN)) + { + /* DSI or XTAL CLK */ + cyPmClockBackup.imoClkSrc = + (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL; + + /* IMO - set IMOCLK source to MHz OSC */ + CyIMO_SetSource(CY_IMO_SOURCE_IMO); + } + else + { + /* IMO */ + cyPmClockBackup.imoClkSrc = CY_IMO_SOURCE_IMO; + } + + /* Save clk_imo source */ + cyPmClockBackup.clkImoSrc = CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK; + + /* If IMOCLK2X or SPC OSC is source for clk_imo, set it to IMOCLK */ + if(CY_PM_CLKDIST_IMO_OUT_IMO != cyPmClockBackup.clkImoSrc) + { + /* Set IMOCLK to source for clk_imo */ + CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | + CY_PM_CLKDIST_IMO_OUT_IMO; + } /* Need to change nothing if IMOCLK is source clk_imo */ + + /* IMO doubler - disable it (saved above) */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) + { + CyIMO_DisableDoubler(); + } + + /* Master clock - save divider and set it to divide-by-one (if no yet) */ + cyPmClockBackup.clkSyncDiv = CY_PM_CLKDIST_MSTR0_REG; + if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv) + { + CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE); + } /* Need to change nothing if master clock divider is 1 */ + + /* Master clock - save current source */ + cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK; + + /* Master clock source - set it to IMO if not yet. */ + if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc) + { + CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO); + } /* Need to change nothing if master clock source is IMO */ + + /* Bus clock - save divider and set it, if needed, to divide-by-one */ + cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG; + if(CY_PM_BUS_CLK_DIV_BY_ONE != cyPmClockBackup.clkBusDiv) + { + CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE); + } /* Do nothing if saved and actual values are equal */ + + /* Set number of wait cycles for the flash according CPU frequency in MHz */ + CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ); + + /* PLL - check enable state, disable if needed */ + if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE)) + { + /* PLL is enabled - save state and disable */ + cyPmClockBackup.pllEnableState = CY_PM_ENABLED; + CyPLL_OUT_Stop(); + } + else + { + /* PLL is disabled - save state */ + cyPmClockBackup.pllEnableState = CY_PM_DISABLED; + } + + /* MHz ECO - check enable state and disable if needed */ + if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE)) + { + /* MHz ECO is enabled - save state and disable */ + cyPmClockBackup.xmhzEnableState = CY_PM_ENABLED; + CyXTAL_Stop(); + } + else + { + /* MHz ECO is disabled - save state */ + cyPmClockBackup.xmhzEnableState = CY_PM_DISABLED; + } + + + /*************************************************************************** + * Save enable state of delay between the system bus clock and each of the + * 4 individual analog clocks. This bit non-retention and it's value should + * be restored on wakeup. + ***************************************************************************/ + if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN)) + { + cyPmClockBackup.clkDistDelay = CY_PM_ENABLED; + } + else + { + cyPmClockBackup.clkDistDelay = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmRestoreClocks +******************************************************************************** +* +* Summary: +* Restores any state that was preserved by the last call to CyPmSaveClocks(). +* The Flash wait state setting is also restored. +* +* Note If the Master Clock source is routed through the DSI inputs, then it +* must be set manually to another source before using the +* CyPmSaveClocks()/CyPmRestoreClocks() functions. +* +* PSoC 3 and PSoC 5LP: +* The merge region could be used to process state when the megahertz crystal is +* not ready after the hold-off timeout. +* +* PSoC 5: +* The 130 ms is given for the megahertz crystal to stabilize. It's readiness is +* not verified after the hold-off timeout. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyPmRestoreClocks(void) +{ + #if (!CY_PSOC5A) + + cystatus status = CYRET_TIMEOUT; + uint16 i; + + #endif /* (!CY_PSOC5A) */ + + + /* Convertion table between CyIMO_SetFreq() parameters and register's value */ + const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { + CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ, CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ, + CY_IMO_FREQ_48MHZ, 5u, 6u}; + + /* Restore enable state of delay between the system bus clock and ACLKs. */ + if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay) + { + /* Delay for both the bandgap and the delay line to settle out */ + CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) * + CY_PM_GET_CPU_FREQ_MHZ); + + CY_PM_CLKDIST_DELAY_REG |= CY_PM_CLKDIST_DELAY_EN; + } + + /* MHz ECO restore state */ + if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) + { + /*********************************************************************** + * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait + * period uses FTW for period measurement. This could cause a problem + * if CTW/FTW is used as a wake up time in the low power modes APIs. + * So, the XTAL wait procedure is implemented with a software delay. + ***********************************************************************/ + + /* Enable XMHZ XTAL with no wait */ + (void) CyXTAL_Start(CY_PM_XTAL_MHZ_NO_WAIT); + + #if(CY_PSOC5A) + + /* Make a 130 milliseconds delay */ + CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ * CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US); + + #else + + /* Read XERR bit to clear it */ + (void) CY_PM_FASTCLK_XMHZ_CSR_REG; + + /* Wait */ + for(i = CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US; i > 0u; i--) + { + /* Make a 200 microseconds delay */ + CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ); + + /* High output indicates oscillator failure */ + if(0u == (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_XERR)) + { + status = CYRET_SUCCESS; + break; + } + } + + if(CYRET_TIMEOUT == status) + { + /******************************************************************* + * Process the situation when megahertz crystal is not ready. + * Time to stabialize value is crystal specific. + *******************************************************************/ + + /* `#START_MHZ_ECO_TIMEOUT` */ + + /* `#END` */ + } + + #endif /* (CY_PSOC5A) */ + + } /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */ + + + /* Temprorary set the maximum flash wait cycles */ + CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); + + /* The XTAL and DSI clocks are ready to be source for Master clock. */ + if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) || + (CY_PM_MASTER_CLK_SRC_DSI == cyPmClockBackup.masterClkSrc)) + { + /* Restore Master clock's divider */ + if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) + { + /* Restore Master clock divider */ + CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); + } + + /* Restore Master clock source */ + CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); + } + + /* IMO - restore IMO frequency */ + if((0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) && + (CY_IMO_FREQ_24MHZ == cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq])) + { + /* Restore IMO frequency (24 MHz) and trim it for USB */ + CyIMO_SetFreq(CY_IMO_FREQ_USB); + } + else + { + /* Restore IMO frequency */ + CyIMO_SetFreq(cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq]); + + if(0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) + { + CY_PM_FASTCLK_IMO_CR_REG |= CY_PM_FASTCLK_IMO_CR_USB; + } + else + { + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_PM_FASTCLK_IMO_CR_USB)); + } + } + + /* IMO - restore enable state if needed */ + if((CY_PM_ENABLED == cyPmClockBackup.imoEnable) && + (0u == (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) + { + /* IMO - restore enabled state */ + CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); + } + + /* IMO - restore disable state if needed */ + if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) && + (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) + { + CyIMO_Stop(); + } + + /* IMO - restore IMOCLK source */ + CyIMO_SetSource(cyPmClockBackup.imoClkSrc); + + /* Restore IMO doubler enable state (turned off by CyPmSaveClocks()) */ + if(CY_PM_ENABLED == cyPmClockBackup.imo2x) + { + CyIMO_EnableDoubler(); + } + + /* IMO - restore clk_imo source, if needed */ + if(cyPmClockBackup.clkImoSrc != (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK)) + { + CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | + cyPmClockBackup.clkImoSrc; + } + + /* PLL restore state */ + if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState) + { + /*********************************************************************** + * Enable PLL. The actual CyPLL_OUT_Start() without wait period uses FTW + * for period measurement. This could cause a problem if CTW/FTW is used + * as a wakeup time in the low power modes APIs. To omit this issue PLL + * wait procedure is implemented with a software delay. + ***********************************************************************/ + + /* Enable PLL */ + (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT); + + /* Make a 250 us delay */ + CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ); + } /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */ + + + /* PLL and IMO is ready to be source for Master clock */ + if((CY_PM_MASTER_CLK_SRC_IMO == cyPmClockBackup.masterClkSrc) || + (CY_PM_MASTER_CLK_SRC_PLL == cyPmClockBackup.masterClkSrc)) + { + /* Restore Master clock divider */ + if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) + { + CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); + } + + /* Restore Master clock source */ + CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); + } + + /* Bus clock - restore divider, if needed */ + if(cyPmClockBackup.clkBusDiv != ((uint16)((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG)) + { + CyBusClk_SetDivider(cyPmClockBackup.clkBusDiv); + } + + /* Restore flash wait cycles */ + CY_PM_CACHE_CR_REG = ((CY_PM_CACHE_CR_REG & ((uint8)(~CY_PM_CACHE_CR_CYCLES_MASK))) | + cyPmClockBackup.flashWaitCycles); + + /* Digital and analog clocks - restore state */ + CY_PM_ACT_CFG1_REG = cyPmClockBackup.enClkA; + CY_PM_ACT_CFG2_REG = cyPmClockBackup.enClkD; +} + + +/******************************************************************************* +* Function Name: CyPmAltAct +******************************************************************************** +* +* Summary: +* Puts the part into the Alternate Active (Standby) state. The Alternate Active +* state can allow for any of the capabilities of the device to be active, but +* the operation of this function is dependent on the CPU being disabled during +* the Alternate Active state. The configuration code and the component APIs +* will configure the template for the Alternate Active state to be the same as +* the Active state with the exception that the CPU will be disabled during +* Alternate Active. +* +* Note Before calling this function, you must manually configure the power mode +* of the source clocks for the timer that is used as the wakeup timer. +* +* PSoC 3: +* Before switching to Alternate Active, if a wakeupTime other than NONE is +* specified, then the appropriate timer state is configured as specified with +* the interrupt for that timer disabled. The wakeup source will be the +* combination of the values specified in the wakeupSource and any timer +* specified in the wakeupTime argument. Once the wakeup condition is +* satisfied, then all saved state is restored and the function returns in the +* Active state. +* +* Note that if the wakeupTime is made with a different value, the period before +* the wakeup occurs can be significantly shorter than the specified time. If +* the next call is made with the same wakeupTime value, then the wakeup will +* occur the specified period after the previous wakeup occurred. +* +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. If the CTW, FTW or One PPS is already +* configured for wakeup, for example with the SleepTimer or RTC components, +* then specify NONE for the wakeupTime and include the appropriate source for +* wakeupSource. +* +* PSoC 5: +* This function is used to both enter the Alternate Active mode and halt the +* processor. For PSoC 3 these two actions must be paired together. With +* PSoC 5 the processor can be halted independently with the __WFI() function +* from the CMSIS library that is included in Creator. This function should be +* used instead when the action required is just to halt the processor until an +* enabled interrupt occurs. +* +* Neither of the parameters to the CyPmAltAct() function are used. The +* parameters must be set to 0 (PM_ALT_ACT_TIME_NONE and PM_ALT_ACT_SRC_NONE). +* The wake up time configuration can be done by a separate component: the CTW +* wakeup interval should be configured with the Sleep Timer component and one +* second interval should be configured with the RTC component. +* +* Upon function execution the device will be switched from Active to Alternate +* Active mode and the CPU will be halted. When an enabled interrupt occurs the +* device will be switched to Active mode and the CPU will be started. Note that +* if a wakeup event occurs and the associated interrupt is not enabled, then +* the device will switch to Active mode with the CPU still halted. The CPU will +* remain halted until an enabled interrupt occurs. +* +* PSoC 5LP: +* This function is used to both enter the Alternate Active mode and halt the +* processor. For PSoC 3 these two actions must be paired together. With PSoC +* 5LP the processor can be halted independently with the __WFI() function from +* the CMSIS library that is included in Creator. This function should be used +* instead when the action required is just to halt the processor until an +* enabled interrupt occurs. +* +* The wakeupTime parameter is not used for this device. It must be set to zero +* (PM_ALT_ACT_TIME_NONE). The wake up time configuration can be done by a +* separate component: the CTW wakeup interval should be configured with the +* Sleep Timer component and one second interval should be configured with the +* RTC component. +* +* The wakeup behavior depends on wakeupSource parameter in the following +* manner: upon function execution the device will be switched from Active to +* Alternate Active mode and then the CPU will be halted. When an enabled wakeup +* event occurs the device will return to Active mode. Similarly when an +* enabled interrupt occurs the CPU will be started. These two actions will +* occur together provided that the event that occurs is an enabled wakeup +* source and also generates an interrupt. If just the wakeup event occurs then +* the device will be in Active mode, but the CPU will remain halted waiting for +* an interrupt. If an interrupt occurs from something other than a wakeup +* source, then the CPU will restart with the device in Alternate Active mode +* until a wakeup event occurs. +* +* For example, if CyPmAltAct(PM_ALT_ACT_TIME_NONE, PM_ALT_ACT_SRC_PICU) is +* called and PICU interrupt occurs, the CPU will be started and device will be +* switched into Active mode. And if CyPmAltAct(PM_ALT_ACT_TIME_NONE, +* PM_ALT_ACT_SRC_NONE) is called and PICU interrupt occurs, the CPU will be +* started while device remains in Alternate Active mode. +* +* Parameters: +* wakeupTime: Specifies a timer wakeup source and the frequency of that +* source. For PSoC 5 and PSoC 5LP this parameter is ignored. +* +* Define Time +* PM_ALT_ACT_TIME_NONE None +* PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second +* PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms +* PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms +* PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms +* PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms +* PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms +* PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms +* PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms +* PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms +* PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms +* PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms +* PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms +* PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms +* PM_ALT_ACT_TIME_FTW(1-256)* FTW: 10us to 2.56 ms +* +* *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that +* specifies how many increments of 10 us to delay. + For PSoC 3 silicon the valid range of values is 1 to 256. +* +* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* a wakeupTime has been specified the associated timer will be +* included as a wakeup source. For PSoC 5 this parameter is +* ignored. +* +* Define Source +* PM_ALT_ACT_SRC_NONE None +* PM_ALT_ACT_SRC_COMPARATOR0 Comparator 0 +* PM_ALT_ACT_SRC_COMPARATOR1 Comparator 1 +* PM_ALT_ACT_SRC_COMPARATOR2 Comparator 2 +* PM_ALT_ACT_SRC_COMPARATOR3 Comparator 3 +* PM_ALT_ACT_SRC_INTERRUPT Interrupt +* PM_ALT_ACT_SRC_PICU PICU +* PM_ALT_ACT_SRC_I2C I2C +* PM_ALT_ACT_SRC_BOOSTCONVERTER Boost Converter +* PM_ALT_ACT_SRC_FTW Fast Timewheel* +* PM_ALT_ACT_SRC_VD High and Low Voltage Detection (HVI, LVI)* +* PM_ALT_ACT_SRC_CTW Central Timewheel** +* PM_ALT_ACT_SRC_ONE_PPS One PPS** +* PM_ALT_ACT_SRC_LCD LCD +* +* *Note : FTW and HVI/LVI wakeup signals are in the same mask bit. +* **Note: CTW and One PPS wakeup signals are in the same mask bit. +* +* When specifying a Comparator as the wakeupSource an instance specific define +* should be used that will track with the specific comparator that the instance +* is placed into. As an example, for a Comparator instance named MyComp the +* value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* +* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus() +* function must be called upon wakeup with corresponding parameter. Please +* refer to the CyPmReadStatus() API in the System Reference Guide for more +* information. +* +* Return: +* None +* +* Reentrant: +* No +* +* Side Effects: +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is +* used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time) +* will be left started. +* +*******************************************************************************/ +void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) +{ + #if(CY_PSOC5) + + /* Arguments expected to be 0 */ + CYASSERT(PM_ALT_ACT_TIME_NONE == wakeupTime); + + #if(CY_PSOC5A) + + /* The wakeupSource argument expected to be 0 */ + CYASSERT(PM_ALT_ACT_SRC_NONE == wakeupSource); + + if(0u != wakeupSource) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5A) */ + + if(0u != wakeupTime) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5) */ + + + #if(CY_PSOC3) + + /* FTW - save current and set new configuration */ + if((wakeupTime >= PM_ALT_ACT_TIME_FTW(1u)) && (wakeupTime <= PM_ALT_ACT_TIME_FTW(256u))) + { + CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime)); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_FTW; + } + + /* CTW - save current and set new configuration */ + if((wakeupTime >= PM_ALT_ACT_TIME_CTW_2MS) && (wakeupTime <= PM_ALT_ACT_TIME_CTW_4096MS)) + { + /* Save current CTW configuration and set new one */ + CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_CTW; + } + + /* 1PPS - save current and set new configuration */ + if(PM_ALT_ACT_TIME_ONE_PPS == wakeupTime) + { + /* Save current 1PPS configuration and set new one */ + CyPmOppsSet(); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS; + } + + #endif /* (CY_PSOC3) */ + + + #if(CY_PSOC3 || CY_PSOC5LP) + + /* Save and set new wake up configuration */ + + /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + /* LCD */ + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + + /* Switch to the Alternate Active mode */ + CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_ALT_ACT); + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into the mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + /* Point of return from Alternate Active Mode */ + + #if(CY_PSOC3 || CY_PSOC5LP) + + /* Restore wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ +} + + +/******************************************************************************* +* Function Name: CyPmSleep +******************************************************************************** +* +* Summary: +* Puts the part into the Sleep state. +* +* Note Before calling this function, you must manually configure the power +* mode of the source clocks for the timer that is used as wakeup timer. +* +* Note Before calling this function, you must prepare clock tree configuration +* for the low power mode by calling CyPmSaveClocks(). And restore clock +* configuration after CyPmSleep() execution by calling CyPmRestoreClocks(). See +* Power Management section, Clock Configuration subsection of the System +* Reference Guide for more information. +* +* PSoC 3: +* Before switching to Sleep, if a wakeupTime other than NONE is specified, +* then the appropriate timer state is configured as specified with the +* interrupt for that timer disabled. The wakeup source will be the combination +* of the values specified in the wakeupSource and any timer specified in the +* wakeupTime argument. Once the wakeup condition is satisfied, then all saved +* state is restored and the function returns in the Active state. +* +* Note that if the wakeupTime is made with a different value, the period before +* the wakeup occurs can be significantly shorter than the specified time. If +* the next call is made with the same wakeupTime value, then the wakeup will +* occur the specified period after the previous wakeup occurred. +* +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. If the CTW or One PPS is already +* configured for wakeup, for example with the SleepTimer or RTC components, +* then specify NONE for the wakeupTime and include the appropriate source for +* wakeupSource. +* +* PSoC 5: +* Neither parameter to this function is used for PSoC 5. The parameters must be +* set to 0 (PM_SLEEP_TIME_NONE and PM_SLEEP_SRC_NONE). The device will go +* into Sleep mode until it is woken by an interrupt from the Central Time Wheel +* (CTW). The CTW must already be configured to generate an interrupt. It is +* configured using the SleepTimer component. Only the CTW can be used to wake +* the device from sleep mode. The other wakeup sources, Once per second or +* Port Interrupt Controller (PICU), cannot be used reliably with PSoC 5. This +* function automatically disables these interrupt sources and then restores +* them after the devices is woken by the CTW. +* +* The duration of sleep needs to be controlled so that the device doesn't wake +* up too soon after going to sleep or remain asleep for too long. Reliable +* sleep times of between 1 ms and 128 ms can be supported. This requirement is +* satisfied with CTW settings of 4, 8, 16, 32, 64, 128 or 256 ms. To control +* the sleep time the CTW is reset automatically just before putting the device +* to sleep. The resulting wakeup time is half the duration programmed into the +* CTW with an uncertainty of 1 ms due to the arrival time of the first ILO +* clock edge. For example, the setting of 4 ms will result in a sleep time +* between 1 ms and 2 ms. +* +* PSoC 5LP: +* The wakeupTime parameter is not used and the only NONE can be specified. +* The wakeup time must be configured with the component, SleepTimer for CTW +* intervals and RTC for 1PPS interval. The component must be configured to +* generate an interrrupt. +* +* Parameters: +* wakeupTime: Specifies a timer wakeup source and the frequency of that +* source. For PSoC 5 and PSoC 5LP, this parameter is ignored. +* +* Define Time +* PM_SLEEP_TIME_NONE None +* PM_SLEEP_TIME_ONE_PPS One PPS: 1 second +* PM_SLEEP_TIME_CTW_2MS CTW: 2 ms +* PM_SLEEP_TIME_CTW_4MS CTW: 4 ms +* PM_SLEEP_TIME_CTW_8MS CTW: 8 ms +* PM_SLEEP_TIME_CTW_16MS CTW: 16 ms +* PM_SLEEP_TIME_CTW_32MS CTW: 32 ms +* PM_SLEEP_TIME_CTW_64MS CTW: 64 ms +* PM_SLEEP_TIME_CTW_128MS CTW: 128 ms +* PM_SLEEP_TIME_CTW_256MS CTW: 256 ms +* PM_SLEEP_TIME_CTW_512MS CTW: 512 ms +* PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms +* PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms +* PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms +* +* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* a wakeupTime has been specified the associated timer will be +* included as a wakeup source. For PSoC 5 this parameter is +* ignored. +* +* Define Source +* PM_SLEEP_SRC_NONE None +* PM_SLEEP_SRC_COMPARATOR0 Comparator 0 +* PM_SLEEP_SRC_COMPARATOR1 Comparator 1 +* PM_SLEEP_SRC_COMPARATOR2 Comparator 2 +* PM_SLEEP_SRC_COMPARATOR3 Comparator 3 +* PM_SLEEP_SRC_PICU PICU +* PM_SLEEP_SRC_I2C I2C +* PM_SLEEP_SRC_BOOSTCONVERTER Boost Converter +* PM_SLEEP_SRC_VD High and Low Voltage Detection (HVI, LVI) +* PM_SLEEP_SRC_CTW Central Timewheel* +* PM_SLEEP_SRC_ONE_PPS One PPS* +* PM_SLEEP_SRC_LCD LCD +* +* *Note: CTW and One PPS wakeup signals are in the same mask bit. +* For PSoC 5, these are in a different bit (value 1024). +* +* When specifying a Comparator as the wakeupSource an instance specific define +* should be used that will track with the specific comparator that the instance +* is placed into. As an example for a Comparator instance named MyComp the +* value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* +* When CTW or One PPS is used as a wakeup source, the CyPmReadStatus() +* function must be called upon wakeup with corresponding parameter. Please +* refer to the CyPmReadStatus() API in the System Reference Guide for more +* information. +* +* Return: +* None +* +* Reentrant: +* No +* +* Side Effects and Restrictions: +* For PSoC 5 silicon the wakeup source is not selectable. In this case the +* wakeupSource argument is ignored and any of the available wakeup sources will +* wake the device. +* +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is +* used as wake up time) will be left started. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using rising edges of the 1 kHz ILO. +* +* For PSoC 3 silicon hardware buzz should be disabled before entering a sleep +* power mode. It is disabled by PSoC Creator during startup. +* If a Low Voltage Interrupt (LVI), High Voltage Interrupt (HVI) or Brown Out +* detect (power supply supervising capabilities) are required in a design +* during sleep, use the Central Time Wheel (CTW) to periodically wake the +* device, perform software buzz, and refresh the supervisory services. If LVI, +* HVI, or Brown Out is not required, then use of the CTW is not required. +* Refer to the device errata for more information. +* +*******************************************************************************/ +void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + + #if(CY_PSOC3 || CY_PSOC5LP) + + /*********************************************************************** + * The Hibernate/Sleep regulator has a settling time after a reset. + * During this time, the system ignores requests to enter Sleep and + * Hibernate modes. The holdoff delay is measured using rising edges of + * the 1 kHz ILO. + ***********************************************************************/ + if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) + { + /* Disable hold off - no action on restore */ + CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; + } + else + { + /* Abort, device is not ready for low power mode entry */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + + return; + } + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + + #if(CY_PSOC3) + + /* Silicon Revision ID is below TO6 */ + if(CYDEV_CHIP_REV_ACTUAL < 5u) + { + /* Hardware buzz expected to be disabled in Sleep mode */ + CYASSERT(0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)); + + /* LVI/HVI requires hardware buzz to be enabled */ + if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | + CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) + { + CYASSERT(0u != 0u); + } + } + + #endif /* (CY_PSOC3) */ + + + /******************************************************************************* + * For ARM-based devices, an interrupt is required for the CPU to wake up. The + * Power Management implementation assumes that wakeup time is configured with a + * separate component (component-based wakeup time configuration) for an + * interrupt to be issued on terminal count. For more information, refer to the + * Wakeup Time Configuration section of System Reference Guide. + *******************************************************************************/ + #if(CY_PSOC5) + + /* Arguments expected to be 0 */ + CYASSERT(PM_SLEEP_TIME_NONE == wakeupTime); + + #if(CY_PSOC5A) + + /* The wakeupSource argument expected to be 0 */ + CYASSERT(PM_SLEEP_SRC_NONE == wakeupSource); + + if(0u != wakeupSource) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5A) */ + + if(0u != wakeupTime) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5) */ + + + /* Prepare hardware for Sleep mode */ + CyPmSlpSaveSet(); + + + #if(CY_PSOC3) + + /* CTW - save current and set new configuration */ + if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS)) + { + /* Save current and set new configuration of the CTW */ + CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_SLEEP_SRC_CTW; + } + + /* 1PPS - save current and set new configuration */ + if(PM_SLEEP_TIME_ONE_PPS == wakeupTime) + { + /* Save current and set new configuration of the 1PPS */ + CyPmOppsSet(); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_SLEEP_SRC_ONE_PPS; + } + + #endif /* (CY_PSOC3) */ + + + #if(!CY_PSOC5A) + + /* Save and set new wake up configuration */ + + /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + /* LCD */ + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); + + #endif /* (!CY_PSOC5A) */ + + + /******************************************************************* + * Do not use merge region below unless any component datasheet + * suggest to do so. + *******************************************************************/ + /* `#START CY_PM_JUST_BEFORE_SLEEP` */ + + /* `#END` */ + + + /* Last moment IMO frequency change */ + if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) + { + /* IMO frequency is 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; + } + else + { + /* IMO frequency is not 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; + + /* Save IMO frequency */ + cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + + /* Set IMO frequency to 12 MHz */ + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); + } + + /* Switch to the Sleep mode */ + CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP); + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into the mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + /* Point of return from Sleep Mode */ + + /* Restore last moment IMO frequency change */ + if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) + { + CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | + cyPmBackup.imoActFreq; + } + + + /******************************************************************* + * Do not use merge region below unless any component datasheet + * suggest to do so. + *******************************************************************/ + /* `#START CY_PM_JUST_AFTER_WAKEUP_FROM_SLEEP` */ + + /* `#END` */ + + + /* Restore hardware configuration */ + CyPmSlpRestore(); + + + #if(!CY_PSOC5A) + + /* Restore current wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; + + #endif /* (!CY_PSOC5A) */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyPmHibernate +******************************************************************************** +* +* Summary: +* Puts the part into the Hibernate state. +* +* PSoC 3 and PSoC 5LP: +* Before switching to Hibernate, the current status of the PICU wakeup source +* bit is saved and then set. This configures the device to wake up from the +* PICU. Make sure you have at least one pin configured to generate a PICU +* interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls +* the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]." +* In the Pins component datasheet, this register is referred to as the IRQ +* option. Once the wakeup occurs, the PICU wakeup source bit is restored and +* the PSoC returns to the Active state. +* +* PSoC 5: +* The only method supported for waking up from the Hibernate state is a +* hardware reset of the device. The PICU wakeup source cannot be used +* reliably, so the PICU interrupt sources are automatically disabled by this +* function before putting the device into the Hibernate state. +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +* Side Effects: +* Applications must wait 20 us before re-entering hibernate or sleep after +* waking up from hibernate. The 20 us allows the sleep regulator time to +* stabilize before the next hibernate / sleep event occurs. The 20 us +* requirement begins when the device wakes up. There is no hardware check that +* this requirement is met. The specified delay should be done on ISR entry. +* +* After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is +* instance name of the Pins component) function must be called to clear the +* latched pin events to allow proper Hibernate mode entry andd to enable +* detection of future events. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using rising edges of the 1 kHz ILO. +* +*******************************************************************************/ +void CyPmHibernate(void) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + #if(CY_PSOC3 || CY_PSOC5LP) + + /*********************************************************************** + * The Hibernate/Sleep regulator has a settling time after a reset. + * During this time, the system ignores requests to enter Sleep and + * Hibernate modes. The holdoff delay is measured using rising edges of + * the 1 kHz ILO. + ***********************************************************************/ + if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) + { + /* Disable hold off - no action on restore */ + CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; + } + else + { + /* Abort, device is not ready for low power mode entry */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + + return; + } + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + /* Prepare device for proper Hibernate mode entry */ + CyPmHibSaveSet(); + + + #if(!CY_PSOC5A) + + /* Save and enable only wakeup on PICU */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU; + + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = 0x00u; + + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = 0x00u; + + #endif /* (!CY_PSOC5A) */ + + + /* Last moment IMO frequency change */ + if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) + { + /* IMO frequency is 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; + } + else + { + /* IMO frequency is not 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; + + /* Save IMO frequency */ + cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + + /* Set IMO frequency to 12 MHz */ + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); + } + + + /* Switch to Hibernate Mode */ + CY_PM_MODE_CSR_REG = (CY_PM_MODE_CSR_REG & ((uint8) (~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_HIBERNATE; + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into the mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + /* Point of return from Hibernate mode */ + + + /* Restore last moment IMO frequency change */ + if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) + { + CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | + cyPmBackup.imoActFreq; + } + + + /* Restore device for proper Hibernate mode exit*/ + CyPmHibRestore(); + + + #if(!CY_PSOC5A) + + /* Restore current wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; + + #endif /* (!CY_PSOC5A) */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyPmReadStatus +******************************************************************************** +* +* Summary: +* Manages the Power Manager Interrupt Status Register. This register has the +* interrupt status for the one pulse per second, central timewheel and fast +* timewheel timers. This hardware register clears on read. To allow for only +* clearing the bits of interest and preserving the other bits, this function +* uses a shadow register that retains the state. This function reads the +* status register and ORs that value with the shadow register. That is the +* value that is returned. Then the bits in the mask that are set are cleared +* from this value and written back to the shadow register. +* +* Note You must call this function within 1 ms (1 clock cycle of the ILO) +* after a CTW event has occurred. +* +* Parameters: +* mask: Bits in the shadow register to clear. +* +* Define Source +* CY_PM_FTW_INT Fast Timewheel +* CY_PM_CTW_INT Central Timewheel +* CY_PM_ONEPPS_INT One Pulse Per Second +* +* Return: +* Status. Same bits values as the mask parameter. +* +*******************************************************************************/ +uint8 CyPmReadStatus(uint8 mask) +{ + static uint8 interruptStatus; + uint8 interruptState; + uint8 tmpStatus; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Save value of the register, copy it and clear desired bit */ + interruptStatus |= CY_PM_INT_SR_REG; + tmpStatus = interruptStatus; + interruptStatus &= ((uint8)(~mask)); + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: CyPmHibSaveSet +******************************************************************************** +* +* Summary: +* Prepare device for proper Hibernate low power mode entry: +* - Disables I2C backup regulator +* - Save state of I2C backup regulator (PSoC 5) +* - Saves ILO power down mode state and enable it (all but PSoC 5) +* - Saves state of 1 kHz and 100 kHz ILO and disable them (all but PSoC 5) +* - Disables sleep regulator and shorts vccd to vpwrsleep (all but PSoC 5) +* - Save LVI/HVI configuration and disable them - CyPmHviLviSaveDisable() +* - CyPmHibSlpSaveSet() function is called +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHibSaveSet(void) +{ + /* I2C backup reg must be off when the sleep regulator is unavailable */ + if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP)) + { + /*********************************************************************** + * If I2C backup regulator is enabled, all the fixed-function registers + * store their values while device is in low power mode, otherwise their + * configuration is lost. The I2C API makes a decision to restore or not + * to restore I2C registers based on this. If this regulator will be + * disabled and then enabled, I2C API will suppose that I2C block + * registers preserved their values, while this is not true. So, the + * backup regulator is disabled. And its value is restored only for + * and PSoC 5 devices. The I2C sleep APIs is responsible for restoration. + ***********************************************************************/ + + #if(CY_PSOC5A) + + cyPmBackup.i2cRegBackup = CY_PM_ENABLED; + + #endif /* (CY_PSOC5A) */ + + /* Disable I2C backup register */ + CY_PM_PWRSYS_CR1_REG &= ((uint8)(~CY_PM_PWRSYS_CR1_I2CREG_BACKUP)); + } + else + { + #if(CY_PSOC5A) + + /* Save disabled state of the I2C backup regulator */ + cyPmBackup.i2cRegBackup = CY_PM_DISABLED; + + #endif /* (CY_PSOC5A) */ + } + + + #if(!CY_PSOC5A) + + /* Save current ILO power mode and ensure low power mode */ + cyPmBackup.iloPowerMode = CyILO_SetPowerMode(CY_PM_POWERDOWN_MODE); + + /* Save current 1kHz ILO enable state. Disabled automatically. */ + cyPmBackup.ilo1kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_1K)) ? + CY_PM_DISABLED : CY_PM_ENABLED; + + /* Save current 100kHz ILO enable state. Disabled automatically. */ + cyPmBackup.ilo100kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_100K)) ? + CY_PM_DISABLED : CY_PM_ENABLED; + + + /* Disable the sleep regulator and shorts vccd to vpwrsleep */ + if(0u == (CY_PM_PWRSYS_SLP_TR_REG & CY_PM_PWRSYS_SLP_TR_BYPASS)) + { + /* Save current bypass state */ + cyPmBackup.slpTrBypass = CY_PM_DISABLED; + CY_PM_PWRSYS_SLP_TR_REG |= CY_PM_PWRSYS_SLP_TR_BYPASS; + } + else + { + cyPmBackup.slpTrBypass = CY_PM_ENABLED; + } + + /* LPCOMPs are always enabled (even when BOTH ext_vccd=1 and ext_vcca=1)*/ + + #endif /* (!CY_PSOC5A) */ + + + /* Device is PSoC 5 and the revision is ES1 or earlier. */ + #if(CY_PSOC5A) + + /* Disable all the PICU interrupts */ + CyPmDisablePicuInterrupts(); + + #endif /* (CY_PSOC5A) */ + + + /*************************************************************************** + * LVI/HVI must be disabled in Hibernate + ***************************************************************************/ + + /* Save LVI/HVI configuration and disable them */ + CyPmHviLviSaveDisable(); + + + /* Make the same preparations for Hibernate and Sleep modes */ + CyPmHibSlpSaveSet(); + + + /*************************************************************************** + * Save and set power mode wakeup trim registers + ***************************************************************************/ + #if(CY_PSOC3 || CY_PSOC5LP) + + cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; + cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG; + + CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0; + CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1; + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +} + + +/******************************************************************************* +* Function Name: CyPmHibRestore +******************************************************************************** +* +* Summary: +* Restore device for proper Hibernate mode exit: +* - Restore LVI/HVI configuration - call CyPmHviLviRestore() +* - CyPmHibSlpSaveRestore() function is called +* - Restores state of I2C backup regulator (PSoC 5) +* - Restores ILO power down mode state and enable it (all but PSoC 5) +* - Restores state of 1 kHz and 100 kHz ILO and disable them (all but PSoC 5) +* - Restores sleep regulator settings (all but PSoC 5) +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +static void CyPmHibRestore(void) +{ + /* Restore LVI/HVI configuration */ + CyPmHviLviRestore(); + + /* Restore the same configuration for Hibernate and Sleep modes */ + CyPmHibSlpRestore(); + + #if(CY_PSOC5A) + + /* Restore I2C backup regulator configuration */ + if(CY_PM_ENABLED == cyPmBackup.i2cRegBackup) + { + /* Enable I2C backup regulator state */ + CY_PM_PWRSYS_CR1_REG |= CY_PM_PWRSYS_CR1_I2CREG_BACKUP; + } + + #endif /* (CY_PSOC5A) */ + + + #if(!CY_PSOC5A) + + /* Restore 1kHz ILO enable state */ + if(CY_PM_ENABLED == cyPmBackup.ilo1kEnable) + { + /* Enable 1kHz ILO */ + CyILO_Start1K(); + } + + /* Restore 100kHz ILO enable state */ + if(CY_PM_ENABLED == cyPmBackup.ilo100kEnable) + { + /* Enable 100kHz ILO */ + CyILO_Start100K(); + } + + /* Restore ILO power mode */ + (void) CyILO_SetPowerMode(cyPmBackup.iloPowerMode); + + + if(CY_PM_DISABLED == cyPmBackup.slpTrBypass) + { + /* Enable the sleep regulator */ + CY_PM_PWRSYS_SLP_TR_REG &= ((uint8)(~CY_PM_PWRSYS_SLP_TR_BYPASS)); + } + + #endif /* (!CY_PSOC5A) */ + + + /*************************************************************************** + * Restore power mode wakeup trim registers + ***************************************************************************/ + #if(CY_PSOC3 || CY_PSOC5LP) + + CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0; + CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1; + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ +} + + +/******************************************************************************* +* Function Name: CyPmCtwSetInterval +******************************************************************************** +* +* Summary: +* Performs CTW configuration: +* - Disables CTW interrupt +* - Enables 1 kHz ILO +* - Sets new CTW interval +* +* Parameters: +* ctwInterval: the CTW interval to be set. +* +* Return: +* None +* +* Side Effects: +* Enables ILO 1 KHz clock and leaves it enabled. +* +*******************************************************************************/ +void CyPmCtwSetInterval(uint8 ctwInterval) +{ + /* Disable CTW interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_IE)); + + /* Enable 1kHz ILO (required for CTW operation) */ + CyILO_Start1K(); + + /* Interval could be set only while CTW is disabled */ + if(0u != (CY_PM_TW_CFG2_REG & CY_PM_CTW_EN)) + { + /* Set CTW interval if needed */ + if(CY_PM_TW_CFG1_REG != ctwInterval) + { + /* Disable the CTW, set new CTW interval and enable it again */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_EN)); + CY_PM_TW_CFG1_REG = ctwInterval; + CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; + } /* Required interval is already set */ + } + else + { + /* Set CTW interval if needed */ + if(CY_PM_TW_CFG1_REG != ctwInterval) + { + /* Set the new CTW interval. Could be changed if CTW is disabled */ + CY_PM_TW_CFG1_REG = ctwInterval; + } /* Required interval is already set */ + + /* Enable the CTW */ + CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; + } +} + + +/******************************************************************************* +* Function Name: CyPmOppsSet +******************************************************************************** +* +* Summary: +* Performs 1PPS configuration: +* - Starts 32 KHz XTAL +* - Disables 1PPS interupts +* - Enables 1PPS +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyPmOppsSet(void) +{ + /* Enable 32kHz XTAL if needed */ + if(0u == (CY_PM_SLOWCLK_X32_CR_REG & CY_PM_X32_CR_X32EN)) + { + /* Enable 32kHz XTAL */ + CyXTAL_32KHZ_Start(); + } + + /* Disable 1PPS interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_1PPS_IE)); + + /* Enable 1PPS operation */ + CY_PM_TW_CFG2_REG |= CY_PM_1PPS_EN; +} + + +/******************************************************************************* +* Function Name: CyPmFtwSetInterval +******************************************************************************** +* +* Summary: +* Performs FTW configuration: +* - Disables FTW interrupt +* - Enables 100 kHz ILO +* - Sets new FTW interval. +* +* Parameters: +* ftwInterval - FTW counter interval. +* +* Return: +* None +* +* Side Effects: +* Enables ILO 100 KHz clock and leaves it enabled. +* +*******************************************************************************/ +void CyPmFtwSetInterval(uint8 ftwInterval) +{ + /* Disable FTW interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_IE)); + + /* Enable 100kHz ILO */ + CyILO_Start100K(); + + /* Iterval could be set only while FTW is disabled */ + if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN)) + { + /* Disable FTW, set new FTW interval if needed and enable it again */ + if(CY_PM_TW_CFG0_REG != ftwInterval) + { + /* Disable the CTW, set new CTW interval and enable it again */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN)); + CY_PM_TW_CFG0_REG = ftwInterval; + CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; + } /* Required interval is already set */ + } + else + { + /* Set new FTW counter interval if needed. FTW is disabled. */ + if(CY_PM_TW_CFG0_REG != ftwInterval) + { + /* Set the new CTW interval. Could be changed if CTW is disabled */ + CY_PM_TW_CFG0_REG = ftwInterval; + } /* Required interval is already set */ + + /* Enable the FTW */ + CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; + } +} + + +#if(CY_PSOC5A) + + /******************************************************************************* + * Function Name: CyPmSavePicuInterrupts + ******************************************************************************** + * + * Summary: + * Saves PICU interrupt type registers to the backup structure. + * + * Parameters: + * None + * + * Return: + * None + * + * Reentrant: + * No + * + *******************************************************************************/ + static void CyPmSavePicuInterrupts(void) + { + /* Save all the PICU interrupt type */ + (void) memcpy((void *) &cyPmBackup.picuIntType[0u], + (void *) CY_PM_PICU_0_6_INT_BASE, + CY_PM_PICU_0_6_INT_SIZE); + + (void) memcpy((void *) &cyPmBackup.picuIntType[CY_PM_PICU_0_6_INT_SIZE], + (void *) CY_PM_PICU_12_INT_BASE, + CY_PM_PICU_12_INT_SIZE); + + (void) memcpy((void *) &cyPmBackup.picuIntType[CY_PM_PICU_0_6_INT_SIZE + CY_PM_PICU_12_INT_SIZE], + (void *) CY_PM_PICU_15_INT_BASE, + CY_PM_PICU_15_INT_SIZE); + + } + + + /******************************************************************************* + * Function Name: CyPmDisablePicuInterrupts + ******************************************************************************** + * + * Summary: + * Disableds PICU interrupts. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + static void CyPmDisablePicuInterrupts(void) + { + /* Disable all the PICU interrupts */ + (void) memset((void *) CY_PM_PICU_0_6_INT_BASE, 0, CY_PM_PICU_0_6_INT_SIZE); + (void) memset((void *) CY_PM_PICU_12_INT_BASE, 0, CY_PM_PICU_12_INT_SIZE ); + (void) memset((void *) CY_PM_PICU_15_INT_BASE, 0, CY_PM_PICU_15_INT_SIZE ); + } + + + /******************************************************************************* + * Function Name: CyPmRestorePicuInterrupts + ******************************************************************************** + * + * Summary: + * Restores PICU interrupt type registers from the backup structure. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + static void CyPmRestorePicuInterrupts(void) + { + /* Save all the PICU interrupt type */ + (void) memcpy((void *) CY_PM_PICU_0_6_INT_BASE, + (void *) &cyPmBackup.picuIntType[0u], + CY_PM_PICU_0_6_INT_SIZE); + + (void) memcpy((void *) CY_PM_PICU_12_INT_BASE, + (void *) &cyPmBackup.picuIntType[CY_PM_PICU_0_6_INT_SIZE], + CY_PM_PICU_12_INT_SIZE); + + (void) memcpy((void *) CY_PM_PICU_15_INT_BASE, + (void *) &cyPmBackup.picuIntType[CY_PM_PICU_0_6_INT_SIZE + CY_PM_PICU_12_INT_SIZE], + CY_PM_PICU_15_INT_SIZE); + + } + +#endif /* (CY_PSOC5A) */ + + +/******************************************************************************* +* Function Name: CyPmSlpSaveSet +******************************************************************************** +* +* Summary: +* Prepare device for proper Sleep low power mode entry: +* - Prepare CTW for Sleep mode entry (PSoC 5) +* * Save timewheels configuration +* * Disable FTW and 1PPS (enable and interrupt) +* * Reset CTW +* * Save and disable PICU interrupts +* * Save and disable PRES-A and PRES-D +* - Save and disable LVI/HVI configuration (PSoC 5) +* - Save and set to max buzz interval (PSoC 5) +* - CyPmHibSlpSaveSet() function is called +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmSlpSaveSet(void) +{ + #if(CY_PSOC5A) + + /* Preserve the Timewheel Configuration Register 2 */ + cyPmBackup.pmTwCfg2 = CY_PM_TW_CFG2_REG; + + /* Clear the enable and interrupt enables for the FTW and ONEPPS */ + CY_PM_TW_CFG2_REG &= ((uint8)(~(CY_PM_FTW_IE | CY_PM_FTW_EN | CY_PM_1PPS_EN | CY_PM_1PPS_IE))); + + /* Reset free-running CTW counter to 0 and held it there */ + CY_PM_WDT_CFG_REG |= CY_PM_WDT_CFG_CTW_RESET; + + /* Exit CTW counter reset state */ + CY_PM_WDT_CFG_REG &= ((uint8)(~CY_PM_WDT_CFG_CTW_RESET)); + + /* Save and disable PICU interrupts */ + CyPmSavePicuInterrupts(); + CyPmDisablePicuInterrupts(); + + /* Save and disable PRES-A and PRES-D */ + cyPmBackup.pres1 = CY_PM_RESET_CR1_REG & CY_PM_RESET_CR1_DIS_PRES1; + cyPmBackup.pres2 = CY_PM_RESET_CR3_REG & CY_PM_RESET_CR3_DIS_PRES2; + CY_PM_RESET_CR1_REG &= ((uint8)(~CY_PM_RESET_CR1_DIS_PRES1)); + CY_PM_RESET_CR3_REG &= ((uint8)(~CY_PM_RESET_CR3_DIS_PRES2)); + + #endif /* (CY_PSOC5A) */ + + + #if(CY_PSOC5A) + + /*************************************************************************** + * LVI/HVI must be disabled as it doesn't work during buzzing. + * + * Using hardware buzz in conjunction with other device wakeup sources + * can cause the device to lockup, halting further code execution. The + * hardware buzz provides power supply supervising capability in sleep. + * It is enabled by default and there is no way to disable it. So the buzz + * interval is set to maximum (512 ms). The CTW must be configured to wake up + * at a rate less than hardware buzz interval. + ***************************************************************************/ + + /* Save and disable LVI/HVI */ + CyPmHviLviSaveDisable(); + + /* Save buzz trim value */ + cyPmBackup.buzzSleepTrim = CY_PM_PWRSYS_BUZZ_TR_REG & ((uint8)(~CY_PM_PWRSYS_BUZZ_TR_MASK)); + + /* Set buzz interval to maximum */ + CY_PM_PWRSYS_BUZZ_TR_REG = CY_PM_PWRSYS_BUZZ_TR_512_TICKS | + (CY_PM_PWRSYS_BUZZ_TR_REG & CY_PM_PWRSYS_BUZZ_TR_MASK); + + #endif /* (CY_PSOC5A) */ + + + /* Apply configuration that are same for Sleep and Hibernate */ + CyPmHibSlpSaveSet(); +} + + +/******************************************************************************* +* Function Name: CyPmSlpRestore +******************************************************************************** +* +* Summary: +* Restore device for proper Sleep mode exit: +* - Restore timewheel configuration (PSoC 5) +* - Restore PRES-A and PRES-D (PSoC 5) +* - Restore PICU interrupts (PSoC 5) +* - Restore buzz sleep trim value (PSoC 5) +* - Call to CyPmHibSlpSaveRestore() +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +static void CyPmSlpRestore(void) +{ + #if(CY_PSOC5A) + + /* Restore the Timewheel Configuration Register 2 */ + CY_PM_TW_CFG2_REG = cyPmBackup.pmTwCfg2; + + /* Restore PICU interrupts */ + CyPmRestorePicuInterrupts(); + + /* Restore PRES-A and PRES-D (assumed they were disabled) */ + CY_PM_RESET_CR1_REG |= cyPmBackup.pres1; + CY_PM_RESET_CR3_REG |= cyPmBackup.pres2; + + #endif /* (CY_PSOC5A) */ + + + #if(CY_PSOC5A) + + /* Restore LVI/HVI configuration */ + CyPmHviLviRestore(); + + /* Restore buzz sleep trim value */ + CY_PM_PWRSYS_BUZZ_TR_REG = cyPmBackup.buzzSleepTrim | + (CY_PM_PWRSYS_BUZZ_TR_REG & CY_PM_PWRSYS_BUZZ_TR_MASK); + + #endif /* (CY_PSOC5A) */ + + + /* Restore configuration that are same for Sleep and Hibernate */ + CyPmHibSlpRestore(); +} + + +/******************************************************************************* +* Function Name: CyPmHibSlpSaveSet +******************************************************************************** +* +* Summary: +* This API is used for preparing device for Sleep and Hibernate low power +* modes entry: +* - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5) +* - Saves SC/CT routing connections (PSoC 3/5/5LP) +* - Disables Serial Wire Viewer (SWV) (PSoC 3) +* - Save boost reference selection and set it to internal +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHibSlpSaveSet(void) +{ + #if(CY_PSOC5A) + + /* Save CMP routing registers */ + cyPmBackup.cmpData[0u] = CY_GET_REG8(CYREG_CMP0_SW0); + cyPmBackup.cmpData[1u] = CY_GET_REG8(CYREG_CMP0_SW2); + cyPmBackup.cmpData[2u] = CY_GET_REG8(CYREG_CMP0_SW3); + cyPmBackup.cmpData[3u] = CY_GET_REG8(CYREG_CMP0_SW4); + cyPmBackup.cmpData[4u] = CY_GET_REG8(CYREG_CMP0_SW6); + + cyPmBackup.cmpData[5u] = CY_GET_REG8(CYREG_CMP1_SW0); + cyPmBackup.cmpData[6u] = CY_GET_REG8(CYREG_CMP1_SW2); + cyPmBackup.cmpData[7u] = CY_GET_REG8(CYREG_CMP1_SW3); + cyPmBackup.cmpData[8u] = CY_GET_REG8(CYREG_CMP1_SW4); + cyPmBackup.cmpData[9u] = CY_GET_REG8(CYREG_CMP1_SW6); + + cyPmBackup.cmpData[10u] = CY_GET_REG8(CYREG_CMP2_SW0); + cyPmBackup.cmpData[11u] = CY_GET_REG8(CYREG_CMP2_SW2); + cyPmBackup.cmpData[12u] = CY_GET_REG8(CYREG_CMP2_SW3); + cyPmBackup.cmpData[13u] = CY_GET_REG8(CYREG_CMP2_SW4); + cyPmBackup.cmpData[14u] = CY_GET_REG8(CYREG_CMP2_SW6); + + cyPmBackup.cmpData[15u] = CY_GET_REG8(CYREG_CMP3_SW0); + cyPmBackup.cmpData[16u] = CY_GET_REG8(CYREG_CMP3_SW2); + cyPmBackup.cmpData[17u] = CY_GET_REG8(CYREG_CMP3_SW3); + cyPmBackup.cmpData[18u] = CY_GET_REG8(CYREG_CMP3_SW4); + cyPmBackup.cmpData[19u] = CY_GET_REG8(CYREG_CMP3_SW6); + + + /* Clear CMP routing registers */ + CY_SET_REG8(CYREG_CMP0_SW0 , 0u); + CY_SET_REG8(CYREG_CMP0_SW2 , 0u); + CY_SET_REG8(CYREG_CMP0_SW3 , 0u); + CY_SET_REG8(CYREG_CMP0_SW4 , 0u); + CY_SET_REG8(CYREG_CMP0_SW6 , 0u); + + CY_SET_REG8(CYREG_CMP1_SW0 , 0u); + CY_SET_REG8(CYREG_CMP1_SW2 , 0u); + CY_SET_REG8(CYREG_CMP1_SW3 , 0u); + CY_SET_REG8(CYREG_CMP1_SW4 , 0u); + CY_SET_REG8(CYREG_CMP1_SW6 , 0u); + + CY_SET_REG8(CYREG_CMP2_SW0 , 0u); + CY_SET_REG8(CYREG_CMP2_SW2 , 0u); + CY_SET_REG8(CYREG_CMP2_SW3 , 0u); + CY_SET_REG8(CYREG_CMP2_SW4 , 0u); + CY_SET_REG8(CYREG_CMP2_SW6 , 0u); + + CY_SET_REG8(CYREG_CMP3_SW0 , 0u); + CY_SET_REG8(CYREG_CMP3_SW2 , 0u); + CY_SET_REG8(CYREG_CMP3_SW3 , 0u); + CY_SET_REG8(CYREG_CMP3_SW4 , 0u); + CY_SET_REG8(CYREG_CMP3_SW6 , 0u); + + + /* Save DAC routing registers */ + cyPmBackup.dacData[0u] = CY_GET_REG8(CYREG_DAC0_SW0); + cyPmBackup.dacData[1u] = CY_GET_REG8(CYREG_DAC0_SW2); + cyPmBackup.dacData[2u] = CY_GET_REG8(CYREG_DAC0_SW3); + cyPmBackup.dacData[3u] = CY_GET_REG8(CYREG_DAC0_SW4); + + cyPmBackup.dacData[4u] = CY_GET_REG8(CYREG_DAC1_SW0); + cyPmBackup.dacData[5u] = CY_GET_REG8(CYREG_DAC1_SW2); + cyPmBackup.dacData[6u] = CY_GET_REG8(CYREG_DAC1_SW3); + cyPmBackup.dacData[7u] = CY_GET_REG8(CYREG_DAC1_SW4); + + cyPmBackup.dacData[8u] = CY_GET_REG8(CYREG_DAC2_SW0); + cyPmBackup.dacData[9u] = CY_GET_REG8(CYREG_DAC2_SW2); + cyPmBackup.dacData[10u] = CY_GET_REG8(CYREG_DAC2_SW3); + cyPmBackup.dacData[11u] = CY_GET_REG8(CYREG_DAC2_SW4); + + cyPmBackup.dacData[12u] = CY_GET_REG8(CYREG_DAC3_SW0); + cyPmBackup.dacData[13u] = CY_GET_REG8(CYREG_DAC3_SW2); + cyPmBackup.dacData[14u] = CY_GET_REG8(CYREG_DAC3_SW3); + cyPmBackup.dacData[15u] = CY_GET_REG8(CYREG_DAC3_SW4); + + /* Clear DAC routing registers */ + CY_SET_REG8(CYREG_DAC0_SW0 , 0u); + CY_SET_REG8(CYREG_DAC0_SW2 , 0u); + CY_SET_REG8(CYREG_DAC0_SW3 , 0u); + CY_SET_REG8(CYREG_DAC0_SW4 , 0u); + + CY_SET_REG8(CYREG_DAC1_SW0 , 0u); + CY_SET_REG8(CYREG_DAC1_SW2 , 0u); + CY_SET_REG8(CYREG_DAC1_SW3 , 0u); + CY_SET_REG8(CYREG_DAC1_SW4 , 0u); + + CY_SET_REG8(CYREG_DAC2_SW0 , 0u); + CY_SET_REG8(CYREG_DAC2_SW2 , 0u); + CY_SET_REG8(CYREG_DAC2_SW3 , 0u); + CY_SET_REG8(CYREG_DAC2_SW4 , 0u); + + CY_SET_REG8(CYREG_DAC3_SW0 , 0u); + CY_SET_REG8(CYREG_DAC3_SW2 , 0u); + CY_SET_REG8(CYREG_DAC3_SW3 , 0u); + CY_SET_REG8(CYREG_DAC3_SW4 , 0u); + + + /* Save DSM routing registers */ + cyPmBackup.dsmData[0u] = CY_GET_REG8(CYREG_DSM0_SW0); + cyPmBackup.dsmData[1u] = CY_GET_REG8(CYREG_DSM0_SW2); + cyPmBackup.dsmData[2u] = CY_GET_REG8(CYREG_DSM0_SW3); + cyPmBackup.dsmData[3u] = CY_GET_REG8(CYREG_DSM0_SW4); + cyPmBackup.dsmData[4u] = CY_GET_REG8(CYREG_DSM0_SW6); + + /* Clear DSM routing registers */ + CY_SET_REG8(CYREG_DSM0_SW0 , 0u); + CY_SET_REG8(CYREG_DSM0_SW2 , 0u); + CY_SET_REG8(CYREG_DSM0_SW3 , 0u); + CY_SET_REG8(CYREG_DSM0_SW4 , 0u); + CY_SET_REG8(CYREG_DSM0_SW6 , 0u); + + + /* Save SAR routing registers */ + cyPmBackup.sarData[0u] = CY_GET_REG8(CYREG_SAR0_SW0); + cyPmBackup.sarData[1u] = CY_GET_REG8(CYREG_SAR0_SW2); + cyPmBackup.sarData[2u] = CY_GET_REG8(CYREG_SAR0_SW3); + cyPmBackup.sarData[3u] = CY_GET_REG8(CYREG_SAR0_SW4); + cyPmBackup.sarData[4u] = CY_GET_REG8(CYREG_SAR0_SW6); + + cyPmBackup.sarData[5u] = CY_GET_REG8(CYREG_SAR1_SW0); + cyPmBackup.sarData[6u] = CY_GET_REG8(CYREG_SAR1_SW2); + cyPmBackup.sarData[7u] = CY_GET_REG8(CYREG_SAR1_SW3); + cyPmBackup.sarData[8u] = CY_GET_REG8(CYREG_SAR1_SW4); + cyPmBackup.sarData[9u] = CY_GET_REG8(CYREG_SAR1_SW6); + + + /* Clear SAR routing registers */ + CY_SET_REG8(CYREG_SAR0_SW0 , 0u); + CY_SET_REG8(CYREG_SAR0_SW2 , 0u); + CY_SET_REG8(CYREG_SAR0_SW3 , 0u); + CY_SET_REG8(CYREG_SAR0_SW4 , 0u); + CY_SET_REG8(CYREG_SAR0_SW6 , 0u); + + CY_SET_REG8(CYREG_SAR1_SW0 , 0u); + CY_SET_REG8(CYREG_SAR1_SW2 , 0u); + CY_SET_REG8(CYREG_SAR1_SW3 , 0u); + CY_SET_REG8(CYREG_SAR1_SW4 , 0u); + CY_SET_REG8(CYREG_SAR1_SW6 , 0u); + + #endif /* (CY_PSOC5A) */ + + + #if(CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) + + /* Save SC/CT routing registers */ + cyPmBackup.scctData[0u] = CY_GET_REG8(CYREG_SC0_SW0 ); + cyPmBackup.scctData[1u] = CY_GET_REG8(CYREG_SC0_SW2 ); + cyPmBackup.scctData[2u] = CY_GET_REG8(CYREG_SC0_SW3 ); + cyPmBackup.scctData[3u] = CY_GET_REG8(CYREG_SC0_SW4 ); + cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 ); + cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 ); + cyPmBackup.scctData[6u] = CY_GET_REG8(CYREG_SC0_SW10); + + cyPmBackup.scctData[7u] = CY_GET_REG8(CYREG_SC1_SW0 ); + cyPmBackup.scctData[8u] = CY_GET_REG8(CYREG_SC1_SW2 ); + cyPmBackup.scctData[9u] = CY_GET_REG8(CYREG_SC1_SW3 ); + cyPmBackup.scctData[10u] = CY_GET_REG8(CYREG_SC1_SW4 ); + cyPmBackup.scctData[11u] = CY_GET_REG8(CYREG_SC1_SW6 ); + cyPmBackup.scctData[12u] = CY_GET_REG8(CYREG_SC1_SW8 ); + cyPmBackup.scctData[13u] = CY_GET_REG8(CYREG_SC1_SW10); + + cyPmBackup.scctData[14u] = CY_GET_REG8(CYREG_SC2_SW0 ); + cyPmBackup.scctData[15u] = CY_GET_REG8(CYREG_SC2_SW2 ); + cyPmBackup.scctData[16u] = CY_GET_REG8(CYREG_SC2_SW3 ); + cyPmBackup.scctData[17u] = CY_GET_REG8(CYREG_SC2_SW4 ); + cyPmBackup.scctData[18u] = CY_GET_REG8(CYREG_SC2_SW6 ); + cyPmBackup.scctData[19u] = CY_GET_REG8(CYREG_SC2_SW8 ); + cyPmBackup.scctData[20u] = CY_GET_REG8(CYREG_SC2_SW10); + + cyPmBackup.scctData[21u] = CY_GET_REG8(CYREG_SC3_SW0 ); + cyPmBackup.scctData[22u] = CY_GET_REG8(CYREG_SC3_SW2 ); + cyPmBackup.scctData[23u] = CY_GET_REG8(CYREG_SC3_SW3 ); + cyPmBackup.scctData[24u] = CY_GET_REG8(CYREG_SC3_SW4 ); + cyPmBackup.scctData[25u] = CY_GET_REG8(CYREG_SC3_SW6 ); + cyPmBackup.scctData[26u] = CY_GET_REG8(CYREG_SC3_SW8 ); + cyPmBackup.scctData[27u] = CY_GET_REG8(CYREG_SC3_SW10); + + CY_SET_REG8(CYREG_SC0_SW0 , 0u); + CY_SET_REG8(CYREG_SC0_SW2 , 0u); + CY_SET_REG8(CYREG_SC0_SW3 , 0u); + CY_SET_REG8(CYREG_SC0_SW4 , 0u); + CY_SET_REG8(CYREG_SC0_SW6 , 0u); + CY_SET_REG8(CYREG_SC0_SW8 , 0u); + CY_SET_REG8(CYREG_SC0_SW10, 0u); + + CY_SET_REG8(CYREG_SC1_SW0 , 0u); + CY_SET_REG8(CYREG_SC1_SW2 , 0u); + CY_SET_REG8(CYREG_SC1_SW3 , 0u); + CY_SET_REG8(CYREG_SC1_SW4 , 0u); + CY_SET_REG8(CYREG_SC1_SW6 , 0u); + CY_SET_REG8(CYREG_SC1_SW8 , 0u); + CY_SET_REG8(CYREG_SC1_SW10, 0u); + + CY_SET_REG8(CYREG_SC2_SW0 , 0u); + CY_SET_REG8(CYREG_SC2_SW2 , 0u); + CY_SET_REG8(CYREG_SC2_SW3 , 0u); + CY_SET_REG8(CYREG_SC2_SW4 , 0u); + CY_SET_REG8(CYREG_SC2_SW6 , 0u); + CY_SET_REG8(CYREG_SC2_SW8 , 0u); + CY_SET_REG8(CYREG_SC2_SW10, 0u); + + CY_SET_REG8(CYREG_SC3_SW0 , 0u); + CY_SET_REG8(CYREG_SC3_SW2 , 0u); + CY_SET_REG8(CYREG_SC3_SW3 , 0u); + CY_SET_REG8(CYREG_SC3_SW4 , 0u); + CY_SET_REG8(CYREG_SC3_SW6 , 0u); + CY_SET_REG8(CYREG_SC3_SW8 , 0u); + CY_SET_REG8(CYREG_SC3_SW10, 0u); + + #endif /* (CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) */ + + + #if(CY_PSOC3) + + /* Serial Wire Viewer (SWV) workaround */ + + /* Disable SWV before entering low power mode */ + if(0u != (CY_PM_MLOGIC_DBG_REG & CY_PM_MLOGIC_DBG_SWV_CLK_EN)) + { + /* Save SWV clock enabled state */ + cyPmBackup.swvClkEnabled = CY_PM_ENABLED; + + /* Save current ports drive mode settings */ + cyPmBackup.prt1Dm = CY_PM_PRT1_PC3_REG & ((uint8)(~CY_PM_PRT1_PC3_DM_MASK)); + + /* Set drive mode to strong output */ + CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | + CY_PM_PRT1_PC3_DM_STRONG; + + /* Disable SWV clocks */ + CY_PM_MLOGIC_DBG_REG &= ((uint8)(~CY_PM_MLOGIC_DBG_SWV_CLK_EN)); + } + else + { + /* Save SWV clock disabled state */ + cyPmBackup.swvClkEnabled = CY_PM_DISABLED; + } + + #endif /* (CY_PSOC3) */ + + + /*************************************************************************** + * Save boost reference and set it to boost's internal by clearing the bit. + * External (chip bandgap) reference is not available in Sleep and Hibernate. + ***************************************************************************/ + if(0u != (CY_PM_BOOST_CR2_REG & CY_PM_BOOST_CR2_EREFSEL_EXT)) + { + cyPmBackup.boostRefExt = CY_PM_ENABLED; + CY_PM_BOOST_CR2_REG &= ((uint8)(~CY_PM_BOOST_CR2_EREFSEL_EXT)); + } + else + { + cyPmBackup.boostRefExt = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmHibSlpRestore +******************************************************************************** +* +* Summary: +* This API is used for restoring device configurations after wakeup from Sleep +* and Hibernate low power modes: +* - Restores COMP, VIDAC, DSM and SAR routing connections (PSoC 5) +* - Restores SC/CT routing connections (PSoC 3/5/5LP) +* - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3) +* - Restores initial buzz rate (PSoC 5) +* - Restore boost reference selection +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +static void CyPmHibSlpRestore(void) +{ + #if(CY_PSOC5A) + + /* Restore COMP routing registers */ + CY_SET_REG8(CYREG_CMP0_SW0 , cyPmBackup.cmpData[0u] ); + CY_SET_REG8(CYREG_CMP0_SW2 , cyPmBackup.cmpData[1u] ); + CY_SET_REG8(CYREG_CMP0_SW3 , cyPmBackup.cmpData[2u] ); + CY_SET_REG8(CYREG_CMP0_SW4 , cyPmBackup.cmpData[3u] ); + CY_SET_REG8(CYREG_CMP0_SW6 , cyPmBackup.cmpData[4u] ); + + CY_SET_REG8(CYREG_CMP1_SW0 , cyPmBackup.cmpData[5u] ); + CY_SET_REG8(CYREG_CMP1_SW2 , cyPmBackup.cmpData[6u] ); + CY_SET_REG8(CYREG_CMP1_SW3 , cyPmBackup.cmpData[7u] ); + CY_SET_REG8(CYREG_CMP1_SW4 , cyPmBackup.cmpData[8u] ); + CY_SET_REG8(CYREG_CMP1_SW6 , cyPmBackup.cmpData[9u] ); + + CY_SET_REG8(CYREG_CMP2_SW0 , cyPmBackup.cmpData[10u]); + CY_SET_REG8(CYREG_CMP2_SW2 , cyPmBackup.cmpData[11u]); + CY_SET_REG8(CYREG_CMP2_SW3 , cyPmBackup.cmpData[12u]); + CY_SET_REG8(CYREG_CMP2_SW4 , cyPmBackup.cmpData[13u]); + CY_SET_REG8(CYREG_CMP2_SW6 , cyPmBackup.cmpData[14u]); + + CY_SET_REG8(CYREG_CMP3_SW0 , cyPmBackup.cmpData[15u]); + CY_SET_REG8(CYREG_CMP3_SW2 , cyPmBackup.cmpData[16u]); + CY_SET_REG8(CYREG_CMP3_SW3 , cyPmBackup.cmpData[17u]); + CY_SET_REG8(CYREG_CMP3_SW4 , cyPmBackup.cmpData[18u]); + CY_SET_REG8(CYREG_CMP3_SW6 , cyPmBackup.cmpData[19u]); + + /* Restore DAC routing registers */ + CY_SET_REG8(CYREG_DAC0_SW0 , cyPmBackup.dacData[0u] ); + CY_SET_REG8(CYREG_DAC0_SW2 , cyPmBackup.dacData[1u] ); + CY_SET_REG8(CYREG_DAC0_SW3 , cyPmBackup.dacData[2u] ); + CY_SET_REG8(CYREG_DAC0_SW4 , cyPmBackup.dacData[3u] ); + + CY_SET_REG8(CYREG_DAC1_SW0 , cyPmBackup.dacData[4u] ); + CY_SET_REG8(CYREG_DAC1_SW2 , cyPmBackup.dacData[5u] ); + CY_SET_REG8(CYREG_DAC1_SW3 , cyPmBackup.dacData[6u] ); + CY_SET_REG8(CYREG_DAC1_SW4 , cyPmBackup.dacData[7u] ); + + CY_SET_REG8(CYREG_DAC2_SW0 , cyPmBackup.dacData[8u] ); + CY_SET_REG8(CYREG_DAC2_SW2 , cyPmBackup.dacData[9u] ); + CY_SET_REG8(CYREG_DAC2_SW3 , cyPmBackup.dacData[10u]); + CY_SET_REG8(CYREG_DAC2_SW4 , cyPmBackup.dacData[11u]); + + CY_SET_REG8(CYREG_DAC3_SW0 , cyPmBackup.dacData[12u]); + CY_SET_REG8(CYREG_DAC3_SW2 , cyPmBackup.dacData[13u]); + CY_SET_REG8(CYREG_DAC3_SW3 , cyPmBackup.dacData[14u]); + CY_SET_REG8(CYREG_DAC3_SW4 , cyPmBackup.dacData[15u]); + + + /* Restore DSM routing registers */ + CY_SET_REG8(CYREG_DSM0_SW0 , cyPmBackup.dsmData[0u]); + CY_SET_REG8(CYREG_DSM0_SW2 , cyPmBackup.dsmData[1u]); + CY_SET_REG8(CYREG_DSM0_SW3 , cyPmBackup.dsmData[2u]); + CY_SET_REG8(CYREG_DSM0_SW4 , cyPmBackup.dsmData[3u]); + CY_SET_REG8(CYREG_DSM0_SW6 , cyPmBackup.dsmData[4u]); + + + /* Restore SAR routing registers */ + CY_SET_REG8(CYREG_SAR0_SW0 , cyPmBackup.sarData[0u]); + CY_SET_REG8(CYREG_SAR0_SW2 , cyPmBackup.sarData[1u]); + CY_SET_REG8(CYREG_SAR0_SW3 , cyPmBackup.sarData[2u]); + CY_SET_REG8(CYREG_SAR0_SW4 , cyPmBackup.sarData[3u]); + CY_SET_REG8(CYREG_SAR0_SW6 , cyPmBackup.sarData[4u]); + + CY_SET_REG8(CYREG_SAR1_SW0 , cyPmBackup.sarData[5u]); + CY_SET_REG8(CYREG_SAR1_SW2 , cyPmBackup.sarData[6u]); + CY_SET_REG8(CYREG_SAR1_SW3 , cyPmBackup.sarData[7u]); + CY_SET_REG8(CYREG_SAR1_SW4 , cyPmBackup.sarData[8u]); + CY_SET_REG8(CYREG_SAR1_SW6 , cyPmBackup.sarData[9u]); + + #endif /* (CY_PSOC5A) */ + + #if(CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) + + /* Restore SC/CT routing registers */ + CY_SET_REG8(CYREG_SC0_SW0 , cyPmBackup.scctData[0u] ); + CY_SET_REG8(CYREG_SC0_SW2 , cyPmBackup.scctData[1u] ); + CY_SET_REG8(CYREG_SC0_SW3 , cyPmBackup.scctData[2u] ); + CY_SET_REG8(CYREG_SC0_SW4 , cyPmBackup.scctData[3u] ); + CY_SET_REG8(CYREG_SC0_SW6 , cyPmBackup.scctData[4u] ); + CY_SET_REG8(CYREG_SC0_SW8 , cyPmBackup.scctData[5u] ); + CY_SET_REG8(CYREG_SC0_SW10, cyPmBackup.scctData[6u] ); + + CY_SET_REG8(CYREG_SC1_SW0 , cyPmBackup.scctData[7u] ); + CY_SET_REG8(CYREG_SC1_SW2 , cyPmBackup.scctData[8u] ); + CY_SET_REG8(CYREG_SC1_SW3 , cyPmBackup.scctData[9u] ); + CY_SET_REG8(CYREG_SC1_SW4 , cyPmBackup.scctData[10u]); + CY_SET_REG8(CYREG_SC1_SW6 , cyPmBackup.scctData[11u]); + CY_SET_REG8(CYREG_SC1_SW8 , cyPmBackup.scctData[12u]); + CY_SET_REG8(CYREG_SC1_SW10, cyPmBackup.scctData[13u]); + + CY_SET_REG8(CYREG_SC2_SW0 , cyPmBackup.scctData[14u]); + CY_SET_REG8(CYREG_SC2_SW2 , cyPmBackup.scctData[15u]); + CY_SET_REG8(CYREG_SC2_SW3 , cyPmBackup.scctData[16u]); + CY_SET_REG8(CYREG_SC2_SW4 , cyPmBackup.scctData[17u]); + CY_SET_REG8(CYREG_SC2_SW6 , cyPmBackup.scctData[18u]); + CY_SET_REG8(CYREG_SC2_SW8 , cyPmBackup.scctData[19u]); + CY_SET_REG8(CYREG_SC2_SW10, cyPmBackup.scctData[20u]); + + CY_SET_REG8(CYREG_SC3_SW0 , cyPmBackup.scctData[21u]); + CY_SET_REG8(CYREG_SC3_SW2 , cyPmBackup.scctData[22u]); + CY_SET_REG8(CYREG_SC3_SW3 , cyPmBackup.scctData[23u]); + CY_SET_REG8(CYREG_SC3_SW4 , cyPmBackup.scctData[24u]); + CY_SET_REG8(CYREG_SC3_SW6 , cyPmBackup.scctData[25u]); + CY_SET_REG8(CYREG_SC3_SW8 , cyPmBackup.scctData[26u]); + CY_SET_REG8(CYREG_SC3_SW10, cyPmBackup.scctData[27u]); + + #endif /* (CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) */ + + + #if(CY_PSOC3) + + /* Serial Wire Viewer (SWV) workaround */ + if(CY_PM_ENABLED == cyPmBackup.swvClkEnabled) + { + /* Restore ports drive mode */ + CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | + cyPmBackup.prt1Dm; + + /* Enable SWV clocks */ + CY_PM_MLOGIC_DBG_REG |= CY_PM_MLOGIC_DBG_SWV_CLK_EN; + } + + #endif /* (CY_PSOC3) */ + + + #if(CY_PSOC5A) + + /* Restore buzz sleep trim value */ + CY_PM_PWRSYS_BUZZ_TR_REG = cyPmBackup.buzzSleepTrim | \ + (CY_PM_PWRSYS_BUZZ_TR_REG & CY_PM_PWRSYS_BUZZ_TR_MASK); + + #endif /* (CY_PSOC5A) */ + + + /* Restore boost reference */ + if(CY_PM_ENABLED == cyPmBackup.boostRefExt) + { + CY_PM_BOOST_CR2_REG |= CY_PM_BOOST_CR2_EREFSEL_EXT; + } +} + + +/******************************************************************************* +* Function Name: CyPmHviLviSaveDisable +******************************************************************************** +* +* Summary: +* Saves analog and digital LVI and HVI configuration and disables them. +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHviLviSaveDisable(void) +{ + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVID_EN)) + { + cyPmBackup.lvidEn = CY_PM_ENABLED; + cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK; + + /* Save state of reset device at a specified Vddd threshold */ + #if(CY_PSOC5A) + + /* Not applicable PSoC 5 */ + cyPmBackup.lvidRst = CY_PM_DISABLED; + + #else + + cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \ + CY_PM_DISABLED : CY_PM_ENABLED; + + #endif /* (CY_PSOC5A) */ + + CyVdLvDigitDisable(); + } + else + { + cyPmBackup.lvidEn = CY_PM_DISABLED; + } + + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVIA_EN)) + { + cyPmBackup.lviaEn = CY_PM_ENABLED; + cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u; + + /* Save state of reset device at a specified Vdda threshold */ + #if(CY_PSOC5A) + + /* Not applicable PSoC 5 */ + cyPmBackup.lviaRst = CY_PM_DISABLED; + + #else + + cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \ + CY_PM_DISABLED : CY_PM_ENABLED; + + #endif /* (CY_PSOC5A) */ + + CyVdLvAnalogDisable(); + } + else + { + cyPmBackup.lviaEn = CY_PM_DISABLED; + } + + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_HVIA_EN)) + { + cyPmBackup.hviaEn = CY_PM_ENABLED; + CyVdHvAnalogDisable(); + } + else + { + cyPmBackup.hviaEn = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmHviLviRestore +******************************************************************************** +* +* Summary: +* Restores analog and digital LVI and HVI configuration. +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHviLviRestore(void) +{ + /* Restore LVI/HVI configuration */ + if(CY_PM_ENABLED == cyPmBackup.lvidEn) + { + CyVdLvDigitEnable(cyPmBackup.lvidRst, cyPmBackup.lvidTrip); + } + + if(CY_PM_ENABLED == cyPmBackup.lviaEn) + { + CyVdLvAnalogEnable(cyPmBackup.lviaRst, cyPmBackup.lviaTrip); + } + + if(CY_PM_ENABLED == cyPmBackup.hviaEn) + { + CyVdHvAnalogEnable(); + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h new file mode 100644 index 0000000..76bfd69 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h @@ -0,0 +1,779 @@ +/******************************************************************************* +* File Name: cyPm.h +* Version 3.40 +* +* Description: +* Provides the function definitions for the power management API. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPM_H) +#define CY_BOOT_CYPM_H + +#include "cytypes.h" /* Register access API */ +#include "cydevice_trm.h" /* Registers addresses */ +#include "cyfitter.h" /* Comparators placement */ +#include "CyLib.h" /* Clock API */ +#include "CyFlash.h" /* Flash API - CyFlash_SetWaitCycles() */ + + +/*************************************** +* Function Prototypes +***************************************/ +void CyPmSaveClocks(void) ; +void CyPmRestoreClocks(void) ; +void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) ; +void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) ; +void CyPmHibernate(void) ; + +uint8 CyPmReadStatus(uint8 mask) ; + +/* Internal APIs and are not meant to be called directly by the user */ +void CyPmCtwSetInterval(uint8 ctwInterval) ; +void CyPmFtwSetInterval(uint8 ftwInterval) ; +void CyPmOppsSet(void) ; + + +/*************************************** +* API Constants +***************************************/ + +#define PM_SLEEP_SRC_NONE (0x0000u) +#define PM_SLEEP_TIME_NONE (0x00u) +#define PM_ALT_ACT_SRC_NONE (0x0000u) +#define PM_ALT_ACT_TIME_NONE (0x0000u) + +#if(CY_PSOC3) + + /* Wake up time for the Sleep mode */ + #define PM_SLEEP_TIME_ONE_PPS (0x01u) + #define PM_SLEEP_TIME_CTW_2MS (0x02u) + #define PM_SLEEP_TIME_CTW_4MS (0x03u) + #define PM_SLEEP_TIME_CTW_8MS (0x04u) + #define PM_SLEEP_TIME_CTW_16MS (0x05u) + #define PM_SLEEP_TIME_CTW_32MS (0x06u) + #define PM_SLEEP_TIME_CTW_64MS (0x07u) + #define PM_SLEEP_TIME_CTW_128MS (0x08u) + #define PM_SLEEP_TIME_CTW_256MS (0x09u) + #define PM_SLEEP_TIME_CTW_512MS (0x0Au) + #define PM_SLEEP_TIME_CTW_1024MS (0x0Bu) + #define PM_SLEEP_TIME_CTW_2048MS (0x0Cu) + #define PM_SLEEP_TIME_CTW_4096MS (0x0Du) + + /* Difference between parameter's value and register's one */ + #define CY_PM_FTW_INTERVAL_SHIFT (0x000Eu) + + /* Wake up time for the Alternate Active mode */ + #define PM_ALT_ACT_TIME_ONE_PPS (0x0001u) + #define PM_ALT_ACT_TIME_CTW_2MS (0x0002u) + #define PM_ALT_ACT_TIME_CTW_4MS (0x0003u) + #define PM_ALT_ACT_TIME_CTW_8MS (0x0004u) + #define PM_ALT_ACT_TIME_CTW_16MS (0x0005u) + #define PM_ALT_ACT_TIME_CTW_32MS (0x0006u) + #define PM_ALT_ACT_TIME_CTW_64MS (0x0007u) + #define PM_ALT_ACT_TIME_CTW_128MS (0x0008u) + #define PM_ALT_ACT_TIME_CTW_256MS (0x0009u) + #define PM_ALT_ACT_TIME_CTW_512MS (0x000Au) + #define PM_ALT_ACT_TIME_CTW_1024MS (0x000Bu) + #define PM_ALT_ACT_TIME_CTW_2048MS (0x000Cu) + #define PM_ALT_ACT_TIME_CTW_4096MS (0x000Du) + #define PM_ALT_ACT_TIME_FTW(x) ((x) + CY_PM_FTW_INTERVAL_SHIFT) + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC3 || CY_PSOC5LP) + + /* Wake up sources for the Sleep mode */ + #define PM_SLEEP_SRC_COMPARATOR0 (0x0001u) + #define PM_SLEEP_SRC_COMPARATOR1 (0x0002u) + #define PM_SLEEP_SRC_COMPARATOR2 (0x0004u) + #define PM_SLEEP_SRC_COMPARATOR3 (0x0008u) + #define PM_SLEEP_SRC_PICU (0x0040u) + #define PM_SLEEP_SRC_I2C (0x0080u) + #define PM_SLEEP_SRC_BOOSTCONVERTER (0x0200u) + #define PM_SLEEP_SRC_VD (0x0400u) + #define PM_SLEEP_SRC_CTW (0x0800u) + #define PM_SLEEP_SRC_ONE_PPS (0x0800u) + #define PM_SLEEP_SRC_LCD (0x1000u) + + /* Wake up sources for the Alternate Active mode */ + #define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u) + #define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u) + #define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u) + #define PM_ALT_ACT_SRC_COMPARATOR3 (0x0008u) + #define PM_ALT_ACT_SRC_INTERRUPT (0x0010u) + #define PM_ALT_ACT_SRC_PICU (0x0040u) + #define PM_ALT_ACT_SRC_I2C (0x0080u) + #define PM_ALT_ACT_SRC_BOOSTCONVERTER (0x0200u) + #define PM_ALT_ACT_SRC_FTW (0x0400u) + #define PM_ALT_ACT_SRC_VD (0x0400u) + #define PM_ALT_ACT_SRC_CTW (0x0800u) + #define PM_ALT_ACT_SRC_ONE_PPS (0x0800u) + #define PM_ALT_ACT_SRC_LCD (0x1000u) + +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +#define CY_PM_WAKEUP_PICU (0x04u) +#define CY_PM_IMO_NO_WAIT_TO_SETTLE (0x00u) +#define CY_PM_POWERDOWN_MODE (0x01u) +#define CY_PM_HIGHPOWER_MODE (0x00u) /* Deprecated */ +#define CY_PM_ENABLED (0x01u) +#define CY_PM_DISABLED (0x00u) + +/* No wait for PLL to stabilize, used in CyPLL_OUT_Start() */ +#define CY_PM_PLL_OUT_NO_WAIT (0u) + +/* No wait for MHZ XTAL to stabilize, used in CyXTAL_Start() */ +#define CY_PM_XTAL_MHZ_NO_WAIT (0u) + +#define CY_PM_WAIT_200_US (200u) +#define CY_PM_WAIT_250_US (250u) +#define CY_PM_WAIT_20_US (20u) + +#define CY_PM_FREQ_3MHZ (3u) +#define CY_PM_FREQ_12MHZ (12u) +#define CY_PM_FREQ_48MHZ (48u) + + +#if(CY_PSOC5A) + #define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (650u) +#else + #define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u) +#endif /* (CY_PSOC5A) */ + + +/* Delay line bandgap current settling time starting from a wakeup event */ +#define CY_PM_CLK_DELAY_BANDGAP_SETTLE_US (50u) + +/* Delay line internal bias settling */ +#define CY_PM_CLK_DELAY_BIAS_SETTLE_US (25u) + + +/* Max flash wait cycles for each device */ +#if(CY_PSOC3) + #define CY_PM_MAX_FLASH_WAIT_CYCLES (45u) +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5A) + #define CY_PM_MAX_FLASH_WAIT_CYCLES (55u) +#endif /* (CY_PSOC5A) */ + +#if(CY_PSOC5LP) + #define CY_PM_MAX_FLASH_WAIT_CYCLES (55u) +#endif /* (CY_PSOC5LP) */ + + +/******************************************************************************* +* This marco is used to obtain the CPU frequency in MHz. It should be only used +* when the clock distribution system is prepared for the low power mode entry. +* This macro is silicon dependent as PSoC 5 devices have no CPU clock divider +* and PSoC 3 devices have different placement of the CPU clock divider register +* bitfield. +*******************************************************************************/ +#if(CY_PSOC3) + #define CY_PM_GET_CPU_FREQ_MHZ ((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \ + ((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u))) +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + + /* The CPU clock is directly derived from bus clock */ + #define CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low +* power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI) +* instruction. The ARM compilers has __wfi() instristic that inserts a WFI +* instruction into the instruction stream generated by the compiler. The GCC +* compiler has to execute assembly language instruction. +*******************************************************************************/ +#if(CY_PSOC5) + + #if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */ + #define CY_PM_WFI __wfi() + #else /* ASM for GCC */ + #define CY_PM_WFI asm volatile ("WFI \n") + #endif /* (__ARMCC_VERSION) */ + +#else + + #define CY_PM_WFI CY_NOP + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Macro for the wakeupTime argument of the CyPmAltAct() function. The FTW should +* be programmed manually for non PSoC 3 devices. +*******************************************************************************/ +#if(CY_PSOC3) + + #define PM_ALT_ACT_FTW_INTERVAL(x) ((uint8)((x) - CY_PM_FTW_INTERVAL_SHIFT)) + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* This macro defines the IMO frequency that will be set by CyPmSaveClocks() +* function based on Enable Fast IMO during Startup option from the DWR file. +* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering +* low power mode and restore IMO back to the value set by CyPmSaveClocks() +* immediately on wakeup. +*******************************************************************************/ + +/* Enable Fast IMO during Startup - enabled */ +#if(1u == CYDEV_CONFIGURATION_IMOENABLED) + + /* IMO will be configured to 48 MHz */ + #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_48MHZ) + +#else + + /* IMO will be configured to 12 MHz */ + #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_12MHZ) + +#endif /* (1u == CYDEV_CONFIGURATION_IMOENABLED) */ + + +typedef struct cyPmClockBackupStruct +{ + /* CyPmSaveClocks()/CyPmRestoreClocks() */ + uint8 enClkA; /* Analog clocks enable */ + uint8 enClkD; /* Digital clocks enable */ + uint8 masterClkSrc; /* The Master clock source */ + uint8 imoFreq; /* IMO frequency (reg's value) */ + uint8 imoUsbClk; /* IMO USB CLK (reg's value) */ + uint8 flashWaitCycles; /* Flash wait cycles */ + uint8 imoEnable; /* IMO enable in Active mode */ + uint8 imoClkSrc; /* The IMO output */ + uint8 clkImoSrc; + uint8 imo2x; /* IMO doubler enable state */ + uint8 clkSyncDiv; /* Master clk divider */ + uint16 clkBusDiv; /* The clk_bus divider */ + uint8 pllEnableState; /* PLL enable state */ + uint8 xmhzEnableState; /* XM HZ enable state */ + uint8 clkDistDelay; /* Delay for clk_bus and ACLKs */ + +} CY_PM_CLOCK_BACKUP_STRUCT; + + +typedef struct cyPmBackupStruct +{ + #if(!CY_PSOC5A) + + uint8 iloPowerMode; /* ILO power mode */ + uint8 ilo1kEnable; /* ILO 1K enable state */ + uint8 ilo100kEnable; /* ILO 100K enable state */ + + uint8 slpTrBypass; /* Sleep Trim Bypass */ + + #endif /* (!CY_PSOC5A) */ + + + #if(CY_PSOC5A) + + /* State of the I2C regulator backup */ + uint8 i2cRegBackup; + + #endif /* (CY_PSOC5A) */ + + + #if(CY_PSOC5A) + uint8 buzzSleepTrim; + #endif /* (CY_PSOC5A) */ + + + #if(CY_PSOC3) + + uint8 swvClkEnabled; /* SWV clock enable state */ + uint8 prt1Dm; /* Ports drive mode configuration */ + + #endif /* (CY_PSOC3) */ + + #if(CY_PSOC3 || CY_PSOC5LP) + + uint8 wakeupCfg0; /* Wake up configuration 0 */ + uint8 wakeupCfg1; /* Wake up configuration 1 */ + uint8 wakeupCfg2; /* Wake up configuration 2 */ + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + + #if(CY_PSOC3 || CY_PSOC5LP) + + uint8 wakeupTrim0; + uint8 wakeupTrim1; + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + + #if(CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) + + uint8 scctData[28u]; /* SC/CT routing registers */ + + #endif /* (CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) */ + + #if(CY_PSOC5A) + + uint8 cmpData[20u]; + uint8 dacData[16u]; + uint8 dsmData[5u]; + uint8 sarData[10u]; + + uint8 pmTwCfg2; + uint8 picuIntType[72u]; + + uint8 pres1; + uint8 pres2; + + #endif /* (CY_PSOC5A) */ + + + /* CyPmHviLviSaveDisable()/CyPmHviLviRestore() */ + uint8 lvidEn; + uint8 lvidTrip; + uint8 lviaEn; + uint8 lviaTrip; + uint8 hviaEn; + uint8 lvidRst; + uint8 lviaRst; + + uint8 imoActFreq; /* Last moment IMO change */ + uint8 imoActFreq12Mhz; /* 12 MHz or not */ + + uint8 boostRefExt; /* Boost reference selection */ + +} CY_PM_BACKUP_STRUCT; + + +/*************************************** +* Registers +***************************************/ + +/* Power Mode Wakeup Trim Register 1 */ +#define CY_PM_PWRSYS_WAKE_TR1_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) +#define CY_PM_PWRSYS_WAKE_TR1_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) + +/* Master clock Divider Value Register */ +#define CY_PM_CLKDIST_MSTR0_REG (* (reg8 *) CYREG_CLKDIST_MSTR0 ) +#define CY_PM_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0 ) + +/* Master Clock Configuration Register/CPU Divider Value */ +#define CY_PM_CLKDIST_MSTR1_REG (* (reg8 *) CYREG_CLKDIST_MSTR1 ) +#define CY_PM_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1 ) + +/* Clock distribution configuration Register */ +#define CY_PM_CLKDIST_CR_REG (* (reg8 *) CYREG_CLKDIST_CR ) +#define CY_PM_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR ) + +/* CLK_BUS LSB Divider Value Register */ +#define CY_PM_CLK_BUS_LSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG0 ) +#define CY_PM_CLK_BUS_LSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0 ) + +/* CLK_BUS MSB Divider Value Register */ +#define CY_PM_CLK_BUS_MSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG1 ) +#define CY_PM_CLK_BUS_MSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1 ) + +/* CLK_BUS Configuration Register */ +#define CLK_BUS_CFG_REG (* (reg8 *) CYREG_CLKDIST_BCFG2 ) +#define CLK_BUS_CFG_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2 ) + +/* Power Mode Control/Status Register */ +#define CY_PM_MODE_CSR_REG (* (reg8 *) CYREG_PM_MODE_CSR ) +#define CY_PM_MODE_CSR_PTR ( (reg8 *) CYREG_PM_MODE_CSR ) + +/* Power System Control Register 1 */ +#define CY_PM_PWRSYS_CR1_REG (* (reg8 *) CYREG_PWRSYS_CR1 ) +#define CY_PM_PWRSYS_CR1_PTR ( (reg8 *) CYREG_PWRSYS_CR1 ) + +/* Power System Control Register 0 */ +#define CY_PM_PWRSYS_CR0_REG (* (reg8 *) CYREG_PWRSYS_CR0 ) +#define CY_PM_PWRSYS_CR0_PTR ( (reg8 *) CYREG_PWRSYS_CR0 ) + +/* Internal Low-speed Oscillator Control Register 0 */ +#define CY_PM_SLOWCLK_ILO_CR0_REG (* (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) +#define CY_PM_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) + +/* External 32kHz Crystal Oscillator Control Register */ +#define CY_PM_SLOWCLK_X32_CR_REG (* (reg8 *) CYREG_SLOWCLK_X32_CR ) +#define CY_PM_SLOWCLK_X32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR ) + +#if(CY_PSOC3) + + /* MLOGIC Debug Register */ + #define CY_PM_MLOGIC_DBG_REG (* (reg8 *) CYREG_MLOGIC_DEBUG ) + #define CY_PM_MLOGIC_DBG_PTR ( (reg8 *) CYREG_MLOGIC_DEBUG ) + + /* Port Pin Configuration Register */ + #define CY_PM_PRT1_PC3_REG (* (reg8 *) CYREG_PRT1_PC3 ) + #define CY_PM_PRT1_PC3_PTR ( (reg8 *) CYREG_PRT1_PC3 ) + +#endif /* (CY_PSOC3) */ + + +#if(!CY_PSOC5A) + + /* Sleep Regulator Trim Register */ + #define CY_PM_PWRSYS_SLP_TR_REG (* (reg8 *) CYREG_PWRSYS_SLP_TR ) + #define CY_PM_PWRSYS_SLP_TR_PTR ( (reg8 *) CYREG_PWRSYS_SLP_TR ) + +#endif /* (CY_PSOC3) */ + +/* Reset System Control Register */ +#define CY_PM_RESET_CR1_REG (* (reg8 *) CYREG_RESET_CR1 ) +#define CY_PM_RESET_CR1_PTR ( (reg8 *) CYREG_RESET_CR1 ) + +#if(CY_PSOC5A) + + /* LVD/POR Test Mode Control Register */ + #define CY_PM_RESET_CR3_REG (* (reg8 *) CYREG_RESET_CR3 ) + #define CY_PM_RESET_CR3_PTR ( (reg8 *) CYREG_RESET_CR3 ) + +#endif /* (CY_PSOC5A) */ + +/* Power Mode Wakeup Trim Register 0 */ +#define CY_PM_PWRSYS_WAKE_TR0_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) +#define CY_PM_PWRSYS_WAKE_TR0_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) + +#if(CY_PSOC3) + + /* Power Mode Wakeup Trim Register 2 */ + #define CY_PM_PWRSYS_WAKE_TR2_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) + #define CY_PM_PWRSYS_WAKE_TR2_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) + +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5A) + + /* Power Mode Buzz Trim Register */ + #define CY_PM_PWRSYS_BUZZ_TR_REG (* (reg8 *) CYREG_PWRSYS_BUZZ_TR ) + #define CY_PM_PWRSYS_BUZZ_TR_PTR ( (reg8 *) CYREG_PWRSYS_BUZZ_TR ) + +#endif /* (CY_PSOC5A) */ + +/* Power Manager Interrupt Status Register */ +#define CY_PM_INT_SR_REG (* (reg8 *) CYREG_PM_INT_SR ) +#define CY_PM_INT_SR_PTR ( (reg8 *) CYREG_PM_INT_SR ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) +#define CY_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) + +/* Active Power Mode Configuration Register 1 */ +#define CY_PM_ACT_CFG1_REG (* (reg8 *) CYREG_PM_ACT_CFG1 ) +#define CY_PM_ACT_CFG1_PTR ( (reg8 *) CYREG_PM_ACT_CFG1 ) + +/* Active Power Mode Configuration Register 2 */ +#define CY_PM_ACT_CFG2_REG (* (reg8 *) CYREG_PM_ACT_CFG2 ) +#define CY_PM_ACT_CFG2_PTR ( (reg8 *) CYREG_PM_ACT_CFG2 ) + +/* Boost Control 1 */ +#define CY_PM_BOOST_CR1_REG (* (reg8 *) CYREG_BOOST_CR1 ) +#define CY_PM_BOOST_CR1_PTR ( (reg8 *) CYREG_BOOST_CR1 ) + +/* Timewheel Configuration Register 0 */ +#define CY_PM_TW_CFG0_REG (* (reg8 *) CYREG_PM_TW_CFG0 ) +#define CY_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0 ) + +/* Timewheel Configuration Register 1 */ +#define CY_PM_TW_CFG1_REG (* (reg8 *) CYREG_PM_TW_CFG1 ) +#define CY_PM_TW_CFG1_PTR ( (reg8 *) CYREG_PM_TW_CFG1 ) + +/* Timewheel Configuration Register 2 */ +#define CY_PM_TW_CFG2_REG (* (reg8 *) CYREG_PM_TW_CFG2 ) +#define CY_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2 ) + +/* PLL Status Register */ +#define CY_PM_FASTCLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR ) +#define CY_PM_FASTCLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR ) + +/* Internal Main Oscillator Control Register */ +#define CY_PM_FASTCLK_IMO_CR_REG (* (reg8 *) CYREG_FASTCLK_IMO_CR ) +#define CY_PM_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR ) + +/* PLL Configuration Register */ +#define CY_PM_FASTCLK_PLL_CFG0_REG (* (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) +#define CY_PM_FASTCLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) + +/* External 4-33 MHz Crystal Oscillator Status and Control Register */ +#define CY_PM_FASTCLK_XMHZ_CSR_REG (* (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) +#define CY_PM_FASTCLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) + +/* Delay block Configuration Register */ +#define CY_PM_CLKDIST_DELAY_REG (* (reg8 *) CYREG_CLKDIST_DLY1 ) +#define CY_PM_CLKDIST_DELAY_PTR ( (reg8 *) CYREG_CLKDIST_DLY1 ) + + +#if(CY_PSOC3) + + /* Cache Control Register */ + #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CR ) + #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CR ) + +#else /* Device is PSoC 5 */ + + /* Cache Control Register */ + #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) + #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC3 || CY_PSOC5LP) + + /* Power Mode Wakeup Mask Configuration Register 0 */ + #define CY_PM_WAKEUP_CFG0_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG0 ) + #define CY_PM_WAKEUP_CFG0_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG0 ) + + /* Power Mode Wakeup Mask Configuration Register 1 */ + #define CY_PM_WAKEUP_CFG1_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG1 ) + #define CY_PM_WAKEUP_CFG1_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG1 ) + + /* Power Mode Wakeup Mask Configuration Register 2 */ + #define CY_PM_WAKEUP_CFG2_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG2 ) + #define CY_PM_WAKEUP_CFG2_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG2 ) + +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +#if(CY_PSOC5A) + + /* Watchdog Timer Configuration Register */ + #define CY_PM_WDT_CFG_REG (* (reg8 *) CYREG_PM_WDT_CFG ) + #define CY_PM_WDT_CFG_PTR ( (reg8 *) CYREG_PM_WDT_CFG ) + +#endif /* (CY_PSOC5A) */ + + +/* Boost Control 2 */ +#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 ) +#define CY_PM_BOOST_CR2_PTR ( (reg8 *) CYREG_BOOST_CR2 ) + + +/*************************************** +* Register Constants +***************************************/ + +/* Internal Main Oscillator Control Register */ + +#define CY_PM_FASTCLK_IMO_CR_FREQ_MASK (0x07u) /* IMO frequency mask */ +#define CY_PM_FASTCLK_IMO_CR_FREQ_12MHZ (0x00u) /* IMO frequency 12 MHz */ +#define CY_PM_FASTCLK_IMO_CR_F2XON (0x10u) /* IMO doubler enable */ +#define CY_PM_FASTCLK_IMO_CR_USB (0x40u) /* IMO is in USB mode */ + +#define CY_PM_MASTER_CLK_SRC_IMO (0u) +#define CY_PM_MASTER_CLK_SRC_PLL (1u) +#define CY_PM_MASTER_CLK_SRC_XTAL (2u) +#define CY_PM_MASTER_CLK_SRC_DSI (3u) +#define CY_PM_MASTER_CLK_SRC_MASK (3u) + +#define CY_PM_PLL_CFG0_ENABLE (0x01u) /* PLL enable */ +#define CY_PM_PLL_STATUS_LOCK (0x01u) /* PLL Lock Status */ +#define CY_PM_XMHZ_CSR_ENABLE (0x01u) /* Enable X MHz OSC */ +#define CY_PM_XMHZ_CSR_XERR (0x80u) /* High indicates failure */ +#define CY_PM_BOOST_ENABLE (0x08u) /* Boost enable */ +#define CY_PM_ILO_CR0_EN_1K (0x02u) /* Enable 1kHz ILO */ +#define CY_PM_ILO_CR0_EN_100K (0x04u) /* Enable 100kHz ILO */ +#define CY_PM_ILO_CR0_PD_MODE (0x10u) /* Power down mode for ILO*/ +#define CY_PM_X32_CR_X32EN (0x01u) /* Enable 32kHz OSC */ + +#define CY_PM_CTW_IE (0x08u) /* CTW interrupt enable */ +#define CY_PM_CTW_EN (0x04u) /* CTW enable */ +#define CY_PM_FTW_IE (0x02u) /* FTW interrupt enable */ +#define CY_PM_FTW_EN (0x01u) /* FTW enable */ +#define CY_PM_1PPS_EN (0x10u) /* 1PPS enable */ +#define CY_PM_1PPS_IE (0x20u) /* 1PPS interrupt enable */ + + +#define CY_PM_ACT_EN_CLK_A_MASK (0x0Fu) +#define CY_PM_ACT_EN_CLK_D_MASK (0xFFu) + +#define CY_PM_DIV_BY_ONE (0x00u) + +/* Internal Main Oscillator Control Register */ +#define CY_PM_FASTCLK_IMO_CR_XCLKEN (0x20u) + +/* Clock distribution configuration Register */ +#define CY_PM_CLKDIST_IMO_OUT_MASK (0x30u) +#define CY_PM_CLKDIST_IMO_OUT_IMO (0x00u) +#define CY_PM_CLKDIST_IMO2X_SRC (0x40u) + +/* Waiting for the hibernate/sleep regulator to stabilize */ +#define CY_PM_MODE_CSR_PWRUP_PULSE_Q (0x08u) + +#define CY_PM_MODE_CSR_ACTIVE (0x00u) /* Active power mode */ +#define CY_PM_MODE_CSR_ALT_ACT (0x01u) /* Alternate Active power */ +#define CY_PM_MODE_CSR_SLEEP (0x03u) /* Sleep power mode */ +#define CY_PM_MODE_CSR_HIBERNATE (0x04u) /* Hibernate power mode */ +#define CY_PM_MODE_CSR_MASK (0x07u) + +/* I2C regulator backup enable */ +#define CY_PM_PWRSYS_CR1_I2CREG_BACKUP (0x04u) + +/* When set, prepares the system to disable the LDO-A */ +#define CY_PM_PWRSYS_CR1_LDOA_ISO (0x01u) + +/* When set, disables the analog LDO regulator */ +#define CY_PM_PWRSYS_CR1_LDOA_DIS (0x02u) + +#define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET (0x04u) + +#define CY_PM_FTW_INT (0x01u) /* FTW event has occured */ +#define CY_PM_CTW_INT (0x02u) /* CTW event has occured */ +#define CY_PM_ONEPPS_INT (0x04u) /* 1PPS event has occured */ + +/* Active Power Mode Configuration Register 0 */ +#define CY_PM_ACT_CFG0_IMO (0x10u) /* IMO enable in Active */ + +/* Cache Control Register (same mask for all device revisions) */ +#define CY_PM_CACHE_CR_CYCLES_MASK (0xC0u) + +/* Bus Clock divider to divide-by-one */ +#define CY_PM_BUS_CLK_DIV_BY_ONE (0x00u) + +/* HVI/LVI feature on the external analog and digital supply mask */ +#define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u) + +/* The high-voltage-interrupt feature on the external analog supply */ +#define CY_PM_RESET_CR1_HVIA_EN (0x04u) + +/* The low-voltage-interrupt feature on the external analog supply */ +#define CY_PM_RESET_CR1_LVIA_EN (0x02u) + +/* The low-voltage-interrupt feature on the external digital supply */ +#define CY_PM_RESET_CR1_LVID_EN (0x01u) + +#if(CY_PSOC5A) + + /* Partly disables PRES-A and PRES-D circuits */ + #define CY_PM_RESET_CR1_DIS_PRES1 (0x10u) + + /* Partly disables PRES-A and PRES-D circuits */ + #define CY_PM_RESET_CR3_DIS_PRES2 (0x08u) + +#endif /* (CY_PSOC5A) */ + +/* Allows the system to program delays on clk_sync_d */ +#define CY_PM_CLKDIST_DELAY_EN (0x04u) + + +#if(CY_PSOC3 || CY_PSOC5LP) + + #define CY_PM_WAKEUP_SRC_CMPS_MASK (0x000Fu) + + /* Holdoff mask sleep trim */ + #define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK (0x1Fu) + +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +#if(CY_PSOC3) + + /* CPU clock divider mask */ + #define CY_PM_CLKDIST_CPU_DIV_MASK (0xF0u) + + /* Serial Wire View (SWV) clock enable */ + #define CY_PM_MLOGIC_DBG_SWV_CLK_EN (0x04u) + + /* Port drive mode */ + #define CY_PM_PRT1_PC3_DM_MASK (0xf1u) + + /* Mode 6, stong pull-up, strong pull-down */ + #define CY_PM_PRT1_PC3_DM_STRONG (0x0Cu) + + /* When set, enables buzz wakeups */ + #define CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ (0x01u) + +#endif /* (CY_PSOC3) */ + + +#if(!CY_PSOC5A) + + /* Disable the sleep regulator and shorts vccd to vpwrsleep */ + #define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u) + +#endif /* (!CY_PSOC5A) */ + + +#if(CY_PSOC5A) + + #define CY_PM_PWRSYS_BUZZ_TR_512_TICKS (0x08u) + #define CY_PM_PWRSYS_BUZZ_TR_MASK (0xF0u) + +#endif /* (CY_PSOC5A) */ + + +#if(CY_PSOC5A) + + /* Watchdog Timer Configuration Register */ + #define CY_PM_WDT_CFG_CTW_RESET (0x80u) + + /*************************************************************************** + * The PICU interrupt type registers are divided into three sections where + * the registers addresses are consecutive. + ***************************************************************************/ + #define CY_PM_PICU_0_6_INT_BASE (CYDEV_PICU_INTTYPE_PICU0_BASE ) + #define CY_PM_PICU_12_INT_BASE (CYDEV_PICU_INTTYPE_PICU12_BASE) + #define CY_PM_PICU_15_INT_BASE (CYDEV_PICU_INTTYPE_PICU15_BASE) + + #define CY_PM_PICU_0_6_INT_SIZE (CYDEV_PICU_INTTYPE_PICU0_SIZE + CYDEV_PICU_INTTYPE_PICU1_SIZE + \ + CYDEV_PICU_INTTYPE_PICU2_SIZE + CYDEV_PICU_INTTYPE_PICU3_SIZE + \ + CYDEV_PICU_INTTYPE_PICU4_SIZE + CYDEV_PICU_INTTYPE_PICU5_SIZE + \ + CYDEV_PICU_INTTYPE_PICU6_SIZE) + #define CY_PM_PICU_12_INT_SIZE (CYDEV_PICU_INTTYPE_PICU12_SIZE) + #define CY_PM_PICU_15_INT_SIZE (CYDEV_PICU_INTTYPE_PICU15_SIZE) + +#endif /* (CY_PSOC5A) */ + +/* Boost Control 2: Select external precision reference */ +#define CY_PM_BOOST_CR2_EREFSEL_EXT (0x08u) + + + +#if(CY_PSOC3) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0x90u) + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC5LP) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0xB0u) + +#endif /* (CY_PSOC5LP) */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 +*******************************************************************************/ +#if(CY_PSOC3) + + /* Was removed as redundant */ + #define CY_PM_FTW_INTERVAL_MASK (0xFFu) + +#endif /* (CY_PSOC3) */ + +/* Was removed as redundant */ +#define CY_PM_CTW_INTERVAL_MASK (0x0Fu) + +#endif /* (CY_BOOT_CYPM_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h new file mode 100644 index 0000000..dd8b331 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h @@ -0,0 +1,5359 @@ +/******************************************************************************* +* FILENAME: cydevice.h +* OBSOLETE: Do not use this file. Use the _trm version instead. +* PSoC Creator 2.2 Component Pack 6 +* +* DESCRIPTION: +* This file provides all of the address values for the entire PSoC device. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CYDEVICE_H) +#define CYDEVICE_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00040000u +#define CYDEV_FLASH_DATA_MBASE 0x00000000u +#define CYDEV_FLASH_DATA_MSIZE 0x00040000u +#define CYDEV_SRAM_BASE 0x1fff8000u +#define CYDEV_SRAM_SIZE 0x00010000u +#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000u +#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000u +#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000u +#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000u +#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000u +#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000u +#define CYDEV_SRAM_CODE_MBASE 0x1fff8000u +#define CYDEV_SRAM_CODE_MSIZE 0x00008000u +#define CYDEV_SRAM_DATA_MBASE 0x20000000u +#define CYDEV_SRAM_DATA_MSIZE 0x00008000u +#define CYDEV_SRAM_DATA16K_MBASE 0x20001000u +#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000u +#define CYDEV_SRAM_DATA32K_MBASE 0x20002000u +#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000u +#define CYDEV_SRAM_DATA64K_MBASE 0x20004000u +#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000u +#define CYDEV_DMA_BASE 0x20008000u +#define CYDEV_DMA_SIZE 0x00008000u +#define CYDEV_DMA_SRAM64K_MBASE 0x20008000u +#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000u +#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000u +#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000u +#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000u +#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000u +#define CYDEV_DMA_SRAM_MBASE 0x2000f000u +#define CYDEV_DMA_SRAM_MSIZE 0x00001000u +#define CYDEV_CLKDIST_BASE 0x40004000u +#define CYDEV_CLKDIST_SIZE 0x00000110u +#define CYDEV_CLKDIST_CR 0x40004000u +#define CYDEV_CLKDIST_LD 0x40004001u +#define CYDEV_CLKDIST_WRK0 0x40004002u +#define CYDEV_CLKDIST_WRK1 0x40004003u +#define CYDEV_CLKDIST_MSTR0 0x40004004u +#define CYDEV_CLKDIST_MSTR1 0x40004005u +#define CYDEV_CLKDIST_BCFG0 0x40004006u +#define CYDEV_CLKDIST_BCFG1 0x40004007u +#define CYDEV_CLKDIST_BCFG2 0x40004008u +#define CYDEV_CLKDIST_UCFG 0x40004009u +#define CYDEV_CLKDIST_DLY0 0x4000400au +#define CYDEV_CLKDIST_DLY1 0x4000400bu +#define CYDEV_CLKDIST_DMASK 0x40004010u +#define CYDEV_CLKDIST_AMASK 0x40004014u +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080u +#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081u +#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082u +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084u +#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085u +#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086u +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088u +#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089u +#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408au +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408du +#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408eu +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090u +#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091u +#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092u +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094u +#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095u +#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096u +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098u +#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099u +#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409au +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409du +#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409eu +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100u +#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101u +#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102u +#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103u +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104u +#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105u +#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106u +#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107u +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108u +#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109u +#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410au +#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410bu +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410du +#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410eu +#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410fu +#define CYDEV_FASTCLK_BASE 0x40004200u +#define CYDEV_FASTCLK_SIZE 0x00000026u +#define CYDEV_FASTCLK_IMO_BASE 0x40004200u +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u +#define CYDEV_FASTCLK_IMO_CR 0x40004200u +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u +#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210u +#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212u +#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213u +#define CYDEV_FASTCLK_PLL_BASE 0x40004220u +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u +#define CYDEV_FASTCLK_PLL_CFG0 0x40004220u +#define CYDEV_FASTCLK_PLL_CFG1 0x40004221u +#define CYDEV_FASTCLK_PLL_P 0x40004222u +#define CYDEV_FASTCLK_PLL_Q 0x40004223u +#define CYDEV_FASTCLK_PLL_SR 0x40004225u +#define CYDEV_SLOWCLK_BASE 0x40004300u +#define CYDEV_SLOWCLK_SIZE 0x0000000bu +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u +#define CYDEV_SLOWCLK_ILO_CR0 0x40004300u +#define CYDEV_SLOWCLK_ILO_CR1 0x40004301u +#define CYDEV_SLOWCLK_X32_BASE 0x40004308u +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u +#define CYDEV_SLOWCLK_X32_CR 0x40004308u +#define CYDEV_SLOWCLK_X32_CFG 0x40004309u +#define CYDEV_SLOWCLK_X32_TST 0x4000430au +#define CYDEV_BOOST_BASE 0x40004320u +#define CYDEV_BOOST_SIZE 0x00000007u +#define CYDEV_BOOST_CR0 0x40004320u +#define CYDEV_BOOST_CR1 0x40004321u +#define CYDEV_BOOST_CR2 0x40004322u +#define CYDEV_BOOST_CR3 0x40004323u +#define CYDEV_BOOST_SR 0x40004324u +#define CYDEV_BOOST_CR4 0x40004325u +#define CYDEV_BOOST_SR2 0x40004326u +#define CYDEV_PWRSYS_BASE 0x40004330u +#define CYDEV_PWRSYS_SIZE 0x00000002u +#define CYDEV_PWRSYS_CR0 0x40004330u +#define CYDEV_PWRSYS_CR1 0x40004331u +#define CYDEV_PM_BASE 0x40004380u +#define CYDEV_PM_SIZE 0x00000057u +#define CYDEV_PM_TW_CFG0 0x40004380u +#define CYDEV_PM_TW_CFG1 0x40004381u +#define CYDEV_PM_TW_CFG2 0x40004382u +#define CYDEV_PM_WDT_CFG 0x40004383u +#define CYDEV_PM_WDT_CR 0x40004384u +#define CYDEV_PM_INT_SR 0x40004390u +#define CYDEV_PM_MODE_CFG0 0x40004391u +#define CYDEV_PM_MODE_CFG1 0x40004392u +#define CYDEV_PM_MODE_CSR 0x40004393u +#define CYDEV_PM_USB_CR0 0x40004394u +#define CYDEV_PM_WAKEUP_CFG0 0x40004398u +#define CYDEV_PM_WAKEUP_CFG1 0x40004399u +#define CYDEV_PM_WAKEUP_CFG2 0x4000439au +#define CYDEV_PM_ACT_BASE 0x400043a0u +#define CYDEV_PM_ACT_SIZE 0x0000000eu +#define CYDEV_PM_ACT_CFG0 0x400043a0u +#define CYDEV_PM_ACT_CFG1 0x400043a1u +#define CYDEV_PM_ACT_CFG2 0x400043a2u +#define CYDEV_PM_ACT_CFG3 0x400043a3u +#define CYDEV_PM_ACT_CFG4 0x400043a4u +#define CYDEV_PM_ACT_CFG5 0x400043a5u +#define CYDEV_PM_ACT_CFG6 0x400043a6u +#define CYDEV_PM_ACT_CFG7 0x400043a7u +#define CYDEV_PM_ACT_CFG8 0x400043a8u +#define CYDEV_PM_ACT_CFG9 0x400043a9u +#define CYDEV_PM_ACT_CFG10 0x400043aau +#define CYDEV_PM_ACT_CFG11 0x400043abu +#define CYDEV_PM_ACT_CFG12 0x400043acu +#define CYDEV_PM_ACT_CFG13 0x400043adu +#define CYDEV_PM_STBY_BASE 0x400043b0u +#define CYDEV_PM_STBY_SIZE 0x0000000eu +#define CYDEV_PM_STBY_CFG0 0x400043b0u +#define CYDEV_PM_STBY_CFG1 0x400043b1u +#define CYDEV_PM_STBY_CFG2 0x400043b2u +#define CYDEV_PM_STBY_CFG3 0x400043b3u +#define CYDEV_PM_STBY_CFG4 0x400043b4u +#define CYDEV_PM_STBY_CFG5 0x400043b5u +#define CYDEV_PM_STBY_CFG6 0x400043b6u +#define CYDEV_PM_STBY_CFG7 0x400043b7u +#define CYDEV_PM_STBY_CFG8 0x400043b8u +#define CYDEV_PM_STBY_CFG9 0x400043b9u +#define CYDEV_PM_STBY_CFG10 0x400043bau +#define CYDEV_PM_STBY_CFG11 0x400043bbu +#define CYDEV_PM_STBY_CFG12 0x400043bcu +#define CYDEV_PM_STBY_CFG13 0x400043bdu +#define CYDEV_PM_AVAIL_BASE 0x400043c0u +#define CYDEV_PM_AVAIL_SIZE 0x00000017u +#define CYDEV_PM_AVAIL_CR0 0x400043c0u +#define CYDEV_PM_AVAIL_CR1 0x400043c1u +#define CYDEV_PM_AVAIL_CR2 0x400043c2u +#define CYDEV_PM_AVAIL_CR3 0x400043c3u +#define CYDEV_PM_AVAIL_CR4 0x400043c4u +#define CYDEV_PM_AVAIL_CR5 0x400043c5u +#define CYDEV_PM_AVAIL_CR6 0x400043c6u +#define CYDEV_PM_AVAIL_SR0 0x400043d0u +#define CYDEV_PM_AVAIL_SR1 0x400043d1u +#define CYDEV_PM_AVAIL_SR2 0x400043d2u +#define CYDEV_PM_AVAIL_SR3 0x400043d3u +#define CYDEV_PM_AVAIL_SR4 0x400043d4u +#define CYDEV_PM_AVAIL_SR5 0x400043d5u +#define CYDEV_PM_AVAIL_SR6 0x400043d6u +#define CYDEV_PICU_BASE 0x40004500u +#define CYDEV_PICU_SIZE 0x000000b0u +#define CYDEV_PICU_INTTYPE_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507u +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450au +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450bu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450cu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450du +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450eu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450fu +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517u +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451au +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451bu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451cu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451du +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451eu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451fu +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527u +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452au +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452bu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452cu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452du +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452eu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452fu +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537u +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567u +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457au +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457bu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457cu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457du +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457eu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457fu +#define CYDEV_PICU_STAT_BASE 0x40004580u +#define CYDEV_PICU_STAT_SIZE 0x00000010u +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580u +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581u +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582u +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583u +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584u +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585u +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586u +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458cu +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458fu +#define CYDEV_PICU_SNAP_BASE 0x40004590u +#define CYDEV_PICU_SNAP_SIZE 0x00000010u +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590u +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591u +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592u +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593u +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594u +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595u +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596u +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459cu +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459fu +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045afu +#define CYDEV_MFGCFG_BASE 0x40004600u +#define CYDEV_MFGCFG_SIZE 0x000000edu +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612u +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627u +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631u +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633u +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635u +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637u +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu +#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681u +#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682u +#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683u +#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686u +#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687u +#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468au +#define CYDEV_MFGCFG_ILO_BASE 0x40004690u +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u +#define CYDEV_MFGCFG_ILO_TR0 0x40004690u +#define CYDEV_MFGCFG_ILO_TR1 0x40004691u +#define CYDEV_MFGCFG_X32_BASE 0x40004698u +#define CYDEV_MFGCFG_X32_SIZE 0x00000001u +#define CYDEV_MFGCFG_X32_TR 0x40004698u +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u +#define CYDEV_MFGCFG_IMO_TR0 0x400046a0u +#define CYDEV_MFGCFG_IMO_TR1 0x400046a1u +#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2u +#define CYDEV_MFGCFG_IMO_C36M 0x400046a3u +#define CYDEV_MFGCFG_IMO_TR2 0x400046a4u +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u +#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8u +#define CYDEV_MFGCFG_DLY 0x400046c0u +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du +#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2u +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u +#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5u +#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ecu +#define CYDEV_RESET_BASE 0x400046f0u +#define CYDEV_RESET_SIZE 0x0000000fu +#define CYDEV_RESET_IPOR_CR0 0x400046f0u +#define CYDEV_RESET_IPOR_CR1 0x400046f1u +#define CYDEV_RESET_IPOR_CR2 0x400046f2u +#define CYDEV_RESET_IPOR_CR3 0x400046f3u +#define CYDEV_RESET_CR0 0x400046f4u +#define CYDEV_RESET_CR1 0x400046f5u +#define CYDEV_RESET_CR2 0x400046f6u +#define CYDEV_RESET_CR3 0x400046f7u +#define CYDEV_RESET_CR4 0x400046f8u +#define CYDEV_RESET_CR5 0x400046f9u +#define CYDEV_RESET_SR0 0x400046fau +#define CYDEV_RESET_SR1 0x400046fbu +#define CYDEV_RESET_SR2 0x400046fcu +#define CYDEV_RESET_SR3 0x400046fdu +#define CYDEV_RESET_TR 0x400046feu +#define CYDEV_SPC_BASE 0x40004700u +#define CYDEV_SPC_SIZE 0x00000100u +#define CYDEV_SPC_FM_EE_CR 0x40004700u +#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701u +#define CYDEV_SPC_EE_SCR 0x40004702u +#define CYDEV_SPC_EE_ERR 0x40004703u +#define CYDEV_SPC_CPU_DATA 0x40004720u +#define CYDEV_SPC_DMA_DATA 0x40004721u +#define CYDEV_SPC_SR 0x40004722u +#define CYDEV_SPC_CR 0x40004723u +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u +#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u +#define CYDEV_CACHE_BASE 0x40004800u +#define CYDEV_CACHE_SIZE 0x0000009cu +#define CYDEV_CACHE_CC_CTL 0x40004800u +#define CYDEV_CACHE_ECC_CORR 0x40004880u +#define CYDEV_CACHE_ECC_ERR 0x40004888u +#define CYDEV_CACHE_FLASH_ERR 0x40004890u +#define CYDEV_CACHE_HITMISS 0x40004898u +#define CYDEV_I2C_BASE 0x40004900u +#define CYDEV_I2C_SIZE 0x000000e1u +#define CYDEV_I2C_XCFG 0x400049c8u +#define CYDEV_I2C_ADR 0x400049cau +#define CYDEV_I2C_CFG 0x400049d6u +#define CYDEV_I2C_CSR 0x400049d7u +#define CYDEV_I2C_D 0x400049d8u +#define CYDEV_I2C_MCSR 0x400049d9u +#define CYDEV_I2C_CLK_DIV1 0x400049dbu +#define CYDEV_I2C_CLK_DIV2 0x400049dcu +#define CYDEV_I2C_TMOUT_CSR 0x400049ddu +#define CYDEV_I2C_TMOUT_SR 0x400049deu +#define CYDEV_I2C_TMOUT_CFG0 0x400049dfu +#define CYDEV_I2C_TMOUT_CFG1 0x400049e0u +#define CYDEV_DEC_BASE 0x40004e00u +#define CYDEV_DEC_SIZE 0x00000015u +#define CYDEV_DEC_CR 0x40004e00u +#define CYDEV_DEC_SR 0x40004e01u +#define CYDEV_DEC_SHIFT1 0x40004e02u +#define CYDEV_DEC_SHIFT2 0x40004e03u +#define CYDEV_DEC_DR2 0x40004e04u +#define CYDEV_DEC_DR2H 0x40004e05u +#define CYDEV_DEC_DR1 0x40004e06u +#define CYDEV_DEC_OCOR 0x40004e08u +#define CYDEV_DEC_OCORM 0x40004e09u +#define CYDEV_DEC_OCORH 0x40004e0au +#define CYDEV_DEC_GCOR 0x40004e0cu +#define CYDEV_DEC_GCORH 0x40004e0du +#define CYDEV_DEC_GVAL 0x40004e0eu +#define CYDEV_DEC_OUTSAMP 0x40004e10u +#define CYDEV_DEC_OUTSAMPM 0x40004e11u +#define CYDEV_DEC_OUTSAMPH 0x40004e12u +#define CYDEV_DEC_OUTSAMPS 0x40004e13u +#define CYDEV_DEC_COHER 0x40004e14u +#define CYDEV_TMR0_BASE 0x40004f00u +#define CYDEV_TMR0_SIZE 0x0000000cu +#define CYDEV_TMR0_CFG0 0x40004f00u +#define CYDEV_TMR0_CFG1 0x40004f01u +#define CYDEV_TMR0_CFG2 0x40004f02u +#define CYDEV_TMR0_SR0 0x40004f03u +#define CYDEV_TMR0_PER0 0x40004f04u +#define CYDEV_TMR0_PER1 0x40004f05u +#define CYDEV_TMR0_CNT_CMP0 0x40004f06u +#define CYDEV_TMR0_CNT_CMP1 0x40004f07u +#define CYDEV_TMR0_CAP0 0x40004f08u +#define CYDEV_TMR0_CAP1 0x40004f09u +#define CYDEV_TMR0_RT0 0x40004f0au +#define CYDEV_TMR0_RT1 0x40004f0bu +#define CYDEV_TMR1_BASE 0x40004f0cu +#define CYDEV_TMR1_SIZE 0x0000000cu +#define CYDEV_TMR1_CFG0 0x40004f0cu +#define CYDEV_TMR1_CFG1 0x40004f0du +#define CYDEV_TMR1_CFG2 0x40004f0eu +#define CYDEV_TMR1_SR0 0x40004f0fu +#define CYDEV_TMR1_PER0 0x40004f10u +#define CYDEV_TMR1_PER1 0x40004f11u +#define CYDEV_TMR1_CNT_CMP0 0x40004f12u +#define CYDEV_TMR1_CNT_CMP1 0x40004f13u +#define CYDEV_TMR1_CAP0 0x40004f14u +#define CYDEV_TMR1_CAP1 0x40004f15u +#define CYDEV_TMR1_RT0 0x40004f16u +#define CYDEV_TMR1_RT1 0x40004f17u +#define CYDEV_TMR2_BASE 0x40004f18u +#define CYDEV_TMR2_SIZE 0x0000000cu +#define CYDEV_TMR2_CFG0 0x40004f18u +#define CYDEV_TMR2_CFG1 0x40004f19u +#define CYDEV_TMR2_CFG2 0x40004f1au +#define CYDEV_TMR2_SR0 0x40004f1bu +#define CYDEV_TMR2_PER0 0x40004f1cu +#define CYDEV_TMR2_PER1 0x40004f1du +#define CYDEV_TMR2_CNT_CMP0 0x40004f1eu +#define CYDEV_TMR2_CNT_CMP1 0x40004f1fu +#define CYDEV_TMR2_CAP0 0x40004f20u +#define CYDEV_TMR2_CAP1 0x40004f21u +#define CYDEV_TMR2_RT0 0x40004f22u +#define CYDEV_TMR2_RT1 0x40004f23u +#define CYDEV_TMR3_BASE 0x40004f24u +#define CYDEV_TMR3_SIZE 0x0000000cu +#define CYDEV_TMR3_CFG0 0x40004f24u +#define CYDEV_TMR3_CFG1 0x40004f25u +#define CYDEV_TMR3_CFG2 0x40004f26u +#define CYDEV_TMR3_SR0 0x40004f27u +#define CYDEV_TMR3_PER0 0x40004f28u +#define CYDEV_TMR3_PER1 0x40004f29u +#define CYDEV_TMR3_CNT_CMP0 0x40004f2au +#define CYDEV_TMR3_CNT_CMP1 0x40004f2bu +#define CYDEV_TMR3_CAP0 0x40004f2cu +#define CYDEV_TMR3_CAP1 0x40004f2du +#define CYDEV_TMR3_RT0 0x40004f2eu +#define CYDEV_TMR3_RT1 0x40004f2fu +#define CYDEV_IO_BASE 0x40005000u +#define CYDEV_IO_SIZE 0x00000200u +#define CYDEV_IO_PC_BASE 0x40005000u +#define CYDEV_IO_PC_SIZE 0x00000080u +#define CYDEV_IO_PC_PRT0_BASE 0x40005000u +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT0_PC0 0x40005000u +#define CYDEV_IO_PC_PRT0_PC1 0x40005001u +#define CYDEV_IO_PC_PRT0_PC2 0x40005002u +#define CYDEV_IO_PC_PRT0_PC3 0x40005003u +#define CYDEV_IO_PC_PRT0_PC4 0x40005004u +#define CYDEV_IO_PC_PRT0_PC5 0x40005005u +#define CYDEV_IO_PC_PRT0_PC6 0x40005006u +#define CYDEV_IO_PC_PRT0_PC7 0x40005007u +#define CYDEV_IO_PC_PRT1_BASE 0x40005008u +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT1_PC0 0x40005008u +#define CYDEV_IO_PC_PRT1_PC1 0x40005009u +#define CYDEV_IO_PC_PRT1_PC2 0x4000500au +#define CYDEV_IO_PC_PRT1_PC3 0x4000500bu +#define CYDEV_IO_PC_PRT1_PC4 0x4000500cu +#define CYDEV_IO_PC_PRT1_PC5 0x4000500du +#define CYDEV_IO_PC_PRT1_PC6 0x4000500eu +#define CYDEV_IO_PC_PRT1_PC7 0x4000500fu +#define CYDEV_IO_PC_PRT2_BASE 0x40005010u +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT2_PC0 0x40005010u +#define CYDEV_IO_PC_PRT2_PC1 0x40005011u +#define CYDEV_IO_PC_PRT2_PC2 0x40005012u +#define CYDEV_IO_PC_PRT2_PC3 0x40005013u +#define CYDEV_IO_PC_PRT2_PC4 0x40005014u +#define CYDEV_IO_PC_PRT2_PC5 0x40005015u +#define CYDEV_IO_PC_PRT2_PC6 0x40005016u +#define CYDEV_IO_PC_PRT2_PC7 0x40005017u +#define CYDEV_IO_PC_PRT3_BASE 0x40005018u +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT3_PC0 0x40005018u +#define CYDEV_IO_PC_PRT3_PC1 0x40005019u +#define CYDEV_IO_PC_PRT3_PC2 0x4000501au +#define CYDEV_IO_PC_PRT3_PC3 0x4000501bu +#define CYDEV_IO_PC_PRT3_PC4 0x4000501cu +#define CYDEV_IO_PC_PRT3_PC5 0x4000501du +#define CYDEV_IO_PC_PRT3_PC6 0x4000501eu +#define CYDEV_IO_PC_PRT3_PC7 0x4000501fu +#define CYDEV_IO_PC_PRT4_BASE 0x40005020u +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT4_PC0 0x40005020u +#define CYDEV_IO_PC_PRT4_PC1 0x40005021u +#define CYDEV_IO_PC_PRT4_PC2 0x40005022u +#define CYDEV_IO_PC_PRT4_PC3 0x40005023u +#define CYDEV_IO_PC_PRT4_PC4 0x40005024u +#define CYDEV_IO_PC_PRT4_PC5 0x40005025u +#define CYDEV_IO_PC_PRT4_PC6 0x40005026u +#define CYDEV_IO_PC_PRT4_PC7 0x40005027u +#define CYDEV_IO_PC_PRT5_BASE 0x40005028u +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT5_PC0 0x40005028u +#define CYDEV_IO_PC_PRT5_PC1 0x40005029u +#define CYDEV_IO_PC_PRT5_PC2 0x4000502au +#define CYDEV_IO_PC_PRT5_PC3 0x4000502bu +#define CYDEV_IO_PC_PRT5_PC4 0x4000502cu +#define CYDEV_IO_PC_PRT5_PC5 0x4000502du +#define CYDEV_IO_PC_PRT5_PC6 0x4000502eu +#define CYDEV_IO_PC_PRT5_PC7 0x4000502fu +#define CYDEV_IO_PC_PRT6_BASE 0x40005030u +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT6_PC0 0x40005030u +#define CYDEV_IO_PC_PRT6_PC1 0x40005031u +#define CYDEV_IO_PC_PRT6_PC2 0x40005032u +#define CYDEV_IO_PC_PRT6_PC3 0x40005033u +#define CYDEV_IO_PC_PRT6_PC4 0x40005034u +#define CYDEV_IO_PC_PRT6_PC5 0x40005035u +#define CYDEV_IO_PC_PRT6_PC6 0x40005036u +#define CYDEV_IO_PC_PRT6_PC7 0x40005037u +#define CYDEV_IO_PC_PRT12_BASE 0x40005060u +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT12_PC0 0x40005060u +#define CYDEV_IO_PC_PRT12_PC1 0x40005061u +#define CYDEV_IO_PC_PRT12_PC2 0x40005062u +#define CYDEV_IO_PC_PRT12_PC3 0x40005063u +#define CYDEV_IO_PC_PRT12_PC4 0x40005064u +#define CYDEV_IO_PC_PRT12_PC5 0x40005065u +#define CYDEV_IO_PC_PRT12_PC6 0x40005066u +#define CYDEV_IO_PC_PRT12_PC7 0x40005067u +#define CYDEV_IO_PC_PRT15_BASE 0x40005078u +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u +#define CYDEV_IO_PC_PRT15_PC0 0x40005078u +#define CYDEV_IO_PC_PRT15_PC1 0x40005079u +#define CYDEV_IO_PC_PRT15_PC2 0x4000507au +#define CYDEV_IO_PC_PRT15_PC3 0x4000507bu +#define CYDEV_IO_PC_PRT15_PC4 0x4000507cu +#define CYDEV_IO_PC_PRT15_PC5 0x4000507du +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u +#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507fu +#define CYDEV_IO_DR_BASE 0x40005080u +#define CYDEV_IO_DR_SIZE 0x00000010u +#define CYDEV_IO_DR_PRT0_BASE 0x40005080u +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080u +#define CYDEV_IO_DR_PRT1_BASE 0x40005081u +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081u +#define CYDEV_IO_DR_PRT2_BASE 0x40005082u +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082u +#define CYDEV_IO_DR_PRT3_BASE 0x40005083u +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083u +#define CYDEV_IO_DR_PRT4_BASE 0x40005084u +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084u +#define CYDEV_IO_DR_PRT5_BASE 0x40005085u +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085u +#define CYDEV_IO_DR_PRT6_BASE 0x40005086u +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086u +#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508cu +#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508fu +#define CYDEV_IO_PS_BASE 0x40005090u +#define CYDEV_IO_PS_SIZE 0x00000010u +#define CYDEV_IO_PS_PRT0_BASE 0x40005090u +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090u +#define CYDEV_IO_PS_PRT1_BASE 0x40005091u +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091u +#define CYDEV_IO_PS_PRT2_BASE 0x40005092u +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092u +#define CYDEV_IO_PS_PRT3_BASE 0x40005093u +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093u +#define CYDEV_IO_PS_PRT4_BASE 0x40005094u +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094u +#define CYDEV_IO_PS_PRT5_BASE 0x40005095u +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095u +#define CYDEV_IO_PS_PRT6_BASE 0x40005096u +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096u +#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509cu +#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509fu +#define CYDEV_IO_PRT_BASE 0x40005100u +#define CYDEV_IO_PRT_SIZE 0x00000100u +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT0_DR 0x40005100u +#define CYDEV_IO_PRT_PRT0_PS 0x40005101u +#define CYDEV_IO_PRT_PRT0_DM0 0x40005102u +#define CYDEV_IO_PRT_PRT0_DM1 0x40005103u +#define CYDEV_IO_PRT_PRT0_DM2 0x40005104u +#define CYDEV_IO_PRT_PRT0_SLW 0x40005105u +#define CYDEV_IO_PRT_PRT0_BYP 0x40005106u +#define CYDEV_IO_PRT_PRT0_BIE 0x40005107u +#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108u +#define CYDEV_IO_PRT_PRT0_CTL 0x40005109u +#define CYDEV_IO_PRT_PRT0_PRT 0x4000510au +#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510bu +#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510cu +#define CYDEV_IO_PRT_PRT0_AG 0x4000510du +#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510eu +#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510fu +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT1_DR 0x40005110u +#define CYDEV_IO_PRT_PRT1_PS 0x40005111u +#define CYDEV_IO_PRT_PRT1_DM0 0x40005112u +#define CYDEV_IO_PRT_PRT1_DM1 0x40005113u +#define CYDEV_IO_PRT_PRT1_DM2 0x40005114u +#define CYDEV_IO_PRT_PRT1_SLW 0x40005115u +#define CYDEV_IO_PRT_PRT1_BYP 0x40005116u +#define CYDEV_IO_PRT_PRT1_BIE 0x40005117u +#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118u +#define CYDEV_IO_PRT_PRT1_CTL 0x40005119u +#define CYDEV_IO_PRT_PRT1_PRT 0x4000511au +#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511bu +#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511cu +#define CYDEV_IO_PRT_PRT1_AG 0x4000511du +#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511eu +#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511fu +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT2_DR 0x40005120u +#define CYDEV_IO_PRT_PRT2_PS 0x40005121u +#define CYDEV_IO_PRT_PRT2_DM0 0x40005122u +#define CYDEV_IO_PRT_PRT2_DM1 0x40005123u +#define CYDEV_IO_PRT_PRT2_DM2 0x40005124u +#define CYDEV_IO_PRT_PRT2_SLW 0x40005125u +#define CYDEV_IO_PRT_PRT2_BYP 0x40005126u +#define CYDEV_IO_PRT_PRT2_BIE 0x40005127u +#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128u +#define CYDEV_IO_PRT_PRT2_CTL 0x40005129u +#define CYDEV_IO_PRT_PRT2_PRT 0x4000512au +#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512bu +#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512cu +#define CYDEV_IO_PRT_PRT2_AG 0x4000512du +#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512eu +#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512fu +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT3_DR 0x40005130u +#define CYDEV_IO_PRT_PRT3_PS 0x40005131u +#define CYDEV_IO_PRT_PRT3_DM0 0x40005132u +#define CYDEV_IO_PRT_PRT3_DM1 0x40005133u +#define CYDEV_IO_PRT_PRT3_DM2 0x40005134u +#define CYDEV_IO_PRT_PRT3_SLW 0x40005135u +#define CYDEV_IO_PRT_PRT3_BYP 0x40005136u +#define CYDEV_IO_PRT_PRT3_BIE 0x40005137u +#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138u +#define CYDEV_IO_PRT_PRT3_CTL 0x40005139u +#define CYDEV_IO_PRT_PRT3_PRT 0x4000513au +#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513bu +#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513cu +#define CYDEV_IO_PRT_PRT3_AG 0x4000513du +#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513eu +#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513fu +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT4_DR 0x40005140u +#define CYDEV_IO_PRT_PRT4_PS 0x40005141u +#define CYDEV_IO_PRT_PRT4_DM0 0x40005142u +#define CYDEV_IO_PRT_PRT4_DM1 0x40005143u +#define CYDEV_IO_PRT_PRT4_DM2 0x40005144u +#define CYDEV_IO_PRT_PRT4_SLW 0x40005145u +#define CYDEV_IO_PRT_PRT4_BYP 0x40005146u +#define CYDEV_IO_PRT_PRT4_BIE 0x40005147u +#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148u +#define CYDEV_IO_PRT_PRT4_CTL 0x40005149u +#define CYDEV_IO_PRT_PRT4_PRT 0x4000514au +#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514bu +#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514cu +#define CYDEV_IO_PRT_PRT4_AG 0x4000514du +#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514eu +#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514fu +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT5_DR 0x40005150u +#define CYDEV_IO_PRT_PRT5_PS 0x40005151u +#define CYDEV_IO_PRT_PRT5_DM0 0x40005152u +#define CYDEV_IO_PRT_PRT5_DM1 0x40005153u +#define CYDEV_IO_PRT_PRT5_DM2 0x40005154u +#define CYDEV_IO_PRT_PRT5_SLW 0x40005155u +#define CYDEV_IO_PRT_PRT5_BYP 0x40005156u +#define CYDEV_IO_PRT_PRT5_BIE 0x40005157u +#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158u +#define CYDEV_IO_PRT_PRT5_CTL 0x40005159u +#define CYDEV_IO_PRT_PRT5_PRT 0x4000515au +#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515bu +#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515cu +#define CYDEV_IO_PRT_PRT5_AG 0x4000515du +#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515eu +#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515fu +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT6_DR 0x40005160u +#define CYDEV_IO_PRT_PRT6_PS 0x40005161u +#define CYDEV_IO_PRT_PRT6_DM0 0x40005162u +#define CYDEV_IO_PRT_PRT6_DM1 0x40005163u +#define CYDEV_IO_PRT_PRT6_DM2 0x40005164u +#define CYDEV_IO_PRT_PRT6_SLW 0x40005165u +#define CYDEV_IO_PRT_PRT6_BYP 0x40005166u +#define CYDEV_IO_PRT_PRT6_BIE 0x40005167u +#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168u +#define CYDEV_IO_PRT_PRT6_CTL 0x40005169u +#define CYDEV_IO_PRT_PRT6_PRT 0x4000516au +#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516bu +#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516cu +#define CYDEV_IO_PRT_PRT6_AG 0x4000516du +#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516eu +#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516fu +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT12_DR 0x400051c0u +#define CYDEV_IO_PRT_PRT12_PS 0x400051c1u +#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2u +#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3u +#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4u +#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5u +#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6u +#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7u +#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8u +#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9u +#define CYDEV_IO_PRT_PRT12_PRT 0x400051cau +#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cbu +#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051ccu +#define CYDEV_IO_PRT_PRT12_AG 0x400051cdu +#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ceu +#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cfu +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT15_DR 0x400051f0u +#define CYDEV_IO_PRT_PRT15_PS 0x400051f1u +#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2u +#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3u +#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4u +#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5u +#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6u +#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7u +#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8u +#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9u +#define CYDEV_IO_PRT_PRT15_PRT 0x400051fau +#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fbu +#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fcu +#define CYDEV_IO_PRT_PRT15_AG 0x400051fdu +#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051feu +#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ffu +#define CYDEV_PRTDSI_BASE 0x40005200u +#define CYDEV_PRTDSI_SIZE 0x0000007fu +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200u +#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201u +#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202u +#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203u +#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204u +#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205u +#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206u +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208u +#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209u +#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520au +#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520bu +#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520cu +#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520du +#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520eu +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210u +#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211u +#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212u +#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213u +#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214u +#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215u +#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216u +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218u +#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219u +#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521au +#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521bu +#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521cu +#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521du +#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521eu +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220u +#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221u +#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222u +#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223u +#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224u +#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225u +#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226u +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228u +#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229u +#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522au +#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522bu +#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522cu +#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522du +#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522eu +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230u +#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231u +#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232u +#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233u +#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234u +#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235u +#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236u +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u +#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260u +#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261u +#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262u +#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263u +#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264u +#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265u +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278u +#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279u +#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527au +#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527bu +#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527cu +#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527du +#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527eu +#define CYDEV_EMIF_BASE 0x40005400u +#define CYDEV_EMIF_SIZE 0x00000007u +#define CYDEV_EMIF_NO_UDB 0x40005400u +#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401u +#define CYDEV_EMIF_MEM_DWN 0x40005402u +#define CYDEV_EMIF_MEMCLK_DIV 0x40005403u +#define CYDEV_EMIF_CLOCK_EN 0x40005404u +#define CYDEV_EMIF_EM_TYPE 0x40005405u +#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406u +#define CYDEV_ANAIF_BASE 0x40005800u +#define CYDEV_ANAIF_SIZE 0x000003a9u +#define CYDEV_ANAIF_CFG_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801u +#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802u +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805u +#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806u +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809u +#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580au +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580du +#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580eu +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821u +#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822u +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825u +#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826u +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829u +#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582au +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582du +#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582eu +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840u +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841u +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842u +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843u +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849u +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584bu +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584du +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584fu +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859u +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585bu +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585du +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585fu +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869u +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586au +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586bu +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u +#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586du +#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586eu +#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586fu +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871u +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873u +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877u +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879u +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587bu +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587cu +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u +#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881u +#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882u +#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883u +#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884u +#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885u +#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886u +#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887u +#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888u +#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889u +#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588au +#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588bu +#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588cu +#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588du +#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588eu +#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588fu +#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890u +#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891u +#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892u +#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893u +#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894u +#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895u +#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896u +#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897u +#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898u +#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899u +#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589au +#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589bu +#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589cu +#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589du +#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589eu +#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589fu +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u +#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901u +#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902u +#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903u +#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904u +#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905u +#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906u +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u +#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909u +#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590au +#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590bu +#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590cu +#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590du +#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590eu +#define CYDEV_ANAIF_RT_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SIZE 0x00000162u +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02u +#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03u +#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04u +#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06u +#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07u +#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08u +#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0au +#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0bu +#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0cu +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12u +#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13u +#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14u +#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16u +#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17u +#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18u +#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1au +#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1bu +#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1cu +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22u +#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23u +#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24u +#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26u +#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27u +#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28u +#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2au +#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2bu +#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2cu +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32u +#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33u +#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34u +#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36u +#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37u +#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38u +#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3au +#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3bu +#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3cu +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82u +#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83u +#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84u +#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87u +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8au +#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8bu +#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8cu +#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8fu +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92u +#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93u +#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94u +#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97u +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9au +#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9bu +#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9cu +#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9fu +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2u +#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3u +#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4u +#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6u +#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7u +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005acau +#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acbu +#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005accu +#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005aceu +#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acfu +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2u +#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3u +#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4u +#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6u +#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7u +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005adau +#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adbu +#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adcu +#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005adeu +#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adfu +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02u +#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03u +#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04u +#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06u +#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07u +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22u +#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23u +#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24u +#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26u +#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27u +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2au +#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2bu +#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2cu +#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2eu +#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2fu +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41u +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43u +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45u +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47u +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u +#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51u +#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52u +#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53u +#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54u +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u +#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56u +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u +#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5au +#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5bu +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u +#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5du +#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5eu +#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5fu +#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60u +#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61u +#define CYDEV_ANAIF_WRK_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_SIZE 0x00000029u +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83u +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89u +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u +#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91u +#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92u +#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93u +#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94u +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97u +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u +#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99u +#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9au +#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9bu +#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9cu +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1u +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3u +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8u +#define CYDEV_USB_BASE 0x40006000u +#define CYDEV_USB_SIZE 0x00000300u +#define CYDEV_USB_EP0_DR0 0x40006000u +#define CYDEV_USB_EP0_DR1 0x40006001u +#define CYDEV_USB_EP0_DR2 0x40006002u +#define CYDEV_USB_EP0_DR3 0x40006003u +#define CYDEV_USB_EP0_DR4 0x40006004u +#define CYDEV_USB_EP0_DR5 0x40006005u +#define CYDEV_USB_EP0_DR6 0x40006006u +#define CYDEV_USB_EP0_DR7 0x40006007u +#define CYDEV_USB_CR0 0x40006008u +#define CYDEV_USB_CR1 0x40006009u +#define CYDEV_USB_SIE_EP_INT_EN 0x4000600au +#define CYDEV_USB_SIE_EP_INT_SR 0x4000600bu +#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP1_CNT0 0x4000600cu +#define CYDEV_USB_SIE_EP1_CNT1 0x4000600du +#define CYDEV_USB_SIE_EP1_CR0 0x4000600eu +#define CYDEV_USB_USBIO_CR0 0x40006010u +#define CYDEV_USB_USBIO_CR1 0x40006012u +#define CYDEV_USB_DYN_RECONFIG 0x40006014u +#define CYDEV_USB_SOF0 0x40006018u +#define CYDEV_USB_SOF1 0x40006019u +#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP2_CNT0 0x4000601cu +#define CYDEV_USB_SIE_EP2_CNT1 0x4000601du +#define CYDEV_USB_SIE_EP2_CR0 0x4000601eu +#define CYDEV_USB_EP0_CR 0x40006028u +#define CYDEV_USB_EP0_CNT 0x40006029u +#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP3_CNT0 0x4000602cu +#define CYDEV_USB_SIE_EP3_CNT1 0x4000602du +#define CYDEV_USB_SIE_EP3_CR0 0x4000602eu +#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP4_CNT0 0x4000603cu +#define CYDEV_USB_SIE_EP4_CNT1 0x4000603du +#define CYDEV_USB_SIE_EP4_CR0 0x4000603eu +#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP5_CNT0 0x4000604cu +#define CYDEV_USB_SIE_EP5_CNT1 0x4000604du +#define CYDEV_USB_SIE_EP5_CR0 0x4000604eu +#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP6_CNT0 0x4000605cu +#define CYDEV_USB_SIE_EP6_CNT1 0x4000605du +#define CYDEV_USB_SIE_EP6_CR0 0x4000605eu +#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP7_CNT0 0x4000606cu +#define CYDEV_USB_SIE_EP7_CNT1 0x4000606du +#define CYDEV_USB_SIE_EP7_CR0 0x4000606eu +#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP8_CNT0 0x4000607cu +#define CYDEV_USB_SIE_EP8_CNT1 0x4000607du +#define CYDEV_USB_SIE_EP8_CR0 0x4000607eu +#define CYDEV_USB_ARB_EP1_BASE 0x40006080u +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP1_CFG 0x40006080u +#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081u +#define CYDEV_USB_ARB_EP1_SR 0x40006082u +#define CYDEV_USB_ARB_RW1_BASE 0x40006084u +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW1_WA 0x40006084u +#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085u +#define CYDEV_USB_ARB_RW1_RA 0x40006086u +#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087u +#define CYDEV_USB_ARB_RW1_DR 0x40006088u +#define CYDEV_USB_BUF_SIZE 0x4000608cu +#define CYDEV_USB_EP_ACTIVE 0x4000608eu +#define CYDEV_USB_EP_TYPE 0x4000608fu +#define CYDEV_USB_ARB_EP2_BASE 0x40006090u +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP2_CFG 0x40006090u +#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091u +#define CYDEV_USB_ARB_EP2_SR 0x40006092u +#define CYDEV_USB_ARB_RW2_BASE 0x40006094u +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW2_WA 0x40006094u +#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095u +#define CYDEV_USB_ARB_RW2_RA 0x40006096u +#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097u +#define CYDEV_USB_ARB_RW2_DR 0x40006098u +#define CYDEV_USB_ARB_CFG 0x4000609cu +#define CYDEV_USB_USB_CLK_EN 0x4000609du +#define CYDEV_USB_ARB_INT_EN 0x4000609eu +#define CYDEV_USB_ARB_INT_SR 0x4000609fu +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP3_CFG 0x400060a0u +#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1u +#define CYDEV_USB_ARB_EP3_SR 0x400060a2u +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW3_WA 0x400060a4u +#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5u +#define CYDEV_USB_ARB_RW3_RA 0x400060a6u +#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7u +#define CYDEV_USB_ARB_RW3_DR 0x400060a8u +#define CYDEV_USB_CWA 0x400060acu +#define CYDEV_USB_CWA_MSB 0x400060adu +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP4_CFG 0x400060b0u +#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1u +#define CYDEV_USB_ARB_EP4_SR 0x400060b2u +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW4_WA 0x400060b4u +#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5u +#define CYDEV_USB_ARB_RW4_RA 0x400060b6u +#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7u +#define CYDEV_USB_ARB_RW4_DR 0x400060b8u +#define CYDEV_USB_DMA_THRES 0x400060bcu +#define CYDEV_USB_DMA_THRES_MSB 0x400060bdu +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP5_CFG 0x400060c0u +#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1u +#define CYDEV_USB_ARB_EP5_SR 0x400060c2u +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW5_WA 0x400060c4u +#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5u +#define CYDEV_USB_ARB_RW5_RA 0x400060c6u +#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7u +#define CYDEV_USB_ARB_RW5_DR 0x400060c8u +#define CYDEV_USB_BUS_RST_CNT 0x400060ccu +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP6_CFG 0x400060d0u +#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1u +#define CYDEV_USB_ARB_EP6_SR 0x400060d2u +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW6_WA 0x400060d4u +#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5u +#define CYDEV_USB_ARB_RW6_RA 0x400060d6u +#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7u +#define CYDEV_USB_ARB_RW6_DR 0x400060d8u +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP7_CFG 0x400060e0u +#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1u +#define CYDEV_USB_ARB_EP7_SR 0x400060e2u +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW7_WA 0x400060e4u +#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5u +#define CYDEV_USB_ARB_RW7_RA 0x400060e6u +#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7u +#define CYDEV_USB_ARB_RW7_DR 0x400060e8u +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP8_CFG 0x400060f0u +#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1u +#define CYDEV_USB_ARB_EP8_SR 0x400060f2u +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW8_WA 0x400060f4u +#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5u +#define CYDEV_USB_ARB_RW8_RA 0x400060f6u +#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7u +#define CYDEV_USB_ARB_RW8_DR 0x400060f8u +#define CYDEV_USB_MEM_BASE 0x40006100u +#define CYDEV_USB_MEM_SIZE 0x00000200u +#define CYDEV_USB_MEM_DATA_MBASE 0x40006100u +#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200u +#define CYDEV_UWRK_BASE 0x40006400u +#define CYDEV_UWRK_SIZE 0x00000b60u +#define CYDEV_UWRK_UWRK8_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u +#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401u +#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402u +#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403u +#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404u +#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405u +#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406u +#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407u +#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408u +#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409u +#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640au +#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640du +#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410u +#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411u +#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412u +#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413u +#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414u +#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415u +#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416u +#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417u +#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418u +#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419u +#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641au +#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641du +#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420u +#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421u +#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422u +#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423u +#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424u +#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425u +#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426u +#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427u +#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428u +#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429u +#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642au +#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642du +#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430u +#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431u +#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432u +#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433u +#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434u +#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435u +#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436u +#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437u +#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438u +#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439u +#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643au +#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643du +#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440u +#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441u +#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442u +#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443u +#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444u +#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445u +#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446u +#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447u +#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448u +#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449u +#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644au +#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644du +#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450u +#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451u +#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452u +#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453u +#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454u +#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455u +#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456u +#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457u +#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458u +#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459u +#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645au +#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645du +#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460u +#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461u +#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462u +#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463u +#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464u +#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465u +#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466u +#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467u +#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468u +#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469u +#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646au +#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646du +#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470u +#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471u +#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472u +#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473u +#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474u +#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475u +#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476u +#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477u +#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478u +#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479u +#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647au +#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647du +#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480u +#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481u +#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482u +#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483u +#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484u +#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485u +#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486u +#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487u +#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488u +#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489u +#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648au +#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648du +#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490u +#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491u +#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492u +#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493u +#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494u +#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495u +#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496u +#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497u +#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498u +#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499u +#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649au +#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649du +#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0u +#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1u +#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2u +#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3u +#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4u +#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5u +#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6u +#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7u +#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8u +#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9u +#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aau +#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064abu +#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064acu +#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064adu +#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064aeu +#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064afu +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u +#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504u +#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505u +#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506u +#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507u +#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508u +#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509u +#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650au +#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514u +#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515u +#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516u +#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517u +#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518u +#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519u +#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651au +#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524u +#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525u +#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526u +#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527u +#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528u +#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529u +#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652au +#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534u +#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535u +#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536u +#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537u +#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538u +#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539u +#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653au +#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544u +#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545u +#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546u +#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547u +#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548u +#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549u +#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654au +#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554u +#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555u +#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556u +#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557u +#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558u +#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559u +#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655au +#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564u +#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565u +#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566u +#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567u +#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568u +#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569u +#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656au +#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574u +#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575u +#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576u +#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577u +#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578u +#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579u +#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657au +#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584u +#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585u +#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586u +#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587u +#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588u +#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589u +#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658au +#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594u +#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595u +#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596u +#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597u +#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598u +#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599u +#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659au +#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4u +#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5u +#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6u +#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7u +#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8u +#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9u +#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aau +#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065abu +#define CYDEV_UWRK_UWRK16_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068cau +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068ccu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ceu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068dau +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dcu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068deu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695eu +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006acau +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006accu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006aceu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56u +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068acu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068aeu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068bau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068cau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068ccu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ceu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068dau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068eau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ecu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068eeu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695cu +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aacu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aaeu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006acau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006accu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006aceu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aeau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aecu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aeeu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56u +#define CYDEV_PHUB_BASE 0x40007000u +#define CYDEV_PHUB_SIZE 0x00000c00u +#define CYDEV_PHUB_CFG 0x40007000u +#define CYDEV_PHUB_ERR 0x40007004u +#define CYDEV_PHUB_ERR_ADR 0x40007008u +#define CYDEV_PHUB_CH0_BASE 0x40007010u +#define CYDEV_PHUB_CH0_SIZE 0x0000000cu +#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010u +#define CYDEV_PHUB_CH0_ACTION 0x40007014u +#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018u +#define CYDEV_PHUB_CH1_BASE 0x40007020u +#define CYDEV_PHUB_CH1_SIZE 0x0000000cu +#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020u +#define CYDEV_PHUB_CH1_ACTION 0x40007024u +#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028u +#define CYDEV_PHUB_CH2_BASE 0x40007030u +#define CYDEV_PHUB_CH2_SIZE 0x0000000cu +#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030u +#define CYDEV_PHUB_CH2_ACTION 0x40007034u +#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038u +#define CYDEV_PHUB_CH3_BASE 0x40007040u +#define CYDEV_PHUB_CH3_SIZE 0x0000000cu +#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040u +#define CYDEV_PHUB_CH3_ACTION 0x40007044u +#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048u +#define CYDEV_PHUB_CH4_BASE 0x40007050u +#define CYDEV_PHUB_CH4_SIZE 0x0000000cu +#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050u +#define CYDEV_PHUB_CH4_ACTION 0x40007054u +#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058u +#define CYDEV_PHUB_CH5_BASE 0x40007060u +#define CYDEV_PHUB_CH5_SIZE 0x0000000cu +#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060u +#define CYDEV_PHUB_CH5_ACTION 0x40007064u +#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068u +#define CYDEV_PHUB_CH6_BASE 0x40007070u +#define CYDEV_PHUB_CH6_SIZE 0x0000000cu +#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070u +#define CYDEV_PHUB_CH6_ACTION 0x40007074u +#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078u +#define CYDEV_PHUB_CH7_BASE 0x40007080u +#define CYDEV_PHUB_CH7_SIZE 0x0000000cu +#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080u +#define CYDEV_PHUB_CH7_ACTION 0x40007084u +#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088u +#define CYDEV_PHUB_CH8_BASE 0x40007090u +#define CYDEV_PHUB_CH8_SIZE 0x0000000cu +#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090u +#define CYDEV_PHUB_CH8_ACTION 0x40007094u +#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098u +#define CYDEV_PHUB_CH9_BASE 0x400070a0u +#define CYDEV_PHUB_CH9_SIZE 0x0000000cu +#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0u +#define CYDEV_PHUB_CH9_ACTION 0x400070a4u +#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8u +#define CYDEV_PHUB_CH10_BASE 0x400070b0u +#define CYDEV_PHUB_CH10_SIZE 0x0000000cu +#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0u +#define CYDEV_PHUB_CH10_ACTION 0x400070b4u +#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8u +#define CYDEV_PHUB_CH11_BASE 0x400070c0u +#define CYDEV_PHUB_CH11_SIZE 0x0000000cu +#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0u +#define CYDEV_PHUB_CH11_ACTION 0x400070c4u +#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8u +#define CYDEV_PHUB_CH12_BASE 0x400070d0u +#define CYDEV_PHUB_CH12_SIZE 0x0000000cu +#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0u +#define CYDEV_PHUB_CH12_ACTION 0x400070d4u +#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8u +#define CYDEV_PHUB_CH13_BASE 0x400070e0u +#define CYDEV_PHUB_CH13_SIZE 0x0000000cu +#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0u +#define CYDEV_PHUB_CH13_ACTION 0x400070e4u +#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8u +#define CYDEV_PHUB_CH14_BASE 0x400070f0u +#define CYDEV_PHUB_CH14_SIZE 0x0000000cu +#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0u +#define CYDEV_PHUB_CH14_ACTION 0x400070f4u +#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8u +#define CYDEV_PHUB_CH15_BASE 0x40007100u +#define CYDEV_PHUB_CH15_SIZE 0x0000000cu +#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100u +#define CYDEV_PHUB_CH15_ACTION 0x40007104u +#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108u +#define CYDEV_PHUB_CH16_BASE 0x40007110u +#define CYDEV_PHUB_CH16_SIZE 0x0000000cu +#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110u +#define CYDEV_PHUB_CH16_ACTION 0x40007114u +#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118u +#define CYDEV_PHUB_CH17_BASE 0x40007120u +#define CYDEV_PHUB_CH17_SIZE 0x0000000cu +#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120u +#define CYDEV_PHUB_CH17_ACTION 0x40007124u +#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128u +#define CYDEV_PHUB_CH18_BASE 0x40007130u +#define CYDEV_PHUB_CH18_SIZE 0x0000000cu +#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130u +#define CYDEV_PHUB_CH18_ACTION 0x40007134u +#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138u +#define CYDEV_PHUB_CH19_BASE 0x40007140u +#define CYDEV_PHUB_CH19_SIZE 0x0000000cu +#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140u +#define CYDEV_PHUB_CH19_ACTION 0x40007144u +#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148u +#define CYDEV_PHUB_CH20_BASE 0x40007150u +#define CYDEV_PHUB_CH20_SIZE 0x0000000cu +#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150u +#define CYDEV_PHUB_CH20_ACTION 0x40007154u +#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158u +#define CYDEV_PHUB_CH21_BASE 0x40007160u +#define CYDEV_PHUB_CH21_SIZE 0x0000000cu +#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160u +#define CYDEV_PHUB_CH21_ACTION 0x40007164u +#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168u +#define CYDEV_PHUB_CH22_BASE 0x40007170u +#define CYDEV_PHUB_CH22_SIZE 0x0000000cu +#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170u +#define CYDEV_PHUB_CH22_ACTION 0x40007174u +#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178u +#define CYDEV_PHUB_CH23_BASE 0x40007180u +#define CYDEV_PHUB_CH23_SIZE 0x0000000cu +#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180u +#define CYDEV_PHUB_CH23_ACTION 0x40007184u +#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188u +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600u +#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604u +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608u +#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760cu +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610u +#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614u +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618u +#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761cu +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620u +#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624u +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628u +#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762cu +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630u +#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634u +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638u +#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763cu +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640u +#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644u +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648u +#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764cu +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650u +#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654u +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658u +#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765cu +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660u +#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664u +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668u +#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766cu +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670u +#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674u +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678u +#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767cu +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680u +#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684u +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688u +#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768cu +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690u +#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694u +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698u +#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769cu +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4u +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076acu +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4u +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bcu +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800u +#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804u +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808u +#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780cu +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810u +#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814u +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818u +#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781cu +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820u +#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824u +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828u +#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782cu +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830u +#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834u +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838u +#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783cu +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840u +#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844u +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848u +#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784cu +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850u +#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854u +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858u +#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785cu +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860u +#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864u +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868u +#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786cu +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870u +#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874u +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878u +#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787cu +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880u +#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884u +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888u +#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788cu +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890u +#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894u +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898u +#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789cu +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0u +#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4u +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8u +#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078acu +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0u +#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4u +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8u +#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bcu +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0u +#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4u +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8u +#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078ccu +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0u +#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4u +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8u +#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dcu +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0u +#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4u +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8u +#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ecu +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0u +#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4u +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8u +#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fcu +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900u +#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904u +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908u +#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790cu +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910u +#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914u +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918u +#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791cu +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920u +#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924u +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928u +#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792cu +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930u +#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934u +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938u +#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793cu +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940u +#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944u +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948u +#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794cu +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950u +#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954u +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958u +#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795cu +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960u +#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964u +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968u +#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796cu +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970u +#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974u +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978u +#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797cu +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980u +#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984u +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988u +#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798cu +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990u +#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994u +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998u +#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799cu +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0u +#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4u +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8u +#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079acu +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0u +#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4u +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8u +#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bcu +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0u +#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4u +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8u +#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079ccu +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0u +#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4u +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8u +#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dcu +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0u +#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4u +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8u +#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ecu +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0u +#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4u +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8u +#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fcu +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00u +#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04u +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08u +#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10u +#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14u +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18u +#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20u +#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24u +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28u +#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30u +#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34u +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38u +#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40u +#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44u +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48u +#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50u +#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54u +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58u +#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60u +#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64u +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68u +#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70u +#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74u +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78u +#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80u +#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84u +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88u +#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90u +#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94u +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98u +#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aacu +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abcu +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007accu +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adcu +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aecu +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0u +#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4u +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8u +#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afcu +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00u +#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04u +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08u +#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10u +#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14u +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18u +#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20u +#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24u +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28u +#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30u +#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34u +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38u +#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40u +#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44u +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48u +#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50u +#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54u +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58u +#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60u +#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64u +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68u +#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70u +#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74u +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78u +#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80u +#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84u +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88u +#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90u +#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94u +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98u +#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bacu +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bccu +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0u +#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4u +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8u +#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007becu +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu +#define CYDEV_EE_BASE 0x40008000u +#define CYDEV_EE_SIZE 0x00000800u +#define CYDEV_EE_DATA_MBASE 0x40008000u +#define CYDEV_EE_DATA_MSIZE 0x00000800u +#define CYDEV_CAN0_BASE 0x4000a000u +#define CYDEV_CAN0_SIZE 0x000002a0u +#define CYDEV_CAN0_CSR_BASE 0x4000a000u +#define CYDEV_CAN0_CSR_SIZE 0x00000018u +#define CYDEV_CAN0_CSR_INT_SR 0x4000a000u +#define CYDEV_CAN0_CSR_INT_EN 0x4000a004u +#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008u +#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00cu +#define CYDEV_CAN0_CSR_CMD 0x4000a010u +#define CYDEV_CAN0_CSR_CFG 0x4000a014u +#define CYDEV_CAN0_TX0_BASE 0x4000a020u +#define CYDEV_CAN0_TX0_SIZE 0x00000010u +#define CYDEV_CAN0_TX0_CMD 0x4000a020u +#define CYDEV_CAN0_TX0_ID 0x4000a024u +#define CYDEV_CAN0_TX0_DH 0x4000a028u +#define CYDEV_CAN0_TX0_DL 0x4000a02cu +#define CYDEV_CAN0_TX1_BASE 0x4000a030u +#define CYDEV_CAN0_TX1_SIZE 0x00000010u +#define CYDEV_CAN0_TX1_CMD 0x4000a030u +#define CYDEV_CAN0_TX1_ID 0x4000a034u +#define CYDEV_CAN0_TX1_DH 0x4000a038u +#define CYDEV_CAN0_TX1_DL 0x4000a03cu +#define CYDEV_CAN0_TX2_BASE 0x4000a040u +#define CYDEV_CAN0_TX2_SIZE 0x00000010u +#define CYDEV_CAN0_TX2_CMD 0x4000a040u +#define CYDEV_CAN0_TX2_ID 0x4000a044u +#define CYDEV_CAN0_TX2_DH 0x4000a048u +#define CYDEV_CAN0_TX2_DL 0x4000a04cu +#define CYDEV_CAN0_TX3_BASE 0x4000a050u +#define CYDEV_CAN0_TX3_SIZE 0x00000010u +#define CYDEV_CAN0_TX3_CMD 0x4000a050u +#define CYDEV_CAN0_TX3_ID 0x4000a054u +#define CYDEV_CAN0_TX3_DH 0x4000a058u +#define CYDEV_CAN0_TX3_DL 0x4000a05cu +#define CYDEV_CAN0_TX4_BASE 0x4000a060u +#define CYDEV_CAN0_TX4_SIZE 0x00000010u +#define CYDEV_CAN0_TX4_CMD 0x4000a060u +#define CYDEV_CAN0_TX4_ID 0x4000a064u +#define CYDEV_CAN0_TX4_DH 0x4000a068u +#define CYDEV_CAN0_TX4_DL 0x4000a06cu +#define CYDEV_CAN0_TX5_BASE 0x4000a070u +#define CYDEV_CAN0_TX5_SIZE 0x00000010u +#define CYDEV_CAN0_TX5_CMD 0x4000a070u +#define CYDEV_CAN0_TX5_ID 0x4000a074u +#define CYDEV_CAN0_TX5_DH 0x4000a078u +#define CYDEV_CAN0_TX5_DL 0x4000a07cu +#define CYDEV_CAN0_TX6_BASE 0x4000a080u +#define CYDEV_CAN0_TX6_SIZE 0x00000010u +#define CYDEV_CAN0_TX6_CMD 0x4000a080u +#define CYDEV_CAN0_TX6_ID 0x4000a084u +#define CYDEV_CAN0_TX6_DH 0x4000a088u +#define CYDEV_CAN0_TX6_DL 0x4000a08cu +#define CYDEV_CAN0_TX7_BASE 0x4000a090u +#define CYDEV_CAN0_TX7_SIZE 0x00000010u +#define CYDEV_CAN0_TX7_CMD 0x4000a090u +#define CYDEV_CAN0_TX7_ID 0x4000a094u +#define CYDEV_CAN0_TX7_DH 0x4000a098u +#define CYDEV_CAN0_TX7_DL 0x4000a09cu +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u +#define CYDEV_CAN0_RX0_SIZE 0x00000020u +#define CYDEV_CAN0_RX0_CMD 0x4000a0a0u +#define CYDEV_CAN0_RX0_ID 0x4000a0a4u +#define CYDEV_CAN0_RX0_DH 0x4000a0a8u +#define CYDEV_CAN0_RX0_DL 0x4000a0acu +#define CYDEV_CAN0_RX0_AMR 0x4000a0b0u +#define CYDEV_CAN0_RX0_ACR 0x4000a0b4u +#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8u +#define CYDEV_CAN0_RX0_ACRD 0x4000a0bcu +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u +#define CYDEV_CAN0_RX1_SIZE 0x00000020u +#define CYDEV_CAN0_RX1_CMD 0x4000a0c0u +#define CYDEV_CAN0_RX1_ID 0x4000a0c4u +#define CYDEV_CAN0_RX1_DH 0x4000a0c8u +#define CYDEV_CAN0_RX1_DL 0x4000a0ccu +#define CYDEV_CAN0_RX1_AMR 0x4000a0d0u +#define CYDEV_CAN0_RX1_ACR 0x4000a0d4u +#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8u +#define CYDEV_CAN0_RX1_ACRD 0x4000a0dcu +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u +#define CYDEV_CAN0_RX2_SIZE 0x00000020u +#define CYDEV_CAN0_RX2_CMD 0x4000a0e0u +#define CYDEV_CAN0_RX2_ID 0x4000a0e4u +#define CYDEV_CAN0_RX2_DH 0x4000a0e8u +#define CYDEV_CAN0_RX2_DL 0x4000a0ecu +#define CYDEV_CAN0_RX2_AMR 0x4000a0f0u +#define CYDEV_CAN0_RX2_ACR 0x4000a0f4u +#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8u +#define CYDEV_CAN0_RX2_ACRD 0x4000a0fcu +#define CYDEV_CAN0_RX3_BASE 0x4000a100u +#define CYDEV_CAN0_RX3_SIZE 0x00000020u +#define CYDEV_CAN0_RX3_CMD 0x4000a100u +#define CYDEV_CAN0_RX3_ID 0x4000a104u +#define CYDEV_CAN0_RX3_DH 0x4000a108u +#define CYDEV_CAN0_RX3_DL 0x4000a10cu +#define CYDEV_CAN0_RX3_AMR 0x4000a110u +#define CYDEV_CAN0_RX3_ACR 0x4000a114u +#define CYDEV_CAN0_RX3_AMRD 0x4000a118u +#define CYDEV_CAN0_RX3_ACRD 0x4000a11cu +#define CYDEV_CAN0_RX4_BASE 0x4000a120u +#define CYDEV_CAN0_RX4_SIZE 0x00000020u +#define CYDEV_CAN0_RX4_CMD 0x4000a120u +#define CYDEV_CAN0_RX4_ID 0x4000a124u +#define CYDEV_CAN0_RX4_DH 0x4000a128u +#define CYDEV_CAN0_RX4_DL 0x4000a12cu +#define CYDEV_CAN0_RX4_AMR 0x4000a130u +#define CYDEV_CAN0_RX4_ACR 0x4000a134u +#define CYDEV_CAN0_RX4_AMRD 0x4000a138u +#define CYDEV_CAN0_RX4_ACRD 0x4000a13cu +#define CYDEV_CAN0_RX5_BASE 0x4000a140u +#define CYDEV_CAN0_RX5_SIZE 0x00000020u +#define CYDEV_CAN0_RX5_CMD 0x4000a140u +#define CYDEV_CAN0_RX5_ID 0x4000a144u +#define CYDEV_CAN0_RX5_DH 0x4000a148u +#define CYDEV_CAN0_RX5_DL 0x4000a14cu +#define CYDEV_CAN0_RX5_AMR 0x4000a150u +#define CYDEV_CAN0_RX5_ACR 0x4000a154u +#define CYDEV_CAN0_RX5_AMRD 0x4000a158u +#define CYDEV_CAN0_RX5_ACRD 0x4000a15cu +#define CYDEV_CAN0_RX6_BASE 0x4000a160u +#define CYDEV_CAN0_RX6_SIZE 0x00000020u +#define CYDEV_CAN0_RX6_CMD 0x4000a160u +#define CYDEV_CAN0_RX6_ID 0x4000a164u +#define CYDEV_CAN0_RX6_DH 0x4000a168u +#define CYDEV_CAN0_RX6_DL 0x4000a16cu +#define CYDEV_CAN0_RX6_AMR 0x4000a170u +#define CYDEV_CAN0_RX6_ACR 0x4000a174u +#define CYDEV_CAN0_RX6_AMRD 0x4000a178u +#define CYDEV_CAN0_RX6_ACRD 0x4000a17cu +#define CYDEV_CAN0_RX7_BASE 0x4000a180u +#define CYDEV_CAN0_RX7_SIZE 0x00000020u +#define CYDEV_CAN0_RX7_CMD 0x4000a180u +#define CYDEV_CAN0_RX7_ID 0x4000a184u +#define CYDEV_CAN0_RX7_DH 0x4000a188u +#define CYDEV_CAN0_RX7_DL 0x4000a18cu +#define CYDEV_CAN0_RX7_AMR 0x4000a190u +#define CYDEV_CAN0_RX7_ACR 0x4000a194u +#define CYDEV_CAN0_RX7_AMRD 0x4000a198u +#define CYDEV_CAN0_RX7_ACRD 0x4000a19cu +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u +#define CYDEV_CAN0_RX8_SIZE 0x00000020u +#define CYDEV_CAN0_RX8_CMD 0x4000a1a0u +#define CYDEV_CAN0_RX8_ID 0x4000a1a4u +#define CYDEV_CAN0_RX8_DH 0x4000a1a8u +#define CYDEV_CAN0_RX8_DL 0x4000a1acu +#define CYDEV_CAN0_RX8_AMR 0x4000a1b0u +#define CYDEV_CAN0_RX8_ACR 0x4000a1b4u +#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8u +#define CYDEV_CAN0_RX8_ACRD 0x4000a1bcu +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u +#define CYDEV_CAN0_RX9_SIZE 0x00000020u +#define CYDEV_CAN0_RX9_CMD 0x4000a1c0u +#define CYDEV_CAN0_RX9_ID 0x4000a1c4u +#define CYDEV_CAN0_RX9_DH 0x4000a1c8u +#define CYDEV_CAN0_RX9_DL 0x4000a1ccu +#define CYDEV_CAN0_RX9_AMR 0x4000a1d0u +#define CYDEV_CAN0_RX9_ACR 0x4000a1d4u +#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8u +#define CYDEV_CAN0_RX9_ACRD 0x4000a1dcu +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u +#define CYDEV_CAN0_RX10_SIZE 0x00000020u +#define CYDEV_CAN0_RX10_CMD 0x4000a1e0u +#define CYDEV_CAN0_RX10_ID 0x4000a1e4u +#define CYDEV_CAN0_RX10_DH 0x4000a1e8u +#define CYDEV_CAN0_RX10_DL 0x4000a1ecu +#define CYDEV_CAN0_RX10_AMR 0x4000a1f0u +#define CYDEV_CAN0_RX10_ACR 0x4000a1f4u +#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8u +#define CYDEV_CAN0_RX10_ACRD 0x4000a1fcu +#define CYDEV_CAN0_RX11_BASE 0x4000a200u +#define CYDEV_CAN0_RX11_SIZE 0x00000020u +#define CYDEV_CAN0_RX11_CMD 0x4000a200u +#define CYDEV_CAN0_RX11_ID 0x4000a204u +#define CYDEV_CAN0_RX11_DH 0x4000a208u +#define CYDEV_CAN0_RX11_DL 0x4000a20cu +#define CYDEV_CAN0_RX11_AMR 0x4000a210u +#define CYDEV_CAN0_RX11_ACR 0x4000a214u +#define CYDEV_CAN0_RX11_AMRD 0x4000a218u +#define CYDEV_CAN0_RX11_ACRD 0x4000a21cu +#define CYDEV_CAN0_RX12_BASE 0x4000a220u +#define CYDEV_CAN0_RX12_SIZE 0x00000020u +#define CYDEV_CAN0_RX12_CMD 0x4000a220u +#define CYDEV_CAN0_RX12_ID 0x4000a224u +#define CYDEV_CAN0_RX12_DH 0x4000a228u +#define CYDEV_CAN0_RX12_DL 0x4000a22cu +#define CYDEV_CAN0_RX12_AMR 0x4000a230u +#define CYDEV_CAN0_RX12_ACR 0x4000a234u +#define CYDEV_CAN0_RX12_AMRD 0x4000a238u +#define CYDEV_CAN0_RX12_ACRD 0x4000a23cu +#define CYDEV_CAN0_RX13_BASE 0x4000a240u +#define CYDEV_CAN0_RX13_SIZE 0x00000020u +#define CYDEV_CAN0_RX13_CMD 0x4000a240u +#define CYDEV_CAN0_RX13_ID 0x4000a244u +#define CYDEV_CAN0_RX13_DH 0x4000a248u +#define CYDEV_CAN0_RX13_DL 0x4000a24cu +#define CYDEV_CAN0_RX13_AMR 0x4000a250u +#define CYDEV_CAN0_RX13_ACR 0x4000a254u +#define CYDEV_CAN0_RX13_AMRD 0x4000a258u +#define CYDEV_CAN0_RX13_ACRD 0x4000a25cu +#define CYDEV_CAN0_RX14_BASE 0x4000a260u +#define CYDEV_CAN0_RX14_SIZE 0x00000020u +#define CYDEV_CAN0_RX14_CMD 0x4000a260u +#define CYDEV_CAN0_RX14_ID 0x4000a264u +#define CYDEV_CAN0_RX14_DH 0x4000a268u +#define CYDEV_CAN0_RX14_DL 0x4000a26cu +#define CYDEV_CAN0_RX14_AMR 0x4000a270u +#define CYDEV_CAN0_RX14_ACR 0x4000a274u +#define CYDEV_CAN0_RX14_AMRD 0x4000a278u +#define CYDEV_CAN0_RX14_ACRD 0x4000a27cu +#define CYDEV_CAN0_RX15_BASE 0x4000a280u +#define CYDEV_CAN0_RX15_SIZE 0x00000020u +#define CYDEV_CAN0_RX15_CMD 0x4000a280u +#define CYDEV_CAN0_RX15_ID 0x4000a284u +#define CYDEV_CAN0_RX15_DH 0x4000a288u +#define CYDEV_CAN0_RX15_DL 0x4000a28cu +#define CYDEV_CAN0_RX15_AMR 0x4000a290u +#define CYDEV_CAN0_RX15_ACR 0x4000a294u +#define CYDEV_CAN0_RX15_AMRD 0x4000a298u +#define CYDEV_CAN0_RX15_ACRD 0x4000a29cu +#define CYDEV_DFB0_BASE 0x4000c000u +#define CYDEV_DFB0_SIZE 0x000007b5u +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u +#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u +#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u +#define CYDEV_DFB0_CR 0x4000c780u +#define CYDEV_DFB0_SR 0x4000c784u +#define CYDEV_DFB0_RAM_EN 0x4000c788u +#define CYDEV_DFB0_RAM_DIR 0x4000c78cu +#define CYDEV_DFB0_SEMA 0x4000c790u +#define CYDEV_DFB0_DSI_CTRL 0x4000c794u +#define CYDEV_DFB0_INT_CTRL 0x4000c798u +#define CYDEV_DFB0_DMA_CTRL 0x4000c79cu +#define CYDEV_DFB0_STAGEA 0x4000c7a0u +#define CYDEV_DFB0_STAGEAM 0x4000c7a1u +#define CYDEV_DFB0_STAGEAH 0x4000c7a2u +#define CYDEV_DFB0_STAGEB 0x4000c7a4u +#define CYDEV_DFB0_STAGEBM 0x4000c7a5u +#define CYDEV_DFB0_STAGEBH 0x4000c7a6u +#define CYDEV_DFB0_HOLDA 0x4000c7a8u +#define CYDEV_DFB0_HOLDAM 0x4000c7a9u +#define CYDEV_DFB0_HOLDAH 0x4000c7aau +#define CYDEV_DFB0_HOLDAS 0x4000c7abu +#define CYDEV_DFB0_HOLDB 0x4000c7acu +#define CYDEV_DFB0_HOLDBM 0x4000c7adu +#define CYDEV_DFB0_HOLDBH 0x4000c7aeu +#define CYDEV_DFB0_HOLDBS 0x4000c7afu +#define CYDEV_DFB0_COHER 0x4000c7b0u +#define CYDEV_DFB0_DALIGN 0x4000c7b4u +#define CYDEV_UCFG_BASE 0x40010000u +#define CYDEV_UCFG_SIZE 0x00005040u +#define CYDEV_UCFG_B0_BASE 0x40010000u +#define CYDEV_UCFG_B0_SIZE 0x00000fefu +#define CYDEV_UCFG_B0_P0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000cu +#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001cu +#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002cu +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036u +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003au +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu +#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040u +#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041u +#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042u +#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043u +#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044u +#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045u +#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046u +#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047u +#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048u +#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049u +#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004au +#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004bu +#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004cu +#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004du +#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004eu +#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004fu +#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050u +#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051u +#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052u +#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053u +#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054u +#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055u +#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056u +#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057u +#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058u +#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059u +#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005au +#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005bu +#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005cu +#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005du +#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005eu +#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005fu +#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060u +#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062u +#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064u +#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066u +#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068u +#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006au +#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006cu +#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006eu +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008cu +#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009cu +#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100acu +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6u +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100bau +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu +#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0u +#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1u +#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2u +#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3u +#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4u +#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5u +#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6u +#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7u +#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8u +#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9u +#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100cau +#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cbu +#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100ccu +#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cdu +#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ceu +#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cfu +#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0u +#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1u +#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2u +#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3u +#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4u +#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5u +#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6u +#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7u +#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8u +#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9u +#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100dau +#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100dbu +#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dcu +#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100ddu +#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100deu +#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100dfu +#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0u +#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2u +#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4u +#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6u +#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8u +#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100eau +#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ecu +#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100eeu +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P1_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020cu +#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021cu +#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022cu +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236u +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023au +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu +#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240u +#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241u +#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242u +#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243u +#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244u +#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245u +#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246u +#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247u +#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248u +#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249u +#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024au +#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024bu +#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024cu +#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024du +#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024eu +#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024fu +#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250u +#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251u +#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252u +#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253u +#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254u +#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255u +#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256u +#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257u +#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258u +#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259u +#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025au +#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025bu +#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025cu +#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025du +#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025eu +#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025fu +#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260u +#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262u +#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264u +#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266u +#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268u +#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026au +#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026cu +#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026eu +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028cu +#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029cu +#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102acu +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6u +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102bau +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu +#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0u +#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1u +#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2u +#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3u +#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4u +#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5u +#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6u +#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7u +#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8u +#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9u +#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102cau +#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cbu +#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102ccu +#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cdu +#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ceu +#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cfu +#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0u +#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1u +#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2u +#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3u +#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4u +#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5u +#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6u +#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7u +#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8u +#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9u +#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102dau +#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102dbu +#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dcu +#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102ddu +#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102deu +#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102dfu +#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0u +#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2u +#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4u +#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6u +#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8u +#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102eau +#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ecu +#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102eeu +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P2_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040cu +#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041cu +#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042cu +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436u +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043au +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu +#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440u +#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441u +#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442u +#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443u +#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444u +#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445u +#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446u +#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447u +#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448u +#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449u +#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044au +#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044bu +#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044cu +#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044du +#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044eu +#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044fu +#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450u +#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451u +#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452u +#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453u +#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454u +#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455u +#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456u +#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457u +#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458u +#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459u +#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045au +#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045bu +#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045cu +#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045du +#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045eu +#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045fu +#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460u +#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462u +#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464u +#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466u +#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468u +#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046au +#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046cu +#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046eu +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048cu +#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049cu +#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104acu +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6u +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104bau +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu +#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0u +#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1u +#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2u +#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3u +#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4u +#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5u +#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6u +#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7u +#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8u +#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9u +#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104cau +#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cbu +#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104ccu +#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cdu +#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ceu +#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cfu +#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0u +#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1u +#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2u +#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3u +#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4u +#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5u +#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6u +#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7u +#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8u +#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9u +#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104dau +#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104dbu +#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dcu +#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104ddu +#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104deu +#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104dfu +#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0u +#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2u +#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4u +#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6u +#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8u +#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104eau +#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ecu +#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104eeu +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P3_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060cu +#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061cu +#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062cu +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636u +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063au +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu +#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640u +#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641u +#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642u +#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643u +#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644u +#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645u +#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646u +#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647u +#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648u +#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649u +#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064au +#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064bu +#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064cu +#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064du +#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064eu +#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064fu +#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650u +#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651u +#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652u +#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653u +#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654u +#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655u +#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656u +#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657u +#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658u +#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659u +#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065au +#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065bu +#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065cu +#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065du +#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065eu +#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065fu +#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660u +#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662u +#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664u +#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666u +#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668u +#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066au +#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066cu +#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066eu +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068cu +#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069cu +#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106acu +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6u +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106bau +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu +#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0u +#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1u +#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2u +#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3u +#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4u +#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5u +#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6u +#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7u +#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8u +#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9u +#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106cau +#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cbu +#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106ccu +#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cdu +#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ceu +#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cfu +#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0u +#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1u +#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2u +#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3u +#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4u +#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5u +#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6u +#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7u +#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8u +#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9u +#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106dau +#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106dbu +#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dcu +#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106ddu +#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106deu +#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106dfu +#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0u +#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2u +#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4u +#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6u +#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8u +#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106eau +#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ecu +#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106eeu +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P4_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080cu +#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081cu +#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082cu +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836u +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083au +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu +#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840u +#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841u +#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842u +#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843u +#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844u +#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845u +#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846u +#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847u +#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848u +#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849u +#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084au +#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084bu +#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084cu +#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084du +#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084eu +#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084fu +#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850u +#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851u +#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852u +#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853u +#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854u +#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855u +#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856u +#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857u +#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858u +#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859u +#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085au +#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085bu +#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085cu +#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085du +#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085eu +#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085fu +#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860u +#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862u +#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864u +#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866u +#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868u +#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086au +#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086cu +#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086eu +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088cu +#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089cu +#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108acu +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6u +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108bau +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu +#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0u +#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1u +#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2u +#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3u +#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4u +#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5u +#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6u +#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7u +#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8u +#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9u +#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108cau +#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cbu +#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108ccu +#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cdu +#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ceu +#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cfu +#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0u +#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1u +#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2u +#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3u +#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4u +#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5u +#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6u +#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7u +#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8u +#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9u +#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108dau +#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108dbu +#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dcu +#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108ddu +#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108deu +#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108dfu +#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0u +#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2u +#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4u +#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6u +#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8u +#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108eau +#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ecu +#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108eeu +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0cu +#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1cu +#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2cu +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36u +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu +#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40u +#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41u +#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42u +#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43u +#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44u +#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45u +#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46u +#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47u +#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48u +#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49u +#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4au +#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4bu +#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4cu +#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4du +#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4eu +#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4fu +#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50u +#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51u +#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52u +#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53u +#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54u +#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55u +#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56u +#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57u +#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58u +#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59u +#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5au +#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5bu +#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5cu +#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5du +#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5eu +#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5fu +#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60u +#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62u +#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64u +#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66u +#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68u +#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6au +#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6cu +#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6eu +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8cu +#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9cu +#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aacu +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6u +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010abau +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu +#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0u +#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1u +#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2u +#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3u +#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4u +#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5u +#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6u +#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7u +#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8u +#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9u +#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010acau +#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acbu +#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010accu +#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acdu +#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010aceu +#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acfu +#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0u +#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1u +#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2u +#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3u +#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4u +#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5u +#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6u +#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7u +#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8u +#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9u +#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010adau +#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adbu +#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adcu +#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010addu +#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010adeu +#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adfu +#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0u +#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2u +#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4u +#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6u +#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8u +#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aeau +#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aecu +#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aeeu +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0cu +#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1cu +#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2cu +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36u +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu +#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40u +#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41u +#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42u +#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43u +#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44u +#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45u +#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46u +#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47u +#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48u +#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49u +#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4au +#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4bu +#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4cu +#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4du +#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4eu +#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4fu +#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50u +#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51u +#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52u +#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53u +#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54u +#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55u +#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56u +#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57u +#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58u +#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59u +#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5au +#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5bu +#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5cu +#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5du +#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5eu +#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5fu +#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60u +#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62u +#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64u +#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66u +#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68u +#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6au +#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6cu +#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6eu +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8cu +#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9cu +#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cacu +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6u +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu +#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0u +#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1u +#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2u +#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3u +#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4u +#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5u +#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6u +#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7u +#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8u +#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9u +#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010ccau +#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccbu +#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010cccu +#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccdu +#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cceu +#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccfu +#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0u +#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1u +#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2u +#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3u +#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4u +#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5u +#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6u +#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7u +#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8u +#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9u +#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cdau +#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdbu +#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdcu +#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cddu +#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cdeu +#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdfu +#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0u +#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2u +#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4u +#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6u +#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8u +#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010ceau +#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cecu +#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010ceeu +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0cu +#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1cu +#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2cu +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36u +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu +#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40u +#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41u +#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42u +#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43u +#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44u +#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45u +#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46u +#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47u +#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48u +#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49u +#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4au +#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4bu +#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4cu +#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4du +#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4eu +#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4fu +#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50u +#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51u +#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52u +#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53u +#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54u +#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55u +#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56u +#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57u +#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58u +#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59u +#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5au +#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5bu +#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5cu +#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5du +#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5eu +#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5fu +#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60u +#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62u +#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64u +#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66u +#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68u +#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6au +#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6cu +#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6eu +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8cu +#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9cu +#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eacu +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6u +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu +#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0u +#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1u +#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2u +#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3u +#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4u +#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5u +#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6u +#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7u +#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8u +#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9u +#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010ecau +#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecbu +#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010eccu +#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecdu +#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010eceu +#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecfu +#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0u +#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1u +#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2u +#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3u +#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4u +#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5u +#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6u +#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7u +#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8u +#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9u +#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010edau +#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edbu +#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edcu +#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010eddu +#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010edeu +#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edfu +#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0u +#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2u +#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4u +#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6u +#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8u +#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eeau +#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eecu +#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eeeu +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_BASE 0x40011000u +#define CYDEV_UCFG_B1_SIZE 0x00000fefu +#define CYDEV_UCFG_B1_P2_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140cu +#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141cu +#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142cu +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436u +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143au +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu +#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440u +#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441u +#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442u +#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443u +#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444u +#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445u +#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446u +#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447u +#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448u +#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449u +#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144au +#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144bu +#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144cu +#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144du +#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144eu +#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144fu +#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450u +#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451u +#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452u +#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453u +#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454u +#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455u +#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456u +#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457u +#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458u +#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459u +#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145au +#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145bu +#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145cu +#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145du +#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145eu +#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145fu +#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460u +#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462u +#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464u +#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466u +#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468u +#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146au +#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146cu +#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146eu +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148cu +#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149cu +#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114acu +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6u +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114bau +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu +#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0u +#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1u +#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2u +#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3u +#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4u +#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5u +#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6u +#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7u +#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8u +#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9u +#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114cau +#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cbu +#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114ccu +#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cdu +#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ceu +#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cfu +#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0u +#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1u +#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2u +#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3u +#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4u +#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5u +#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6u +#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7u +#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8u +#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9u +#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114dau +#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114dbu +#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dcu +#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114ddu +#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114deu +#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114dfu +#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0u +#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2u +#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4u +#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6u +#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8u +#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114eau +#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ecu +#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114eeu +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P3_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160cu +#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161cu +#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162cu +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636u +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163au +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu +#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640u +#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641u +#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642u +#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643u +#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644u +#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645u +#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646u +#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647u +#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648u +#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649u +#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164au +#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164bu +#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164cu +#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164du +#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164eu +#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164fu +#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650u +#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651u +#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652u +#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653u +#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654u +#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655u +#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656u +#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657u +#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658u +#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659u +#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165au +#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165bu +#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165cu +#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165du +#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165eu +#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165fu +#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660u +#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662u +#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664u +#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666u +#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668u +#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166au +#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166cu +#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166eu +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168cu +#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169cu +#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116acu +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6u +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116bau +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu +#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0u +#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1u +#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2u +#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3u +#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4u +#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5u +#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6u +#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7u +#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8u +#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9u +#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116cau +#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cbu +#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116ccu +#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cdu +#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ceu +#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cfu +#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0u +#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1u +#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2u +#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3u +#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4u +#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5u +#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6u +#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7u +#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8u +#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9u +#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116dau +#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116dbu +#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dcu +#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116ddu +#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116deu +#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116dfu +#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0u +#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2u +#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4u +#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6u +#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8u +#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116eau +#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ecu +#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116eeu +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P4_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180cu +#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181cu +#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182cu +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836u +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183au +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu +#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840u +#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841u +#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842u +#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843u +#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844u +#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845u +#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846u +#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847u +#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848u +#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849u +#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184au +#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184bu +#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184cu +#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184du +#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184eu +#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184fu +#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850u +#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851u +#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852u +#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853u +#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854u +#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855u +#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856u +#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857u +#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858u +#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859u +#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185au +#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185bu +#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185cu +#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185du +#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185eu +#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185fu +#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860u +#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862u +#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864u +#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866u +#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868u +#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186au +#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186cu +#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186eu +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188cu +#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189cu +#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118acu +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6u +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118bau +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu +#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0u +#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1u +#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2u +#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3u +#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4u +#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5u +#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6u +#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7u +#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8u +#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9u +#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118cau +#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cbu +#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118ccu +#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cdu +#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ceu +#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cfu +#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0u +#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1u +#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2u +#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3u +#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4u +#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5u +#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6u +#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7u +#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8u +#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9u +#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118dau +#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118dbu +#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dcu +#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118ddu +#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118deu +#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118dfu +#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0u +#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2u +#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4u +#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6u +#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8u +#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118eau +#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ecu +#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118eeu +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0cu +#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1cu +#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2cu +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36u +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu +#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40u +#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41u +#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42u +#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43u +#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44u +#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45u +#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46u +#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47u +#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48u +#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49u +#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4au +#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4bu +#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4cu +#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4du +#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4eu +#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4fu +#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50u +#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51u +#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52u +#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53u +#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54u +#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55u +#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56u +#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57u +#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58u +#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59u +#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5au +#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5bu +#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5cu +#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5du +#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5eu +#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5fu +#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60u +#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62u +#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64u +#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66u +#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68u +#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6au +#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6cu +#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6eu +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8cu +#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9cu +#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aacu +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6u +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011abau +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu +#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0u +#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1u +#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2u +#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3u +#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4u +#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5u +#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6u +#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7u +#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8u +#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9u +#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011acau +#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acbu +#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011accu +#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acdu +#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011aceu +#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acfu +#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0u +#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1u +#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2u +#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3u +#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4u +#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5u +#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6u +#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7u +#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8u +#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9u +#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011adau +#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adbu +#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adcu +#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011addu +#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011adeu +#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adfu +#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0u +#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2u +#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4u +#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6u +#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8u +#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aeau +#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aecu +#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aeeu +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_DSI0_BASE 0x40014000u +#define CYDEV_UCFG_DSI0_SIZE 0x000000efu +#define CYDEV_UCFG_DSI1_BASE 0x40014100u +#define CYDEV_UCFG_DSI1_SIZE 0x000000efu +#define CYDEV_UCFG_DSI2_BASE 0x40014200u +#define CYDEV_UCFG_DSI2_SIZE 0x000000efu +#define CYDEV_UCFG_DSI3_BASE 0x40014300u +#define CYDEV_UCFG_DSI3_SIZE 0x000000efu +#define CYDEV_UCFG_DSI4_BASE 0x40014400u +#define CYDEV_UCFG_DSI4_SIZE 0x000000efu +#define CYDEV_UCFG_DSI5_BASE 0x40014500u +#define CYDEV_UCFG_DSI5_SIZE 0x000000efu +#define CYDEV_UCFG_DSI6_BASE 0x40014600u +#define CYDEV_UCFG_DSI6_SIZE 0x000000efu +#define CYDEV_UCFG_DSI7_BASE 0x40014700u +#define CYDEV_UCFG_DSI7_SIZE 0x000000efu +#define CYDEV_UCFG_DSI8_BASE 0x40014800u +#define CYDEV_UCFG_DSI8_SIZE 0x000000efu +#define CYDEV_UCFG_DSI9_BASE 0x40014900u +#define CYDEV_UCFG_DSI9_SIZE 0x000000efu +#define CYDEV_UCFG_DSI12_BASE 0x40014c00u +#define CYDEV_UCFG_DSI12_SIZE 0x000000efu +#define CYDEV_UCFG_DSI13_BASE 0x40014d00u +#define CYDEV_UCFG_DSI13_SIZE 0x000000efu +#define CYDEV_UCFG_BCTL0_BASE 0x40015000u +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u +#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000u +#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001u +#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002u +#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003u +#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007u +#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008u +#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009u +#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500au +#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500bu +#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500cu +#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500du +#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500eu +#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500fu +#define CYDEV_UCFG_BCTL1_BASE 0x40015010u +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u +#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010u +#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011u +#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012u +#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013u +#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017u +#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018u +#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019u +#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501au +#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501bu +#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501cu +#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501du +#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501eu +#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501fu +#define CYDEV_IDMUX_BASE 0x40015100u +#define CYDEV_IDMUX_SIZE 0x00000016u +#define CYDEV_IDMUX_IRQ_CTL0 0x40015100u +#define CYDEV_IDMUX_IRQ_CTL1 0x40015101u +#define CYDEV_IDMUX_IRQ_CTL2 0x40015102u +#define CYDEV_IDMUX_IRQ_CTL3 0x40015103u +#define CYDEV_IDMUX_IRQ_CTL4 0x40015104u +#define CYDEV_IDMUX_IRQ_CTL5 0x40015105u +#define CYDEV_IDMUX_IRQ_CTL6 0x40015106u +#define CYDEV_IDMUX_IRQ_CTL7 0x40015107u +#define CYDEV_IDMUX_DRQ_CTL0 0x40015110u +#define CYDEV_IDMUX_DRQ_CTL1 0x40015111u +#define CYDEV_IDMUX_DRQ_CTL2 0x40015112u +#define CYDEV_IDMUX_DRQ_CTL3 0x40015113u +#define CYDEV_IDMUX_DRQ_CTL4 0x40015114u +#define CYDEV_IDMUX_DRQ_CTL5 0x40015115u +#define CYDEV_CACHERAM_BASE 0x40030000u +#define CYDEV_CACHERAM_SIZE 0x00000400u +#define CYDEV_CACHERAM_DATA_MBASE 0x40030000u +#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400u +#define CYDEV_SFR_BASE 0x40050100u +#define CYDEV_SFR_SIZE 0x000000fbu +#define CYDEV_SFR_GPIO0 0x40050180u +#define CYDEV_SFR_GPIRD0 0x40050189u +#define CYDEV_SFR_GPIO0_SEL 0x4005018au +#define CYDEV_SFR_GPIO1 0x40050190u +#define CYDEV_SFR_GPIRD1 0x40050191u +#define CYDEV_SFR_GPIO2 0x40050198u +#define CYDEV_SFR_GPIRD2 0x40050199u +#define CYDEV_SFR_GPIO2_SEL 0x4005019au +#define CYDEV_SFR_GPIO1_SEL 0x400501a2u +#define CYDEV_SFR_GPIO3 0x400501b0u +#define CYDEV_SFR_GPIRD3 0x400501b1u +#define CYDEV_SFR_GPIO3_SEL 0x400501b2u +#define CYDEV_SFR_GPIO4 0x400501c0u +#define CYDEV_SFR_GPIRD4 0x400501c1u +#define CYDEV_SFR_GPIO4_SEL 0x400501c2u +#define CYDEV_SFR_GPIO5 0x400501c8u +#define CYDEV_SFR_GPIRD5 0x400501c9u +#define CYDEV_SFR_GPIO5_SEL 0x400501cau +#define CYDEV_SFR_GPIO6 0x400501d8u +#define CYDEV_SFR_GPIRD6 0x400501d9u +#define CYDEV_SFR_GPIO6_SEL 0x400501dau +#define CYDEV_SFR_GPIO12 0x400501e8u +#define CYDEV_SFR_GPIRD12 0x400501e9u +#define CYDEV_SFR_GPIO12_SEL 0x400501f2u +#define CYDEV_SFR_GPIO15 0x400501f8u +#define CYDEV_SFR_GPIRD15 0x400501f9u +#define CYDEV_SFR_GPIO15_SEL 0x400501fau +#define CYDEV_P3BA_BASE 0x40050300u +#define CYDEV_P3BA_SIZE 0x0000002bu +#define CYDEV_P3BA_Y_START 0x40050300u +#define CYDEV_P3BA_YROLL 0x40050301u +#define CYDEV_P3BA_YCFG 0x40050302u +#define CYDEV_P3BA_X_START1 0x40050303u +#define CYDEV_P3BA_X_START2 0x40050304u +#define CYDEV_P3BA_XROLL1 0x40050305u +#define CYDEV_P3BA_XROLL2 0x40050306u +#define CYDEV_P3BA_XINC 0x40050307u +#define CYDEV_P3BA_XCFG 0x40050308u +#define CYDEV_P3BA_OFFSETADDR1 0x40050309u +#define CYDEV_P3BA_OFFSETADDR2 0x4005030au +#define CYDEV_P3BA_OFFSETADDR3 0x4005030bu +#define CYDEV_P3BA_ABSADDR1 0x4005030cu +#define CYDEV_P3BA_ABSADDR2 0x4005030du +#define CYDEV_P3BA_ABSADDR3 0x4005030eu +#define CYDEV_P3BA_ABSADDR4 0x4005030fu +#define CYDEV_P3BA_DATCFG1 0x40050310u +#define CYDEV_P3BA_DATCFG2 0x40050311u +#define CYDEV_P3BA_CMP_RSLT1 0x40050314u +#define CYDEV_P3BA_CMP_RSLT2 0x40050315u +#define CYDEV_P3BA_CMP_RSLT3 0x40050316u +#define CYDEV_P3BA_CMP_RSLT4 0x40050317u +#define CYDEV_P3BA_DATA_REG1 0x40050318u +#define CYDEV_P3BA_DATA_REG2 0x40050319u +#define CYDEV_P3BA_DATA_REG3 0x4005031au +#define CYDEV_P3BA_DATA_REG4 0x4005031bu +#define CYDEV_P3BA_EXP_DATA1 0x4005031cu +#define CYDEV_P3BA_EXP_DATA2 0x4005031du +#define CYDEV_P3BA_EXP_DATA3 0x4005031eu +#define CYDEV_P3BA_EXP_DATA4 0x4005031fu +#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320u +#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321u +#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322u +#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323u +#define CYDEV_P3BA_BIST_EN 0x40050324u +#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325u +#define CYDEV_P3BA_SEQCFG1 0x40050326u +#define CYDEV_P3BA_SEQCFG2 0x40050327u +#define CYDEV_P3BA_Y_CURR 0x40050328u +#define CYDEV_P3BA_X_CURR1 0x40050329u +#define CYDEV_P3BA_X_CURR2 0x4005032au +#define CYDEV_PANTHER_BASE 0x40080000u +#define CYDEV_PANTHER_SIZE 0x00000020u +#define CYDEV_PANTHER_STCALIB_CFG 0x40080000u +#define CYDEV_PANTHER_WAITPIPE 0x40080004u +#define CYDEV_PANTHER_TRACE_CFG 0x40080008u +#define CYDEV_PANTHER_DBG_CFG 0x4008000cu +#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018u +#define CYDEV_PANTHER_DEVICE_ID 0x4008001cu +#define CYDEV_FLSECC_BASE 0x48000000u +#define CYDEV_FLSECC_SIZE 0x00008000u +#define CYDEV_FLSECC_DATA_MBASE 0x48000000u +#define CYDEV_FLSECC_DATA_MSIZE 0x00008000u +#define CYDEV_FLSHID_BASE 0x49000000u +#define CYDEV_FLSHID_SIZE 0x00000200u +#define CYDEV_FLSHID_RSVD_MBASE 0x49000000u +#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080u +#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u +#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101u +#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u +#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u +#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u +#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105u +#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106u +#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107u +#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u +#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u +#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au +#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu +#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu +#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du +#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu +#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011au +#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011du +#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u +#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188u +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau +#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu +#define CYDEV_EXTMEM_BASE 0x60000000u +#define CYDEV_EXTMEM_SIZE 0x00800000u +#define CYDEV_EXTMEM_DATA_MBASE 0x60000000u +#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000u +#define CYDEV_ITM_BASE 0xe0000000u +#define CYDEV_ITM_SIZE 0x00001000u +#define CYDEV_ITM_TRACE_EN 0xe0000e00u +#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40u +#define CYDEV_ITM_TRACE_CTRL 0xe0000e80u +#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0u +#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4u +#define CYDEV_ITM_PID4 0xe0000fd0u +#define CYDEV_ITM_PID5 0xe0000fd4u +#define CYDEV_ITM_PID6 0xe0000fd8u +#define CYDEV_ITM_PID7 0xe0000fdcu +#define CYDEV_ITM_PID0 0xe0000fe0u +#define CYDEV_ITM_PID1 0xe0000fe4u +#define CYDEV_ITM_PID2 0xe0000fe8u +#define CYDEV_ITM_PID3 0xe0000fecu +#define CYDEV_ITM_CID0 0xe0000ff0u +#define CYDEV_ITM_CID1 0xe0000ff4u +#define CYDEV_ITM_CID2 0xe0000ff8u +#define CYDEV_ITM_CID3 0xe0000ffcu +#define CYDEV_DWT_BASE 0xe0001000u +#define CYDEV_DWT_SIZE 0x0000005cu +#define CYDEV_DWT_CTRL 0xe0001000u +#define CYDEV_DWT_CYCLE_COUNT 0xe0001004u +#define CYDEV_DWT_CPI_COUNT 0xe0001008u +#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100cu +#define CYDEV_DWT_SLEEP_COUNT 0xe0001010u +#define CYDEV_DWT_LSU_COUNT 0xe0001014u +#define CYDEV_DWT_FOLD_COUNT 0xe0001018u +#define CYDEV_DWT_PC_SAMPLE 0xe000101cu +#define CYDEV_DWT_COMP_0 0xe0001020u +#define CYDEV_DWT_MASK_0 0xe0001024u +#define CYDEV_DWT_FUNCTION_0 0xe0001028u +#define CYDEV_DWT_COMP_1 0xe0001030u +#define CYDEV_DWT_MASK_1 0xe0001034u +#define CYDEV_DWT_FUNCTION_1 0xe0001038u +#define CYDEV_DWT_COMP_2 0xe0001040u +#define CYDEV_DWT_MASK_2 0xe0001044u +#define CYDEV_DWT_FUNCTION_2 0xe0001048u +#define CYDEV_DWT_COMP_3 0xe0001050u +#define CYDEV_DWT_MASK_3 0xe0001054u +#define CYDEV_DWT_FUNCTION_3 0xe0001058u +#define CYDEV_FPB_BASE 0xe0002000u +#define CYDEV_FPB_SIZE 0x00001000u +#define CYDEV_FPB_CTRL 0xe0002000u +#define CYDEV_FPB_REMAP 0xe0002004u +#define CYDEV_FPB_FP_COMP_0 0xe0002008u +#define CYDEV_FPB_FP_COMP_1 0xe000200cu +#define CYDEV_FPB_FP_COMP_2 0xe0002010u +#define CYDEV_FPB_FP_COMP_3 0xe0002014u +#define CYDEV_FPB_FP_COMP_4 0xe0002018u +#define CYDEV_FPB_FP_COMP_5 0xe000201cu +#define CYDEV_FPB_FP_COMP_6 0xe0002020u +#define CYDEV_FPB_FP_COMP_7 0xe0002024u +#define CYDEV_FPB_PID4 0xe0002fd0u +#define CYDEV_FPB_PID5 0xe0002fd4u +#define CYDEV_FPB_PID6 0xe0002fd8u +#define CYDEV_FPB_PID7 0xe0002fdcu +#define CYDEV_FPB_PID0 0xe0002fe0u +#define CYDEV_FPB_PID1 0xe0002fe4u +#define CYDEV_FPB_PID2 0xe0002fe8u +#define CYDEV_FPB_PID3 0xe0002fecu +#define CYDEV_FPB_CID0 0xe0002ff0u +#define CYDEV_FPB_CID1 0xe0002ff4u +#define CYDEV_FPB_CID2 0xe0002ff8u +#define CYDEV_FPB_CID3 0xe0002ffcu +#define CYDEV_NVIC_BASE 0xe000e000u +#define CYDEV_NVIC_SIZE 0x00000d3cu +#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004u +#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010u +#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014u +#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018u +#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01cu +#define CYDEV_NVIC_SETENA0 0xe000e100u +#define CYDEV_NVIC_CLRENA0 0xe000e180u +#define CYDEV_NVIC_SETPEND0 0xe000e200u +#define CYDEV_NVIC_CLRPEND0 0xe000e280u +#define CYDEV_NVIC_ACTIVE0 0xe000e300u +#define CYDEV_NVIC_PRI_0 0xe000e400u +#define CYDEV_NVIC_PRI_1 0xe000e401u +#define CYDEV_NVIC_PRI_2 0xe000e402u +#define CYDEV_NVIC_PRI_3 0xe000e403u +#define CYDEV_NVIC_PRI_4 0xe000e404u +#define CYDEV_NVIC_PRI_5 0xe000e405u +#define CYDEV_NVIC_PRI_6 0xe000e406u +#define CYDEV_NVIC_PRI_7 0xe000e407u +#define CYDEV_NVIC_PRI_8 0xe000e408u +#define CYDEV_NVIC_PRI_9 0xe000e409u +#define CYDEV_NVIC_PRI_10 0xe000e40au +#define CYDEV_NVIC_PRI_11 0xe000e40bu +#define CYDEV_NVIC_PRI_12 0xe000e40cu +#define CYDEV_NVIC_PRI_13 0xe000e40du +#define CYDEV_NVIC_PRI_14 0xe000e40eu +#define CYDEV_NVIC_PRI_15 0xe000e40fu +#define CYDEV_NVIC_PRI_16 0xe000e410u +#define CYDEV_NVIC_PRI_17 0xe000e411u +#define CYDEV_NVIC_PRI_18 0xe000e412u +#define CYDEV_NVIC_PRI_19 0xe000e413u +#define CYDEV_NVIC_PRI_20 0xe000e414u +#define CYDEV_NVIC_PRI_21 0xe000e415u +#define CYDEV_NVIC_PRI_22 0xe000e416u +#define CYDEV_NVIC_PRI_23 0xe000e417u +#define CYDEV_NVIC_PRI_24 0xe000e418u +#define CYDEV_NVIC_PRI_25 0xe000e419u +#define CYDEV_NVIC_PRI_26 0xe000e41au +#define CYDEV_NVIC_PRI_27 0xe000e41bu +#define CYDEV_NVIC_PRI_28 0xe000e41cu +#define CYDEV_NVIC_PRI_29 0xe000e41du +#define CYDEV_NVIC_PRI_30 0xe000e41eu +#define CYDEV_NVIC_PRI_31 0xe000e41fu +#define CYDEV_NVIC_CPUID_BASE 0xe000ed00u +#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04u +#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08u +#define CYDEV_NVIC_APPLN_INTR 0xe000ed0cu +#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10u +#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14u +#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u +#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu +#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u +#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24u +#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u +#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29u +#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2au +#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2cu +#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u +#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u +#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38u +#define CYDEV_CORE_DBG_BASE 0xe000edf0u +#define CYDEV_CORE_DBG_SIZE 0x00000010u +#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0u +#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4u +#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8u +#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfcu +#define CYDEV_TPIU_BASE 0xe0040000u +#define CYDEV_TPIU_SIZE 0x00001000u +#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u +#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u +#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u +#define CYDEV_TPIU_PROTOCOL 0xe00400f0u +#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300u +#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304u +#define CYDEV_TPIU_TRIGGER 0xe0040ee8u +#define CYDEV_TPIU_ITETMDATA 0xe0040eecu +#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0u +#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8u +#define CYDEV_TPIU_ITITMDATA 0xe0040efcu +#define CYDEV_TPIU_ITCTRL 0xe0040f00u +#define CYDEV_TPIU_DEVID 0xe0040fc8u +#define CYDEV_TPIU_DEVTYPE 0xe0040fccu +#define CYDEV_TPIU_PID4 0xe0040fd0u +#define CYDEV_TPIU_PID5 0xe0040fd4u +#define CYDEV_TPIU_PID6 0xe0040fd8u +#define CYDEV_TPIU_PID7 0xe0040fdcu +#define CYDEV_TPIU_PID0 0xe0040fe0u +#define CYDEV_TPIU_PID1 0xe0040fe4u +#define CYDEV_TPIU_PID2 0xe0040fe8u +#define CYDEV_TPIU_PID3 0xe0040fecu +#define CYDEV_TPIU_CID0 0xe0040ff0u +#define CYDEV_TPIU_CID1 0xe0040ff4u +#define CYDEV_TPIU_CID2 0xe0040ff8u +#define CYDEV_TPIU_CID3 0xe0040ffcu +#define CYDEV_ETM_BASE 0xe0041000u +#define CYDEV_ETM_SIZE 0x00001000u +#define CYDEV_ETM_CTL 0xe0041000u +#define CYDEV_ETM_CFG_CODE 0xe0041004u +#define CYDEV_ETM_TRIG_EVENT 0xe0041008u +#define CYDEV_ETM_STATUS 0xe0041010u +#define CYDEV_ETM_SYS_CFG 0xe0041014u +#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020u +#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024u +#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102cu +#define CYDEV_ETM_SYNC_FREQ 0xe00411e0u +#define CYDEV_ETM_ETM_ID 0xe00411e4u +#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8u +#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u +#define CYDEV_ETM_CS_TRACE_ID 0xe0041200u +#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300u +#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304u +#define CYDEV_ETM_PDSR 0xe0041314u +#define CYDEV_ETM_ITMISCIN 0xe0041ee0u +#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8u +#define CYDEV_ETM_ITATBCTR2 0xe0041ef0u +#define CYDEV_ETM_ITATBCTR0 0xe0041ef8u +#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00u +#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0u +#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4u +#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0u +#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4u +#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8u +#define CYDEV_ETM_DEV_TYPE 0xe0041fccu +#define CYDEV_ETM_PID4 0xe0041fd0u +#define CYDEV_ETM_PID5 0xe0041fd4u +#define CYDEV_ETM_PID6 0xe0041fd8u +#define CYDEV_ETM_PID7 0xe0041fdcu +#define CYDEV_ETM_PID0 0xe0041fe0u +#define CYDEV_ETM_PID1 0xe0041fe4u +#define CYDEV_ETM_PID2 0xe0041fe8u +#define CYDEV_ETM_PID3 0xe0041fecu +#define CYDEV_ETM_CID0 0xe0041ff0u +#define CYDEV_ETM_CID1 0xe0041ff4u +#define CYDEV_ETM_CID2 0xe0041ff8u +#define CYDEV_ETM_CID3 0xe0041ffcu +#define CYDEV_ROM_TABLE_BASE 0xe00ff000u +#define CYDEV_ROM_TABLE_SIZE 0x00001000u +#define CYDEV_ROM_TABLE_NVIC 0xe00ff000u +#define CYDEV_ROM_TABLE_DWT 0xe00ff004u +#define CYDEV_ROM_TABLE_FPB 0xe00ff008u +#define CYDEV_ROM_TABLE_ITM 0xe00ff00cu +#define CYDEV_ROM_TABLE_TPIU 0xe00ff010u +#define CYDEV_ROM_TABLE_ETM 0xe00ff014u +#define CYDEV_ROM_TABLE_END 0xe00ff018u +#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffccu +#define CYDEV_ROM_TABLE_PID4 0xe00fffd0u +#define CYDEV_ROM_TABLE_PID5 0xe00fffd4u +#define CYDEV_ROM_TABLE_PID6 0xe00fffd8u +#define CYDEV_ROM_TABLE_PID7 0xe00fffdcu +#define CYDEV_ROM_TABLE_PID0 0xe00fffe0u +#define CYDEV_ROM_TABLE_PID1 0xe00fffe4u +#define CYDEV_ROM_TABLE_PID2 0xe00fffe8u +#define CYDEV_ROM_TABLE_PID3 0xe00fffecu +#define CYDEV_ROM_TABLE_CID0 0xe00ffff0u +#define CYDEV_ROM_TABLE_CID1 0xe00ffff4u +#define CYDEV_ROM_TABLE_CID2 0xe00ffff8u +#define CYDEV_ROM_TABLE_CID3 0xe00ffffcu +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000u +#define CYDEV_FLS_ROW_SIZE 0x00000100u +#define CYDEV_ECC_SECTOR_SIZE 0x00002000u +#define CYDEV_ECC_ROW_SIZE 0x00000020u +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u +#define CYDEV_EEPROM_ROW_SIZE 0x00000010u +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004u +#define CYCLK_LD_SYNC_EN 0x00000002u +#define CYCLK_LD_LOAD 0x00000001u +#define CYCLK_PIPE 0x00000080u +#define CYCLK_SSS 0x00000040u +#define CYCLK_EARLY 0x00000020u +#define CYCLK_DUTY 0x00000010u +#define CYCLK_SYNC 0x00000008u +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 +#endif /* CYDEVICE_H */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h new file mode 100644 index 0000000..f14bf4a --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -0,0 +1,5359 @@ +/******************************************************************************* +* FILENAME: cydevice_trm.h +* +* PSoC Creator 2.2 Component Pack 6 +* +* DESCRIPTION: +* This file provides all of the address values for the entire PSoC device. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CYDEVICE_TRM_H) +#define CYDEVICE_TRM_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00040000u +#define CYREG_FLASH_DATA_MBASE 0x00000000u +#define CYREG_FLASH_DATA_MSIZE 0x00040000u +#define CYDEV_SRAM_BASE 0x1fff8000u +#define CYDEV_SRAM_SIZE 0x00010000u +#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000u +#define CYREG_SRAM_CODE64K_MSIZE 0x00004000u +#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000u +#define CYREG_SRAM_CODE32K_MSIZE 0x00002000u +#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000u +#define CYREG_SRAM_CODE16K_MSIZE 0x00001000u +#define CYREG_SRAM_CODE_MBASE 0x1fff8000u +#define CYREG_SRAM_CODE_MSIZE 0x00008000u +#define CYREG_SRAM_DATA_MBASE 0x20000000u +#define CYREG_SRAM_DATA_MSIZE 0x00008000u +#define CYREG_SRAM_DATA16K_MBASE 0x20001000u +#define CYREG_SRAM_DATA16K_MSIZE 0x00001000u +#define CYREG_SRAM_DATA32K_MBASE 0x20002000u +#define CYREG_SRAM_DATA32K_MSIZE 0x00002000u +#define CYREG_SRAM_DATA64K_MBASE 0x20004000u +#define CYREG_SRAM_DATA64K_MSIZE 0x00004000u +#define CYDEV_DMA_BASE 0x20008000u +#define CYDEV_DMA_SIZE 0x00008000u +#define CYREG_DMA_SRAM64K_MBASE 0x20008000u +#define CYREG_DMA_SRAM64K_MSIZE 0x00004000u +#define CYREG_DMA_SRAM32K_MBASE 0x2000c000u +#define CYREG_DMA_SRAM32K_MSIZE 0x00002000u +#define CYREG_DMA_SRAM16K_MBASE 0x2000e000u +#define CYREG_DMA_SRAM16K_MSIZE 0x00001000u +#define CYREG_DMA_SRAM_MBASE 0x2000f000u +#define CYREG_DMA_SRAM_MSIZE 0x00001000u +#define CYDEV_CLKDIST_BASE 0x40004000u +#define CYDEV_CLKDIST_SIZE 0x00000110u +#define CYREG_CLKDIST_CR 0x40004000u +#define CYREG_CLKDIST_LD 0x40004001u +#define CYREG_CLKDIST_WRK0 0x40004002u +#define CYREG_CLKDIST_WRK1 0x40004003u +#define CYREG_CLKDIST_MSTR0 0x40004004u +#define CYREG_CLKDIST_MSTR1 0x40004005u +#define CYREG_CLKDIST_BCFG0 0x40004006u +#define CYREG_CLKDIST_BCFG1 0x40004007u +#define CYREG_CLKDIST_BCFG2 0x40004008u +#define CYREG_CLKDIST_UCFG 0x40004009u +#define CYREG_CLKDIST_DLY0 0x4000400au +#define CYREG_CLKDIST_DLY1 0x4000400bu +#define CYREG_CLKDIST_DMASK 0x40004010u +#define CYREG_CLKDIST_AMASK 0x40004014u +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080u +#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081u +#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082u +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084u +#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085u +#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086u +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088u +#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089u +#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408au +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408cu +#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408du +#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408eu +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090u +#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091u +#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092u +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094u +#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095u +#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096u +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098u +#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099u +#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409au +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409cu +#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409du +#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409eu +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100u +#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101u +#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102u +#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103u +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104u +#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105u +#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106u +#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107u +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108u +#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109u +#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410au +#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410bu +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410cu +#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410du +#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410eu +#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410fu +#define CYDEV_FASTCLK_BASE 0x40004200u +#define CYDEV_FASTCLK_SIZE 0x00000026u +#define CYDEV_FASTCLK_IMO_BASE 0x40004200u +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u +#define CYREG_FASTCLK_IMO_CR 0x40004200u +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u +#define CYREG_FASTCLK_XMHZ_CSR 0x40004210u +#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212u +#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213u +#define CYDEV_FASTCLK_PLL_BASE 0x40004220u +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u +#define CYREG_FASTCLK_PLL_CFG0 0x40004220u +#define CYREG_FASTCLK_PLL_CFG1 0x40004221u +#define CYREG_FASTCLK_PLL_P 0x40004222u +#define CYREG_FASTCLK_PLL_Q 0x40004223u +#define CYREG_FASTCLK_PLL_SR 0x40004225u +#define CYDEV_SLOWCLK_BASE 0x40004300u +#define CYDEV_SLOWCLK_SIZE 0x0000000bu +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u +#define CYREG_SLOWCLK_ILO_CR0 0x40004300u +#define CYREG_SLOWCLK_ILO_CR1 0x40004301u +#define CYDEV_SLOWCLK_X32_BASE 0x40004308u +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u +#define CYREG_SLOWCLK_X32_CR 0x40004308u +#define CYREG_SLOWCLK_X32_CFG 0x40004309u +#define CYREG_SLOWCLK_X32_TST 0x4000430au +#define CYDEV_BOOST_BASE 0x40004320u +#define CYDEV_BOOST_SIZE 0x00000007u +#define CYREG_BOOST_CR0 0x40004320u +#define CYREG_BOOST_CR1 0x40004321u +#define CYREG_BOOST_CR2 0x40004322u +#define CYREG_BOOST_CR3 0x40004323u +#define CYREG_BOOST_SR 0x40004324u +#define CYREG_BOOST_CR4 0x40004325u +#define CYREG_BOOST_SR2 0x40004326u +#define CYDEV_PWRSYS_BASE 0x40004330u +#define CYDEV_PWRSYS_SIZE 0x00000002u +#define CYREG_PWRSYS_CR0 0x40004330u +#define CYREG_PWRSYS_CR1 0x40004331u +#define CYDEV_PM_BASE 0x40004380u +#define CYDEV_PM_SIZE 0x00000057u +#define CYREG_PM_TW_CFG0 0x40004380u +#define CYREG_PM_TW_CFG1 0x40004381u +#define CYREG_PM_TW_CFG2 0x40004382u +#define CYREG_PM_WDT_CFG 0x40004383u +#define CYREG_PM_WDT_CR 0x40004384u +#define CYREG_PM_INT_SR 0x40004390u +#define CYREG_PM_MODE_CFG0 0x40004391u +#define CYREG_PM_MODE_CFG1 0x40004392u +#define CYREG_PM_MODE_CSR 0x40004393u +#define CYREG_PM_USB_CR0 0x40004394u +#define CYREG_PM_WAKEUP_CFG0 0x40004398u +#define CYREG_PM_WAKEUP_CFG1 0x40004399u +#define CYREG_PM_WAKEUP_CFG2 0x4000439au +#define CYDEV_PM_ACT_BASE 0x400043a0u +#define CYDEV_PM_ACT_SIZE 0x0000000eu +#define CYREG_PM_ACT_CFG0 0x400043a0u +#define CYREG_PM_ACT_CFG1 0x400043a1u +#define CYREG_PM_ACT_CFG2 0x400043a2u +#define CYREG_PM_ACT_CFG3 0x400043a3u +#define CYREG_PM_ACT_CFG4 0x400043a4u +#define CYREG_PM_ACT_CFG5 0x400043a5u +#define CYREG_PM_ACT_CFG6 0x400043a6u +#define CYREG_PM_ACT_CFG7 0x400043a7u +#define CYREG_PM_ACT_CFG8 0x400043a8u +#define CYREG_PM_ACT_CFG9 0x400043a9u +#define CYREG_PM_ACT_CFG10 0x400043aau +#define CYREG_PM_ACT_CFG11 0x400043abu +#define CYREG_PM_ACT_CFG12 0x400043acu +#define CYREG_PM_ACT_CFG13 0x400043adu +#define CYDEV_PM_STBY_BASE 0x400043b0u +#define CYDEV_PM_STBY_SIZE 0x0000000eu +#define CYREG_PM_STBY_CFG0 0x400043b0u +#define CYREG_PM_STBY_CFG1 0x400043b1u +#define CYREG_PM_STBY_CFG2 0x400043b2u +#define CYREG_PM_STBY_CFG3 0x400043b3u +#define CYREG_PM_STBY_CFG4 0x400043b4u +#define CYREG_PM_STBY_CFG5 0x400043b5u +#define CYREG_PM_STBY_CFG6 0x400043b6u +#define CYREG_PM_STBY_CFG7 0x400043b7u +#define CYREG_PM_STBY_CFG8 0x400043b8u +#define CYREG_PM_STBY_CFG9 0x400043b9u +#define CYREG_PM_STBY_CFG10 0x400043bau +#define CYREG_PM_STBY_CFG11 0x400043bbu +#define CYREG_PM_STBY_CFG12 0x400043bcu +#define CYREG_PM_STBY_CFG13 0x400043bdu +#define CYDEV_PM_AVAIL_BASE 0x400043c0u +#define CYDEV_PM_AVAIL_SIZE 0x00000017u +#define CYREG_PM_AVAIL_CR0 0x400043c0u +#define CYREG_PM_AVAIL_CR1 0x400043c1u +#define CYREG_PM_AVAIL_CR2 0x400043c2u +#define CYREG_PM_AVAIL_CR3 0x400043c3u +#define CYREG_PM_AVAIL_CR4 0x400043c4u +#define CYREG_PM_AVAIL_CR5 0x400043c5u +#define CYREG_PM_AVAIL_CR6 0x400043c6u +#define CYREG_PM_AVAIL_SR0 0x400043d0u +#define CYREG_PM_AVAIL_SR1 0x400043d1u +#define CYREG_PM_AVAIL_SR2 0x400043d2u +#define CYREG_PM_AVAIL_SR3 0x400043d3u +#define CYREG_PM_AVAIL_SR4 0x400043d4u +#define CYREG_PM_AVAIL_SR5 0x400043d5u +#define CYREG_PM_AVAIL_SR6 0x400043d6u +#define CYDEV_PICU_BASE 0x40004500u +#define CYDEV_PICU_SIZE 0x000000b0u +#define CYDEV_PICU_INTTYPE_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u +#define CYREG_PICU0_INTTYPE0 0x40004500u +#define CYREG_PICU0_INTTYPE1 0x40004501u +#define CYREG_PICU0_INTTYPE2 0x40004502u +#define CYREG_PICU0_INTTYPE3 0x40004503u +#define CYREG_PICU0_INTTYPE4 0x40004504u +#define CYREG_PICU0_INTTYPE5 0x40004505u +#define CYREG_PICU0_INTTYPE6 0x40004506u +#define CYREG_PICU0_INTTYPE7 0x40004507u +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u +#define CYREG_PICU1_INTTYPE0 0x40004508u +#define CYREG_PICU1_INTTYPE1 0x40004509u +#define CYREG_PICU1_INTTYPE2 0x4000450au +#define CYREG_PICU1_INTTYPE3 0x4000450bu +#define CYREG_PICU1_INTTYPE4 0x4000450cu +#define CYREG_PICU1_INTTYPE5 0x4000450du +#define CYREG_PICU1_INTTYPE6 0x4000450eu +#define CYREG_PICU1_INTTYPE7 0x4000450fu +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u +#define CYREG_PICU2_INTTYPE0 0x40004510u +#define CYREG_PICU2_INTTYPE1 0x40004511u +#define CYREG_PICU2_INTTYPE2 0x40004512u +#define CYREG_PICU2_INTTYPE3 0x40004513u +#define CYREG_PICU2_INTTYPE4 0x40004514u +#define CYREG_PICU2_INTTYPE5 0x40004515u +#define CYREG_PICU2_INTTYPE6 0x40004516u +#define CYREG_PICU2_INTTYPE7 0x40004517u +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u +#define CYREG_PICU3_INTTYPE0 0x40004518u +#define CYREG_PICU3_INTTYPE1 0x40004519u +#define CYREG_PICU3_INTTYPE2 0x4000451au +#define CYREG_PICU3_INTTYPE3 0x4000451bu +#define CYREG_PICU3_INTTYPE4 0x4000451cu +#define CYREG_PICU3_INTTYPE5 0x4000451du +#define CYREG_PICU3_INTTYPE6 0x4000451eu +#define CYREG_PICU3_INTTYPE7 0x4000451fu +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u +#define CYREG_PICU4_INTTYPE0 0x40004520u +#define CYREG_PICU4_INTTYPE1 0x40004521u +#define CYREG_PICU4_INTTYPE2 0x40004522u +#define CYREG_PICU4_INTTYPE3 0x40004523u +#define CYREG_PICU4_INTTYPE4 0x40004524u +#define CYREG_PICU4_INTTYPE5 0x40004525u +#define CYREG_PICU4_INTTYPE6 0x40004526u +#define CYREG_PICU4_INTTYPE7 0x40004527u +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u +#define CYREG_PICU5_INTTYPE0 0x40004528u +#define CYREG_PICU5_INTTYPE1 0x40004529u +#define CYREG_PICU5_INTTYPE2 0x4000452au +#define CYREG_PICU5_INTTYPE3 0x4000452bu +#define CYREG_PICU5_INTTYPE4 0x4000452cu +#define CYREG_PICU5_INTTYPE5 0x4000452du +#define CYREG_PICU5_INTTYPE6 0x4000452eu +#define CYREG_PICU5_INTTYPE7 0x4000452fu +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u +#define CYREG_PICU6_INTTYPE0 0x40004530u +#define CYREG_PICU6_INTTYPE1 0x40004531u +#define CYREG_PICU6_INTTYPE2 0x40004532u +#define CYREG_PICU6_INTTYPE3 0x40004533u +#define CYREG_PICU6_INTTYPE4 0x40004534u +#define CYREG_PICU6_INTTYPE5 0x40004535u +#define CYREG_PICU6_INTTYPE6 0x40004536u +#define CYREG_PICU6_INTTYPE7 0x40004537u +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u +#define CYREG_PICU12_INTTYPE0 0x40004560u +#define CYREG_PICU12_INTTYPE1 0x40004561u +#define CYREG_PICU12_INTTYPE2 0x40004562u +#define CYREG_PICU12_INTTYPE3 0x40004563u +#define CYREG_PICU12_INTTYPE4 0x40004564u +#define CYREG_PICU12_INTTYPE5 0x40004565u +#define CYREG_PICU12_INTTYPE6 0x40004566u +#define CYREG_PICU12_INTTYPE7 0x40004567u +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u +#define CYREG_PICU15_INTTYPE0 0x40004578u +#define CYREG_PICU15_INTTYPE1 0x40004579u +#define CYREG_PICU15_INTTYPE2 0x4000457au +#define CYREG_PICU15_INTTYPE3 0x4000457bu +#define CYREG_PICU15_INTTYPE4 0x4000457cu +#define CYREG_PICU15_INTTYPE5 0x4000457du +#define CYREG_PICU15_INTTYPE6 0x4000457eu +#define CYREG_PICU15_INTTYPE7 0x4000457fu +#define CYDEV_PICU_STAT_BASE 0x40004580u +#define CYDEV_PICU_STAT_SIZE 0x00000010u +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_INTSTAT 0x40004580u +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_INTSTAT 0x40004581u +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_INTSTAT 0x40004582u +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_INTSTAT 0x40004583u +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_INTSTAT 0x40004584u +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_INTSTAT 0x40004585u +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_INTSTAT 0x40004586u +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_INTSTAT 0x4000458cu +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u +#define CYREG_PICU15_INTSTAT 0x4000458fu +#define CYDEV_PICU_SNAP_BASE 0x40004590u +#define CYDEV_PICU_SNAP_SIZE 0x00000010u +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_SNAP 0x40004590u +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_SNAP 0x40004591u +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_SNAP 0x40004592u +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_SNAP 0x40004593u +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_SNAP 0x40004594u +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_SNAP 0x40004595u +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_SNAP 0x40004596u +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_SNAP 0x4000459cu +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u +#define CYREG_PICU_15_SNAP_15 0x4000459fu +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_DISABLE_COR 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_DISABLE_COR 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_DISABLE_COR 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_DISABLE_COR 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_DISABLE_COR 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_DISABLE_COR 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_DISABLE_COR 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_DISABLE_COR 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u +#define CYREG_PICU15_DISABLE_COR 0x400045afu +#define CYDEV_MFGCFG_BASE 0x40004600u +#define CYDEV_MFGCFG_SIZE 0x000000edu +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u +#define CYREG_DAC0_TR 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u +#define CYREG_DAC1_TR 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u +#define CYREG_DAC2_TR 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u +#define CYREG_DAC3_TR 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u +#define CYREG_NPUMP_DSM_TR0 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u +#define CYREG_NPUMP_SC_TR0 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u +#define CYREG_NPUMP_OPAMP_TR0 0x40004612u +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u +#define CYREG_SAR0_TR0 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u +#define CYREG_SAR1_TR0 0x40004616u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_TR0 0x40004620u +#define CYREG_OPAMP0_TR1 0x40004621u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_TR0 0x40004622u +#define CYREG_OPAMP1_TR1 0x40004623u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_TR0 0x40004624u +#define CYREG_OPAMP2_TR1 0x40004625u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_TR0 0x40004626u +#define CYREG_OPAMP3_TR1 0x40004627u +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u +#define CYREG_CMP0_TR0 0x40004630u +#define CYREG_CMP0_TR1 0x40004631u +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u +#define CYREG_CMP1_TR0 0x40004632u +#define CYREG_CMP1_TR1 0x40004633u +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u +#define CYREG_CMP2_TR0 0x40004634u +#define CYREG_CMP2_TR1 0x40004635u +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u +#define CYREG_CMP3_TR0 0x40004636u +#define CYREG_CMP3_TR1 0x40004637u +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu +#define CYREG_PWRSYS_HIB_TR0 0x40004680u +#define CYREG_PWRSYS_HIB_TR1 0x40004681u +#define CYREG_PWRSYS_I2C_TR 0x40004682u +#define CYREG_PWRSYS_SLP_TR 0x40004683u +#define CYREG_PWRSYS_BUZZ_TR 0x40004684u +#define CYREG_PWRSYS_WAKE_TR0 0x40004685u +#define CYREG_PWRSYS_WAKE_TR1 0x40004686u +#define CYREG_PWRSYS_BREF_TR 0x40004687u +#define CYREG_PWRSYS_BG_TR 0x40004688u +#define CYREG_PWRSYS_WAKE_TR2 0x40004689u +#define CYREG_PWRSYS_WAKE_TR3 0x4000468au +#define CYDEV_MFGCFG_ILO_BASE 0x40004690u +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u +#define CYREG_ILO_TR0 0x40004690u +#define CYREG_ILO_TR1 0x40004691u +#define CYDEV_MFGCFG_X32_BASE 0x40004698u +#define CYDEV_MFGCFG_X32_SIZE 0x00000001u +#define CYREG_X32_TR 0x40004698u +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u +#define CYREG_IMO_TR0 0x400046a0u +#define CYREG_IMO_TR1 0x400046a1u +#define CYREG_IMO_GAIN 0x400046a2u +#define CYREG_IMO_C36M 0x400046a3u +#define CYREG_IMO_TR2 0x400046a4u +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u +#define CYREG_XMHZ_TR 0x400046a8u +#define CYREG_MFGCFG_DLY 0x400046c0u +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du +#define CYREG_MLOGIC_DMPSTR 0x400046e2u +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u +#define CYREG_MLOGIC_SEG_CR 0x400046e4u +#define CYREG_MLOGIC_SEG_CFG0 0x400046e5u +#define CYREG_MLOGIC_DEBUG 0x400046e8u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u +#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau +#define CYREG_MLOGIC_REV_ID 0x400046ecu +#define CYDEV_RESET_BASE 0x400046f0u +#define CYDEV_RESET_SIZE 0x0000000fu +#define CYREG_RESET_IPOR_CR0 0x400046f0u +#define CYREG_RESET_IPOR_CR1 0x400046f1u +#define CYREG_RESET_IPOR_CR2 0x400046f2u +#define CYREG_RESET_IPOR_CR3 0x400046f3u +#define CYREG_RESET_CR0 0x400046f4u +#define CYREG_RESET_CR1 0x400046f5u +#define CYREG_RESET_CR2 0x400046f6u +#define CYREG_RESET_CR3 0x400046f7u +#define CYREG_RESET_CR4 0x400046f8u +#define CYREG_RESET_CR5 0x400046f9u +#define CYREG_RESET_SR0 0x400046fau +#define CYREG_RESET_SR1 0x400046fbu +#define CYREG_RESET_SR2 0x400046fcu +#define CYREG_RESET_SR3 0x400046fdu +#define CYREG_RESET_TR 0x400046feu +#define CYDEV_SPC_BASE 0x40004700u +#define CYDEV_SPC_SIZE 0x00000100u +#define CYREG_SPC_FM_EE_CR 0x40004700u +#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701u +#define CYREG_SPC_EE_SCR 0x40004702u +#define CYREG_SPC_EE_ERR 0x40004703u +#define CYREG_SPC_CPU_DATA 0x40004720u +#define CYREG_SPC_DMA_DATA 0x40004721u +#define CYREG_SPC_SR 0x40004722u +#define CYREG_SPC_CR 0x40004723u +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u +#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780u +#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u +#define CYDEV_CACHE_BASE 0x40004800u +#define CYDEV_CACHE_SIZE 0x0000009cu +#define CYREG_CACHE_CC_CTL 0x40004800u +#define CYREG_CACHE_ECC_CORR 0x40004880u +#define CYREG_CACHE_ECC_ERR 0x40004888u +#define CYREG_CACHE_FLASH_ERR 0x40004890u +#define CYREG_CACHE_HITMISS 0x40004898u +#define CYDEV_I2C_BASE 0x40004900u +#define CYDEV_I2C_SIZE 0x000000e1u +#define CYREG_I2C_XCFG 0x400049c8u +#define CYREG_I2C_ADR 0x400049cau +#define CYREG_I2C_CFG 0x400049d6u +#define CYREG_I2C_CSR 0x400049d7u +#define CYREG_I2C_D 0x400049d8u +#define CYREG_I2C_MCSR 0x400049d9u +#define CYREG_I2C_CLK_DIV1 0x400049dbu +#define CYREG_I2C_CLK_DIV2 0x400049dcu +#define CYREG_I2C_TMOUT_CSR 0x400049ddu +#define CYREG_I2C_TMOUT_SR 0x400049deu +#define CYREG_I2C_TMOUT_CFG0 0x400049dfu +#define CYREG_I2C_TMOUT_CFG1 0x400049e0u +#define CYDEV_DEC_BASE 0x40004e00u +#define CYDEV_DEC_SIZE 0x00000015u +#define CYREG_DEC_CR 0x40004e00u +#define CYREG_DEC_SR 0x40004e01u +#define CYREG_DEC_SHIFT1 0x40004e02u +#define CYREG_DEC_SHIFT2 0x40004e03u +#define CYREG_DEC_DR2 0x40004e04u +#define CYREG_DEC_DR2H 0x40004e05u +#define CYREG_DEC_DR1 0x40004e06u +#define CYREG_DEC_OCOR 0x40004e08u +#define CYREG_DEC_OCORM 0x40004e09u +#define CYREG_DEC_OCORH 0x40004e0au +#define CYREG_DEC_GCOR 0x40004e0cu +#define CYREG_DEC_GCORH 0x40004e0du +#define CYREG_DEC_GVAL 0x40004e0eu +#define CYREG_DEC_OUTSAMP 0x40004e10u +#define CYREG_DEC_OUTSAMPM 0x40004e11u +#define CYREG_DEC_OUTSAMPH 0x40004e12u +#define CYREG_DEC_OUTSAMPS 0x40004e13u +#define CYREG_DEC_COHER 0x40004e14u +#define CYDEV_TMR0_BASE 0x40004f00u +#define CYDEV_TMR0_SIZE 0x0000000cu +#define CYREG_TMR0_CFG0 0x40004f00u +#define CYREG_TMR0_CFG1 0x40004f01u +#define CYREG_TMR0_CFG2 0x40004f02u +#define CYREG_TMR0_SR0 0x40004f03u +#define CYREG_TMR0_PER0 0x40004f04u +#define CYREG_TMR0_PER1 0x40004f05u +#define CYREG_TMR0_CNT_CMP0 0x40004f06u +#define CYREG_TMR0_CNT_CMP1 0x40004f07u +#define CYREG_TMR0_CAP0 0x40004f08u +#define CYREG_TMR0_CAP1 0x40004f09u +#define CYREG_TMR0_RT0 0x40004f0au +#define CYREG_TMR0_RT1 0x40004f0bu +#define CYDEV_TMR1_BASE 0x40004f0cu +#define CYDEV_TMR1_SIZE 0x0000000cu +#define CYREG_TMR1_CFG0 0x40004f0cu +#define CYREG_TMR1_CFG1 0x40004f0du +#define CYREG_TMR1_CFG2 0x40004f0eu +#define CYREG_TMR1_SR0 0x40004f0fu +#define CYREG_TMR1_PER0 0x40004f10u +#define CYREG_TMR1_PER1 0x40004f11u +#define CYREG_TMR1_CNT_CMP0 0x40004f12u +#define CYREG_TMR1_CNT_CMP1 0x40004f13u +#define CYREG_TMR1_CAP0 0x40004f14u +#define CYREG_TMR1_CAP1 0x40004f15u +#define CYREG_TMR1_RT0 0x40004f16u +#define CYREG_TMR1_RT1 0x40004f17u +#define CYDEV_TMR2_BASE 0x40004f18u +#define CYDEV_TMR2_SIZE 0x0000000cu +#define CYREG_TMR2_CFG0 0x40004f18u +#define CYREG_TMR2_CFG1 0x40004f19u +#define CYREG_TMR2_CFG2 0x40004f1au +#define CYREG_TMR2_SR0 0x40004f1bu +#define CYREG_TMR2_PER0 0x40004f1cu +#define CYREG_TMR2_PER1 0x40004f1du +#define CYREG_TMR2_CNT_CMP0 0x40004f1eu +#define CYREG_TMR2_CNT_CMP1 0x40004f1fu +#define CYREG_TMR2_CAP0 0x40004f20u +#define CYREG_TMR2_CAP1 0x40004f21u +#define CYREG_TMR2_RT0 0x40004f22u +#define CYREG_TMR2_RT1 0x40004f23u +#define CYDEV_TMR3_BASE 0x40004f24u +#define CYDEV_TMR3_SIZE 0x0000000cu +#define CYREG_TMR3_CFG0 0x40004f24u +#define CYREG_TMR3_CFG1 0x40004f25u +#define CYREG_TMR3_CFG2 0x40004f26u +#define CYREG_TMR3_SR0 0x40004f27u +#define CYREG_TMR3_PER0 0x40004f28u +#define CYREG_TMR3_PER1 0x40004f29u +#define CYREG_TMR3_CNT_CMP0 0x40004f2au +#define CYREG_TMR3_CNT_CMP1 0x40004f2bu +#define CYREG_TMR3_CAP0 0x40004f2cu +#define CYREG_TMR3_CAP1 0x40004f2du +#define CYREG_TMR3_RT0 0x40004f2eu +#define CYREG_TMR3_RT1 0x40004f2fu +#define CYDEV_IO_BASE 0x40005000u +#define CYDEV_IO_SIZE 0x00000200u +#define CYDEV_IO_PC_BASE 0x40005000u +#define CYDEV_IO_PC_SIZE 0x00000080u +#define CYDEV_IO_PC_PRT0_BASE 0x40005000u +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u +#define CYREG_PRT0_PC0 0x40005000u +#define CYREG_PRT0_PC1 0x40005001u +#define CYREG_PRT0_PC2 0x40005002u +#define CYREG_PRT0_PC3 0x40005003u +#define CYREG_PRT0_PC4 0x40005004u +#define CYREG_PRT0_PC5 0x40005005u +#define CYREG_PRT0_PC6 0x40005006u +#define CYREG_PRT0_PC7 0x40005007u +#define CYDEV_IO_PC_PRT1_BASE 0x40005008u +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u +#define CYREG_PRT1_PC0 0x40005008u +#define CYREG_PRT1_PC1 0x40005009u +#define CYREG_PRT1_PC2 0x4000500au +#define CYREG_PRT1_PC3 0x4000500bu +#define CYREG_PRT1_PC4 0x4000500cu +#define CYREG_PRT1_PC5 0x4000500du +#define CYREG_PRT1_PC6 0x4000500eu +#define CYREG_PRT1_PC7 0x4000500fu +#define CYDEV_IO_PC_PRT2_BASE 0x40005010u +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u +#define CYREG_PRT2_PC0 0x40005010u +#define CYREG_PRT2_PC1 0x40005011u +#define CYREG_PRT2_PC2 0x40005012u +#define CYREG_PRT2_PC3 0x40005013u +#define CYREG_PRT2_PC4 0x40005014u +#define CYREG_PRT2_PC5 0x40005015u +#define CYREG_PRT2_PC6 0x40005016u +#define CYREG_PRT2_PC7 0x40005017u +#define CYDEV_IO_PC_PRT3_BASE 0x40005018u +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u +#define CYREG_PRT3_PC0 0x40005018u +#define CYREG_PRT3_PC1 0x40005019u +#define CYREG_PRT3_PC2 0x4000501au +#define CYREG_PRT3_PC3 0x4000501bu +#define CYREG_PRT3_PC4 0x4000501cu +#define CYREG_PRT3_PC5 0x4000501du +#define CYREG_PRT3_PC6 0x4000501eu +#define CYREG_PRT3_PC7 0x4000501fu +#define CYDEV_IO_PC_PRT4_BASE 0x40005020u +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u +#define CYREG_PRT4_PC0 0x40005020u +#define CYREG_PRT4_PC1 0x40005021u +#define CYREG_PRT4_PC2 0x40005022u +#define CYREG_PRT4_PC3 0x40005023u +#define CYREG_PRT4_PC4 0x40005024u +#define CYREG_PRT4_PC5 0x40005025u +#define CYREG_PRT4_PC6 0x40005026u +#define CYREG_PRT4_PC7 0x40005027u +#define CYDEV_IO_PC_PRT5_BASE 0x40005028u +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u +#define CYREG_PRT5_PC0 0x40005028u +#define CYREG_PRT5_PC1 0x40005029u +#define CYREG_PRT5_PC2 0x4000502au +#define CYREG_PRT5_PC3 0x4000502bu +#define CYREG_PRT5_PC4 0x4000502cu +#define CYREG_PRT5_PC5 0x4000502du +#define CYREG_PRT5_PC6 0x4000502eu +#define CYREG_PRT5_PC7 0x4000502fu +#define CYDEV_IO_PC_PRT6_BASE 0x40005030u +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u +#define CYREG_PRT6_PC0 0x40005030u +#define CYREG_PRT6_PC1 0x40005031u +#define CYREG_PRT6_PC2 0x40005032u +#define CYREG_PRT6_PC3 0x40005033u +#define CYREG_PRT6_PC4 0x40005034u +#define CYREG_PRT6_PC5 0x40005035u +#define CYREG_PRT6_PC6 0x40005036u +#define CYREG_PRT6_PC7 0x40005037u +#define CYDEV_IO_PC_PRT12_BASE 0x40005060u +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u +#define CYREG_PRT12_PC0 0x40005060u +#define CYREG_PRT12_PC1 0x40005061u +#define CYREG_PRT12_PC2 0x40005062u +#define CYREG_PRT12_PC3 0x40005063u +#define CYREG_PRT12_PC4 0x40005064u +#define CYREG_PRT12_PC5 0x40005065u +#define CYREG_PRT12_PC6 0x40005066u +#define CYREG_PRT12_PC7 0x40005067u +#define CYDEV_IO_PC_PRT15_BASE 0x40005078u +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u +#define CYREG_IO_PC_PRT15_PC0 0x40005078u +#define CYREG_IO_PC_PRT15_PC1 0x40005079u +#define CYREG_IO_PC_PRT15_PC2 0x4000507au +#define CYREG_IO_PC_PRT15_PC3 0x4000507bu +#define CYREG_IO_PC_PRT15_PC4 0x4000507cu +#define CYREG_IO_PC_PRT15_PC5 0x4000507du +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u +#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507eu +#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507fu +#define CYDEV_IO_DR_BASE 0x40005080u +#define CYDEV_IO_DR_SIZE 0x00000010u +#define CYDEV_IO_DR_PRT0_BASE 0x40005080u +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u +#define CYREG_PRT0_DR_ALIAS 0x40005080u +#define CYDEV_IO_DR_PRT1_BASE 0x40005081u +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u +#define CYREG_PRT1_DR_ALIAS 0x40005081u +#define CYDEV_IO_DR_PRT2_BASE 0x40005082u +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u +#define CYREG_PRT2_DR_ALIAS 0x40005082u +#define CYDEV_IO_DR_PRT3_BASE 0x40005083u +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u +#define CYREG_PRT3_DR_ALIAS 0x40005083u +#define CYDEV_IO_DR_PRT4_BASE 0x40005084u +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u +#define CYREG_PRT4_DR_ALIAS 0x40005084u +#define CYDEV_IO_DR_PRT5_BASE 0x40005085u +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u +#define CYREG_PRT5_DR_ALIAS 0x40005085u +#define CYDEV_IO_DR_PRT6_BASE 0x40005086u +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u +#define CYREG_PRT6_DR_ALIAS 0x40005086u +#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u +#define CYREG_PRT12_DR_ALIAS 0x4000508cu +#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u +#define CYREG_PRT15_DR_15_ALIAS 0x4000508fu +#define CYDEV_IO_PS_BASE 0x40005090u +#define CYDEV_IO_PS_SIZE 0x00000010u +#define CYDEV_IO_PS_PRT0_BASE 0x40005090u +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u +#define CYREG_PRT0_PS_ALIAS 0x40005090u +#define CYDEV_IO_PS_PRT1_BASE 0x40005091u +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u +#define CYREG_PRT1_PS_ALIAS 0x40005091u +#define CYDEV_IO_PS_PRT2_BASE 0x40005092u +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u +#define CYREG_PRT2_PS_ALIAS 0x40005092u +#define CYDEV_IO_PS_PRT3_BASE 0x40005093u +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u +#define CYREG_PRT3_PS_ALIAS 0x40005093u +#define CYDEV_IO_PS_PRT4_BASE 0x40005094u +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u +#define CYREG_PRT4_PS_ALIAS 0x40005094u +#define CYDEV_IO_PS_PRT5_BASE 0x40005095u +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u +#define CYREG_PRT5_PS_ALIAS 0x40005095u +#define CYDEV_IO_PS_PRT6_BASE 0x40005096u +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u +#define CYREG_PRT6_PS_ALIAS 0x40005096u +#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u +#define CYREG_PRT12_PS_ALIAS 0x4000509cu +#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u +#define CYREG_PRT15_PS15_ALIAS 0x4000509fu +#define CYDEV_IO_PRT_BASE 0x40005100u +#define CYDEV_IO_PRT_SIZE 0x00000100u +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u +#define CYREG_PRT0_DR 0x40005100u +#define CYREG_PRT0_PS 0x40005101u +#define CYREG_PRT0_DM0 0x40005102u +#define CYREG_PRT0_DM1 0x40005103u +#define CYREG_PRT0_DM2 0x40005104u +#define CYREG_PRT0_SLW 0x40005105u +#define CYREG_PRT0_BYP 0x40005106u +#define CYREG_PRT0_BIE 0x40005107u +#define CYREG_PRT0_INP_DIS 0x40005108u +#define CYREG_PRT0_CTL 0x40005109u +#define CYREG_PRT0_PRT 0x4000510au +#define CYREG_PRT0_BIT_MASK 0x4000510bu +#define CYREG_PRT0_AMUX 0x4000510cu +#define CYREG_PRT0_AG 0x4000510du +#define CYREG_PRT0_LCD_COM_SEG 0x4000510eu +#define CYREG_PRT0_LCD_EN 0x4000510fu +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u +#define CYREG_PRT1_DR 0x40005110u +#define CYREG_PRT1_PS 0x40005111u +#define CYREG_PRT1_DM0 0x40005112u +#define CYREG_PRT1_DM1 0x40005113u +#define CYREG_PRT1_DM2 0x40005114u +#define CYREG_PRT1_SLW 0x40005115u +#define CYREG_PRT1_BYP 0x40005116u +#define CYREG_PRT1_BIE 0x40005117u +#define CYREG_PRT1_INP_DIS 0x40005118u +#define CYREG_PRT1_CTL 0x40005119u +#define CYREG_PRT1_PRT 0x4000511au +#define CYREG_PRT1_BIT_MASK 0x4000511bu +#define CYREG_PRT1_AMUX 0x4000511cu +#define CYREG_PRT1_AG 0x4000511du +#define CYREG_PRT1_LCD_COM_SEG 0x4000511eu +#define CYREG_PRT1_LCD_EN 0x4000511fu +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u +#define CYREG_PRT2_DR 0x40005120u +#define CYREG_PRT2_PS 0x40005121u +#define CYREG_PRT2_DM0 0x40005122u +#define CYREG_PRT2_DM1 0x40005123u +#define CYREG_PRT2_DM2 0x40005124u +#define CYREG_PRT2_SLW 0x40005125u +#define CYREG_PRT2_BYP 0x40005126u +#define CYREG_PRT2_BIE 0x40005127u +#define CYREG_PRT2_INP_DIS 0x40005128u +#define CYREG_PRT2_CTL 0x40005129u +#define CYREG_PRT2_PRT 0x4000512au +#define CYREG_PRT2_BIT_MASK 0x4000512bu +#define CYREG_PRT2_AMUX 0x4000512cu +#define CYREG_PRT2_AG 0x4000512du +#define CYREG_PRT2_LCD_COM_SEG 0x4000512eu +#define CYREG_PRT2_LCD_EN 0x4000512fu +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u +#define CYREG_PRT3_DR 0x40005130u +#define CYREG_PRT3_PS 0x40005131u +#define CYREG_PRT3_DM0 0x40005132u +#define CYREG_PRT3_DM1 0x40005133u +#define CYREG_PRT3_DM2 0x40005134u +#define CYREG_PRT3_SLW 0x40005135u +#define CYREG_PRT3_BYP 0x40005136u +#define CYREG_PRT3_BIE 0x40005137u +#define CYREG_PRT3_INP_DIS 0x40005138u +#define CYREG_PRT3_CTL 0x40005139u +#define CYREG_PRT3_PRT 0x4000513au +#define CYREG_PRT3_BIT_MASK 0x4000513bu +#define CYREG_PRT3_AMUX 0x4000513cu +#define CYREG_PRT3_AG 0x4000513du +#define CYREG_PRT3_LCD_COM_SEG 0x4000513eu +#define CYREG_PRT3_LCD_EN 0x4000513fu +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u +#define CYREG_PRT4_DR 0x40005140u +#define CYREG_PRT4_PS 0x40005141u +#define CYREG_PRT4_DM0 0x40005142u +#define CYREG_PRT4_DM1 0x40005143u +#define CYREG_PRT4_DM2 0x40005144u +#define CYREG_PRT4_SLW 0x40005145u +#define CYREG_PRT4_BYP 0x40005146u +#define CYREG_PRT4_BIE 0x40005147u +#define CYREG_PRT4_INP_DIS 0x40005148u +#define CYREG_PRT4_CTL 0x40005149u +#define CYREG_PRT4_PRT 0x4000514au +#define CYREG_PRT4_BIT_MASK 0x4000514bu +#define CYREG_PRT4_AMUX 0x4000514cu +#define CYREG_PRT4_AG 0x4000514du +#define CYREG_PRT4_LCD_COM_SEG 0x4000514eu +#define CYREG_PRT4_LCD_EN 0x4000514fu +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u +#define CYREG_PRT5_DR 0x40005150u +#define CYREG_PRT5_PS 0x40005151u +#define CYREG_PRT5_DM0 0x40005152u +#define CYREG_PRT5_DM1 0x40005153u +#define CYREG_PRT5_DM2 0x40005154u +#define CYREG_PRT5_SLW 0x40005155u +#define CYREG_PRT5_BYP 0x40005156u +#define CYREG_PRT5_BIE 0x40005157u +#define CYREG_PRT5_INP_DIS 0x40005158u +#define CYREG_PRT5_CTL 0x40005159u +#define CYREG_PRT5_PRT 0x4000515au +#define CYREG_PRT5_BIT_MASK 0x4000515bu +#define CYREG_PRT5_AMUX 0x4000515cu +#define CYREG_PRT5_AG 0x4000515du +#define CYREG_PRT5_LCD_COM_SEG 0x4000515eu +#define CYREG_PRT5_LCD_EN 0x4000515fu +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u +#define CYREG_PRT6_DR 0x40005160u +#define CYREG_PRT6_PS 0x40005161u +#define CYREG_PRT6_DM0 0x40005162u +#define CYREG_PRT6_DM1 0x40005163u +#define CYREG_PRT6_DM2 0x40005164u +#define CYREG_PRT6_SLW 0x40005165u +#define CYREG_PRT6_BYP 0x40005166u +#define CYREG_PRT6_BIE 0x40005167u +#define CYREG_PRT6_INP_DIS 0x40005168u +#define CYREG_PRT6_CTL 0x40005169u +#define CYREG_PRT6_PRT 0x4000516au +#define CYREG_PRT6_BIT_MASK 0x4000516bu +#define CYREG_PRT6_AMUX 0x4000516cu +#define CYREG_PRT6_AG 0x4000516du +#define CYREG_PRT6_LCD_COM_SEG 0x4000516eu +#define CYREG_PRT6_LCD_EN 0x4000516fu +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u +#define CYREG_PRT12_DR 0x400051c0u +#define CYREG_PRT12_PS 0x400051c1u +#define CYREG_PRT12_DM0 0x400051c2u +#define CYREG_PRT12_DM1 0x400051c3u +#define CYREG_PRT12_DM2 0x400051c4u +#define CYREG_PRT12_SLW 0x400051c5u +#define CYREG_PRT12_BYP 0x400051c6u +#define CYREG_PRT12_BIE 0x400051c7u +#define CYREG_PRT12_INP_DIS 0x400051c8u +#define CYREG_PRT12_SIO_HYST_EN 0x400051c9u +#define CYREG_PRT12_PRT 0x400051cau +#define CYREG_PRT12_BIT_MASK 0x400051cbu +#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051ccu +#define CYREG_PRT12_AG 0x400051cdu +#define CYREG_PRT12_SIO_CFG 0x400051ceu +#define CYREG_PRT12_SIO_DIFF 0x400051cfu +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u +#define CYREG_PRT15_DR 0x400051f0u +#define CYREG_PRT15_PS 0x400051f1u +#define CYREG_PRT15_DM0 0x400051f2u +#define CYREG_PRT15_DM1 0x400051f3u +#define CYREG_PRT15_DM2 0x400051f4u +#define CYREG_PRT15_SLW 0x400051f5u +#define CYREG_PRT15_BYP 0x400051f6u +#define CYREG_PRT15_BIE 0x400051f7u +#define CYREG_PRT15_INP_DIS 0x400051f8u +#define CYREG_PRT15_CTL 0x400051f9u +#define CYREG_PRT15_PRT 0x400051fau +#define CYREG_PRT15_BIT_MASK 0x400051fbu +#define CYREG_PRT15_AMUX 0x400051fcu +#define CYREG_PRT15_AG 0x400051fdu +#define CYREG_PRT15_LCD_COM_SEG 0x400051feu +#define CYREG_PRT15_LCD_EN 0x400051ffu +#define CYDEV_PRTDSI_BASE 0x40005200u +#define CYDEV_PRTDSI_SIZE 0x0000007fu +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u +#define CYREG_PRT0_OUT_SEL0 0x40005200u +#define CYREG_PRT0_OUT_SEL1 0x40005201u +#define CYREG_PRT0_OE_SEL0 0x40005202u +#define CYREG_PRT0_OE_SEL1 0x40005203u +#define CYREG_PRT0_DBL_SYNC_IN 0x40005204u +#define CYREG_PRT0_SYNC_OUT 0x40005205u +#define CYREG_PRT0_CAPS_SEL 0x40005206u +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u +#define CYREG_PRT1_OUT_SEL0 0x40005208u +#define CYREG_PRT1_OUT_SEL1 0x40005209u +#define CYREG_PRT1_OE_SEL0 0x4000520au +#define CYREG_PRT1_OE_SEL1 0x4000520bu +#define CYREG_PRT1_DBL_SYNC_IN 0x4000520cu +#define CYREG_PRT1_SYNC_OUT 0x4000520du +#define CYREG_PRT1_CAPS_SEL 0x4000520eu +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u +#define CYREG_PRT2_OUT_SEL0 0x40005210u +#define CYREG_PRT2_OUT_SEL1 0x40005211u +#define CYREG_PRT2_OE_SEL0 0x40005212u +#define CYREG_PRT2_OE_SEL1 0x40005213u +#define CYREG_PRT2_DBL_SYNC_IN 0x40005214u +#define CYREG_PRT2_SYNC_OUT 0x40005215u +#define CYREG_PRT2_CAPS_SEL 0x40005216u +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u +#define CYREG_PRT3_OUT_SEL0 0x40005218u +#define CYREG_PRT3_OUT_SEL1 0x40005219u +#define CYREG_PRT3_OE_SEL0 0x4000521au +#define CYREG_PRT3_OE_SEL1 0x4000521bu +#define CYREG_PRT3_DBL_SYNC_IN 0x4000521cu +#define CYREG_PRT3_SYNC_OUT 0x4000521du +#define CYREG_PRT3_CAPS_SEL 0x4000521eu +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u +#define CYREG_PRT4_OUT_SEL0 0x40005220u +#define CYREG_PRT4_OUT_SEL1 0x40005221u +#define CYREG_PRT4_OE_SEL0 0x40005222u +#define CYREG_PRT4_OE_SEL1 0x40005223u +#define CYREG_PRT4_DBL_SYNC_IN 0x40005224u +#define CYREG_PRT4_SYNC_OUT 0x40005225u +#define CYREG_PRT4_CAPS_SEL 0x40005226u +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u +#define CYREG_PRT5_OUT_SEL0 0x40005228u +#define CYREG_PRT5_OUT_SEL1 0x40005229u +#define CYREG_PRT5_OE_SEL0 0x4000522au +#define CYREG_PRT5_OE_SEL1 0x4000522bu +#define CYREG_PRT5_DBL_SYNC_IN 0x4000522cu +#define CYREG_PRT5_SYNC_OUT 0x4000522du +#define CYREG_PRT5_CAPS_SEL 0x4000522eu +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u +#define CYREG_PRT6_OUT_SEL0 0x40005230u +#define CYREG_PRT6_OUT_SEL1 0x40005231u +#define CYREG_PRT6_OE_SEL0 0x40005232u +#define CYREG_PRT6_OE_SEL1 0x40005233u +#define CYREG_PRT6_DBL_SYNC_IN 0x40005234u +#define CYREG_PRT6_SYNC_OUT 0x40005235u +#define CYREG_PRT6_CAPS_SEL 0x40005236u +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u +#define CYREG_PRT12_OUT_SEL0 0x40005260u +#define CYREG_PRT12_OUT_SEL1 0x40005261u +#define CYREG_PRT12_OE_SEL0 0x40005262u +#define CYREG_PRT12_OE_SEL1 0x40005263u +#define CYREG_PRT12_DBL_SYNC_IN 0x40005264u +#define CYREG_PRT12_SYNC_OUT 0x40005265u +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u +#define CYREG_PRT15_OUT_SEL0 0x40005278u +#define CYREG_PRT15_OUT_SEL1 0x40005279u +#define CYREG_PRT15_OE_SEL0 0x4000527au +#define CYREG_PRT15_OE_SEL1 0x4000527bu +#define CYREG_PRT15_DBL_SYNC_IN 0x4000527cu +#define CYREG_PRT15_SYNC_OUT 0x4000527du +#define CYREG_PRT15_CAPS_SEL 0x4000527eu +#define CYDEV_EMIF_BASE 0x40005400u +#define CYDEV_EMIF_SIZE 0x00000007u +#define CYREG_EMIF_NO_UDB 0x40005400u +#define CYREG_EMIF_RP_WAIT_STATES 0x40005401u +#define CYREG_EMIF_MEM_DWN 0x40005402u +#define CYREG_EMIF_MEMCLK_DIV 0x40005403u +#define CYREG_EMIF_CLOCK_EN 0x40005404u +#define CYREG_EMIF_EM_TYPE 0x40005405u +#define CYREG_EMIF_WP_WAIT_STATES 0x40005406u +#define CYDEV_ANAIF_BASE 0x40005800u +#define CYDEV_ANAIF_SIZE 0x000003a9u +#define CYDEV_ANAIF_CFG_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u +#define CYREG_SC0_CR0 0x40005800u +#define CYREG_SC0_CR1 0x40005801u +#define CYREG_SC0_CR2 0x40005802u +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u +#define CYREG_SC1_CR0 0x40005804u +#define CYREG_SC1_CR1 0x40005805u +#define CYREG_SC1_CR2 0x40005806u +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u +#define CYREG_SC2_CR0 0x40005808u +#define CYREG_SC2_CR1 0x40005809u +#define CYREG_SC2_CR2 0x4000580au +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u +#define CYREG_SC3_CR0 0x4000580cu +#define CYREG_SC3_CR1 0x4000580du +#define CYREG_SC3_CR2 0x4000580eu +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u +#define CYREG_DAC0_CR0 0x40005820u +#define CYREG_DAC0_CR1 0x40005821u +#define CYREG_DAC0_TST 0x40005822u +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u +#define CYREG_DAC1_CR0 0x40005824u +#define CYREG_DAC1_CR1 0x40005825u +#define CYREG_DAC1_TST 0x40005826u +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u +#define CYREG_DAC2_CR0 0x40005828u +#define CYREG_DAC2_CR1 0x40005829u +#define CYREG_DAC2_TST 0x4000582au +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u +#define CYREG_DAC3_CR0 0x4000582cu +#define CYREG_DAC3_CR1 0x4000582du +#define CYREG_DAC3_TST 0x4000582eu +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u +#define CYREG_CMP0_CR 0x40005840u +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u +#define CYREG_CMP1_CR 0x40005841u +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u +#define CYREG_CMP2_CR 0x40005842u +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u +#define CYREG_CMP3_CR 0x40005843u +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u +#define CYREG_LUT0_CR 0x40005848u +#define CYREG_LUT0_MX 0x40005849u +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u +#define CYREG_LUT1_CR 0x4000584au +#define CYREG_LUT1_MX 0x4000584bu +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u +#define CYREG_LUT2_CR 0x4000584cu +#define CYREG_LUT2_MX 0x4000584du +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u +#define CYREG_LUT3_CR 0x4000584eu +#define CYREG_LUT3_MX 0x4000584fu +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_CR 0x40005858u +#define CYREG_OPAMP0_RSVD 0x40005859u +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_CR 0x4000585au +#define CYREG_OPAMP1_RSVD 0x4000585bu +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_CR 0x4000585cu +#define CYREG_OPAMP2_RSVD 0x4000585du +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_CR 0x4000585eu +#define CYREG_OPAMP3_RSVD 0x4000585fu +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u +#define CYREG_LCDDAC_CR0 0x40005868u +#define CYREG_LCDDAC_CR1 0x40005869u +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u +#define CYREG_LCDDRV_CR 0x4000586au +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u +#define CYREG_LCDTMR_CFG 0x4000586bu +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u +#define CYREG_BG_CR0 0x4000586cu +#define CYREG_BG_RSVD 0x4000586du +#define CYREG_BG_DFT0 0x4000586eu +#define CYREG_BG_DFT1 0x4000586fu +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u +#define CYREG_CAPSL_CFG0 0x40005870u +#define CYREG_CAPSL_CFG1 0x40005871u +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u +#define CYREG_CAPSR_CFG0 0x40005872u +#define CYREG_CAPSR_CFG1 0x40005873u +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u +#define CYREG_PUMP_CR0 0x40005876u +#define CYREG_PUMP_CR1 0x40005877u +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u +#define CYREG_LPF0_CR0 0x40005878u +#define CYREG_LPF0_RSVD 0x40005879u +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u +#define CYREG_LPF1_CR0 0x4000587au +#define CYREG_LPF1_RSVD 0x4000587bu +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u +#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587cu +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u +#define CYREG_DSM0_CR0 0x40005880u +#define CYREG_DSM0_CR1 0x40005881u +#define CYREG_DSM0_CR2 0x40005882u +#define CYREG_DSM0_CR3 0x40005883u +#define CYREG_DSM0_CR4 0x40005884u +#define CYREG_DSM0_CR5 0x40005885u +#define CYREG_DSM0_CR6 0x40005886u +#define CYREG_DSM0_CR7 0x40005887u +#define CYREG_DSM0_CR8 0x40005888u +#define CYREG_DSM0_CR9 0x40005889u +#define CYREG_DSM0_CR10 0x4000588au +#define CYREG_DSM0_CR11 0x4000588bu +#define CYREG_DSM0_CR12 0x4000588cu +#define CYREG_DSM0_CR13 0x4000588du +#define CYREG_DSM0_CR14 0x4000588eu +#define CYREG_DSM0_CR15 0x4000588fu +#define CYREG_DSM0_CR16 0x40005890u +#define CYREG_DSM0_CR17 0x40005891u +#define CYREG_DSM0_REF0 0x40005892u +#define CYREG_DSM0_REF1 0x40005893u +#define CYREG_DSM0_REF2 0x40005894u +#define CYREG_DSM0_REF3 0x40005895u +#define CYREG_DSM0_DEM0 0x40005896u +#define CYREG_DSM0_DEM1 0x40005897u +#define CYREG_DSM0_TST0 0x40005898u +#define CYREG_DSM0_TST1 0x40005899u +#define CYREG_DSM0_BUF0 0x4000589au +#define CYREG_DSM0_BUF1 0x4000589bu +#define CYREG_DSM0_BUF2 0x4000589cu +#define CYREG_DSM0_BUF3 0x4000589du +#define CYREG_DSM0_MISC 0x4000589eu +#define CYREG_DSM0_RSVD1 0x4000589fu +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u +#define CYREG_SAR0_CSR0 0x40005900u +#define CYREG_SAR0_CSR1 0x40005901u +#define CYREG_SAR0_CSR2 0x40005902u +#define CYREG_SAR0_CSR3 0x40005903u +#define CYREG_SAR0_CSR4 0x40005904u +#define CYREG_SAR0_CSR5 0x40005905u +#define CYREG_SAR0_CSR6 0x40005906u +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u +#define CYREG_SAR1_CSR0 0x40005908u +#define CYREG_SAR1_CSR1 0x40005909u +#define CYREG_SAR1_CSR2 0x4000590au +#define CYREG_SAR1_CSR3 0x4000590bu +#define CYREG_SAR1_CSR4 0x4000590cu +#define CYREG_SAR1_CSR5 0x4000590du +#define CYREG_SAR1_CSR6 0x4000590eu +#define CYDEV_ANAIF_RT_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SIZE 0x00000162u +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du +#define CYREG_SC0_SW0 0x40005a00u +#define CYREG_SC0_SW2 0x40005a02u +#define CYREG_SC0_SW3 0x40005a03u +#define CYREG_SC0_SW4 0x40005a04u +#define CYREG_SC0_SW6 0x40005a06u +#define CYREG_SC0_SW7 0x40005a07u +#define CYREG_SC0_SW8 0x40005a08u +#define CYREG_SC0_SW10 0x40005a0au +#define CYREG_SC0_CLK 0x40005a0bu +#define CYREG_SC0_BST 0x40005a0cu +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du +#define CYREG_SC1_SW0 0x40005a10u +#define CYREG_SC1_SW2 0x40005a12u +#define CYREG_SC1_SW3 0x40005a13u +#define CYREG_SC1_SW4 0x40005a14u +#define CYREG_SC1_SW6 0x40005a16u +#define CYREG_SC1_SW7 0x40005a17u +#define CYREG_SC1_SW8 0x40005a18u +#define CYREG_SC1_SW10 0x40005a1au +#define CYREG_SC1_CLK 0x40005a1bu +#define CYREG_SC1_BST 0x40005a1cu +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du +#define CYREG_SC2_SW0 0x40005a20u +#define CYREG_SC2_SW2 0x40005a22u +#define CYREG_SC2_SW3 0x40005a23u +#define CYREG_SC2_SW4 0x40005a24u +#define CYREG_SC2_SW6 0x40005a26u +#define CYREG_SC2_SW7 0x40005a27u +#define CYREG_SC2_SW8 0x40005a28u +#define CYREG_SC2_SW10 0x40005a2au +#define CYREG_SC2_CLK 0x40005a2bu +#define CYREG_SC2_BST 0x40005a2cu +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du +#define CYREG_SC3_SW0 0x40005a30u +#define CYREG_SC3_SW2 0x40005a32u +#define CYREG_SC3_SW3 0x40005a33u +#define CYREG_SC3_SW4 0x40005a34u +#define CYREG_SC3_SW6 0x40005a36u +#define CYREG_SC3_SW7 0x40005a37u +#define CYREG_SC3_SW8 0x40005a38u +#define CYREG_SC3_SW10 0x40005a3au +#define CYREG_SC3_CLK 0x40005a3bu +#define CYREG_SC3_BST 0x40005a3cu +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u +#define CYREG_DAC0_SW0 0x40005a80u +#define CYREG_DAC0_SW2 0x40005a82u +#define CYREG_DAC0_SW3 0x40005a83u +#define CYREG_DAC0_SW4 0x40005a84u +#define CYREG_DAC0_STROBE 0x40005a87u +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u +#define CYREG_DAC1_SW0 0x40005a88u +#define CYREG_DAC1_SW2 0x40005a8au +#define CYREG_DAC1_SW3 0x40005a8bu +#define CYREG_DAC1_SW4 0x40005a8cu +#define CYREG_DAC1_STROBE 0x40005a8fu +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u +#define CYREG_DAC2_SW0 0x40005a90u +#define CYREG_DAC2_SW2 0x40005a92u +#define CYREG_DAC2_SW3 0x40005a93u +#define CYREG_DAC2_SW4 0x40005a94u +#define CYREG_DAC2_STROBE 0x40005a97u +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u +#define CYREG_DAC3_SW0 0x40005a98u +#define CYREG_DAC3_SW2 0x40005a9au +#define CYREG_DAC3_SW3 0x40005a9bu +#define CYREG_DAC3_SW4 0x40005a9cu +#define CYREG_DAC3_STROBE 0x40005a9fu +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u +#define CYREG_CMP0_SW0 0x40005ac0u +#define CYREG_CMP0_SW2 0x40005ac2u +#define CYREG_CMP0_SW3 0x40005ac3u +#define CYREG_CMP0_SW4 0x40005ac4u +#define CYREG_CMP0_SW6 0x40005ac6u +#define CYREG_CMP0_CLK 0x40005ac7u +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u +#define CYREG_CMP1_SW0 0x40005ac8u +#define CYREG_CMP1_SW2 0x40005acau +#define CYREG_CMP1_SW3 0x40005acbu +#define CYREG_CMP1_SW4 0x40005accu +#define CYREG_CMP1_SW6 0x40005aceu +#define CYREG_CMP1_CLK 0x40005acfu +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u +#define CYREG_CMP2_SW0 0x40005ad0u +#define CYREG_CMP2_SW2 0x40005ad2u +#define CYREG_CMP2_SW3 0x40005ad3u +#define CYREG_CMP2_SW4 0x40005ad4u +#define CYREG_CMP2_SW6 0x40005ad6u +#define CYREG_CMP2_CLK 0x40005ad7u +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u +#define CYREG_CMP3_SW0 0x40005ad8u +#define CYREG_CMP3_SW2 0x40005adau +#define CYREG_CMP3_SW3 0x40005adbu +#define CYREG_CMP3_SW4 0x40005adcu +#define CYREG_CMP3_SW6 0x40005adeu +#define CYREG_CMP3_CLK 0x40005adfu +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u +#define CYREG_DSM0_SW0 0x40005b00u +#define CYREG_DSM0_SW2 0x40005b02u +#define CYREG_DSM0_SW3 0x40005b03u +#define CYREG_DSM0_SW4 0x40005b04u +#define CYREG_DSM0_SW6 0x40005b06u +#define CYREG_DSM0_CLK 0x40005b07u +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u +#define CYREG_SAR0_SW0 0x40005b20u +#define CYREG_SAR0_SW2 0x40005b22u +#define CYREG_SAR0_SW3 0x40005b23u +#define CYREG_SAR0_SW4 0x40005b24u +#define CYREG_SAR0_SW6 0x40005b26u +#define CYREG_SAR0_CLK 0x40005b27u +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u +#define CYREG_SAR1_SW0 0x40005b28u +#define CYREG_SAR1_SW2 0x40005b2au +#define CYREG_SAR1_SW3 0x40005b2bu +#define CYREG_SAR1_SW4 0x40005b2cu +#define CYREG_SAR1_SW6 0x40005b2eu +#define CYREG_SAR1_CLK 0x40005b2fu +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_MX 0x40005b40u +#define CYREG_OPAMP0_SW 0x40005b41u +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_MX 0x40005b42u +#define CYREG_OPAMP1_SW 0x40005b43u +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_MX 0x40005b44u +#define CYREG_OPAMP2_SW 0x40005b45u +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_MX 0x40005b46u +#define CYREG_OPAMP3_SW 0x40005b47u +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u +#define CYREG_LCDDAC_SW0 0x40005b50u +#define CYREG_LCDDAC_SW1 0x40005b51u +#define CYREG_LCDDAC_SW2 0x40005b52u +#define CYREG_LCDDAC_SW3 0x40005b53u +#define CYREG_LCDDAC_SW4 0x40005b54u +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u +#define CYREG_SC_MISC 0x40005b56u +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u +#define CYREG_BUS_SW0 0x40005b58u +#define CYREG_BUS_SW2 0x40005b5au +#define CYREG_BUS_SW3 0x40005b5bu +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u +#define CYREG_DFT_CR0 0x40005b5cu +#define CYREG_DFT_CR1 0x40005b5du +#define CYREG_DFT_CR2 0x40005b5eu +#define CYREG_DFT_CR3 0x40005b5fu +#define CYREG_DFT_CR4 0x40005b60u +#define CYREG_DFT_CR5 0x40005b61u +#define CYDEV_ANAIF_WRK_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_SIZE 0x00000029u +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u +#define CYREG_DAC0_D 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u +#define CYREG_DAC1_D 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u +#define CYREG_DAC2_D 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u +#define CYREG_DAC3_D 0x40005b83u +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u +#define CYREG_DSM0_OUT0 0x40005b88u +#define CYREG_DSM0_OUT1 0x40005b89u +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u +#define CYREG_LUT_SR 0x40005b90u +#define CYREG_LUT_WRK1 0x40005b91u +#define CYREG_LUT_MSK 0x40005b92u +#define CYREG_LUT_CLK 0x40005b93u +#define CYREG_LUT_CPTR 0x40005b94u +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u +#define CYREG_CMP_WRK 0x40005b96u +#define CYREG_CMP_TST 0x40005b97u +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u +#define CYREG_SC_SR 0x40005b98u +#define CYREG_SC_WRK1 0x40005b99u +#define CYREG_SC_MSK 0x40005b9au +#define CYREG_SC_CMPINV 0x40005b9bu +#define CYREG_SC_CPTR 0x40005b9cu +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u +#define CYREG_SAR0_WRK0 0x40005ba0u +#define CYREG_SAR0_WRK1 0x40005ba1u +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u +#define CYREG_SAR1_WRK0 0x40005ba2u +#define CYREG_SAR1_WRK1 0x40005ba3u +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u +#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8u +#define CYDEV_USB_BASE 0x40006000u +#define CYDEV_USB_SIZE 0x00000300u +#define CYREG_USB_EP0_DR0 0x40006000u +#define CYREG_USB_EP0_DR1 0x40006001u +#define CYREG_USB_EP0_DR2 0x40006002u +#define CYREG_USB_EP0_DR3 0x40006003u +#define CYREG_USB_EP0_DR4 0x40006004u +#define CYREG_USB_EP0_DR5 0x40006005u +#define CYREG_USB_EP0_DR6 0x40006006u +#define CYREG_USB_EP0_DR7 0x40006007u +#define CYREG_USB_CR0 0x40006008u +#define CYREG_USB_CR1 0x40006009u +#define CYREG_USB_SIE_EP_INT_EN 0x4000600au +#define CYREG_USB_SIE_EP_INT_SR 0x4000600bu +#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u +#define CYREG_USB_SIE_EP1_CNT0 0x4000600cu +#define CYREG_USB_SIE_EP1_CNT1 0x4000600du +#define CYREG_USB_SIE_EP1_CR0 0x4000600eu +#define CYREG_USB_USBIO_CR0 0x40006010u +#define CYREG_USB_USBIO_CR1 0x40006012u +#define CYREG_USB_DYN_RECONFIG 0x40006014u +#define CYREG_USB_SOF0 0x40006018u +#define CYREG_USB_SOF1 0x40006019u +#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u +#define CYREG_USB_SIE_EP2_CNT0 0x4000601cu +#define CYREG_USB_SIE_EP2_CNT1 0x4000601du +#define CYREG_USB_SIE_EP2_CR0 0x4000601eu +#define CYREG_USB_EP0_CR 0x40006028u +#define CYREG_USB_EP0_CNT 0x40006029u +#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u +#define CYREG_USB_SIE_EP3_CNT0 0x4000602cu +#define CYREG_USB_SIE_EP3_CNT1 0x4000602du +#define CYREG_USB_SIE_EP3_CR0 0x4000602eu +#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u +#define CYREG_USB_SIE_EP4_CNT0 0x4000603cu +#define CYREG_USB_SIE_EP4_CNT1 0x4000603du +#define CYREG_USB_SIE_EP4_CR0 0x4000603eu +#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u +#define CYREG_USB_SIE_EP5_CNT0 0x4000604cu +#define CYREG_USB_SIE_EP5_CNT1 0x4000604du +#define CYREG_USB_SIE_EP5_CR0 0x4000604eu +#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u +#define CYREG_USB_SIE_EP6_CNT0 0x4000605cu +#define CYREG_USB_SIE_EP6_CNT1 0x4000605du +#define CYREG_USB_SIE_EP6_CR0 0x4000605eu +#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u +#define CYREG_USB_SIE_EP7_CNT0 0x4000606cu +#define CYREG_USB_SIE_EP7_CNT1 0x4000606du +#define CYREG_USB_SIE_EP7_CR0 0x4000606eu +#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u +#define CYREG_USB_SIE_EP8_CNT0 0x4000607cu +#define CYREG_USB_SIE_EP8_CNT1 0x4000607du +#define CYREG_USB_SIE_EP8_CR0 0x4000607eu +#define CYDEV_USB_ARB_EP1_BASE 0x40006080u +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u +#define CYREG_USB_ARB_EP1_CFG 0x40006080u +#define CYREG_USB_ARB_EP1_INT_EN 0x40006081u +#define CYREG_USB_ARB_EP1_SR 0x40006082u +#define CYDEV_USB_ARB_RW1_BASE 0x40006084u +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u +#define CYREG_USB_ARB_RW1_WA 0x40006084u +#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085u +#define CYREG_USB_ARB_RW1_RA 0x40006086u +#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087u +#define CYREG_USB_ARB_RW1_DR 0x40006088u +#define CYREG_USB_BUF_SIZE 0x4000608cu +#define CYREG_USB_EP_ACTIVE 0x4000608eu +#define CYREG_USB_EP_TYPE 0x4000608fu +#define CYDEV_USB_ARB_EP2_BASE 0x40006090u +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u +#define CYREG_USB_ARB_EP2_CFG 0x40006090u +#define CYREG_USB_ARB_EP2_INT_EN 0x40006091u +#define CYREG_USB_ARB_EP2_SR 0x40006092u +#define CYDEV_USB_ARB_RW2_BASE 0x40006094u +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u +#define CYREG_USB_ARB_RW2_WA 0x40006094u +#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095u +#define CYREG_USB_ARB_RW2_RA 0x40006096u +#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097u +#define CYREG_USB_ARB_RW2_DR 0x40006098u +#define CYREG_USB_ARB_CFG 0x4000609cu +#define CYREG_USB_USB_CLK_EN 0x4000609du +#define CYREG_USB_ARB_INT_EN 0x4000609eu +#define CYREG_USB_ARB_INT_SR 0x4000609fu +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u +#define CYREG_USB_ARB_EP3_CFG 0x400060a0u +#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1u +#define CYREG_USB_ARB_EP3_SR 0x400060a2u +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u +#define CYREG_USB_ARB_RW3_WA 0x400060a4u +#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5u +#define CYREG_USB_ARB_RW3_RA 0x400060a6u +#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7u +#define CYREG_USB_ARB_RW3_DR 0x400060a8u +#define CYREG_USB_CWA 0x400060acu +#define CYREG_USB_CWA_MSB 0x400060adu +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u +#define CYREG_USB_ARB_EP4_CFG 0x400060b0u +#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1u +#define CYREG_USB_ARB_EP4_SR 0x400060b2u +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u +#define CYREG_USB_ARB_RW4_WA 0x400060b4u +#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5u +#define CYREG_USB_ARB_RW4_RA 0x400060b6u +#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7u +#define CYREG_USB_ARB_RW4_DR 0x400060b8u +#define CYREG_USB_DMA_THRES 0x400060bcu +#define CYREG_USB_DMA_THRES_MSB 0x400060bdu +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u +#define CYREG_USB_ARB_EP5_CFG 0x400060c0u +#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1u +#define CYREG_USB_ARB_EP5_SR 0x400060c2u +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u +#define CYREG_USB_ARB_RW5_WA 0x400060c4u +#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5u +#define CYREG_USB_ARB_RW5_RA 0x400060c6u +#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7u +#define CYREG_USB_ARB_RW5_DR 0x400060c8u +#define CYREG_USB_BUS_RST_CNT 0x400060ccu +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u +#define CYREG_USB_ARB_EP6_CFG 0x400060d0u +#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1u +#define CYREG_USB_ARB_EP6_SR 0x400060d2u +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u +#define CYREG_USB_ARB_RW6_WA 0x400060d4u +#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5u +#define CYREG_USB_ARB_RW6_RA 0x400060d6u +#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7u +#define CYREG_USB_ARB_RW6_DR 0x400060d8u +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u +#define CYREG_USB_ARB_EP7_CFG 0x400060e0u +#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1u +#define CYREG_USB_ARB_EP7_SR 0x400060e2u +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u +#define CYREG_USB_ARB_RW7_WA 0x400060e4u +#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5u +#define CYREG_USB_ARB_RW7_RA 0x400060e6u +#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7u +#define CYREG_USB_ARB_RW7_DR 0x400060e8u +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u +#define CYREG_USB_ARB_EP8_CFG 0x400060f0u +#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1u +#define CYREG_USB_ARB_EP8_SR 0x400060f2u +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u +#define CYREG_USB_ARB_RW8_WA 0x400060f4u +#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5u +#define CYREG_USB_ARB_RW8_RA 0x400060f6u +#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7u +#define CYREG_USB_ARB_RW8_DR 0x400060f8u +#define CYDEV_USB_MEM_BASE 0x40006100u +#define CYDEV_USB_MEM_SIZE 0x00000200u +#define CYREG_USB_MEM_DATA_MBASE 0x40006100u +#define CYREG_USB_MEM_DATA_MSIZE 0x00000200u +#define CYDEV_UWRK_BASE 0x40006400u +#define CYDEV_UWRK_SIZE 0x00000b60u +#define CYDEV_UWRK_UWRK8_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u +#define CYREG_B0_UDB00_A0 0x40006400u +#define CYREG_B0_UDB01_A0 0x40006401u +#define CYREG_B0_UDB02_A0 0x40006402u +#define CYREG_B0_UDB03_A0 0x40006403u +#define CYREG_B0_UDB04_A0 0x40006404u +#define CYREG_B0_UDB05_A0 0x40006405u +#define CYREG_B0_UDB06_A0 0x40006406u +#define CYREG_B0_UDB07_A0 0x40006407u +#define CYREG_B0_UDB08_A0 0x40006408u +#define CYREG_B0_UDB09_A0 0x40006409u +#define CYREG_B0_UDB10_A0 0x4000640au +#define CYREG_B0_UDB11_A0 0x4000640bu +#define CYREG_B0_UDB12_A0 0x4000640cu +#define CYREG_B0_UDB13_A0 0x4000640du +#define CYREG_B0_UDB14_A0 0x4000640eu +#define CYREG_B0_UDB15_A0 0x4000640fu +#define CYREG_B0_UDB00_A1 0x40006410u +#define CYREG_B0_UDB01_A1 0x40006411u +#define CYREG_B0_UDB02_A1 0x40006412u +#define CYREG_B0_UDB03_A1 0x40006413u +#define CYREG_B0_UDB04_A1 0x40006414u +#define CYREG_B0_UDB05_A1 0x40006415u +#define CYREG_B0_UDB06_A1 0x40006416u +#define CYREG_B0_UDB07_A1 0x40006417u +#define CYREG_B0_UDB08_A1 0x40006418u +#define CYREG_B0_UDB09_A1 0x40006419u +#define CYREG_B0_UDB10_A1 0x4000641au +#define CYREG_B0_UDB11_A1 0x4000641bu +#define CYREG_B0_UDB12_A1 0x4000641cu +#define CYREG_B0_UDB13_A1 0x4000641du +#define CYREG_B0_UDB14_A1 0x4000641eu +#define CYREG_B0_UDB15_A1 0x4000641fu +#define CYREG_B0_UDB00_D0 0x40006420u +#define CYREG_B0_UDB01_D0 0x40006421u +#define CYREG_B0_UDB02_D0 0x40006422u +#define CYREG_B0_UDB03_D0 0x40006423u +#define CYREG_B0_UDB04_D0 0x40006424u +#define CYREG_B0_UDB05_D0 0x40006425u +#define CYREG_B0_UDB06_D0 0x40006426u +#define CYREG_B0_UDB07_D0 0x40006427u +#define CYREG_B0_UDB08_D0 0x40006428u +#define CYREG_B0_UDB09_D0 0x40006429u +#define CYREG_B0_UDB10_D0 0x4000642au +#define CYREG_B0_UDB11_D0 0x4000642bu +#define CYREG_B0_UDB12_D0 0x4000642cu +#define CYREG_B0_UDB13_D0 0x4000642du +#define CYREG_B0_UDB14_D0 0x4000642eu +#define CYREG_B0_UDB15_D0 0x4000642fu +#define CYREG_B0_UDB00_D1 0x40006430u +#define CYREG_B0_UDB01_D1 0x40006431u +#define CYREG_B0_UDB02_D1 0x40006432u +#define CYREG_B0_UDB03_D1 0x40006433u +#define CYREG_B0_UDB04_D1 0x40006434u +#define CYREG_B0_UDB05_D1 0x40006435u +#define CYREG_B0_UDB06_D1 0x40006436u +#define CYREG_B0_UDB07_D1 0x40006437u +#define CYREG_B0_UDB08_D1 0x40006438u +#define CYREG_B0_UDB09_D1 0x40006439u +#define CYREG_B0_UDB10_D1 0x4000643au +#define CYREG_B0_UDB11_D1 0x4000643bu +#define CYREG_B0_UDB12_D1 0x4000643cu +#define CYREG_B0_UDB13_D1 0x4000643du +#define CYREG_B0_UDB14_D1 0x4000643eu +#define CYREG_B0_UDB15_D1 0x4000643fu +#define CYREG_B0_UDB00_F0 0x40006440u +#define CYREG_B0_UDB01_F0 0x40006441u +#define CYREG_B0_UDB02_F0 0x40006442u +#define CYREG_B0_UDB03_F0 0x40006443u +#define CYREG_B0_UDB04_F0 0x40006444u +#define CYREG_B0_UDB05_F0 0x40006445u +#define CYREG_B0_UDB06_F0 0x40006446u +#define CYREG_B0_UDB07_F0 0x40006447u +#define CYREG_B0_UDB08_F0 0x40006448u +#define CYREG_B0_UDB09_F0 0x40006449u +#define CYREG_B0_UDB10_F0 0x4000644au +#define CYREG_B0_UDB11_F0 0x4000644bu +#define CYREG_B0_UDB12_F0 0x4000644cu +#define CYREG_B0_UDB13_F0 0x4000644du +#define CYREG_B0_UDB14_F0 0x4000644eu +#define CYREG_B0_UDB15_F0 0x4000644fu +#define CYREG_B0_UDB00_F1 0x40006450u +#define CYREG_B0_UDB01_F1 0x40006451u +#define CYREG_B0_UDB02_F1 0x40006452u +#define CYREG_B0_UDB03_F1 0x40006453u +#define CYREG_B0_UDB04_F1 0x40006454u +#define CYREG_B0_UDB05_F1 0x40006455u +#define CYREG_B0_UDB06_F1 0x40006456u +#define CYREG_B0_UDB07_F1 0x40006457u +#define CYREG_B0_UDB08_F1 0x40006458u +#define CYREG_B0_UDB09_F1 0x40006459u +#define CYREG_B0_UDB10_F1 0x4000645au +#define CYREG_B0_UDB11_F1 0x4000645bu +#define CYREG_B0_UDB12_F1 0x4000645cu +#define CYREG_B0_UDB13_F1 0x4000645du +#define CYREG_B0_UDB14_F1 0x4000645eu +#define CYREG_B0_UDB15_F1 0x4000645fu +#define CYREG_B0_UDB00_ST 0x40006460u +#define CYREG_B0_UDB01_ST 0x40006461u +#define CYREG_B0_UDB02_ST 0x40006462u +#define CYREG_B0_UDB03_ST 0x40006463u +#define CYREG_B0_UDB04_ST 0x40006464u +#define CYREG_B0_UDB05_ST 0x40006465u +#define CYREG_B0_UDB06_ST 0x40006466u +#define CYREG_B0_UDB07_ST 0x40006467u +#define CYREG_B0_UDB08_ST 0x40006468u +#define CYREG_B0_UDB09_ST 0x40006469u +#define CYREG_B0_UDB10_ST 0x4000646au +#define CYREG_B0_UDB11_ST 0x4000646bu +#define CYREG_B0_UDB12_ST 0x4000646cu +#define CYREG_B0_UDB13_ST 0x4000646du +#define CYREG_B0_UDB14_ST 0x4000646eu +#define CYREG_B0_UDB15_ST 0x4000646fu +#define CYREG_B0_UDB00_CTL 0x40006470u +#define CYREG_B0_UDB01_CTL 0x40006471u +#define CYREG_B0_UDB02_CTL 0x40006472u +#define CYREG_B0_UDB03_CTL 0x40006473u +#define CYREG_B0_UDB04_CTL 0x40006474u +#define CYREG_B0_UDB05_CTL 0x40006475u +#define CYREG_B0_UDB06_CTL 0x40006476u +#define CYREG_B0_UDB07_CTL 0x40006477u +#define CYREG_B0_UDB08_CTL 0x40006478u +#define CYREG_B0_UDB09_CTL 0x40006479u +#define CYREG_B0_UDB10_CTL 0x4000647au +#define CYREG_B0_UDB11_CTL 0x4000647bu +#define CYREG_B0_UDB12_CTL 0x4000647cu +#define CYREG_B0_UDB13_CTL 0x4000647du +#define CYREG_B0_UDB14_CTL 0x4000647eu +#define CYREG_B0_UDB15_CTL 0x4000647fu +#define CYREG_B0_UDB00_MSK 0x40006480u +#define CYREG_B0_UDB01_MSK 0x40006481u +#define CYREG_B0_UDB02_MSK 0x40006482u +#define CYREG_B0_UDB03_MSK 0x40006483u +#define CYREG_B0_UDB04_MSK 0x40006484u +#define CYREG_B0_UDB05_MSK 0x40006485u +#define CYREG_B0_UDB06_MSK 0x40006486u +#define CYREG_B0_UDB07_MSK 0x40006487u +#define CYREG_B0_UDB08_MSK 0x40006488u +#define CYREG_B0_UDB09_MSK 0x40006489u +#define CYREG_B0_UDB10_MSK 0x4000648au +#define CYREG_B0_UDB11_MSK 0x4000648bu +#define CYREG_B0_UDB12_MSK 0x4000648cu +#define CYREG_B0_UDB13_MSK 0x4000648du +#define CYREG_B0_UDB14_MSK 0x4000648eu +#define CYREG_B0_UDB15_MSK 0x4000648fu +#define CYREG_B0_UDB00_ACTL 0x40006490u +#define CYREG_B0_UDB01_ACTL 0x40006491u +#define CYREG_B0_UDB02_ACTL 0x40006492u +#define CYREG_B0_UDB03_ACTL 0x40006493u +#define CYREG_B0_UDB04_ACTL 0x40006494u +#define CYREG_B0_UDB05_ACTL 0x40006495u +#define CYREG_B0_UDB06_ACTL 0x40006496u +#define CYREG_B0_UDB07_ACTL 0x40006497u +#define CYREG_B0_UDB08_ACTL 0x40006498u +#define CYREG_B0_UDB09_ACTL 0x40006499u +#define CYREG_B0_UDB10_ACTL 0x4000649au +#define CYREG_B0_UDB11_ACTL 0x4000649bu +#define CYREG_B0_UDB12_ACTL 0x4000649cu +#define CYREG_B0_UDB13_ACTL 0x4000649du +#define CYREG_B0_UDB14_ACTL 0x4000649eu +#define CYREG_B0_UDB15_ACTL 0x4000649fu +#define CYREG_B0_UDB00_MC 0x400064a0u +#define CYREG_B0_UDB01_MC 0x400064a1u +#define CYREG_B0_UDB02_MC 0x400064a2u +#define CYREG_B0_UDB03_MC 0x400064a3u +#define CYREG_B0_UDB04_MC 0x400064a4u +#define CYREG_B0_UDB05_MC 0x400064a5u +#define CYREG_B0_UDB06_MC 0x400064a6u +#define CYREG_B0_UDB07_MC 0x400064a7u +#define CYREG_B0_UDB08_MC 0x400064a8u +#define CYREG_B0_UDB09_MC 0x400064a9u +#define CYREG_B0_UDB10_MC 0x400064aau +#define CYREG_B0_UDB11_MC 0x400064abu +#define CYREG_B0_UDB12_MC 0x400064acu +#define CYREG_B0_UDB13_MC 0x400064adu +#define CYREG_B0_UDB14_MC 0x400064aeu +#define CYREG_B0_UDB15_MC 0x400064afu +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u +#define CYREG_B1_UDB04_A0 0x40006504u +#define CYREG_B1_UDB05_A0 0x40006505u +#define CYREG_B1_UDB06_A0 0x40006506u +#define CYREG_B1_UDB07_A0 0x40006507u +#define CYREG_B1_UDB08_A0 0x40006508u +#define CYREG_B1_UDB09_A0 0x40006509u +#define CYREG_B1_UDB10_A0 0x4000650au +#define CYREG_B1_UDB11_A0 0x4000650bu +#define CYREG_B1_UDB04_A1 0x40006514u +#define CYREG_B1_UDB05_A1 0x40006515u +#define CYREG_B1_UDB06_A1 0x40006516u +#define CYREG_B1_UDB07_A1 0x40006517u +#define CYREG_B1_UDB08_A1 0x40006518u +#define CYREG_B1_UDB09_A1 0x40006519u +#define CYREG_B1_UDB10_A1 0x4000651au +#define CYREG_B1_UDB11_A1 0x4000651bu +#define CYREG_B1_UDB04_D0 0x40006524u +#define CYREG_B1_UDB05_D0 0x40006525u +#define CYREG_B1_UDB06_D0 0x40006526u +#define CYREG_B1_UDB07_D0 0x40006527u +#define CYREG_B1_UDB08_D0 0x40006528u +#define CYREG_B1_UDB09_D0 0x40006529u +#define CYREG_B1_UDB10_D0 0x4000652au +#define CYREG_B1_UDB11_D0 0x4000652bu +#define CYREG_B1_UDB04_D1 0x40006534u +#define CYREG_B1_UDB05_D1 0x40006535u +#define CYREG_B1_UDB06_D1 0x40006536u +#define CYREG_B1_UDB07_D1 0x40006537u +#define CYREG_B1_UDB08_D1 0x40006538u +#define CYREG_B1_UDB09_D1 0x40006539u +#define CYREG_B1_UDB10_D1 0x4000653au +#define CYREG_B1_UDB11_D1 0x4000653bu +#define CYREG_B1_UDB04_F0 0x40006544u +#define CYREG_B1_UDB05_F0 0x40006545u +#define CYREG_B1_UDB06_F0 0x40006546u +#define CYREG_B1_UDB07_F0 0x40006547u +#define CYREG_B1_UDB08_F0 0x40006548u +#define CYREG_B1_UDB09_F0 0x40006549u +#define CYREG_B1_UDB10_F0 0x4000654au +#define CYREG_B1_UDB11_F0 0x4000654bu +#define CYREG_B1_UDB04_F1 0x40006554u +#define CYREG_B1_UDB05_F1 0x40006555u +#define CYREG_B1_UDB06_F1 0x40006556u +#define CYREG_B1_UDB07_F1 0x40006557u +#define CYREG_B1_UDB08_F1 0x40006558u +#define CYREG_B1_UDB09_F1 0x40006559u +#define CYREG_B1_UDB10_F1 0x4000655au +#define CYREG_B1_UDB11_F1 0x4000655bu +#define CYREG_B1_UDB04_ST 0x40006564u +#define CYREG_B1_UDB05_ST 0x40006565u +#define CYREG_B1_UDB06_ST 0x40006566u +#define CYREG_B1_UDB07_ST 0x40006567u +#define CYREG_B1_UDB08_ST 0x40006568u +#define CYREG_B1_UDB09_ST 0x40006569u +#define CYREG_B1_UDB10_ST 0x4000656au +#define CYREG_B1_UDB11_ST 0x4000656bu +#define CYREG_B1_UDB04_CTL 0x40006574u +#define CYREG_B1_UDB05_CTL 0x40006575u +#define CYREG_B1_UDB06_CTL 0x40006576u +#define CYREG_B1_UDB07_CTL 0x40006577u +#define CYREG_B1_UDB08_CTL 0x40006578u +#define CYREG_B1_UDB09_CTL 0x40006579u +#define CYREG_B1_UDB10_CTL 0x4000657au +#define CYREG_B1_UDB11_CTL 0x4000657bu +#define CYREG_B1_UDB04_MSK 0x40006584u +#define CYREG_B1_UDB05_MSK 0x40006585u +#define CYREG_B1_UDB06_MSK 0x40006586u +#define CYREG_B1_UDB07_MSK 0x40006587u +#define CYREG_B1_UDB08_MSK 0x40006588u +#define CYREG_B1_UDB09_MSK 0x40006589u +#define CYREG_B1_UDB10_MSK 0x4000658au +#define CYREG_B1_UDB11_MSK 0x4000658bu +#define CYREG_B1_UDB04_ACTL 0x40006594u +#define CYREG_B1_UDB05_ACTL 0x40006595u +#define CYREG_B1_UDB06_ACTL 0x40006596u +#define CYREG_B1_UDB07_ACTL 0x40006597u +#define CYREG_B1_UDB08_ACTL 0x40006598u +#define CYREG_B1_UDB09_ACTL 0x40006599u +#define CYREG_B1_UDB10_ACTL 0x4000659au +#define CYREG_B1_UDB11_ACTL 0x4000659bu +#define CYREG_B1_UDB04_MC 0x400065a4u +#define CYREG_B1_UDB05_MC 0x400065a5u +#define CYREG_B1_UDB06_MC 0x400065a6u +#define CYREG_B1_UDB07_MC 0x400065a7u +#define CYREG_B1_UDB08_MC 0x400065a8u +#define CYREG_B1_UDB09_MC 0x400065a9u +#define CYREG_B1_UDB10_MC 0x400065aau +#define CYREG_B1_UDB11_MC 0x400065abu +#define CYDEV_UWRK_UWRK16_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u +#define CYREG_B0_UDB00_A0_A1 0x40006800u +#define CYREG_B0_UDB01_A0_A1 0x40006802u +#define CYREG_B0_UDB02_A0_A1 0x40006804u +#define CYREG_B0_UDB03_A0_A1 0x40006806u +#define CYREG_B0_UDB04_A0_A1 0x40006808u +#define CYREG_B0_UDB05_A0_A1 0x4000680au +#define CYREG_B0_UDB06_A0_A1 0x4000680cu +#define CYREG_B0_UDB07_A0_A1 0x4000680eu +#define CYREG_B0_UDB08_A0_A1 0x40006810u +#define CYREG_B0_UDB09_A0_A1 0x40006812u +#define CYREG_B0_UDB10_A0_A1 0x40006814u +#define CYREG_B0_UDB11_A0_A1 0x40006816u +#define CYREG_B0_UDB12_A0_A1 0x40006818u +#define CYREG_B0_UDB13_A0_A1 0x4000681au +#define CYREG_B0_UDB14_A0_A1 0x4000681cu +#define CYREG_B0_UDB15_A0_A1 0x4000681eu +#define CYREG_B0_UDB00_D0_D1 0x40006840u +#define CYREG_B0_UDB01_D0_D1 0x40006842u +#define CYREG_B0_UDB02_D0_D1 0x40006844u +#define CYREG_B0_UDB03_D0_D1 0x40006846u +#define CYREG_B0_UDB04_D0_D1 0x40006848u +#define CYREG_B0_UDB05_D0_D1 0x4000684au +#define CYREG_B0_UDB06_D0_D1 0x4000684cu +#define CYREG_B0_UDB07_D0_D1 0x4000684eu +#define CYREG_B0_UDB08_D0_D1 0x40006850u +#define CYREG_B0_UDB09_D0_D1 0x40006852u +#define CYREG_B0_UDB10_D0_D1 0x40006854u +#define CYREG_B0_UDB11_D0_D1 0x40006856u +#define CYREG_B0_UDB12_D0_D1 0x40006858u +#define CYREG_B0_UDB13_D0_D1 0x4000685au +#define CYREG_B0_UDB14_D0_D1 0x4000685cu +#define CYREG_B0_UDB15_D0_D1 0x4000685eu +#define CYREG_B0_UDB00_F0_F1 0x40006880u +#define CYREG_B0_UDB01_F0_F1 0x40006882u +#define CYREG_B0_UDB02_F0_F1 0x40006884u +#define CYREG_B0_UDB03_F0_F1 0x40006886u +#define CYREG_B0_UDB04_F0_F1 0x40006888u +#define CYREG_B0_UDB05_F0_F1 0x4000688au +#define CYREG_B0_UDB06_F0_F1 0x4000688cu +#define CYREG_B0_UDB07_F0_F1 0x4000688eu +#define CYREG_B0_UDB08_F0_F1 0x40006890u +#define CYREG_B0_UDB09_F0_F1 0x40006892u +#define CYREG_B0_UDB10_F0_F1 0x40006894u +#define CYREG_B0_UDB11_F0_F1 0x40006896u +#define CYREG_B0_UDB12_F0_F1 0x40006898u +#define CYREG_B0_UDB13_F0_F1 0x4000689au +#define CYREG_B0_UDB14_F0_F1 0x4000689cu +#define CYREG_B0_UDB15_F0_F1 0x4000689eu +#define CYREG_B0_UDB00_ST_CTL 0x400068c0u +#define CYREG_B0_UDB01_ST_CTL 0x400068c2u +#define CYREG_B0_UDB02_ST_CTL 0x400068c4u +#define CYREG_B0_UDB03_ST_CTL 0x400068c6u +#define CYREG_B0_UDB04_ST_CTL 0x400068c8u +#define CYREG_B0_UDB05_ST_CTL 0x400068cau +#define CYREG_B0_UDB06_ST_CTL 0x400068ccu +#define CYREG_B0_UDB07_ST_CTL 0x400068ceu +#define CYREG_B0_UDB08_ST_CTL 0x400068d0u +#define CYREG_B0_UDB09_ST_CTL 0x400068d2u +#define CYREG_B0_UDB10_ST_CTL 0x400068d4u +#define CYREG_B0_UDB11_ST_CTL 0x400068d6u +#define CYREG_B0_UDB12_ST_CTL 0x400068d8u +#define CYREG_B0_UDB13_ST_CTL 0x400068dau +#define CYREG_B0_UDB14_ST_CTL 0x400068dcu +#define CYREG_B0_UDB15_ST_CTL 0x400068deu +#define CYREG_B0_UDB00_MSK_ACTL 0x40006900u +#define CYREG_B0_UDB01_MSK_ACTL 0x40006902u +#define CYREG_B0_UDB02_MSK_ACTL 0x40006904u +#define CYREG_B0_UDB03_MSK_ACTL 0x40006906u +#define CYREG_B0_UDB04_MSK_ACTL 0x40006908u +#define CYREG_B0_UDB05_MSK_ACTL 0x4000690au +#define CYREG_B0_UDB06_MSK_ACTL 0x4000690cu +#define CYREG_B0_UDB07_MSK_ACTL 0x4000690eu +#define CYREG_B0_UDB08_MSK_ACTL 0x40006910u +#define CYREG_B0_UDB09_MSK_ACTL 0x40006912u +#define CYREG_B0_UDB10_MSK_ACTL 0x40006914u +#define CYREG_B0_UDB11_MSK_ACTL 0x40006916u +#define CYREG_B0_UDB12_MSK_ACTL 0x40006918u +#define CYREG_B0_UDB13_MSK_ACTL 0x4000691au +#define CYREG_B0_UDB14_MSK_ACTL 0x4000691cu +#define CYREG_B0_UDB15_MSK_ACTL 0x4000691eu +#define CYREG_B0_UDB00_MC_00 0x40006940u +#define CYREG_B0_UDB01_MC_00 0x40006942u +#define CYREG_B0_UDB02_MC_00 0x40006944u +#define CYREG_B0_UDB03_MC_00 0x40006946u +#define CYREG_B0_UDB04_MC_00 0x40006948u +#define CYREG_B0_UDB05_MC_00 0x4000694au +#define CYREG_B0_UDB06_MC_00 0x4000694cu +#define CYREG_B0_UDB07_MC_00 0x4000694eu +#define CYREG_B0_UDB08_MC_00 0x40006950u +#define CYREG_B0_UDB09_MC_00 0x40006952u +#define CYREG_B0_UDB10_MC_00 0x40006954u +#define CYREG_B0_UDB11_MC_00 0x40006956u +#define CYREG_B0_UDB12_MC_00 0x40006958u +#define CYREG_B0_UDB13_MC_00 0x4000695au +#define CYREG_B0_UDB14_MC_00 0x4000695cu +#define CYREG_B0_UDB15_MC_00 0x4000695eu +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u +#define CYREG_B1_UDB04_A0_A1 0x40006a08u +#define CYREG_B1_UDB05_A0_A1 0x40006a0au +#define CYREG_B1_UDB06_A0_A1 0x40006a0cu +#define CYREG_B1_UDB07_A0_A1 0x40006a0eu +#define CYREG_B1_UDB08_A0_A1 0x40006a10u +#define CYREG_B1_UDB09_A0_A1 0x40006a12u +#define CYREG_B1_UDB10_A0_A1 0x40006a14u +#define CYREG_B1_UDB11_A0_A1 0x40006a16u +#define CYREG_B1_UDB04_D0_D1 0x40006a48u +#define CYREG_B1_UDB05_D0_D1 0x40006a4au +#define CYREG_B1_UDB06_D0_D1 0x40006a4cu +#define CYREG_B1_UDB07_D0_D1 0x40006a4eu +#define CYREG_B1_UDB08_D0_D1 0x40006a50u +#define CYREG_B1_UDB09_D0_D1 0x40006a52u +#define CYREG_B1_UDB10_D0_D1 0x40006a54u +#define CYREG_B1_UDB11_D0_D1 0x40006a56u +#define CYREG_B1_UDB04_F0_F1 0x40006a88u +#define CYREG_B1_UDB05_F0_F1 0x40006a8au +#define CYREG_B1_UDB06_F0_F1 0x40006a8cu +#define CYREG_B1_UDB07_F0_F1 0x40006a8eu +#define CYREG_B1_UDB08_F0_F1 0x40006a90u +#define CYREG_B1_UDB09_F0_F1 0x40006a92u +#define CYREG_B1_UDB10_F0_F1 0x40006a94u +#define CYREG_B1_UDB11_F0_F1 0x40006a96u +#define CYREG_B1_UDB04_ST_CTL 0x40006ac8u +#define CYREG_B1_UDB05_ST_CTL 0x40006acau +#define CYREG_B1_UDB06_ST_CTL 0x40006accu +#define CYREG_B1_UDB07_ST_CTL 0x40006aceu +#define CYREG_B1_UDB08_ST_CTL 0x40006ad0u +#define CYREG_B1_UDB09_ST_CTL 0x40006ad2u +#define CYREG_B1_UDB10_ST_CTL 0x40006ad4u +#define CYREG_B1_UDB11_ST_CTL 0x40006ad6u +#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08u +#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0au +#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0cu +#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0eu +#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10u +#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12u +#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14u +#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16u +#define CYREG_B1_UDB04_MC_00 0x40006b48u +#define CYREG_B1_UDB05_MC_00 0x40006b4au +#define CYREG_B1_UDB06_MC_00 0x40006b4cu +#define CYREG_B1_UDB07_MC_00 0x40006b4eu +#define CYREG_B1_UDB08_MC_00 0x40006b50u +#define CYREG_B1_UDB09_MC_00 0x40006b52u +#define CYREG_B1_UDB10_MC_00 0x40006b54u +#define CYREG_B1_UDB11_MC_00 0x40006b56u +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu +#define CYREG_B0_UDB00_01_A0 0x40006800u +#define CYREG_B0_UDB01_02_A0 0x40006802u +#define CYREG_B0_UDB02_03_A0 0x40006804u +#define CYREG_B0_UDB03_04_A0 0x40006806u +#define CYREG_B0_UDB04_05_A0 0x40006808u +#define CYREG_B0_UDB05_06_A0 0x4000680au +#define CYREG_B0_UDB06_07_A0 0x4000680cu +#define CYREG_B0_UDB07_08_A0 0x4000680eu +#define CYREG_B0_UDB08_09_A0 0x40006810u +#define CYREG_B0_UDB09_10_A0 0x40006812u +#define CYREG_B0_UDB10_11_A0 0x40006814u +#define CYREG_B0_UDB11_12_A0 0x40006816u +#define CYREG_B0_UDB12_13_A0 0x40006818u +#define CYREG_B0_UDB13_14_A0 0x4000681au +#define CYREG_B0_UDB14_15_A0 0x4000681cu +#define CYREG_B0_UDB00_01_A1 0x40006820u +#define CYREG_B0_UDB01_02_A1 0x40006822u +#define CYREG_B0_UDB02_03_A1 0x40006824u +#define CYREG_B0_UDB03_04_A1 0x40006826u +#define CYREG_B0_UDB04_05_A1 0x40006828u +#define CYREG_B0_UDB05_06_A1 0x4000682au +#define CYREG_B0_UDB06_07_A1 0x4000682cu +#define CYREG_B0_UDB07_08_A1 0x4000682eu +#define CYREG_B0_UDB08_09_A1 0x40006830u +#define CYREG_B0_UDB09_10_A1 0x40006832u +#define CYREG_B0_UDB10_11_A1 0x40006834u +#define CYREG_B0_UDB11_12_A1 0x40006836u +#define CYREG_B0_UDB12_13_A1 0x40006838u +#define CYREG_B0_UDB13_14_A1 0x4000683au +#define CYREG_B0_UDB14_15_A1 0x4000683cu +#define CYREG_B0_UDB00_01_D0 0x40006840u +#define CYREG_B0_UDB01_02_D0 0x40006842u +#define CYREG_B0_UDB02_03_D0 0x40006844u +#define CYREG_B0_UDB03_04_D0 0x40006846u +#define CYREG_B0_UDB04_05_D0 0x40006848u +#define CYREG_B0_UDB05_06_D0 0x4000684au +#define CYREG_B0_UDB06_07_D0 0x4000684cu +#define CYREG_B0_UDB07_08_D0 0x4000684eu +#define CYREG_B0_UDB08_09_D0 0x40006850u +#define CYREG_B0_UDB09_10_D0 0x40006852u +#define CYREG_B0_UDB10_11_D0 0x40006854u +#define CYREG_B0_UDB11_12_D0 0x40006856u +#define CYREG_B0_UDB12_13_D0 0x40006858u +#define CYREG_B0_UDB13_14_D0 0x4000685au +#define CYREG_B0_UDB14_15_D0 0x4000685cu +#define CYREG_B0_UDB00_01_D1 0x40006860u +#define CYREG_B0_UDB01_02_D1 0x40006862u +#define CYREG_B0_UDB02_03_D1 0x40006864u +#define CYREG_B0_UDB03_04_D1 0x40006866u +#define CYREG_B0_UDB04_05_D1 0x40006868u +#define CYREG_B0_UDB05_06_D1 0x4000686au +#define CYREG_B0_UDB06_07_D1 0x4000686cu +#define CYREG_B0_UDB07_08_D1 0x4000686eu +#define CYREG_B0_UDB08_09_D1 0x40006870u +#define CYREG_B0_UDB09_10_D1 0x40006872u +#define CYREG_B0_UDB10_11_D1 0x40006874u +#define CYREG_B0_UDB11_12_D1 0x40006876u +#define CYREG_B0_UDB12_13_D1 0x40006878u +#define CYREG_B0_UDB13_14_D1 0x4000687au +#define CYREG_B0_UDB14_15_D1 0x4000687cu +#define CYREG_B0_UDB00_01_F0 0x40006880u +#define CYREG_B0_UDB01_02_F0 0x40006882u +#define CYREG_B0_UDB02_03_F0 0x40006884u +#define CYREG_B0_UDB03_04_F0 0x40006886u +#define CYREG_B0_UDB04_05_F0 0x40006888u +#define CYREG_B0_UDB05_06_F0 0x4000688au +#define CYREG_B0_UDB06_07_F0 0x4000688cu +#define CYREG_B0_UDB07_08_F0 0x4000688eu +#define CYREG_B0_UDB08_09_F0 0x40006890u +#define CYREG_B0_UDB09_10_F0 0x40006892u +#define CYREG_B0_UDB10_11_F0 0x40006894u +#define CYREG_B0_UDB11_12_F0 0x40006896u +#define CYREG_B0_UDB12_13_F0 0x40006898u +#define CYREG_B0_UDB13_14_F0 0x4000689au +#define CYREG_B0_UDB14_15_F0 0x4000689cu +#define CYREG_B0_UDB00_01_F1 0x400068a0u +#define CYREG_B0_UDB01_02_F1 0x400068a2u +#define CYREG_B0_UDB02_03_F1 0x400068a4u +#define CYREG_B0_UDB03_04_F1 0x400068a6u +#define CYREG_B0_UDB04_05_F1 0x400068a8u +#define CYREG_B0_UDB05_06_F1 0x400068aau +#define CYREG_B0_UDB06_07_F1 0x400068acu +#define CYREG_B0_UDB07_08_F1 0x400068aeu +#define CYREG_B0_UDB08_09_F1 0x400068b0u +#define CYREG_B0_UDB09_10_F1 0x400068b2u +#define CYREG_B0_UDB10_11_F1 0x400068b4u +#define CYREG_B0_UDB11_12_F1 0x400068b6u +#define CYREG_B0_UDB12_13_F1 0x400068b8u +#define CYREG_B0_UDB13_14_F1 0x400068bau +#define CYREG_B0_UDB14_15_F1 0x400068bcu +#define CYREG_B0_UDB00_01_ST 0x400068c0u +#define CYREG_B0_UDB01_02_ST 0x400068c2u +#define CYREG_B0_UDB02_03_ST 0x400068c4u +#define CYREG_B0_UDB03_04_ST 0x400068c6u +#define CYREG_B0_UDB04_05_ST 0x400068c8u +#define CYREG_B0_UDB05_06_ST 0x400068cau +#define CYREG_B0_UDB06_07_ST 0x400068ccu +#define CYREG_B0_UDB07_08_ST 0x400068ceu +#define CYREG_B0_UDB08_09_ST 0x400068d0u +#define CYREG_B0_UDB09_10_ST 0x400068d2u +#define CYREG_B0_UDB10_11_ST 0x400068d4u +#define CYREG_B0_UDB11_12_ST 0x400068d6u +#define CYREG_B0_UDB12_13_ST 0x400068d8u +#define CYREG_B0_UDB13_14_ST 0x400068dau +#define CYREG_B0_UDB14_15_ST 0x400068dcu +#define CYREG_B0_UDB00_01_CTL 0x400068e0u +#define CYREG_B0_UDB01_02_CTL 0x400068e2u +#define CYREG_B0_UDB02_03_CTL 0x400068e4u +#define CYREG_B0_UDB03_04_CTL 0x400068e6u +#define CYREG_B0_UDB04_05_CTL 0x400068e8u +#define CYREG_B0_UDB05_06_CTL 0x400068eau +#define CYREG_B0_UDB06_07_CTL 0x400068ecu +#define CYREG_B0_UDB07_08_CTL 0x400068eeu +#define CYREG_B0_UDB08_09_CTL 0x400068f0u +#define CYREG_B0_UDB09_10_CTL 0x400068f2u +#define CYREG_B0_UDB10_11_CTL 0x400068f4u +#define CYREG_B0_UDB11_12_CTL 0x400068f6u +#define CYREG_B0_UDB12_13_CTL 0x400068f8u +#define CYREG_B0_UDB13_14_CTL 0x400068fau +#define CYREG_B0_UDB14_15_CTL 0x400068fcu +#define CYREG_B0_UDB00_01_MSK 0x40006900u +#define CYREG_B0_UDB01_02_MSK 0x40006902u +#define CYREG_B0_UDB02_03_MSK 0x40006904u +#define CYREG_B0_UDB03_04_MSK 0x40006906u +#define CYREG_B0_UDB04_05_MSK 0x40006908u +#define CYREG_B0_UDB05_06_MSK 0x4000690au +#define CYREG_B0_UDB06_07_MSK 0x4000690cu +#define CYREG_B0_UDB07_08_MSK 0x4000690eu +#define CYREG_B0_UDB08_09_MSK 0x40006910u +#define CYREG_B0_UDB09_10_MSK 0x40006912u +#define CYREG_B0_UDB10_11_MSK 0x40006914u +#define CYREG_B0_UDB11_12_MSK 0x40006916u +#define CYREG_B0_UDB12_13_MSK 0x40006918u +#define CYREG_B0_UDB13_14_MSK 0x4000691au +#define CYREG_B0_UDB14_15_MSK 0x4000691cu +#define CYREG_B0_UDB00_01_ACTL 0x40006920u +#define CYREG_B0_UDB01_02_ACTL 0x40006922u +#define CYREG_B0_UDB02_03_ACTL 0x40006924u +#define CYREG_B0_UDB03_04_ACTL 0x40006926u +#define CYREG_B0_UDB04_05_ACTL 0x40006928u +#define CYREG_B0_UDB05_06_ACTL 0x4000692au +#define CYREG_B0_UDB06_07_ACTL 0x4000692cu +#define CYREG_B0_UDB07_08_ACTL 0x4000692eu +#define CYREG_B0_UDB08_09_ACTL 0x40006930u +#define CYREG_B0_UDB09_10_ACTL 0x40006932u +#define CYREG_B0_UDB10_11_ACTL 0x40006934u +#define CYREG_B0_UDB11_12_ACTL 0x40006936u +#define CYREG_B0_UDB12_13_ACTL 0x40006938u +#define CYREG_B0_UDB13_14_ACTL 0x4000693au +#define CYREG_B0_UDB14_15_ACTL 0x4000693cu +#define CYREG_B0_UDB00_01_MC 0x40006940u +#define CYREG_B0_UDB01_02_MC 0x40006942u +#define CYREG_B0_UDB02_03_MC 0x40006944u +#define CYREG_B0_UDB03_04_MC 0x40006946u +#define CYREG_B0_UDB04_05_MC 0x40006948u +#define CYREG_B0_UDB05_06_MC 0x4000694au +#define CYREG_B0_UDB06_07_MC 0x4000694cu +#define CYREG_B0_UDB07_08_MC 0x4000694eu +#define CYREG_B0_UDB08_09_MC 0x40006950u +#define CYREG_B0_UDB09_10_MC 0x40006952u +#define CYREG_B0_UDB10_11_MC 0x40006954u +#define CYREG_B0_UDB11_12_MC 0x40006956u +#define CYREG_B0_UDB12_13_MC 0x40006958u +#define CYREG_B0_UDB13_14_MC 0x4000695au +#define CYREG_B0_UDB14_15_MC 0x4000695cu +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu +#define CYREG_B1_UDB04_05_A0 0x40006a08u +#define CYREG_B1_UDB05_06_A0 0x40006a0au +#define CYREG_B1_UDB06_07_A0 0x40006a0cu +#define CYREG_B1_UDB07_08_A0 0x40006a0eu +#define CYREG_B1_UDB08_09_A0 0x40006a10u +#define CYREG_B1_UDB09_10_A0 0x40006a12u +#define CYREG_B1_UDB10_11_A0 0x40006a14u +#define CYREG_B1_UDB11_12_A0 0x40006a16u +#define CYREG_B1_UDB04_05_A1 0x40006a28u +#define CYREG_B1_UDB05_06_A1 0x40006a2au +#define CYREG_B1_UDB06_07_A1 0x40006a2cu +#define CYREG_B1_UDB07_08_A1 0x40006a2eu +#define CYREG_B1_UDB08_09_A1 0x40006a30u +#define CYREG_B1_UDB09_10_A1 0x40006a32u +#define CYREG_B1_UDB10_11_A1 0x40006a34u +#define CYREG_B1_UDB11_12_A1 0x40006a36u +#define CYREG_B1_UDB04_05_D0 0x40006a48u +#define CYREG_B1_UDB05_06_D0 0x40006a4au +#define CYREG_B1_UDB06_07_D0 0x40006a4cu +#define CYREG_B1_UDB07_08_D0 0x40006a4eu +#define CYREG_B1_UDB08_09_D0 0x40006a50u +#define CYREG_B1_UDB09_10_D0 0x40006a52u +#define CYREG_B1_UDB10_11_D0 0x40006a54u +#define CYREG_B1_UDB11_12_D0 0x40006a56u +#define CYREG_B1_UDB04_05_D1 0x40006a68u +#define CYREG_B1_UDB05_06_D1 0x40006a6au +#define CYREG_B1_UDB06_07_D1 0x40006a6cu +#define CYREG_B1_UDB07_08_D1 0x40006a6eu +#define CYREG_B1_UDB08_09_D1 0x40006a70u +#define CYREG_B1_UDB09_10_D1 0x40006a72u +#define CYREG_B1_UDB10_11_D1 0x40006a74u +#define CYREG_B1_UDB11_12_D1 0x40006a76u +#define CYREG_B1_UDB04_05_F0 0x40006a88u +#define CYREG_B1_UDB05_06_F0 0x40006a8au +#define CYREG_B1_UDB06_07_F0 0x40006a8cu +#define CYREG_B1_UDB07_08_F0 0x40006a8eu +#define CYREG_B1_UDB08_09_F0 0x40006a90u +#define CYREG_B1_UDB09_10_F0 0x40006a92u +#define CYREG_B1_UDB10_11_F0 0x40006a94u +#define CYREG_B1_UDB11_12_F0 0x40006a96u +#define CYREG_B1_UDB04_05_F1 0x40006aa8u +#define CYREG_B1_UDB05_06_F1 0x40006aaau +#define CYREG_B1_UDB06_07_F1 0x40006aacu +#define CYREG_B1_UDB07_08_F1 0x40006aaeu +#define CYREG_B1_UDB08_09_F1 0x40006ab0u +#define CYREG_B1_UDB09_10_F1 0x40006ab2u +#define CYREG_B1_UDB10_11_F1 0x40006ab4u +#define CYREG_B1_UDB11_12_F1 0x40006ab6u +#define CYREG_B1_UDB04_05_ST 0x40006ac8u +#define CYREG_B1_UDB05_06_ST 0x40006acau +#define CYREG_B1_UDB06_07_ST 0x40006accu +#define CYREG_B1_UDB07_08_ST 0x40006aceu +#define CYREG_B1_UDB08_09_ST 0x40006ad0u +#define CYREG_B1_UDB09_10_ST 0x40006ad2u +#define CYREG_B1_UDB10_11_ST 0x40006ad4u +#define CYREG_B1_UDB11_12_ST 0x40006ad6u +#define CYREG_B1_UDB04_05_CTL 0x40006ae8u +#define CYREG_B1_UDB05_06_CTL 0x40006aeau +#define CYREG_B1_UDB06_07_CTL 0x40006aecu +#define CYREG_B1_UDB07_08_CTL 0x40006aeeu +#define CYREG_B1_UDB08_09_CTL 0x40006af0u +#define CYREG_B1_UDB09_10_CTL 0x40006af2u +#define CYREG_B1_UDB10_11_CTL 0x40006af4u +#define CYREG_B1_UDB11_12_CTL 0x40006af6u +#define CYREG_B1_UDB04_05_MSK 0x40006b08u +#define CYREG_B1_UDB05_06_MSK 0x40006b0au +#define CYREG_B1_UDB06_07_MSK 0x40006b0cu +#define CYREG_B1_UDB07_08_MSK 0x40006b0eu +#define CYREG_B1_UDB08_09_MSK 0x40006b10u +#define CYREG_B1_UDB09_10_MSK 0x40006b12u +#define CYREG_B1_UDB10_11_MSK 0x40006b14u +#define CYREG_B1_UDB11_12_MSK 0x40006b16u +#define CYREG_B1_UDB04_05_ACTL 0x40006b28u +#define CYREG_B1_UDB05_06_ACTL 0x40006b2au +#define CYREG_B1_UDB06_07_ACTL 0x40006b2cu +#define CYREG_B1_UDB07_08_ACTL 0x40006b2eu +#define CYREG_B1_UDB08_09_ACTL 0x40006b30u +#define CYREG_B1_UDB09_10_ACTL 0x40006b32u +#define CYREG_B1_UDB10_11_ACTL 0x40006b34u +#define CYREG_B1_UDB11_12_ACTL 0x40006b36u +#define CYREG_B1_UDB04_05_MC 0x40006b48u +#define CYREG_B1_UDB05_06_MC 0x40006b4au +#define CYREG_B1_UDB06_07_MC 0x40006b4cu +#define CYREG_B1_UDB07_08_MC 0x40006b4eu +#define CYREG_B1_UDB08_09_MC 0x40006b50u +#define CYREG_B1_UDB09_10_MC 0x40006b52u +#define CYREG_B1_UDB10_11_MC 0x40006b54u +#define CYREG_B1_UDB11_12_MC 0x40006b56u +#define CYDEV_PHUB_BASE 0x40007000u +#define CYDEV_PHUB_SIZE 0x00000c00u +#define CYREG_PHUB_CFG 0x40007000u +#define CYREG_PHUB_ERR 0x40007004u +#define CYREG_PHUB_ERR_ADR 0x40007008u +#define CYDEV_PHUB_CH0_BASE 0x40007010u +#define CYDEV_PHUB_CH0_SIZE 0x0000000cu +#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010u +#define CYREG_PHUB_CH0_ACTION 0x40007014u +#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018u +#define CYDEV_PHUB_CH1_BASE 0x40007020u +#define CYDEV_PHUB_CH1_SIZE 0x0000000cu +#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020u +#define CYREG_PHUB_CH1_ACTION 0x40007024u +#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028u +#define CYDEV_PHUB_CH2_BASE 0x40007030u +#define CYDEV_PHUB_CH2_SIZE 0x0000000cu +#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030u +#define CYREG_PHUB_CH2_ACTION 0x40007034u +#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038u +#define CYDEV_PHUB_CH3_BASE 0x40007040u +#define CYDEV_PHUB_CH3_SIZE 0x0000000cu +#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040u +#define CYREG_PHUB_CH3_ACTION 0x40007044u +#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048u +#define CYDEV_PHUB_CH4_BASE 0x40007050u +#define CYDEV_PHUB_CH4_SIZE 0x0000000cu +#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050u +#define CYREG_PHUB_CH4_ACTION 0x40007054u +#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058u +#define CYDEV_PHUB_CH5_BASE 0x40007060u +#define CYDEV_PHUB_CH5_SIZE 0x0000000cu +#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060u +#define CYREG_PHUB_CH5_ACTION 0x40007064u +#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068u +#define CYDEV_PHUB_CH6_BASE 0x40007070u +#define CYDEV_PHUB_CH6_SIZE 0x0000000cu +#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070u +#define CYREG_PHUB_CH6_ACTION 0x40007074u +#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078u +#define CYDEV_PHUB_CH7_BASE 0x40007080u +#define CYDEV_PHUB_CH7_SIZE 0x0000000cu +#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080u +#define CYREG_PHUB_CH7_ACTION 0x40007084u +#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088u +#define CYDEV_PHUB_CH8_BASE 0x40007090u +#define CYDEV_PHUB_CH8_SIZE 0x0000000cu +#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090u +#define CYREG_PHUB_CH8_ACTION 0x40007094u +#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098u +#define CYDEV_PHUB_CH9_BASE 0x400070a0u +#define CYDEV_PHUB_CH9_SIZE 0x0000000cu +#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0u +#define CYREG_PHUB_CH9_ACTION 0x400070a4u +#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8u +#define CYDEV_PHUB_CH10_BASE 0x400070b0u +#define CYDEV_PHUB_CH10_SIZE 0x0000000cu +#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0u +#define CYREG_PHUB_CH10_ACTION 0x400070b4u +#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8u +#define CYDEV_PHUB_CH11_BASE 0x400070c0u +#define CYDEV_PHUB_CH11_SIZE 0x0000000cu +#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0u +#define CYREG_PHUB_CH11_ACTION 0x400070c4u +#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8u +#define CYDEV_PHUB_CH12_BASE 0x400070d0u +#define CYDEV_PHUB_CH12_SIZE 0x0000000cu +#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0u +#define CYREG_PHUB_CH12_ACTION 0x400070d4u +#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8u +#define CYDEV_PHUB_CH13_BASE 0x400070e0u +#define CYDEV_PHUB_CH13_SIZE 0x0000000cu +#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0u +#define CYREG_PHUB_CH13_ACTION 0x400070e4u +#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8u +#define CYDEV_PHUB_CH14_BASE 0x400070f0u +#define CYDEV_PHUB_CH14_SIZE 0x0000000cu +#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0u +#define CYREG_PHUB_CH14_ACTION 0x400070f4u +#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8u +#define CYDEV_PHUB_CH15_BASE 0x40007100u +#define CYDEV_PHUB_CH15_SIZE 0x0000000cu +#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100u +#define CYREG_PHUB_CH15_ACTION 0x40007104u +#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108u +#define CYDEV_PHUB_CH16_BASE 0x40007110u +#define CYDEV_PHUB_CH16_SIZE 0x0000000cu +#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110u +#define CYREG_PHUB_CH16_ACTION 0x40007114u +#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118u +#define CYDEV_PHUB_CH17_BASE 0x40007120u +#define CYDEV_PHUB_CH17_SIZE 0x0000000cu +#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120u +#define CYREG_PHUB_CH17_ACTION 0x40007124u +#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128u +#define CYDEV_PHUB_CH18_BASE 0x40007130u +#define CYDEV_PHUB_CH18_SIZE 0x0000000cu +#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130u +#define CYREG_PHUB_CH18_ACTION 0x40007134u +#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138u +#define CYDEV_PHUB_CH19_BASE 0x40007140u +#define CYDEV_PHUB_CH19_SIZE 0x0000000cu +#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140u +#define CYREG_PHUB_CH19_ACTION 0x40007144u +#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148u +#define CYDEV_PHUB_CH20_BASE 0x40007150u +#define CYDEV_PHUB_CH20_SIZE 0x0000000cu +#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150u +#define CYREG_PHUB_CH20_ACTION 0x40007154u +#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158u +#define CYDEV_PHUB_CH21_BASE 0x40007160u +#define CYDEV_PHUB_CH21_SIZE 0x0000000cu +#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160u +#define CYREG_PHUB_CH21_ACTION 0x40007164u +#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168u +#define CYDEV_PHUB_CH22_BASE 0x40007170u +#define CYDEV_PHUB_CH22_SIZE 0x0000000cu +#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170u +#define CYREG_PHUB_CH22_ACTION 0x40007174u +#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178u +#define CYDEV_PHUB_CH23_BASE 0x40007180u +#define CYDEV_PHUB_CH23_SIZE 0x0000000cu +#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180u +#define CYREG_PHUB_CH23_ACTION 0x40007184u +#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188u +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600u +#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604u +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608u +#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760cu +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610u +#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614u +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618u +#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761cu +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620u +#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624u +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628u +#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762cu +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630u +#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634u +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638u +#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763cu +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640u +#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644u +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648u +#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764cu +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650u +#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654u +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658u +#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765cu +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660u +#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664u +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668u +#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766cu +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670u +#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674u +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678u +#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767cu +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680u +#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684u +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688u +#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768cu +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690u +#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694u +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698u +#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769cu +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0u +#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4u +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8u +#define CYREG_PHUB_CFGMEM21_CFG1 0x400076acu +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0u +#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4u +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8u +#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bcu +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800u +#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804u +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808u +#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780cu +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810u +#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814u +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818u +#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781cu +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820u +#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824u +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828u +#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782cu +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830u +#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834u +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838u +#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783cu +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840u +#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844u +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848u +#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784cu +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850u +#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854u +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858u +#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785cu +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860u +#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864u +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868u +#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786cu +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870u +#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874u +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878u +#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787cu +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880u +#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884u +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888u +#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788cu +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890u +#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894u +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898u +#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789cu +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0u +#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4u +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8u +#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078acu +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0u +#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4u +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8u +#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bcu +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0u +#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4u +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8u +#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078ccu +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0u +#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4u +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8u +#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dcu +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0u +#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4u +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8u +#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ecu +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0u +#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4u +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8u +#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fcu +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900u +#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904u +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908u +#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790cu +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910u +#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914u +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918u +#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791cu +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920u +#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924u +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928u +#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792cu +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930u +#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934u +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938u +#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793cu +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940u +#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944u +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948u +#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794cu +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950u +#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954u +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958u +#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795cu +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960u +#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964u +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968u +#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796cu +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970u +#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974u +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978u +#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797cu +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980u +#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984u +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988u +#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798cu +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990u +#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994u +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998u +#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799cu +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0u +#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4u +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8u +#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079acu +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0u +#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4u +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8u +#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bcu +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0u +#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4u +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8u +#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079ccu +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0u +#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4u +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8u +#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dcu +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0u +#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4u +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8u +#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ecu +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0u +#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4u +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8u +#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fcu +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00u +#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04u +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08u +#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10u +#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14u +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18u +#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20u +#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24u +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28u +#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30u +#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34u +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38u +#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40u +#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44u +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48u +#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50u +#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54u +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58u +#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60u +#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64u +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68u +#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70u +#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74u +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78u +#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80u +#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84u +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88u +#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90u +#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94u +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98u +#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u +#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u +#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aacu +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u +#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u +#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abcu +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u +#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u +#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007accu +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u +#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u +#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adcu +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u +#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u +#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aecu +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0u +#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4u +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8u +#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afcu +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00u +#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04u +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08u +#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10u +#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14u +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18u +#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20u +#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24u +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28u +#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30u +#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34u +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38u +#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40u +#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44u +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48u +#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50u +#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54u +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58u +#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60u +#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64u +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68u +#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70u +#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74u +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78u +#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80u +#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84u +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88u +#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90u +#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94u +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98u +#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u +#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u +#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bacu +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u +#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u +#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u +#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u +#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bccu +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u +#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u +#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0u +#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4u +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8u +#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007becu +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u +#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u +#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu +#define CYDEV_EE_BASE 0x40008000u +#define CYDEV_EE_SIZE 0x00000800u +#define CYREG_EE_DATA_MBASE 0x40008000u +#define CYREG_EE_DATA_MSIZE 0x00000800u +#define CYDEV_CAN0_BASE 0x4000a000u +#define CYDEV_CAN0_SIZE 0x000002a0u +#define CYDEV_CAN0_CSR_BASE 0x4000a000u +#define CYDEV_CAN0_CSR_SIZE 0x00000018u +#define CYREG_CAN0_CSR_INT_SR 0x4000a000u +#define CYREG_CAN0_CSR_INT_EN 0x4000a004u +#define CYREG_CAN0_CSR_BUF_SR 0x4000a008u +#define CYREG_CAN0_CSR_ERR_SR 0x4000a00cu +#define CYREG_CAN0_CSR_CMD 0x4000a010u +#define CYREG_CAN0_CSR_CFG 0x4000a014u +#define CYDEV_CAN0_TX0_BASE 0x4000a020u +#define CYDEV_CAN0_TX0_SIZE 0x00000010u +#define CYREG_CAN0_TX0_CMD 0x4000a020u +#define CYREG_CAN0_TX0_ID 0x4000a024u +#define CYREG_CAN0_TX0_DH 0x4000a028u +#define CYREG_CAN0_TX0_DL 0x4000a02cu +#define CYDEV_CAN0_TX1_BASE 0x4000a030u +#define CYDEV_CAN0_TX1_SIZE 0x00000010u +#define CYREG_CAN0_TX1_CMD 0x4000a030u +#define CYREG_CAN0_TX1_ID 0x4000a034u +#define CYREG_CAN0_TX1_DH 0x4000a038u +#define CYREG_CAN0_TX1_DL 0x4000a03cu +#define CYDEV_CAN0_TX2_BASE 0x4000a040u +#define CYDEV_CAN0_TX2_SIZE 0x00000010u +#define CYREG_CAN0_TX2_CMD 0x4000a040u +#define CYREG_CAN0_TX2_ID 0x4000a044u +#define CYREG_CAN0_TX2_DH 0x4000a048u +#define CYREG_CAN0_TX2_DL 0x4000a04cu +#define CYDEV_CAN0_TX3_BASE 0x4000a050u +#define CYDEV_CAN0_TX3_SIZE 0x00000010u +#define CYREG_CAN0_TX3_CMD 0x4000a050u +#define CYREG_CAN0_TX3_ID 0x4000a054u +#define CYREG_CAN0_TX3_DH 0x4000a058u +#define CYREG_CAN0_TX3_DL 0x4000a05cu +#define CYDEV_CAN0_TX4_BASE 0x4000a060u +#define CYDEV_CAN0_TX4_SIZE 0x00000010u +#define CYREG_CAN0_TX4_CMD 0x4000a060u +#define CYREG_CAN0_TX4_ID 0x4000a064u +#define CYREG_CAN0_TX4_DH 0x4000a068u +#define CYREG_CAN0_TX4_DL 0x4000a06cu +#define CYDEV_CAN0_TX5_BASE 0x4000a070u +#define CYDEV_CAN0_TX5_SIZE 0x00000010u +#define CYREG_CAN0_TX5_CMD 0x4000a070u +#define CYREG_CAN0_TX5_ID 0x4000a074u +#define CYREG_CAN0_TX5_DH 0x4000a078u +#define CYREG_CAN0_TX5_DL 0x4000a07cu +#define CYDEV_CAN0_TX6_BASE 0x4000a080u +#define CYDEV_CAN0_TX6_SIZE 0x00000010u +#define CYREG_CAN0_TX6_CMD 0x4000a080u +#define CYREG_CAN0_TX6_ID 0x4000a084u +#define CYREG_CAN0_TX6_DH 0x4000a088u +#define CYREG_CAN0_TX6_DL 0x4000a08cu +#define CYDEV_CAN0_TX7_BASE 0x4000a090u +#define CYDEV_CAN0_TX7_SIZE 0x00000010u +#define CYREG_CAN0_TX7_CMD 0x4000a090u +#define CYREG_CAN0_TX7_ID 0x4000a094u +#define CYREG_CAN0_TX7_DH 0x4000a098u +#define CYREG_CAN0_TX7_DL 0x4000a09cu +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u +#define CYDEV_CAN0_RX0_SIZE 0x00000020u +#define CYREG_CAN0_RX0_CMD 0x4000a0a0u +#define CYREG_CAN0_RX0_ID 0x4000a0a4u +#define CYREG_CAN0_RX0_DH 0x4000a0a8u +#define CYREG_CAN0_RX0_DL 0x4000a0acu +#define CYREG_CAN0_RX0_AMR 0x4000a0b0u +#define CYREG_CAN0_RX0_ACR 0x4000a0b4u +#define CYREG_CAN0_RX0_AMRD 0x4000a0b8u +#define CYREG_CAN0_RX0_ACRD 0x4000a0bcu +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u +#define CYDEV_CAN0_RX1_SIZE 0x00000020u +#define CYREG_CAN0_RX1_CMD 0x4000a0c0u +#define CYREG_CAN0_RX1_ID 0x4000a0c4u +#define CYREG_CAN0_RX1_DH 0x4000a0c8u +#define CYREG_CAN0_RX1_DL 0x4000a0ccu +#define CYREG_CAN0_RX1_AMR 0x4000a0d0u +#define CYREG_CAN0_RX1_ACR 0x4000a0d4u +#define CYREG_CAN0_RX1_AMRD 0x4000a0d8u +#define CYREG_CAN0_RX1_ACRD 0x4000a0dcu +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u +#define CYDEV_CAN0_RX2_SIZE 0x00000020u +#define CYREG_CAN0_RX2_CMD 0x4000a0e0u +#define CYREG_CAN0_RX2_ID 0x4000a0e4u +#define CYREG_CAN0_RX2_DH 0x4000a0e8u +#define CYREG_CAN0_RX2_DL 0x4000a0ecu +#define CYREG_CAN0_RX2_AMR 0x4000a0f0u +#define CYREG_CAN0_RX2_ACR 0x4000a0f4u +#define CYREG_CAN0_RX2_AMRD 0x4000a0f8u +#define CYREG_CAN0_RX2_ACRD 0x4000a0fcu +#define CYDEV_CAN0_RX3_BASE 0x4000a100u +#define CYDEV_CAN0_RX3_SIZE 0x00000020u +#define CYREG_CAN0_RX3_CMD 0x4000a100u +#define CYREG_CAN0_RX3_ID 0x4000a104u +#define CYREG_CAN0_RX3_DH 0x4000a108u +#define CYREG_CAN0_RX3_DL 0x4000a10cu +#define CYREG_CAN0_RX3_AMR 0x4000a110u +#define CYREG_CAN0_RX3_ACR 0x4000a114u +#define CYREG_CAN0_RX3_AMRD 0x4000a118u +#define CYREG_CAN0_RX3_ACRD 0x4000a11cu +#define CYDEV_CAN0_RX4_BASE 0x4000a120u +#define CYDEV_CAN0_RX4_SIZE 0x00000020u +#define CYREG_CAN0_RX4_CMD 0x4000a120u +#define CYREG_CAN0_RX4_ID 0x4000a124u +#define CYREG_CAN0_RX4_DH 0x4000a128u +#define CYREG_CAN0_RX4_DL 0x4000a12cu +#define CYREG_CAN0_RX4_AMR 0x4000a130u +#define CYREG_CAN0_RX4_ACR 0x4000a134u +#define CYREG_CAN0_RX4_AMRD 0x4000a138u +#define CYREG_CAN0_RX4_ACRD 0x4000a13cu +#define CYDEV_CAN0_RX5_BASE 0x4000a140u +#define CYDEV_CAN0_RX5_SIZE 0x00000020u +#define CYREG_CAN0_RX5_CMD 0x4000a140u +#define CYREG_CAN0_RX5_ID 0x4000a144u +#define CYREG_CAN0_RX5_DH 0x4000a148u +#define CYREG_CAN0_RX5_DL 0x4000a14cu +#define CYREG_CAN0_RX5_AMR 0x4000a150u +#define CYREG_CAN0_RX5_ACR 0x4000a154u +#define CYREG_CAN0_RX5_AMRD 0x4000a158u +#define CYREG_CAN0_RX5_ACRD 0x4000a15cu +#define CYDEV_CAN0_RX6_BASE 0x4000a160u +#define CYDEV_CAN0_RX6_SIZE 0x00000020u +#define CYREG_CAN0_RX6_CMD 0x4000a160u +#define CYREG_CAN0_RX6_ID 0x4000a164u +#define CYREG_CAN0_RX6_DH 0x4000a168u +#define CYREG_CAN0_RX6_DL 0x4000a16cu +#define CYREG_CAN0_RX6_AMR 0x4000a170u +#define CYREG_CAN0_RX6_ACR 0x4000a174u +#define CYREG_CAN0_RX6_AMRD 0x4000a178u +#define CYREG_CAN0_RX6_ACRD 0x4000a17cu +#define CYDEV_CAN0_RX7_BASE 0x4000a180u +#define CYDEV_CAN0_RX7_SIZE 0x00000020u +#define CYREG_CAN0_RX7_CMD 0x4000a180u +#define CYREG_CAN0_RX7_ID 0x4000a184u +#define CYREG_CAN0_RX7_DH 0x4000a188u +#define CYREG_CAN0_RX7_DL 0x4000a18cu +#define CYREG_CAN0_RX7_AMR 0x4000a190u +#define CYREG_CAN0_RX7_ACR 0x4000a194u +#define CYREG_CAN0_RX7_AMRD 0x4000a198u +#define CYREG_CAN0_RX7_ACRD 0x4000a19cu +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u +#define CYDEV_CAN0_RX8_SIZE 0x00000020u +#define CYREG_CAN0_RX8_CMD 0x4000a1a0u +#define CYREG_CAN0_RX8_ID 0x4000a1a4u +#define CYREG_CAN0_RX8_DH 0x4000a1a8u +#define CYREG_CAN0_RX8_DL 0x4000a1acu +#define CYREG_CAN0_RX8_AMR 0x4000a1b0u +#define CYREG_CAN0_RX8_ACR 0x4000a1b4u +#define CYREG_CAN0_RX8_AMRD 0x4000a1b8u +#define CYREG_CAN0_RX8_ACRD 0x4000a1bcu +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u +#define CYDEV_CAN0_RX9_SIZE 0x00000020u +#define CYREG_CAN0_RX9_CMD 0x4000a1c0u +#define CYREG_CAN0_RX9_ID 0x4000a1c4u +#define CYREG_CAN0_RX9_DH 0x4000a1c8u +#define CYREG_CAN0_RX9_DL 0x4000a1ccu +#define CYREG_CAN0_RX9_AMR 0x4000a1d0u +#define CYREG_CAN0_RX9_ACR 0x4000a1d4u +#define CYREG_CAN0_RX9_AMRD 0x4000a1d8u +#define CYREG_CAN0_RX9_ACRD 0x4000a1dcu +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u +#define CYDEV_CAN0_RX10_SIZE 0x00000020u +#define CYREG_CAN0_RX10_CMD 0x4000a1e0u +#define CYREG_CAN0_RX10_ID 0x4000a1e4u +#define CYREG_CAN0_RX10_DH 0x4000a1e8u +#define CYREG_CAN0_RX10_DL 0x4000a1ecu +#define CYREG_CAN0_RX10_AMR 0x4000a1f0u +#define CYREG_CAN0_RX10_ACR 0x4000a1f4u +#define CYREG_CAN0_RX10_AMRD 0x4000a1f8u +#define CYREG_CAN0_RX10_ACRD 0x4000a1fcu +#define CYDEV_CAN0_RX11_BASE 0x4000a200u +#define CYDEV_CAN0_RX11_SIZE 0x00000020u +#define CYREG_CAN0_RX11_CMD 0x4000a200u +#define CYREG_CAN0_RX11_ID 0x4000a204u +#define CYREG_CAN0_RX11_DH 0x4000a208u +#define CYREG_CAN0_RX11_DL 0x4000a20cu +#define CYREG_CAN0_RX11_AMR 0x4000a210u +#define CYREG_CAN0_RX11_ACR 0x4000a214u +#define CYREG_CAN0_RX11_AMRD 0x4000a218u +#define CYREG_CAN0_RX11_ACRD 0x4000a21cu +#define CYDEV_CAN0_RX12_BASE 0x4000a220u +#define CYDEV_CAN0_RX12_SIZE 0x00000020u +#define CYREG_CAN0_RX12_CMD 0x4000a220u +#define CYREG_CAN0_RX12_ID 0x4000a224u +#define CYREG_CAN0_RX12_DH 0x4000a228u +#define CYREG_CAN0_RX12_DL 0x4000a22cu +#define CYREG_CAN0_RX12_AMR 0x4000a230u +#define CYREG_CAN0_RX12_ACR 0x4000a234u +#define CYREG_CAN0_RX12_AMRD 0x4000a238u +#define CYREG_CAN0_RX12_ACRD 0x4000a23cu +#define CYDEV_CAN0_RX13_BASE 0x4000a240u +#define CYDEV_CAN0_RX13_SIZE 0x00000020u +#define CYREG_CAN0_RX13_CMD 0x4000a240u +#define CYREG_CAN0_RX13_ID 0x4000a244u +#define CYREG_CAN0_RX13_DH 0x4000a248u +#define CYREG_CAN0_RX13_DL 0x4000a24cu +#define CYREG_CAN0_RX13_AMR 0x4000a250u +#define CYREG_CAN0_RX13_ACR 0x4000a254u +#define CYREG_CAN0_RX13_AMRD 0x4000a258u +#define CYREG_CAN0_RX13_ACRD 0x4000a25cu +#define CYDEV_CAN0_RX14_BASE 0x4000a260u +#define CYDEV_CAN0_RX14_SIZE 0x00000020u +#define CYREG_CAN0_RX14_CMD 0x4000a260u +#define CYREG_CAN0_RX14_ID 0x4000a264u +#define CYREG_CAN0_RX14_DH 0x4000a268u +#define CYREG_CAN0_RX14_DL 0x4000a26cu +#define CYREG_CAN0_RX14_AMR 0x4000a270u +#define CYREG_CAN0_RX14_ACR 0x4000a274u +#define CYREG_CAN0_RX14_AMRD 0x4000a278u +#define CYREG_CAN0_RX14_ACRD 0x4000a27cu +#define CYDEV_CAN0_RX15_BASE 0x4000a280u +#define CYDEV_CAN0_RX15_SIZE 0x00000020u +#define CYREG_CAN0_RX15_CMD 0x4000a280u +#define CYREG_CAN0_RX15_ID 0x4000a284u +#define CYREG_CAN0_RX15_DH 0x4000a288u +#define CYREG_CAN0_RX15_DL 0x4000a28cu +#define CYREG_CAN0_RX15_AMR 0x4000a290u +#define CYREG_CAN0_RX15_ACR 0x4000a294u +#define CYREG_CAN0_RX15_AMRD 0x4000a298u +#define CYREG_CAN0_RX15_ACRD 0x4000a29cu +#define CYDEV_DFB0_BASE 0x4000c000u +#define CYDEV_DFB0_SIZE 0x000007b5u +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u +#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u +#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u +#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u +#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u +#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u +#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u +#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u +#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u +#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u +#define CYREG_DFB0_CR 0x4000c780u +#define CYREG_DFB0_SR 0x4000c784u +#define CYREG_DFB0_RAM_EN 0x4000c788u +#define CYREG_DFB0_RAM_DIR 0x4000c78cu +#define CYREG_DFB0_SEMA 0x4000c790u +#define CYREG_DFB0_DSI_CTRL 0x4000c794u +#define CYREG_DFB0_INT_CTRL 0x4000c798u +#define CYREG_DFB0_DMA_CTRL 0x4000c79cu +#define CYREG_DFB0_STAGEA 0x4000c7a0u +#define CYREG_DFB0_STAGEAM 0x4000c7a1u +#define CYREG_DFB0_STAGEAH 0x4000c7a2u +#define CYREG_DFB0_STAGEB 0x4000c7a4u +#define CYREG_DFB0_STAGEBM 0x4000c7a5u +#define CYREG_DFB0_STAGEBH 0x4000c7a6u +#define CYREG_DFB0_HOLDA 0x4000c7a8u +#define CYREG_DFB0_HOLDAM 0x4000c7a9u +#define CYREG_DFB0_HOLDAH 0x4000c7aau +#define CYREG_DFB0_HOLDAS 0x4000c7abu +#define CYREG_DFB0_HOLDB 0x4000c7acu +#define CYREG_DFB0_HOLDBM 0x4000c7adu +#define CYREG_DFB0_HOLDBH 0x4000c7aeu +#define CYREG_DFB0_HOLDBS 0x4000c7afu +#define CYREG_DFB0_COHER 0x4000c7b0u +#define CYREG_DFB0_DALIGN 0x4000c7b4u +#define CYDEV_UCFG_BASE 0x40010000u +#define CYDEV_UCFG_SIZE 0x00005040u +#define CYDEV_UCFG_B0_BASE 0x40010000u +#define CYDEV_UCFG_B0_SIZE 0x00000fefu +#define CYDEV_UCFG_B0_P0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u +#define CYREG_B0_P0_U0_PLD_IT0 0x40010000u +#define CYREG_B0_P0_U0_PLD_IT1 0x40010004u +#define CYREG_B0_P0_U0_PLD_IT2 0x40010008u +#define CYREG_B0_P0_U0_PLD_IT3 0x4001000cu +#define CYREG_B0_P0_U0_PLD_IT4 0x40010010u +#define CYREG_B0_P0_U0_PLD_IT5 0x40010014u +#define CYREG_B0_P0_U0_PLD_IT6 0x40010018u +#define CYREG_B0_P0_U0_PLD_IT7 0x4001001cu +#define CYREG_B0_P0_U0_PLD_IT8 0x40010020u +#define CYREG_B0_P0_U0_PLD_IT9 0x40010024u +#define CYREG_B0_P0_U0_PLD_IT10 0x40010028u +#define CYREG_B0_P0_U0_PLD_IT11 0x4001002cu +#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030u +#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032u +#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034u +#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036u +#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u +#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003au +#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu +#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu +#define CYREG_B0_P0_U0_CFG0 0x40010040u +#define CYREG_B0_P0_U0_CFG1 0x40010041u +#define CYREG_B0_P0_U0_CFG2 0x40010042u +#define CYREG_B0_P0_U0_CFG3 0x40010043u +#define CYREG_B0_P0_U0_CFG4 0x40010044u +#define CYREG_B0_P0_U0_CFG5 0x40010045u +#define CYREG_B0_P0_U0_CFG6 0x40010046u +#define CYREG_B0_P0_U0_CFG7 0x40010047u +#define CYREG_B0_P0_U0_CFG8 0x40010048u +#define CYREG_B0_P0_U0_CFG9 0x40010049u +#define CYREG_B0_P0_U0_CFG10 0x4001004au +#define CYREG_B0_P0_U0_CFG11 0x4001004bu +#define CYREG_B0_P0_U0_CFG12 0x4001004cu +#define CYREG_B0_P0_U0_CFG13 0x4001004du +#define CYREG_B0_P0_U0_CFG14 0x4001004eu +#define CYREG_B0_P0_U0_CFG15 0x4001004fu +#define CYREG_B0_P0_U0_CFG16 0x40010050u +#define CYREG_B0_P0_U0_CFG17 0x40010051u +#define CYREG_B0_P0_U0_CFG18 0x40010052u +#define CYREG_B0_P0_U0_CFG19 0x40010053u +#define CYREG_B0_P0_U0_CFG20 0x40010054u +#define CYREG_B0_P0_U0_CFG21 0x40010055u +#define CYREG_B0_P0_U0_CFG22 0x40010056u +#define CYREG_B0_P0_U0_CFG23 0x40010057u +#define CYREG_B0_P0_U0_CFG24 0x40010058u +#define CYREG_B0_P0_U0_CFG25 0x40010059u +#define CYREG_B0_P0_U0_CFG26 0x4001005au +#define CYREG_B0_P0_U0_CFG27 0x4001005bu +#define CYREG_B0_P0_U0_CFG28 0x4001005cu +#define CYREG_B0_P0_U0_CFG29 0x4001005du +#define CYREG_B0_P0_U0_CFG30 0x4001005eu +#define CYREG_B0_P0_U0_CFG31 0x4001005fu +#define CYREG_B0_P0_U0_DCFG0 0x40010060u +#define CYREG_B0_P0_U0_DCFG1 0x40010062u +#define CYREG_B0_P0_U0_DCFG2 0x40010064u +#define CYREG_B0_P0_U0_DCFG3 0x40010066u +#define CYREG_B0_P0_U0_DCFG4 0x40010068u +#define CYREG_B0_P0_U0_DCFG5 0x4001006au +#define CYREG_B0_P0_U0_DCFG6 0x4001006cu +#define CYREG_B0_P0_U0_DCFG7 0x4001006eu +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u +#define CYREG_B0_P0_U1_PLD_IT0 0x40010080u +#define CYREG_B0_P0_U1_PLD_IT1 0x40010084u +#define CYREG_B0_P0_U1_PLD_IT2 0x40010088u +#define CYREG_B0_P0_U1_PLD_IT3 0x4001008cu +#define CYREG_B0_P0_U1_PLD_IT4 0x40010090u +#define CYREG_B0_P0_U1_PLD_IT5 0x40010094u +#define CYREG_B0_P0_U1_PLD_IT6 0x40010098u +#define CYREG_B0_P0_U1_PLD_IT7 0x4001009cu +#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0u +#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4u +#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8u +#define CYREG_B0_P0_U1_PLD_IT11 0x400100acu +#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0u +#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2u +#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4u +#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6u +#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u +#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100bau +#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu +#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu +#define CYREG_B0_P0_U1_CFG0 0x400100c0u +#define CYREG_B0_P0_U1_CFG1 0x400100c1u +#define CYREG_B0_P0_U1_CFG2 0x400100c2u +#define CYREG_B0_P0_U1_CFG3 0x400100c3u +#define CYREG_B0_P0_U1_CFG4 0x400100c4u +#define CYREG_B0_P0_U1_CFG5 0x400100c5u +#define CYREG_B0_P0_U1_CFG6 0x400100c6u +#define CYREG_B0_P0_U1_CFG7 0x400100c7u +#define CYREG_B0_P0_U1_CFG8 0x400100c8u +#define CYREG_B0_P0_U1_CFG9 0x400100c9u +#define CYREG_B0_P0_U1_CFG10 0x400100cau +#define CYREG_B0_P0_U1_CFG11 0x400100cbu +#define CYREG_B0_P0_U1_CFG12 0x400100ccu +#define CYREG_B0_P0_U1_CFG13 0x400100cdu +#define CYREG_B0_P0_U1_CFG14 0x400100ceu +#define CYREG_B0_P0_U1_CFG15 0x400100cfu +#define CYREG_B0_P0_U1_CFG16 0x400100d0u +#define CYREG_B0_P0_U1_CFG17 0x400100d1u +#define CYREG_B0_P0_U1_CFG18 0x400100d2u +#define CYREG_B0_P0_U1_CFG19 0x400100d3u +#define CYREG_B0_P0_U1_CFG20 0x400100d4u +#define CYREG_B0_P0_U1_CFG21 0x400100d5u +#define CYREG_B0_P0_U1_CFG22 0x400100d6u +#define CYREG_B0_P0_U1_CFG23 0x400100d7u +#define CYREG_B0_P0_U1_CFG24 0x400100d8u +#define CYREG_B0_P0_U1_CFG25 0x400100d9u +#define CYREG_B0_P0_U1_CFG26 0x400100dau +#define CYREG_B0_P0_U1_CFG27 0x400100dbu +#define CYREG_B0_P0_U1_CFG28 0x400100dcu +#define CYREG_B0_P0_U1_CFG29 0x400100ddu +#define CYREG_B0_P0_U1_CFG30 0x400100deu +#define CYREG_B0_P0_U1_CFG31 0x400100dfu +#define CYREG_B0_P0_U1_DCFG0 0x400100e0u +#define CYREG_B0_P0_U1_DCFG1 0x400100e2u +#define CYREG_B0_P0_U1_DCFG2 0x400100e4u +#define CYREG_B0_P0_U1_DCFG3 0x400100e6u +#define CYREG_B0_P0_U1_DCFG4 0x400100e8u +#define CYREG_B0_P0_U1_DCFG5 0x400100eau +#define CYREG_B0_P0_U1_DCFG6 0x400100ecu +#define CYREG_B0_P0_U1_DCFG7 0x400100eeu +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P1_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u +#define CYREG_B0_P1_U0_PLD_IT0 0x40010200u +#define CYREG_B0_P1_U0_PLD_IT1 0x40010204u +#define CYREG_B0_P1_U0_PLD_IT2 0x40010208u +#define CYREG_B0_P1_U0_PLD_IT3 0x4001020cu +#define CYREG_B0_P1_U0_PLD_IT4 0x40010210u +#define CYREG_B0_P1_U0_PLD_IT5 0x40010214u +#define CYREG_B0_P1_U0_PLD_IT6 0x40010218u +#define CYREG_B0_P1_U0_PLD_IT7 0x4001021cu +#define CYREG_B0_P1_U0_PLD_IT8 0x40010220u +#define CYREG_B0_P1_U0_PLD_IT9 0x40010224u +#define CYREG_B0_P1_U0_PLD_IT10 0x40010228u +#define CYREG_B0_P1_U0_PLD_IT11 0x4001022cu +#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230u +#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232u +#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234u +#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236u +#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u +#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023au +#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu +#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu +#define CYREG_B0_P1_U0_CFG0 0x40010240u +#define CYREG_B0_P1_U0_CFG1 0x40010241u +#define CYREG_B0_P1_U0_CFG2 0x40010242u +#define CYREG_B0_P1_U0_CFG3 0x40010243u +#define CYREG_B0_P1_U0_CFG4 0x40010244u +#define CYREG_B0_P1_U0_CFG5 0x40010245u +#define CYREG_B0_P1_U0_CFG6 0x40010246u +#define CYREG_B0_P1_U0_CFG7 0x40010247u +#define CYREG_B0_P1_U0_CFG8 0x40010248u +#define CYREG_B0_P1_U0_CFG9 0x40010249u +#define CYREG_B0_P1_U0_CFG10 0x4001024au +#define CYREG_B0_P1_U0_CFG11 0x4001024bu +#define CYREG_B0_P1_U0_CFG12 0x4001024cu +#define CYREG_B0_P1_U0_CFG13 0x4001024du +#define CYREG_B0_P1_U0_CFG14 0x4001024eu +#define CYREG_B0_P1_U0_CFG15 0x4001024fu +#define CYREG_B0_P1_U0_CFG16 0x40010250u +#define CYREG_B0_P1_U0_CFG17 0x40010251u +#define CYREG_B0_P1_U0_CFG18 0x40010252u +#define CYREG_B0_P1_U0_CFG19 0x40010253u +#define CYREG_B0_P1_U0_CFG20 0x40010254u +#define CYREG_B0_P1_U0_CFG21 0x40010255u +#define CYREG_B0_P1_U0_CFG22 0x40010256u +#define CYREG_B0_P1_U0_CFG23 0x40010257u +#define CYREG_B0_P1_U0_CFG24 0x40010258u +#define CYREG_B0_P1_U0_CFG25 0x40010259u +#define CYREG_B0_P1_U0_CFG26 0x4001025au +#define CYREG_B0_P1_U0_CFG27 0x4001025bu +#define CYREG_B0_P1_U0_CFG28 0x4001025cu +#define CYREG_B0_P1_U0_CFG29 0x4001025du +#define CYREG_B0_P1_U0_CFG30 0x4001025eu +#define CYREG_B0_P1_U0_CFG31 0x4001025fu +#define CYREG_B0_P1_U0_DCFG0 0x40010260u +#define CYREG_B0_P1_U0_DCFG1 0x40010262u +#define CYREG_B0_P1_U0_DCFG2 0x40010264u +#define CYREG_B0_P1_U0_DCFG3 0x40010266u +#define CYREG_B0_P1_U0_DCFG4 0x40010268u +#define CYREG_B0_P1_U0_DCFG5 0x4001026au +#define CYREG_B0_P1_U0_DCFG6 0x4001026cu +#define CYREG_B0_P1_U0_DCFG7 0x4001026eu +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u +#define CYREG_B0_P1_U1_PLD_IT0 0x40010280u +#define CYREG_B0_P1_U1_PLD_IT1 0x40010284u +#define CYREG_B0_P1_U1_PLD_IT2 0x40010288u +#define CYREG_B0_P1_U1_PLD_IT3 0x4001028cu +#define CYREG_B0_P1_U1_PLD_IT4 0x40010290u +#define CYREG_B0_P1_U1_PLD_IT5 0x40010294u +#define CYREG_B0_P1_U1_PLD_IT6 0x40010298u +#define CYREG_B0_P1_U1_PLD_IT7 0x4001029cu +#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0u +#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4u +#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8u +#define CYREG_B0_P1_U1_PLD_IT11 0x400102acu +#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0u +#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2u +#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4u +#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6u +#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u +#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102bau +#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu +#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu +#define CYREG_B0_P1_U1_CFG0 0x400102c0u +#define CYREG_B0_P1_U1_CFG1 0x400102c1u +#define CYREG_B0_P1_U1_CFG2 0x400102c2u +#define CYREG_B0_P1_U1_CFG3 0x400102c3u +#define CYREG_B0_P1_U1_CFG4 0x400102c4u +#define CYREG_B0_P1_U1_CFG5 0x400102c5u +#define CYREG_B0_P1_U1_CFG6 0x400102c6u +#define CYREG_B0_P1_U1_CFG7 0x400102c7u +#define CYREG_B0_P1_U1_CFG8 0x400102c8u +#define CYREG_B0_P1_U1_CFG9 0x400102c9u +#define CYREG_B0_P1_U1_CFG10 0x400102cau +#define CYREG_B0_P1_U1_CFG11 0x400102cbu +#define CYREG_B0_P1_U1_CFG12 0x400102ccu +#define CYREG_B0_P1_U1_CFG13 0x400102cdu +#define CYREG_B0_P1_U1_CFG14 0x400102ceu +#define CYREG_B0_P1_U1_CFG15 0x400102cfu +#define CYREG_B0_P1_U1_CFG16 0x400102d0u +#define CYREG_B0_P1_U1_CFG17 0x400102d1u +#define CYREG_B0_P1_U1_CFG18 0x400102d2u +#define CYREG_B0_P1_U1_CFG19 0x400102d3u +#define CYREG_B0_P1_U1_CFG20 0x400102d4u +#define CYREG_B0_P1_U1_CFG21 0x400102d5u +#define CYREG_B0_P1_U1_CFG22 0x400102d6u +#define CYREG_B0_P1_U1_CFG23 0x400102d7u +#define CYREG_B0_P1_U1_CFG24 0x400102d8u +#define CYREG_B0_P1_U1_CFG25 0x400102d9u +#define CYREG_B0_P1_U1_CFG26 0x400102dau +#define CYREG_B0_P1_U1_CFG27 0x400102dbu +#define CYREG_B0_P1_U1_CFG28 0x400102dcu +#define CYREG_B0_P1_U1_CFG29 0x400102ddu +#define CYREG_B0_P1_U1_CFG30 0x400102deu +#define CYREG_B0_P1_U1_CFG31 0x400102dfu +#define CYREG_B0_P1_U1_DCFG0 0x400102e0u +#define CYREG_B0_P1_U1_DCFG1 0x400102e2u +#define CYREG_B0_P1_U1_DCFG2 0x400102e4u +#define CYREG_B0_P1_U1_DCFG3 0x400102e6u +#define CYREG_B0_P1_U1_DCFG4 0x400102e8u +#define CYREG_B0_P1_U1_DCFG5 0x400102eau +#define CYREG_B0_P1_U1_DCFG6 0x400102ecu +#define CYREG_B0_P1_U1_DCFG7 0x400102eeu +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P2_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u +#define CYREG_B0_P2_U0_PLD_IT0 0x40010400u +#define CYREG_B0_P2_U0_PLD_IT1 0x40010404u +#define CYREG_B0_P2_U0_PLD_IT2 0x40010408u +#define CYREG_B0_P2_U0_PLD_IT3 0x4001040cu +#define CYREG_B0_P2_U0_PLD_IT4 0x40010410u +#define CYREG_B0_P2_U0_PLD_IT5 0x40010414u +#define CYREG_B0_P2_U0_PLD_IT6 0x40010418u +#define CYREG_B0_P2_U0_PLD_IT7 0x4001041cu +#define CYREG_B0_P2_U0_PLD_IT8 0x40010420u +#define CYREG_B0_P2_U0_PLD_IT9 0x40010424u +#define CYREG_B0_P2_U0_PLD_IT10 0x40010428u +#define CYREG_B0_P2_U0_PLD_IT11 0x4001042cu +#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430u +#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432u +#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434u +#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436u +#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u +#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043au +#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu +#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu +#define CYREG_B0_P2_U0_CFG0 0x40010440u +#define CYREG_B0_P2_U0_CFG1 0x40010441u +#define CYREG_B0_P2_U0_CFG2 0x40010442u +#define CYREG_B0_P2_U0_CFG3 0x40010443u +#define CYREG_B0_P2_U0_CFG4 0x40010444u +#define CYREG_B0_P2_U0_CFG5 0x40010445u +#define CYREG_B0_P2_U0_CFG6 0x40010446u +#define CYREG_B0_P2_U0_CFG7 0x40010447u +#define CYREG_B0_P2_U0_CFG8 0x40010448u +#define CYREG_B0_P2_U0_CFG9 0x40010449u +#define CYREG_B0_P2_U0_CFG10 0x4001044au +#define CYREG_B0_P2_U0_CFG11 0x4001044bu +#define CYREG_B0_P2_U0_CFG12 0x4001044cu +#define CYREG_B0_P2_U0_CFG13 0x4001044du +#define CYREG_B0_P2_U0_CFG14 0x4001044eu +#define CYREG_B0_P2_U0_CFG15 0x4001044fu +#define CYREG_B0_P2_U0_CFG16 0x40010450u +#define CYREG_B0_P2_U0_CFG17 0x40010451u +#define CYREG_B0_P2_U0_CFG18 0x40010452u +#define CYREG_B0_P2_U0_CFG19 0x40010453u +#define CYREG_B0_P2_U0_CFG20 0x40010454u +#define CYREG_B0_P2_U0_CFG21 0x40010455u +#define CYREG_B0_P2_U0_CFG22 0x40010456u +#define CYREG_B0_P2_U0_CFG23 0x40010457u +#define CYREG_B0_P2_U0_CFG24 0x40010458u +#define CYREG_B0_P2_U0_CFG25 0x40010459u +#define CYREG_B0_P2_U0_CFG26 0x4001045au +#define CYREG_B0_P2_U0_CFG27 0x4001045bu +#define CYREG_B0_P2_U0_CFG28 0x4001045cu +#define CYREG_B0_P2_U0_CFG29 0x4001045du +#define CYREG_B0_P2_U0_CFG30 0x4001045eu +#define CYREG_B0_P2_U0_CFG31 0x4001045fu +#define CYREG_B0_P2_U0_DCFG0 0x40010460u +#define CYREG_B0_P2_U0_DCFG1 0x40010462u +#define CYREG_B0_P2_U0_DCFG2 0x40010464u +#define CYREG_B0_P2_U0_DCFG3 0x40010466u +#define CYREG_B0_P2_U0_DCFG4 0x40010468u +#define CYREG_B0_P2_U0_DCFG5 0x4001046au +#define CYREG_B0_P2_U0_DCFG6 0x4001046cu +#define CYREG_B0_P2_U0_DCFG7 0x4001046eu +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u +#define CYREG_B0_P2_U1_PLD_IT0 0x40010480u +#define CYREG_B0_P2_U1_PLD_IT1 0x40010484u +#define CYREG_B0_P2_U1_PLD_IT2 0x40010488u +#define CYREG_B0_P2_U1_PLD_IT3 0x4001048cu +#define CYREG_B0_P2_U1_PLD_IT4 0x40010490u +#define CYREG_B0_P2_U1_PLD_IT5 0x40010494u +#define CYREG_B0_P2_U1_PLD_IT6 0x40010498u +#define CYREG_B0_P2_U1_PLD_IT7 0x4001049cu +#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0u +#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4u +#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8u +#define CYREG_B0_P2_U1_PLD_IT11 0x400104acu +#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0u +#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2u +#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4u +#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6u +#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u +#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104bau +#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu +#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu +#define CYREG_B0_P2_U1_CFG0 0x400104c0u +#define CYREG_B0_P2_U1_CFG1 0x400104c1u +#define CYREG_B0_P2_U1_CFG2 0x400104c2u +#define CYREG_B0_P2_U1_CFG3 0x400104c3u +#define CYREG_B0_P2_U1_CFG4 0x400104c4u +#define CYREG_B0_P2_U1_CFG5 0x400104c5u +#define CYREG_B0_P2_U1_CFG6 0x400104c6u +#define CYREG_B0_P2_U1_CFG7 0x400104c7u +#define CYREG_B0_P2_U1_CFG8 0x400104c8u +#define CYREG_B0_P2_U1_CFG9 0x400104c9u +#define CYREG_B0_P2_U1_CFG10 0x400104cau +#define CYREG_B0_P2_U1_CFG11 0x400104cbu +#define CYREG_B0_P2_U1_CFG12 0x400104ccu +#define CYREG_B0_P2_U1_CFG13 0x400104cdu +#define CYREG_B0_P2_U1_CFG14 0x400104ceu +#define CYREG_B0_P2_U1_CFG15 0x400104cfu +#define CYREG_B0_P2_U1_CFG16 0x400104d0u +#define CYREG_B0_P2_U1_CFG17 0x400104d1u +#define CYREG_B0_P2_U1_CFG18 0x400104d2u +#define CYREG_B0_P2_U1_CFG19 0x400104d3u +#define CYREG_B0_P2_U1_CFG20 0x400104d4u +#define CYREG_B0_P2_U1_CFG21 0x400104d5u +#define CYREG_B0_P2_U1_CFG22 0x400104d6u +#define CYREG_B0_P2_U1_CFG23 0x400104d7u +#define CYREG_B0_P2_U1_CFG24 0x400104d8u +#define CYREG_B0_P2_U1_CFG25 0x400104d9u +#define CYREG_B0_P2_U1_CFG26 0x400104dau +#define CYREG_B0_P2_U1_CFG27 0x400104dbu +#define CYREG_B0_P2_U1_CFG28 0x400104dcu +#define CYREG_B0_P2_U1_CFG29 0x400104ddu +#define CYREG_B0_P2_U1_CFG30 0x400104deu +#define CYREG_B0_P2_U1_CFG31 0x400104dfu +#define CYREG_B0_P2_U1_DCFG0 0x400104e0u +#define CYREG_B0_P2_U1_DCFG1 0x400104e2u +#define CYREG_B0_P2_U1_DCFG2 0x400104e4u +#define CYREG_B0_P2_U1_DCFG3 0x400104e6u +#define CYREG_B0_P2_U1_DCFG4 0x400104e8u +#define CYREG_B0_P2_U1_DCFG5 0x400104eau +#define CYREG_B0_P2_U1_DCFG6 0x400104ecu +#define CYREG_B0_P2_U1_DCFG7 0x400104eeu +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P3_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u +#define CYREG_B0_P3_U0_PLD_IT0 0x40010600u +#define CYREG_B0_P3_U0_PLD_IT1 0x40010604u +#define CYREG_B0_P3_U0_PLD_IT2 0x40010608u +#define CYREG_B0_P3_U0_PLD_IT3 0x4001060cu +#define CYREG_B0_P3_U0_PLD_IT4 0x40010610u +#define CYREG_B0_P3_U0_PLD_IT5 0x40010614u +#define CYREG_B0_P3_U0_PLD_IT6 0x40010618u +#define CYREG_B0_P3_U0_PLD_IT7 0x4001061cu +#define CYREG_B0_P3_U0_PLD_IT8 0x40010620u +#define CYREG_B0_P3_U0_PLD_IT9 0x40010624u +#define CYREG_B0_P3_U0_PLD_IT10 0x40010628u +#define CYREG_B0_P3_U0_PLD_IT11 0x4001062cu +#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630u +#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632u +#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634u +#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636u +#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u +#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063au +#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu +#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu +#define CYREG_B0_P3_U0_CFG0 0x40010640u +#define CYREG_B0_P3_U0_CFG1 0x40010641u +#define CYREG_B0_P3_U0_CFG2 0x40010642u +#define CYREG_B0_P3_U0_CFG3 0x40010643u +#define CYREG_B0_P3_U0_CFG4 0x40010644u +#define CYREG_B0_P3_U0_CFG5 0x40010645u +#define CYREG_B0_P3_U0_CFG6 0x40010646u +#define CYREG_B0_P3_U0_CFG7 0x40010647u +#define CYREG_B0_P3_U0_CFG8 0x40010648u +#define CYREG_B0_P3_U0_CFG9 0x40010649u +#define CYREG_B0_P3_U0_CFG10 0x4001064au +#define CYREG_B0_P3_U0_CFG11 0x4001064bu +#define CYREG_B0_P3_U0_CFG12 0x4001064cu +#define CYREG_B0_P3_U0_CFG13 0x4001064du +#define CYREG_B0_P3_U0_CFG14 0x4001064eu +#define CYREG_B0_P3_U0_CFG15 0x4001064fu +#define CYREG_B0_P3_U0_CFG16 0x40010650u +#define CYREG_B0_P3_U0_CFG17 0x40010651u +#define CYREG_B0_P3_U0_CFG18 0x40010652u +#define CYREG_B0_P3_U0_CFG19 0x40010653u +#define CYREG_B0_P3_U0_CFG20 0x40010654u +#define CYREG_B0_P3_U0_CFG21 0x40010655u +#define CYREG_B0_P3_U0_CFG22 0x40010656u +#define CYREG_B0_P3_U0_CFG23 0x40010657u +#define CYREG_B0_P3_U0_CFG24 0x40010658u +#define CYREG_B0_P3_U0_CFG25 0x40010659u +#define CYREG_B0_P3_U0_CFG26 0x4001065au +#define CYREG_B0_P3_U0_CFG27 0x4001065bu +#define CYREG_B0_P3_U0_CFG28 0x4001065cu +#define CYREG_B0_P3_U0_CFG29 0x4001065du +#define CYREG_B0_P3_U0_CFG30 0x4001065eu +#define CYREG_B0_P3_U0_CFG31 0x4001065fu +#define CYREG_B0_P3_U0_DCFG0 0x40010660u +#define CYREG_B0_P3_U0_DCFG1 0x40010662u +#define CYREG_B0_P3_U0_DCFG2 0x40010664u +#define CYREG_B0_P3_U0_DCFG3 0x40010666u +#define CYREG_B0_P3_U0_DCFG4 0x40010668u +#define CYREG_B0_P3_U0_DCFG5 0x4001066au +#define CYREG_B0_P3_U0_DCFG6 0x4001066cu +#define CYREG_B0_P3_U0_DCFG7 0x4001066eu +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u +#define CYREG_B0_P3_U1_PLD_IT0 0x40010680u +#define CYREG_B0_P3_U1_PLD_IT1 0x40010684u +#define CYREG_B0_P3_U1_PLD_IT2 0x40010688u +#define CYREG_B0_P3_U1_PLD_IT3 0x4001068cu +#define CYREG_B0_P3_U1_PLD_IT4 0x40010690u +#define CYREG_B0_P3_U1_PLD_IT5 0x40010694u +#define CYREG_B0_P3_U1_PLD_IT6 0x40010698u +#define CYREG_B0_P3_U1_PLD_IT7 0x4001069cu +#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0u +#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4u +#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8u +#define CYREG_B0_P3_U1_PLD_IT11 0x400106acu +#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0u +#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2u +#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4u +#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6u +#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u +#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106bau +#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu +#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu +#define CYREG_B0_P3_U1_CFG0 0x400106c0u +#define CYREG_B0_P3_U1_CFG1 0x400106c1u +#define CYREG_B0_P3_U1_CFG2 0x400106c2u +#define CYREG_B0_P3_U1_CFG3 0x400106c3u +#define CYREG_B0_P3_U1_CFG4 0x400106c4u +#define CYREG_B0_P3_U1_CFG5 0x400106c5u +#define CYREG_B0_P3_U1_CFG6 0x400106c6u +#define CYREG_B0_P3_U1_CFG7 0x400106c7u +#define CYREG_B0_P3_U1_CFG8 0x400106c8u +#define CYREG_B0_P3_U1_CFG9 0x400106c9u +#define CYREG_B0_P3_U1_CFG10 0x400106cau +#define CYREG_B0_P3_U1_CFG11 0x400106cbu +#define CYREG_B0_P3_U1_CFG12 0x400106ccu +#define CYREG_B0_P3_U1_CFG13 0x400106cdu +#define CYREG_B0_P3_U1_CFG14 0x400106ceu +#define CYREG_B0_P3_U1_CFG15 0x400106cfu +#define CYREG_B0_P3_U1_CFG16 0x400106d0u +#define CYREG_B0_P3_U1_CFG17 0x400106d1u +#define CYREG_B0_P3_U1_CFG18 0x400106d2u +#define CYREG_B0_P3_U1_CFG19 0x400106d3u +#define CYREG_B0_P3_U1_CFG20 0x400106d4u +#define CYREG_B0_P3_U1_CFG21 0x400106d5u +#define CYREG_B0_P3_U1_CFG22 0x400106d6u +#define CYREG_B0_P3_U1_CFG23 0x400106d7u +#define CYREG_B0_P3_U1_CFG24 0x400106d8u +#define CYREG_B0_P3_U1_CFG25 0x400106d9u +#define CYREG_B0_P3_U1_CFG26 0x400106dau +#define CYREG_B0_P3_U1_CFG27 0x400106dbu +#define CYREG_B0_P3_U1_CFG28 0x400106dcu +#define CYREG_B0_P3_U1_CFG29 0x400106ddu +#define CYREG_B0_P3_U1_CFG30 0x400106deu +#define CYREG_B0_P3_U1_CFG31 0x400106dfu +#define CYREG_B0_P3_U1_DCFG0 0x400106e0u +#define CYREG_B0_P3_U1_DCFG1 0x400106e2u +#define CYREG_B0_P3_U1_DCFG2 0x400106e4u +#define CYREG_B0_P3_U1_DCFG3 0x400106e6u +#define CYREG_B0_P3_U1_DCFG4 0x400106e8u +#define CYREG_B0_P3_U1_DCFG5 0x400106eau +#define CYREG_B0_P3_U1_DCFG6 0x400106ecu +#define CYREG_B0_P3_U1_DCFG7 0x400106eeu +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P4_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u +#define CYREG_B0_P4_U0_PLD_IT0 0x40010800u +#define CYREG_B0_P4_U0_PLD_IT1 0x40010804u +#define CYREG_B0_P4_U0_PLD_IT2 0x40010808u +#define CYREG_B0_P4_U0_PLD_IT3 0x4001080cu +#define CYREG_B0_P4_U0_PLD_IT4 0x40010810u +#define CYREG_B0_P4_U0_PLD_IT5 0x40010814u +#define CYREG_B0_P4_U0_PLD_IT6 0x40010818u +#define CYREG_B0_P4_U0_PLD_IT7 0x4001081cu +#define CYREG_B0_P4_U0_PLD_IT8 0x40010820u +#define CYREG_B0_P4_U0_PLD_IT9 0x40010824u +#define CYREG_B0_P4_U0_PLD_IT10 0x40010828u +#define CYREG_B0_P4_U0_PLD_IT11 0x4001082cu +#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830u +#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832u +#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834u +#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836u +#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u +#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083au +#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu +#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu +#define CYREG_B0_P4_U0_CFG0 0x40010840u +#define CYREG_B0_P4_U0_CFG1 0x40010841u +#define CYREG_B0_P4_U0_CFG2 0x40010842u +#define CYREG_B0_P4_U0_CFG3 0x40010843u +#define CYREG_B0_P4_U0_CFG4 0x40010844u +#define CYREG_B0_P4_U0_CFG5 0x40010845u +#define CYREG_B0_P4_U0_CFG6 0x40010846u +#define CYREG_B0_P4_U0_CFG7 0x40010847u +#define CYREG_B0_P4_U0_CFG8 0x40010848u +#define CYREG_B0_P4_U0_CFG9 0x40010849u +#define CYREG_B0_P4_U0_CFG10 0x4001084au +#define CYREG_B0_P4_U0_CFG11 0x4001084bu +#define CYREG_B0_P4_U0_CFG12 0x4001084cu +#define CYREG_B0_P4_U0_CFG13 0x4001084du +#define CYREG_B0_P4_U0_CFG14 0x4001084eu +#define CYREG_B0_P4_U0_CFG15 0x4001084fu +#define CYREG_B0_P4_U0_CFG16 0x40010850u +#define CYREG_B0_P4_U0_CFG17 0x40010851u +#define CYREG_B0_P4_U0_CFG18 0x40010852u +#define CYREG_B0_P4_U0_CFG19 0x40010853u +#define CYREG_B0_P4_U0_CFG20 0x40010854u +#define CYREG_B0_P4_U0_CFG21 0x40010855u +#define CYREG_B0_P4_U0_CFG22 0x40010856u +#define CYREG_B0_P4_U0_CFG23 0x40010857u +#define CYREG_B0_P4_U0_CFG24 0x40010858u +#define CYREG_B0_P4_U0_CFG25 0x40010859u +#define CYREG_B0_P4_U0_CFG26 0x4001085au +#define CYREG_B0_P4_U0_CFG27 0x4001085bu +#define CYREG_B0_P4_U0_CFG28 0x4001085cu +#define CYREG_B0_P4_U0_CFG29 0x4001085du +#define CYREG_B0_P4_U0_CFG30 0x4001085eu +#define CYREG_B0_P4_U0_CFG31 0x4001085fu +#define CYREG_B0_P4_U0_DCFG0 0x40010860u +#define CYREG_B0_P4_U0_DCFG1 0x40010862u +#define CYREG_B0_P4_U0_DCFG2 0x40010864u +#define CYREG_B0_P4_U0_DCFG3 0x40010866u +#define CYREG_B0_P4_U0_DCFG4 0x40010868u +#define CYREG_B0_P4_U0_DCFG5 0x4001086au +#define CYREG_B0_P4_U0_DCFG6 0x4001086cu +#define CYREG_B0_P4_U0_DCFG7 0x4001086eu +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u +#define CYREG_B0_P4_U1_PLD_IT0 0x40010880u +#define CYREG_B0_P4_U1_PLD_IT1 0x40010884u +#define CYREG_B0_P4_U1_PLD_IT2 0x40010888u +#define CYREG_B0_P4_U1_PLD_IT3 0x4001088cu +#define CYREG_B0_P4_U1_PLD_IT4 0x40010890u +#define CYREG_B0_P4_U1_PLD_IT5 0x40010894u +#define CYREG_B0_P4_U1_PLD_IT6 0x40010898u +#define CYREG_B0_P4_U1_PLD_IT7 0x4001089cu +#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0u +#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4u +#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8u +#define CYREG_B0_P4_U1_PLD_IT11 0x400108acu +#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0u +#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2u +#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4u +#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6u +#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u +#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108bau +#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu +#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu +#define CYREG_B0_P4_U1_CFG0 0x400108c0u +#define CYREG_B0_P4_U1_CFG1 0x400108c1u +#define CYREG_B0_P4_U1_CFG2 0x400108c2u +#define CYREG_B0_P4_U1_CFG3 0x400108c3u +#define CYREG_B0_P4_U1_CFG4 0x400108c4u +#define CYREG_B0_P4_U1_CFG5 0x400108c5u +#define CYREG_B0_P4_U1_CFG6 0x400108c6u +#define CYREG_B0_P4_U1_CFG7 0x400108c7u +#define CYREG_B0_P4_U1_CFG8 0x400108c8u +#define CYREG_B0_P4_U1_CFG9 0x400108c9u +#define CYREG_B0_P4_U1_CFG10 0x400108cau +#define CYREG_B0_P4_U1_CFG11 0x400108cbu +#define CYREG_B0_P4_U1_CFG12 0x400108ccu +#define CYREG_B0_P4_U1_CFG13 0x400108cdu +#define CYREG_B0_P4_U1_CFG14 0x400108ceu +#define CYREG_B0_P4_U1_CFG15 0x400108cfu +#define CYREG_B0_P4_U1_CFG16 0x400108d0u +#define CYREG_B0_P4_U1_CFG17 0x400108d1u +#define CYREG_B0_P4_U1_CFG18 0x400108d2u +#define CYREG_B0_P4_U1_CFG19 0x400108d3u +#define CYREG_B0_P4_U1_CFG20 0x400108d4u +#define CYREG_B0_P4_U1_CFG21 0x400108d5u +#define CYREG_B0_P4_U1_CFG22 0x400108d6u +#define CYREG_B0_P4_U1_CFG23 0x400108d7u +#define CYREG_B0_P4_U1_CFG24 0x400108d8u +#define CYREG_B0_P4_U1_CFG25 0x400108d9u +#define CYREG_B0_P4_U1_CFG26 0x400108dau +#define CYREG_B0_P4_U1_CFG27 0x400108dbu +#define CYREG_B0_P4_U1_CFG28 0x400108dcu +#define CYREG_B0_P4_U1_CFG29 0x400108ddu +#define CYREG_B0_P4_U1_CFG30 0x400108deu +#define CYREG_B0_P4_U1_CFG31 0x400108dfu +#define CYREG_B0_P4_U1_DCFG0 0x400108e0u +#define CYREG_B0_P4_U1_DCFG1 0x400108e2u +#define CYREG_B0_P4_U1_DCFG2 0x400108e4u +#define CYREG_B0_P4_U1_DCFG3 0x400108e6u +#define CYREG_B0_P4_U1_DCFG4 0x400108e8u +#define CYREG_B0_P4_U1_DCFG5 0x400108eau +#define CYREG_B0_P4_U1_DCFG6 0x400108ecu +#define CYREG_B0_P4_U1_DCFG7 0x400108eeu +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u +#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00u +#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04u +#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08u +#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0cu +#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10u +#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14u +#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18u +#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1cu +#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20u +#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24u +#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28u +#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2cu +#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30u +#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32u +#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34u +#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36u +#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u +#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au +#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu +#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu +#define CYREG_B0_P5_U0_CFG0 0x40010a40u +#define CYREG_B0_P5_U0_CFG1 0x40010a41u +#define CYREG_B0_P5_U0_CFG2 0x40010a42u +#define CYREG_B0_P5_U0_CFG3 0x40010a43u +#define CYREG_B0_P5_U0_CFG4 0x40010a44u +#define CYREG_B0_P5_U0_CFG5 0x40010a45u +#define CYREG_B0_P5_U0_CFG6 0x40010a46u +#define CYREG_B0_P5_U0_CFG7 0x40010a47u +#define CYREG_B0_P5_U0_CFG8 0x40010a48u +#define CYREG_B0_P5_U0_CFG9 0x40010a49u +#define CYREG_B0_P5_U0_CFG10 0x40010a4au +#define CYREG_B0_P5_U0_CFG11 0x40010a4bu +#define CYREG_B0_P5_U0_CFG12 0x40010a4cu +#define CYREG_B0_P5_U0_CFG13 0x40010a4du +#define CYREG_B0_P5_U0_CFG14 0x40010a4eu +#define CYREG_B0_P5_U0_CFG15 0x40010a4fu +#define CYREG_B0_P5_U0_CFG16 0x40010a50u +#define CYREG_B0_P5_U0_CFG17 0x40010a51u +#define CYREG_B0_P5_U0_CFG18 0x40010a52u +#define CYREG_B0_P5_U0_CFG19 0x40010a53u +#define CYREG_B0_P5_U0_CFG20 0x40010a54u +#define CYREG_B0_P5_U0_CFG21 0x40010a55u +#define CYREG_B0_P5_U0_CFG22 0x40010a56u +#define CYREG_B0_P5_U0_CFG23 0x40010a57u +#define CYREG_B0_P5_U0_CFG24 0x40010a58u +#define CYREG_B0_P5_U0_CFG25 0x40010a59u +#define CYREG_B0_P5_U0_CFG26 0x40010a5au +#define CYREG_B0_P5_U0_CFG27 0x40010a5bu +#define CYREG_B0_P5_U0_CFG28 0x40010a5cu +#define CYREG_B0_P5_U0_CFG29 0x40010a5du +#define CYREG_B0_P5_U0_CFG30 0x40010a5eu +#define CYREG_B0_P5_U0_CFG31 0x40010a5fu +#define CYREG_B0_P5_U0_DCFG0 0x40010a60u +#define CYREG_B0_P5_U0_DCFG1 0x40010a62u +#define CYREG_B0_P5_U0_DCFG2 0x40010a64u +#define CYREG_B0_P5_U0_DCFG3 0x40010a66u +#define CYREG_B0_P5_U0_DCFG4 0x40010a68u +#define CYREG_B0_P5_U0_DCFG5 0x40010a6au +#define CYREG_B0_P5_U0_DCFG6 0x40010a6cu +#define CYREG_B0_P5_U0_DCFG7 0x40010a6eu +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u +#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80u +#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84u +#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88u +#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8cu +#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90u +#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94u +#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98u +#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9cu +#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0u +#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4u +#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8u +#define CYREG_B0_P5_U1_PLD_IT11 0x40010aacu +#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0u +#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2u +#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4u +#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6u +#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u +#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010abau +#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu +#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu +#define CYREG_B0_P5_U1_CFG0 0x40010ac0u +#define CYREG_B0_P5_U1_CFG1 0x40010ac1u +#define CYREG_B0_P5_U1_CFG2 0x40010ac2u +#define CYREG_B0_P5_U1_CFG3 0x40010ac3u +#define CYREG_B0_P5_U1_CFG4 0x40010ac4u +#define CYREG_B0_P5_U1_CFG5 0x40010ac5u +#define CYREG_B0_P5_U1_CFG6 0x40010ac6u +#define CYREG_B0_P5_U1_CFG7 0x40010ac7u +#define CYREG_B0_P5_U1_CFG8 0x40010ac8u +#define CYREG_B0_P5_U1_CFG9 0x40010ac9u +#define CYREG_B0_P5_U1_CFG10 0x40010acau +#define CYREG_B0_P5_U1_CFG11 0x40010acbu +#define CYREG_B0_P5_U1_CFG12 0x40010accu +#define CYREG_B0_P5_U1_CFG13 0x40010acdu +#define CYREG_B0_P5_U1_CFG14 0x40010aceu +#define CYREG_B0_P5_U1_CFG15 0x40010acfu +#define CYREG_B0_P5_U1_CFG16 0x40010ad0u +#define CYREG_B0_P5_U1_CFG17 0x40010ad1u +#define CYREG_B0_P5_U1_CFG18 0x40010ad2u +#define CYREG_B0_P5_U1_CFG19 0x40010ad3u +#define CYREG_B0_P5_U1_CFG20 0x40010ad4u +#define CYREG_B0_P5_U1_CFG21 0x40010ad5u +#define CYREG_B0_P5_U1_CFG22 0x40010ad6u +#define CYREG_B0_P5_U1_CFG23 0x40010ad7u +#define CYREG_B0_P5_U1_CFG24 0x40010ad8u +#define CYREG_B0_P5_U1_CFG25 0x40010ad9u +#define CYREG_B0_P5_U1_CFG26 0x40010adau +#define CYREG_B0_P5_U1_CFG27 0x40010adbu +#define CYREG_B0_P5_U1_CFG28 0x40010adcu +#define CYREG_B0_P5_U1_CFG29 0x40010addu +#define CYREG_B0_P5_U1_CFG30 0x40010adeu +#define CYREG_B0_P5_U1_CFG31 0x40010adfu +#define CYREG_B0_P5_U1_DCFG0 0x40010ae0u +#define CYREG_B0_P5_U1_DCFG1 0x40010ae2u +#define CYREG_B0_P5_U1_DCFG2 0x40010ae4u +#define CYREG_B0_P5_U1_DCFG3 0x40010ae6u +#define CYREG_B0_P5_U1_DCFG4 0x40010ae8u +#define CYREG_B0_P5_U1_DCFG5 0x40010aeau +#define CYREG_B0_P5_U1_DCFG6 0x40010aecu +#define CYREG_B0_P5_U1_DCFG7 0x40010aeeu +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u +#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00u +#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04u +#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08u +#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0cu +#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10u +#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14u +#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18u +#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1cu +#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20u +#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24u +#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28u +#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2cu +#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30u +#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32u +#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34u +#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36u +#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u +#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au +#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu +#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu +#define CYREG_B0_P6_U0_CFG0 0x40010c40u +#define CYREG_B0_P6_U0_CFG1 0x40010c41u +#define CYREG_B0_P6_U0_CFG2 0x40010c42u +#define CYREG_B0_P6_U0_CFG3 0x40010c43u +#define CYREG_B0_P6_U0_CFG4 0x40010c44u +#define CYREG_B0_P6_U0_CFG5 0x40010c45u +#define CYREG_B0_P6_U0_CFG6 0x40010c46u +#define CYREG_B0_P6_U0_CFG7 0x40010c47u +#define CYREG_B0_P6_U0_CFG8 0x40010c48u +#define CYREG_B0_P6_U0_CFG9 0x40010c49u +#define CYREG_B0_P6_U0_CFG10 0x40010c4au +#define CYREG_B0_P6_U0_CFG11 0x40010c4bu +#define CYREG_B0_P6_U0_CFG12 0x40010c4cu +#define CYREG_B0_P6_U0_CFG13 0x40010c4du +#define CYREG_B0_P6_U0_CFG14 0x40010c4eu +#define CYREG_B0_P6_U0_CFG15 0x40010c4fu +#define CYREG_B0_P6_U0_CFG16 0x40010c50u +#define CYREG_B0_P6_U0_CFG17 0x40010c51u +#define CYREG_B0_P6_U0_CFG18 0x40010c52u +#define CYREG_B0_P6_U0_CFG19 0x40010c53u +#define CYREG_B0_P6_U0_CFG20 0x40010c54u +#define CYREG_B0_P6_U0_CFG21 0x40010c55u +#define CYREG_B0_P6_U0_CFG22 0x40010c56u +#define CYREG_B0_P6_U0_CFG23 0x40010c57u +#define CYREG_B0_P6_U0_CFG24 0x40010c58u +#define CYREG_B0_P6_U0_CFG25 0x40010c59u +#define CYREG_B0_P6_U0_CFG26 0x40010c5au +#define CYREG_B0_P6_U0_CFG27 0x40010c5bu +#define CYREG_B0_P6_U0_CFG28 0x40010c5cu +#define CYREG_B0_P6_U0_CFG29 0x40010c5du +#define CYREG_B0_P6_U0_CFG30 0x40010c5eu +#define CYREG_B0_P6_U0_CFG31 0x40010c5fu +#define CYREG_B0_P6_U0_DCFG0 0x40010c60u +#define CYREG_B0_P6_U0_DCFG1 0x40010c62u +#define CYREG_B0_P6_U0_DCFG2 0x40010c64u +#define CYREG_B0_P6_U0_DCFG3 0x40010c66u +#define CYREG_B0_P6_U0_DCFG4 0x40010c68u +#define CYREG_B0_P6_U0_DCFG5 0x40010c6au +#define CYREG_B0_P6_U0_DCFG6 0x40010c6cu +#define CYREG_B0_P6_U0_DCFG7 0x40010c6eu +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u +#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80u +#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84u +#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88u +#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8cu +#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90u +#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94u +#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98u +#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9cu +#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0u +#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4u +#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8u +#define CYREG_B0_P6_U1_PLD_IT11 0x40010cacu +#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0u +#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2u +#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4u +#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6u +#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u +#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau +#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu +#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu +#define CYREG_B0_P6_U1_CFG0 0x40010cc0u +#define CYREG_B0_P6_U1_CFG1 0x40010cc1u +#define CYREG_B0_P6_U1_CFG2 0x40010cc2u +#define CYREG_B0_P6_U1_CFG3 0x40010cc3u +#define CYREG_B0_P6_U1_CFG4 0x40010cc4u +#define CYREG_B0_P6_U1_CFG5 0x40010cc5u +#define CYREG_B0_P6_U1_CFG6 0x40010cc6u +#define CYREG_B0_P6_U1_CFG7 0x40010cc7u +#define CYREG_B0_P6_U1_CFG8 0x40010cc8u +#define CYREG_B0_P6_U1_CFG9 0x40010cc9u +#define CYREG_B0_P6_U1_CFG10 0x40010ccau +#define CYREG_B0_P6_U1_CFG11 0x40010ccbu +#define CYREG_B0_P6_U1_CFG12 0x40010cccu +#define CYREG_B0_P6_U1_CFG13 0x40010ccdu +#define CYREG_B0_P6_U1_CFG14 0x40010cceu +#define CYREG_B0_P6_U1_CFG15 0x40010ccfu +#define CYREG_B0_P6_U1_CFG16 0x40010cd0u +#define CYREG_B0_P6_U1_CFG17 0x40010cd1u +#define CYREG_B0_P6_U1_CFG18 0x40010cd2u +#define CYREG_B0_P6_U1_CFG19 0x40010cd3u +#define CYREG_B0_P6_U1_CFG20 0x40010cd4u +#define CYREG_B0_P6_U1_CFG21 0x40010cd5u +#define CYREG_B0_P6_U1_CFG22 0x40010cd6u +#define CYREG_B0_P6_U1_CFG23 0x40010cd7u +#define CYREG_B0_P6_U1_CFG24 0x40010cd8u +#define CYREG_B0_P6_U1_CFG25 0x40010cd9u +#define CYREG_B0_P6_U1_CFG26 0x40010cdau +#define CYREG_B0_P6_U1_CFG27 0x40010cdbu +#define CYREG_B0_P6_U1_CFG28 0x40010cdcu +#define CYREG_B0_P6_U1_CFG29 0x40010cddu +#define CYREG_B0_P6_U1_CFG30 0x40010cdeu +#define CYREG_B0_P6_U1_CFG31 0x40010cdfu +#define CYREG_B0_P6_U1_DCFG0 0x40010ce0u +#define CYREG_B0_P6_U1_DCFG1 0x40010ce2u +#define CYREG_B0_P6_U1_DCFG2 0x40010ce4u +#define CYREG_B0_P6_U1_DCFG3 0x40010ce6u +#define CYREG_B0_P6_U1_DCFG4 0x40010ce8u +#define CYREG_B0_P6_U1_DCFG5 0x40010ceau +#define CYREG_B0_P6_U1_DCFG6 0x40010cecu +#define CYREG_B0_P6_U1_DCFG7 0x40010ceeu +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u +#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00u +#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04u +#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08u +#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0cu +#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10u +#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14u +#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18u +#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1cu +#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20u +#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24u +#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28u +#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2cu +#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30u +#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32u +#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34u +#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36u +#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u +#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au +#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu +#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu +#define CYREG_B0_P7_U0_CFG0 0x40010e40u +#define CYREG_B0_P7_U0_CFG1 0x40010e41u +#define CYREG_B0_P7_U0_CFG2 0x40010e42u +#define CYREG_B0_P7_U0_CFG3 0x40010e43u +#define CYREG_B0_P7_U0_CFG4 0x40010e44u +#define CYREG_B0_P7_U0_CFG5 0x40010e45u +#define CYREG_B0_P7_U0_CFG6 0x40010e46u +#define CYREG_B0_P7_U0_CFG7 0x40010e47u +#define CYREG_B0_P7_U0_CFG8 0x40010e48u +#define CYREG_B0_P7_U0_CFG9 0x40010e49u +#define CYREG_B0_P7_U0_CFG10 0x40010e4au +#define CYREG_B0_P7_U0_CFG11 0x40010e4bu +#define CYREG_B0_P7_U0_CFG12 0x40010e4cu +#define CYREG_B0_P7_U0_CFG13 0x40010e4du +#define CYREG_B0_P7_U0_CFG14 0x40010e4eu +#define CYREG_B0_P7_U0_CFG15 0x40010e4fu +#define CYREG_B0_P7_U0_CFG16 0x40010e50u +#define CYREG_B0_P7_U0_CFG17 0x40010e51u +#define CYREG_B0_P7_U0_CFG18 0x40010e52u +#define CYREG_B0_P7_U0_CFG19 0x40010e53u +#define CYREG_B0_P7_U0_CFG20 0x40010e54u +#define CYREG_B0_P7_U0_CFG21 0x40010e55u +#define CYREG_B0_P7_U0_CFG22 0x40010e56u +#define CYREG_B0_P7_U0_CFG23 0x40010e57u +#define CYREG_B0_P7_U0_CFG24 0x40010e58u +#define CYREG_B0_P7_U0_CFG25 0x40010e59u +#define CYREG_B0_P7_U0_CFG26 0x40010e5au +#define CYREG_B0_P7_U0_CFG27 0x40010e5bu +#define CYREG_B0_P7_U0_CFG28 0x40010e5cu +#define CYREG_B0_P7_U0_CFG29 0x40010e5du +#define CYREG_B0_P7_U0_CFG30 0x40010e5eu +#define CYREG_B0_P7_U0_CFG31 0x40010e5fu +#define CYREG_B0_P7_U0_DCFG0 0x40010e60u +#define CYREG_B0_P7_U0_DCFG1 0x40010e62u +#define CYREG_B0_P7_U0_DCFG2 0x40010e64u +#define CYREG_B0_P7_U0_DCFG3 0x40010e66u +#define CYREG_B0_P7_U0_DCFG4 0x40010e68u +#define CYREG_B0_P7_U0_DCFG5 0x40010e6au +#define CYREG_B0_P7_U0_DCFG6 0x40010e6cu +#define CYREG_B0_P7_U0_DCFG7 0x40010e6eu +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u +#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80u +#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84u +#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88u +#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8cu +#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90u +#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94u +#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98u +#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9cu +#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0u +#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4u +#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8u +#define CYREG_B0_P7_U1_PLD_IT11 0x40010eacu +#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0u +#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2u +#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4u +#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6u +#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u +#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau +#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu +#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu +#define CYREG_B0_P7_U1_CFG0 0x40010ec0u +#define CYREG_B0_P7_U1_CFG1 0x40010ec1u +#define CYREG_B0_P7_U1_CFG2 0x40010ec2u +#define CYREG_B0_P7_U1_CFG3 0x40010ec3u +#define CYREG_B0_P7_U1_CFG4 0x40010ec4u +#define CYREG_B0_P7_U1_CFG5 0x40010ec5u +#define CYREG_B0_P7_U1_CFG6 0x40010ec6u +#define CYREG_B0_P7_U1_CFG7 0x40010ec7u +#define CYREG_B0_P7_U1_CFG8 0x40010ec8u +#define CYREG_B0_P7_U1_CFG9 0x40010ec9u +#define CYREG_B0_P7_U1_CFG10 0x40010ecau +#define CYREG_B0_P7_U1_CFG11 0x40010ecbu +#define CYREG_B0_P7_U1_CFG12 0x40010eccu +#define CYREG_B0_P7_U1_CFG13 0x40010ecdu +#define CYREG_B0_P7_U1_CFG14 0x40010eceu +#define CYREG_B0_P7_U1_CFG15 0x40010ecfu +#define CYREG_B0_P7_U1_CFG16 0x40010ed0u +#define CYREG_B0_P7_U1_CFG17 0x40010ed1u +#define CYREG_B0_P7_U1_CFG18 0x40010ed2u +#define CYREG_B0_P7_U1_CFG19 0x40010ed3u +#define CYREG_B0_P7_U1_CFG20 0x40010ed4u +#define CYREG_B0_P7_U1_CFG21 0x40010ed5u +#define CYREG_B0_P7_U1_CFG22 0x40010ed6u +#define CYREG_B0_P7_U1_CFG23 0x40010ed7u +#define CYREG_B0_P7_U1_CFG24 0x40010ed8u +#define CYREG_B0_P7_U1_CFG25 0x40010ed9u +#define CYREG_B0_P7_U1_CFG26 0x40010edau +#define CYREG_B0_P7_U1_CFG27 0x40010edbu +#define CYREG_B0_P7_U1_CFG28 0x40010edcu +#define CYREG_B0_P7_U1_CFG29 0x40010eddu +#define CYREG_B0_P7_U1_CFG30 0x40010edeu +#define CYREG_B0_P7_U1_CFG31 0x40010edfu +#define CYREG_B0_P7_U1_DCFG0 0x40010ee0u +#define CYREG_B0_P7_U1_DCFG1 0x40010ee2u +#define CYREG_B0_P7_U1_DCFG2 0x40010ee4u +#define CYREG_B0_P7_U1_DCFG3 0x40010ee6u +#define CYREG_B0_P7_U1_DCFG4 0x40010ee8u +#define CYREG_B0_P7_U1_DCFG5 0x40010eeau +#define CYREG_B0_P7_U1_DCFG6 0x40010eecu +#define CYREG_B0_P7_U1_DCFG7 0x40010eeeu +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_BASE 0x40011000u +#define CYDEV_UCFG_B1_SIZE 0x00000fefu +#define CYDEV_UCFG_B1_P2_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u +#define CYREG_B1_P2_U0_PLD_IT0 0x40011400u +#define CYREG_B1_P2_U0_PLD_IT1 0x40011404u +#define CYREG_B1_P2_U0_PLD_IT2 0x40011408u +#define CYREG_B1_P2_U0_PLD_IT3 0x4001140cu +#define CYREG_B1_P2_U0_PLD_IT4 0x40011410u +#define CYREG_B1_P2_U0_PLD_IT5 0x40011414u +#define CYREG_B1_P2_U0_PLD_IT6 0x40011418u +#define CYREG_B1_P2_U0_PLD_IT7 0x4001141cu +#define CYREG_B1_P2_U0_PLD_IT8 0x40011420u +#define CYREG_B1_P2_U0_PLD_IT9 0x40011424u +#define CYREG_B1_P2_U0_PLD_IT10 0x40011428u +#define CYREG_B1_P2_U0_PLD_IT11 0x4001142cu +#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430u +#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432u +#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434u +#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436u +#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u +#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143au +#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu +#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu +#define CYREG_B1_P2_U0_CFG0 0x40011440u +#define CYREG_B1_P2_U0_CFG1 0x40011441u +#define CYREG_B1_P2_U0_CFG2 0x40011442u +#define CYREG_B1_P2_U0_CFG3 0x40011443u +#define CYREG_B1_P2_U0_CFG4 0x40011444u +#define CYREG_B1_P2_U0_CFG5 0x40011445u +#define CYREG_B1_P2_U0_CFG6 0x40011446u +#define CYREG_B1_P2_U0_CFG7 0x40011447u +#define CYREG_B1_P2_U0_CFG8 0x40011448u +#define CYREG_B1_P2_U0_CFG9 0x40011449u +#define CYREG_B1_P2_U0_CFG10 0x4001144au +#define CYREG_B1_P2_U0_CFG11 0x4001144bu +#define CYREG_B1_P2_U0_CFG12 0x4001144cu +#define CYREG_B1_P2_U0_CFG13 0x4001144du +#define CYREG_B1_P2_U0_CFG14 0x4001144eu +#define CYREG_B1_P2_U0_CFG15 0x4001144fu +#define CYREG_B1_P2_U0_CFG16 0x40011450u +#define CYREG_B1_P2_U0_CFG17 0x40011451u +#define CYREG_B1_P2_U0_CFG18 0x40011452u +#define CYREG_B1_P2_U0_CFG19 0x40011453u +#define CYREG_B1_P2_U0_CFG20 0x40011454u +#define CYREG_B1_P2_U0_CFG21 0x40011455u +#define CYREG_B1_P2_U0_CFG22 0x40011456u +#define CYREG_B1_P2_U0_CFG23 0x40011457u +#define CYREG_B1_P2_U0_CFG24 0x40011458u +#define CYREG_B1_P2_U0_CFG25 0x40011459u +#define CYREG_B1_P2_U0_CFG26 0x4001145au +#define CYREG_B1_P2_U0_CFG27 0x4001145bu +#define CYREG_B1_P2_U0_CFG28 0x4001145cu +#define CYREG_B1_P2_U0_CFG29 0x4001145du +#define CYREG_B1_P2_U0_CFG30 0x4001145eu +#define CYREG_B1_P2_U0_CFG31 0x4001145fu +#define CYREG_B1_P2_U0_DCFG0 0x40011460u +#define CYREG_B1_P2_U0_DCFG1 0x40011462u +#define CYREG_B1_P2_U0_DCFG2 0x40011464u +#define CYREG_B1_P2_U0_DCFG3 0x40011466u +#define CYREG_B1_P2_U0_DCFG4 0x40011468u +#define CYREG_B1_P2_U0_DCFG5 0x4001146au +#define CYREG_B1_P2_U0_DCFG6 0x4001146cu +#define CYREG_B1_P2_U0_DCFG7 0x4001146eu +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u +#define CYREG_B1_P2_U1_PLD_IT0 0x40011480u +#define CYREG_B1_P2_U1_PLD_IT1 0x40011484u +#define CYREG_B1_P2_U1_PLD_IT2 0x40011488u +#define CYREG_B1_P2_U1_PLD_IT3 0x4001148cu +#define CYREG_B1_P2_U1_PLD_IT4 0x40011490u +#define CYREG_B1_P2_U1_PLD_IT5 0x40011494u +#define CYREG_B1_P2_U1_PLD_IT6 0x40011498u +#define CYREG_B1_P2_U1_PLD_IT7 0x4001149cu +#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0u +#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4u +#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8u +#define CYREG_B1_P2_U1_PLD_IT11 0x400114acu +#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0u +#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2u +#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4u +#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6u +#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u +#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114bau +#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu +#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu +#define CYREG_B1_P2_U1_CFG0 0x400114c0u +#define CYREG_B1_P2_U1_CFG1 0x400114c1u +#define CYREG_B1_P2_U1_CFG2 0x400114c2u +#define CYREG_B1_P2_U1_CFG3 0x400114c3u +#define CYREG_B1_P2_U1_CFG4 0x400114c4u +#define CYREG_B1_P2_U1_CFG5 0x400114c5u +#define CYREG_B1_P2_U1_CFG6 0x400114c6u +#define CYREG_B1_P2_U1_CFG7 0x400114c7u +#define CYREG_B1_P2_U1_CFG8 0x400114c8u +#define CYREG_B1_P2_U1_CFG9 0x400114c9u +#define CYREG_B1_P2_U1_CFG10 0x400114cau +#define CYREG_B1_P2_U1_CFG11 0x400114cbu +#define CYREG_B1_P2_U1_CFG12 0x400114ccu +#define CYREG_B1_P2_U1_CFG13 0x400114cdu +#define CYREG_B1_P2_U1_CFG14 0x400114ceu +#define CYREG_B1_P2_U1_CFG15 0x400114cfu +#define CYREG_B1_P2_U1_CFG16 0x400114d0u +#define CYREG_B1_P2_U1_CFG17 0x400114d1u +#define CYREG_B1_P2_U1_CFG18 0x400114d2u +#define CYREG_B1_P2_U1_CFG19 0x400114d3u +#define CYREG_B1_P2_U1_CFG20 0x400114d4u +#define CYREG_B1_P2_U1_CFG21 0x400114d5u +#define CYREG_B1_P2_U1_CFG22 0x400114d6u +#define CYREG_B1_P2_U1_CFG23 0x400114d7u +#define CYREG_B1_P2_U1_CFG24 0x400114d8u +#define CYREG_B1_P2_U1_CFG25 0x400114d9u +#define CYREG_B1_P2_U1_CFG26 0x400114dau +#define CYREG_B1_P2_U1_CFG27 0x400114dbu +#define CYREG_B1_P2_U1_CFG28 0x400114dcu +#define CYREG_B1_P2_U1_CFG29 0x400114ddu +#define CYREG_B1_P2_U1_CFG30 0x400114deu +#define CYREG_B1_P2_U1_CFG31 0x400114dfu +#define CYREG_B1_P2_U1_DCFG0 0x400114e0u +#define CYREG_B1_P2_U1_DCFG1 0x400114e2u +#define CYREG_B1_P2_U1_DCFG2 0x400114e4u +#define CYREG_B1_P2_U1_DCFG3 0x400114e6u +#define CYREG_B1_P2_U1_DCFG4 0x400114e8u +#define CYREG_B1_P2_U1_DCFG5 0x400114eau +#define CYREG_B1_P2_U1_DCFG6 0x400114ecu +#define CYREG_B1_P2_U1_DCFG7 0x400114eeu +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P3_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u +#define CYREG_B1_P3_U0_PLD_IT0 0x40011600u +#define CYREG_B1_P3_U0_PLD_IT1 0x40011604u +#define CYREG_B1_P3_U0_PLD_IT2 0x40011608u +#define CYREG_B1_P3_U0_PLD_IT3 0x4001160cu +#define CYREG_B1_P3_U0_PLD_IT4 0x40011610u +#define CYREG_B1_P3_U0_PLD_IT5 0x40011614u +#define CYREG_B1_P3_U0_PLD_IT6 0x40011618u +#define CYREG_B1_P3_U0_PLD_IT7 0x4001161cu +#define CYREG_B1_P3_U0_PLD_IT8 0x40011620u +#define CYREG_B1_P3_U0_PLD_IT9 0x40011624u +#define CYREG_B1_P3_U0_PLD_IT10 0x40011628u +#define CYREG_B1_P3_U0_PLD_IT11 0x4001162cu +#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630u +#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632u +#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634u +#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636u +#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u +#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163au +#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu +#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu +#define CYREG_B1_P3_U0_CFG0 0x40011640u +#define CYREG_B1_P3_U0_CFG1 0x40011641u +#define CYREG_B1_P3_U0_CFG2 0x40011642u +#define CYREG_B1_P3_U0_CFG3 0x40011643u +#define CYREG_B1_P3_U0_CFG4 0x40011644u +#define CYREG_B1_P3_U0_CFG5 0x40011645u +#define CYREG_B1_P3_U0_CFG6 0x40011646u +#define CYREG_B1_P3_U0_CFG7 0x40011647u +#define CYREG_B1_P3_U0_CFG8 0x40011648u +#define CYREG_B1_P3_U0_CFG9 0x40011649u +#define CYREG_B1_P3_U0_CFG10 0x4001164au +#define CYREG_B1_P3_U0_CFG11 0x4001164bu +#define CYREG_B1_P3_U0_CFG12 0x4001164cu +#define CYREG_B1_P3_U0_CFG13 0x4001164du +#define CYREG_B1_P3_U0_CFG14 0x4001164eu +#define CYREG_B1_P3_U0_CFG15 0x4001164fu +#define CYREG_B1_P3_U0_CFG16 0x40011650u +#define CYREG_B1_P3_U0_CFG17 0x40011651u +#define CYREG_B1_P3_U0_CFG18 0x40011652u +#define CYREG_B1_P3_U0_CFG19 0x40011653u +#define CYREG_B1_P3_U0_CFG20 0x40011654u +#define CYREG_B1_P3_U0_CFG21 0x40011655u +#define CYREG_B1_P3_U0_CFG22 0x40011656u +#define CYREG_B1_P3_U0_CFG23 0x40011657u +#define CYREG_B1_P3_U0_CFG24 0x40011658u +#define CYREG_B1_P3_U0_CFG25 0x40011659u +#define CYREG_B1_P3_U0_CFG26 0x4001165au +#define CYREG_B1_P3_U0_CFG27 0x4001165bu +#define CYREG_B1_P3_U0_CFG28 0x4001165cu +#define CYREG_B1_P3_U0_CFG29 0x4001165du +#define CYREG_B1_P3_U0_CFG30 0x4001165eu +#define CYREG_B1_P3_U0_CFG31 0x4001165fu +#define CYREG_B1_P3_U0_DCFG0 0x40011660u +#define CYREG_B1_P3_U0_DCFG1 0x40011662u +#define CYREG_B1_P3_U0_DCFG2 0x40011664u +#define CYREG_B1_P3_U0_DCFG3 0x40011666u +#define CYREG_B1_P3_U0_DCFG4 0x40011668u +#define CYREG_B1_P3_U0_DCFG5 0x4001166au +#define CYREG_B1_P3_U0_DCFG6 0x4001166cu +#define CYREG_B1_P3_U0_DCFG7 0x4001166eu +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u +#define CYREG_B1_P3_U1_PLD_IT0 0x40011680u +#define CYREG_B1_P3_U1_PLD_IT1 0x40011684u +#define CYREG_B1_P3_U1_PLD_IT2 0x40011688u +#define CYREG_B1_P3_U1_PLD_IT3 0x4001168cu +#define CYREG_B1_P3_U1_PLD_IT4 0x40011690u +#define CYREG_B1_P3_U1_PLD_IT5 0x40011694u +#define CYREG_B1_P3_U1_PLD_IT6 0x40011698u +#define CYREG_B1_P3_U1_PLD_IT7 0x4001169cu +#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0u +#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4u +#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8u +#define CYREG_B1_P3_U1_PLD_IT11 0x400116acu +#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0u +#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2u +#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4u +#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6u +#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u +#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116bau +#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu +#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu +#define CYREG_B1_P3_U1_CFG0 0x400116c0u +#define CYREG_B1_P3_U1_CFG1 0x400116c1u +#define CYREG_B1_P3_U1_CFG2 0x400116c2u +#define CYREG_B1_P3_U1_CFG3 0x400116c3u +#define CYREG_B1_P3_U1_CFG4 0x400116c4u +#define CYREG_B1_P3_U1_CFG5 0x400116c5u +#define CYREG_B1_P3_U1_CFG6 0x400116c6u +#define CYREG_B1_P3_U1_CFG7 0x400116c7u +#define CYREG_B1_P3_U1_CFG8 0x400116c8u +#define CYREG_B1_P3_U1_CFG9 0x400116c9u +#define CYREG_B1_P3_U1_CFG10 0x400116cau +#define CYREG_B1_P3_U1_CFG11 0x400116cbu +#define CYREG_B1_P3_U1_CFG12 0x400116ccu +#define CYREG_B1_P3_U1_CFG13 0x400116cdu +#define CYREG_B1_P3_U1_CFG14 0x400116ceu +#define CYREG_B1_P3_U1_CFG15 0x400116cfu +#define CYREG_B1_P3_U1_CFG16 0x400116d0u +#define CYREG_B1_P3_U1_CFG17 0x400116d1u +#define CYREG_B1_P3_U1_CFG18 0x400116d2u +#define CYREG_B1_P3_U1_CFG19 0x400116d3u +#define CYREG_B1_P3_U1_CFG20 0x400116d4u +#define CYREG_B1_P3_U1_CFG21 0x400116d5u +#define CYREG_B1_P3_U1_CFG22 0x400116d6u +#define CYREG_B1_P3_U1_CFG23 0x400116d7u +#define CYREG_B1_P3_U1_CFG24 0x400116d8u +#define CYREG_B1_P3_U1_CFG25 0x400116d9u +#define CYREG_B1_P3_U1_CFG26 0x400116dau +#define CYREG_B1_P3_U1_CFG27 0x400116dbu +#define CYREG_B1_P3_U1_CFG28 0x400116dcu +#define CYREG_B1_P3_U1_CFG29 0x400116ddu +#define CYREG_B1_P3_U1_CFG30 0x400116deu +#define CYREG_B1_P3_U1_CFG31 0x400116dfu +#define CYREG_B1_P3_U1_DCFG0 0x400116e0u +#define CYREG_B1_P3_U1_DCFG1 0x400116e2u +#define CYREG_B1_P3_U1_DCFG2 0x400116e4u +#define CYREG_B1_P3_U1_DCFG3 0x400116e6u +#define CYREG_B1_P3_U1_DCFG4 0x400116e8u +#define CYREG_B1_P3_U1_DCFG5 0x400116eau +#define CYREG_B1_P3_U1_DCFG6 0x400116ecu +#define CYREG_B1_P3_U1_DCFG7 0x400116eeu +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P4_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u +#define CYREG_B1_P4_U0_PLD_IT0 0x40011800u +#define CYREG_B1_P4_U0_PLD_IT1 0x40011804u +#define CYREG_B1_P4_U0_PLD_IT2 0x40011808u +#define CYREG_B1_P4_U0_PLD_IT3 0x4001180cu +#define CYREG_B1_P4_U0_PLD_IT4 0x40011810u +#define CYREG_B1_P4_U0_PLD_IT5 0x40011814u +#define CYREG_B1_P4_U0_PLD_IT6 0x40011818u +#define CYREG_B1_P4_U0_PLD_IT7 0x4001181cu +#define CYREG_B1_P4_U0_PLD_IT8 0x40011820u +#define CYREG_B1_P4_U0_PLD_IT9 0x40011824u +#define CYREG_B1_P4_U0_PLD_IT10 0x40011828u +#define CYREG_B1_P4_U0_PLD_IT11 0x4001182cu +#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830u +#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832u +#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834u +#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836u +#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u +#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183au +#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu +#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu +#define CYREG_B1_P4_U0_CFG0 0x40011840u +#define CYREG_B1_P4_U0_CFG1 0x40011841u +#define CYREG_B1_P4_U0_CFG2 0x40011842u +#define CYREG_B1_P4_U0_CFG3 0x40011843u +#define CYREG_B1_P4_U0_CFG4 0x40011844u +#define CYREG_B1_P4_U0_CFG5 0x40011845u +#define CYREG_B1_P4_U0_CFG6 0x40011846u +#define CYREG_B1_P4_U0_CFG7 0x40011847u +#define CYREG_B1_P4_U0_CFG8 0x40011848u +#define CYREG_B1_P4_U0_CFG9 0x40011849u +#define CYREG_B1_P4_U0_CFG10 0x4001184au +#define CYREG_B1_P4_U0_CFG11 0x4001184bu +#define CYREG_B1_P4_U0_CFG12 0x4001184cu +#define CYREG_B1_P4_U0_CFG13 0x4001184du +#define CYREG_B1_P4_U0_CFG14 0x4001184eu +#define CYREG_B1_P4_U0_CFG15 0x4001184fu +#define CYREG_B1_P4_U0_CFG16 0x40011850u +#define CYREG_B1_P4_U0_CFG17 0x40011851u +#define CYREG_B1_P4_U0_CFG18 0x40011852u +#define CYREG_B1_P4_U0_CFG19 0x40011853u +#define CYREG_B1_P4_U0_CFG20 0x40011854u +#define CYREG_B1_P4_U0_CFG21 0x40011855u +#define CYREG_B1_P4_U0_CFG22 0x40011856u +#define CYREG_B1_P4_U0_CFG23 0x40011857u +#define CYREG_B1_P4_U0_CFG24 0x40011858u +#define CYREG_B1_P4_U0_CFG25 0x40011859u +#define CYREG_B1_P4_U0_CFG26 0x4001185au +#define CYREG_B1_P4_U0_CFG27 0x4001185bu +#define CYREG_B1_P4_U0_CFG28 0x4001185cu +#define CYREG_B1_P4_U0_CFG29 0x4001185du +#define CYREG_B1_P4_U0_CFG30 0x4001185eu +#define CYREG_B1_P4_U0_CFG31 0x4001185fu +#define CYREG_B1_P4_U0_DCFG0 0x40011860u +#define CYREG_B1_P4_U0_DCFG1 0x40011862u +#define CYREG_B1_P4_U0_DCFG2 0x40011864u +#define CYREG_B1_P4_U0_DCFG3 0x40011866u +#define CYREG_B1_P4_U0_DCFG4 0x40011868u +#define CYREG_B1_P4_U0_DCFG5 0x4001186au +#define CYREG_B1_P4_U0_DCFG6 0x4001186cu +#define CYREG_B1_P4_U0_DCFG7 0x4001186eu +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u +#define CYREG_B1_P4_U1_PLD_IT0 0x40011880u +#define CYREG_B1_P4_U1_PLD_IT1 0x40011884u +#define CYREG_B1_P4_U1_PLD_IT2 0x40011888u +#define CYREG_B1_P4_U1_PLD_IT3 0x4001188cu +#define CYREG_B1_P4_U1_PLD_IT4 0x40011890u +#define CYREG_B1_P4_U1_PLD_IT5 0x40011894u +#define CYREG_B1_P4_U1_PLD_IT6 0x40011898u +#define CYREG_B1_P4_U1_PLD_IT7 0x4001189cu +#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0u +#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4u +#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8u +#define CYREG_B1_P4_U1_PLD_IT11 0x400118acu +#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0u +#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2u +#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4u +#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6u +#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u +#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118bau +#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu +#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu +#define CYREG_B1_P4_U1_CFG0 0x400118c0u +#define CYREG_B1_P4_U1_CFG1 0x400118c1u +#define CYREG_B1_P4_U1_CFG2 0x400118c2u +#define CYREG_B1_P4_U1_CFG3 0x400118c3u +#define CYREG_B1_P4_U1_CFG4 0x400118c4u +#define CYREG_B1_P4_U1_CFG5 0x400118c5u +#define CYREG_B1_P4_U1_CFG6 0x400118c6u +#define CYREG_B1_P4_U1_CFG7 0x400118c7u +#define CYREG_B1_P4_U1_CFG8 0x400118c8u +#define CYREG_B1_P4_U1_CFG9 0x400118c9u +#define CYREG_B1_P4_U1_CFG10 0x400118cau +#define CYREG_B1_P4_U1_CFG11 0x400118cbu +#define CYREG_B1_P4_U1_CFG12 0x400118ccu +#define CYREG_B1_P4_U1_CFG13 0x400118cdu +#define CYREG_B1_P4_U1_CFG14 0x400118ceu +#define CYREG_B1_P4_U1_CFG15 0x400118cfu +#define CYREG_B1_P4_U1_CFG16 0x400118d0u +#define CYREG_B1_P4_U1_CFG17 0x400118d1u +#define CYREG_B1_P4_U1_CFG18 0x400118d2u +#define CYREG_B1_P4_U1_CFG19 0x400118d3u +#define CYREG_B1_P4_U1_CFG20 0x400118d4u +#define CYREG_B1_P4_U1_CFG21 0x400118d5u +#define CYREG_B1_P4_U1_CFG22 0x400118d6u +#define CYREG_B1_P4_U1_CFG23 0x400118d7u +#define CYREG_B1_P4_U1_CFG24 0x400118d8u +#define CYREG_B1_P4_U1_CFG25 0x400118d9u +#define CYREG_B1_P4_U1_CFG26 0x400118dau +#define CYREG_B1_P4_U1_CFG27 0x400118dbu +#define CYREG_B1_P4_U1_CFG28 0x400118dcu +#define CYREG_B1_P4_U1_CFG29 0x400118ddu +#define CYREG_B1_P4_U1_CFG30 0x400118deu +#define CYREG_B1_P4_U1_CFG31 0x400118dfu +#define CYREG_B1_P4_U1_DCFG0 0x400118e0u +#define CYREG_B1_P4_U1_DCFG1 0x400118e2u +#define CYREG_B1_P4_U1_DCFG2 0x400118e4u +#define CYREG_B1_P4_U1_DCFG3 0x400118e6u +#define CYREG_B1_P4_U1_DCFG4 0x400118e8u +#define CYREG_B1_P4_U1_DCFG5 0x400118eau +#define CYREG_B1_P4_U1_DCFG6 0x400118ecu +#define CYREG_B1_P4_U1_DCFG7 0x400118eeu +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u +#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00u +#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04u +#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08u +#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0cu +#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10u +#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14u +#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18u +#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1cu +#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20u +#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24u +#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28u +#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2cu +#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30u +#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32u +#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34u +#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36u +#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u +#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au +#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu +#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu +#define CYREG_B1_P5_U0_CFG0 0x40011a40u +#define CYREG_B1_P5_U0_CFG1 0x40011a41u +#define CYREG_B1_P5_U0_CFG2 0x40011a42u +#define CYREG_B1_P5_U0_CFG3 0x40011a43u +#define CYREG_B1_P5_U0_CFG4 0x40011a44u +#define CYREG_B1_P5_U0_CFG5 0x40011a45u +#define CYREG_B1_P5_U0_CFG6 0x40011a46u +#define CYREG_B1_P5_U0_CFG7 0x40011a47u +#define CYREG_B1_P5_U0_CFG8 0x40011a48u +#define CYREG_B1_P5_U0_CFG9 0x40011a49u +#define CYREG_B1_P5_U0_CFG10 0x40011a4au +#define CYREG_B1_P5_U0_CFG11 0x40011a4bu +#define CYREG_B1_P5_U0_CFG12 0x40011a4cu +#define CYREG_B1_P5_U0_CFG13 0x40011a4du +#define CYREG_B1_P5_U0_CFG14 0x40011a4eu +#define CYREG_B1_P5_U0_CFG15 0x40011a4fu +#define CYREG_B1_P5_U0_CFG16 0x40011a50u +#define CYREG_B1_P5_U0_CFG17 0x40011a51u +#define CYREG_B1_P5_U0_CFG18 0x40011a52u +#define CYREG_B1_P5_U0_CFG19 0x40011a53u +#define CYREG_B1_P5_U0_CFG20 0x40011a54u +#define CYREG_B1_P5_U0_CFG21 0x40011a55u +#define CYREG_B1_P5_U0_CFG22 0x40011a56u +#define CYREG_B1_P5_U0_CFG23 0x40011a57u +#define CYREG_B1_P5_U0_CFG24 0x40011a58u +#define CYREG_B1_P5_U0_CFG25 0x40011a59u +#define CYREG_B1_P5_U0_CFG26 0x40011a5au +#define CYREG_B1_P5_U0_CFG27 0x40011a5bu +#define CYREG_B1_P5_U0_CFG28 0x40011a5cu +#define CYREG_B1_P5_U0_CFG29 0x40011a5du +#define CYREG_B1_P5_U0_CFG30 0x40011a5eu +#define CYREG_B1_P5_U0_CFG31 0x40011a5fu +#define CYREG_B1_P5_U0_DCFG0 0x40011a60u +#define CYREG_B1_P5_U0_DCFG1 0x40011a62u +#define CYREG_B1_P5_U0_DCFG2 0x40011a64u +#define CYREG_B1_P5_U0_DCFG3 0x40011a66u +#define CYREG_B1_P5_U0_DCFG4 0x40011a68u +#define CYREG_B1_P5_U0_DCFG5 0x40011a6au +#define CYREG_B1_P5_U0_DCFG6 0x40011a6cu +#define CYREG_B1_P5_U0_DCFG7 0x40011a6eu +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u +#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80u +#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84u +#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88u +#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8cu +#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90u +#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94u +#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98u +#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9cu +#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0u +#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4u +#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8u +#define CYREG_B1_P5_U1_PLD_IT11 0x40011aacu +#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0u +#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2u +#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4u +#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6u +#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u +#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011abau +#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu +#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu +#define CYREG_B1_P5_U1_CFG0 0x40011ac0u +#define CYREG_B1_P5_U1_CFG1 0x40011ac1u +#define CYREG_B1_P5_U1_CFG2 0x40011ac2u +#define CYREG_B1_P5_U1_CFG3 0x40011ac3u +#define CYREG_B1_P5_U1_CFG4 0x40011ac4u +#define CYREG_B1_P5_U1_CFG5 0x40011ac5u +#define CYREG_B1_P5_U1_CFG6 0x40011ac6u +#define CYREG_B1_P5_U1_CFG7 0x40011ac7u +#define CYREG_B1_P5_U1_CFG8 0x40011ac8u +#define CYREG_B1_P5_U1_CFG9 0x40011ac9u +#define CYREG_B1_P5_U1_CFG10 0x40011acau +#define CYREG_B1_P5_U1_CFG11 0x40011acbu +#define CYREG_B1_P5_U1_CFG12 0x40011accu +#define CYREG_B1_P5_U1_CFG13 0x40011acdu +#define CYREG_B1_P5_U1_CFG14 0x40011aceu +#define CYREG_B1_P5_U1_CFG15 0x40011acfu +#define CYREG_B1_P5_U1_CFG16 0x40011ad0u +#define CYREG_B1_P5_U1_CFG17 0x40011ad1u +#define CYREG_B1_P5_U1_CFG18 0x40011ad2u +#define CYREG_B1_P5_U1_CFG19 0x40011ad3u +#define CYREG_B1_P5_U1_CFG20 0x40011ad4u +#define CYREG_B1_P5_U1_CFG21 0x40011ad5u +#define CYREG_B1_P5_U1_CFG22 0x40011ad6u +#define CYREG_B1_P5_U1_CFG23 0x40011ad7u +#define CYREG_B1_P5_U1_CFG24 0x40011ad8u +#define CYREG_B1_P5_U1_CFG25 0x40011ad9u +#define CYREG_B1_P5_U1_CFG26 0x40011adau +#define CYREG_B1_P5_U1_CFG27 0x40011adbu +#define CYREG_B1_P5_U1_CFG28 0x40011adcu +#define CYREG_B1_P5_U1_CFG29 0x40011addu +#define CYREG_B1_P5_U1_CFG30 0x40011adeu +#define CYREG_B1_P5_U1_CFG31 0x40011adfu +#define CYREG_B1_P5_U1_DCFG0 0x40011ae0u +#define CYREG_B1_P5_U1_DCFG1 0x40011ae2u +#define CYREG_B1_P5_U1_DCFG2 0x40011ae4u +#define CYREG_B1_P5_U1_DCFG3 0x40011ae6u +#define CYREG_B1_P5_U1_DCFG4 0x40011ae8u +#define CYREG_B1_P5_U1_DCFG5 0x40011aeau +#define CYREG_B1_P5_U1_DCFG6 0x40011aecu +#define CYREG_B1_P5_U1_DCFG7 0x40011aeeu +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_DSI0_BASE 0x40014000u +#define CYDEV_UCFG_DSI0_SIZE 0x000000efu +#define CYDEV_UCFG_DSI1_BASE 0x40014100u +#define CYDEV_UCFG_DSI1_SIZE 0x000000efu +#define CYDEV_UCFG_DSI2_BASE 0x40014200u +#define CYDEV_UCFG_DSI2_SIZE 0x000000efu +#define CYDEV_UCFG_DSI3_BASE 0x40014300u +#define CYDEV_UCFG_DSI3_SIZE 0x000000efu +#define CYDEV_UCFG_DSI4_BASE 0x40014400u +#define CYDEV_UCFG_DSI4_SIZE 0x000000efu +#define CYDEV_UCFG_DSI5_BASE 0x40014500u +#define CYDEV_UCFG_DSI5_SIZE 0x000000efu +#define CYDEV_UCFG_DSI6_BASE 0x40014600u +#define CYDEV_UCFG_DSI6_SIZE 0x000000efu +#define CYDEV_UCFG_DSI7_BASE 0x40014700u +#define CYDEV_UCFG_DSI7_SIZE 0x000000efu +#define CYDEV_UCFG_DSI8_BASE 0x40014800u +#define CYDEV_UCFG_DSI8_SIZE 0x000000efu +#define CYDEV_UCFG_DSI9_BASE 0x40014900u +#define CYDEV_UCFG_DSI9_SIZE 0x000000efu +#define CYDEV_UCFG_DSI12_BASE 0x40014c00u +#define CYDEV_UCFG_DSI12_SIZE 0x000000efu +#define CYDEV_UCFG_DSI13_BASE 0x40014d00u +#define CYDEV_UCFG_DSI13_SIZE 0x000000efu +#define CYDEV_UCFG_BCTL0_BASE 0x40015000u +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u +#define CYREG_BCTL0_MDCLK_EN 0x40015000u +#define CYREG_BCTL0_MBCLK_EN 0x40015001u +#define CYREG_BCTL0_WAIT_CFG 0x40015002u +#define CYREG_BCTL0_BANK_CTL 0x40015003u +#define CYREG_BCTL0_UDB_TEST_3 0x40015007u +#define CYREG_BCTL0_DCLK_EN0 0x40015008u +#define CYREG_BCTL0_BCLK_EN0 0x40015009u +#define CYREG_BCTL0_DCLK_EN1 0x4001500au +#define CYREG_BCTL0_BCLK_EN1 0x4001500bu +#define CYREG_BCTL0_DCLK_EN2 0x4001500cu +#define CYREG_BCTL0_BCLK_EN2 0x4001500du +#define CYREG_BCTL0_DCLK_EN3 0x4001500eu +#define CYREG_BCTL0_BCLK_EN3 0x4001500fu +#define CYDEV_UCFG_BCTL1_BASE 0x40015010u +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u +#define CYREG_BCTL1_MDCLK_EN 0x40015010u +#define CYREG_BCTL1_MBCLK_EN 0x40015011u +#define CYREG_BCTL1_WAIT_CFG 0x40015012u +#define CYREG_BCTL1_BANK_CTL 0x40015013u +#define CYREG_BCTL1_UDB_TEST_3 0x40015017u +#define CYREG_BCTL1_DCLK_EN0 0x40015018u +#define CYREG_BCTL1_BCLK_EN0 0x40015019u +#define CYREG_BCTL1_DCLK_EN1 0x4001501au +#define CYREG_BCTL1_BCLK_EN1 0x4001501bu +#define CYREG_BCTL1_DCLK_EN2 0x4001501cu +#define CYREG_BCTL1_BCLK_EN2 0x4001501du +#define CYREG_BCTL1_DCLK_EN3 0x4001501eu +#define CYREG_BCTL1_BCLK_EN3 0x4001501fu +#define CYDEV_IDMUX_BASE 0x40015100u +#define CYDEV_IDMUX_SIZE 0x00000016u +#define CYREG_IDMUX_IRQ_CTL0 0x40015100u +#define CYREG_IDMUX_IRQ_CTL1 0x40015101u +#define CYREG_IDMUX_IRQ_CTL2 0x40015102u +#define CYREG_IDMUX_IRQ_CTL3 0x40015103u +#define CYREG_IDMUX_IRQ_CTL4 0x40015104u +#define CYREG_IDMUX_IRQ_CTL5 0x40015105u +#define CYREG_IDMUX_IRQ_CTL6 0x40015106u +#define CYREG_IDMUX_IRQ_CTL7 0x40015107u +#define CYREG_IDMUX_DRQ_CTL0 0x40015110u +#define CYREG_IDMUX_DRQ_CTL1 0x40015111u +#define CYREG_IDMUX_DRQ_CTL2 0x40015112u +#define CYREG_IDMUX_DRQ_CTL3 0x40015113u +#define CYREG_IDMUX_DRQ_CTL4 0x40015114u +#define CYREG_IDMUX_DRQ_CTL5 0x40015115u +#define CYDEV_CACHERAM_BASE 0x40030000u +#define CYDEV_CACHERAM_SIZE 0x00000400u +#define CYREG_CACHERAM_DATA_MBASE 0x40030000u +#define CYREG_CACHERAM_DATA_MSIZE 0x00000400u +#define CYDEV_SFR_BASE 0x40050100u +#define CYDEV_SFR_SIZE 0x000000fbu +#define CYREG_SFR_GPIO0 0x40050180u +#define CYREG_SFR_GPIRD0 0x40050189u +#define CYREG_SFR_GPIO0_SEL 0x4005018au +#define CYREG_SFR_GPIO1 0x40050190u +#define CYREG_SFR_GPIRD1 0x40050191u +#define CYREG_SFR_GPIO2 0x40050198u +#define CYREG_SFR_GPIRD2 0x40050199u +#define CYREG_SFR_GPIO2_SEL 0x4005019au +#define CYREG_SFR_GPIO1_SEL 0x400501a2u +#define CYREG_SFR_GPIO3 0x400501b0u +#define CYREG_SFR_GPIRD3 0x400501b1u +#define CYREG_SFR_GPIO3_SEL 0x400501b2u +#define CYREG_SFR_GPIO4 0x400501c0u +#define CYREG_SFR_GPIRD4 0x400501c1u +#define CYREG_SFR_GPIO4_SEL 0x400501c2u +#define CYREG_SFR_GPIO5 0x400501c8u +#define CYREG_SFR_GPIRD5 0x400501c9u +#define CYREG_SFR_GPIO5_SEL 0x400501cau +#define CYREG_SFR_GPIO6 0x400501d8u +#define CYREG_SFR_GPIRD6 0x400501d9u +#define CYREG_SFR_GPIO6_SEL 0x400501dau +#define CYREG_SFR_GPIO12 0x400501e8u +#define CYREG_SFR_GPIRD12 0x400501e9u +#define CYREG_SFR_GPIO12_SEL 0x400501f2u +#define CYREG_SFR_GPIO15 0x400501f8u +#define CYREG_SFR_GPIRD15 0x400501f9u +#define CYREG_SFR_GPIO15_SEL 0x400501fau +#define CYDEV_P3BA_BASE 0x40050300u +#define CYDEV_P3BA_SIZE 0x0000002bu +#define CYREG_P3BA_Y_START 0x40050300u +#define CYREG_P3BA_YROLL 0x40050301u +#define CYREG_P3BA_YCFG 0x40050302u +#define CYREG_P3BA_X_START1 0x40050303u +#define CYREG_P3BA_X_START2 0x40050304u +#define CYREG_P3BA_XROLL1 0x40050305u +#define CYREG_P3BA_XROLL2 0x40050306u +#define CYREG_P3BA_XINC 0x40050307u +#define CYREG_P3BA_XCFG 0x40050308u +#define CYREG_P3BA_OFFSETADDR1 0x40050309u +#define CYREG_P3BA_OFFSETADDR2 0x4005030au +#define CYREG_P3BA_OFFSETADDR3 0x4005030bu +#define CYREG_P3BA_ABSADDR1 0x4005030cu +#define CYREG_P3BA_ABSADDR2 0x4005030du +#define CYREG_P3BA_ABSADDR3 0x4005030eu +#define CYREG_P3BA_ABSADDR4 0x4005030fu +#define CYREG_P3BA_DATCFG1 0x40050310u +#define CYREG_P3BA_DATCFG2 0x40050311u +#define CYREG_P3BA_CMP_RSLT1 0x40050314u +#define CYREG_P3BA_CMP_RSLT2 0x40050315u +#define CYREG_P3BA_CMP_RSLT3 0x40050316u +#define CYREG_P3BA_CMP_RSLT4 0x40050317u +#define CYREG_P3BA_DATA_REG1 0x40050318u +#define CYREG_P3BA_DATA_REG2 0x40050319u +#define CYREG_P3BA_DATA_REG3 0x4005031au +#define CYREG_P3BA_DATA_REG4 0x4005031bu +#define CYREG_P3BA_EXP_DATA1 0x4005031cu +#define CYREG_P3BA_EXP_DATA2 0x4005031du +#define CYREG_P3BA_EXP_DATA3 0x4005031eu +#define CYREG_P3BA_EXP_DATA4 0x4005031fu +#define CYREG_P3BA_MSTR_HRDATA1 0x40050320u +#define CYREG_P3BA_MSTR_HRDATA2 0x40050321u +#define CYREG_P3BA_MSTR_HRDATA3 0x40050322u +#define CYREG_P3BA_MSTR_HRDATA4 0x40050323u +#define CYREG_P3BA_BIST_EN 0x40050324u +#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325u +#define CYREG_P3BA_SEQCFG1 0x40050326u +#define CYREG_P3BA_SEQCFG2 0x40050327u +#define CYREG_P3BA_Y_CURR 0x40050328u +#define CYREG_P3BA_X_CURR1 0x40050329u +#define CYREG_P3BA_X_CURR2 0x4005032au +#define CYDEV_PANTHER_BASE 0x40080000u +#define CYDEV_PANTHER_SIZE 0x00000020u +#define CYREG_PANTHER_STCALIB_CFG 0x40080000u +#define CYREG_PANTHER_WAITPIPE 0x40080004u +#define CYREG_PANTHER_TRACE_CFG 0x40080008u +#define CYREG_PANTHER_DBG_CFG 0x4008000cu +#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018u +#define CYREG_PANTHER_DEVICE_ID 0x4008001cu +#define CYDEV_FLSECC_BASE 0x48000000u +#define CYDEV_FLSECC_SIZE 0x00008000u +#define CYREG_FLSECC_DATA_MBASE 0x48000000u +#define CYREG_FLSECC_DATA_MSIZE 0x00008000u +#define CYDEV_FLSHID_BASE 0x49000000u +#define CYDEV_FLSHID_SIZE 0x00000200u +#define CYREG_FLSHID_RSVD_MBASE 0x49000000u +#define CYREG_FLSHID_RSVD_MSIZE 0x00000080u +#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080u +#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u +#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100u +#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101u +#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u +#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u +#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u +#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105u +#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106u +#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107u +#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u +#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u +#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au +#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu +#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu +#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du +#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu +#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u +#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118u +#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119u +#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011au +#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu +#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu +#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011du +#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu +#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu +#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au +#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du +#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu +#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au +#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du +#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u +#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188u +#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu +#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu +#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u +#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u +#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u +#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u +#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u +#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau +#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu +#define CYDEV_EXTMEM_BASE 0x60000000u +#define CYDEV_EXTMEM_SIZE 0x00800000u +#define CYREG_EXTMEM_DATA_MBASE 0x60000000u +#define CYREG_EXTMEM_DATA_MSIZE 0x00800000u +#define CYDEV_ITM_BASE 0xe0000000u +#define CYDEV_ITM_SIZE 0x00001000u +#define CYREG_ITM_TRACE_EN 0xe0000e00u +#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40u +#define CYREG_ITM_TRACE_CTRL 0xe0000e80u +#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0u +#define CYREG_ITM_LOCK_STATUS 0xe0000fb4u +#define CYREG_ITM_PID4 0xe0000fd0u +#define CYREG_ITM_PID5 0xe0000fd4u +#define CYREG_ITM_PID6 0xe0000fd8u +#define CYREG_ITM_PID7 0xe0000fdcu +#define CYREG_ITM_PID0 0xe0000fe0u +#define CYREG_ITM_PID1 0xe0000fe4u +#define CYREG_ITM_PID2 0xe0000fe8u +#define CYREG_ITM_PID3 0xe0000fecu +#define CYREG_ITM_CID0 0xe0000ff0u +#define CYREG_ITM_CID1 0xe0000ff4u +#define CYREG_ITM_CID2 0xe0000ff8u +#define CYREG_ITM_CID3 0xe0000ffcu +#define CYDEV_DWT_BASE 0xe0001000u +#define CYDEV_DWT_SIZE 0x0000005cu +#define CYREG_DWT_CTRL 0xe0001000u +#define CYREG_DWT_CYCLE_COUNT 0xe0001004u +#define CYREG_DWT_CPI_COUNT 0xe0001008u +#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100cu +#define CYREG_DWT_SLEEP_COUNT 0xe0001010u +#define CYREG_DWT_LSU_COUNT 0xe0001014u +#define CYREG_DWT_FOLD_COUNT 0xe0001018u +#define CYREG_DWT_PC_SAMPLE 0xe000101cu +#define CYREG_DWT_COMP_0 0xe0001020u +#define CYREG_DWT_MASK_0 0xe0001024u +#define CYREG_DWT_FUNCTION_0 0xe0001028u +#define CYREG_DWT_COMP_1 0xe0001030u +#define CYREG_DWT_MASK_1 0xe0001034u +#define CYREG_DWT_FUNCTION_1 0xe0001038u +#define CYREG_DWT_COMP_2 0xe0001040u +#define CYREG_DWT_MASK_2 0xe0001044u +#define CYREG_DWT_FUNCTION_2 0xe0001048u +#define CYREG_DWT_COMP_3 0xe0001050u +#define CYREG_DWT_MASK_3 0xe0001054u +#define CYREG_DWT_FUNCTION_3 0xe0001058u +#define CYDEV_FPB_BASE 0xe0002000u +#define CYDEV_FPB_SIZE 0x00001000u +#define CYREG_FPB_CTRL 0xe0002000u +#define CYREG_FPB_REMAP 0xe0002004u +#define CYREG_FPB_FP_COMP_0 0xe0002008u +#define CYREG_FPB_FP_COMP_1 0xe000200cu +#define CYREG_FPB_FP_COMP_2 0xe0002010u +#define CYREG_FPB_FP_COMP_3 0xe0002014u +#define CYREG_FPB_FP_COMP_4 0xe0002018u +#define CYREG_FPB_FP_COMP_5 0xe000201cu +#define CYREG_FPB_FP_COMP_6 0xe0002020u +#define CYREG_FPB_FP_COMP_7 0xe0002024u +#define CYREG_FPB_PID4 0xe0002fd0u +#define CYREG_FPB_PID5 0xe0002fd4u +#define CYREG_FPB_PID6 0xe0002fd8u +#define CYREG_FPB_PID7 0xe0002fdcu +#define CYREG_FPB_PID0 0xe0002fe0u +#define CYREG_FPB_PID1 0xe0002fe4u +#define CYREG_FPB_PID2 0xe0002fe8u +#define CYREG_FPB_PID3 0xe0002fecu +#define CYREG_FPB_CID0 0xe0002ff0u +#define CYREG_FPB_CID1 0xe0002ff4u +#define CYREG_FPB_CID2 0xe0002ff8u +#define CYREG_FPB_CID3 0xe0002ffcu +#define CYDEV_NVIC_BASE 0xe000e000u +#define CYDEV_NVIC_SIZE 0x00000d3cu +#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004u +#define CYREG_NVIC_SYSTICK_CTL 0xe000e010u +#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014u +#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018u +#define CYREG_NVIC_SYSTICK_CAL 0xe000e01cu +#define CYREG_NVIC_SETENA0 0xe000e100u +#define CYREG_NVIC_CLRENA0 0xe000e180u +#define CYREG_NVIC_SETPEND0 0xe000e200u +#define CYREG_NVIC_CLRPEND0 0xe000e280u +#define CYREG_NVIC_ACTIVE0 0xe000e300u +#define CYREG_NVIC_PRI_0 0xe000e400u +#define CYREG_NVIC_PRI_1 0xe000e401u +#define CYREG_NVIC_PRI_2 0xe000e402u +#define CYREG_NVIC_PRI_3 0xe000e403u +#define CYREG_NVIC_PRI_4 0xe000e404u +#define CYREG_NVIC_PRI_5 0xe000e405u +#define CYREG_NVIC_PRI_6 0xe000e406u +#define CYREG_NVIC_PRI_7 0xe000e407u +#define CYREG_NVIC_PRI_8 0xe000e408u +#define CYREG_NVIC_PRI_9 0xe000e409u +#define CYREG_NVIC_PRI_10 0xe000e40au +#define CYREG_NVIC_PRI_11 0xe000e40bu +#define CYREG_NVIC_PRI_12 0xe000e40cu +#define CYREG_NVIC_PRI_13 0xe000e40du +#define CYREG_NVIC_PRI_14 0xe000e40eu +#define CYREG_NVIC_PRI_15 0xe000e40fu +#define CYREG_NVIC_PRI_16 0xe000e410u +#define CYREG_NVIC_PRI_17 0xe000e411u +#define CYREG_NVIC_PRI_18 0xe000e412u +#define CYREG_NVIC_PRI_19 0xe000e413u +#define CYREG_NVIC_PRI_20 0xe000e414u +#define CYREG_NVIC_PRI_21 0xe000e415u +#define CYREG_NVIC_PRI_22 0xe000e416u +#define CYREG_NVIC_PRI_23 0xe000e417u +#define CYREG_NVIC_PRI_24 0xe000e418u +#define CYREG_NVIC_PRI_25 0xe000e419u +#define CYREG_NVIC_PRI_26 0xe000e41au +#define CYREG_NVIC_PRI_27 0xe000e41bu +#define CYREG_NVIC_PRI_28 0xe000e41cu +#define CYREG_NVIC_PRI_29 0xe000e41du +#define CYREG_NVIC_PRI_30 0xe000e41eu +#define CYREG_NVIC_PRI_31 0xe000e41fu +#define CYREG_NVIC_CPUID_BASE 0xe000ed00u +#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04u +#define CYREG_NVIC_VECT_OFFSET 0xe000ed08u +#define CYREG_NVIC_APPLN_INTR 0xe000ed0cu +#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10u +#define CYREG_NVIC_CFG_CONTROL 0xe000ed14u +#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u +#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu +#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u +#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24u +#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u +#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29u +#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2au +#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2cu +#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u +#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u +#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38u +#define CYDEV_CORE_DBG_BASE 0xe000edf0u +#define CYDEV_CORE_DBG_SIZE 0x00000010u +#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0u +#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4u +#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8u +#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfcu +#define CYDEV_TPIU_BASE 0xe0040000u +#define CYDEV_TPIU_SIZE 0x00001000u +#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u +#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u +#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u +#define CYREG_TPIU_PROTOCOL 0xe00400f0u +#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300u +#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304u +#define CYREG_TPIU_TRIGGER 0xe0040ee8u +#define CYREG_TPIU_ITETMDATA 0xe0040eecu +#define CYREG_TPIU_ITATBCTR2 0xe0040ef0u +#define CYREG_TPIU_ITATBCTR0 0xe0040ef8u +#define CYREG_TPIU_ITITMDATA 0xe0040efcu +#define CYREG_TPIU_ITCTRL 0xe0040f00u +#define CYREG_TPIU_DEVID 0xe0040fc8u +#define CYREG_TPIU_DEVTYPE 0xe0040fccu +#define CYREG_TPIU_PID4 0xe0040fd0u +#define CYREG_TPIU_PID5 0xe0040fd4u +#define CYREG_TPIU_PID6 0xe0040fd8u +#define CYREG_TPIU_PID7 0xe0040fdcu +#define CYREG_TPIU_PID0 0xe0040fe0u +#define CYREG_TPIU_PID1 0xe0040fe4u +#define CYREG_TPIU_PID2 0xe0040fe8u +#define CYREG_TPIU_PID3 0xe0040fecu +#define CYREG_TPIU_CID0 0xe0040ff0u +#define CYREG_TPIU_CID1 0xe0040ff4u +#define CYREG_TPIU_CID2 0xe0040ff8u +#define CYREG_TPIU_CID3 0xe0040ffcu +#define CYDEV_ETM_BASE 0xe0041000u +#define CYDEV_ETM_SIZE 0x00001000u +#define CYREG_ETM_CTL 0xe0041000u +#define CYREG_ETM_CFG_CODE 0xe0041004u +#define CYREG_ETM_TRIG_EVENT 0xe0041008u +#define CYREG_ETM_STATUS 0xe0041010u +#define CYREG_ETM_SYS_CFG 0xe0041014u +#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020u +#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024u +#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102cu +#define CYREG_ETM_SYNC_FREQ 0xe00411e0u +#define CYREG_ETM_ETM_ID 0xe00411e4u +#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8u +#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u +#define CYREG_ETM_CS_TRACE_ID 0xe0041200u +#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300u +#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304u +#define CYREG_ETM_PDSR 0xe0041314u +#define CYREG_ETM_ITMISCIN 0xe0041ee0u +#define CYREG_ETM_ITTRIGOUT 0xe0041ee8u +#define CYREG_ETM_ITATBCTR2 0xe0041ef0u +#define CYREG_ETM_ITATBCTR0 0xe0041ef8u +#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00u +#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0u +#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4u +#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0u +#define CYREG_ETM_LOCK_STATUS 0xe0041fb4u +#define CYREG_ETM_AUTH_STATUS 0xe0041fb8u +#define CYREG_ETM_DEV_TYPE 0xe0041fccu +#define CYREG_ETM_PID4 0xe0041fd0u +#define CYREG_ETM_PID5 0xe0041fd4u +#define CYREG_ETM_PID6 0xe0041fd8u +#define CYREG_ETM_PID7 0xe0041fdcu +#define CYREG_ETM_PID0 0xe0041fe0u +#define CYREG_ETM_PID1 0xe0041fe4u +#define CYREG_ETM_PID2 0xe0041fe8u +#define CYREG_ETM_PID3 0xe0041fecu +#define CYREG_ETM_CID0 0xe0041ff0u +#define CYREG_ETM_CID1 0xe0041ff4u +#define CYREG_ETM_CID2 0xe0041ff8u +#define CYREG_ETM_CID3 0xe0041ffcu +#define CYDEV_ROM_TABLE_BASE 0xe00ff000u +#define CYDEV_ROM_TABLE_SIZE 0x00001000u +#define CYREG_ROM_TABLE_NVIC 0xe00ff000u +#define CYREG_ROM_TABLE_DWT 0xe00ff004u +#define CYREG_ROM_TABLE_FPB 0xe00ff008u +#define CYREG_ROM_TABLE_ITM 0xe00ff00cu +#define CYREG_ROM_TABLE_TPIU 0xe00ff010u +#define CYREG_ROM_TABLE_ETM 0xe00ff014u +#define CYREG_ROM_TABLE_END 0xe00ff018u +#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffccu +#define CYREG_ROM_TABLE_PID4 0xe00fffd0u +#define CYREG_ROM_TABLE_PID5 0xe00fffd4u +#define CYREG_ROM_TABLE_PID6 0xe00fffd8u +#define CYREG_ROM_TABLE_PID7 0xe00fffdcu +#define CYREG_ROM_TABLE_PID0 0xe00fffe0u +#define CYREG_ROM_TABLE_PID1 0xe00fffe4u +#define CYREG_ROM_TABLE_PID2 0xe00fffe8u +#define CYREG_ROM_TABLE_PID3 0xe00fffecu +#define CYREG_ROM_TABLE_CID0 0xe00ffff0u +#define CYREG_ROM_TABLE_CID1 0xe00ffff4u +#define CYREG_ROM_TABLE_CID2 0xe00ffff8u +#define CYREG_ROM_TABLE_CID3 0xe00ffffcu +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000u +#define CYDEV_FLS_ROW_SIZE 0x00000100u +#define CYDEV_ECC_SECTOR_SIZE 0x00002000u +#define CYDEV_ECC_ROW_SIZE 0x00000020u +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u +#define CYDEV_EEPROM_ROW_SIZE 0x00000010u +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004u +#define CYCLK_LD_SYNC_EN 0x00000002u +#define CYCLK_LD_LOAD 0x00000001u +#define CYCLK_PIPE 0x00000080u +#define CYCLK_SSS 0x00000040u +#define CYCLK_EARLY 0x00000020u +#define CYCLK_DUTY 0x00000010u +#define CYCLK_SYNC 0x00000008u +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 +#endif /* CYDEVICE_TRM_H */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc new file mode 100644 index 0000000..5240bd6 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -0,0 +1,5356 @@ +/******************************************************************************* +* FILENAME: cydevicegnu.inc +* OBSOLETE: Do not use this file. Use the _trm version instead. +* PSoC Creator 2.2 Component Pack 6 +* +* DESCRIPTION: +* This file provides all of the address values for the entire PSoC device. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.set CYDEV_FLASH_BASE, 0x00000000 +.set CYDEV_FLASH_SIZE, 0x00040000 +.set CYDEV_FLASH_DATA_MBASE, 0x00000000 +.set CYDEV_FLASH_DATA_MSIZE, 0x00040000 +.set CYDEV_SRAM_BASE, 0x1fff8000 +.set CYDEV_SRAM_SIZE, 0x00010000 +.set CYDEV_SRAM_CODE64K_MBASE, 0x1fff8000 +.set CYDEV_SRAM_CODE64K_MSIZE, 0x00004000 +.set CYDEV_SRAM_CODE32K_MBASE, 0x1fffc000 +.set CYDEV_SRAM_CODE32K_MSIZE, 0x00002000 +.set CYDEV_SRAM_CODE16K_MBASE, 0x1fffe000 +.set CYDEV_SRAM_CODE16K_MSIZE, 0x00001000 +.set CYDEV_SRAM_CODE_MBASE, 0x1fff8000 +.set CYDEV_SRAM_CODE_MSIZE, 0x00008000 +.set CYDEV_SRAM_DATA_MBASE, 0x20000000 +.set CYDEV_SRAM_DATA_MSIZE, 0x00008000 +.set CYDEV_SRAM_DATA16K_MBASE, 0x20001000 +.set CYDEV_SRAM_DATA16K_MSIZE, 0x00001000 +.set CYDEV_SRAM_DATA32K_MBASE, 0x20002000 +.set CYDEV_SRAM_DATA32K_MSIZE, 0x00002000 +.set CYDEV_SRAM_DATA64K_MBASE, 0x20004000 +.set CYDEV_SRAM_DATA64K_MSIZE, 0x00004000 +.set CYDEV_DMA_BASE, 0x20008000 +.set CYDEV_DMA_SIZE, 0x00008000 +.set CYDEV_DMA_SRAM64K_MBASE, 0x20008000 +.set CYDEV_DMA_SRAM64K_MSIZE, 0x00004000 +.set CYDEV_DMA_SRAM32K_MBASE, 0x2000c000 +.set CYDEV_DMA_SRAM32K_MSIZE, 0x00002000 +.set CYDEV_DMA_SRAM16K_MBASE, 0x2000e000 +.set CYDEV_DMA_SRAM16K_MSIZE, 0x00001000 +.set CYDEV_DMA_SRAM_MBASE, 0x2000f000 +.set CYDEV_DMA_SRAM_MSIZE, 0x00001000 +.set CYDEV_CLKDIST_BASE, 0x40004000 +.set CYDEV_CLKDIST_SIZE, 0x00000110 +.set CYDEV_CLKDIST_CR, 0x40004000 +.set CYDEV_CLKDIST_LD, 0x40004001 +.set CYDEV_CLKDIST_WRK0, 0x40004002 +.set CYDEV_CLKDIST_WRK1, 0x40004003 +.set CYDEV_CLKDIST_MSTR0, 0x40004004 +.set CYDEV_CLKDIST_MSTR1, 0x40004005 +.set CYDEV_CLKDIST_BCFG0, 0x40004006 +.set CYDEV_CLKDIST_BCFG1, 0x40004007 +.set CYDEV_CLKDIST_BCFG2, 0x40004008 +.set CYDEV_CLKDIST_UCFG, 0x40004009 +.set CYDEV_CLKDIST_DLY0, 0x4000400a +.set CYDEV_CLKDIST_DLY1, 0x4000400b +.set CYDEV_CLKDIST_DMASK, 0x40004010 +.set CYDEV_CLKDIST_AMASK, 0x40004014 +.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG0_CFG0, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_CFG1, 0x40004081 +.set CYDEV_CLKDIST_DCFG0_CFG2, 0x40004082 +.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG1_CFG0, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_CFG1, 0x40004085 +.set CYDEV_CLKDIST_DCFG1_CFG2, 0x40004086 +.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG2_CFG0, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_CFG1, 0x40004089 +.set CYDEV_CLKDIST_DCFG2_CFG2, 0x4000408a +.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG3_CFG0, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_CFG1, 0x4000408d +.set CYDEV_CLKDIST_DCFG3_CFG2, 0x4000408e +.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG4_CFG0, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_CFG1, 0x40004091 +.set CYDEV_CLKDIST_DCFG4_CFG2, 0x40004092 +.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG5_CFG0, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_CFG1, 0x40004095 +.set CYDEV_CLKDIST_DCFG5_CFG2, 0x40004096 +.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG6_CFG0, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_CFG1, 0x40004099 +.set CYDEV_CLKDIST_DCFG6_CFG2, 0x4000409a +.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG7_CFG0, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_CFG1, 0x4000409d +.set CYDEV_CLKDIST_DCFG7_CFG2, 0x4000409e +.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG0_CFG0, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_CFG1, 0x40004101 +.set CYDEV_CLKDIST_ACFG0_CFG2, 0x40004102 +.set CYDEV_CLKDIST_ACFG0_CFG3, 0x40004103 +.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG1_CFG0, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_CFG1, 0x40004105 +.set CYDEV_CLKDIST_ACFG1_CFG2, 0x40004106 +.set CYDEV_CLKDIST_ACFG1_CFG3, 0x40004107 +.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG2_CFG0, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_CFG1, 0x40004109 +.set CYDEV_CLKDIST_ACFG2_CFG2, 0x4000410a +.set CYDEV_CLKDIST_ACFG2_CFG3, 0x4000410b +.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG3_CFG0, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_CFG1, 0x4000410d +.set CYDEV_CLKDIST_ACFG3_CFG2, 0x4000410e +.set CYDEV_CLKDIST_ACFG3_CFG3, 0x4000410f +.set CYDEV_FASTCLK_BASE, 0x40004200 +.set CYDEV_FASTCLK_SIZE, 0x00000026 +.set CYDEV_FASTCLK_IMO_BASE, 0x40004200 +.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 +.set CYDEV_FASTCLK_IMO_CR, 0x40004200 +.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 +.set CYDEV_FASTCLK_XMHZ_CSR, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_CFG0, 0x40004212 +.set CYDEV_FASTCLK_XMHZ_CFG1, 0x40004213 +.set CYDEV_FASTCLK_PLL_BASE, 0x40004220 +.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 +.set CYDEV_FASTCLK_PLL_CFG0, 0x40004220 +.set CYDEV_FASTCLK_PLL_CFG1, 0x40004221 +.set CYDEV_FASTCLK_PLL_P, 0x40004222 +.set CYDEV_FASTCLK_PLL_Q, 0x40004223 +.set CYDEV_FASTCLK_PLL_SR, 0x40004225 +.set CYDEV_SLOWCLK_BASE, 0x40004300 +.set CYDEV_SLOWCLK_SIZE, 0x0000000b +.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 +.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 +.set CYDEV_SLOWCLK_ILO_CR0, 0x40004300 +.set CYDEV_SLOWCLK_ILO_CR1, 0x40004301 +.set CYDEV_SLOWCLK_X32_BASE, 0x40004308 +.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 +.set CYDEV_SLOWCLK_X32_CR, 0x40004308 +.set CYDEV_SLOWCLK_X32_CFG, 0x40004309 +.set CYDEV_SLOWCLK_X32_TST, 0x4000430a +.set CYDEV_BOOST_BASE, 0x40004320 +.set CYDEV_BOOST_SIZE, 0x00000007 +.set CYDEV_BOOST_CR0, 0x40004320 +.set CYDEV_BOOST_CR1, 0x40004321 +.set CYDEV_BOOST_CR2, 0x40004322 +.set CYDEV_BOOST_CR3, 0x40004323 +.set CYDEV_BOOST_SR, 0x40004324 +.set CYDEV_BOOST_CR4, 0x40004325 +.set CYDEV_BOOST_SR2, 0x40004326 +.set CYDEV_PWRSYS_BASE, 0x40004330 +.set CYDEV_PWRSYS_SIZE, 0x00000002 +.set CYDEV_PWRSYS_CR0, 0x40004330 +.set CYDEV_PWRSYS_CR1, 0x40004331 +.set CYDEV_PM_BASE, 0x40004380 +.set CYDEV_PM_SIZE, 0x00000057 +.set CYDEV_PM_TW_CFG0, 0x40004380 +.set CYDEV_PM_TW_CFG1, 0x40004381 +.set CYDEV_PM_TW_CFG2, 0x40004382 +.set CYDEV_PM_WDT_CFG, 0x40004383 +.set CYDEV_PM_WDT_CR, 0x40004384 +.set CYDEV_PM_INT_SR, 0x40004390 +.set CYDEV_PM_MODE_CFG0, 0x40004391 +.set CYDEV_PM_MODE_CFG1, 0x40004392 +.set CYDEV_PM_MODE_CSR, 0x40004393 +.set CYDEV_PM_USB_CR0, 0x40004394 +.set CYDEV_PM_WAKEUP_CFG0, 0x40004398 +.set CYDEV_PM_WAKEUP_CFG1, 0x40004399 +.set CYDEV_PM_WAKEUP_CFG2, 0x4000439a +.set CYDEV_PM_ACT_BASE, 0x400043a0 +.set CYDEV_PM_ACT_SIZE, 0x0000000e +.set CYDEV_PM_ACT_CFG0, 0x400043a0 +.set CYDEV_PM_ACT_CFG1, 0x400043a1 +.set CYDEV_PM_ACT_CFG2, 0x400043a2 +.set CYDEV_PM_ACT_CFG3, 0x400043a3 +.set CYDEV_PM_ACT_CFG4, 0x400043a4 +.set CYDEV_PM_ACT_CFG5, 0x400043a5 +.set CYDEV_PM_ACT_CFG6, 0x400043a6 +.set CYDEV_PM_ACT_CFG7, 0x400043a7 +.set CYDEV_PM_ACT_CFG8, 0x400043a8 +.set CYDEV_PM_ACT_CFG9, 0x400043a9 +.set CYDEV_PM_ACT_CFG10, 0x400043aa +.set CYDEV_PM_ACT_CFG11, 0x400043ab +.set CYDEV_PM_ACT_CFG12, 0x400043ac +.set CYDEV_PM_ACT_CFG13, 0x400043ad +.set CYDEV_PM_STBY_BASE, 0x400043b0 +.set CYDEV_PM_STBY_SIZE, 0x0000000e +.set CYDEV_PM_STBY_CFG0, 0x400043b0 +.set CYDEV_PM_STBY_CFG1, 0x400043b1 +.set CYDEV_PM_STBY_CFG2, 0x400043b2 +.set CYDEV_PM_STBY_CFG3, 0x400043b3 +.set CYDEV_PM_STBY_CFG4, 0x400043b4 +.set CYDEV_PM_STBY_CFG5, 0x400043b5 +.set CYDEV_PM_STBY_CFG6, 0x400043b6 +.set CYDEV_PM_STBY_CFG7, 0x400043b7 +.set CYDEV_PM_STBY_CFG8, 0x400043b8 +.set CYDEV_PM_STBY_CFG9, 0x400043b9 +.set CYDEV_PM_STBY_CFG10, 0x400043ba +.set CYDEV_PM_STBY_CFG11, 0x400043bb +.set CYDEV_PM_STBY_CFG12, 0x400043bc +.set CYDEV_PM_STBY_CFG13, 0x400043bd +.set CYDEV_PM_AVAIL_BASE, 0x400043c0 +.set CYDEV_PM_AVAIL_SIZE, 0x00000017 +.set CYDEV_PM_AVAIL_CR0, 0x400043c0 +.set CYDEV_PM_AVAIL_CR1, 0x400043c1 +.set CYDEV_PM_AVAIL_CR2, 0x400043c2 +.set CYDEV_PM_AVAIL_CR3, 0x400043c3 +.set CYDEV_PM_AVAIL_CR4, 0x400043c4 +.set CYDEV_PM_AVAIL_CR5, 0x400043c5 +.set CYDEV_PM_AVAIL_CR6, 0x400043c6 +.set CYDEV_PM_AVAIL_SR0, 0x400043d0 +.set CYDEV_PM_AVAIL_SR1, 0x400043d1 +.set CYDEV_PM_AVAIL_SR2, 0x400043d2 +.set CYDEV_PM_AVAIL_SR3, 0x400043d3 +.set CYDEV_PM_AVAIL_SR4, 0x400043d4 +.set CYDEV_PM_AVAIL_SR5, 0x400043d5 +.set CYDEV_PM_AVAIL_SR6, 0x400043d6 +.set CYDEV_PICU_BASE, 0x40004500 +.set CYDEV_PICU_SIZE, 0x000000b0 +.set CYDEV_PICU_INTTYPE_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 +.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE0, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE1, 0x40004501 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE2, 0x40004502 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE3, 0x40004503 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE4, 0x40004504 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE5, 0x40004505 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE6, 0x40004506 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE7, 0x40004507 +.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE0, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE1, 0x40004509 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE2, 0x4000450a +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE3, 0x4000450b +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE4, 0x4000450c +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE5, 0x4000450d +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE6, 0x4000450e +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE7, 0x4000450f +.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE0, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE1, 0x40004511 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE2, 0x40004512 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE3, 0x40004513 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE4, 0x40004514 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE5, 0x40004515 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE6, 0x40004516 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE7, 0x40004517 +.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE0, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE1, 0x40004519 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE2, 0x4000451a +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE3, 0x4000451b +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE4, 0x4000451c +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE5, 0x4000451d +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE6, 0x4000451e +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE7, 0x4000451f +.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE0, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE1, 0x40004521 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE2, 0x40004522 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE3, 0x40004523 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE4, 0x40004524 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE5, 0x40004525 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE6, 0x40004526 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE7, 0x40004527 +.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE0, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE1, 0x40004529 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE2, 0x4000452a +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE3, 0x4000452b +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE4, 0x4000452c +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE5, 0x4000452d +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE6, 0x4000452e +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE7, 0x4000452f +.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE0, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE1, 0x40004531 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE2, 0x40004532 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE3, 0x40004533 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE4, 0x40004534 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE5, 0x40004535 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE6, 0x40004536 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE7, 0x40004537 +.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE0, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE1, 0x40004561 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE2, 0x40004562 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE3, 0x40004563 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE4, 0x40004564 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE5, 0x40004565 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE6, 0x40004566 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE7, 0x40004567 +.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE0, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE1, 0x40004579 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE2, 0x4000457a +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE3, 0x4000457b +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE4, 0x4000457c +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE5, 0x4000457d +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE6, 0x4000457e +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE7, 0x4000457f +.set CYDEV_PICU_STAT_BASE, 0x40004580 +.set CYDEV_PICU_STAT_SIZE, 0x00000010 +.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 +.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU0_INTSTAT, 0x40004580 +.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 +.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU1_INTSTAT, 0x40004581 +.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 +.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU2_INTSTAT, 0x40004582 +.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 +.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU3_INTSTAT, 0x40004583 +.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 +.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU4_INTSTAT, 0x40004584 +.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 +.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU5_INTSTAT, 0x40004585 +.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 +.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU6_INTSTAT, 0x40004586 +.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c +.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU12_INTSTAT, 0x4000458c +.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f +.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU15_INTSTAT, 0x4000458f +.set CYDEV_PICU_SNAP_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_SIZE, 0x00000010 +.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU0_SNAP, 0x40004590 +.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 +.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU1_SNAP, 0x40004591 +.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 +.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU2_SNAP, 0x40004592 +.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 +.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU3_SNAP, 0x40004593 +.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 +.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU4_SNAP, 0x40004594 +.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 +.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU5_SNAP, 0x40004595 +.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 +.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU6_SNAP, 0x40004596 +.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c +.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU12_SNAP, 0x4000459c +.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f +.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU_15_SNAP_15, 0x4000459f +.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 +.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af +.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR, 0x400045af +.set CYDEV_MFGCFG_BASE, 0x40004600 +.set CYDEV_MFGCFG_SIZE, 0x000000ed +.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 +.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 +.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC0_TR, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC1_TR, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC2_TR, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC3_TR, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_SAR0_TR0, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_SAR1_TR0, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR0, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR1, 0x40004621 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR0, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR1, 0x40004623 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR0, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR1, 0x40004625 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR0, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR1, 0x40004627 +.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP0_TR0, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_TR1, 0x40004631 +.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP1_TR0, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_TR1, 0x40004633 +.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP2_TR0, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_TR1, 0x40004635 +.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP3_TR0, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_TR1, 0x40004637 +.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b +.set CYDEV_MFGCFG_PWRSYS_HIB_TR0, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_HIB_TR1, 0x40004681 +.set CYDEV_MFGCFG_PWRSYS_I2C_TR, 0x40004682 +.set CYDEV_MFGCFG_PWRSYS_SLP_TR, 0x40004683 +.set CYDEV_MFGCFG_PWRSYS_BUZZ_TR, 0x40004684 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR0, 0x40004685 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR1, 0x40004686 +.set CYDEV_MFGCFG_PWRSYS_BREF_TR, 0x40004687 +.set CYDEV_MFGCFG_PWRSYS_BG_TR, 0x40004688 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR2, 0x40004689 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR3, 0x4000468a +.set CYDEV_MFGCFG_ILO_BASE, 0x40004690 +.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ILO_TR0, 0x40004690 +.set CYDEV_MFGCFG_ILO_TR1, 0x40004691 +.set CYDEV_MFGCFG_X32_BASE, 0x40004698 +.set CYDEV_MFGCFG_X32_SIZE, 0x00000001 +.set CYDEV_MFGCFG_X32_TR, 0x40004698 +.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 +.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 +.set CYDEV_MFGCFG_IMO_TR0, 0x400046a0 +.set CYDEV_MFGCFG_IMO_TR1, 0x400046a1 +.set CYDEV_MFGCFG_IMO_GAIN, 0x400046a2 +.set CYDEV_MFGCFG_IMO_C36M, 0x400046a3 +.set CYDEV_MFGCFG_IMO_TR2, 0x400046a4 +.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 +.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 +.set CYDEV_MFGCFG_XMHZ_TR, 0x400046a8 +.set CYDEV_MFGCFG_DLY, 0x400046c0 +.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 +.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d +.set CYDEV_MFGCFG_MLOGIC_DMPSTR, 0x400046e2 +.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 +.set CYDEV_MFGCFG_MLOGIC_SEG_CR, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_CFG0, 0x400046e5 +.set CYDEV_MFGCFG_MLOGIC_DEBUG, 0x400046e8 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_REV_ID, 0x400046ec +.set CYDEV_RESET_BASE, 0x400046f0 +.set CYDEV_RESET_SIZE, 0x0000000f +.set CYDEV_RESET_IPOR_CR0, 0x400046f0 +.set CYDEV_RESET_IPOR_CR1, 0x400046f1 +.set CYDEV_RESET_IPOR_CR2, 0x400046f2 +.set CYDEV_RESET_IPOR_CR3, 0x400046f3 +.set CYDEV_RESET_CR0, 0x400046f4 +.set CYDEV_RESET_CR1, 0x400046f5 +.set CYDEV_RESET_CR2, 0x400046f6 +.set CYDEV_RESET_CR3, 0x400046f7 +.set CYDEV_RESET_CR4, 0x400046f8 +.set CYDEV_RESET_CR5, 0x400046f9 +.set CYDEV_RESET_SR0, 0x400046fa +.set CYDEV_RESET_SR1, 0x400046fb +.set CYDEV_RESET_SR2, 0x400046fc +.set CYDEV_RESET_SR3, 0x400046fd +.set CYDEV_RESET_TR, 0x400046fe +.set CYDEV_SPC_BASE, 0x40004700 +.set CYDEV_SPC_SIZE, 0x00000100 +.set CYDEV_SPC_FM_EE_CR, 0x40004700 +.set CYDEV_SPC_FM_EE_WAKE_CNT, 0x40004701 +.set CYDEV_SPC_EE_SCR, 0x40004702 +.set CYDEV_SPC_EE_ERR, 0x40004703 +.set CYDEV_SPC_CPU_DATA, 0x40004720 +.set CYDEV_SPC_DMA_DATA, 0x40004721 +.set CYDEV_SPC_SR, 0x40004722 +.set CYDEV_SPC_CR, 0x40004723 +.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 +.set CYDEV_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 +.set CYDEV_CACHE_BASE, 0x40004800 +.set CYDEV_CACHE_SIZE, 0x0000009c +.set CYDEV_CACHE_CC_CTL, 0x40004800 +.set CYDEV_CACHE_ECC_CORR, 0x40004880 +.set CYDEV_CACHE_ECC_ERR, 0x40004888 +.set CYDEV_CACHE_FLASH_ERR, 0x40004890 +.set CYDEV_CACHE_HITMISS, 0x40004898 +.set CYDEV_I2C_BASE, 0x40004900 +.set CYDEV_I2C_SIZE, 0x000000e1 +.set CYDEV_I2C_XCFG, 0x400049c8 +.set CYDEV_I2C_ADR, 0x400049ca +.set CYDEV_I2C_CFG, 0x400049d6 +.set CYDEV_I2C_CSR, 0x400049d7 +.set CYDEV_I2C_D, 0x400049d8 +.set CYDEV_I2C_MCSR, 0x400049d9 +.set CYDEV_I2C_CLK_DIV1, 0x400049db +.set CYDEV_I2C_CLK_DIV2, 0x400049dc +.set CYDEV_I2C_TMOUT_CSR, 0x400049dd +.set CYDEV_I2C_TMOUT_SR, 0x400049de +.set CYDEV_I2C_TMOUT_CFG0, 0x400049df +.set CYDEV_I2C_TMOUT_CFG1, 0x400049e0 +.set CYDEV_DEC_BASE, 0x40004e00 +.set CYDEV_DEC_SIZE, 0x00000015 +.set CYDEV_DEC_CR, 0x40004e00 +.set CYDEV_DEC_SR, 0x40004e01 +.set CYDEV_DEC_SHIFT1, 0x40004e02 +.set CYDEV_DEC_SHIFT2, 0x40004e03 +.set CYDEV_DEC_DR2, 0x40004e04 +.set CYDEV_DEC_DR2H, 0x40004e05 +.set CYDEV_DEC_DR1, 0x40004e06 +.set CYDEV_DEC_OCOR, 0x40004e08 +.set CYDEV_DEC_OCORM, 0x40004e09 +.set CYDEV_DEC_OCORH, 0x40004e0a +.set CYDEV_DEC_GCOR, 0x40004e0c +.set CYDEV_DEC_GCORH, 0x40004e0d +.set CYDEV_DEC_GVAL, 0x40004e0e +.set CYDEV_DEC_OUTSAMP, 0x40004e10 +.set CYDEV_DEC_OUTSAMPM, 0x40004e11 +.set CYDEV_DEC_OUTSAMPH, 0x40004e12 +.set CYDEV_DEC_OUTSAMPS, 0x40004e13 +.set CYDEV_DEC_COHER, 0x40004e14 +.set CYDEV_TMR0_BASE, 0x40004f00 +.set CYDEV_TMR0_SIZE, 0x0000000c +.set CYDEV_TMR0_CFG0, 0x40004f00 +.set CYDEV_TMR0_CFG1, 0x40004f01 +.set CYDEV_TMR0_CFG2, 0x40004f02 +.set CYDEV_TMR0_SR0, 0x40004f03 +.set CYDEV_TMR0_PER0, 0x40004f04 +.set CYDEV_TMR0_PER1, 0x40004f05 +.set CYDEV_TMR0_CNT_CMP0, 0x40004f06 +.set CYDEV_TMR0_CNT_CMP1, 0x40004f07 +.set CYDEV_TMR0_CAP0, 0x40004f08 +.set CYDEV_TMR0_CAP1, 0x40004f09 +.set CYDEV_TMR0_RT0, 0x40004f0a +.set CYDEV_TMR0_RT1, 0x40004f0b +.set CYDEV_TMR1_BASE, 0x40004f0c +.set CYDEV_TMR1_SIZE, 0x0000000c +.set CYDEV_TMR1_CFG0, 0x40004f0c +.set CYDEV_TMR1_CFG1, 0x40004f0d +.set CYDEV_TMR1_CFG2, 0x40004f0e +.set CYDEV_TMR1_SR0, 0x40004f0f +.set CYDEV_TMR1_PER0, 0x40004f10 +.set CYDEV_TMR1_PER1, 0x40004f11 +.set CYDEV_TMR1_CNT_CMP0, 0x40004f12 +.set CYDEV_TMR1_CNT_CMP1, 0x40004f13 +.set CYDEV_TMR1_CAP0, 0x40004f14 +.set CYDEV_TMR1_CAP1, 0x40004f15 +.set CYDEV_TMR1_RT0, 0x40004f16 +.set CYDEV_TMR1_RT1, 0x40004f17 +.set CYDEV_TMR2_BASE, 0x40004f18 +.set CYDEV_TMR2_SIZE, 0x0000000c +.set CYDEV_TMR2_CFG0, 0x40004f18 +.set CYDEV_TMR2_CFG1, 0x40004f19 +.set CYDEV_TMR2_CFG2, 0x40004f1a +.set CYDEV_TMR2_SR0, 0x40004f1b +.set CYDEV_TMR2_PER0, 0x40004f1c +.set CYDEV_TMR2_PER1, 0x40004f1d +.set CYDEV_TMR2_CNT_CMP0, 0x40004f1e +.set CYDEV_TMR2_CNT_CMP1, 0x40004f1f +.set CYDEV_TMR2_CAP0, 0x40004f20 +.set CYDEV_TMR2_CAP1, 0x40004f21 +.set CYDEV_TMR2_RT0, 0x40004f22 +.set CYDEV_TMR2_RT1, 0x40004f23 +.set CYDEV_TMR3_BASE, 0x40004f24 +.set CYDEV_TMR3_SIZE, 0x0000000c +.set CYDEV_TMR3_CFG0, 0x40004f24 +.set CYDEV_TMR3_CFG1, 0x40004f25 +.set CYDEV_TMR3_CFG2, 0x40004f26 +.set CYDEV_TMR3_SR0, 0x40004f27 +.set CYDEV_TMR3_PER0, 0x40004f28 +.set CYDEV_TMR3_PER1, 0x40004f29 +.set CYDEV_TMR3_CNT_CMP0, 0x40004f2a +.set CYDEV_TMR3_CNT_CMP1, 0x40004f2b +.set CYDEV_TMR3_CAP0, 0x40004f2c +.set CYDEV_TMR3_CAP1, 0x40004f2d +.set CYDEV_TMR3_RT0, 0x40004f2e +.set CYDEV_TMR3_RT1, 0x40004f2f +.set CYDEV_IO_BASE, 0x40005000 +.set CYDEV_IO_SIZE, 0x00000200 +.set CYDEV_IO_PC_BASE, 0x40005000 +.set CYDEV_IO_PC_SIZE, 0x00000080 +.set CYDEV_IO_PC_PRT0_BASE, 0x40005000 +.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT0_PC0, 0x40005000 +.set CYDEV_IO_PC_PRT0_PC1, 0x40005001 +.set CYDEV_IO_PC_PRT0_PC2, 0x40005002 +.set CYDEV_IO_PC_PRT0_PC3, 0x40005003 +.set CYDEV_IO_PC_PRT0_PC4, 0x40005004 +.set CYDEV_IO_PC_PRT0_PC5, 0x40005005 +.set CYDEV_IO_PC_PRT0_PC6, 0x40005006 +.set CYDEV_IO_PC_PRT0_PC7, 0x40005007 +.set CYDEV_IO_PC_PRT1_BASE, 0x40005008 +.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT1_PC0, 0x40005008 +.set CYDEV_IO_PC_PRT1_PC1, 0x40005009 +.set CYDEV_IO_PC_PRT1_PC2, 0x4000500a +.set CYDEV_IO_PC_PRT1_PC3, 0x4000500b +.set CYDEV_IO_PC_PRT1_PC4, 0x4000500c +.set CYDEV_IO_PC_PRT1_PC5, 0x4000500d +.set CYDEV_IO_PC_PRT1_PC6, 0x4000500e +.set CYDEV_IO_PC_PRT1_PC7, 0x4000500f +.set CYDEV_IO_PC_PRT2_BASE, 0x40005010 +.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT2_PC0, 0x40005010 +.set CYDEV_IO_PC_PRT2_PC1, 0x40005011 +.set CYDEV_IO_PC_PRT2_PC2, 0x40005012 +.set CYDEV_IO_PC_PRT2_PC3, 0x40005013 +.set CYDEV_IO_PC_PRT2_PC4, 0x40005014 +.set CYDEV_IO_PC_PRT2_PC5, 0x40005015 +.set CYDEV_IO_PC_PRT2_PC6, 0x40005016 +.set CYDEV_IO_PC_PRT2_PC7, 0x40005017 +.set CYDEV_IO_PC_PRT3_BASE, 0x40005018 +.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT3_PC0, 0x40005018 +.set CYDEV_IO_PC_PRT3_PC1, 0x40005019 +.set CYDEV_IO_PC_PRT3_PC2, 0x4000501a +.set CYDEV_IO_PC_PRT3_PC3, 0x4000501b +.set CYDEV_IO_PC_PRT3_PC4, 0x4000501c +.set CYDEV_IO_PC_PRT3_PC5, 0x4000501d +.set CYDEV_IO_PC_PRT3_PC6, 0x4000501e +.set CYDEV_IO_PC_PRT3_PC7, 0x4000501f +.set CYDEV_IO_PC_PRT4_BASE, 0x40005020 +.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT4_PC0, 0x40005020 +.set CYDEV_IO_PC_PRT4_PC1, 0x40005021 +.set CYDEV_IO_PC_PRT4_PC2, 0x40005022 +.set CYDEV_IO_PC_PRT4_PC3, 0x40005023 +.set CYDEV_IO_PC_PRT4_PC4, 0x40005024 +.set CYDEV_IO_PC_PRT4_PC5, 0x40005025 +.set CYDEV_IO_PC_PRT4_PC6, 0x40005026 +.set CYDEV_IO_PC_PRT4_PC7, 0x40005027 +.set CYDEV_IO_PC_PRT5_BASE, 0x40005028 +.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT5_PC0, 0x40005028 +.set CYDEV_IO_PC_PRT5_PC1, 0x40005029 +.set CYDEV_IO_PC_PRT5_PC2, 0x4000502a +.set CYDEV_IO_PC_PRT5_PC3, 0x4000502b +.set CYDEV_IO_PC_PRT5_PC4, 0x4000502c +.set CYDEV_IO_PC_PRT5_PC5, 0x4000502d +.set CYDEV_IO_PC_PRT5_PC6, 0x4000502e +.set CYDEV_IO_PC_PRT5_PC7, 0x4000502f +.set CYDEV_IO_PC_PRT6_BASE, 0x40005030 +.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT6_PC0, 0x40005030 +.set CYDEV_IO_PC_PRT6_PC1, 0x40005031 +.set CYDEV_IO_PC_PRT6_PC2, 0x40005032 +.set CYDEV_IO_PC_PRT6_PC3, 0x40005033 +.set CYDEV_IO_PC_PRT6_PC4, 0x40005034 +.set CYDEV_IO_PC_PRT6_PC5, 0x40005035 +.set CYDEV_IO_PC_PRT6_PC6, 0x40005036 +.set CYDEV_IO_PC_PRT6_PC7, 0x40005037 +.set CYDEV_IO_PC_PRT12_BASE, 0x40005060 +.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT12_PC0, 0x40005060 +.set CYDEV_IO_PC_PRT12_PC1, 0x40005061 +.set CYDEV_IO_PC_PRT12_PC2, 0x40005062 +.set CYDEV_IO_PC_PRT12_PC3, 0x40005063 +.set CYDEV_IO_PC_PRT12_PC4, 0x40005064 +.set CYDEV_IO_PC_PRT12_PC5, 0x40005065 +.set CYDEV_IO_PC_PRT12_PC6, 0x40005066 +.set CYDEV_IO_PC_PRT12_PC7, 0x40005067 +.set CYDEV_IO_PC_PRT15_BASE, 0x40005078 +.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 +.set CYDEV_IO_PC_PRT15_PC0, 0x40005078 +.set CYDEV_IO_PC_PRT15_PC1, 0x40005079 +.set CYDEV_IO_PC_PRT15_PC2, 0x4000507a +.set CYDEV_IO_PC_PRT15_PC3, 0x4000507b +.set CYDEV_IO_PC_PRT15_PC4, 0x4000507c +.set CYDEV_IO_PC_PRT15_PC5, 0x4000507d +.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 +.set CYDEV_IO_PC_PRT15_7_6_PC0, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_PC1, 0x4000507f +.set CYDEV_IO_DR_BASE, 0x40005080 +.set CYDEV_IO_DR_SIZE, 0x00000010 +.set CYDEV_IO_DR_PRT0_BASE, 0x40005080 +.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT0_DR_ALIAS, 0x40005080 +.set CYDEV_IO_DR_PRT1_BASE, 0x40005081 +.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT1_DR_ALIAS, 0x40005081 +.set CYDEV_IO_DR_PRT2_BASE, 0x40005082 +.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT2_DR_ALIAS, 0x40005082 +.set CYDEV_IO_DR_PRT3_BASE, 0x40005083 +.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT3_DR_ALIAS, 0x40005083 +.set CYDEV_IO_DR_PRT4_BASE, 0x40005084 +.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT4_DR_ALIAS, 0x40005084 +.set CYDEV_IO_DR_PRT5_BASE, 0x40005085 +.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT5_DR_ALIAS, 0x40005085 +.set CYDEV_IO_DR_PRT6_BASE, 0x40005086 +.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT6_DR_ALIAS, 0x40005086 +.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c +.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT12_DR_ALIAS, 0x4000508c +.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f +.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT15_DR_15_ALIAS, 0x4000508f +.set CYDEV_IO_PS_BASE, 0x40005090 +.set CYDEV_IO_PS_SIZE, 0x00000010 +.set CYDEV_IO_PS_PRT0_BASE, 0x40005090 +.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT0_PS_ALIAS, 0x40005090 +.set CYDEV_IO_PS_PRT1_BASE, 0x40005091 +.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT1_PS_ALIAS, 0x40005091 +.set CYDEV_IO_PS_PRT2_BASE, 0x40005092 +.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT2_PS_ALIAS, 0x40005092 +.set CYDEV_IO_PS_PRT3_BASE, 0x40005093 +.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT3_PS_ALIAS, 0x40005093 +.set CYDEV_IO_PS_PRT4_BASE, 0x40005094 +.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT4_PS_ALIAS, 0x40005094 +.set CYDEV_IO_PS_PRT5_BASE, 0x40005095 +.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT5_PS_ALIAS, 0x40005095 +.set CYDEV_IO_PS_PRT6_BASE, 0x40005096 +.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT6_PS_ALIAS, 0x40005096 +.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c +.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT12_PS_ALIAS, 0x4000509c +.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f +.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT15_PS15_ALIAS, 0x4000509f +.set CYDEV_IO_PRT_BASE, 0x40005100 +.set CYDEV_IO_PRT_SIZE, 0x00000100 +.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 +.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT0_DR, 0x40005100 +.set CYDEV_IO_PRT_PRT0_PS, 0x40005101 +.set CYDEV_IO_PRT_PRT0_DM0, 0x40005102 +.set CYDEV_IO_PRT_PRT0_DM1, 0x40005103 +.set CYDEV_IO_PRT_PRT0_DM2, 0x40005104 +.set CYDEV_IO_PRT_PRT0_SLW, 0x40005105 +.set CYDEV_IO_PRT_PRT0_BYP, 0x40005106 +.set CYDEV_IO_PRT_PRT0_BIE, 0x40005107 +.set CYDEV_IO_PRT_PRT0_INP_DIS, 0x40005108 +.set CYDEV_IO_PRT_PRT0_CTL, 0x40005109 +.set CYDEV_IO_PRT_PRT0_PRT, 0x4000510a +.set CYDEV_IO_PRT_PRT0_BIT_MASK, 0x4000510b +.set CYDEV_IO_PRT_PRT0_AMUX, 0x4000510c +.set CYDEV_IO_PRT_PRT0_AG, 0x4000510d +.set CYDEV_IO_PRT_PRT0_LCD_COM_SEG, 0x4000510e +.set CYDEV_IO_PRT_PRT0_LCD_EN, 0x4000510f +.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 +.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT1_DR, 0x40005110 +.set CYDEV_IO_PRT_PRT1_PS, 0x40005111 +.set CYDEV_IO_PRT_PRT1_DM0, 0x40005112 +.set CYDEV_IO_PRT_PRT1_DM1, 0x40005113 +.set CYDEV_IO_PRT_PRT1_DM2, 0x40005114 +.set CYDEV_IO_PRT_PRT1_SLW, 0x40005115 +.set CYDEV_IO_PRT_PRT1_BYP, 0x40005116 +.set CYDEV_IO_PRT_PRT1_BIE, 0x40005117 +.set CYDEV_IO_PRT_PRT1_INP_DIS, 0x40005118 +.set CYDEV_IO_PRT_PRT1_CTL, 0x40005119 +.set CYDEV_IO_PRT_PRT1_PRT, 0x4000511a +.set CYDEV_IO_PRT_PRT1_BIT_MASK, 0x4000511b +.set CYDEV_IO_PRT_PRT1_AMUX, 0x4000511c +.set CYDEV_IO_PRT_PRT1_AG, 0x4000511d +.set CYDEV_IO_PRT_PRT1_LCD_COM_SEG, 0x4000511e +.set CYDEV_IO_PRT_PRT1_LCD_EN, 0x4000511f +.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 +.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT2_DR, 0x40005120 +.set CYDEV_IO_PRT_PRT2_PS, 0x40005121 +.set CYDEV_IO_PRT_PRT2_DM0, 0x40005122 +.set CYDEV_IO_PRT_PRT2_DM1, 0x40005123 +.set CYDEV_IO_PRT_PRT2_DM2, 0x40005124 +.set CYDEV_IO_PRT_PRT2_SLW, 0x40005125 +.set CYDEV_IO_PRT_PRT2_BYP, 0x40005126 +.set CYDEV_IO_PRT_PRT2_BIE, 0x40005127 +.set CYDEV_IO_PRT_PRT2_INP_DIS, 0x40005128 +.set CYDEV_IO_PRT_PRT2_CTL, 0x40005129 +.set CYDEV_IO_PRT_PRT2_PRT, 0x4000512a +.set CYDEV_IO_PRT_PRT2_BIT_MASK, 0x4000512b +.set CYDEV_IO_PRT_PRT2_AMUX, 0x4000512c +.set CYDEV_IO_PRT_PRT2_AG, 0x4000512d +.set CYDEV_IO_PRT_PRT2_LCD_COM_SEG, 0x4000512e +.set CYDEV_IO_PRT_PRT2_LCD_EN, 0x4000512f +.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 +.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT3_DR, 0x40005130 +.set CYDEV_IO_PRT_PRT3_PS, 0x40005131 +.set CYDEV_IO_PRT_PRT3_DM0, 0x40005132 +.set CYDEV_IO_PRT_PRT3_DM1, 0x40005133 +.set CYDEV_IO_PRT_PRT3_DM2, 0x40005134 +.set CYDEV_IO_PRT_PRT3_SLW, 0x40005135 +.set CYDEV_IO_PRT_PRT3_BYP, 0x40005136 +.set CYDEV_IO_PRT_PRT3_BIE, 0x40005137 +.set CYDEV_IO_PRT_PRT3_INP_DIS, 0x40005138 +.set CYDEV_IO_PRT_PRT3_CTL, 0x40005139 +.set CYDEV_IO_PRT_PRT3_PRT, 0x4000513a +.set CYDEV_IO_PRT_PRT3_BIT_MASK, 0x4000513b +.set CYDEV_IO_PRT_PRT3_AMUX, 0x4000513c +.set CYDEV_IO_PRT_PRT3_AG, 0x4000513d +.set CYDEV_IO_PRT_PRT3_LCD_COM_SEG, 0x4000513e +.set CYDEV_IO_PRT_PRT3_LCD_EN, 0x4000513f +.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 +.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT4_DR, 0x40005140 +.set CYDEV_IO_PRT_PRT4_PS, 0x40005141 +.set CYDEV_IO_PRT_PRT4_DM0, 0x40005142 +.set CYDEV_IO_PRT_PRT4_DM1, 0x40005143 +.set CYDEV_IO_PRT_PRT4_DM2, 0x40005144 +.set CYDEV_IO_PRT_PRT4_SLW, 0x40005145 +.set CYDEV_IO_PRT_PRT4_BYP, 0x40005146 +.set CYDEV_IO_PRT_PRT4_BIE, 0x40005147 +.set CYDEV_IO_PRT_PRT4_INP_DIS, 0x40005148 +.set CYDEV_IO_PRT_PRT4_CTL, 0x40005149 +.set CYDEV_IO_PRT_PRT4_PRT, 0x4000514a +.set CYDEV_IO_PRT_PRT4_BIT_MASK, 0x4000514b +.set CYDEV_IO_PRT_PRT4_AMUX, 0x4000514c +.set CYDEV_IO_PRT_PRT4_AG, 0x4000514d +.set CYDEV_IO_PRT_PRT4_LCD_COM_SEG, 0x4000514e +.set CYDEV_IO_PRT_PRT4_LCD_EN, 0x4000514f +.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 +.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT5_DR, 0x40005150 +.set CYDEV_IO_PRT_PRT5_PS, 0x40005151 +.set CYDEV_IO_PRT_PRT5_DM0, 0x40005152 +.set CYDEV_IO_PRT_PRT5_DM1, 0x40005153 +.set CYDEV_IO_PRT_PRT5_DM2, 0x40005154 +.set CYDEV_IO_PRT_PRT5_SLW, 0x40005155 +.set CYDEV_IO_PRT_PRT5_BYP, 0x40005156 +.set CYDEV_IO_PRT_PRT5_BIE, 0x40005157 +.set CYDEV_IO_PRT_PRT5_INP_DIS, 0x40005158 +.set CYDEV_IO_PRT_PRT5_CTL, 0x40005159 +.set CYDEV_IO_PRT_PRT5_PRT, 0x4000515a +.set CYDEV_IO_PRT_PRT5_BIT_MASK, 0x4000515b +.set CYDEV_IO_PRT_PRT5_AMUX, 0x4000515c +.set CYDEV_IO_PRT_PRT5_AG, 0x4000515d +.set CYDEV_IO_PRT_PRT5_LCD_COM_SEG, 0x4000515e +.set CYDEV_IO_PRT_PRT5_LCD_EN, 0x4000515f +.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 +.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT6_DR, 0x40005160 +.set CYDEV_IO_PRT_PRT6_PS, 0x40005161 +.set CYDEV_IO_PRT_PRT6_DM0, 0x40005162 +.set CYDEV_IO_PRT_PRT6_DM1, 0x40005163 +.set CYDEV_IO_PRT_PRT6_DM2, 0x40005164 +.set CYDEV_IO_PRT_PRT6_SLW, 0x40005165 +.set CYDEV_IO_PRT_PRT6_BYP, 0x40005166 +.set CYDEV_IO_PRT_PRT6_BIE, 0x40005167 +.set CYDEV_IO_PRT_PRT6_INP_DIS, 0x40005168 +.set CYDEV_IO_PRT_PRT6_CTL, 0x40005169 +.set CYDEV_IO_PRT_PRT6_PRT, 0x4000516a +.set CYDEV_IO_PRT_PRT6_BIT_MASK, 0x4000516b +.set CYDEV_IO_PRT_PRT6_AMUX, 0x4000516c +.set CYDEV_IO_PRT_PRT6_AG, 0x4000516d +.set CYDEV_IO_PRT_PRT6_LCD_COM_SEG, 0x4000516e +.set CYDEV_IO_PRT_PRT6_LCD_EN, 0x4000516f +.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT12_DR, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_PS, 0x400051c1 +.set CYDEV_IO_PRT_PRT12_DM0, 0x400051c2 +.set CYDEV_IO_PRT_PRT12_DM1, 0x400051c3 +.set CYDEV_IO_PRT_PRT12_DM2, 0x400051c4 +.set CYDEV_IO_PRT_PRT12_SLW, 0x400051c5 +.set CYDEV_IO_PRT_PRT12_BYP, 0x400051c6 +.set CYDEV_IO_PRT_PRT12_BIE, 0x400051c7 +.set CYDEV_IO_PRT_PRT12_INP_DIS, 0x400051c8 +.set CYDEV_IO_PRT_PRT12_SIO_HYST_EN, 0x400051c9 +.set CYDEV_IO_PRT_PRT12_PRT, 0x400051ca +.set CYDEV_IO_PRT_PRT12_BIT_MASK, 0x400051cb +.set CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ, 0x400051cc +.set CYDEV_IO_PRT_PRT12_AG, 0x400051cd +.set CYDEV_IO_PRT_PRT12_SIO_CFG, 0x400051ce +.set CYDEV_IO_PRT_PRT12_SIO_DIFF, 0x400051cf +.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT15_DR, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_PS, 0x400051f1 +.set CYDEV_IO_PRT_PRT15_DM0, 0x400051f2 +.set CYDEV_IO_PRT_PRT15_DM1, 0x400051f3 +.set CYDEV_IO_PRT_PRT15_DM2, 0x400051f4 +.set CYDEV_IO_PRT_PRT15_SLW, 0x400051f5 +.set CYDEV_IO_PRT_PRT15_BYP, 0x400051f6 +.set CYDEV_IO_PRT_PRT15_BIE, 0x400051f7 +.set CYDEV_IO_PRT_PRT15_INP_DIS, 0x400051f8 +.set CYDEV_IO_PRT_PRT15_CTL, 0x400051f9 +.set CYDEV_IO_PRT_PRT15_PRT, 0x400051fa +.set CYDEV_IO_PRT_PRT15_BIT_MASK, 0x400051fb +.set CYDEV_IO_PRT_PRT15_AMUX, 0x400051fc +.set CYDEV_IO_PRT_PRT15_AG, 0x400051fd +.set CYDEV_IO_PRT_PRT15_LCD_COM_SEG, 0x400051fe +.set CYDEV_IO_PRT_PRT15_LCD_EN, 0x400051ff +.set CYDEV_PRTDSI_BASE, 0x40005200 +.set CYDEV_PRTDSI_SIZE, 0x0000007f +.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 +.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT0_OUT_SEL0, 0x40005200 +.set CYDEV_PRTDSI_PRT0_OUT_SEL1, 0x40005201 +.set CYDEV_PRTDSI_PRT0_OE_SEL0, 0x40005202 +.set CYDEV_PRTDSI_PRT0_OE_SEL1, 0x40005203 +.set CYDEV_PRTDSI_PRT0_DBL_SYNC_IN, 0x40005204 +.set CYDEV_PRTDSI_PRT0_SYNC_OUT, 0x40005205 +.set CYDEV_PRTDSI_PRT0_CAPS_SEL, 0x40005206 +.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 +.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT1_OUT_SEL0, 0x40005208 +.set CYDEV_PRTDSI_PRT1_OUT_SEL1, 0x40005209 +.set CYDEV_PRTDSI_PRT1_OE_SEL0, 0x4000520a +.set CYDEV_PRTDSI_PRT1_OE_SEL1, 0x4000520b +.set CYDEV_PRTDSI_PRT1_DBL_SYNC_IN, 0x4000520c +.set CYDEV_PRTDSI_PRT1_SYNC_OUT, 0x4000520d +.set CYDEV_PRTDSI_PRT1_CAPS_SEL, 0x4000520e +.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 +.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT2_OUT_SEL0, 0x40005210 +.set CYDEV_PRTDSI_PRT2_OUT_SEL1, 0x40005211 +.set CYDEV_PRTDSI_PRT2_OE_SEL0, 0x40005212 +.set CYDEV_PRTDSI_PRT2_OE_SEL1, 0x40005213 +.set CYDEV_PRTDSI_PRT2_DBL_SYNC_IN, 0x40005214 +.set CYDEV_PRTDSI_PRT2_SYNC_OUT, 0x40005215 +.set CYDEV_PRTDSI_PRT2_CAPS_SEL, 0x40005216 +.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 +.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT3_OUT_SEL0, 0x40005218 +.set CYDEV_PRTDSI_PRT3_OUT_SEL1, 0x40005219 +.set CYDEV_PRTDSI_PRT3_OE_SEL0, 0x4000521a +.set CYDEV_PRTDSI_PRT3_OE_SEL1, 0x4000521b +.set CYDEV_PRTDSI_PRT3_DBL_SYNC_IN, 0x4000521c +.set CYDEV_PRTDSI_PRT3_SYNC_OUT, 0x4000521d +.set CYDEV_PRTDSI_PRT3_CAPS_SEL, 0x4000521e +.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 +.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT4_OUT_SEL0, 0x40005220 +.set CYDEV_PRTDSI_PRT4_OUT_SEL1, 0x40005221 +.set CYDEV_PRTDSI_PRT4_OE_SEL0, 0x40005222 +.set CYDEV_PRTDSI_PRT4_OE_SEL1, 0x40005223 +.set CYDEV_PRTDSI_PRT4_DBL_SYNC_IN, 0x40005224 +.set CYDEV_PRTDSI_PRT4_SYNC_OUT, 0x40005225 +.set CYDEV_PRTDSI_PRT4_CAPS_SEL, 0x40005226 +.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 +.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT5_OUT_SEL0, 0x40005228 +.set CYDEV_PRTDSI_PRT5_OUT_SEL1, 0x40005229 +.set CYDEV_PRTDSI_PRT5_OE_SEL0, 0x4000522a +.set CYDEV_PRTDSI_PRT5_OE_SEL1, 0x4000522b +.set CYDEV_PRTDSI_PRT5_DBL_SYNC_IN, 0x4000522c +.set CYDEV_PRTDSI_PRT5_SYNC_OUT, 0x4000522d +.set CYDEV_PRTDSI_PRT5_CAPS_SEL, 0x4000522e +.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 +.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT6_OUT_SEL0, 0x40005230 +.set CYDEV_PRTDSI_PRT6_OUT_SEL1, 0x40005231 +.set CYDEV_PRTDSI_PRT6_OE_SEL0, 0x40005232 +.set CYDEV_PRTDSI_PRT6_OE_SEL1, 0x40005233 +.set CYDEV_PRTDSI_PRT6_DBL_SYNC_IN, 0x40005234 +.set CYDEV_PRTDSI_PRT6_SYNC_OUT, 0x40005235 +.set CYDEV_PRTDSI_PRT6_CAPS_SEL, 0x40005236 +.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 +.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 +.set CYDEV_PRTDSI_PRT12_OUT_SEL0, 0x40005260 +.set CYDEV_PRTDSI_PRT12_OUT_SEL1, 0x40005261 +.set CYDEV_PRTDSI_PRT12_OE_SEL0, 0x40005262 +.set CYDEV_PRTDSI_PRT12_OE_SEL1, 0x40005263 +.set CYDEV_PRTDSI_PRT12_DBL_SYNC_IN, 0x40005264 +.set CYDEV_PRTDSI_PRT12_SYNC_OUT, 0x40005265 +.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 +.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT15_OUT_SEL0, 0x40005278 +.set CYDEV_PRTDSI_PRT15_OUT_SEL1, 0x40005279 +.set CYDEV_PRTDSI_PRT15_OE_SEL0, 0x4000527a +.set CYDEV_PRTDSI_PRT15_OE_SEL1, 0x4000527b +.set CYDEV_PRTDSI_PRT15_DBL_SYNC_IN, 0x4000527c +.set CYDEV_PRTDSI_PRT15_SYNC_OUT, 0x4000527d +.set CYDEV_PRTDSI_PRT15_CAPS_SEL, 0x4000527e +.set CYDEV_EMIF_BASE, 0x40005400 +.set CYDEV_EMIF_SIZE, 0x00000007 +.set CYDEV_EMIF_NO_UDB, 0x40005400 +.set CYDEV_EMIF_RP_WAIT_STATES, 0x40005401 +.set CYDEV_EMIF_MEM_DWN, 0x40005402 +.set CYDEV_EMIF_MEMCLK_DIV, 0x40005403 +.set CYDEV_EMIF_CLOCK_EN, 0x40005404 +.set CYDEV_EMIF_EM_TYPE, 0x40005405 +.set CYDEV_EMIF_WP_WAIT_STATES, 0x40005406 +.set CYDEV_ANAIF_BASE, 0x40005800 +.set CYDEV_ANAIF_SIZE, 0x000003a9 +.set CYDEV_ANAIF_CFG_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f +.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC0_CR0, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_CR1, 0x40005801 +.set CYDEV_ANAIF_CFG_SC0_CR2, 0x40005802 +.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC1_CR0, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_CR1, 0x40005805 +.set CYDEV_ANAIF_CFG_SC1_CR2, 0x40005806 +.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC2_CR0, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_CR1, 0x40005809 +.set CYDEV_ANAIF_CFG_SC2_CR2, 0x4000580a +.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC3_CR0, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_CR1, 0x4000580d +.set CYDEV_ANAIF_CFG_SC3_CR2, 0x4000580e +.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC0_CR0, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_CR1, 0x40005821 +.set CYDEV_ANAIF_CFG_DAC0_TST, 0x40005822 +.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC1_CR0, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_CR1, 0x40005825 +.set CYDEV_ANAIF_CFG_DAC1_TST, 0x40005826 +.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC2_CR0, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_CR1, 0x40005829 +.set CYDEV_ANAIF_CFG_DAC2_TST, 0x4000582a +.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC3_CR0, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_CR1, 0x4000582d +.set CYDEV_ANAIF_CFG_DAC3_TST, 0x4000582e +.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP0_CR, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP1_CR, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP2_CR, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 +.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP3_CR, 0x40005843 +.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT0_CR, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_MX, 0x40005849 +.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT1_CR, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_MX, 0x4000584b +.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT2_CR, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_MX, 0x4000584d +.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT3_CR, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_MX, 0x4000584f +.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP0_CR, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_RSVD, 0x40005859 +.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP1_CR, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_RSVD, 0x4000585b +.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP2_CR, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_RSVD, 0x4000585d +.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP3_CR, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_RSVD, 0x4000585f +.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LCDDAC_CR0, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_CR1, 0x40005869 +.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_LCDDRV_CR, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b +.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_LCDTMR_CFG, 0x4000586b +.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 +.set CYDEV_ANAIF_CFG_BG_CR0, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_RSVD, 0x4000586d +.set CYDEV_ANAIF_CFG_BG_DFT0, 0x4000586e +.set CYDEV_ANAIF_CFG_BG_DFT1, 0x4000586f +.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_CAPSL_CFG0, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_CFG1, 0x40005871 +.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_CAPSR_CFG0, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_CFG1, 0x40005873 +.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_PUMP_CR0, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_CR1, 0x40005877 +.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LPF0_CR0, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_RSVD, 0x40005879 +.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LPF1_CR0, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_RSVD, 0x4000587b +.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c +.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_MISC_CR0, 0x4000587c +.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 +.set CYDEV_ANAIF_CFG_DSM0_CR0, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_CR1, 0x40005881 +.set CYDEV_ANAIF_CFG_DSM0_CR2, 0x40005882 +.set CYDEV_ANAIF_CFG_DSM0_CR3, 0x40005883 +.set CYDEV_ANAIF_CFG_DSM0_CR4, 0x40005884 +.set CYDEV_ANAIF_CFG_DSM0_CR5, 0x40005885 +.set CYDEV_ANAIF_CFG_DSM0_CR6, 0x40005886 +.set CYDEV_ANAIF_CFG_DSM0_CR7, 0x40005887 +.set CYDEV_ANAIF_CFG_DSM0_CR8, 0x40005888 +.set CYDEV_ANAIF_CFG_DSM0_CR9, 0x40005889 +.set CYDEV_ANAIF_CFG_DSM0_CR10, 0x4000588a +.set CYDEV_ANAIF_CFG_DSM0_CR11, 0x4000588b +.set CYDEV_ANAIF_CFG_DSM0_CR12, 0x4000588c +.set CYDEV_ANAIF_CFG_DSM0_CR13, 0x4000588d +.set CYDEV_ANAIF_CFG_DSM0_CR14, 0x4000588e +.set CYDEV_ANAIF_CFG_DSM0_CR15, 0x4000588f +.set CYDEV_ANAIF_CFG_DSM0_CR16, 0x40005890 +.set CYDEV_ANAIF_CFG_DSM0_CR17, 0x40005891 +.set CYDEV_ANAIF_CFG_DSM0_REF0, 0x40005892 +.set CYDEV_ANAIF_CFG_DSM0_REF1, 0x40005893 +.set CYDEV_ANAIF_CFG_DSM0_REF2, 0x40005894 +.set CYDEV_ANAIF_CFG_DSM0_REF3, 0x40005895 +.set CYDEV_ANAIF_CFG_DSM0_DEM0, 0x40005896 +.set CYDEV_ANAIF_CFG_DSM0_DEM1, 0x40005897 +.set CYDEV_ANAIF_CFG_DSM0_TST0, 0x40005898 +.set CYDEV_ANAIF_CFG_DSM0_TST1, 0x40005899 +.set CYDEV_ANAIF_CFG_DSM0_BUF0, 0x4000589a +.set CYDEV_ANAIF_CFG_DSM0_BUF1, 0x4000589b +.set CYDEV_ANAIF_CFG_DSM0_BUF2, 0x4000589c +.set CYDEV_ANAIF_CFG_DSM0_BUF3, 0x4000589d +.set CYDEV_ANAIF_CFG_DSM0_MISC, 0x4000589e +.set CYDEV_ANAIF_CFG_DSM0_RSVD1, 0x4000589f +.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 +.set CYDEV_ANAIF_CFG_SAR0_CSR0, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_CSR1, 0x40005901 +.set CYDEV_ANAIF_CFG_SAR0_CSR2, 0x40005902 +.set CYDEV_ANAIF_CFG_SAR0_CSR3, 0x40005903 +.set CYDEV_ANAIF_CFG_SAR0_CSR4, 0x40005904 +.set CYDEV_ANAIF_CFG_SAR0_CSR5, 0x40005905 +.set CYDEV_ANAIF_CFG_SAR0_CSR6, 0x40005906 +.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 +.set CYDEV_ANAIF_CFG_SAR1_CSR0, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_CSR1, 0x40005909 +.set CYDEV_ANAIF_CFG_SAR1_CSR2, 0x4000590a +.set CYDEV_ANAIF_CFG_SAR1_CSR3, 0x4000590b +.set CYDEV_ANAIF_CFG_SAR1_CSR4, 0x4000590c +.set CYDEV_ANAIF_CFG_SAR1_CSR5, 0x4000590d +.set CYDEV_ANAIF_CFG_SAR1_CSR6, 0x4000590e +.set CYDEV_ANAIF_RT_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SIZE, 0x00000162 +.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC0_SW0, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SW2, 0x40005a02 +.set CYDEV_ANAIF_RT_SC0_SW3, 0x40005a03 +.set CYDEV_ANAIF_RT_SC0_SW4, 0x40005a04 +.set CYDEV_ANAIF_RT_SC0_SW6, 0x40005a06 +.set CYDEV_ANAIF_RT_SC0_SW7, 0x40005a07 +.set CYDEV_ANAIF_RT_SC0_SW8, 0x40005a08 +.set CYDEV_ANAIF_RT_SC0_SW10, 0x40005a0a +.set CYDEV_ANAIF_RT_SC0_CLK, 0x40005a0b +.set CYDEV_ANAIF_RT_SC0_BST, 0x40005a0c +.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC1_SW0, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SW2, 0x40005a12 +.set CYDEV_ANAIF_RT_SC1_SW3, 0x40005a13 +.set CYDEV_ANAIF_RT_SC1_SW4, 0x40005a14 +.set CYDEV_ANAIF_RT_SC1_SW6, 0x40005a16 +.set CYDEV_ANAIF_RT_SC1_SW7, 0x40005a17 +.set CYDEV_ANAIF_RT_SC1_SW8, 0x40005a18 +.set CYDEV_ANAIF_RT_SC1_SW10, 0x40005a1a +.set CYDEV_ANAIF_RT_SC1_CLK, 0x40005a1b +.set CYDEV_ANAIF_RT_SC1_BST, 0x40005a1c +.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC2_SW0, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SW2, 0x40005a22 +.set CYDEV_ANAIF_RT_SC2_SW3, 0x40005a23 +.set CYDEV_ANAIF_RT_SC2_SW4, 0x40005a24 +.set CYDEV_ANAIF_RT_SC2_SW6, 0x40005a26 +.set CYDEV_ANAIF_RT_SC2_SW7, 0x40005a27 +.set CYDEV_ANAIF_RT_SC2_SW8, 0x40005a28 +.set CYDEV_ANAIF_RT_SC2_SW10, 0x40005a2a +.set CYDEV_ANAIF_RT_SC2_CLK, 0x40005a2b +.set CYDEV_ANAIF_RT_SC2_BST, 0x40005a2c +.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC3_SW0, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SW2, 0x40005a32 +.set CYDEV_ANAIF_RT_SC3_SW3, 0x40005a33 +.set CYDEV_ANAIF_RT_SC3_SW4, 0x40005a34 +.set CYDEV_ANAIF_RT_SC3_SW6, 0x40005a36 +.set CYDEV_ANAIF_RT_SC3_SW7, 0x40005a37 +.set CYDEV_ANAIF_RT_SC3_SW8, 0x40005a38 +.set CYDEV_ANAIF_RT_SC3_SW10, 0x40005a3a +.set CYDEV_ANAIF_RT_SC3_CLK, 0x40005a3b +.set CYDEV_ANAIF_RT_SC3_BST, 0x40005a3c +.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC0_SW0, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SW2, 0x40005a82 +.set CYDEV_ANAIF_RT_DAC0_SW3, 0x40005a83 +.set CYDEV_ANAIF_RT_DAC0_SW4, 0x40005a84 +.set CYDEV_ANAIF_RT_DAC0_STROBE, 0x40005a87 +.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC1_SW0, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SW2, 0x40005a8a +.set CYDEV_ANAIF_RT_DAC1_SW3, 0x40005a8b +.set CYDEV_ANAIF_RT_DAC1_SW4, 0x40005a8c +.set CYDEV_ANAIF_RT_DAC1_STROBE, 0x40005a8f +.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC2_SW0, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SW2, 0x40005a92 +.set CYDEV_ANAIF_RT_DAC2_SW3, 0x40005a93 +.set CYDEV_ANAIF_RT_DAC2_SW4, 0x40005a94 +.set CYDEV_ANAIF_RT_DAC2_STROBE, 0x40005a97 +.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC3_SW0, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SW2, 0x40005a9a +.set CYDEV_ANAIF_RT_DAC3_SW3, 0x40005a9b +.set CYDEV_ANAIF_RT_DAC3_SW4, 0x40005a9c +.set CYDEV_ANAIF_RT_DAC3_STROBE, 0x40005a9f +.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP0_SW0, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SW2, 0x40005ac2 +.set CYDEV_ANAIF_RT_CMP0_SW3, 0x40005ac3 +.set CYDEV_ANAIF_RT_CMP0_SW4, 0x40005ac4 +.set CYDEV_ANAIF_RT_CMP0_SW6, 0x40005ac6 +.set CYDEV_ANAIF_RT_CMP0_CLK, 0x40005ac7 +.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP1_SW0, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SW2, 0x40005aca +.set CYDEV_ANAIF_RT_CMP1_SW3, 0x40005acb +.set CYDEV_ANAIF_RT_CMP1_SW4, 0x40005acc +.set CYDEV_ANAIF_RT_CMP1_SW6, 0x40005ace +.set CYDEV_ANAIF_RT_CMP1_CLK, 0x40005acf +.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP2_SW0, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SW2, 0x40005ad2 +.set CYDEV_ANAIF_RT_CMP2_SW3, 0x40005ad3 +.set CYDEV_ANAIF_RT_CMP2_SW4, 0x40005ad4 +.set CYDEV_ANAIF_RT_CMP2_SW6, 0x40005ad6 +.set CYDEV_ANAIF_RT_CMP2_CLK, 0x40005ad7 +.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP3_SW0, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SW2, 0x40005ada +.set CYDEV_ANAIF_RT_CMP3_SW3, 0x40005adb +.set CYDEV_ANAIF_RT_CMP3_SW4, 0x40005adc +.set CYDEV_ANAIF_RT_CMP3_SW6, 0x40005ade +.set CYDEV_ANAIF_RT_CMP3_CLK, 0x40005adf +.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DSM0_SW0, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SW2, 0x40005b02 +.set CYDEV_ANAIF_RT_DSM0_SW3, 0x40005b03 +.set CYDEV_ANAIF_RT_DSM0_SW4, 0x40005b04 +.set CYDEV_ANAIF_RT_DSM0_SW6, 0x40005b06 +.set CYDEV_ANAIF_RT_DSM0_CLK, 0x40005b07 +.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_SAR0_SW0, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SW2, 0x40005b22 +.set CYDEV_ANAIF_RT_SAR0_SW3, 0x40005b23 +.set CYDEV_ANAIF_RT_SAR0_SW4, 0x40005b24 +.set CYDEV_ANAIF_RT_SAR0_SW6, 0x40005b26 +.set CYDEV_ANAIF_RT_SAR0_CLK, 0x40005b27 +.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_SAR1_SW0, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SW2, 0x40005b2a +.set CYDEV_ANAIF_RT_SAR1_SW3, 0x40005b2b +.set CYDEV_ANAIF_RT_SAR1_SW4, 0x40005b2c +.set CYDEV_ANAIF_RT_SAR1_SW6, 0x40005b2e +.set CYDEV_ANAIF_RT_SAR1_CLK, 0x40005b2f +.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP0_MX, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SW, 0x40005b41 +.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP1_MX, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SW, 0x40005b43 +.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP2_MX, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SW, 0x40005b45 +.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP3_MX, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SW, 0x40005b47 +.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 +.set CYDEV_ANAIF_RT_LCDDAC_SW0, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SW1, 0x40005b51 +.set CYDEV_ANAIF_RT_LCDDAC_SW2, 0x40005b52 +.set CYDEV_ANAIF_RT_LCDDAC_SW3, 0x40005b53 +.set CYDEV_ANAIF_RT_LCDDAC_SW4, 0x40005b54 +.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 +.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 +.set CYDEV_ANAIF_RT_SC_MISC, 0x40005b56 +.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 +.set CYDEV_ANAIF_RT_BUS_SW0, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SW2, 0x40005b5a +.set CYDEV_ANAIF_RT_BUS_SW3, 0x40005b5b +.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 +.set CYDEV_ANAIF_RT_DFT_CR0, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_CR1, 0x40005b5d +.set CYDEV_ANAIF_RT_DFT_CR2, 0x40005b5e +.set CYDEV_ANAIF_RT_DFT_CR3, 0x40005b5f +.set CYDEV_ANAIF_RT_DFT_CR4, 0x40005b60 +.set CYDEV_ANAIF_RT_DFT_CR5, 0x40005b61 +.set CYDEV_ANAIF_WRK_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_SIZE, 0x00000029 +.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC0_D, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC1_D, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC2_D, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 +.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC3_D, 0x40005b83 +.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_DSM0_OUT0, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_OUT1, 0x40005b89 +.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 +.set CYDEV_ANAIF_WRK_LUT_SR, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_WRK1, 0x40005b91 +.set CYDEV_ANAIF_WRK_LUT_MSK, 0x40005b92 +.set CYDEV_ANAIF_WRK_LUT_CLK, 0x40005b93 +.set CYDEV_ANAIF_WRK_LUT_CPTR, 0x40005b94 +.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_CMP_WRK, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_TST, 0x40005b97 +.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 +.set CYDEV_ANAIF_WRK_SC_SR, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_WRK1, 0x40005b99 +.set CYDEV_ANAIF_WRK_SC_MSK, 0x40005b9a +.set CYDEV_ANAIF_WRK_SC_CMPINV, 0x40005b9b +.set CYDEV_ANAIF_WRK_SC_CPTR, 0x40005b9c +.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_SAR0_WRK0, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_WRK1, 0x40005ba1 +.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_SAR1_WRK0, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_WRK1, 0x40005ba3 +.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 +.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_SARS_SOF, 0x40005ba8 +.set CYDEV_USB_BASE, 0x40006000 +.set CYDEV_USB_SIZE, 0x00000300 +.set CYDEV_USB_EP0_DR0, 0x40006000 +.set CYDEV_USB_EP0_DR1, 0x40006001 +.set CYDEV_USB_EP0_DR2, 0x40006002 +.set CYDEV_USB_EP0_DR3, 0x40006003 +.set CYDEV_USB_EP0_DR4, 0x40006004 +.set CYDEV_USB_EP0_DR5, 0x40006005 +.set CYDEV_USB_EP0_DR6, 0x40006006 +.set CYDEV_USB_EP0_DR7, 0x40006007 +.set CYDEV_USB_CR0, 0x40006008 +.set CYDEV_USB_CR1, 0x40006009 +.set CYDEV_USB_SIE_EP_INT_EN, 0x4000600a +.set CYDEV_USB_SIE_EP_INT_SR, 0x4000600b +.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c +.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP1_CNT0, 0x4000600c +.set CYDEV_USB_SIE_EP1_CNT1, 0x4000600d +.set CYDEV_USB_SIE_EP1_CR0, 0x4000600e +.set CYDEV_USB_USBIO_CR0, 0x40006010 +.set CYDEV_USB_USBIO_CR1, 0x40006012 +.set CYDEV_USB_DYN_RECONFIG, 0x40006014 +.set CYDEV_USB_SOF0, 0x40006018 +.set CYDEV_USB_SOF1, 0x40006019 +.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c +.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP2_CNT0, 0x4000601c +.set CYDEV_USB_SIE_EP2_CNT1, 0x4000601d +.set CYDEV_USB_SIE_EP2_CR0, 0x4000601e +.set CYDEV_USB_EP0_CR, 0x40006028 +.set CYDEV_USB_EP0_CNT, 0x40006029 +.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c +.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP3_CNT0, 0x4000602c +.set CYDEV_USB_SIE_EP3_CNT1, 0x4000602d +.set CYDEV_USB_SIE_EP3_CR0, 0x4000602e +.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c +.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP4_CNT0, 0x4000603c +.set CYDEV_USB_SIE_EP4_CNT1, 0x4000603d +.set CYDEV_USB_SIE_EP4_CR0, 0x4000603e +.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c +.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP5_CNT0, 0x4000604c +.set CYDEV_USB_SIE_EP5_CNT1, 0x4000604d +.set CYDEV_USB_SIE_EP5_CR0, 0x4000604e +.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c +.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP6_CNT0, 0x4000605c +.set CYDEV_USB_SIE_EP6_CNT1, 0x4000605d +.set CYDEV_USB_SIE_EP6_CR0, 0x4000605e +.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c +.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP7_CNT0, 0x4000606c +.set CYDEV_USB_SIE_EP7_CNT1, 0x4000606d +.set CYDEV_USB_SIE_EP7_CR0, 0x4000606e +.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c +.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP8_CNT0, 0x4000607c +.set CYDEV_USB_SIE_EP8_CNT1, 0x4000607d +.set CYDEV_USB_SIE_EP8_CR0, 0x4000607e +.set CYDEV_USB_ARB_EP1_BASE, 0x40006080 +.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP1_CFG, 0x40006080 +.set CYDEV_USB_ARB_EP1_INT_EN, 0x40006081 +.set CYDEV_USB_ARB_EP1_SR, 0x40006082 +.set CYDEV_USB_ARB_RW1_BASE, 0x40006084 +.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW1_WA, 0x40006084 +.set CYDEV_USB_ARB_RW1_WA_MSB, 0x40006085 +.set CYDEV_USB_ARB_RW1_RA, 0x40006086 +.set CYDEV_USB_ARB_RW1_RA_MSB, 0x40006087 +.set CYDEV_USB_ARB_RW1_DR, 0x40006088 +.set CYDEV_USB_BUF_SIZE, 0x4000608c +.set CYDEV_USB_EP_ACTIVE, 0x4000608e +.set CYDEV_USB_EP_TYPE, 0x4000608f +.set CYDEV_USB_ARB_EP2_BASE, 0x40006090 +.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP2_CFG, 0x40006090 +.set CYDEV_USB_ARB_EP2_INT_EN, 0x40006091 +.set CYDEV_USB_ARB_EP2_SR, 0x40006092 +.set CYDEV_USB_ARB_RW2_BASE, 0x40006094 +.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW2_WA, 0x40006094 +.set CYDEV_USB_ARB_RW2_WA_MSB, 0x40006095 +.set CYDEV_USB_ARB_RW2_RA, 0x40006096 +.set CYDEV_USB_ARB_RW2_RA_MSB, 0x40006097 +.set CYDEV_USB_ARB_RW2_DR, 0x40006098 +.set CYDEV_USB_ARB_CFG, 0x4000609c +.set CYDEV_USB_USB_CLK_EN, 0x4000609d +.set CYDEV_USB_ARB_INT_EN, 0x4000609e +.set CYDEV_USB_ARB_INT_SR, 0x4000609f +.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 +.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP3_CFG, 0x400060a0 +.set CYDEV_USB_ARB_EP3_INT_EN, 0x400060a1 +.set CYDEV_USB_ARB_EP3_SR, 0x400060a2 +.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 +.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW3_WA, 0x400060a4 +.set CYDEV_USB_ARB_RW3_WA_MSB, 0x400060a5 +.set CYDEV_USB_ARB_RW3_RA, 0x400060a6 +.set CYDEV_USB_ARB_RW3_RA_MSB, 0x400060a7 +.set CYDEV_USB_ARB_RW3_DR, 0x400060a8 +.set CYDEV_USB_CWA, 0x400060ac +.set CYDEV_USB_CWA_MSB, 0x400060ad +.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 +.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP4_CFG, 0x400060b0 +.set CYDEV_USB_ARB_EP4_INT_EN, 0x400060b1 +.set CYDEV_USB_ARB_EP4_SR, 0x400060b2 +.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 +.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW4_WA, 0x400060b4 +.set CYDEV_USB_ARB_RW4_WA_MSB, 0x400060b5 +.set CYDEV_USB_ARB_RW4_RA, 0x400060b6 +.set CYDEV_USB_ARB_RW4_RA_MSB, 0x400060b7 +.set CYDEV_USB_ARB_RW4_DR, 0x400060b8 +.set CYDEV_USB_DMA_THRES, 0x400060bc +.set CYDEV_USB_DMA_THRES_MSB, 0x400060bd +.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 +.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP5_CFG, 0x400060c0 +.set CYDEV_USB_ARB_EP5_INT_EN, 0x400060c1 +.set CYDEV_USB_ARB_EP5_SR, 0x400060c2 +.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 +.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW5_WA, 0x400060c4 +.set CYDEV_USB_ARB_RW5_WA_MSB, 0x400060c5 +.set CYDEV_USB_ARB_RW5_RA, 0x400060c6 +.set CYDEV_USB_ARB_RW5_RA_MSB, 0x400060c7 +.set CYDEV_USB_ARB_RW5_DR, 0x400060c8 +.set CYDEV_USB_BUS_RST_CNT, 0x400060cc +.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 +.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP6_CFG, 0x400060d0 +.set CYDEV_USB_ARB_EP6_INT_EN, 0x400060d1 +.set CYDEV_USB_ARB_EP6_SR, 0x400060d2 +.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 +.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW6_WA, 0x400060d4 +.set CYDEV_USB_ARB_RW6_WA_MSB, 0x400060d5 +.set CYDEV_USB_ARB_RW6_RA, 0x400060d6 +.set CYDEV_USB_ARB_RW6_RA_MSB, 0x400060d7 +.set CYDEV_USB_ARB_RW6_DR, 0x400060d8 +.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 +.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP7_CFG, 0x400060e0 +.set CYDEV_USB_ARB_EP7_INT_EN, 0x400060e1 +.set CYDEV_USB_ARB_EP7_SR, 0x400060e2 +.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 +.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW7_WA, 0x400060e4 +.set CYDEV_USB_ARB_RW7_WA_MSB, 0x400060e5 +.set CYDEV_USB_ARB_RW7_RA, 0x400060e6 +.set CYDEV_USB_ARB_RW7_RA_MSB, 0x400060e7 +.set CYDEV_USB_ARB_RW7_DR, 0x400060e8 +.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 +.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP8_CFG, 0x400060f0 +.set CYDEV_USB_ARB_EP8_INT_EN, 0x400060f1 +.set CYDEV_USB_ARB_EP8_SR, 0x400060f2 +.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 +.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW8_WA, 0x400060f4 +.set CYDEV_USB_ARB_RW8_WA_MSB, 0x400060f5 +.set CYDEV_USB_ARB_RW8_RA, 0x400060f6 +.set CYDEV_USB_ARB_RW8_RA_MSB, 0x400060f7 +.set CYDEV_USB_ARB_RW8_DR, 0x400060f8 +.set CYDEV_USB_MEM_BASE, 0x40006100 +.set CYDEV_USB_MEM_SIZE, 0x00000200 +.set CYDEV_USB_MEM_DATA_MBASE, 0x40006100 +.set CYDEV_USB_MEM_DATA_MSIZE, 0x00000200 +.set CYDEV_UWRK_BASE, 0x40006400 +.set CYDEV_UWRK_SIZE, 0x00000b60 +.set CYDEV_UWRK_UWRK8_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 +.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 +.set CYDEV_UWRK_UWRK8_B0_UDB00_A0, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_UDB01_A0, 0x40006401 +.set CYDEV_UWRK_UWRK8_B0_UDB02_A0, 0x40006402 +.set CYDEV_UWRK_UWRK8_B0_UDB03_A0, 0x40006403 +.set CYDEV_UWRK_UWRK8_B0_UDB04_A0, 0x40006404 +.set CYDEV_UWRK_UWRK8_B0_UDB05_A0, 0x40006405 +.set CYDEV_UWRK_UWRK8_B0_UDB06_A0, 0x40006406 +.set CYDEV_UWRK_UWRK8_B0_UDB07_A0, 0x40006407 +.set CYDEV_UWRK_UWRK8_B0_UDB08_A0, 0x40006408 +.set CYDEV_UWRK_UWRK8_B0_UDB09_A0, 0x40006409 +.set CYDEV_UWRK_UWRK8_B0_UDB10_A0, 0x4000640a +.set CYDEV_UWRK_UWRK8_B0_UDB11_A0, 0x4000640b +.set CYDEV_UWRK_UWRK8_B0_UDB12_A0, 0x4000640c +.set CYDEV_UWRK_UWRK8_B0_UDB13_A0, 0x4000640d +.set CYDEV_UWRK_UWRK8_B0_UDB14_A0, 0x4000640e +.set CYDEV_UWRK_UWRK8_B0_UDB15_A0, 0x4000640f +.set CYDEV_UWRK_UWRK8_B0_UDB00_A1, 0x40006410 +.set CYDEV_UWRK_UWRK8_B0_UDB01_A1, 0x40006411 +.set CYDEV_UWRK_UWRK8_B0_UDB02_A1, 0x40006412 +.set CYDEV_UWRK_UWRK8_B0_UDB03_A1, 0x40006413 +.set CYDEV_UWRK_UWRK8_B0_UDB04_A1, 0x40006414 +.set CYDEV_UWRK_UWRK8_B0_UDB05_A1, 0x40006415 +.set CYDEV_UWRK_UWRK8_B0_UDB06_A1, 0x40006416 +.set CYDEV_UWRK_UWRK8_B0_UDB07_A1, 0x40006417 +.set CYDEV_UWRK_UWRK8_B0_UDB08_A1, 0x40006418 +.set CYDEV_UWRK_UWRK8_B0_UDB09_A1, 0x40006419 +.set CYDEV_UWRK_UWRK8_B0_UDB10_A1, 0x4000641a +.set CYDEV_UWRK_UWRK8_B0_UDB11_A1, 0x4000641b +.set CYDEV_UWRK_UWRK8_B0_UDB12_A1, 0x4000641c +.set CYDEV_UWRK_UWRK8_B0_UDB13_A1, 0x4000641d +.set CYDEV_UWRK_UWRK8_B0_UDB14_A1, 0x4000641e +.set CYDEV_UWRK_UWRK8_B0_UDB15_A1, 0x4000641f +.set CYDEV_UWRK_UWRK8_B0_UDB00_D0, 0x40006420 +.set CYDEV_UWRK_UWRK8_B0_UDB01_D0, 0x40006421 +.set CYDEV_UWRK_UWRK8_B0_UDB02_D0, 0x40006422 +.set CYDEV_UWRK_UWRK8_B0_UDB03_D0, 0x40006423 +.set CYDEV_UWRK_UWRK8_B0_UDB04_D0, 0x40006424 +.set CYDEV_UWRK_UWRK8_B0_UDB05_D0, 0x40006425 +.set CYDEV_UWRK_UWRK8_B0_UDB06_D0, 0x40006426 +.set CYDEV_UWRK_UWRK8_B0_UDB07_D0, 0x40006427 +.set CYDEV_UWRK_UWRK8_B0_UDB08_D0, 0x40006428 +.set CYDEV_UWRK_UWRK8_B0_UDB09_D0, 0x40006429 +.set CYDEV_UWRK_UWRK8_B0_UDB10_D0, 0x4000642a +.set CYDEV_UWRK_UWRK8_B0_UDB11_D0, 0x4000642b +.set CYDEV_UWRK_UWRK8_B0_UDB12_D0, 0x4000642c +.set CYDEV_UWRK_UWRK8_B0_UDB13_D0, 0x4000642d +.set CYDEV_UWRK_UWRK8_B0_UDB14_D0, 0x4000642e +.set CYDEV_UWRK_UWRK8_B0_UDB15_D0, 0x4000642f +.set CYDEV_UWRK_UWRK8_B0_UDB00_D1, 0x40006430 +.set CYDEV_UWRK_UWRK8_B0_UDB01_D1, 0x40006431 +.set CYDEV_UWRK_UWRK8_B0_UDB02_D1, 0x40006432 +.set CYDEV_UWRK_UWRK8_B0_UDB03_D1, 0x40006433 +.set CYDEV_UWRK_UWRK8_B0_UDB04_D1, 0x40006434 +.set CYDEV_UWRK_UWRK8_B0_UDB05_D1, 0x40006435 +.set CYDEV_UWRK_UWRK8_B0_UDB06_D1, 0x40006436 +.set CYDEV_UWRK_UWRK8_B0_UDB07_D1, 0x40006437 +.set CYDEV_UWRK_UWRK8_B0_UDB08_D1, 0x40006438 +.set CYDEV_UWRK_UWRK8_B0_UDB09_D1, 0x40006439 +.set CYDEV_UWRK_UWRK8_B0_UDB10_D1, 0x4000643a +.set CYDEV_UWRK_UWRK8_B0_UDB11_D1, 0x4000643b +.set CYDEV_UWRK_UWRK8_B0_UDB12_D1, 0x4000643c +.set CYDEV_UWRK_UWRK8_B0_UDB13_D1, 0x4000643d +.set CYDEV_UWRK_UWRK8_B0_UDB14_D1, 0x4000643e +.set CYDEV_UWRK_UWRK8_B0_UDB15_D1, 0x4000643f +.set CYDEV_UWRK_UWRK8_B0_UDB00_F0, 0x40006440 +.set CYDEV_UWRK_UWRK8_B0_UDB01_F0, 0x40006441 +.set CYDEV_UWRK_UWRK8_B0_UDB02_F0, 0x40006442 +.set CYDEV_UWRK_UWRK8_B0_UDB03_F0, 0x40006443 +.set CYDEV_UWRK_UWRK8_B0_UDB04_F0, 0x40006444 +.set CYDEV_UWRK_UWRK8_B0_UDB05_F0, 0x40006445 +.set CYDEV_UWRK_UWRK8_B0_UDB06_F0, 0x40006446 +.set CYDEV_UWRK_UWRK8_B0_UDB07_F0, 0x40006447 +.set CYDEV_UWRK_UWRK8_B0_UDB08_F0, 0x40006448 +.set CYDEV_UWRK_UWRK8_B0_UDB09_F0, 0x40006449 +.set CYDEV_UWRK_UWRK8_B0_UDB10_F0, 0x4000644a +.set CYDEV_UWRK_UWRK8_B0_UDB11_F0, 0x4000644b +.set CYDEV_UWRK_UWRK8_B0_UDB12_F0, 0x4000644c +.set CYDEV_UWRK_UWRK8_B0_UDB13_F0, 0x4000644d +.set CYDEV_UWRK_UWRK8_B0_UDB14_F0, 0x4000644e +.set CYDEV_UWRK_UWRK8_B0_UDB15_F0, 0x4000644f +.set CYDEV_UWRK_UWRK8_B0_UDB00_F1, 0x40006450 +.set CYDEV_UWRK_UWRK8_B0_UDB01_F1, 0x40006451 +.set CYDEV_UWRK_UWRK8_B0_UDB02_F1, 0x40006452 +.set CYDEV_UWRK_UWRK8_B0_UDB03_F1, 0x40006453 +.set CYDEV_UWRK_UWRK8_B0_UDB04_F1, 0x40006454 +.set CYDEV_UWRK_UWRK8_B0_UDB05_F1, 0x40006455 +.set CYDEV_UWRK_UWRK8_B0_UDB06_F1, 0x40006456 +.set CYDEV_UWRK_UWRK8_B0_UDB07_F1, 0x40006457 +.set CYDEV_UWRK_UWRK8_B0_UDB08_F1, 0x40006458 +.set CYDEV_UWRK_UWRK8_B0_UDB09_F1, 0x40006459 +.set CYDEV_UWRK_UWRK8_B0_UDB10_F1, 0x4000645a +.set CYDEV_UWRK_UWRK8_B0_UDB11_F1, 0x4000645b +.set CYDEV_UWRK_UWRK8_B0_UDB12_F1, 0x4000645c +.set CYDEV_UWRK_UWRK8_B0_UDB13_F1, 0x4000645d +.set CYDEV_UWRK_UWRK8_B0_UDB14_F1, 0x4000645e +.set CYDEV_UWRK_UWRK8_B0_UDB15_F1, 0x4000645f +.set CYDEV_UWRK_UWRK8_B0_UDB00_ST, 0x40006460 +.set CYDEV_UWRK_UWRK8_B0_UDB01_ST, 0x40006461 +.set CYDEV_UWRK_UWRK8_B0_UDB02_ST, 0x40006462 +.set CYDEV_UWRK_UWRK8_B0_UDB03_ST, 0x40006463 +.set CYDEV_UWRK_UWRK8_B0_UDB04_ST, 0x40006464 +.set CYDEV_UWRK_UWRK8_B0_UDB05_ST, 0x40006465 +.set CYDEV_UWRK_UWRK8_B0_UDB06_ST, 0x40006466 +.set CYDEV_UWRK_UWRK8_B0_UDB07_ST, 0x40006467 +.set CYDEV_UWRK_UWRK8_B0_UDB08_ST, 0x40006468 +.set CYDEV_UWRK_UWRK8_B0_UDB09_ST, 0x40006469 +.set CYDEV_UWRK_UWRK8_B0_UDB10_ST, 0x4000646a +.set CYDEV_UWRK_UWRK8_B0_UDB11_ST, 0x4000646b +.set CYDEV_UWRK_UWRK8_B0_UDB12_ST, 0x4000646c +.set CYDEV_UWRK_UWRK8_B0_UDB13_ST, 0x4000646d +.set CYDEV_UWRK_UWRK8_B0_UDB14_ST, 0x4000646e +.set CYDEV_UWRK_UWRK8_B0_UDB15_ST, 0x4000646f +.set CYDEV_UWRK_UWRK8_B0_UDB00_CTL, 0x40006470 +.set CYDEV_UWRK_UWRK8_B0_UDB01_CTL, 0x40006471 +.set CYDEV_UWRK_UWRK8_B0_UDB02_CTL, 0x40006472 +.set CYDEV_UWRK_UWRK8_B0_UDB03_CTL, 0x40006473 +.set CYDEV_UWRK_UWRK8_B0_UDB04_CTL, 0x40006474 +.set CYDEV_UWRK_UWRK8_B0_UDB05_CTL, 0x40006475 +.set CYDEV_UWRK_UWRK8_B0_UDB06_CTL, 0x40006476 +.set CYDEV_UWRK_UWRK8_B0_UDB07_CTL, 0x40006477 +.set CYDEV_UWRK_UWRK8_B0_UDB08_CTL, 0x40006478 +.set CYDEV_UWRK_UWRK8_B0_UDB09_CTL, 0x40006479 +.set CYDEV_UWRK_UWRK8_B0_UDB10_CTL, 0x4000647a +.set CYDEV_UWRK_UWRK8_B0_UDB11_CTL, 0x4000647b +.set CYDEV_UWRK_UWRK8_B0_UDB12_CTL, 0x4000647c +.set CYDEV_UWRK_UWRK8_B0_UDB13_CTL, 0x4000647d +.set CYDEV_UWRK_UWRK8_B0_UDB14_CTL, 0x4000647e +.set CYDEV_UWRK_UWRK8_B0_UDB15_CTL, 0x4000647f +.set CYDEV_UWRK_UWRK8_B0_UDB00_MSK, 0x40006480 +.set CYDEV_UWRK_UWRK8_B0_UDB01_MSK, 0x40006481 +.set CYDEV_UWRK_UWRK8_B0_UDB02_MSK, 0x40006482 +.set CYDEV_UWRK_UWRK8_B0_UDB03_MSK, 0x40006483 +.set CYDEV_UWRK_UWRK8_B0_UDB04_MSK, 0x40006484 +.set CYDEV_UWRK_UWRK8_B0_UDB05_MSK, 0x40006485 +.set CYDEV_UWRK_UWRK8_B0_UDB06_MSK, 0x40006486 +.set CYDEV_UWRK_UWRK8_B0_UDB07_MSK, 0x40006487 +.set CYDEV_UWRK_UWRK8_B0_UDB08_MSK, 0x40006488 +.set CYDEV_UWRK_UWRK8_B0_UDB09_MSK, 0x40006489 +.set CYDEV_UWRK_UWRK8_B0_UDB10_MSK, 0x4000648a +.set CYDEV_UWRK_UWRK8_B0_UDB11_MSK, 0x4000648b +.set CYDEV_UWRK_UWRK8_B0_UDB12_MSK, 0x4000648c +.set CYDEV_UWRK_UWRK8_B0_UDB13_MSK, 0x4000648d +.set CYDEV_UWRK_UWRK8_B0_UDB14_MSK, 0x4000648e +.set CYDEV_UWRK_UWRK8_B0_UDB15_MSK, 0x4000648f +.set CYDEV_UWRK_UWRK8_B0_UDB00_ACTL, 0x40006490 +.set CYDEV_UWRK_UWRK8_B0_UDB01_ACTL, 0x40006491 +.set CYDEV_UWRK_UWRK8_B0_UDB02_ACTL, 0x40006492 +.set CYDEV_UWRK_UWRK8_B0_UDB03_ACTL, 0x40006493 +.set CYDEV_UWRK_UWRK8_B0_UDB04_ACTL, 0x40006494 +.set CYDEV_UWRK_UWRK8_B0_UDB05_ACTL, 0x40006495 +.set CYDEV_UWRK_UWRK8_B0_UDB06_ACTL, 0x40006496 +.set CYDEV_UWRK_UWRK8_B0_UDB07_ACTL, 0x40006497 +.set CYDEV_UWRK_UWRK8_B0_UDB08_ACTL, 0x40006498 +.set CYDEV_UWRK_UWRK8_B0_UDB09_ACTL, 0x40006499 +.set CYDEV_UWRK_UWRK8_B0_UDB10_ACTL, 0x4000649a +.set CYDEV_UWRK_UWRK8_B0_UDB11_ACTL, 0x4000649b +.set CYDEV_UWRK_UWRK8_B0_UDB12_ACTL, 0x4000649c +.set CYDEV_UWRK_UWRK8_B0_UDB13_ACTL, 0x4000649d +.set CYDEV_UWRK_UWRK8_B0_UDB14_ACTL, 0x4000649e +.set CYDEV_UWRK_UWRK8_B0_UDB15_ACTL, 0x4000649f +.set CYDEV_UWRK_UWRK8_B0_UDB00_MC, 0x400064a0 +.set CYDEV_UWRK_UWRK8_B0_UDB01_MC, 0x400064a1 +.set CYDEV_UWRK_UWRK8_B0_UDB02_MC, 0x400064a2 +.set CYDEV_UWRK_UWRK8_B0_UDB03_MC, 0x400064a3 +.set CYDEV_UWRK_UWRK8_B0_UDB04_MC, 0x400064a4 +.set CYDEV_UWRK_UWRK8_B0_UDB05_MC, 0x400064a5 +.set CYDEV_UWRK_UWRK8_B0_UDB06_MC, 0x400064a6 +.set CYDEV_UWRK_UWRK8_B0_UDB07_MC, 0x400064a7 +.set CYDEV_UWRK_UWRK8_B0_UDB08_MC, 0x400064a8 +.set CYDEV_UWRK_UWRK8_B0_UDB09_MC, 0x400064a9 +.set CYDEV_UWRK_UWRK8_B0_UDB10_MC, 0x400064aa +.set CYDEV_UWRK_UWRK8_B0_UDB11_MC, 0x400064ab +.set CYDEV_UWRK_UWRK8_B0_UDB12_MC, 0x400064ac +.set CYDEV_UWRK_UWRK8_B0_UDB13_MC, 0x400064ad +.set CYDEV_UWRK_UWRK8_B0_UDB14_MC, 0x400064ae +.set CYDEV_UWRK_UWRK8_B0_UDB15_MC, 0x400064af +.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 +.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 +.set CYDEV_UWRK_UWRK8_B1_UDB04_A0, 0x40006504 +.set CYDEV_UWRK_UWRK8_B1_UDB05_A0, 0x40006505 +.set CYDEV_UWRK_UWRK8_B1_UDB06_A0, 0x40006506 +.set CYDEV_UWRK_UWRK8_B1_UDB07_A0, 0x40006507 +.set CYDEV_UWRK_UWRK8_B1_UDB08_A0, 0x40006508 +.set CYDEV_UWRK_UWRK8_B1_UDB09_A0, 0x40006509 +.set CYDEV_UWRK_UWRK8_B1_UDB10_A0, 0x4000650a +.set CYDEV_UWRK_UWRK8_B1_UDB11_A0, 0x4000650b +.set CYDEV_UWRK_UWRK8_B1_UDB04_A1, 0x40006514 +.set CYDEV_UWRK_UWRK8_B1_UDB05_A1, 0x40006515 +.set CYDEV_UWRK_UWRK8_B1_UDB06_A1, 0x40006516 +.set CYDEV_UWRK_UWRK8_B1_UDB07_A1, 0x40006517 +.set CYDEV_UWRK_UWRK8_B1_UDB08_A1, 0x40006518 +.set CYDEV_UWRK_UWRK8_B1_UDB09_A1, 0x40006519 +.set CYDEV_UWRK_UWRK8_B1_UDB10_A1, 0x4000651a +.set CYDEV_UWRK_UWRK8_B1_UDB11_A1, 0x4000651b +.set CYDEV_UWRK_UWRK8_B1_UDB04_D0, 0x40006524 +.set CYDEV_UWRK_UWRK8_B1_UDB05_D0, 0x40006525 +.set CYDEV_UWRK_UWRK8_B1_UDB06_D0, 0x40006526 +.set CYDEV_UWRK_UWRK8_B1_UDB07_D0, 0x40006527 +.set CYDEV_UWRK_UWRK8_B1_UDB08_D0, 0x40006528 +.set CYDEV_UWRK_UWRK8_B1_UDB09_D0, 0x40006529 +.set CYDEV_UWRK_UWRK8_B1_UDB10_D0, 0x4000652a +.set CYDEV_UWRK_UWRK8_B1_UDB11_D0, 0x4000652b +.set CYDEV_UWRK_UWRK8_B1_UDB04_D1, 0x40006534 +.set CYDEV_UWRK_UWRK8_B1_UDB05_D1, 0x40006535 +.set CYDEV_UWRK_UWRK8_B1_UDB06_D1, 0x40006536 +.set CYDEV_UWRK_UWRK8_B1_UDB07_D1, 0x40006537 +.set CYDEV_UWRK_UWRK8_B1_UDB08_D1, 0x40006538 +.set CYDEV_UWRK_UWRK8_B1_UDB09_D1, 0x40006539 +.set CYDEV_UWRK_UWRK8_B1_UDB10_D1, 0x4000653a +.set CYDEV_UWRK_UWRK8_B1_UDB11_D1, 0x4000653b +.set CYDEV_UWRK_UWRK8_B1_UDB04_F0, 0x40006544 +.set CYDEV_UWRK_UWRK8_B1_UDB05_F0, 0x40006545 +.set CYDEV_UWRK_UWRK8_B1_UDB06_F0, 0x40006546 +.set CYDEV_UWRK_UWRK8_B1_UDB07_F0, 0x40006547 +.set CYDEV_UWRK_UWRK8_B1_UDB08_F0, 0x40006548 +.set CYDEV_UWRK_UWRK8_B1_UDB09_F0, 0x40006549 +.set CYDEV_UWRK_UWRK8_B1_UDB10_F0, 0x4000654a +.set CYDEV_UWRK_UWRK8_B1_UDB11_F0, 0x4000654b +.set CYDEV_UWRK_UWRK8_B1_UDB04_F1, 0x40006554 +.set CYDEV_UWRK_UWRK8_B1_UDB05_F1, 0x40006555 +.set CYDEV_UWRK_UWRK8_B1_UDB06_F1, 0x40006556 +.set CYDEV_UWRK_UWRK8_B1_UDB07_F1, 0x40006557 +.set CYDEV_UWRK_UWRK8_B1_UDB08_F1, 0x40006558 +.set CYDEV_UWRK_UWRK8_B1_UDB09_F1, 0x40006559 +.set CYDEV_UWRK_UWRK8_B1_UDB10_F1, 0x4000655a +.set CYDEV_UWRK_UWRK8_B1_UDB11_F1, 0x4000655b +.set CYDEV_UWRK_UWRK8_B1_UDB04_ST, 0x40006564 +.set CYDEV_UWRK_UWRK8_B1_UDB05_ST, 0x40006565 +.set CYDEV_UWRK_UWRK8_B1_UDB06_ST, 0x40006566 +.set CYDEV_UWRK_UWRK8_B1_UDB07_ST, 0x40006567 +.set CYDEV_UWRK_UWRK8_B1_UDB08_ST, 0x40006568 +.set CYDEV_UWRK_UWRK8_B1_UDB09_ST, 0x40006569 +.set CYDEV_UWRK_UWRK8_B1_UDB10_ST, 0x4000656a +.set CYDEV_UWRK_UWRK8_B1_UDB11_ST, 0x4000656b +.set CYDEV_UWRK_UWRK8_B1_UDB04_CTL, 0x40006574 +.set CYDEV_UWRK_UWRK8_B1_UDB05_CTL, 0x40006575 +.set CYDEV_UWRK_UWRK8_B1_UDB06_CTL, 0x40006576 +.set CYDEV_UWRK_UWRK8_B1_UDB07_CTL, 0x40006577 +.set CYDEV_UWRK_UWRK8_B1_UDB08_CTL, 0x40006578 +.set CYDEV_UWRK_UWRK8_B1_UDB09_CTL, 0x40006579 +.set CYDEV_UWRK_UWRK8_B1_UDB10_CTL, 0x4000657a +.set CYDEV_UWRK_UWRK8_B1_UDB11_CTL, 0x4000657b +.set CYDEV_UWRK_UWRK8_B1_UDB04_MSK, 0x40006584 +.set CYDEV_UWRK_UWRK8_B1_UDB05_MSK, 0x40006585 +.set CYDEV_UWRK_UWRK8_B1_UDB06_MSK, 0x40006586 +.set CYDEV_UWRK_UWRK8_B1_UDB07_MSK, 0x40006587 +.set CYDEV_UWRK_UWRK8_B1_UDB08_MSK, 0x40006588 +.set CYDEV_UWRK_UWRK8_B1_UDB09_MSK, 0x40006589 +.set CYDEV_UWRK_UWRK8_B1_UDB10_MSK, 0x4000658a +.set CYDEV_UWRK_UWRK8_B1_UDB11_MSK, 0x4000658b +.set CYDEV_UWRK_UWRK8_B1_UDB04_ACTL, 0x40006594 +.set CYDEV_UWRK_UWRK8_B1_UDB05_ACTL, 0x40006595 +.set CYDEV_UWRK_UWRK8_B1_UDB06_ACTL, 0x40006596 +.set CYDEV_UWRK_UWRK8_B1_UDB07_ACTL, 0x40006597 +.set CYDEV_UWRK_UWRK8_B1_UDB08_ACTL, 0x40006598 +.set CYDEV_UWRK_UWRK8_B1_UDB09_ACTL, 0x40006599 +.set CYDEV_UWRK_UWRK8_B1_UDB10_ACTL, 0x4000659a +.set CYDEV_UWRK_UWRK8_B1_UDB11_ACTL, 0x4000659b +.set CYDEV_UWRK_UWRK8_B1_UDB04_MC, 0x400065a4 +.set CYDEV_UWRK_UWRK8_B1_UDB05_MC, 0x400065a5 +.set CYDEV_UWRK_UWRK8_B1_UDB06_MC, 0x400065a6 +.set CYDEV_UWRK_UWRK8_B1_UDB07_MC, 0x400065a7 +.set CYDEV_UWRK_UWRK8_B1_UDB08_MC, 0x400065a8 +.set CYDEV_UWRK_UWRK8_B1_UDB09_MC, 0x400065a9 +.set CYDEV_UWRK_UWRK8_B1_UDB10_MC, 0x400065aa +.set CYDEV_UWRK_UWRK8_B1_UDB11_MC, 0x400065ab +.set CYDEV_UWRK_UWRK16_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1, 0x40006802 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1, 0x40006804 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1, 0x40006806 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1, 0x40006808 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1, 0x4000680a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1, 0x4000680c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1, 0x4000680e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1, 0x40006810 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1, 0x40006812 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1, 0x40006814 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1, 0x40006816 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1, 0x40006818 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1, 0x4000681a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1, 0x4000681c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1, 0x4000681e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1, 0x40006840 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1, 0x40006842 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1, 0x40006844 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1, 0x40006846 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1, 0x40006848 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1, 0x4000684a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1, 0x4000684c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1, 0x4000684e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1, 0x40006850 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1, 0x40006852 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1, 0x40006854 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1, 0x40006856 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1, 0x40006858 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1, 0x4000685a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1, 0x4000685c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1, 0x4000685e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1, 0x40006880 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1, 0x40006882 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1, 0x40006884 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1, 0x40006886 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1, 0x40006888 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1, 0x4000688a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1, 0x4000688c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1, 0x4000688e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1, 0x40006890 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1, 0x40006892 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1, 0x40006894 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1, 0x40006896 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1, 0x40006898 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1, 0x4000689a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1, 0x4000689c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1, 0x4000689e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL, 0x400068c0 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL, 0x400068c2 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL, 0x400068c4 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL, 0x400068c6 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL, 0x400068c8 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL, 0x400068ca +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL, 0x400068cc +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL, 0x400068ce +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL, 0x400068d0 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL, 0x400068d2 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL, 0x400068d4 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL, 0x400068d6 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL, 0x400068d8 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL, 0x400068da +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL, 0x400068dc +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL, 0x400068de +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL, 0x40006900 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL, 0x40006902 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL, 0x40006904 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL, 0x40006906 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL, 0x40006908 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL, 0x4000690a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL, 0x4000690c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL, 0x4000690e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL, 0x40006910 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL, 0x40006912 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL, 0x40006914 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL, 0x40006916 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL, 0x40006918 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL, 0x4000691a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL, 0x4000691c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL, 0x4000691e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00, 0x40006940 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00, 0x40006942 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00, 0x40006944 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00, 0x40006946 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00, 0x40006948 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00, 0x4000694a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00, 0x4000694c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00, 0x4000694e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00, 0x40006950 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00, 0x40006952 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00, 0x40006954 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00, 0x40006956 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00, 0x40006958 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00, 0x4000695a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00, 0x4000695c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00, 0x4000695e +.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1, 0x40006a08 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1, 0x40006a0a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1, 0x40006a0c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1, 0x40006a0e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1, 0x40006a10 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1, 0x40006a12 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1, 0x40006a14 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1, 0x40006a16 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1, 0x40006a48 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1, 0x40006a4a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1, 0x40006a4c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1, 0x40006a4e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1, 0x40006a50 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1, 0x40006a52 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1, 0x40006a54 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1, 0x40006a56 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1, 0x40006a88 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1, 0x40006a8a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1, 0x40006a8c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1, 0x40006a8e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1, 0x40006a90 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1, 0x40006a92 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1, 0x40006a94 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1, 0x40006a96 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL, 0x40006ac8 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL, 0x40006aca +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL, 0x40006acc +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL, 0x40006ace +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL, 0x40006ad0 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL, 0x40006ad2 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL, 0x40006ad4 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL, 0x40006ad6 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL, 0x40006b08 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL, 0x40006b0a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL, 0x40006b0c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL, 0x40006b0e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL, 0x40006b10 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL, 0x40006b12 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL, 0x40006b14 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL, 0x40006b16 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00, 0x40006b48 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00, 0x40006b4a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00, 0x40006b4c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00, 0x40006b4e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00, 0x40006b50 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00, 0x40006b52 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00, 0x40006b54 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00, 0x40006b56 +.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e +.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0, 0x40006802 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0, 0x40006804 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0, 0x40006806 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0, 0x40006808 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0, 0x4000680a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0, 0x4000680c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0, 0x4000680e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0, 0x40006810 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0, 0x40006812 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0, 0x40006814 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0, 0x40006816 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0, 0x40006818 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0, 0x4000681a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0, 0x4000681c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1, 0x40006820 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1, 0x40006822 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1, 0x40006824 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1, 0x40006826 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1, 0x40006828 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1, 0x4000682a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1, 0x4000682c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1, 0x4000682e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1, 0x40006830 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1, 0x40006832 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1, 0x40006834 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1, 0x40006836 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1, 0x40006838 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1, 0x4000683a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1, 0x4000683c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0, 0x40006840 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0, 0x40006842 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0, 0x40006844 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0, 0x40006846 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0, 0x40006848 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0, 0x4000684a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0, 0x4000684c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0, 0x4000684e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0, 0x40006850 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0, 0x40006852 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0, 0x40006854 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0, 0x40006856 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0, 0x40006858 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0, 0x4000685a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0, 0x4000685c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1, 0x40006860 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1, 0x40006862 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1, 0x40006864 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1, 0x40006866 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1, 0x40006868 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1, 0x4000686a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1, 0x4000686c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1, 0x4000686e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1, 0x40006870 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1, 0x40006872 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1, 0x40006874 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1, 0x40006876 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1, 0x40006878 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1, 0x4000687a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1, 0x4000687c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0, 0x40006880 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0, 0x40006882 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0, 0x40006884 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0, 0x40006886 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0, 0x40006888 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0, 0x4000688a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0, 0x4000688c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0, 0x4000688e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0, 0x40006890 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0, 0x40006892 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0, 0x40006894 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0, 0x40006896 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0, 0x40006898 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0, 0x4000689a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0, 0x4000689c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1, 0x400068a0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1, 0x400068a2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1, 0x400068a4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1, 0x400068a6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1, 0x400068a8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1, 0x400068aa +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1, 0x400068ac +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1, 0x400068ae +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1, 0x400068b0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1, 0x400068b2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1, 0x400068b4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1, 0x400068b6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1, 0x400068b8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1, 0x400068ba +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1, 0x400068bc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST, 0x400068c0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST, 0x400068c2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST, 0x400068c4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST, 0x400068c6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST, 0x400068c8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST, 0x400068ca +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST, 0x400068cc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST, 0x400068ce +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST, 0x400068d0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST, 0x400068d2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST, 0x400068d4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST, 0x400068d6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST, 0x400068d8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST, 0x400068da +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST, 0x400068dc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL, 0x400068e0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL, 0x400068e2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL, 0x400068e4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL, 0x400068e6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL, 0x400068e8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL, 0x400068ea +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL, 0x400068ec +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL, 0x400068ee +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL, 0x400068f0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL, 0x400068f2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL, 0x400068f4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL, 0x400068f6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL, 0x400068f8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL, 0x400068fa +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL, 0x400068fc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK, 0x40006900 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK, 0x40006902 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK, 0x40006904 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK, 0x40006906 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK, 0x40006908 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK, 0x4000690a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK, 0x4000690c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK, 0x4000690e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK, 0x40006910 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK, 0x40006912 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK, 0x40006914 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK, 0x40006916 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK, 0x40006918 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK, 0x4000691a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK, 0x4000691c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL, 0x40006920 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL, 0x40006922 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL, 0x40006924 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL, 0x40006926 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL, 0x40006928 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL, 0x4000692a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL, 0x4000692c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL, 0x4000692e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL, 0x40006930 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL, 0x40006932 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL, 0x40006934 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL, 0x40006936 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL, 0x40006938 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL, 0x4000693a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL, 0x4000693c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC, 0x40006940 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC, 0x40006942 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC, 0x40006944 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC, 0x40006946 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC, 0x40006948 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC, 0x4000694a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC, 0x4000694c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC, 0x4000694e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC, 0x40006950 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC, 0x40006952 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC, 0x40006954 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC, 0x40006956 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC, 0x40006958 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC, 0x4000695a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC, 0x4000695c +.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0, 0x40006a08 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0, 0x40006a0a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0, 0x40006a0c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0, 0x40006a0e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0, 0x40006a10 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0, 0x40006a12 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0, 0x40006a14 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0, 0x40006a16 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1, 0x40006a28 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1, 0x40006a2a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1, 0x40006a2c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1, 0x40006a2e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1, 0x40006a30 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1, 0x40006a32 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1, 0x40006a34 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1, 0x40006a36 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0, 0x40006a48 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0, 0x40006a4a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0, 0x40006a4c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0, 0x40006a4e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0, 0x40006a50 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0, 0x40006a52 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0, 0x40006a54 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0, 0x40006a56 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1, 0x40006a68 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1, 0x40006a6a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1, 0x40006a6c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1, 0x40006a6e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1, 0x40006a70 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1, 0x40006a72 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1, 0x40006a74 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1, 0x40006a76 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0, 0x40006a88 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0, 0x40006a8a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0, 0x40006a8c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0, 0x40006a8e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0, 0x40006a90 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0, 0x40006a92 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0, 0x40006a94 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0, 0x40006a96 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1, 0x40006aa8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1, 0x40006aaa +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1, 0x40006aac +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1, 0x40006aae +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1, 0x40006ab0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1, 0x40006ab2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1, 0x40006ab4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1, 0x40006ab6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST, 0x40006ac8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST, 0x40006aca +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST, 0x40006acc +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST, 0x40006ace +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST, 0x40006ad0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST, 0x40006ad2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST, 0x40006ad4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST, 0x40006ad6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL, 0x40006ae8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL, 0x40006aea +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL, 0x40006aec +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL, 0x40006aee +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL, 0x40006af0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL, 0x40006af2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL, 0x40006af4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL, 0x40006af6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK, 0x40006b08 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK, 0x40006b0a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK, 0x40006b0c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK, 0x40006b0e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK, 0x40006b10 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK, 0x40006b12 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK, 0x40006b14 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK, 0x40006b16 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL, 0x40006b28 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL, 0x40006b2a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL, 0x40006b2c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL, 0x40006b2e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL, 0x40006b30 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL, 0x40006b32 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL, 0x40006b34 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL, 0x40006b36 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC, 0x40006b48 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC, 0x40006b4a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC, 0x40006b4c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC, 0x40006b4e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC, 0x40006b50 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC, 0x40006b52 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC, 0x40006b54 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC, 0x40006b56 +.set CYDEV_PHUB_BASE, 0x40007000 +.set CYDEV_PHUB_SIZE, 0x00000c00 +.set CYDEV_PHUB_CFG, 0x40007000 +.set CYDEV_PHUB_ERR, 0x40007004 +.set CYDEV_PHUB_ERR_ADR, 0x40007008 +.set CYDEV_PHUB_CH0_BASE, 0x40007010 +.set CYDEV_PHUB_CH0_SIZE, 0x0000000c +.set CYDEV_PHUB_CH0_BASIC_CFG, 0x40007010 +.set CYDEV_PHUB_CH0_ACTION, 0x40007014 +.set CYDEV_PHUB_CH0_BASIC_STATUS, 0x40007018 +.set CYDEV_PHUB_CH1_BASE, 0x40007020 +.set CYDEV_PHUB_CH1_SIZE, 0x0000000c +.set CYDEV_PHUB_CH1_BASIC_CFG, 0x40007020 +.set CYDEV_PHUB_CH1_ACTION, 0x40007024 +.set CYDEV_PHUB_CH1_BASIC_STATUS, 0x40007028 +.set CYDEV_PHUB_CH2_BASE, 0x40007030 +.set CYDEV_PHUB_CH2_SIZE, 0x0000000c +.set CYDEV_PHUB_CH2_BASIC_CFG, 0x40007030 +.set CYDEV_PHUB_CH2_ACTION, 0x40007034 +.set CYDEV_PHUB_CH2_BASIC_STATUS, 0x40007038 +.set CYDEV_PHUB_CH3_BASE, 0x40007040 +.set CYDEV_PHUB_CH3_SIZE, 0x0000000c +.set CYDEV_PHUB_CH3_BASIC_CFG, 0x40007040 +.set CYDEV_PHUB_CH3_ACTION, 0x40007044 +.set CYDEV_PHUB_CH3_BASIC_STATUS, 0x40007048 +.set CYDEV_PHUB_CH4_BASE, 0x40007050 +.set CYDEV_PHUB_CH4_SIZE, 0x0000000c +.set CYDEV_PHUB_CH4_BASIC_CFG, 0x40007050 +.set CYDEV_PHUB_CH4_ACTION, 0x40007054 +.set CYDEV_PHUB_CH4_BASIC_STATUS, 0x40007058 +.set CYDEV_PHUB_CH5_BASE, 0x40007060 +.set CYDEV_PHUB_CH5_SIZE, 0x0000000c +.set CYDEV_PHUB_CH5_BASIC_CFG, 0x40007060 +.set CYDEV_PHUB_CH5_ACTION, 0x40007064 +.set CYDEV_PHUB_CH5_BASIC_STATUS, 0x40007068 +.set CYDEV_PHUB_CH6_BASE, 0x40007070 +.set CYDEV_PHUB_CH6_SIZE, 0x0000000c +.set CYDEV_PHUB_CH6_BASIC_CFG, 0x40007070 +.set CYDEV_PHUB_CH6_ACTION, 0x40007074 +.set CYDEV_PHUB_CH6_BASIC_STATUS, 0x40007078 +.set CYDEV_PHUB_CH7_BASE, 0x40007080 +.set CYDEV_PHUB_CH7_SIZE, 0x0000000c +.set CYDEV_PHUB_CH7_BASIC_CFG, 0x40007080 +.set CYDEV_PHUB_CH7_ACTION, 0x40007084 +.set CYDEV_PHUB_CH7_BASIC_STATUS, 0x40007088 +.set CYDEV_PHUB_CH8_BASE, 0x40007090 +.set CYDEV_PHUB_CH8_SIZE, 0x0000000c +.set CYDEV_PHUB_CH8_BASIC_CFG, 0x40007090 +.set CYDEV_PHUB_CH8_ACTION, 0x40007094 +.set CYDEV_PHUB_CH8_BASIC_STATUS, 0x40007098 +.set CYDEV_PHUB_CH9_BASE, 0x400070a0 +.set CYDEV_PHUB_CH9_SIZE, 0x0000000c +.set CYDEV_PHUB_CH9_BASIC_CFG, 0x400070a0 +.set CYDEV_PHUB_CH9_ACTION, 0x400070a4 +.set CYDEV_PHUB_CH9_BASIC_STATUS, 0x400070a8 +.set CYDEV_PHUB_CH10_BASE, 0x400070b0 +.set CYDEV_PHUB_CH10_SIZE, 0x0000000c +.set CYDEV_PHUB_CH10_BASIC_CFG, 0x400070b0 +.set CYDEV_PHUB_CH10_ACTION, 0x400070b4 +.set CYDEV_PHUB_CH10_BASIC_STATUS, 0x400070b8 +.set CYDEV_PHUB_CH11_BASE, 0x400070c0 +.set CYDEV_PHUB_CH11_SIZE, 0x0000000c +.set CYDEV_PHUB_CH11_BASIC_CFG, 0x400070c0 +.set CYDEV_PHUB_CH11_ACTION, 0x400070c4 +.set CYDEV_PHUB_CH11_BASIC_STATUS, 0x400070c8 +.set CYDEV_PHUB_CH12_BASE, 0x400070d0 +.set CYDEV_PHUB_CH12_SIZE, 0x0000000c +.set CYDEV_PHUB_CH12_BASIC_CFG, 0x400070d0 +.set CYDEV_PHUB_CH12_ACTION, 0x400070d4 +.set CYDEV_PHUB_CH12_BASIC_STATUS, 0x400070d8 +.set CYDEV_PHUB_CH13_BASE, 0x400070e0 +.set CYDEV_PHUB_CH13_SIZE, 0x0000000c +.set CYDEV_PHUB_CH13_BASIC_CFG, 0x400070e0 +.set CYDEV_PHUB_CH13_ACTION, 0x400070e4 +.set CYDEV_PHUB_CH13_BASIC_STATUS, 0x400070e8 +.set CYDEV_PHUB_CH14_BASE, 0x400070f0 +.set CYDEV_PHUB_CH14_SIZE, 0x0000000c +.set CYDEV_PHUB_CH14_BASIC_CFG, 0x400070f0 +.set CYDEV_PHUB_CH14_ACTION, 0x400070f4 +.set CYDEV_PHUB_CH14_BASIC_STATUS, 0x400070f8 +.set CYDEV_PHUB_CH15_BASE, 0x40007100 +.set CYDEV_PHUB_CH15_SIZE, 0x0000000c +.set CYDEV_PHUB_CH15_BASIC_CFG, 0x40007100 +.set CYDEV_PHUB_CH15_ACTION, 0x40007104 +.set CYDEV_PHUB_CH15_BASIC_STATUS, 0x40007108 +.set CYDEV_PHUB_CH16_BASE, 0x40007110 +.set CYDEV_PHUB_CH16_SIZE, 0x0000000c +.set CYDEV_PHUB_CH16_BASIC_CFG, 0x40007110 +.set CYDEV_PHUB_CH16_ACTION, 0x40007114 +.set CYDEV_PHUB_CH16_BASIC_STATUS, 0x40007118 +.set CYDEV_PHUB_CH17_BASE, 0x40007120 +.set CYDEV_PHUB_CH17_SIZE, 0x0000000c +.set CYDEV_PHUB_CH17_BASIC_CFG, 0x40007120 +.set CYDEV_PHUB_CH17_ACTION, 0x40007124 +.set CYDEV_PHUB_CH17_BASIC_STATUS, 0x40007128 +.set CYDEV_PHUB_CH18_BASE, 0x40007130 +.set CYDEV_PHUB_CH18_SIZE, 0x0000000c +.set CYDEV_PHUB_CH18_BASIC_CFG, 0x40007130 +.set CYDEV_PHUB_CH18_ACTION, 0x40007134 +.set CYDEV_PHUB_CH18_BASIC_STATUS, 0x40007138 +.set CYDEV_PHUB_CH19_BASE, 0x40007140 +.set CYDEV_PHUB_CH19_SIZE, 0x0000000c +.set CYDEV_PHUB_CH19_BASIC_CFG, 0x40007140 +.set CYDEV_PHUB_CH19_ACTION, 0x40007144 +.set CYDEV_PHUB_CH19_BASIC_STATUS, 0x40007148 +.set CYDEV_PHUB_CH20_BASE, 0x40007150 +.set CYDEV_PHUB_CH20_SIZE, 0x0000000c +.set CYDEV_PHUB_CH20_BASIC_CFG, 0x40007150 +.set CYDEV_PHUB_CH20_ACTION, 0x40007154 +.set CYDEV_PHUB_CH20_BASIC_STATUS, 0x40007158 +.set CYDEV_PHUB_CH21_BASE, 0x40007160 +.set CYDEV_PHUB_CH21_SIZE, 0x0000000c +.set CYDEV_PHUB_CH21_BASIC_CFG, 0x40007160 +.set CYDEV_PHUB_CH21_ACTION, 0x40007164 +.set CYDEV_PHUB_CH21_BASIC_STATUS, 0x40007168 +.set CYDEV_PHUB_CH22_BASE, 0x40007170 +.set CYDEV_PHUB_CH22_SIZE, 0x0000000c +.set CYDEV_PHUB_CH22_BASIC_CFG, 0x40007170 +.set CYDEV_PHUB_CH22_ACTION, 0x40007174 +.set CYDEV_PHUB_CH22_BASIC_STATUS, 0x40007178 +.set CYDEV_PHUB_CH23_BASE, 0x40007180 +.set CYDEV_PHUB_CH23_SIZE, 0x0000000c +.set CYDEV_PHUB_CH23_BASIC_CFG, 0x40007180 +.set CYDEV_PHUB_CH23_ACTION, 0x40007184 +.set CYDEV_PHUB_CH23_BASIC_STATUS, 0x40007188 +.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM0_CFG0, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_CFG1, 0x40007604 +.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM1_CFG0, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_CFG1, 0x4000760c +.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM2_CFG0, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_CFG1, 0x40007614 +.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM3_CFG0, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_CFG1, 0x4000761c +.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM4_CFG0, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_CFG1, 0x40007624 +.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM5_CFG0, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_CFG1, 0x4000762c +.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM6_CFG0, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_CFG1, 0x40007634 +.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM7_CFG0, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_CFG1, 0x4000763c +.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM8_CFG0, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_CFG1, 0x40007644 +.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM9_CFG0, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_CFG1, 0x4000764c +.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM10_CFG0, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_CFG1, 0x40007654 +.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM11_CFG0, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_CFG1, 0x4000765c +.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM12_CFG0, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_CFG1, 0x40007664 +.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM13_CFG0, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_CFG1, 0x4000766c +.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM14_CFG0, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_CFG1, 0x40007674 +.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM15_CFG0, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_CFG1, 0x4000767c +.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM16_CFG0, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_CFG1, 0x40007684 +.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM17_CFG0, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_CFG1, 0x4000768c +.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM18_CFG0, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_CFG1, 0x40007694 +.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM19_CFG0, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_CFG1, 0x4000769c +.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM20_CFG0, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_CFG1, 0x400076a4 +.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM21_CFG0, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_CFG1, 0x400076ac +.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM22_CFG0, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_CFG1, 0x400076b4 +.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM23_CFG0, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_CFG1, 0x400076bc +.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 +.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM0_ORIG_TD0, 0x40007800 +.set CYDEV_PHUB_TDMEM0_ORIG_TD1, 0x40007804 +.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 +.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM1_ORIG_TD0, 0x40007808 +.set CYDEV_PHUB_TDMEM1_ORIG_TD1, 0x4000780c +.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 +.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM2_ORIG_TD0, 0x40007810 +.set CYDEV_PHUB_TDMEM2_ORIG_TD1, 0x40007814 +.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 +.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM3_ORIG_TD0, 0x40007818 +.set CYDEV_PHUB_TDMEM3_ORIG_TD1, 0x4000781c +.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 +.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM4_ORIG_TD0, 0x40007820 +.set CYDEV_PHUB_TDMEM4_ORIG_TD1, 0x40007824 +.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 +.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM5_ORIG_TD0, 0x40007828 +.set CYDEV_PHUB_TDMEM5_ORIG_TD1, 0x4000782c +.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 +.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM6_ORIG_TD0, 0x40007830 +.set CYDEV_PHUB_TDMEM6_ORIG_TD1, 0x40007834 +.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 +.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM7_ORIG_TD0, 0x40007838 +.set CYDEV_PHUB_TDMEM7_ORIG_TD1, 0x4000783c +.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 +.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM8_ORIG_TD0, 0x40007840 +.set CYDEV_PHUB_TDMEM8_ORIG_TD1, 0x40007844 +.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 +.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM9_ORIG_TD0, 0x40007848 +.set CYDEV_PHUB_TDMEM9_ORIG_TD1, 0x4000784c +.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 +.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM10_ORIG_TD0, 0x40007850 +.set CYDEV_PHUB_TDMEM10_ORIG_TD1, 0x40007854 +.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 +.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM11_ORIG_TD0, 0x40007858 +.set CYDEV_PHUB_TDMEM11_ORIG_TD1, 0x4000785c +.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 +.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM12_ORIG_TD0, 0x40007860 +.set CYDEV_PHUB_TDMEM12_ORIG_TD1, 0x40007864 +.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 +.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM13_ORIG_TD0, 0x40007868 +.set CYDEV_PHUB_TDMEM13_ORIG_TD1, 0x4000786c +.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 +.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM14_ORIG_TD0, 0x40007870 +.set CYDEV_PHUB_TDMEM14_ORIG_TD1, 0x40007874 +.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 +.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM15_ORIG_TD0, 0x40007878 +.set CYDEV_PHUB_TDMEM15_ORIG_TD1, 0x4000787c +.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 +.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM16_ORIG_TD0, 0x40007880 +.set CYDEV_PHUB_TDMEM16_ORIG_TD1, 0x40007884 +.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 +.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM17_ORIG_TD0, 0x40007888 +.set CYDEV_PHUB_TDMEM17_ORIG_TD1, 0x4000788c +.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 +.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM18_ORIG_TD0, 0x40007890 +.set CYDEV_PHUB_TDMEM18_ORIG_TD1, 0x40007894 +.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 +.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM19_ORIG_TD0, 0x40007898 +.set CYDEV_PHUB_TDMEM19_ORIG_TD1, 0x4000789c +.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 +.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_ORIG_TD1, 0x400078ac +.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 +.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_ORIG_TD1, 0x400078bc +.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 +.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_ORIG_TD1, 0x400078cc +.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 +.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_ORIG_TD1, 0x400078dc +.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 +.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_ORIG_TD1, 0x400078ec +.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 +.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_ORIG_TD1, 0x400078fc +.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 +.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM32_ORIG_TD0, 0x40007900 +.set CYDEV_PHUB_TDMEM32_ORIG_TD1, 0x40007904 +.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 +.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM33_ORIG_TD0, 0x40007908 +.set CYDEV_PHUB_TDMEM33_ORIG_TD1, 0x4000790c +.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 +.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM34_ORIG_TD0, 0x40007910 +.set CYDEV_PHUB_TDMEM34_ORIG_TD1, 0x40007914 +.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 +.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM35_ORIG_TD0, 0x40007918 +.set CYDEV_PHUB_TDMEM35_ORIG_TD1, 0x4000791c +.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 +.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM36_ORIG_TD0, 0x40007920 +.set CYDEV_PHUB_TDMEM36_ORIG_TD1, 0x40007924 +.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 +.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM37_ORIG_TD0, 0x40007928 +.set CYDEV_PHUB_TDMEM37_ORIG_TD1, 0x4000792c +.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 +.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM38_ORIG_TD0, 0x40007930 +.set CYDEV_PHUB_TDMEM38_ORIG_TD1, 0x40007934 +.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 +.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM39_ORIG_TD0, 0x40007938 +.set CYDEV_PHUB_TDMEM39_ORIG_TD1, 0x4000793c +.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 +.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM40_ORIG_TD0, 0x40007940 +.set CYDEV_PHUB_TDMEM40_ORIG_TD1, 0x40007944 +.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 +.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM41_ORIG_TD0, 0x40007948 +.set CYDEV_PHUB_TDMEM41_ORIG_TD1, 0x4000794c +.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 +.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM42_ORIG_TD0, 0x40007950 +.set CYDEV_PHUB_TDMEM42_ORIG_TD1, 0x40007954 +.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 +.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM43_ORIG_TD0, 0x40007958 +.set CYDEV_PHUB_TDMEM43_ORIG_TD1, 0x4000795c +.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 +.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM44_ORIG_TD0, 0x40007960 +.set CYDEV_PHUB_TDMEM44_ORIG_TD1, 0x40007964 +.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 +.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM45_ORIG_TD0, 0x40007968 +.set CYDEV_PHUB_TDMEM45_ORIG_TD1, 0x4000796c +.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 +.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM46_ORIG_TD0, 0x40007970 +.set CYDEV_PHUB_TDMEM46_ORIG_TD1, 0x40007974 +.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 +.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM47_ORIG_TD0, 0x40007978 +.set CYDEV_PHUB_TDMEM47_ORIG_TD1, 0x4000797c +.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 +.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM48_ORIG_TD0, 0x40007980 +.set CYDEV_PHUB_TDMEM48_ORIG_TD1, 0x40007984 +.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 +.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM49_ORIG_TD0, 0x40007988 +.set CYDEV_PHUB_TDMEM49_ORIG_TD1, 0x4000798c +.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 +.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM50_ORIG_TD0, 0x40007990 +.set CYDEV_PHUB_TDMEM50_ORIG_TD1, 0x40007994 +.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 +.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM51_ORIG_TD0, 0x40007998 +.set CYDEV_PHUB_TDMEM51_ORIG_TD1, 0x4000799c +.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 +.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_ORIG_TD1, 0x400079ac +.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 +.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_ORIG_TD1, 0x400079bc +.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 +.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_ORIG_TD1, 0x400079cc +.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 +.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_ORIG_TD1, 0x400079dc +.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 +.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_ORIG_TD1, 0x400079ec +.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 +.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_ORIG_TD1, 0x400079fc +.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 +.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c +.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 +.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c +.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 +.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c +.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 +.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c +.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 +.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c +.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 +.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c +.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 +.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c +.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 +.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c +.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 +.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c +.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 +.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c +.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 +.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_ORIG_TD1, 0x40007aac +.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 +.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_ORIG_TD1, 0x40007abc +.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 +.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_ORIG_TD1, 0x40007acc +.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 +.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_ORIG_TD1, 0x40007adc +.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 +.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_ORIG_TD1, 0x40007aec +.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 +.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_ORIG_TD1, 0x40007afc +.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 +.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c +.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 +.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c +.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 +.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c +.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 +.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c +.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 +.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c +.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 +.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c +.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 +.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c +.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 +.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c +.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 +.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c +.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 +.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c +.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 +.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_ORIG_TD1, 0x40007bac +.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 +.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc +.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 +.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc +.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 +.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc +.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 +.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_ORIG_TD1, 0x40007bec +.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 +.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc +.set CYDEV_EE_BASE, 0x40008000 +.set CYDEV_EE_SIZE, 0x00000800 +.set CYDEV_EE_DATA_MBASE, 0x40008000 +.set CYDEV_EE_DATA_MSIZE, 0x00000800 +.set CYDEV_CAN0_BASE, 0x4000a000 +.set CYDEV_CAN0_SIZE, 0x000002a0 +.set CYDEV_CAN0_CSR_BASE, 0x4000a000 +.set CYDEV_CAN0_CSR_SIZE, 0x00000018 +.set CYDEV_CAN0_CSR_INT_SR, 0x4000a000 +.set CYDEV_CAN0_CSR_INT_EN, 0x4000a004 +.set CYDEV_CAN0_CSR_BUF_SR, 0x4000a008 +.set CYDEV_CAN0_CSR_ERR_SR, 0x4000a00c +.set CYDEV_CAN0_CSR_CMD, 0x4000a010 +.set CYDEV_CAN0_CSR_CFG, 0x4000a014 +.set CYDEV_CAN0_TX0_BASE, 0x4000a020 +.set CYDEV_CAN0_TX0_SIZE, 0x00000010 +.set CYDEV_CAN0_TX0_CMD, 0x4000a020 +.set CYDEV_CAN0_TX0_ID, 0x4000a024 +.set CYDEV_CAN0_TX0_DH, 0x4000a028 +.set CYDEV_CAN0_TX0_DL, 0x4000a02c +.set CYDEV_CAN0_TX1_BASE, 0x4000a030 +.set CYDEV_CAN0_TX1_SIZE, 0x00000010 +.set CYDEV_CAN0_TX1_CMD, 0x4000a030 +.set CYDEV_CAN0_TX1_ID, 0x4000a034 +.set CYDEV_CAN0_TX1_DH, 0x4000a038 +.set CYDEV_CAN0_TX1_DL, 0x4000a03c +.set CYDEV_CAN0_TX2_BASE, 0x4000a040 +.set CYDEV_CAN0_TX2_SIZE, 0x00000010 +.set CYDEV_CAN0_TX2_CMD, 0x4000a040 +.set CYDEV_CAN0_TX2_ID, 0x4000a044 +.set CYDEV_CAN0_TX2_DH, 0x4000a048 +.set CYDEV_CAN0_TX2_DL, 0x4000a04c +.set CYDEV_CAN0_TX3_BASE, 0x4000a050 +.set CYDEV_CAN0_TX3_SIZE, 0x00000010 +.set CYDEV_CAN0_TX3_CMD, 0x4000a050 +.set CYDEV_CAN0_TX3_ID, 0x4000a054 +.set CYDEV_CAN0_TX3_DH, 0x4000a058 +.set CYDEV_CAN0_TX3_DL, 0x4000a05c +.set CYDEV_CAN0_TX4_BASE, 0x4000a060 +.set CYDEV_CAN0_TX4_SIZE, 0x00000010 +.set CYDEV_CAN0_TX4_CMD, 0x4000a060 +.set CYDEV_CAN0_TX4_ID, 0x4000a064 +.set CYDEV_CAN0_TX4_DH, 0x4000a068 +.set CYDEV_CAN0_TX4_DL, 0x4000a06c +.set CYDEV_CAN0_TX5_BASE, 0x4000a070 +.set CYDEV_CAN0_TX5_SIZE, 0x00000010 +.set CYDEV_CAN0_TX5_CMD, 0x4000a070 +.set CYDEV_CAN0_TX5_ID, 0x4000a074 +.set CYDEV_CAN0_TX5_DH, 0x4000a078 +.set CYDEV_CAN0_TX5_DL, 0x4000a07c +.set CYDEV_CAN0_TX6_BASE, 0x4000a080 +.set CYDEV_CAN0_TX6_SIZE, 0x00000010 +.set CYDEV_CAN0_TX6_CMD, 0x4000a080 +.set CYDEV_CAN0_TX6_ID, 0x4000a084 +.set CYDEV_CAN0_TX6_DH, 0x4000a088 +.set CYDEV_CAN0_TX6_DL, 0x4000a08c +.set CYDEV_CAN0_TX7_BASE, 0x4000a090 +.set CYDEV_CAN0_TX7_SIZE, 0x00000010 +.set CYDEV_CAN0_TX7_CMD, 0x4000a090 +.set CYDEV_CAN0_TX7_ID, 0x4000a094 +.set CYDEV_CAN0_TX7_DH, 0x4000a098 +.set CYDEV_CAN0_TX7_DL, 0x4000a09c +.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 +.set CYDEV_CAN0_RX0_SIZE, 0x00000020 +.set CYDEV_CAN0_RX0_CMD, 0x4000a0a0 +.set CYDEV_CAN0_RX0_ID, 0x4000a0a4 +.set CYDEV_CAN0_RX0_DH, 0x4000a0a8 +.set CYDEV_CAN0_RX0_DL, 0x4000a0ac +.set CYDEV_CAN0_RX0_AMR, 0x4000a0b0 +.set CYDEV_CAN0_RX0_ACR, 0x4000a0b4 +.set CYDEV_CAN0_RX0_AMRD, 0x4000a0b8 +.set CYDEV_CAN0_RX0_ACRD, 0x4000a0bc +.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 +.set CYDEV_CAN0_RX1_SIZE, 0x00000020 +.set CYDEV_CAN0_RX1_CMD, 0x4000a0c0 +.set CYDEV_CAN0_RX1_ID, 0x4000a0c4 +.set CYDEV_CAN0_RX1_DH, 0x4000a0c8 +.set CYDEV_CAN0_RX1_DL, 0x4000a0cc +.set CYDEV_CAN0_RX1_AMR, 0x4000a0d0 +.set CYDEV_CAN0_RX1_ACR, 0x4000a0d4 +.set CYDEV_CAN0_RX1_AMRD, 0x4000a0d8 +.set CYDEV_CAN0_RX1_ACRD, 0x4000a0dc +.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 +.set CYDEV_CAN0_RX2_SIZE, 0x00000020 +.set CYDEV_CAN0_RX2_CMD, 0x4000a0e0 +.set CYDEV_CAN0_RX2_ID, 0x4000a0e4 +.set CYDEV_CAN0_RX2_DH, 0x4000a0e8 +.set CYDEV_CAN0_RX2_DL, 0x4000a0ec +.set CYDEV_CAN0_RX2_AMR, 0x4000a0f0 +.set CYDEV_CAN0_RX2_ACR, 0x4000a0f4 +.set CYDEV_CAN0_RX2_AMRD, 0x4000a0f8 +.set CYDEV_CAN0_RX2_ACRD, 0x4000a0fc +.set CYDEV_CAN0_RX3_BASE, 0x4000a100 +.set CYDEV_CAN0_RX3_SIZE, 0x00000020 +.set CYDEV_CAN0_RX3_CMD, 0x4000a100 +.set CYDEV_CAN0_RX3_ID, 0x4000a104 +.set CYDEV_CAN0_RX3_DH, 0x4000a108 +.set CYDEV_CAN0_RX3_DL, 0x4000a10c +.set CYDEV_CAN0_RX3_AMR, 0x4000a110 +.set CYDEV_CAN0_RX3_ACR, 0x4000a114 +.set CYDEV_CAN0_RX3_AMRD, 0x4000a118 +.set CYDEV_CAN0_RX3_ACRD, 0x4000a11c +.set CYDEV_CAN0_RX4_BASE, 0x4000a120 +.set CYDEV_CAN0_RX4_SIZE, 0x00000020 +.set CYDEV_CAN0_RX4_CMD, 0x4000a120 +.set CYDEV_CAN0_RX4_ID, 0x4000a124 +.set CYDEV_CAN0_RX4_DH, 0x4000a128 +.set CYDEV_CAN0_RX4_DL, 0x4000a12c +.set CYDEV_CAN0_RX4_AMR, 0x4000a130 +.set CYDEV_CAN0_RX4_ACR, 0x4000a134 +.set CYDEV_CAN0_RX4_AMRD, 0x4000a138 +.set CYDEV_CAN0_RX4_ACRD, 0x4000a13c +.set CYDEV_CAN0_RX5_BASE, 0x4000a140 +.set CYDEV_CAN0_RX5_SIZE, 0x00000020 +.set CYDEV_CAN0_RX5_CMD, 0x4000a140 +.set CYDEV_CAN0_RX5_ID, 0x4000a144 +.set CYDEV_CAN0_RX5_DH, 0x4000a148 +.set CYDEV_CAN0_RX5_DL, 0x4000a14c +.set CYDEV_CAN0_RX5_AMR, 0x4000a150 +.set CYDEV_CAN0_RX5_ACR, 0x4000a154 +.set CYDEV_CAN0_RX5_AMRD, 0x4000a158 +.set CYDEV_CAN0_RX5_ACRD, 0x4000a15c +.set CYDEV_CAN0_RX6_BASE, 0x4000a160 +.set CYDEV_CAN0_RX6_SIZE, 0x00000020 +.set CYDEV_CAN0_RX6_CMD, 0x4000a160 +.set CYDEV_CAN0_RX6_ID, 0x4000a164 +.set CYDEV_CAN0_RX6_DH, 0x4000a168 +.set CYDEV_CAN0_RX6_DL, 0x4000a16c +.set CYDEV_CAN0_RX6_AMR, 0x4000a170 +.set CYDEV_CAN0_RX6_ACR, 0x4000a174 +.set CYDEV_CAN0_RX6_AMRD, 0x4000a178 +.set CYDEV_CAN0_RX6_ACRD, 0x4000a17c +.set CYDEV_CAN0_RX7_BASE, 0x4000a180 +.set CYDEV_CAN0_RX7_SIZE, 0x00000020 +.set CYDEV_CAN0_RX7_CMD, 0x4000a180 +.set CYDEV_CAN0_RX7_ID, 0x4000a184 +.set CYDEV_CAN0_RX7_DH, 0x4000a188 +.set CYDEV_CAN0_RX7_DL, 0x4000a18c +.set CYDEV_CAN0_RX7_AMR, 0x4000a190 +.set CYDEV_CAN0_RX7_ACR, 0x4000a194 +.set CYDEV_CAN0_RX7_AMRD, 0x4000a198 +.set CYDEV_CAN0_RX7_ACRD, 0x4000a19c +.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 +.set CYDEV_CAN0_RX8_SIZE, 0x00000020 +.set CYDEV_CAN0_RX8_CMD, 0x4000a1a0 +.set CYDEV_CAN0_RX8_ID, 0x4000a1a4 +.set CYDEV_CAN0_RX8_DH, 0x4000a1a8 +.set CYDEV_CAN0_RX8_DL, 0x4000a1ac +.set CYDEV_CAN0_RX8_AMR, 0x4000a1b0 +.set CYDEV_CAN0_RX8_ACR, 0x4000a1b4 +.set CYDEV_CAN0_RX8_AMRD, 0x4000a1b8 +.set CYDEV_CAN0_RX8_ACRD, 0x4000a1bc +.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 +.set CYDEV_CAN0_RX9_SIZE, 0x00000020 +.set CYDEV_CAN0_RX9_CMD, 0x4000a1c0 +.set CYDEV_CAN0_RX9_ID, 0x4000a1c4 +.set CYDEV_CAN0_RX9_DH, 0x4000a1c8 +.set CYDEV_CAN0_RX9_DL, 0x4000a1cc +.set CYDEV_CAN0_RX9_AMR, 0x4000a1d0 +.set CYDEV_CAN0_RX9_ACR, 0x4000a1d4 +.set CYDEV_CAN0_RX9_AMRD, 0x4000a1d8 +.set CYDEV_CAN0_RX9_ACRD, 0x4000a1dc +.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 +.set CYDEV_CAN0_RX10_SIZE, 0x00000020 +.set CYDEV_CAN0_RX10_CMD, 0x4000a1e0 +.set CYDEV_CAN0_RX10_ID, 0x4000a1e4 +.set CYDEV_CAN0_RX10_DH, 0x4000a1e8 +.set CYDEV_CAN0_RX10_DL, 0x4000a1ec +.set CYDEV_CAN0_RX10_AMR, 0x4000a1f0 +.set CYDEV_CAN0_RX10_ACR, 0x4000a1f4 +.set CYDEV_CAN0_RX10_AMRD, 0x4000a1f8 +.set CYDEV_CAN0_RX10_ACRD, 0x4000a1fc +.set CYDEV_CAN0_RX11_BASE, 0x4000a200 +.set CYDEV_CAN0_RX11_SIZE, 0x00000020 +.set CYDEV_CAN0_RX11_CMD, 0x4000a200 +.set CYDEV_CAN0_RX11_ID, 0x4000a204 +.set CYDEV_CAN0_RX11_DH, 0x4000a208 +.set CYDEV_CAN0_RX11_DL, 0x4000a20c +.set CYDEV_CAN0_RX11_AMR, 0x4000a210 +.set CYDEV_CAN0_RX11_ACR, 0x4000a214 +.set CYDEV_CAN0_RX11_AMRD, 0x4000a218 +.set CYDEV_CAN0_RX11_ACRD, 0x4000a21c +.set CYDEV_CAN0_RX12_BASE, 0x4000a220 +.set CYDEV_CAN0_RX12_SIZE, 0x00000020 +.set CYDEV_CAN0_RX12_CMD, 0x4000a220 +.set CYDEV_CAN0_RX12_ID, 0x4000a224 +.set CYDEV_CAN0_RX12_DH, 0x4000a228 +.set CYDEV_CAN0_RX12_DL, 0x4000a22c +.set CYDEV_CAN0_RX12_AMR, 0x4000a230 +.set CYDEV_CAN0_RX12_ACR, 0x4000a234 +.set CYDEV_CAN0_RX12_AMRD, 0x4000a238 +.set CYDEV_CAN0_RX12_ACRD, 0x4000a23c +.set CYDEV_CAN0_RX13_BASE, 0x4000a240 +.set CYDEV_CAN0_RX13_SIZE, 0x00000020 +.set CYDEV_CAN0_RX13_CMD, 0x4000a240 +.set CYDEV_CAN0_RX13_ID, 0x4000a244 +.set CYDEV_CAN0_RX13_DH, 0x4000a248 +.set CYDEV_CAN0_RX13_DL, 0x4000a24c +.set CYDEV_CAN0_RX13_AMR, 0x4000a250 +.set CYDEV_CAN0_RX13_ACR, 0x4000a254 +.set CYDEV_CAN0_RX13_AMRD, 0x4000a258 +.set CYDEV_CAN0_RX13_ACRD, 0x4000a25c +.set CYDEV_CAN0_RX14_BASE, 0x4000a260 +.set CYDEV_CAN0_RX14_SIZE, 0x00000020 +.set CYDEV_CAN0_RX14_CMD, 0x4000a260 +.set CYDEV_CAN0_RX14_ID, 0x4000a264 +.set CYDEV_CAN0_RX14_DH, 0x4000a268 +.set CYDEV_CAN0_RX14_DL, 0x4000a26c +.set CYDEV_CAN0_RX14_AMR, 0x4000a270 +.set CYDEV_CAN0_RX14_ACR, 0x4000a274 +.set CYDEV_CAN0_RX14_AMRD, 0x4000a278 +.set CYDEV_CAN0_RX14_ACRD, 0x4000a27c +.set CYDEV_CAN0_RX15_BASE, 0x4000a280 +.set CYDEV_CAN0_RX15_SIZE, 0x00000020 +.set CYDEV_CAN0_RX15_CMD, 0x4000a280 +.set CYDEV_CAN0_RX15_ID, 0x4000a284 +.set CYDEV_CAN0_RX15_DH, 0x4000a288 +.set CYDEV_CAN0_RX15_DL, 0x4000a28c +.set CYDEV_CAN0_RX15_AMR, 0x4000a290 +.set CYDEV_CAN0_RX15_ACR, 0x4000a294 +.set CYDEV_CAN0_RX15_AMRD, 0x4000a298 +.set CYDEV_CAN0_RX15_ACRD, 0x4000a29c +.set CYDEV_DFB0_BASE, 0x4000c000 +.set CYDEV_DFB0_SIZE, 0x000007b5 +.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 +.set CYDEV_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 +.set CYDEV_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 +.set CYDEV_DFB0_CR, 0x4000c780 +.set CYDEV_DFB0_SR, 0x4000c784 +.set CYDEV_DFB0_RAM_EN, 0x4000c788 +.set CYDEV_DFB0_RAM_DIR, 0x4000c78c +.set CYDEV_DFB0_SEMA, 0x4000c790 +.set CYDEV_DFB0_DSI_CTRL, 0x4000c794 +.set CYDEV_DFB0_INT_CTRL, 0x4000c798 +.set CYDEV_DFB0_DMA_CTRL, 0x4000c79c +.set CYDEV_DFB0_STAGEA, 0x4000c7a0 +.set CYDEV_DFB0_STAGEAM, 0x4000c7a1 +.set CYDEV_DFB0_STAGEAH, 0x4000c7a2 +.set CYDEV_DFB0_STAGEB, 0x4000c7a4 +.set CYDEV_DFB0_STAGEBM, 0x4000c7a5 +.set CYDEV_DFB0_STAGEBH, 0x4000c7a6 +.set CYDEV_DFB0_HOLDA, 0x4000c7a8 +.set CYDEV_DFB0_HOLDAM, 0x4000c7a9 +.set CYDEV_DFB0_HOLDAH, 0x4000c7aa +.set CYDEV_DFB0_HOLDAS, 0x4000c7ab +.set CYDEV_DFB0_HOLDB, 0x4000c7ac +.set CYDEV_DFB0_HOLDBM, 0x4000c7ad +.set CYDEV_DFB0_HOLDBH, 0x4000c7ae +.set CYDEV_DFB0_HOLDBS, 0x4000c7af +.set CYDEV_DFB0_COHER, 0x4000c7b0 +.set CYDEV_DFB0_DALIGN, 0x4000c7b4 +.set CYDEV_UCFG_BASE, 0x40010000 +.set CYDEV_UCFG_SIZE, 0x00005040 +.set CYDEV_UCFG_B0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_SIZE, 0x00000fef +.set CYDEV_UCFG_B0_P0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT0, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT1, 0x40010004 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT2, 0x40010008 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT3, 0x4001000c +.set CYDEV_UCFG_B0_P0_U0_PLD_IT4, 0x40010010 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT5, 0x40010014 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT6, 0x40010018 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT7, 0x4001001c +.set CYDEV_UCFG_B0_P0_U0_PLD_IT8, 0x40010020 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT9, 0x40010024 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT10, 0x40010028 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT11, 0x4001002c +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT0, 0x40010030 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT1, 0x40010032 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT2, 0x40010034 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT3, 0x40010036 +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e +.set CYDEV_UCFG_B0_P0_U0_CFG0, 0x40010040 +.set CYDEV_UCFG_B0_P0_U0_CFG1, 0x40010041 +.set CYDEV_UCFG_B0_P0_U0_CFG2, 0x40010042 +.set CYDEV_UCFG_B0_P0_U0_CFG3, 0x40010043 +.set CYDEV_UCFG_B0_P0_U0_CFG4, 0x40010044 +.set CYDEV_UCFG_B0_P0_U0_CFG5, 0x40010045 +.set CYDEV_UCFG_B0_P0_U0_CFG6, 0x40010046 +.set CYDEV_UCFG_B0_P0_U0_CFG7, 0x40010047 +.set CYDEV_UCFG_B0_P0_U0_CFG8, 0x40010048 +.set CYDEV_UCFG_B0_P0_U0_CFG9, 0x40010049 +.set CYDEV_UCFG_B0_P0_U0_CFG10, 0x4001004a +.set CYDEV_UCFG_B0_P0_U0_CFG11, 0x4001004b +.set CYDEV_UCFG_B0_P0_U0_CFG12, 0x4001004c +.set CYDEV_UCFG_B0_P0_U0_CFG13, 0x4001004d +.set CYDEV_UCFG_B0_P0_U0_CFG14, 0x4001004e +.set CYDEV_UCFG_B0_P0_U0_CFG15, 0x4001004f +.set CYDEV_UCFG_B0_P0_U0_CFG16, 0x40010050 +.set CYDEV_UCFG_B0_P0_U0_CFG17, 0x40010051 +.set CYDEV_UCFG_B0_P0_U0_CFG18, 0x40010052 +.set CYDEV_UCFG_B0_P0_U0_CFG19, 0x40010053 +.set CYDEV_UCFG_B0_P0_U0_CFG20, 0x40010054 +.set CYDEV_UCFG_B0_P0_U0_CFG21, 0x40010055 +.set CYDEV_UCFG_B0_P0_U0_CFG22, 0x40010056 +.set CYDEV_UCFG_B0_P0_U0_CFG23, 0x40010057 +.set CYDEV_UCFG_B0_P0_U0_CFG24, 0x40010058 +.set CYDEV_UCFG_B0_P0_U0_CFG25, 0x40010059 +.set CYDEV_UCFG_B0_P0_U0_CFG26, 0x4001005a +.set CYDEV_UCFG_B0_P0_U0_CFG27, 0x4001005b +.set CYDEV_UCFG_B0_P0_U0_CFG28, 0x4001005c +.set CYDEV_UCFG_B0_P0_U0_CFG29, 0x4001005d +.set CYDEV_UCFG_B0_P0_U0_CFG30, 0x4001005e +.set CYDEV_UCFG_B0_P0_U0_CFG31, 0x4001005f +.set CYDEV_UCFG_B0_P0_U0_DCFG0, 0x40010060 +.set CYDEV_UCFG_B0_P0_U0_DCFG1, 0x40010062 +.set CYDEV_UCFG_B0_P0_U0_DCFG2, 0x40010064 +.set CYDEV_UCFG_B0_P0_U0_DCFG3, 0x40010066 +.set CYDEV_UCFG_B0_P0_U0_DCFG4, 0x40010068 +.set CYDEV_UCFG_B0_P0_U0_DCFG5, 0x4001006a +.set CYDEV_UCFG_B0_P0_U0_DCFG6, 0x4001006c +.set CYDEV_UCFG_B0_P0_U0_DCFG7, 0x4001006e +.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT0, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT1, 0x40010084 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT2, 0x40010088 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT3, 0x4001008c +.set CYDEV_UCFG_B0_P0_U1_PLD_IT4, 0x40010090 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT5, 0x40010094 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT6, 0x40010098 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT7, 0x4001009c +.set CYDEV_UCFG_B0_P0_U1_PLD_IT8, 0x400100a0 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT9, 0x400100a4 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT10, 0x400100a8 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT11, 0x400100ac +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT0, 0x400100b0 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT1, 0x400100b2 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT2, 0x400100b4 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT3, 0x400100b6 +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be +.set CYDEV_UCFG_B0_P0_U1_CFG0, 0x400100c0 +.set CYDEV_UCFG_B0_P0_U1_CFG1, 0x400100c1 +.set CYDEV_UCFG_B0_P0_U1_CFG2, 0x400100c2 +.set CYDEV_UCFG_B0_P0_U1_CFG3, 0x400100c3 +.set CYDEV_UCFG_B0_P0_U1_CFG4, 0x400100c4 +.set CYDEV_UCFG_B0_P0_U1_CFG5, 0x400100c5 +.set CYDEV_UCFG_B0_P0_U1_CFG6, 0x400100c6 +.set CYDEV_UCFG_B0_P0_U1_CFG7, 0x400100c7 +.set CYDEV_UCFG_B0_P0_U1_CFG8, 0x400100c8 +.set CYDEV_UCFG_B0_P0_U1_CFG9, 0x400100c9 +.set CYDEV_UCFG_B0_P0_U1_CFG10, 0x400100ca +.set CYDEV_UCFG_B0_P0_U1_CFG11, 0x400100cb +.set CYDEV_UCFG_B0_P0_U1_CFG12, 0x400100cc +.set CYDEV_UCFG_B0_P0_U1_CFG13, 0x400100cd +.set CYDEV_UCFG_B0_P0_U1_CFG14, 0x400100ce +.set CYDEV_UCFG_B0_P0_U1_CFG15, 0x400100cf +.set CYDEV_UCFG_B0_P0_U1_CFG16, 0x400100d0 +.set CYDEV_UCFG_B0_P0_U1_CFG17, 0x400100d1 +.set CYDEV_UCFG_B0_P0_U1_CFG18, 0x400100d2 +.set CYDEV_UCFG_B0_P0_U1_CFG19, 0x400100d3 +.set CYDEV_UCFG_B0_P0_U1_CFG20, 0x400100d4 +.set CYDEV_UCFG_B0_P0_U1_CFG21, 0x400100d5 +.set CYDEV_UCFG_B0_P0_U1_CFG22, 0x400100d6 +.set CYDEV_UCFG_B0_P0_U1_CFG23, 0x400100d7 +.set CYDEV_UCFG_B0_P0_U1_CFG24, 0x400100d8 +.set CYDEV_UCFG_B0_P0_U1_CFG25, 0x400100d9 +.set CYDEV_UCFG_B0_P0_U1_CFG26, 0x400100da +.set CYDEV_UCFG_B0_P0_U1_CFG27, 0x400100db +.set CYDEV_UCFG_B0_P0_U1_CFG28, 0x400100dc +.set CYDEV_UCFG_B0_P0_U1_CFG29, 0x400100dd +.set CYDEV_UCFG_B0_P0_U1_CFG30, 0x400100de +.set CYDEV_UCFG_B0_P0_U1_CFG31, 0x400100df +.set CYDEV_UCFG_B0_P0_U1_DCFG0, 0x400100e0 +.set CYDEV_UCFG_B0_P0_U1_DCFG1, 0x400100e2 +.set CYDEV_UCFG_B0_P0_U1_DCFG2, 0x400100e4 +.set CYDEV_UCFG_B0_P0_U1_DCFG3, 0x400100e6 +.set CYDEV_UCFG_B0_P0_U1_DCFG4, 0x400100e8 +.set CYDEV_UCFG_B0_P0_U1_DCFG5, 0x400100ea +.set CYDEV_UCFG_B0_P0_U1_DCFG6, 0x400100ec +.set CYDEV_UCFG_B0_P0_U1_DCFG7, 0x400100ee +.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 +.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P1_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT0, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT1, 0x40010204 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT2, 0x40010208 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT3, 0x4001020c +.set CYDEV_UCFG_B0_P1_U0_PLD_IT4, 0x40010210 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT5, 0x40010214 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT6, 0x40010218 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT7, 0x4001021c +.set CYDEV_UCFG_B0_P1_U0_PLD_IT8, 0x40010220 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT9, 0x40010224 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT10, 0x40010228 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT11, 0x4001022c +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT0, 0x40010230 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT1, 0x40010232 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT2, 0x40010234 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT3, 0x40010236 +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e +.set CYDEV_UCFG_B0_P1_U0_CFG0, 0x40010240 +.set CYDEV_UCFG_B0_P1_U0_CFG1, 0x40010241 +.set CYDEV_UCFG_B0_P1_U0_CFG2, 0x40010242 +.set CYDEV_UCFG_B0_P1_U0_CFG3, 0x40010243 +.set CYDEV_UCFG_B0_P1_U0_CFG4, 0x40010244 +.set CYDEV_UCFG_B0_P1_U0_CFG5, 0x40010245 +.set CYDEV_UCFG_B0_P1_U0_CFG6, 0x40010246 +.set CYDEV_UCFG_B0_P1_U0_CFG7, 0x40010247 +.set CYDEV_UCFG_B0_P1_U0_CFG8, 0x40010248 +.set CYDEV_UCFG_B0_P1_U0_CFG9, 0x40010249 +.set CYDEV_UCFG_B0_P1_U0_CFG10, 0x4001024a +.set CYDEV_UCFG_B0_P1_U0_CFG11, 0x4001024b +.set CYDEV_UCFG_B0_P1_U0_CFG12, 0x4001024c +.set CYDEV_UCFG_B0_P1_U0_CFG13, 0x4001024d +.set CYDEV_UCFG_B0_P1_U0_CFG14, 0x4001024e +.set CYDEV_UCFG_B0_P1_U0_CFG15, 0x4001024f +.set CYDEV_UCFG_B0_P1_U0_CFG16, 0x40010250 +.set CYDEV_UCFG_B0_P1_U0_CFG17, 0x40010251 +.set CYDEV_UCFG_B0_P1_U0_CFG18, 0x40010252 +.set CYDEV_UCFG_B0_P1_U0_CFG19, 0x40010253 +.set CYDEV_UCFG_B0_P1_U0_CFG20, 0x40010254 +.set CYDEV_UCFG_B0_P1_U0_CFG21, 0x40010255 +.set CYDEV_UCFG_B0_P1_U0_CFG22, 0x40010256 +.set CYDEV_UCFG_B0_P1_U0_CFG23, 0x40010257 +.set CYDEV_UCFG_B0_P1_U0_CFG24, 0x40010258 +.set CYDEV_UCFG_B0_P1_U0_CFG25, 0x40010259 +.set CYDEV_UCFG_B0_P1_U0_CFG26, 0x4001025a +.set CYDEV_UCFG_B0_P1_U0_CFG27, 0x4001025b +.set CYDEV_UCFG_B0_P1_U0_CFG28, 0x4001025c +.set CYDEV_UCFG_B0_P1_U0_CFG29, 0x4001025d +.set CYDEV_UCFG_B0_P1_U0_CFG30, 0x4001025e +.set CYDEV_UCFG_B0_P1_U0_CFG31, 0x4001025f +.set CYDEV_UCFG_B0_P1_U0_DCFG0, 0x40010260 +.set CYDEV_UCFG_B0_P1_U0_DCFG1, 0x40010262 +.set CYDEV_UCFG_B0_P1_U0_DCFG2, 0x40010264 +.set CYDEV_UCFG_B0_P1_U0_DCFG3, 0x40010266 +.set CYDEV_UCFG_B0_P1_U0_DCFG4, 0x40010268 +.set CYDEV_UCFG_B0_P1_U0_DCFG5, 0x4001026a +.set CYDEV_UCFG_B0_P1_U0_DCFG6, 0x4001026c +.set CYDEV_UCFG_B0_P1_U0_DCFG7, 0x4001026e +.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT0, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT1, 0x40010284 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT2, 0x40010288 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT3, 0x4001028c +.set CYDEV_UCFG_B0_P1_U1_PLD_IT4, 0x40010290 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT5, 0x40010294 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT6, 0x40010298 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT7, 0x4001029c +.set CYDEV_UCFG_B0_P1_U1_PLD_IT8, 0x400102a0 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT9, 0x400102a4 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT10, 0x400102a8 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT11, 0x400102ac +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT0, 0x400102b0 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT1, 0x400102b2 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT2, 0x400102b4 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT3, 0x400102b6 +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be +.set CYDEV_UCFG_B0_P1_U1_CFG0, 0x400102c0 +.set CYDEV_UCFG_B0_P1_U1_CFG1, 0x400102c1 +.set CYDEV_UCFG_B0_P1_U1_CFG2, 0x400102c2 +.set CYDEV_UCFG_B0_P1_U1_CFG3, 0x400102c3 +.set CYDEV_UCFG_B0_P1_U1_CFG4, 0x400102c4 +.set CYDEV_UCFG_B0_P1_U1_CFG5, 0x400102c5 +.set CYDEV_UCFG_B0_P1_U1_CFG6, 0x400102c6 +.set CYDEV_UCFG_B0_P1_U1_CFG7, 0x400102c7 +.set CYDEV_UCFG_B0_P1_U1_CFG8, 0x400102c8 +.set CYDEV_UCFG_B0_P1_U1_CFG9, 0x400102c9 +.set CYDEV_UCFG_B0_P1_U1_CFG10, 0x400102ca +.set CYDEV_UCFG_B0_P1_U1_CFG11, 0x400102cb +.set CYDEV_UCFG_B0_P1_U1_CFG12, 0x400102cc +.set CYDEV_UCFG_B0_P1_U1_CFG13, 0x400102cd +.set CYDEV_UCFG_B0_P1_U1_CFG14, 0x400102ce +.set CYDEV_UCFG_B0_P1_U1_CFG15, 0x400102cf +.set CYDEV_UCFG_B0_P1_U1_CFG16, 0x400102d0 +.set CYDEV_UCFG_B0_P1_U1_CFG17, 0x400102d1 +.set CYDEV_UCFG_B0_P1_U1_CFG18, 0x400102d2 +.set CYDEV_UCFG_B0_P1_U1_CFG19, 0x400102d3 +.set CYDEV_UCFG_B0_P1_U1_CFG20, 0x400102d4 +.set CYDEV_UCFG_B0_P1_U1_CFG21, 0x400102d5 +.set CYDEV_UCFG_B0_P1_U1_CFG22, 0x400102d6 +.set CYDEV_UCFG_B0_P1_U1_CFG23, 0x400102d7 +.set CYDEV_UCFG_B0_P1_U1_CFG24, 0x400102d8 +.set CYDEV_UCFG_B0_P1_U1_CFG25, 0x400102d9 +.set CYDEV_UCFG_B0_P1_U1_CFG26, 0x400102da +.set CYDEV_UCFG_B0_P1_U1_CFG27, 0x400102db +.set CYDEV_UCFG_B0_P1_U1_CFG28, 0x400102dc +.set CYDEV_UCFG_B0_P1_U1_CFG29, 0x400102dd +.set CYDEV_UCFG_B0_P1_U1_CFG30, 0x400102de +.set CYDEV_UCFG_B0_P1_U1_CFG31, 0x400102df +.set CYDEV_UCFG_B0_P1_U1_DCFG0, 0x400102e0 +.set CYDEV_UCFG_B0_P1_U1_DCFG1, 0x400102e2 +.set CYDEV_UCFG_B0_P1_U1_DCFG2, 0x400102e4 +.set CYDEV_UCFG_B0_P1_U1_DCFG3, 0x400102e6 +.set CYDEV_UCFG_B0_P1_U1_DCFG4, 0x400102e8 +.set CYDEV_UCFG_B0_P1_U1_DCFG5, 0x400102ea +.set CYDEV_UCFG_B0_P1_U1_DCFG6, 0x400102ec +.set CYDEV_UCFG_B0_P1_U1_DCFG7, 0x400102ee +.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 +.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P2_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT0, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT1, 0x40010404 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT2, 0x40010408 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT3, 0x4001040c +.set CYDEV_UCFG_B0_P2_U0_PLD_IT4, 0x40010410 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT5, 0x40010414 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT6, 0x40010418 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT7, 0x4001041c +.set CYDEV_UCFG_B0_P2_U0_PLD_IT8, 0x40010420 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT9, 0x40010424 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT10, 0x40010428 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT11, 0x4001042c +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT0, 0x40010430 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT1, 0x40010432 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT2, 0x40010434 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT3, 0x40010436 +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e +.set CYDEV_UCFG_B0_P2_U0_CFG0, 0x40010440 +.set CYDEV_UCFG_B0_P2_U0_CFG1, 0x40010441 +.set CYDEV_UCFG_B0_P2_U0_CFG2, 0x40010442 +.set CYDEV_UCFG_B0_P2_U0_CFG3, 0x40010443 +.set CYDEV_UCFG_B0_P2_U0_CFG4, 0x40010444 +.set CYDEV_UCFG_B0_P2_U0_CFG5, 0x40010445 +.set CYDEV_UCFG_B0_P2_U0_CFG6, 0x40010446 +.set CYDEV_UCFG_B0_P2_U0_CFG7, 0x40010447 +.set CYDEV_UCFG_B0_P2_U0_CFG8, 0x40010448 +.set CYDEV_UCFG_B0_P2_U0_CFG9, 0x40010449 +.set CYDEV_UCFG_B0_P2_U0_CFG10, 0x4001044a +.set CYDEV_UCFG_B0_P2_U0_CFG11, 0x4001044b +.set CYDEV_UCFG_B0_P2_U0_CFG12, 0x4001044c +.set CYDEV_UCFG_B0_P2_U0_CFG13, 0x4001044d +.set CYDEV_UCFG_B0_P2_U0_CFG14, 0x4001044e +.set CYDEV_UCFG_B0_P2_U0_CFG15, 0x4001044f +.set CYDEV_UCFG_B0_P2_U0_CFG16, 0x40010450 +.set CYDEV_UCFG_B0_P2_U0_CFG17, 0x40010451 +.set CYDEV_UCFG_B0_P2_U0_CFG18, 0x40010452 +.set CYDEV_UCFG_B0_P2_U0_CFG19, 0x40010453 +.set CYDEV_UCFG_B0_P2_U0_CFG20, 0x40010454 +.set CYDEV_UCFG_B0_P2_U0_CFG21, 0x40010455 +.set CYDEV_UCFG_B0_P2_U0_CFG22, 0x40010456 +.set CYDEV_UCFG_B0_P2_U0_CFG23, 0x40010457 +.set CYDEV_UCFG_B0_P2_U0_CFG24, 0x40010458 +.set CYDEV_UCFG_B0_P2_U0_CFG25, 0x40010459 +.set CYDEV_UCFG_B0_P2_U0_CFG26, 0x4001045a +.set CYDEV_UCFG_B0_P2_U0_CFG27, 0x4001045b +.set CYDEV_UCFG_B0_P2_U0_CFG28, 0x4001045c +.set CYDEV_UCFG_B0_P2_U0_CFG29, 0x4001045d +.set CYDEV_UCFG_B0_P2_U0_CFG30, 0x4001045e +.set CYDEV_UCFG_B0_P2_U0_CFG31, 0x4001045f +.set CYDEV_UCFG_B0_P2_U0_DCFG0, 0x40010460 +.set CYDEV_UCFG_B0_P2_U0_DCFG1, 0x40010462 +.set CYDEV_UCFG_B0_P2_U0_DCFG2, 0x40010464 +.set CYDEV_UCFG_B0_P2_U0_DCFG3, 0x40010466 +.set CYDEV_UCFG_B0_P2_U0_DCFG4, 0x40010468 +.set CYDEV_UCFG_B0_P2_U0_DCFG5, 0x4001046a +.set CYDEV_UCFG_B0_P2_U0_DCFG6, 0x4001046c +.set CYDEV_UCFG_B0_P2_U0_DCFG7, 0x4001046e +.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT0, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT1, 0x40010484 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT2, 0x40010488 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT3, 0x4001048c +.set CYDEV_UCFG_B0_P2_U1_PLD_IT4, 0x40010490 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT5, 0x40010494 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT6, 0x40010498 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT7, 0x4001049c +.set CYDEV_UCFG_B0_P2_U1_PLD_IT8, 0x400104a0 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT9, 0x400104a4 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT10, 0x400104a8 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT11, 0x400104ac +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT0, 0x400104b0 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT1, 0x400104b2 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT2, 0x400104b4 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT3, 0x400104b6 +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be +.set CYDEV_UCFG_B0_P2_U1_CFG0, 0x400104c0 +.set CYDEV_UCFG_B0_P2_U1_CFG1, 0x400104c1 +.set CYDEV_UCFG_B0_P2_U1_CFG2, 0x400104c2 +.set CYDEV_UCFG_B0_P2_U1_CFG3, 0x400104c3 +.set CYDEV_UCFG_B0_P2_U1_CFG4, 0x400104c4 +.set CYDEV_UCFG_B0_P2_U1_CFG5, 0x400104c5 +.set CYDEV_UCFG_B0_P2_U1_CFG6, 0x400104c6 +.set CYDEV_UCFG_B0_P2_U1_CFG7, 0x400104c7 +.set CYDEV_UCFG_B0_P2_U1_CFG8, 0x400104c8 +.set CYDEV_UCFG_B0_P2_U1_CFG9, 0x400104c9 +.set CYDEV_UCFG_B0_P2_U1_CFG10, 0x400104ca +.set CYDEV_UCFG_B0_P2_U1_CFG11, 0x400104cb +.set CYDEV_UCFG_B0_P2_U1_CFG12, 0x400104cc +.set CYDEV_UCFG_B0_P2_U1_CFG13, 0x400104cd +.set CYDEV_UCFG_B0_P2_U1_CFG14, 0x400104ce +.set CYDEV_UCFG_B0_P2_U1_CFG15, 0x400104cf +.set CYDEV_UCFG_B0_P2_U1_CFG16, 0x400104d0 +.set CYDEV_UCFG_B0_P2_U1_CFG17, 0x400104d1 +.set CYDEV_UCFG_B0_P2_U1_CFG18, 0x400104d2 +.set CYDEV_UCFG_B0_P2_U1_CFG19, 0x400104d3 +.set CYDEV_UCFG_B0_P2_U1_CFG20, 0x400104d4 +.set CYDEV_UCFG_B0_P2_U1_CFG21, 0x400104d5 +.set CYDEV_UCFG_B0_P2_U1_CFG22, 0x400104d6 +.set CYDEV_UCFG_B0_P2_U1_CFG23, 0x400104d7 +.set CYDEV_UCFG_B0_P2_U1_CFG24, 0x400104d8 +.set CYDEV_UCFG_B0_P2_U1_CFG25, 0x400104d9 +.set CYDEV_UCFG_B0_P2_U1_CFG26, 0x400104da +.set CYDEV_UCFG_B0_P2_U1_CFG27, 0x400104db +.set CYDEV_UCFG_B0_P2_U1_CFG28, 0x400104dc +.set CYDEV_UCFG_B0_P2_U1_CFG29, 0x400104dd +.set CYDEV_UCFG_B0_P2_U1_CFG30, 0x400104de +.set CYDEV_UCFG_B0_P2_U1_CFG31, 0x400104df +.set CYDEV_UCFG_B0_P2_U1_DCFG0, 0x400104e0 +.set CYDEV_UCFG_B0_P2_U1_DCFG1, 0x400104e2 +.set CYDEV_UCFG_B0_P2_U1_DCFG2, 0x400104e4 +.set CYDEV_UCFG_B0_P2_U1_DCFG3, 0x400104e6 +.set CYDEV_UCFG_B0_P2_U1_DCFG4, 0x400104e8 +.set CYDEV_UCFG_B0_P2_U1_DCFG5, 0x400104ea +.set CYDEV_UCFG_B0_P2_U1_DCFG6, 0x400104ec +.set CYDEV_UCFG_B0_P2_U1_DCFG7, 0x400104ee +.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 +.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P3_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT0, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT1, 0x40010604 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT2, 0x40010608 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT3, 0x4001060c +.set CYDEV_UCFG_B0_P3_U0_PLD_IT4, 0x40010610 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT5, 0x40010614 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT6, 0x40010618 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT7, 0x4001061c +.set CYDEV_UCFG_B0_P3_U0_PLD_IT8, 0x40010620 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT9, 0x40010624 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT10, 0x40010628 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT11, 0x4001062c +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT0, 0x40010630 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT1, 0x40010632 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT2, 0x40010634 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT3, 0x40010636 +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e +.set CYDEV_UCFG_B0_P3_U0_CFG0, 0x40010640 +.set CYDEV_UCFG_B0_P3_U0_CFG1, 0x40010641 +.set CYDEV_UCFG_B0_P3_U0_CFG2, 0x40010642 +.set CYDEV_UCFG_B0_P3_U0_CFG3, 0x40010643 +.set CYDEV_UCFG_B0_P3_U0_CFG4, 0x40010644 +.set CYDEV_UCFG_B0_P3_U0_CFG5, 0x40010645 +.set CYDEV_UCFG_B0_P3_U0_CFG6, 0x40010646 +.set CYDEV_UCFG_B0_P3_U0_CFG7, 0x40010647 +.set CYDEV_UCFG_B0_P3_U0_CFG8, 0x40010648 +.set CYDEV_UCFG_B0_P3_U0_CFG9, 0x40010649 +.set CYDEV_UCFG_B0_P3_U0_CFG10, 0x4001064a +.set CYDEV_UCFG_B0_P3_U0_CFG11, 0x4001064b +.set CYDEV_UCFG_B0_P3_U0_CFG12, 0x4001064c +.set CYDEV_UCFG_B0_P3_U0_CFG13, 0x4001064d +.set CYDEV_UCFG_B0_P3_U0_CFG14, 0x4001064e +.set CYDEV_UCFG_B0_P3_U0_CFG15, 0x4001064f +.set CYDEV_UCFG_B0_P3_U0_CFG16, 0x40010650 +.set CYDEV_UCFG_B0_P3_U0_CFG17, 0x40010651 +.set CYDEV_UCFG_B0_P3_U0_CFG18, 0x40010652 +.set CYDEV_UCFG_B0_P3_U0_CFG19, 0x40010653 +.set CYDEV_UCFG_B0_P3_U0_CFG20, 0x40010654 +.set CYDEV_UCFG_B0_P3_U0_CFG21, 0x40010655 +.set CYDEV_UCFG_B0_P3_U0_CFG22, 0x40010656 +.set CYDEV_UCFG_B0_P3_U0_CFG23, 0x40010657 +.set CYDEV_UCFG_B0_P3_U0_CFG24, 0x40010658 +.set CYDEV_UCFG_B0_P3_U0_CFG25, 0x40010659 +.set CYDEV_UCFG_B0_P3_U0_CFG26, 0x4001065a +.set CYDEV_UCFG_B0_P3_U0_CFG27, 0x4001065b +.set CYDEV_UCFG_B0_P3_U0_CFG28, 0x4001065c +.set CYDEV_UCFG_B0_P3_U0_CFG29, 0x4001065d +.set CYDEV_UCFG_B0_P3_U0_CFG30, 0x4001065e +.set CYDEV_UCFG_B0_P3_U0_CFG31, 0x4001065f +.set CYDEV_UCFG_B0_P3_U0_DCFG0, 0x40010660 +.set CYDEV_UCFG_B0_P3_U0_DCFG1, 0x40010662 +.set CYDEV_UCFG_B0_P3_U0_DCFG2, 0x40010664 +.set CYDEV_UCFG_B0_P3_U0_DCFG3, 0x40010666 +.set CYDEV_UCFG_B0_P3_U0_DCFG4, 0x40010668 +.set CYDEV_UCFG_B0_P3_U0_DCFG5, 0x4001066a +.set CYDEV_UCFG_B0_P3_U0_DCFG6, 0x4001066c +.set CYDEV_UCFG_B0_P3_U0_DCFG7, 0x4001066e +.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT0, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT1, 0x40010684 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT2, 0x40010688 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT3, 0x4001068c +.set CYDEV_UCFG_B0_P3_U1_PLD_IT4, 0x40010690 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT5, 0x40010694 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT6, 0x40010698 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT7, 0x4001069c +.set CYDEV_UCFG_B0_P3_U1_PLD_IT8, 0x400106a0 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT9, 0x400106a4 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT10, 0x400106a8 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT11, 0x400106ac +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT0, 0x400106b0 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT1, 0x400106b2 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT2, 0x400106b4 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT3, 0x400106b6 +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be +.set CYDEV_UCFG_B0_P3_U1_CFG0, 0x400106c0 +.set CYDEV_UCFG_B0_P3_U1_CFG1, 0x400106c1 +.set CYDEV_UCFG_B0_P3_U1_CFG2, 0x400106c2 +.set CYDEV_UCFG_B0_P3_U1_CFG3, 0x400106c3 +.set CYDEV_UCFG_B0_P3_U1_CFG4, 0x400106c4 +.set CYDEV_UCFG_B0_P3_U1_CFG5, 0x400106c5 +.set CYDEV_UCFG_B0_P3_U1_CFG6, 0x400106c6 +.set CYDEV_UCFG_B0_P3_U1_CFG7, 0x400106c7 +.set CYDEV_UCFG_B0_P3_U1_CFG8, 0x400106c8 +.set CYDEV_UCFG_B0_P3_U1_CFG9, 0x400106c9 +.set CYDEV_UCFG_B0_P3_U1_CFG10, 0x400106ca +.set CYDEV_UCFG_B0_P3_U1_CFG11, 0x400106cb +.set CYDEV_UCFG_B0_P3_U1_CFG12, 0x400106cc +.set CYDEV_UCFG_B0_P3_U1_CFG13, 0x400106cd +.set CYDEV_UCFG_B0_P3_U1_CFG14, 0x400106ce +.set CYDEV_UCFG_B0_P3_U1_CFG15, 0x400106cf +.set CYDEV_UCFG_B0_P3_U1_CFG16, 0x400106d0 +.set CYDEV_UCFG_B0_P3_U1_CFG17, 0x400106d1 +.set CYDEV_UCFG_B0_P3_U1_CFG18, 0x400106d2 +.set CYDEV_UCFG_B0_P3_U1_CFG19, 0x400106d3 +.set CYDEV_UCFG_B0_P3_U1_CFG20, 0x400106d4 +.set CYDEV_UCFG_B0_P3_U1_CFG21, 0x400106d5 +.set CYDEV_UCFG_B0_P3_U1_CFG22, 0x400106d6 +.set CYDEV_UCFG_B0_P3_U1_CFG23, 0x400106d7 +.set CYDEV_UCFG_B0_P3_U1_CFG24, 0x400106d8 +.set CYDEV_UCFG_B0_P3_U1_CFG25, 0x400106d9 +.set CYDEV_UCFG_B0_P3_U1_CFG26, 0x400106da +.set CYDEV_UCFG_B0_P3_U1_CFG27, 0x400106db +.set CYDEV_UCFG_B0_P3_U1_CFG28, 0x400106dc +.set CYDEV_UCFG_B0_P3_U1_CFG29, 0x400106dd +.set CYDEV_UCFG_B0_P3_U1_CFG30, 0x400106de +.set CYDEV_UCFG_B0_P3_U1_CFG31, 0x400106df +.set CYDEV_UCFG_B0_P3_U1_DCFG0, 0x400106e0 +.set CYDEV_UCFG_B0_P3_U1_DCFG1, 0x400106e2 +.set CYDEV_UCFG_B0_P3_U1_DCFG2, 0x400106e4 +.set CYDEV_UCFG_B0_P3_U1_DCFG3, 0x400106e6 +.set CYDEV_UCFG_B0_P3_U1_DCFG4, 0x400106e8 +.set CYDEV_UCFG_B0_P3_U1_DCFG5, 0x400106ea +.set CYDEV_UCFG_B0_P3_U1_DCFG6, 0x400106ec +.set CYDEV_UCFG_B0_P3_U1_DCFG7, 0x400106ee +.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 +.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P4_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT0, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT1, 0x40010804 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT2, 0x40010808 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT3, 0x4001080c +.set CYDEV_UCFG_B0_P4_U0_PLD_IT4, 0x40010810 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT5, 0x40010814 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT6, 0x40010818 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT7, 0x4001081c +.set CYDEV_UCFG_B0_P4_U0_PLD_IT8, 0x40010820 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT9, 0x40010824 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT10, 0x40010828 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT11, 0x4001082c +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT0, 0x40010830 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT1, 0x40010832 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT2, 0x40010834 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT3, 0x40010836 +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e +.set CYDEV_UCFG_B0_P4_U0_CFG0, 0x40010840 +.set CYDEV_UCFG_B0_P4_U0_CFG1, 0x40010841 +.set CYDEV_UCFG_B0_P4_U0_CFG2, 0x40010842 +.set CYDEV_UCFG_B0_P4_U0_CFG3, 0x40010843 +.set CYDEV_UCFG_B0_P4_U0_CFG4, 0x40010844 +.set CYDEV_UCFG_B0_P4_U0_CFG5, 0x40010845 +.set CYDEV_UCFG_B0_P4_U0_CFG6, 0x40010846 +.set CYDEV_UCFG_B0_P4_U0_CFG7, 0x40010847 +.set CYDEV_UCFG_B0_P4_U0_CFG8, 0x40010848 +.set CYDEV_UCFG_B0_P4_U0_CFG9, 0x40010849 +.set CYDEV_UCFG_B0_P4_U0_CFG10, 0x4001084a +.set CYDEV_UCFG_B0_P4_U0_CFG11, 0x4001084b +.set CYDEV_UCFG_B0_P4_U0_CFG12, 0x4001084c +.set CYDEV_UCFG_B0_P4_U0_CFG13, 0x4001084d +.set CYDEV_UCFG_B0_P4_U0_CFG14, 0x4001084e +.set CYDEV_UCFG_B0_P4_U0_CFG15, 0x4001084f +.set CYDEV_UCFG_B0_P4_U0_CFG16, 0x40010850 +.set CYDEV_UCFG_B0_P4_U0_CFG17, 0x40010851 +.set CYDEV_UCFG_B0_P4_U0_CFG18, 0x40010852 +.set CYDEV_UCFG_B0_P4_U0_CFG19, 0x40010853 +.set CYDEV_UCFG_B0_P4_U0_CFG20, 0x40010854 +.set CYDEV_UCFG_B0_P4_U0_CFG21, 0x40010855 +.set CYDEV_UCFG_B0_P4_U0_CFG22, 0x40010856 +.set CYDEV_UCFG_B0_P4_U0_CFG23, 0x40010857 +.set CYDEV_UCFG_B0_P4_U0_CFG24, 0x40010858 +.set CYDEV_UCFG_B0_P4_U0_CFG25, 0x40010859 +.set CYDEV_UCFG_B0_P4_U0_CFG26, 0x4001085a +.set CYDEV_UCFG_B0_P4_U0_CFG27, 0x4001085b +.set CYDEV_UCFG_B0_P4_U0_CFG28, 0x4001085c +.set CYDEV_UCFG_B0_P4_U0_CFG29, 0x4001085d +.set CYDEV_UCFG_B0_P4_U0_CFG30, 0x4001085e +.set CYDEV_UCFG_B0_P4_U0_CFG31, 0x4001085f +.set CYDEV_UCFG_B0_P4_U0_DCFG0, 0x40010860 +.set CYDEV_UCFG_B0_P4_U0_DCFG1, 0x40010862 +.set CYDEV_UCFG_B0_P4_U0_DCFG2, 0x40010864 +.set CYDEV_UCFG_B0_P4_U0_DCFG3, 0x40010866 +.set CYDEV_UCFG_B0_P4_U0_DCFG4, 0x40010868 +.set CYDEV_UCFG_B0_P4_U0_DCFG5, 0x4001086a +.set CYDEV_UCFG_B0_P4_U0_DCFG6, 0x4001086c +.set CYDEV_UCFG_B0_P4_U0_DCFG7, 0x4001086e +.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT0, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT1, 0x40010884 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT2, 0x40010888 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT3, 0x4001088c +.set CYDEV_UCFG_B0_P4_U1_PLD_IT4, 0x40010890 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT5, 0x40010894 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT6, 0x40010898 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT7, 0x4001089c +.set CYDEV_UCFG_B0_P4_U1_PLD_IT8, 0x400108a0 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT9, 0x400108a4 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT10, 0x400108a8 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT11, 0x400108ac +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT0, 0x400108b0 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT1, 0x400108b2 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT2, 0x400108b4 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT3, 0x400108b6 +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be +.set CYDEV_UCFG_B0_P4_U1_CFG0, 0x400108c0 +.set CYDEV_UCFG_B0_P4_U1_CFG1, 0x400108c1 +.set CYDEV_UCFG_B0_P4_U1_CFG2, 0x400108c2 +.set CYDEV_UCFG_B0_P4_U1_CFG3, 0x400108c3 +.set CYDEV_UCFG_B0_P4_U1_CFG4, 0x400108c4 +.set CYDEV_UCFG_B0_P4_U1_CFG5, 0x400108c5 +.set CYDEV_UCFG_B0_P4_U1_CFG6, 0x400108c6 +.set CYDEV_UCFG_B0_P4_U1_CFG7, 0x400108c7 +.set CYDEV_UCFG_B0_P4_U1_CFG8, 0x400108c8 +.set CYDEV_UCFG_B0_P4_U1_CFG9, 0x400108c9 +.set CYDEV_UCFG_B0_P4_U1_CFG10, 0x400108ca +.set CYDEV_UCFG_B0_P4_U1_CFG11, 0x400108cb +.set CYDEV_UCFG_B0_P4_U1_CFG12, 0x400108cc +.set CYDEV_UCFG_B0_P4_U1_CFG13, 0x400108cd +.set CYDEV_UCFG_B0_P4_U1_CFG14, 0x400108ce +.set CYDEV_UCFG_B0_P4_U1_CFG15, 0x400108cf +.set CYDEV_UCFG_B0_P4_U1_CFG16, 0x400108d0 +.set CYDEV_UCFG_B0_P4_U1_CFG17, 0x400108d1 +.set CYDEV_UCFG_B0_P4_U1_CFG18, 0x400108d2 +.set CYDEV_UCFG_B0_P4_U1_CFG19, 0x400108d3 +.set CYDEV_UCFG_B0_P4_U1_CFG20, 0x400108d4 +.set CYDEV_UCFG_B0_P4_U1_CFG21, 0x400108d5 +.set CYDEV_UCFG_B0_P4_U1_CFG22, 0x400108d6 +.set CYDEV_UCFG_B0_P4_U1_CFG23, 0x400108d7 +.set CYDEV_UCFG_B0_P4_U1_CFG24, 0x400108d8 +.set CYDEV_UCFG_B0_P4_U1_CFG25, 0x400108d9 +.set CYDEV_UCFG_B0_P4_U1_CFG26, 0x400108da +.set CYDEV_UCFG_B0_P4_U1_CFG27, 0x400108db +.set CYDEV_UCFG_B0_P4_U1_CFG28, 0x400108dc +.set CYDEV_UCFG_B0_P4_U1_CFG29, 0x400108dd +.set CYDEV_UCFG_B0_P4_U1_CFG30, 0x400108de +.set CYDEV_UCFG_B0_P4_U1_CFG31, 0x400108df +.set CYDEV_UCFG_B0_P4_U1_DCFG0, 0x400108e0 +.set CYDEV_UCFG_B0_P4_U1_DCFG1, 0x400108e2 +.set CYDEV_UCFG_B0_P4_U1_DCFG2, 0x400108e4 +.set CYDEV_UCFG_B0_P4_U1_DCFG3, 0x400108e6 +.set CYDEV_UCFG_B0_P4_U1_DCFG4, 0x400108e8 +.set CYDEV_UCFG_B0_P4_U1_DCFG5, 0x400108ea +.set CYDEV_UCFG_B0_P4_U1_DCFG6, 0x400108ec +.set CYDEV_UCFG_B0_P4_U1_DCFG7, 0x400108ee +.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 +.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT0, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT1, 0x40010a04 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT2, 0x40010a08 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT3, 0x40010a0c +.set CYDEV_UCFG_B0_P5_U0_PLD_IT4, 0x40010a10 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT5, 0x40010a14 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT6, 0x40010a18 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT7, 0x40010a1c +.set CYDEV_UCFG_B0_P5_U0_PLD_IT8, 0x40010a20 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT9, 0x40010a24 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT10, 0x40010a28 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT11, 0x40010a2c +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT0, 0x40010a30 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT1, 0x40010a32 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT2, 0x40010a34 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT3, 0x40010a36 +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e +.set CYDEV_UCFG_B0_P5_U0_CFG0, 0x40010a40 +.set CYDEV_UCFG_B0_P5_U0_CFG1, 0x40010a41 +.set CYDEV_UCFG_B0_P5_U0_CFG2, 0x40010a42 +.set CYDEV_UCFG_B0_P5_U0_CFG3, 0x40010a43 +.set CYDEV_UCFG_B0_P5_U0_CFG4, 0x40010a44 +.set CYDEV_UCFG_B0_P5_U0_CFG5, 0x40010a45 +.set CYDEV_UCFG_B0_P5_U0_CFG6, 0x40010a46 +.set CYDEV_UCFG_B0_P5_U0_CFG7, 0x40010a47 +.set CYDEV_UCFG_B0_P5_U0_CFG8, 0x40010a48 +.set CYDEV_UCFG_B0_P5_U0_CFG9, 0x40010a49 +.set CYDEV_UCFG_B0_P5_U0_CFG10, 0x40010a4a +.set CYDEV_UCFG_B0_P5_U0_CFG11, 0x40010a4b +.set CYDEV_UCFG_B0_P5_U0_CFG12, 0x40010a4c +.set CYDEV_UCFG_B0_P5_U0_CFG13, 0x40010a4d +.set CYDEV_UCFG_B0_P5_U0_CFG14, 0x40010a4e +.set CYDEV_UCFG_B0_P5_U0_CFG15, 0x40010a4f +.set CYDEV_UCFG_B0_P5_U0_CFG16, 0x40010a50 +.set CYDEV_UCFG_B0_P5_U0_CFG17, 0x40010a51 +.set CYDEV_UCFG_B0_P5_U0_CFG18, 0x40010a52 +.set CYDEV_UCFG_B0_P5_U0_CFG19, 0x40010a53 +.set CYDEV_UCFG_B0_P5_U0_CFG20, 0x40010a54 +.set CYDEV_UCFG_B0_P5_U0_CFG21, 0x40010a55 +.set CYDEV_UCFG_B0_P5_U0_CFG22, 0x40010a56 +.set CYDEV_UCFG_B0_P5_U0_CFG23, 0x40010a57 +.set CYDEV_UCFG_B0_P5_U0_CFG24, 0x40010a58 +.set CYDEV_UCFG_B0_P5_U0_CFG25, 0x40010a59 +.set CYDEV_UCFG_B0_P5_U0_CFG26, 0x40010a5a +.set CYDEV_UCFG_B0_P5_U0_CFG27, 0x40010a5b +.set CYDEV_UCFG_B0_P5_U0_CFG28, 0x40010a5c +.set CYDEV_UCFG_B0_P5_U0_CFG29, 0x40010a5d +.set CYDEV_UCFG_B0_P5_U0_CFG30, 0x40010a5e +.set CYDEV_UCFG_B0_P5_U0_CFG31, 0x40010a5f +.set CYDEV_UCFG_B0_P5_U0_DCFG0, 0x40010a60 +.set CYDEV_UCFG_B0_P5_U0_DCFG1, 0x40010a62 +.set CYDEV_UCFG_B0_P5_U0_DCFG2, 0x40010a64 +.set CYDEV_UCFG_B0_P5_U0_DCFG3, 0x40010a66 +.set CYDEV_UCFG_B0_P5_U0_DCFG4, 0x40010a68 +.set CYDEV_UCFG_B0_P5_U0_DCFG5, 0x40010a6a +.set CYDEV_UCFG_B0_P5_U0_DCFG6, 0x40010a6c +.set CYDEV_UCFG_B0_P5_U0_DCFG7, 0x40010a6e +.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT0, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT1, 0x40010a84 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT2, 0x40010a88 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT3, 0x40010a8c +.set CYDEV_UCFG_B0_P5_U1_PLD_IT4, 0x40010a90 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT5, 0x40010a94 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT6, 0x40010a98 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT7, 0x40010a9c +.set CYDEV_UCFG_B0_P5_U1_PLD_IT8, 0x40010aa0 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT9, 0x40010aa4 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT10, 0x40010aa8 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT11, 0x40010aac +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT0, 0x40010ab0 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT1, 0x40010ab2 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT2, 0x40010ab4 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT3, 0x40010ab6 +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe +.set CYDEV_UCFG_B0_P5_U1_CFG0, 0x40010ac0 +.set CYDEV_UCFG_B0_P5_U1_CFG1, 0x40010ac1 +.set CYDEV_UCFG_B0_P5_U1_CFG2, 0x40010ac2 +.set CYDEV_UCFG_B0_P5_U1_CFG3, 0x40010ac3 +.set CYDEV_UCFG_B0_P5_U1_CFG4, 0x40010ac4 +.set CYDEV_UCFG_B0_P5_U1_CFG5, 0x40010ac5 +.set CYDEV_UCFG_B0_P5_U1_CFG6, 0x40010ac6 +.set CYDEV_UCFG_B0_P5_U1_CFG7, 0x40010ac7 +.set CYDEV_UCFG_B0_P5_U1_CFG8, 0x40010ac8 +.set CYDEV_UCFG_B0_P5_U1_CFG9, 0x40010ac9 +.set CYDEV_UCFG_B0_P5_U1_CFG10, 0x40010aca +.set CYDEV_UCFG_B0_P5_U1_CFG11, 0x40010acb +.set CYDEV_UCFG_B0_P5_U1_CFG12, 0x40010acc +.set CYDEV_UCFG_B0_P5_U1_CFG13, 0x40010acd +.set CYDEV_UCFG_B0_P5_U1_CFG14, 0x40010ace +.set CYDEV_UCFG_B0_P5_U1_CFG15, 0x40010acf +.set CYDEV_UCFG_B0_P5_U1_CFG16, 0x40010ad0 +.set CYDEV_UCFG_B0_P5_U1_CFG17, 0x40010ad1 +.set CYDEV_UCFG_B0_P5_U1_CFG18, 0x40010ad2 +.set CYDEV_UCFG_B0_P5_U1_CFG19, 0x40010ad3 +.set CYDEV_UCFG_B0_P5_U1_CFG20, 0x40010ad4 +.set CYDEV_UCFG_B0_P5_U1_CFG21, 0x40010ad5 +.set CYDEV_UCFG_B0_P5_U1_CFG22, 0x40010ad6 +.set CYDEV_UCFG_B0_P5_U1_CFG23, 0x40010ad7 +.set CYDEV_UCFG_B0_P5_U1_CFG24, 0x40010ad8 +.set CYDEV_UCFG_B0_P5_U1_CFG25, 0x40010ad9 +.set CYDEV_UCFG_B0_P5_U1_CFG26, 0x40010ada +.set CYDEV_UCFG_B0_P5_U1_CFG27, 0x40010adb +.set CYDEV_UCFG_B0_P5_U1_CFG28, 0x40010adc +.set CYDEV_UCFG_B0_P5_U1_CFG29, 0x40010add +.set CYDEV_UCFG_B0_P5_U1_CFG30, 0x40010ade +.set CYDEV_UCFG_B0_P5_U1_CFG31, 0x40010adf +.set CYDEV_UCFG_B0_P5_U1_DCFG0, 0x40010ae0 +.set CYDEV_UCFG_B0_P5_U1_DCFG1, 0x40010ae2 +.set CYDEV_UCFG_B0_P5_U1_DCFG2, 0x40010ae4 +.set CYDEV_UCFG_B0_P5_U1_DCFG3, 0x40010ae6 +.set CYDEV_UCFG_B0_P5_U1_DCFG4, 0x40010ae8 +.set CYDEV_UCFG_B0_P5_U1_DCFG5, 0x40010aea +.set CYDEV_UCFG_B0_P5_U1_DCFG6, 0x40010aec +.set CYDEV_UCFG_B0_P5_U1_DCFG7, 0x40010aee +.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 +.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT0, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT1, 0x40010c04 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT2, 0x40010c08 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT3, 0x40010c0c +.set CYDEV_UCFG_B0_P6_U0_PLD_IT4, 0x40010c10 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT5, 0x40010c14 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT6, 0x40010c18 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT7, 0x40010c1c +.set CYDEV_UCFG_B0_P6_U0_PLD_IT8, 0x40010c20 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT9, 0x40010c24 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT10, 0x40010c28 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT11, 0x40010c2c +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT0, 0x40010c30 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT1, 0x40010c32 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT2, 0x40010c34 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT3, 0x40010c36 +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e +.set CYDEV_UCFG_B0_P6_U0_CFG0, 0x40010c40 +.set CYDEV_UCFG_B0_P6_U0_CFG1, 0x40010c41 +.set CYDEV_UCFG_B0_P6_U0_CFG2, 0x40010c42 +.set CYDEV_UCFG_B0_P6_U0_CFG3, 0x40010c43 +.set CYDEV_UCFG_B0_P6_U0_CFG4, 0x40010c44 +.set CYDEV_UCFG_B0_P6_U0_CFG5, 0x40010c45 +.set CYDEV_UCFG_B0_P6_U0_CFG6, 0x40010c46 +.set CYDEV_UCFG_B0_P6_U0_CFG7, 0x40010c47 +.set CYDEV_UCFG_B0_P6_U0_CFG8, 0x40010c48 +.set CYDEV_UCFG_B0_P6_U0_CFG9, 0x40010c49 +.set CYDEV_UCFG_B0_P6_U0_CFG10, 0x40010c4a +.set CYDEV_UCFG_B0_P6_U0_CFG11, 0x40010c4b +.set CYDEV_UCFG_B0_P6_U0_CFG12, 0x40010c4c +.set CYDEV_UCFG_B0_P6_U0_CFG13, 0x40010c4d +.set CYDEV_UCFG_B0_P6_U0_CFG14, 0x40010c4e +.set CYDEV_UCFG_B0_P6_U0_CFG15, 0x40010c4f +.set CYDEV_UCFG_B0_P6_U0_CFG16, 0x40010c50 +.set CYDEV_UCFG_B0_P6_U0_CFG17, 0x40010c51 +.set CYDEV_UCFG_B0_P6_U0_CFG18, 0x40010c52 +.set CYDEV_UCFG_B0_P6_U0_CFG19, 0x40010c53 +.set CYDEV_UCFG_B0_P6_U0_CFG20, 0x40010c54 +.set CYDEV_UCFG_B0_P6_U0_CFG21, 0x40010c55 +.set CYDEV_UCFG_B0_P6_U0_CFG22, 0x40010c56 +.set CYDEV_UCFG_B0_P6_U0_CFG23, 0x40010c57 +.set CYDEV_UCFG_B0_P6_U0_CFG24, 0x40010c58 +.set CYDEV_UCFG_B0_P6_U0_CFG25, 0x40010c59 +.set CYDEV_UCFG_B0_P6_U0_CFG26, 0x40010c5a +.set CYDEV_UCFG_B0_P6_U0_CFG27, 0x40010c5b +.set CYDEV_UCFG_B0_P6_U0_CFG28, 0x40010c5c +.set CYDEV_UCFG_B0_P6_U0_CFG29, 0x40010c5d +.set CYDEV_UCFG_B0_P6_U0_CFG30, 0x40010c5e +.set CYDEV_UCFG_B0_P6_U0_CFG31, 0x40010c5f +.set CYDEV_UCFG_B0_P6_U0_DCFG0, 0x40010c60 +.set CYDEV_UCFG_B0_P6_U0_DCFG1, 0x40010c62 +.set CYDEV_UCFG_B0_P6_U0_DCFG2, 0x40010c64 +.set CYDEV_UCFG_B0_P6_U0_DCFG3, 0x40010c66 +.set CYDEV_UCFG_B0_P6_U0_DCFG4, 0x40010c68 +.set CYDEV_UCFG_B0_P6_U0_DCFG5, 0x40010c6a +.set CYDEV_UCFG_B0_P6_U0_DCFG6, 0x40010c6c +.set CYDEV_UCFG_B0_P6_U0_DCFG7, 0x40010c6e +.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT0, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT1, 0x40010c84 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT2, 0x40010c88 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT3, 0x40010c8c +.set CYDEV_UCFG_B0_P6_U1_PLD_IT4, 0x40010c90 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT5, 0x40010c94 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT6, 0x40010c98 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT7, 0x40010c9c +.set CYDEV_UCFG_B0_P6_U1_PLD_IT8, 0x40010ca0 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT9, 0x40010ca4 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT10, 0x40010ca8 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT11, 0x40010cac +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT0, 0x40010cb0 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT1, 0x40010cb2 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT2, 0x40010cb4 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT3, 0x40010cb6 +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe +.set CYDEV_UCFG_B0_P6_U1_CFG0, 0x40010cc0 +.set CYDEV_UCFG_B0_P6_U1_CFG1, 0x40010cc1 +.set CYDEV_UCFG_B0_P6_U1_CFG2, 0x40010cc2 +.set CYDEV_UCFG_B0_P6_U1_CFG3, 0x40010cc3 +.set CYDEV_UCFG_B0_P6_U1_CFG4, 0x40010cc4 +.set CYDEV_UCFG_B0_P6_U1_CFG5, 0x40010cc5 +.set CYDEV_UCFG_B0_P6_U1_CFG6, 0x40010cc6 +.set CYDEV_UCFG_B0_P6_U1_CFG7, 0x40010cc7 +.set CYDEV_UCFG_B0_P6_U1_CFG8, 0x40010cc8 +.set CYDEV_UCFG_B0_P6_U1_CFG9, 0x40010cc9 +.set CYDEV_UCFG_B0_P6_U1_CFG10, 0x40010cca +.set CYDEV_UCFG_B0_P6_U1_CFG11, 0x40010ccb +.set CYDEV_UCFG_B0_P6_U1_CFG12, 0x40010ccc +.set CYDEV_UCFG_B0_P6_U1_CFG13, 0x40010ccd +.set CYDEV_UCFG_B0_P6_U1_CFG14, 0x40010cce +.set CYDEV_UCFG_B0_P6_U1_CFG15, 0x40010ccf +.set CYDEV_UCFG_B0_P6_U1_CFG16, 0x40010cd0 +.set CYDEV_UCFG_B0_P6_U1_CFG17, 0x40010cd1 +.set CYDEV_UCFG_B0_P6_U1_CFG18, 0x40010cd2 +.set CYDEV_UCFG_B0_P6_U1_CFG19, 0x40010cd3 +.set CYDEV_UCFG_B0_P6_U1_CFG20, 0x40010cd4 +.set CYDEV_UCFG_B0_P6_U1_CFG21, 0x40010cd5 +.set CYDEV_UCFG_B0_P6_U1_CFG22, 0x40010cd6 +.set CYDEV_UCFG_B0_P6_U1_CFG23, 0x40010cd7 +.set CYDEV_UCFG_B0_P6_U1_CFG24, 0x40010cd8 +.set CYDEV_UCFG_B0_P6_U1_CFG25, 0x40010cd9 +.set CYDEV_UCFG_B0_P6_U1_CFG26, 0x40010cda +.set CYDEV_UCFG_B0_P6_U1_CFG27, 0x40010cdb +.set CYDEV_UCFG_B0_P6_U1_CFG28, 0x40010cdc +.set CYDEV_UCFG_B0_P6_U1_CFG29, 0x40010cdd +.set CYDEV_UCFG_B0_P6_U1_CFG30, 0x40010cde +.set CYDEV_UCFG_B0_P6_U1_CFG31, 0x40010cdf +.set CYDEV_UCFG_B0_P6_U1_DCFG0, 0x40010ce0 +.set CYDEV_UCFG_B0_P6_U1_DCFG1, 0x40010ce2 +.set CYDEV_UCFG_B0_P6_U1_DCFG2, 0x40010ce4 +.set CYDEV_UCFG_B0_P6_U1_DCFG3, 0x40010ce6 +.set CYDEV_UCFG_B0_P6_U1_DCFG4, 0x40010ce8 +.set CYDEV_UCFG_B0_P6_U1_DCFG5, 0x40010cea +.set CYDEV_UCFG_B0_P6_U1_DCFG6, 0x40010cec +.set CYDEV_UCFG_B0_P6_U1_DCFG7, 0x40010cee +.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 +.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT0, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT1, 0x40010e04 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT2, 0x40010e08 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT3, 0x40010e0c +.set CYDEV_UCFG_B0_P7_U0_PLD_IT4, 0x40010e10 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT5, 0x40010e14 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT6, 0x40010e18 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT7, 0x40010e1c +.set CYDEV_UCFG_B0_P7_U0_PLD_IT8, 0x40010e20 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT9, 0x40010e24 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT10, 0x40010e28 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT11, 0x40010e2c +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT0, 0x40010e30 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT1, 0x40010e32 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT2, 0x40010e34 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT3, 0x40010e36 +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e +.set CYDEV_UCFG_B0_P7_U0_CFG0, 0x40010e40 +.set CYDEV_UCFG_B0_P7_U0_CFG1, 0x40010e41 +.set CYDEV_UCFG_B0_P7_U0_CFG2, 0x40010e42 +.set CYDEV_UCFG_B0_P7_U0_CFG3, 0x40010e43 +.set CYDEV_UCFG_B0_P7_U0_CFG4, 0x40010e44 +.set CYDEV_UCFG_B0_P7_U0_CFG5, 0x40010e45 +.set CYDEV_UCFG_B0_P7_U0_CFG6, 0x40010e46 +.set CYDEV_UCFG_B0_P7_U0_CFG7, 0x40010e47 +.set CYDEV_UCFG_B0_P7_U0_CFG8, 0x40010e48 +.set CYDEV_UCFG_B0_P7_U0_CFG9, 0x40010e49 +.set CYDEV_UCFG_B0_P7_U0_CFG10, 0x40010e4a +.set CYDEV_UCFG_B0_P7_U0_CFG11, 0x40010e4b +.set CYDEV_UCFG_B0_P7_U0_CFG12, 0x40010e4c +.set CYDEV_UCFG_B0_P7_U0_CFG13, 0x40010e4d +.set CYDEV_UCFG_B0_P7_U0_CFG14, 0x40010e4e +.set CYDEV_UCFG_B0_P7_U0_CFG15, 0x40010e4f +.set CYDEV_UCFG_B0_P7_U0_CFG16, 0x40010e50 +.set CYDEV_UCFG_B0_P7_U0_CFG17, 0x40010e51 +.set CYDEV_UCFG_B0_P7_U0_CFG18, 0x40010e52 +.set CYDEV_UCFG_B0_P7_U0_CFG19, 0x40010e53 +.set CYDEV_UCFG_B0_P7_U0_CFG20, 0x40010e54 +.set CYDEV_UCFG_B0_P7_U0_CFG21, 0x40010e55 +.set CYDEV_UCFG_B0_P7_U0_CFG22, 0x40010e56 +.set CYDEV_UCFG_B0_P7_U0_CFG23, 0x40010e57 +.set CYDEV_UCFG_B0_P7_U0_CFG24, 0x40010e58 +.set CYDEV_UCFG_B0_P7_U0_CFG25, 0x40010e59 +.set CYDEV_UCFG_B0_P7_U0_CFG26, 0x40010e5a +.set CYDEV_UCFG_B0_P7_U0_CFG27, 0x40010e5b +.set CYDEV_UCFG_B0_P7_U0_CFG28, 0x40010e5c +.set CYDEV_UCFG_B0_P7_U0_CFG29, 0x40010e5d +.set CYDEV_UCFG_B0_P7_U0_CFG30, 0x40010e5e +.set CYDEV_UCFG_B0_P7_U0_CFG31, 0x40010e5f +.set CYDEV_UCFG_B0_P7_U0_DCFG0, 0x40010e60 +.set CYDEV_UCFG_B0_P7_U0_DCFG1, 0x40010e62 +.set CYDEV_UCFG_B0_P7_U0_DCFG2, 0x40010e64 +.set CYDEV_UCFG_B0_P7_U0_DCFG3, 0x40010e66 +.set CYDEV_UCFG_B0_P7_U0_DCFG4, 0x40010e68 +.set CYDEV_UCFG_B0_P7_U0_DCFG5, 0x40010e6a +.set CYDEV_UCFG_B0_P7_U0_DCFG6, 0x40010e6c +.set CYDEV_UCFG_B0_P7_U0_DCFG7, 0x40010e6e +.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT0, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT1, 0x40010e84 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT2, 0x40010e88 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT3, 0x40010e8c +.set CYDEV_UCFG_B0_P7_U1_PLD_IT4, 0x40010e90 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT5, 0x40010e94 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT6, 0x40010e98 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT7, 0x40010e9c +.set CYDEV_UCFG_B0_P7_U1_PLD_IT8, 0x40010ea0 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT9, 0x40010ea4 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT10, 0x40010ea8 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT11, 0x40010eac +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT0, 0x40010eb0 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT1, 0x40010eb2 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT2, 0x40010eb4 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT3, 0x40010eb6 +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe +.set CYDEV_UCFG_B0_P7_U1_CFG0, 0x40010ec0 +.set CYDEV_UCFG_B0_P7_U1_CFG1, 0x40010ec1 +.set CYDEV_UCFG_B0_P7_U1_CFG2, 0x40010ec2 +.set CYDEV_UCFG_B0_P7_U1_CFG3, 0x40010ec3 +.set CYDEV_UCFG_B0_P7_U1_CFG4, 0x40010ec4 +.set CYDEV_UCFG_B0_P7_U1_CFG5, 0x40010ec5 +.set CYDEV_UCFG_B0_P7_U1_CFG6, 0x40010ec6 +.set CYDEV_UCFG_B0_P7_U1_CFG7, 0x40010ec7 +.set CYDEV_UCFG_B0_P7_U1_CFG8, 0x40010ec8 +.set CYDEV_UCFG_B0_P7_U1_CFG9, 0x40010ec9 +.set CYDEV_UCFG_B0_P7_U1_CFG10, 0x40010eca +.set CYDEV_UCFG_B0_P7_U1_CFG11, 0x40010ecb +.set CYDEV_UCFG_B0_P7_U1_CFG12, 0x40010ecc +.set CYDEV_UCFG_B0_P7_U1_CFG13, 0x40010ecd +.set CYDEV_UCFG_B0_P7_U1_CFG14, 0x40010ece +.set CYDEV_UCFG_B0_P7_U1_CFG15, 0x40010ecf +.set CYDEV_UCFG_B0_P7_U1_CFG16, 0x40010ed0 +.set CYDEV_UCFG_B0_P7_U1_CFG17, 0x40010ed1 +.set CYDEV_UCFG_B0_P7_U1_CFG18, 0x40010ed2 +.set CYDEV_UCFG_B0_P7_U1_CFG19, 0x40010ed3 +.set CYDEV_UCFG_B0_P7_U1_CFG20, 0x40010ed4 +.set CYDEV_UCFG_B0_P7_U1_CFG21, 0x40010ed5 +.set CYDEV_UCFG_B0_P7_U1_CFG22, 0x40010ed6 +.set CYDEV_UCFG_B0_P7_U1_CFG23, 0x40010ed7 +.set CYDEV_UCFG_B0_P7_U1_CFG24, 0x40010ed8 +.set CYDEV_UCFG_B0_P7_U1_CFG25, 0x40010ed9 +.set CYDEV_UCFG_B0_P7_U1_CFG26, 0x40010eda +.set CYDEV_UCFG_B0_P7_U1_CFG27, 0x40010edb +.set CYDEV_UCFG_B0_P7_U1_CFG28, 0x40010edc +.set CYDEV_UCFG_B0_P7_U1_CFG29, 0x40010edd +.set CYDEV_UCFG_B0_P7_U1_CFG30, 0x40010ede +.set CYDEV_UCFG_B0_P7_U1_CFG31, 0x40010edf +.set CYDEV_UCFG_B0_P7_U1_DCFG0, 0x40010ee0 +.set CYDEV_UCFG_B0_P7_U1_DCFG1, 0x40010ee2 +.set CYDEV_UCFG_B0_P7_U1_DCFG2, 0x40010ee4 +.set CYDEV_UCFG_B0_P7_U1_DCFG3, 0x40010ee6 +.set CYDEV_UCFG_B0_P7_U1_DCFG4, 0x40010ee8 +.set CYDEV_UCFG_B0_P7_U1_DCFG5, 0x40010eea +.set CYDEV_UCFG_B0_P7_U1_DCFG6, 0x40010eec +.set CYDEV_UCFG_B0_P7_U1_DCFG7, 0x40010eee +.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 +.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_BASE, 0x40011000 +.set CYDEV_UCFG_B1_SIZE, 0x00000fef +.set CYDEV_UCFG_B1_P2_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT0, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT1, 0x40011404 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT2, 0x40011408 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT3, 0x4001140c +.set CYDEV_UCFG_B1_P2_U0_PLD_IT4, 0x40011410 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT5, 0x40011414 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT6, 0x40011418 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT7, 0x4001141c +.set CYDEV_UCFG_B1_P2_U0_PLD_IT8, 0x40011420 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT9, 0x40011424 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT10, 0x40011428 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT11, 0x4001142c +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT0, 0x40011430 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT1, 0x40011432 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT2, 0x40011434 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT3, 0x40011436 +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e +.set CYDEV_UCFG_B1_P2_U0_CFG0, 0x40011440 +.set CYDEV_UCFG_B1_P2_U0_CFG1, 0x40011441 +.set CYDEV_UCFG_B1_P2_U0_CFG2, 0x40011442 +.set CYDEV_UCFG_B1_P2_U0_CFG3, 0x40011443 +.set CYDEV_UCFG_B1_P2_U0_CFG4, 0x40011444 +.set CYDEV_UCFG_B1_P2_U0_CFG5, 0x40011445 +.set CYDEV_UCFG_B1_P2_U0_CFG6, 0x40011446 +.set CYDEV_UCFG_B1_P2_U0_CFG7, 0x40011447 +.set CYDEV_UCFG_B1_P2_U0_CFG8, 0x40011448 +.set CYDEV_UCFG_B1_P2_U0_CFG9, 0x40011449 +.set CYDEV_UCFG_B1_P2_U0_CFG10, 0x4001144a +.set CYDEV_UCFG_B1_P2_U0_CFG11, 0x4001144b +.set CYDEV_UCFG_B1_P2_U0_CFG12, 0x4001144c +.set CYDEV_UCFG_B1_P2_U0_CFG13, 0x4001144d +.set CYDEV_UCFG_B1_P2_U0_CFG14, 0x4001144e +.set CYDEV_UCFG_B1_P2_U0_CFG15, 0x4001144f +.set CYDEV_UCFG_B1_P2_U0_CFG16, 0x40011450 +.set CYDEV_UCFG_B1_P2_U0_CFG17, 0x40011451 +.set CYDEV_UCFG_B1_P2_U0_CFG18, 0x40011452 +.set CYDEV_UCFG_B1_P2_U0_CFG19, 0x40011453 +.set CYDEV_UCFG_B1_P2_U0_CFG20, 0x40011454 +.set CYDEV_UCFG_B1_P2_U0_CFG21, 0x40011455 +.set CYDEV_UCFG_B1_P2_U0_CFG22, 0x40011456 +.set CYDEV_UCFG_B1_P2_U0_CFG23, 0x40011457 +.set CYDEV_UCFG_B1_P2_U0_CFG24, 0x40011458 +.set CYDEV_UCFG_B1_P2_U0_CFG25, 0x40011459 +.set CYDEV_UCFG_B1_P2_U0_CFG26, 0x4001145a +.set CYDEV_UCFG_B1_P2_U0_CFG27, 0x4001145b +.set CYDEV_UCFG_B1_P2_U0_CFG28, 0x4001145c +.set CYDEV_UCFG_B1_P2_U0_CFG29, 0x4001145d +.set CYDEV_UCFG_B1_P2_U0_CFG30, 0x4001145e +.set CYDEV_UCFG_B1_P2_U0_CFG31, 0x4001145f +.set CYDEV_UCFG_B1_P2_U0_DCFG0, 0x40011460 +.set CYDEV_UCFG_B1_P2_U0_DCFG1, 0x40011462 +.set CYDEV_UCFG_B1_P2_U0_DCFG2, 0x40011464 +.set CYDEV_UCFG_B1_P2_U0_DCFG3, 0x40011466 +.set CYDEV_UCFG_B1_P2_U0_DCFG4, 0x40011468 +.set CYDEV_UCFG_B1_P2_U0_DCFG5, 0x4001146a +.set CYDEV_UCFG_B1_P2_U0_DCFG6, 0x4001146c +.set CYDEV_UCFG_B1_P2_U0_DCFG7, 0x4001146e +.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT0, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT1, 0x40011484 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT2, 0x40011488 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT3, 0x4001148c +.set CYDEV_UCFG_B1_P2_U1_PLD_IT4, 0x40011490 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT5, 0x40011494 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT6, 0x40011498 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT7, 0x4001149c +.set CYDEV_UCFG_B1_P2_U1_PLD_IT8, 0x400114a0 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT9, 0x400114a4 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT10, 0x400114a8 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT11, 0x400114ac +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT0, 0x400114b0 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT1, 0x400114b2 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT2, 0x400114b4 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT3, 0x400114b6 +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be +.set CYDEV_UCFG_B1_P2_U1_CFG0, 0x400114c0 +.set CYDEV_UCFG_B1_P2_U1_CFG1, 0x400114c1 +.set CYDEV_UCFG_B1_P2_U1_CFG2, 0x400114c2 +.set CYDEV_UCFG_B1_P2_U1_CFG3, 0x400114c3 +.set CYDEV_UCFG_B1_P2_U1_CFG4, 0x400114c4 +.set CYDEV_UCFG_B1_P2_U1_CFG5, 0x400114c5 +.set CYDEV_UCFG_B1_P2_U1_CFG6, 0x400114c6 +.set CYDEV_UCFG_B1_P2_U1_CFG7, 0x400114c7 +.set CYDEV_UCFG_B1_P2_U1_CFG8, 0x400114c8 +.set CYDEV_UCFG_B1_P2_U1_CFG9, 0x400114c9 +.set CYDEV_UCFG_B1_P2_U1_CFG10, 0x400114ca +.set CYDEV_UCFG_B1_P2_U1_CFG11, 0x400114cb +.set CYDEV_UCFG_B1_P2_U1_CFG12, 0x400114cc +.set CYDEV_UCFG_B1_P2_U1_CFG13, 0x400114cd +.set CYDEV_UCFG_B1_P2_U1_CFG14, 0x400114ce +.set CYDEV_UCFG_B1_P2_U1_CFG15, 0x400114cf +.set CYDEV_UCFG_B1_P2_U1_CFG16, 0x400114d0 +.set CYDEV_UCFG_B1_P2_U1_CFG17, 0x400114d1 +.set CYDEV_UCFG_B1_P2_U1_CFG18, 0x400114d2 +.set CYDEV_UCFG_B1_P2_U1_CFG19, 0x400114d3 +.set CYDEV_UCFG_B1_P2_U1_CFG20, 0x400114d4 +.set CYDEV_UCFG_B1_P2_U1_CFG21, 0x400114d5 +.set CYDEV_UCFG_B1_P2_U1_CFG22, 0x400114d6 +.set CYDEV_UCFG_B1_P2_U1_CFG23, 0x400114d7 +.set CYDEV_UCFG_B1_P2_U1_CFG24, 0x400114d8 +.set CYDEV_UCFG_B1_P2_U1_CFG25, 0x400114d9 +.set CYDEV_UCFG_B1_P2_U1_CFG26, 0x400114da +.set CYDEV_UCFG_B1_P2_U1_CFG27, 0x400114db +.set CYDEV_UCFG_B1_P2_U1_CFG28, 0x400114dc +.set CYDEV_UCFG_B1_P2_U1_CFG29, 0x400114dd +.set CYDEV_UCFG_B1_P2_U1_CFG30, 0x400114de +.set CYDEV_UCFG_B1_P2_U1_CFG31, 0x400114df +.set CYDEV_UCFG_B1_P2_U1_DCFG0, 0x400114e0 +.set CYDEV_UCFG_B1_P2_U1_DCFG1, 0x400114e2 +.set CYDEV_UCFG_B1_P2_U1_DCFG2, 0x400114e4 +.set CYDEV_UCFG_B1_P2_U1_DCFG3, 0x400114e6 +.set CYDEV_UCFG_B1_P2_U1_DCFG4, 0x400114e8 +.set CYDEV_UCFG_B1_P2_U1_DCFG5, 0x400114ea +.set CYDEV_UCFG_B1_P2_U1_DCFG6, 0x400114ec +.set CYDEV_UCFG_B1_P2_U1_DCFG7, 0x400114ee +.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 +.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P3_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT0, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT1, 0x40011604 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT2, 0x40011608 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT3, 0x4001160c +.set CYDEV_UCFG_B1_P3_U0_PLD_IT4, 0x40011610 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT5, 0x40011614 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT6, 0x40011618 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT7, 0x4001161c +.set CYDEV_UCFG_B1_P3_U0_PLD_IT8, 0x40011620 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT9, 0x40011624 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT10, 0x40011628 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT11, 0x4001162c +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT0, 0x40011630 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT1, 0x40011632 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT2, 0x40011634 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT3, 0x40011636 +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e +.set CYDEV_UCFG_B1_P3_U0_CFG0, 0x40011640 +.set CYDEV_UCFG_B1_P3_U0_CFG1, 0x40011641 +.set CYDEV_UCFG_B1_P3_U0_CFG2, 0x40011642 +.set CYDEV_UCFG_B1_P3_U0_CFG3, 0x40011643 +.set CYDEV_UCFG_B1_P3_U0_CFG4, 0x40011644 +.set CYDEV_UCFG_B1_P3_U0_CFG5, 0x40011645 +.set CYDEV_UCFG_B1_P3_U0_CFG6, 0x40011646 +.set CYDEV_UCFG_B1_P3_U0_CFG7, 0x40011647 +.set CYDEV_UCFG_B1_P3_U0_CFG8, 0x40011648 +.set CYDEV_UCFG_B1_P3_U0_CFG9, 0x40011649 +.set CYDEV_UCFG_B1_P3_U0_CFG10, 0x4001164a +.set CYDEV_UCFG_B1_P3_U0_CFG11, 0x4001164b +.set CYDEV_UCFG_B1_P3_U0_CFG12, 0x4001164c +.set CYDEV_UCFG_B1_P3_U0_CFG13, 0x4001164d +.set CYDEV_UCFG_B1_P3_U0_CFG14, 0x4001164e +.set CYDEV_UCFG_B1_P3_U0_CFG15, 0x4001164f +.set CYDEV_UCFG_B1_P3_U0_CFG16, 0x40011650 +.set CYDEV_UCFG_B1_P3_U0_CFG17, 0x40011651 +.set CYDEV_UCFG_B1_P3_U0_CFG18, 0x40011652 +.set CYDEV_UCFG_B1_P3_U0_CFG19, 0x40011653 +.set CYDEV_UCFG_B1_P3_U0_CFG20, 0x40011654 +.set CYDEV_UCFG_B1_P3_U0_CFG21, 0x40011655 +.set CYDEV_UCFG_B1_P3_U0_CFG22, 0x40011656 +.set CYDEV_UCFG_B1_P3_U0_CFG23, 0x40011657 +.set CYDEV_UCFG_B1_P3_U0_CFG24, 0x40011658 +.set CYDEV_UCFG_B1_P3_U0_CFG25, 0x40011659 +.set CYDEV_UCFG_B1_P3_U0_CFG26, 0x4001165a +.set CYDEV_UCFG_B1_P3_U0_CFG27, 0x4001165b +.set CYDEV_UCFG_B1_P3_U0_CFG28, 0x4001165c +.set CYDEV_UCFG_B1_P3_U0_CFG29, 0x4001165d +.set CYDEV_UCFG_B1_P3_U0_CFG30, 0x4001165e +.set CYDEV_UCFG_B1_P3_U0_CFG31, 0x4001165f +.set CYDEV_UCFG_B1_P3_U0_DCFG0, 0x40011660 +.set CYDEV_UCFG_B1_P3_U0_DCFG1, 0x40011662 +.set CYDEV_UCFG_B1_P3_U0_DCFG2, 0x40011664 +.set CYDEV_UCFG_B1_P3_U0_DCFG3, 0x40011666 +.set CYDEV_UCFG_B1_P3_U0_DCFG4, 0x40011668 +.set CYDEV_UCFG_B1_P3_U0_DCFG5, 0x4001166a +.set CYDEV_UCFG_B1_P3_U0_DCFG6, 0x4001166c +.set CYDEV_UCFG_B1_P3_U0_DCFG7, 0x4001166e +.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT0, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT1, 0x40011684 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT2, 0x40011688 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT3, 0x4001168c +.set CYDEV_UCFG_B1_P3_U1_PLD_IT4, 0x40011690 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT5, 0x40011694 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT6, 0x40011698 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT7, 0x4001169c +.set CYDEV_UCFG_B1_P3_U1_PLD_IT8, 0x400116a0 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT9, 0x400116a4 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT10, 0x400116a8 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT11, 0x400116ac +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT0, 0x400116b0 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT1, 0x400116b2 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT2, 0x400116b4 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT3, 0x400116b6 +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be +.set CYDEV_UCFG_B1_P3_U1_CFG0, 0x400116c0 +.set CYDEV_UCFG_B1_P3_U1_CFG1, 0x400116c1 +.set CYDEV_UCFG_B1_P3_U1_CFG2, 0x400116c2 +.set CYDEV_UCFG_B1_P3_U1_CFG3, 0x400116c3 +.set CYDEV_UCFG_B1_P3_U1_CFG4, 0x400116c4 +.set CYDEV_UCFG_B1_P3_U1_CFG5, 0x400116c5 +.set CYDEV_UCFG_B1_P3_U1_CFG6, 0x400116c6 +.set CYDEV_UCFG_B1_P3_U1_CFG7, 0x400116c7 +.set CYDEV_UCFG_B1_P3_U1_CFG8, 0x400116c8 +.set CYDEV_UCFG_B1_P3_U1_CFG9, 0x400116c9 +.set CYDEV_UCFG_B1_P3_U1_CFG10, 0x400116ca +.set CYDEV_UCFG_B1_P3_U1_CFG11, 0x400116cb +.set CYDEV_UCFG_B1_P3_U1_CFG12, 0x400116cc +.set CYDEV_UCFG_B1_P3_U1_CFG13, 0x400116cd +.set CYDEV_UCFG_B1_P3_U1_CFG14, 0x400116ce +.set CYDEV_UCFG_B1_P3_U1_CFG15, 0x400116cf +.set CYDEV_UCFG_B1_P3_U1_CFG16, 0x400116d0 +.set CYDEV_UCFG_B1_P3_U1_CFG17, 0x400116d1 +.set CYDEV_UCFG_B1_P3_U1_CFG18, 0x400116d2 +.set CYDEV_UCFG_B1_P3_U1_CFG19, 0x400116d3 +.set CYDEV_UCFG_B1_P3_U1_CFG20, 0x400116d4 +.set CYDEV_UCFG_B1_P3_U1_CFG21, 0x400116d5 +.set CYDEV_UCFG_B1_P3_U1_CFG22, 0x400116d6 +.set CYDEV_UCFG_B1_P3_U1_CFG23, 0x400116d7 +.set CYDEV_UCFG_B1_P3_U1_CFG24, 0x400116d8 +.set CYDEV_UCFG_B1_P3_U1_CFG25, 0x400116d9 +.set CYDEV_UCFG_B1_P3_U1_CFG26, 0x400116da +.set CYDEV_UCFG_B1_P3_U1_CFG27, 0x400116db +.set CYDEV_UCFG_B1_P3_U1_CFG28, 0x400116dc +.set CYDEV_UCFG_B1_P3_U1_CFG29, 0x400116dd +.set CYDEV_UCFG_B1_P3_U1_CFG30, 0x400116de +.set CYDEV_UCFG_B1_P3_U1_CFG31, 0x400116df +.set CYDEV_UCFG_B1_P3_U1_DCFG0, 0x400116e0 +.set CYDEV_UCFG_B1_P3_U1_DCFG1, 0x400116e2 +.set CYDEV_UCFG_B1_P3_U1_DCFG2, 0x400116e4 +.set CYDEV_UCFG_B1_P3_U1_DCFG3, 0x400116e6 +.set CYDEV_UCFG_B1_P3_U1_DCFG4, 0x400116e8 +.set CYDEV_UCFG_B1_P3_U1_DCFG5, 0x400116ea +.set CYDEV_UCFG_B1_P3_U1_DCFG6, 0x400116ec +.set CYDEV_UCFG_B1_P3_U1_DCFG7, 0x400116ee +.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 +.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P4_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT0, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT1, 0x40011804 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT2, 0x40011808 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT3, 0x4001180c +.set CYDEV_UCFG_B1_P4_U0_PLD_IT4, 0x40011810 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT5, 0x40011814 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT6, 0x40011818 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT7, 0x4001181c +.set CYDEV_UCFG_B1_P4_U0_PLD_IT8, 0x40011820 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT9, 0x40011824 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT10, 0x40011828 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT11, 0x4001182c +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT0, 0x40011830 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT1, 0x40011832 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT2, 0x40011834 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT3, 0x40011836 +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e +.set CYDEV_UCFG_B1_P4_U0_CFG0, 0x40011840 +.set CYDEV_UCFG_B1_P4_U0_CFG1, 0x40011841 +.set CYDEV_UCFG_B1_P4_U0_CFG2, 0x40011842 +.set CYDEV_UCFG_B1_P4_U0_CFG3, 0x40011843 +.set CYDEV_UCFG_B1_P4_U0_CFG4, 0x40011844 +.set CYDEV_UCFG_B1_P4_U0_CFG5, 0x40011845 +.set CYDEV_UCFG_B1_P4_U0_CFG6, 0x40011846 +.set CYDEV_UCFG_B1_P4_U0_CFG7, 0x40011847 +.set CYDEV_UCFG_B1_P4_U0_CFG8, 0x40011848 +.set CYDEV_UCFG_B1_P4_U0_CFG9, 0x40011849 +.set CYDEV_UCFG_B1_P4_U0_CFG10, 0x4001184a +.set CYDEV_UCFG_B1_P4_U0_CFG11, 0x4001184b +.set CYDEV_UCFG_B1_P4_U0_CFG12, 0x4001184c +.set CYDEV_UCFG_B1_P4_U0_CFG13, 0x4001184d +.set CYDEV_UCFG_B1_P4_U0_CFG14, 0x4001184e +.set CYDEV_UCFG_B1_P4_U0_CFG15, 0x4001184f +.set CYDEV_UCFG_B1_P4_U0_CFG16, 0x40011850 +.set CYDEV_UCFG_B1_P4_U0_CFG17, 0x40011851 +.set CYDEV_UCFG_B1_P4_U0_CFG18, 0x40011852 +.set CYDEV_UCFG_B1_P4_U0_CFG19, 0x40011853 +.set CYDEV_UCFG_B1_P4_U0_CFG20, 0x40011854 +.set CYDEV_UCFG_B1_P4_U0_CFG21, 0x40011855 +.set CYDEV_UCFG_B1_P4_U0_CFG22, 0x40011856 +.set CYDEV_UCFG_B1_P4_U0_CFG23, 0x40011857 +.set CYDEV_UCFG_B1_P4_U0_CFG24, 0x40011858 +.set CYDEV_UCFG_B1_P4_U0_CFG25, 0x40011859 +.set CYDEV_UCFG_B1_P4_U0_CFG26, 0x4001185a +.set CYDEV_UCFG_B1_P4_U0_CFG27, 0x4001185b +.set CYDEV_UCFG_B1_P4_U0_CFG28, 0x4001185c +.set CYDEV_UCFG_B1_P4_U0_CFG29, 0x4001185d +.set CYDEV_UCFG_B1_P4_U0_CFG30, 0x4001185e +.set CYDEV_UCFG_B1_P4_U0_CFG31, 0x4001185f +.set CYDEV_UCFG_B1_P4_U0_DCFG0, 0x40011860 +.set CYDEV_UCFG_B1_P4_U0_DCFG1, 0x40011862 +.set CYDEV_UCFG_B1_P4_U0_DCFG2, 0x40011864 +.set CYDEV_UCFG_B1_P4_U0_DCFG3, 0x40011866 +.set CYDEV_UCFG_B1_P4_U0_DCFG4, 0x40011868 +.set CYDEV_UCFG_B1_P4_U0_DCFG5, 0x4001186a +.set CYDEV_UCFG_B1_P4_U0_DCFG6, 0x4001186c +.set CYDEV_UCFG_B1_P4_U0_DCFG7, 0x4001186e +.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT0, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT1, 0x40011884 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT2, 0x40011888 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT3, 0x4001188c +.set CYDEV_UCFG_B1_P4_U1_PLD_IT4, 0x40011890 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT5, 0x40011894 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT6, 0x40011898 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT7, 0x4001189c +.set CYDEV_UCFG_B1_P4_U1_PLD_IT8, 0x400118a0 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT9, 0x400118a4 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT10, 0x400118a8 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT11, 0x400118ac +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT0, 0x400118b0 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT1, 0x400118b2 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT2, 0x400118b4 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT3, 0x400118b6 +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be +.set CYDEV_UCFG_B1_P4_U1_CFG0, 0x400118c0 +.set CYDEV_UCFG_B1_P4_U1_CFG1, 0x400118c1 +.set CYDEV_UCFG_B1_P4_U1_CFG2, 0x400118c2 +.set CYDEV_UCFG_B1_P4_U1_CFG3, 0x400118c3 +.set CYDEV_UCFG_B1_P4_U1_CFG4, 0x400118c4 +.set CYDEV_UCFG_B1_P4_U1_CFG5, 0x400118c5 +.set CYDEV_UCFG_B1_P4_U1_CFG6, 0x400118c6 +.set CYDEV_UCFG_B1_P4_U1_CFG7, 0x400118c7 +.set CYDEV_UCFG_B1_P4_U1_CFG8, 0x400118c8 +.set CYDEV_UCFG_B1_P4_U1_CFG9, 0x400118c9 +.set CYDEV_UCFG_B1_P4_U1_CFG10, 0x400118ca +.set CYDEV_UCFG_B1_P4_U1_CFG11, 0x400118cb +.set CYDEV_UCFG_B1_P4_U1_CFG12, 0x400118cc +.set CYDEV_UCFG_B1_P4_U1_CFG13, 0x400118cd +.set CYDEV_UCFG_B1_P4_U1_CFG14, 0x400118ce +.set CYDEV_UCFG_B1_P4_U1_CFG15, 0x400118cf +.set CYDEV_UCFG_B1_P4_U1_CFG16, 0x400118d0 +.set CYDEV_UCFG_B1_P4_U1_CFG17, 0x400118d1 +.set CYDEV_UCFG_B1_P4_U1_CFG18, 0x400118d2 +.set CYDEV_UCFG_B1_P4_U1_CFG19, 0x400118d3 +.set CYDEV_UCFG_B1_P4_U1_CFG20, 0x400118d4 +.set CYDEV_UCFG_B1_P4_U1_CFG21, 0x400118d5 +.set CYDEV_UCFG_B1_P4_U1_CFG22, 0x400118d6 +.set CYDEV_UCFG_B1_P4_U1_CFG23, 0x400118d7 +.set CYDEV_UCFG_B1_P4_U1_CFG24, 0x400118d8 +.set CYDEV_UCFG_B1_P4_U1_CFG25, 0x400118d9 +.set CYDEV_UCFG_B1_P4_U1_CFG26, 0x400118da +.set CYDEV_UCFG_B1_P4_U1_CFG27, 0x400118db +.set CYDEV_UCFG_B1_P4_U1_CFG28, 0x400118dc +.set CYDEV_UCFG_B1_P4_U1_CFG29, 0x400118dd +.set CYDEV_UCFG_B1_P4_U1_CFG30, 0x400118de +.set CYDEV_UCFG_B1_P4_U1_CFG31, 0x400118df +.set CYDEV_UCFG_B1_P4_U1_DCFG0, 0x400118e0 +.set CYDEV_UCFG_B1_P4_U1_DCFG1, 0x400118e2 +.set CYDEV_UCFG_B1_P4_U1_DCFG2, 0x400118e4 +.set CYDEV_UCFG_B1_P4_U1_DCFG3, 0x400118e6 +.set CYDEV_UCFG_B1_P4_U1_DCFG4, 0x400118e8 +.set CYDEV_UCFG_B1_P4_U1_DCFG5, 0x400118ea +.set CYDEV_UCFG_B1_P4_U1_DCFG6, 0x400118ec +.set CYDEV_UCFG_B1_P4_U1_DCFG7, 0x400118ee +.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 +.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT0, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT1, 0x40011a04 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT2, 0x40011a08 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT3, 0x40011a0c +.set CYDEV_UCFG_B1_P5_U0_PLD_IT4, 0x40011a10 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT5, 0x40011a14 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT6, 0x40011a18 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT7, 0x40011a1c +.set CYDEV_UCFG_B1_P5_U0_PLD_IT8, 0x40011a20 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT9, 0x40011a24 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT10, 0x40011a28 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT11, 0x40011a2c +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT0, 0x40011a30 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT1, 0x40011a32 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT2, 0x40011a34 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT3, 0x40011a36 +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e +.set CYDEV_UCFG_B1_P5_U0_CFG0, 0x40011a40 +.set CYDEV_UCFG_B1_P5_U0_CFG1, 0x40011a41 +.set CYDEV_UCFG_B1_P5_U0_CFG2, 0x40011a42 +.set CYDEV_UCFG_B1_P5_U0_CFG3, 0x40011a43 +.set CYDEV_UCFG_B1_P5_U0_CFG4, 0x40011a44 +.set CYDEV_UCFG_B1_P5_U0_CFG5, 0x40011a45 +.set CYDEV_UCFG_B1_P5_U0_CFG6, 0x40011a46 +.set CYDEV_UCFG_B1_P5_U0_CFG7, 0x40011a47 +.set CYDEV_UCFG_B1_P5_U0_CFG8, 0x40011a48 +.set CYDEV_UCFG_B1_P5_U0_CFG9, 0x40011a49 +.set CYDEV_UCFG_B1_P5_U0_CFG10, 0x40011a4a +.set CYDEV_UCFG_B1_P5_U0_CFG11, 0x40011a4b +.set CYDEV_UCFG_B1_P5_U0_CFG12, 0x40011a4c +.set CYDEV_UCFG_B1_P5_U0_CFG13, 0x40011a4d +.set CYDEV_UCFG_B1_P5_U0_CFG14, 0x40011a4e +.set CYDEV_UCFG_B1_P5_U0_CFG15, 0x40011a4f +.set CYDEV_UCFG_B1_P5_U0_CFG16, 0x40011a50 +.set CYDEV_UCFG_B1_P5_U0_CFG17, 0x40011a51 +.set CYDEV_UCFG_B1_P5_U0_CFG18, 0x40011a52 +.set CYDEV_UCFG_B1_P5_U0_CFG19, 0x40011a53 +.set CYDEV_UCFG_B1_P5_U0_CFG20, 0x40011a54 +.set CYDEV_UCFG_B1_P5_U0_CFG21, 0x40011a55 +.set CYDEV_UCFG_B1_P5_U0_CFG22, 0x40011a56 +.set CYDEV_UCFG_B1_P5_U0_CFG23, 0x40011a57 +.set CYDEV_UCFG_B1_P5_U0_CFG24, 0x40011a58 +.set CYDEV_UCFG_B1_P5_U0_CFG25, 0x40011a59 +.set CYDEV_UCFG_B1_P5_U0_CFG26, 0x40011a5a +.set CYDEV_UCFG_B1_P5_U0_CFG27, 0x40011a5b +.set CYDEV_UCFG_B1_P5_U0_CFG28, 0x40011a5c +.set CYDEV_UCFG_B1_P5_U0_CFG29, 0x40011a5d +.set CYDEV_UCFG_B1_P5_U0_CFG30, 0x40011a5e +.set CYDEV_UCFG_B1_P5_U0_CFG31, 0x40011a5f +.set CYDEV_UCFG_B1_P5_U0_DCFG0, 0x40011a60 +.set CYDEV_UCFG_B1_P5_U0_DCFG1, 0x40011a62 +.set CYDEV_UCFG_B1_P5_U0_DCFG2, 0x40011a64 +.set CYDEV_UCFG_B1_P5_U0_DCFG3, 0x40011a66 +.set CYDEV_UCFG_B1_P5_U0_DCFG4, 0x40011a68 +.set CYDEV_UCFG_B1_P5_U0_DCFG5, 0x40011a6a +.set CYDEV_UCFG_B1_P5_U0_DCFG6, 0x40011a6c +.set CYDEV_UCFG_B1_P5_U0_DCFG7, 0x40011a6e +.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT0, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT1, 0x40011a84 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT2, 0x40011a88 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT3, 0x40011a8c +.set CYDEV_UCFG_B1_P5_U1_PLD_IT4, 0x40011a90 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT5, 0x40011a94 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT6, 0x40011a98 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT7, 0x40011a9c +.set CYDEV_UCFG_B1_P5_U1_PLD_IT8, 0x40011aa0 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT9, 0x40011aa4 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT10, 0x40011aa8 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT11, 0x40011aac +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT0, 0x40011ab0 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT1, 0x40011ab2 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT2, 0x40011ab4 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT3, 0x40011ab6 +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe +.set CYDEV_UCFG_B1_P5_U1_CFG0, 0x40011ac0 +.set CYDEV_UCFG_B1_P5_U1_CFG1, 0x40011ac1 +.set CYDEV_UCFG_B1_P5_U1_CFG2, 0x40011ac2 +.set CYDEV_UCFG_B1_P5_U1_CFG3, 0x40011ac3 +.set CYDEV_UCFG_B1_P5_U1_CFG4, 0x40011ac4 +.set CYDEV_UCFG_B1_P5_U1_CFG5, 0x40011ac5 +.set CYDEV_UCFG_B1_P5_U1_CFG6, 0x40011ac6 +.set CYDEV_UCFG_B1_P5_U1_CFG7, 0x40011ac7 +.set CYDEV_UCFG_B1_P5_U1_CFG8, 0x40011ac8 +.set CYDEV_UCFG_B1_P5_U1_CFG9, 0x40011ac9 +.set CYDEV_UCFG_B1_P5_U1_CFG10, 0x40011aca +.set CYDEV_UCFG_B1_P5_U1_CFG11, 0x40011acb +.set CYDEV_UCFG_B1_P5_U1_CFG12, 0x40011acc +.set CYDEV_UCFG_B1_P5_U1_CFG13, 0x40011acd +.set CYDEV_UCFG_B1_P5_U1_CFG14, 0x40011ace +.set CYDEV_UCFG_B1_P5_U1_CFG15, 0x40011acf +.set CYDEV_UCFG_B1_P5_U1_CFG16, 0x40011ad0 +.set CYDEV_UCFG_B1_P5_U1_CFG17, 0x40011ad1 +.set CYDEV_UCFG_B1_P5_U1_CFG18, 0x40011ad2 +.set CYDEV_UCFG_B1_P5_U1_CFG19, 0x40011ad3 +.set CYDEV_UCFG_B1_P5_U1_CFG20, 0x40011ad4 +.set CYDEV_UCFG_B1_P5_U1_CFG21, 0x40011ad5 +.set CYDEV_UCFG_B1_P5_U1_CFG22, 0x40011ad6 +.set CYDEV_UCFG_B1_P5_U1_CFG23, 0x40011ad7 +.set CYDEV_UCFG_B1_P5_U1_CFG24, 0x40011ad8 +.set CYDEV_UCFG_B1_P5_U1_CFG25, 0x40011ad9 +.set CYDEV_UCFG_B1_P5_U1_CFG26, 0x40011ada +.set CYDEV_UCFG_B1_P5_U1_CFG27, 0x40011adb +.set CYDEV_UCFG_B1_P5_U1_CFG28, 0x40011adc +.set CYDEV_UCFG_B1_P5_U1_CFG29, 0x40011add +.set CYDEV_UCFG_B1_P5_U1_CFG30, 0x40011ade +.set CYDEV_UCFG_B1_P5_U1_CFG31, 0x40011adf +.set CYDEV_UCFG_B1_P5_U1_DCFG0, 0x40011ae0 +.set CYDEV_UCFG_B1_P5_U1_DCFG1, 0x40011ae2 +.set CYDEV_UCFG_B1_P5_U1_DCFG2, 0x40011ae4 +.set CYDEV_UCFG_B1_P5_U1_DCFG3, 0x40011ae6 +.set CYDEV_UCFG_B1_P5_U1_DCFG4, 0x40011ae8 +.set CYDEV_UCFG_B1_P5_U1_DCFG5, 0x40011aea +.set CYDEV_UCFG_B1_P5_U1_DCFG6, 0x40011aec +.set CYDEV_UCFG_B1_P5_U1_DCFG7, 0x40011aee +.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 +.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI0_BASE, 0x40014000 +.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI1_BASE, 0x40014100 +.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI2_BASE, 0x40014200 +.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI3_BASE, 0x40014300 +.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI4_BASE, 0x40014400 +.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI5_BASE, 0x40014500 +.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI6_BASE, 0x40014600 +.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI7_BASE, 0x40014700 +.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI8_BASE, 0x40014800 +.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI9_BASE, 0x40014900 +.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI12_BASE, 0x40014c00 +.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI13_BASE, 0x40014d00 +.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef +.set CYDEV_UCFG_BCTL0_BASE, 0x40015000 +.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 +.set CYDEV_UCFG_BCTL0_MDCLK_EN, 0x40015000 +.set CYDEV_UCFG_BCTL0_MBCLK_EN, 0x40015001 +.set CYDEV_UCFG_BCTL0_WAIT_CFG, 0x40015002 +.set CYDEV_UCFG_BCTL0_BANK_CTL, 0x40015003 +.set CYDEV_UCFG_BCTL0_UDB_TEST_3, 0x40015007 +.set CYDEV_UCFG_BCTL0_DCLK_EN0, 0x40015008 +.set CYDEV_UCFG_BCTL0_BCLK_EN0, 0x40015009 +.set CYDEV_UCFG_BCTL0_DCLK_EN1, 0x4001500a +.set CYDEV_UCFG_BCTL0_BCLK_EN1, 0x4001500b +.set CYDEV_UCFG_BCTL0_DCLK_EN2, 0x4001500c +.set CYDEV_UCFG_BCTL0_BCLK_EN2, 0x4001500d +.set CYDEV_UCFG_BCTL0_DCLK_EN3, 0x4001500e +.set CYDEV_UCFG_BCTL0_BCLK_EN3, 0x4001500f +.set CYDEV_UCFG_BCTL1_BASE, 0x40015010 +.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 +.set CYDEV_UCFG_BCTL1_MDCLK_EN, 0x40015010 +.set CYDEV_UCFG_BCTL1_MBCLK_EN, 0x40015011 +.set CYDEV_UCFG_BCTL1_WAIT_CFG, 0x40015012 +.set CYDEV_UCFG_BCTL1_BANK_CTL, 0x40015013 +.set CYDEV_UCFG_BCTL1_UDB_TEST_3, 0x40015017 +.set CYDEV_UCFG_BCTL1_DCLK_EN0, 0x40015018 +.set CYDEV_UCFG_BCTL1_BCLK_EN0, 0x40015019 +.set CYDEV_UCFG_BCTL1_DCLK_EN1, 0x4001501a +.set CYDEV_UCFG_BCTL1_BCLK_EN1, 0x4001501b +.set CYDEV_UCFG_BCTL1_DCLK_EN2, 0x4001501c +.set CYDEV_UCFG_BCTL1_BCLK_EN2, 0x4001501d +.set CYDEV_UCFG_BCTL1_DCLK_EN3, 0x4001501e +.set CYDEV_UCFG_BCTL1_BCLK_EN3, 0x4001501f +.set CYDEV_IDMUX_BASE, 0x40015100 +.set CYDEV_IDMUX_SIZE, 0x00000016 +.set CYDEV_IDMUX_IRQ_CTL0, 0x40015100 +.set CYDEV_IDMUX_IRQ_CTL1, 0x40015101 +.set CYDEV_IDMUX_IRQ_CTL2, 0x40015102 +.set CYDEV_IDMUX_IRQ_CTL3, 0x40015103 +.set CYDEV_IDMUX_IRQ_CTL4, 0x40015104 +.set CYDEV_IDMUX_IRQ_CTL5, 0x40015105 +.set CYDEV_IDMUX_IRQ_CTL6, 0x40015106 +.set CYDEV_IDMUX_IRQ_CTL7, 0x40015107 +.set CYDEV_IDMUX_DRQ_CTL0, 0x40015110 +.set CYDEV_IDMUX_DRQ_CTL1, 0x40015111 +.set CYDEV_IDMUX_DRQ_CTL2, 0x40015112 +.set CYDEV_IDMUX_DRQ_CTL3, 0x40015113 +.set CYDEV_IDMUX_DRQ_CTL4, 0x40015114 +.set CYDEV_IDMUX_DRQ_CTL5, 0x40015115 +.set CYDEV_CACHERAM_BASE, 0x40030000 +.set CYDEV_CACHERAM_SIZE, 0x00000400 +.set CYDEV_CACHERAM_DATA_MBASE, 0x40030000 +.set CYDEV_CACHERAM_DATA_MSIZE, 0x00000400 +.set CYDEV_SFR_BASE, 0x40050100 +.set CYDEV_SFR_SIZE, 0x000000fb +.set CYDEV_SFR_GPIO0, 0x40050180 +.set CYDEV_SFR_GPIRD0, 0x40050189 +.set CYDEV_SFR_GPIO0_SEL, 0x4005018a +.set CYDEV_SFR_GPIO1, 0x40050190 +.set CYDEV_SFR_GPIRD1, 0x40050191 +.set CYDEV_SFR_GPIO2, 0x40050198 +.set CYDEV_SFR_GPIRD2, 0x40050199 +.set CYDEV_SFR_GPIO2_SEL, 0x4005019a +.set CYDEV_SFR_GPIO1_SEL, 0x400501a2 +.set CYDEV_SFR_GPIO3, 0x400501b0 +.set CYDEV_SFR_GPIRD3, 0x400501b1 +.set CYDEV_SFR_GPIO3_SEL, 0x400501b2 +.set CYDEV_SFR_GPIO4, 0x400501c0 +.set CYDEV_SFR_GPIRD4, 0x400501c1 +.set CYDEV_SFR_GPIO4_SEL, 0x400501c2 +.set CYDEV_SFR_GPIO5, 0x400501c8 +.set CYDEV_SFR_GPIRD5, 0x400501c9 +.set CYDEV_SFR_GPIO5_SEL, 0x400501ca +.set CYDEV_SFR_GPIO6, 0x400501d8 +.set CYDEV_SFR_GPIRD6, 0x400501d9 +.set CYDEV_SFR_GPIO6_SEL, 0x400501da +.set CYDEV_SFR_GPIO12, 0x400501e8 +.set CYDEV_SFR_GPIRD12, 0x400501e9 +.set CYDEV_SFR_GPIO12_SEL, 0x400501f2 +.set CYDEV_SFR_GPIO15, 0x400501f8 +.set CYDEV_SFR_GPIRD15, 0x400501f9 +.set CYDEV_SFR_GPIO15_SEL, 0x400501fa +.set CYDEV_P3BA_BASE, 0x40050300 +.set CYDEV_P3BA_SIZE, 0x0000002b +.set CYDEV_P3BA_Y_START, 0x40050300 +.set CYDEV_P3BA_YROLL, 0x40050301 +.set CYDEV_P3BA_YCFG, 0x40050302 +.set CYDEV_P3BA_X_START1, 0x40050303 +.set CYDEV_P3BA_X_START2, 0x40050304 +.set CYDEV_P3BA_XROLL1, 0x40050305 +.set CYDEV_P3BA_XROLL2, 0x40050306 +.set CYDEV_P3BA_XINC, 0x40050307 +.set CYDEV_P3BA_XCFG, 0x40050308 +.set CYDEV_P3BA_OFFSETADDR1, 0x40050309 +.set CYDEV_P3BA_OFFSETADDR2, 0x4005030a +.set CYDEV_P3BA_OFFSETADDR3, 0x4005030b +.set CYDEV_P3BA_ABSADDR1, 0x4005030c +.set CYDEV_P3BA_ABSADDR2, 0x4005030d +.set CYDEV_P3BA_ABSADDR3, 0x4005030e +.set CYDEV_P3BA_ABSADDR4, 0x4005030f +.set CYDEV_P3BA_DATCFG1, 0x40050310 +.set CYDEV_P3BA_DATCFG2, 0x40050311 +.set CYDEV_P3BA_CMP_RSLT1, 0x40050314 +.set CYDEV_P3BA_CMP_RSLT2, 0x40050315 +.set CYDEV_P3BA_CMP_RSLT3, 0x40050316 +.set CYDEV_P3BA_CMP_RSLT4, 0x40050317 +.set CYDEV_P3BA_DATA_REG1, 0x40050318 +.set CYDEV_P3BA_DATA_REG2, 0x40050319 +.set CYDEV_P3BA_DATA_REG3, 0x4005031a +.set CYDEV_P3BA_DATA_REG4, 0x4005031b +.set CYDEV_P3BA_EXP_DATA1, 0x4005031c +.set CYDEV_P3BA_EXP_DATA2, 0x4005031d +.set CYDEV_P3BA_EXP_DATA3, 0x4005031e +.set CYDEV_P3BA_EXP_DATA4, 0x4005031f +.set CYDEV_P3BA_MSTR_HRDATA1, 0x40050320 +.set CYDEV_P3BA_MSTR_HRDATA2, 0x40050321 +.set CYDEV_P3BA_MSTR_HRDATA3, 0x40050322 +.set CYDEV_P3BA_MSTR_HRDATA4, 0x40050323 +.set CYDEV_P3BA_BIST_EN, 0x40050324 +.set CYDEV_P3BA_PHUB_MASTER_SSR, 0x40050325 +.set CYDEV_P3BA_SEQCFG1, 0x40050326 +.set CYDEV_P3BA_SEQCFG2, 0x40050327 +.set CYDEV_P3BA_Y_CURR, 0x40050328 +.set CYDEV_P3BA_X_CURR1, 0x40050329 +.set CYDEV_P3BA_X_CURR2, 0x4005032a +.set CYDEV_PANTHER_BASE, 0x40080000 +.set CYDEV_PANTHER_SIZE, 0x00000020 +.set CYDEV_PANTHER_STCALIB_CFG, 0x40080000 +.set CYDEV_PANTHER_WAITPIPE, 0x40080004 +.set CYDEV_PANTHER_TRACE_CFG, 0x40080008 +.set CYDEV_PANTHER_DBG_CFG, 0x4008000c +.set CYDEV_PANTHER_CM3_LCKRST_STAT, 0x40080018 +.set CYDEV_PANTHER_DEVICE_ID, 0x4008001c +.set CYDEV_FLSECC_BASE, 0x48000000 +.set CYDEV_FLSECC_SIZE, 0x00008000 +.set CYDEV_FLSECC_DATA_MBASE, 0x48000000 +.set CYDEV_FLSECC_DATA_MSIZE, 0x00008000 +.set CYDEV_FLSHID_BASE, 0x49000000 +.set CYDEV_FLSHID_SIZE, 0x00000200 +.set CYDEV_FLSHID_RSVD_MBASE, 0x49000000 +.set CYDEV_FLSHID_RSVD_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_MDATA_MBASE, 0x49000080 +.set CYDEV_FLSHID_CUST_MDATA_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 +.set CYDEV_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_X_LOC, 0x49000101 +.set CYDEV_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 +.set CYDEV_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 +.set CYDEV_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 +.set CYDEV_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 +.set CYDEV_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 +.set CYDEV_FLSHID_CUST_TABLES_MINOR, 0x49000107 +.set CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 +.set CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 +.set CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a +.set CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b +.set CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c +.set CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d +.set CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e +.set CYDEV_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f +.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 +.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 +.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 +.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 +.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 +.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 +.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 +.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a +.set CYDEV_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b +.set CYDEV_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c +.set CYDEV_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d +.set CYDEV_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e +.set CYDEV_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f +.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 +.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 +.set CYDEV_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 +.set CYDEV_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac +.set CYDEV_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae +.set CYDEV_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 +.set CYDEV_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 +.set CYDEV_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 +.set CYDEV_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 +.set CYDEV_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 +.set CYDEV_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba +.set CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce +.set CYDEV_EXTMEM_BASE, 0x60000000 +.set CYDEV_EXTMEM_SIZE, 0x00800000 +.set CYDEV_EXTMEM_DATA_MBASE, 0x60000000 +.set CYDEV_EXTMEM_DATA_MSIZE, 0x00800000 +.set CYDEV_ITM_BASE, 0xe0000000 +.set CYDEV_ITM_SIZE, 0x00001000 +.set CYDEV_ITM_TRACE_EN, 0xe0000e00 +.set CYDEV_ITM_TRACE_PRIVILEGE, 0xe0000e40 +.set CYDEV_ITM_TRACE_CTRL, 0xe0000e80 +.set CYDEV_ITM_LOCK_ACCESS, 0xe0000fb0 +.set CYDEV_ITM_LOCK_STATUS, 0xe0000fb4 +.set CYDEV_ITM_PID4, 0xe0000fd0 +.set CYDEV_ITM_PID5, 0xe0000fd4 +.set CYDEV_ITM_PID6, 0xe0000fd8 +.set CYDEV_ITM_PID7, 0xe0000fdc +.set CYDEV_ITM_PID0, 0xe0000fe0 +.set CYDEV_ITM_PID1, 0xe0000fe4 +.set CYDEV_ITM_PID2, 0xe0000fe8 +.set CYDEV_ITM_PID3, 0xe0000fec +.set CYDEV_ITM_CID0, 0xe0000ff0 +.set CYDEV_ITM_CID1, 0xe0000ff4 +.set CYDEV_ITM_CID2, 0xe0000ff8 +.set CYDEV_ITM_CID3, 0xe0000ffc +.set CYDEV_DWT_BASE, 0xe0001000 +.set CYDEV_DWT_SIZE, 0x0000005c +.set CYDEV_DWT_CTRL, 0xe0001000 +.set CYDEV_DWT_CYCLE_COUNT, 0xe0001004 +.set CYDEV_DWT_CPI_COUNT, 0xe0001008 +.set CYDEV_DWT_EXC_OVHD_COUNT, 0xe000100c +.set CYDEV_DWT_SLEEP_COUNT, 0xe0001010 +.set CYDEV_DWT_LSU_COUNT, 0xe0001014 +.set CYDEV_DWT_FOLD_COUNT, 0xe0001018 +.set CYDEV_DWT_PC_SAMPLE, 0xe000101c +.set CYDEV_DWT_COMP_0, 0xe0001020 +.set CYDEV_DWT_MASK_0, 0xe0001024 +.set CYDEV_DWT_FUNCTION_0, 0xe0001028 +.set CYDEV_DWT_COMP_1, 0xe0001030 +.set CYDEV_DWT_MASK_1, 0xe0001034 +.set CYDEV_DWT_FUNCTION_1, 0xe0001038 +.set CYDEV_DWT_COMP_2, 0xe0001040 +.set CYDEV_DWT_MASK_2, 0xe0001044 +.set CYDEV_DWT_FUNCTION_2, 0xe0001048 +.set CYDEV_DWT_COMP_3, 0xe0001050 +.set CYDEV_DWT_MASK_3, 0xe0001054 +.set CYDEV_DWT_FUNCTION_3, 0xe0001058 +.set CYDEV_FPB_BASE, 0xe0002000 +.set CYDEV_FPB_SIZE, 0x00001000 +.set CYDEV_FPB_CTRL, 0xe0002000 +.set CYDEV_FPB_REMAP, 0xe0002004 +.set CYDEV_FPB_FP_COMP_0, 0xe0002008 +.set CYDEV_FPB_FP_COMP_1, 0xe000200c +.set CYDEV_FPB_FP_COMP_2, 0xe0002010 +.set CYDEV_FPB_FP_COMP_3, 0xe0002014 +.set CYDEV_FPB_FP_COMP_4, 0xe0002018 +.set CYDEV_FPB_FP_COMP_5, 0xe000201c +.set CYDEV_FPB_FP_COMP_6, 0xe0002020 +.set CYDEV_FPB_FP_COMP_7, 0xe0002024 +.set CYDEV_FPB_PID4, 0xe0002fd0 +.set CYDEV_FPB_PID5, 0xe0002fd4 +.set CYDEV_FPB_PID6, 0xe0002fd8 +.set CYDEV_FPB_PID7, 0xe0002fdc +.set CYDEV_FPB_PID0, 0xe0002fe0 +.set CYDEV_FPB_PID1, 0xe0002fe4 +.set CYDEV_FPB_PID2, 0xe0002fe8 +.set CYDEV_FPB_PID3, 0xe0002fec +.set CYDEV_FPB_CID0, 0xe0002ff0 +.set CYDEV_FPB_CID1, 0xe0002ff4 +.set CYDEV_FPB_CID2, 0xe0002ff8 +.set CYDEV_FPB_CID3, 0xe0002ffc +.set CYDEV_NVIC_BASE, 0xe000e000 +.set CYDEV_NVIC_SIZE, 0x00000d3c +.set CYDEV_NVIC_INT_CTL_TYPE, 0xe000e004 +.set CYDEV_NVIC_SYSTICK_CTL, 0xe000e010 +.set CYDEV_NVIC_SYSTICK_RELOAD, 0xe000e014 +.set CYDEV_NVIC_SYSTICK_CURRENT, 0xe000e018 +.set CYDEV_NVIC_SYSTICK_CAL, 0xe000e01c +.set CYDEV_NVIC_SETENA0, 0xe000e100 +.set CYDEV_NVIC_CLRENA0, 0xe000e180 +.set CYDEV_NVIC_SETPEND0, 0xe000e200 +.set CYDEV_NVIC_CLRPEND0, 0xe000e280 +.set CYDEV_NVIC_ACTIVE0, 0xe000e300 +.set CYDEV_NVIC_PRI_0, 0xe000e400 +.set CYDEV_NVIC_PRI_1, 0xe000e401 +.set CYDEV_NVIC_PRI_2, 0xe000e402 +.set CYDEV_NVIC_PRI_3, 0xe000e403 +.set CYDEV_NVIC_PRI_4, 0xe000e404 +.set CYDEV_NVIC_PRI_5, 0xe000e405 +.set CYDEV_NVIC_PRI_6, 0xe000e406 +.set CYDEV_NVIC_PRI_7, 0xe000e407 +.set CYDEV_NVIC_PRI_8, 0xe000e408 +.set CYDEV_NVIC_PRI_9, 0xe000e409 +.set CYDEV_NVIC_PRI_10, 0xe000e40a +.set CYDEV_NVIC_PRI_11, 0xe000e40b +.set CYDEV_NVIC_PRI_12, 0xe000e40c +.set CYDEV_NVIC_PRI_13, 0xe000e40d +.set CYDEV_NVIC_PRI_14, 0xe000e40e +.set CYDEV_NVIC_PRI_15, 0xe000e40f +.set CYDEV_NVIC_PRI_16, 0xe000e410 +.set CYDEV_NVIC_PRI_17, 0xe000e411 +.set CYDEV_NVIC_PRI_18, 0xe000e412 +.set CYDEV_NVIC_PRI_19, 0xe000e413 +.set CYDEV_NVIC_PRI_20, 0xe000e414 +.set CYDEV_NVIC_PRI_21, 0xe000e415 +.set CYDEV_NVIC_PRI_22, 0xe000e416 +.set CYDEV_NVIC_PRI_23, 0xe000e417 +.set CYDEV_NVIC_PRI_24, 0xe000e418 +.set CYDEV_NVIC_PRI_25, 0xe000e419 +.set CYDEV_NVIC_PRI_26, 0xe000e41a +.set CYDEV_NVIC_PRI_27, 0xe000e41b +.set CYDEV_NVIC_PRI_28, 0xe000e41c +.set CYDEV_NVIC_PRI_29, 0xe000e41d +.set CYDEV_NVIC_PRI_30, 0xe000e41e +.set CYDEV_NVIC_PRI_31, 0xe000e41f +.set CYDEV_NVIC_CPUID_BASE, 0xe000ed00 +.set CYDEV_NVIC_INTR_CTRL_STATE, 0xe000ed04 +.set CYDEV_NVIC_VECT_OFFSET, 0xe000ed08 +.set CYDEV_NVIC_APPLN_INTR, 0xe000ed0c +.set CYDEV_NVIC_SYSTEM_CONTROL, 0xe000ed10 +.set CYDEV_NVIC_CFG_CONTROL, 0xe000ed14 +.set CYDEV_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 +.set CYDEV_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c +.set CYDEV_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 +.set CYDEV_NVIC_SYS_HANDLER_CSR, 0xe000ed24 +.set CYDEV_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 +.set CYDEV_NVIC_BUS_FAULT_STATUS, 0xe000ed29 +.set CYDEV_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a +.set CYDEV_NVIC_HARD_FAULT_STATUS, 0xe000ed2c +.set CYDEV_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 +.set CYDEV_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 +.set CYDEV_NVIC_BUS_FAULT_ADD, 0xe000ed38 +.set CYDEV_CORE_DBG_BASE, 0xe000edf0 +.set CYDEV_CORE_DBG_SIZE, 0x00000010 +.set CYDEV_CORE_DBG_DBG_HLT_CS, 0xe000edf0 +.set CYDEV_CORE_DBG_DBG_REG_SEL, 0xe000edf4 +.set CYDEV_CORE_DBG_DBG_REG_DATA, 0xe000edf8 +.set CYDEV_CORE_DBG_EXC_MON_CTL, 0xe000edfc +.set CYDEV_TPIU_BASE, 0xe0040000 +.set CYDEV_TPIU_SIZE, 0x00001000 +.set CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 +.set CYDEV_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 +.set CYDEV_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 +.set CYDEV_TPIU_PROTOCOL, 0xe00400f0 +.set CYDEV_TPIU_FORM_FLUSH_STAT, 0xe0040300 +.set CYDEV_TPIU_FORM_FLUSH_CTRL, 0xe0040304 +.set CYDEV_TPIU_TRIGGER, 0xe0040ee8 +.set CYDEV_TPIU_ITETMDATA, 0xe0040eec +.set CYDEV_TPIU_ITATBCTR2, 0xe0040ef0 +.set CYDEV_TPIU_ITATBCTR0, 0xe0040ef8 +.set CYDEV_TPIU_ITITMDATA, 0xe0040efc +.set CYDEV_TPIU_ITCTRL, 0xe0040f00 +.set CYDEV_TPIU_DEVID, 0xe0040fc8 +.set CYDEV_TPIU_DEVTYPE, 0xe0040fcc +.set CYDEV_TPIU_PID4, 0xe0040fd0 +.set CYDEV_TPIU_PID5, 0xe0040fd4 +.set CYDEV_TPIU_PID6, 0xe0040fd8 +.set CYDEV_TPIU_PID7, 0xe0040fdc +.set CYDEV_TPIU_PID0, 0xe0040fe0 +.set CYDEV_TPIU_PID1, 0xe0040fe4 +.set CYDEV_TPIU_PID2, 0xe0040fe8 +.set CYDEV_TPIU_PID3, 0xe0040fec +.set CYDEV_TPIU_CID0, 0xe0040ff0 +.set CYDEV_TPIU_CID1, 0xe0040ff4 +.set CYDEV_TPIU_CID2, 0xe0040ff8 +.set CYDEV_TPIU_CID3, 0xe0040ffc +.set CYDEV_ETM_BASE, 0xe0041000 +.set CYDEV_ETM_SIZE, 0x00001000 +.set CYDEV_ETM_CTL, 0xe0041000 +.set CYDEV_ETM_CFG_CODE, 0xe0041004 +.set CYDEV_ETM_TRIG_EVENT, 0xe0041008 +.set CYDEV_ETM_STATUS, 0xe0041010 +.set CYDEV_ETM_SYS_CFG, 0xe0041014 +.set CYDEV_ETM_TRACE_ENB_EVENT, 0xe0041020 +.set CYDEV_ETM_TRACE_EN_CTRL1, 0xe0041024 +.set CYDEV_ETM_FIFOFULL_LEVEL, 0xe004102c +.set CYDEV_ETM_SYNC_FREQ, 0xe00411e0 +.set CYDEV_ETM_ETM_ID, 0xe00411e4 +.set CYDEV_ETM_CFG_CODE_EXT, 0xe00411e8 +.set CYDEV_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 +.set CYDEV_ETM_CS_TRACE_ID, 0xe0041200 +.set CYDEV_ETM_OS_LOCK_ACCESS, 0xe0041300 +.set CYDEV_ETM_OS_LOCK_STATUS, 0xe0041304 +.set CYDEV_ETM_PDSR, 0xe0041314 +.set CYDEV_ETM_ITMISCIN, 0xe0041ee0 +.set CYDEV_ETM_ITTRIGOUT, 0xe0041ee8 +.set CYDEV_ETM_ITATBCTR2, 0xe0041ef0 +.set CYDEV_ETM_ITATBCTR0, 0xe0041ef8 +.set CYDEV_ETM_INT_MODE_CTRL, 0xe0041f00 +.set CYDEV_ETM_CLM_TAG_SET, 0xe0041fa0 +.set CYDEV_ETM_CLM_TAG_CLR, 0xe0041fa4 +.set CYDEV_ETM_LOCK_ACCESS, 0xe0041fb0 +.set CYDEV_ETM_LOCK_STATUS, 0xe0041fb4 +.set CYDEV_ETM_AUTH_STATUS, 0xe0041fb8 +.set CYDEV_ETM_DEV_TYPE, 0xe0041fcc +.set CYDEV_ETM_PID4, 0xe0041fd0 +.set CYDEV_ETM_PID5, 0xe0041fd4 +.set CYDEV_ETM_PID6, 0xe0041fd8 +.set CYDEV_ETM_PID7, 0xe0041fdc +.set CYDEV_ETM_PID0, 0xe0041fe0 +.set CYDEV_ETM_PID1, 0xe0041fe4 +.set CYDEV_ETM_PID2, 0xe0041fe8 +.set CYDEV_ETM_PID3, 0xe0041fec +.set CYDEV_ETM_CID0, 0xe0041ff0 +.set CYDEV_ETM_CID1, 0xe0041ff4 +.set CYDEV_ETM_CID2, 0xe0041ff8 +.set CYDEV_ETM_CID3, 0xe0041ffc +.set CYDEV_ROM_TABLE_BASE, 0xe00ff000 +.set CYDEV_ROM_TABLE_SIZE, 0x00001000 +.set CYDEV_ROM_TABLE_NVIC, 0xe00ff000 +.set CYDEV_ROM_TABLE_DWT, 0xe00ff004 +.set CYDEV_ROM_TABLE_FPB, 0xe00ff008 +.set CYDEV_ROM_TABLE_ITM, 0xe00ff00c +.set CYDEV_ROM_TABLE_TPIU, 0xe00ff010 +.set CYDEV_ROM_TABLE_ETM, 0xe00ff014 +.set CYDEV_ROM_TABLE_END, 0xe00ff018 +.set CYDEV_ROM_TABLE_MEMTYPE, 0xe00fffcc +.set CYDEV_ROM_TABLE_PID4, 0xe00fffd0 +.set CYDEV_ROM_TABLE_PID5, 0xe00fffd4 +.set CYDEV_ROM_TABLE_PID6, 0xe00fffd8 +.set CYDEV_ROM_TABLE_PID7, 0xe00fffdc +.set CYDEV_ROM_TABLE_PID0, 0xe00fffe0 +.set CYDEV_ROM_TABLE_PID1, 0xe00fffe4 +.set CYDEV_ROM_TABLE_PID2, 0xe00fffe8 +.set CYDEV_ROM_TABLE_PID3, 0xe00fffec +.set CYDEV_ROM_TABLE_CID0, 0xe00ffff0 +.set CYDEV_ROM_TABLE_CID1, 0xe00ffff4 +.set CYDEV_ROM_TABLE_CID2, 0xe00ffff8 +.set CYDEV_ROM_TABLE_CID3, 0xe00ffffc +.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE +.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE +.set CYDEV_FLS_SECTOR_SIZE, 0x00010000 +.set CYDEV_FLS_ROW_SIZE, 0x00000100 +.set CYDEV_ECC_SECTOR_SIZE, 0x00002000 +.set CYDEV_ECC_ROW_SIZE, 0x00000020 +.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 +.set CYDEV_EEPROM_ROW_SIZE, 0x00000010 +.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE +.set CYCLK_LD_DISABLE, 0x00000004 +.set CYCLK_LD_SYNC_EN, 0x00000002 +.set CYCLK_LD_LOAD, 0x00000001 +.set CYCLK_PIPE, 0x00000080 +.set CYCLK_SSS, 0x00000040 +.set CYCLK_EARLY, 0x00000020 +.set CYCLK_DUTY, 0x00000010 +.set CYCLK_SYNC, 0x00000008 +.set CYCLK_SRC_SEL_CLK_SYNC_D, 0 +.set CYCLK_SRC_SEL_SYNC_DIG, 0 +.set CYCLK_SRC_SEL_IMO, 1 +.set CYCLK_SRC_SEL_XTAL_MHZ, 2 +.set CYCLK_SRC_SEL_XTALM, 2 +.set CYCLK_SRC_SEL_ILO, 3 +.set CYCLK_SRC_SEL_PLL, 4 +.set CYCLK_SRC_SEL_XTAL_KHZ, 5 +.set CYCLK_SRC_SEL_XTALK, 5 +.set CYCLK_SRC_SEL_DSI_G, 6 +.set CYCLK_SRC_SEL_DSI_D, 7 +.set CYCLK_SRC_SEL_CLK_SYNC_A, 0 +.set CYCLK_SRC_SEL_DSI_A, 7 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc new file mode 100644 index 0000000..93a6029 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -0,0 +1,5356 @@ +/******************************************************************************* +* FILENAME: cydevicegnu_trm.inc +* +* PSoC Creator 2.2 Component Pack 6 +* +* DESCRIPTION: +* This file provides all of the address values for the entire PSoC device. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.set CYDEV_FLASH_BASE, 0x00000000 +.set CYDEV_FLASH_SIZE, 0x00040000 +.set CYREG_FLASH_DATA_MBASE, 0x00000000 +.set CYREG_FLASH_DATA_MSIZE, 0x00040000 +.set CYDEV_SRAM_BASE, 0x1fff8000 +.set CYDEV_SRAM_SIZE, 0x00010000 +.set CYREG_SRAM_CODE64K_MBASE, 0x1fff8000 +.set CYREG_SRAM_CODE64K_MSIZE, 0x00004000 +.set CYREG_SRAM_CODE32K_MBASE, 0x1fffc000 +.set CYREG_SRAM_CODE32K_MSIZE, 0x00002000 +.set CYREG_SRAM_CODE16K_MBASE, 0x1fffe000 +.set CYREG_SRAM_CODE16K_MSIZE, 0x00001000 +.set CYREG_SRAM_CODE_MBASE, 0x1fff8000 +.set CYREG_SRAM_CODE_MSIZE, 0x00008000 +.set CYREG_SRAM_DATA_MBASE, 0x20000000 +.set CYREG_SRAM_DATA_MSIZE, 0x00008000 +.set CYREG_SRAM_DATA16K_MBASE, 0x20001000 +.set CYREG_SRAM_DATA16K_MSIZE, 0x00001000 +.set CYREG_SRAM_DATA32K_MBASE, 0x20002000 +.set CYREG_SRAM_DATA32K_MSIZE, 0x00002000 +.set CYREG_SRAM_DATA64K_MBASE, 0x20004000 +.set CYREG_SRAM_DATA64K_MSIZE, 0x00004000 +.set CYDEV_DMA_BASE, 0x20008000 +.set CYDEV_DMA_SIZE, 0x00008000 +.set CYREG_DMA_SRAM64K_MBASE, 0x20008000 +.set CYREG_DMA_SRAM64K_MSIZE, 0x00004000 +.set CYREG_DMA_SRAM32K_MBASE, 0x2000c000 +.set CYREG_DMA_SRAM32K_MSIZE, 0x00002000 +.set CYREG_DMA_SRAM16K_MBASE, 0x2000e000 +.set CYREG_DMA_SRAM16K_MSIZE, 0x00001000 +.set CYREG_DMA_SRAM_MBASE, 0x2000f000 +.set CYREG_DMA_SRAM_MSIZE, 0x00001000 +.set CYDEV_CLKDIST_BASE, 0x40004000 +.set CYDEV_CLKDIST_SIZE, 0x00000110 +.set CYREG_CLKDIST_CR, 0x40004000 +.set CYREG_CLKDIST_LD, 0x40004001 +.set CYREG_CLKDIST_WRK0, 0x40004002 +.set CYREG_CLKDIST_WRK1, 0x40004003 +.set CYREG_CLKDIST_MSTR0, 0x40004004 +.set CYREG_CLKDIST_MSTR1, 0x40004005 +.set CYREG_CLKDIST_BCFG0, 0x40004006 +.set CYREG_CLKDIST_BCFG1, 0x40004007 +.set CYREG_CLKDIST_BCFG2, 0x40004008 +.set CYREG_CLKDIST_UCFG, 0x40004009 +.set CYREG_CLKDIST_DLY0, 0x4000400a +.set CYREG_CLKDIST_DLY1, 0x4000400b +.set CYREG_CLKDIST_DMASK, 0x40004010 +.set CYREG_CLKDIST_AMASK, 0x40004014 +.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG0_CFG0, 0x40004080 +.set CYREG_CLKDIST_DCFG0_CFG1, 0x40004081 +.set CYREG_CLKDIST_DCFG0_CFG2, 0x40004082 +.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG1_CFG0, 0x40004084 +.set CYREG_CLKDIST_DCFG1_CFG1, 0x40004085 +.set CYREG_CLKDIST_DCFG1_CFG2, 0x40004086 +.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG2_CFG0, 0x40004088 +.set CYREG_CLKDIST_DCFG2_CFG1, 0x40004089 +.set CYREG_CLKDIST_DCFG2_CFG2, 0x4000408a +.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG3_CFG0, 0x4000408c +.set CYREG_CLKDIST_DCFG3_CFG1, 0x4000408d +.set CYREG_CLKDIST_DCFG3_CFG2, 0x4000408e +.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG4_CFG0, 0x40004090 +.set CYREG_CLKDIST_DCFG4_CFG1, 0x40004091 +.set CYREG_CLKDIST_DCFG4_CFG2, 0x40004092 +.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG5_CFG0, 0x40004094 +.set CYREG_CLKDIST_DCFG5_CFG1, 0x40004095 +.set CYREG_CLKDIST_DCFG5_CFG2, 0x40004096 +.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG6_CFG0, 0x40004098 +.set CYREG_CLKDIST_DCFG6_CFG1, 0x40004099 +.set CYREG_CLKDIST_DCFG6_CFG2, 0x4000409a +.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG7_CFG0, 0x4000409c +.set CYREG_CLKDIST_DCFG7_CFG1, 0x4000409d +.set CYREG_CLKDIST_DCFG7_CFG2, 0x4000409e +.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG0_CFG0, 0x40004100 +.set CYREG_CLKDIST_ACFG0_CFG1, 0x40004101 +.set CYREG_CLKDIST_ACFG0_CFG2, 0x40004102 +.set CYREG_CLKDIST_ACFG0_CFG3, 0x40004103 +.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG1_CFG0, 0x40004104 +.set CYREG_CLKDIST_ACFG1_CFG1, 0x40004105 +.set CYREG_CLKDIST_ACFG1_CFG2, 0x40004106 +.set CYREG_CLKDIST_ACFG1_CFG3, 0x40004107 +.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG2_CFG0, 0x40004108 +.set CYREG_CLKDIST_ACFG2_CFG1, 0x40004109 +.set CYREG_CLKDIST_ACFG2_CFG2, 0x4000410a +.set CYREG_CLKDIST_ACFG2_CFG3, 0x4000410b +.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG3_CFG0, 0x4000410c +.set CYREG_CLKDIST_ACFG3_CFG1, 0x4000410d +.set CYREG_CLKDIST_ACFG3_CFG2, 0x4000410e +.set CYREG_CLKDIST_ACFG3_CFG3, 0x4000410f +.set CYDEV_FASTCLK_BASE, 0x40004200 +.set CYDEV_FASTCLK_SIZE, 0x00000026 +.set CYDEV_FASTCLK_IMO_BASE, 0x40004200 +.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 +.set CYREG_FASTCLK_IMO_CR, 0x40004200 +.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 +.set CYREG_FASTCLK_XMHZ_CSR, 0x40004210 +.set CYREG_FASTCLK_XMHZ_CFG0, 0x40004212 +.set CYREG_FASTCLK_XMHZ_CFG1, 0x40004213 +.set CYDEV_FASTCLK_PLL_BASE, 0x40004220 +.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 +.set CYREG_FASTCLK_PLL_CFG0, 0x40004220 +.set CYREG_FASTCLK_PLL_CFG1, 0x40004221 +.set CYREG_FASTCLK_PLL_P, 0x40004222 +.set CYREG_FASTCLK_PLL_Q, 0x40004223 +.set CYREG_FASTCLK_PLL_SR, 0x40004225 +.set CYDEV_SLOWCLK_BASE, 0x40004300 +.set CYDEV_SLOWCLK_SIZE, 0x0000000b +.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 +.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 +.set CYREG_SLOWCLK_ILO_CR0, 0x40004300 +.set CYREG_SLOWCLK_ILO_CR1, 0x40004301 +.set CYDEV_SLOWCLK_X32_BASE, 0x40004308 +.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 +.set CYREG_SLOWCLK_X32_CR, 0x40004308 +.set CYREG_SLOWCLK_X32_CFG, 0x40004309 +.set CYREG_SLOWCLK_X32_TST, 0x4000430a +.set CYDEV_BOOST_BASE, 0x40004320 +.set CYDEV_BOOST_SIZE, 0x00000007 +.set CYREG_BOOST_CR0, 0x40004320 +.set CYREG_BOOST_CR1, 0x40004321 +.set CYREG_BOOST_CR2, 0x40004322 +.set CYREG_BOOST_CR3, 0x40004323 +.set CYREG_BOOST_SR, 0x40004324 +.set CYREG_BOOST_CR4, 0x40004325 +.set CYREG_BOOST_SR2, 0x40004326 +.set CYDEV_PWRSYS_BASE, 0x40004330 +.set CYDEV_PWRSYS_SIZE, 0x00000002 +.set CYREG_PWRSYS_CR0, 0x40004330 +.set CYREG_PWRSYS_CR1, 0x40004331 +.set CYDEV_PM_BASE, 0x40004380 +.set CYDEV_PM_SIZE, 0x00000057 +.set CYREG_PM_TW_CFG0, 0x40004380 +.set CYREG_PM_TW_CFG1, 0x40004381 +.set CYREG_PM_TW_CFG2, 0x40004382 +.set CYREG_PM_WDT_CFG, 0x40004383 +.set CYREG_PM_WDT_CR, 0x40004384 +.set CYREG_PM_INT_SR, 0x40004390 +.set CYREG_PM_MODE_CFG0, 0x40004391 +.set CYREG_PM_MODE_CFG1, 0x40004392 +.set CYREG_PM_MODE_CSR, 0x40004393 +.set CYREG_PM_USB_CR0, 0x40004394 +.set CYREG_PM_WAKEUP_CFG0, 0x40004398 +.set CYREG_PM_WAKEUP_CFG1, 0x40004399 +.set CYREG_PM_WAKEUP_CFG2, 0x4000439a +.set CYDEV_PM_ACT_BASE, 0x400043a0 +.set CYDEV_PM_ACT_SIZE, 0x0000000e +.set CYREG_PM_ACT_CFG0, 0x400043a0 +.set CYREG_PM_ACT_CFG1, 0x400043a1 +.set CYREG_PM_ACT_CFG2, 0x400043a2 +.set CYREG_PM_ACT_CFG3, 0x400043a3 +.set CYREG_PM_ACT_CFG4, 0x400043a4 +.set CYREG_PM_ACT_CFG5, 0x400043a5 +.set CYREG_PM_ACT_CFG6, 0x400043a6 +.set CYREG_PM_ACT_CFG7, 0x400043a7 +.set CYREG_PM_ACT_CFG8, 0x400043a8 +.set CYREG_PM_ACT_CFG9, 0x400043a9 +.set CYREG_PM_ACT_CFG10, 0x400043aa +.set CYREG_PM_ACT_CFG11, 0x400043ab +.set CYREG_PM_ACT_CFG12, 0x400043ac +.set CYREG_PM_ACT_CFG13, 0x400043ad +.set CYDEV_PM_STBY_BASE, 0x400043b0 +.set CYDEV_PM_STBY_SIZE, 0x0000000e +.set CYREG_PM_STBY_CFG0, 0x400043b0 +.set CYREG_PM_STBY_CFG1, 0x400043b1 +.set CYREG_PM_STBY_CFG2, 0x400043b2 +.set CYREG_PM_STBY_CFG3, 0x400043b3 +.set CYREG_PM_STBY_CFG4, 0x400043b4 +.set CYREG_PM_STBY_CFG5, 0x400043b5 +.set CYREG_PM_STBY_CFG6, 0x400043b6 +.set CYREG_PM_STBY_CFG7, 0x400043b7 +.set CYREG_PM_STBY_CFG8, 0x400043b8 +.set CYREG_PM_STBY_CFG9, 0x400043b9 +.set CYREG_PM_STBY_CFG10, 0x400043ba +.set CYREG_PM_STBY_CFG11, 0x400043bb +.set CYREG_PM_STBY_CFG12, 0x400043bc +.set CYREG_PM_STBY_CFG13, 0x400043bd +.set CYDEV_PM_AVAIL_BASE, 0x400043c0 +.set CYDEV_PM_AVAIL_SIZE, 0x00000017 +.set CYREG_PM_AVAIL_CR0, 0x400043c0 +.set CYREG_PM_AVAIL_CR1, 0x400043c1 +.set CYREG_PM_AVAIL_CR2, 0x400043c2 +.set CYREG_PM_AVAIL_CR3, 0x400043c3 +.set CYREG_PM_AVAIL_CR4, 0x400043c4 +.set CYREG_PM_AVAIL_CR5, 0x400043c5 +.set CYREG_PM_AVAIL_CR6, 0x400043c6 +.set CYREG_PM_AVAIL_SR0, 0x400043d0 +.set CYREG_PM_AVAIL_SR1, 0x400043d1 +.set CYREG_PM_AVAIL_SR2, 0x400043d2 +.set CYREG_PM_AVAIL_SR3, 0x400043d3 +.set CYREG_PM_AVAIL_SR4, 0x400043d4 +.set CYREG_PM_AVAIL_SR5, 0x400043d5 +.set CYREG_PM_AVAIL_SR6, 0x400043d6 +.set CYDEV_PICU_BASE, 0x40004500 +.set CYDEV_PICU_SIZE, 0x000000b0 +.set CYDEV_PICU_INTTYPE_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 +.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 +.set CYREG_PICU0_INTTYPE0, 0x40004500 +.set CYREG_PICU0_INTTYPE1, 0x40004501 +.set CYREG_PICU0_INTTYPE2, 0x40004502 +.set CYREG_PICU0_INTTYPE3, 0x40004503 +.set CYREG_PICU0_INTTYPE4, 0x40004504 +.set CYREG_PICU0_INTTYPE5, 0x40004505 +.set CYREG_PICU0_INTTYPE6, 0x40004506 +.set CYREG_PICU0_INTTYPE7, 0x40004507 +.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 +.set CYREG_PICU1_INTTYPE0, 0x40004508 +.set CYREG_PICU1_INTTYPE1, 0x40004509 +.set CYREG_PICU1_INTTYPE2, 0x4000450a +.set CYREG_PICU1_INTTYPE3, 0x4000450b +.set CYREG_PICU1_INTTYPE4, 0x4000450c +.set CYREG_PICU1_INTTYPE5, 0x4000450d +.set CYREG_PICU1_INTTYPE6, 0x4000450e +.set CYREG_PICU1_INTTYPE7, 0x4000450f +.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 +.set CYREG_PICU2_INTTYPE0, 0x40004510 +.set CYREG_PICU2_INTTYPE1, 0x40004511 +.set CYREG_PICU2_INTTYPE2, 0x40004512 +.set CYREG_PICU2_INTTYPE3, 0x40004513 +.set CYREG_PICU2_INTTYPE4, 0x40004514 +.set CYREG_PICU2_INTTYPE5, 0x40004515 +.set CYREG_PICU2_INTTYPE6, 0x40004516 +.set CYREG_PICU2_INTTYPE7, 0x40004517 +.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 +.set CYREG_PICU3_INTTYPE0, 0x40004518 +.set CYREG_PICU3_INTTYPE1, 0x40004519 +.set CYREG_PICU3_INTTYPE2, 0x4000451a +.set CYREG_PICU3_INTTYPE3, 0x4000451b +.set CYREG_PICU3_INTTYPE4, 0x4000451c +.set CYREG_PICU3_INTTYPE5, 0x4000451d +.set CYREG_PICU3_INTTYPE6, 0x4000451e +.set CYREG_PICU3_INTTYPE7, 0x4000451f +.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 +.set CYREG_PICU4_INTTYPE0, 0x40004520 +.set CYREG_PICU4_INTTYPE1, 0x40004521 +.set CYREG_PICU4_INTTYPE2, 0x40004522 +.set CYREG_PICU4_INTTYPE3, 0x40004523 +.set CYREG_PICU4_INTTYPE4, 0x40004524 +.set CYREG_PICU4_INTTYPE5, 0x40004525 +.set CYREG_PICU4_INTTYPE6, 0x40004526 +.set CYREG_PICU4_INTTYPE7, 0x40004527 +.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 +.set CYREG_PICU5_INTTYPE0, 0x40004528 +.set CYREG_PICU5_INTTYPE1, 0x40004529 +.set CYREG_PICU5_INTTYPE2, 0x4000452a +.set CYREG_PICU5_INTTYPE3, 0x4000452b +.set CYREG_PICU5_INTTYPE4, 0x4000452c +.set CYREG_PICU5_INTTYPE5, 0x4000452d +.set CYREG_PICU5_INTTYPE6, 0x4000452e +.set CYREG_PICU5_INTTYPE7, 0x4000452f +.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 +.set CYREG_PICU6_INTTYPE0, 0x40004530 +.set CYREG_PICU6_INTTYPE1, 0x40004531 +.set CYREG_PICU6_INTTYPE2, 0x40004532 +.set CYREG_PICU6_INTTYPE3, 0x40004533 +.set CYREG_PICU6_INTTYPE4, 0x40004534 +.set CYREG_PICU6_INTTYPE5, 0x40004535 +.set CYREG_PICU6_INTTYPE6, 0x40004536 +.set CYREG_PICU6_INTTYPE7, 0x40004537 +.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 +.set CYREG_PICU12_INTTYPE0, 0x40004560 +.set CYREG_PICU12_INTTYPE1, 0x40004561 +.set CYREG_PICU12_INTTYPE2, 0x40004562 +.set CYREG_PICU12_INTTYPE3, 0x40004563 +.set CYREG_PICU12_INTTYPE4, 0x40004564 +.set CYREG_PICU12_INTTYPE5, 0x40004565 +.set CYREG_PICU12_INTTYPE6, 0x40004566 +.set CYREG_PICU12_INTTYPE7, 0x40004567 +.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 +.set CYREG_PICU15_INTTYPE0, 0x40004578 +.set CYREG_PICU15_INTTYPE1, 0x40004579 +.set CYREG_PICU15_INTTYPE2, 0x4000457a +.set CYREG_PICU15_INTTYPE3, 0x4000457b +.set CYREG_PICU15_INTTYPE4, 0x4000457c +.set CYREG_PICU15_INTTYPE5, 0x4000457d +.set CYREG_PICU15_INTTYPE6, 0x4000457e +.set CYREG_PICU15_INTTYPE7, 0x4000457f +.set CYDEV_PICU_STAT_BASE, 0x40004580 +.set CYDEV_PICU_STAT_SIZE, 0x00000010 +.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 +.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_INTSTAT, 0x40004580 +.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 +.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_INTSTAT, 0x40004581 +.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 +.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_INTSTAT, 0x40004582 +.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 +.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_INTSTAT, 0x40004583 +.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 +.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_INTSTAT, 0x40004584 +.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 +.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_INTSTAT, 0x40004585 +.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 +.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_INTSTAT, 0x40004586 +.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c +.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_INTSTAT, 0x4000458c +.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f +.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 +.set CYREG_PICU15_INTSTAT, 0x4000458f +.set CYDEV_PICU_SNAP_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_SIZE, 0x00000010 +.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_SNAP, 0x40004590 +.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 +.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_SNAP, 0x40004591 +.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 +.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_SNAP, 0x40004592 +.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 +.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_SNAP, 0x40004593 +.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 +.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_SNAP, 0x40004594 +.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 +.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_SNAP, 0x40004595 +.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 +.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_SNAP, 0x40004596 +.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c +.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_SNAP, 0x4000459c +.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f +.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 +.set CYREG_PICU_15_SNAP_15, 0x4000459f +.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 +.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_DISABLE_COR, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_DISABLE_COR, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_DISABLE_COR, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_DISABLE_COR, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_DISABLE_COR, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_DISABLE_COR, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_DISABLE_COR, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_DISABLE_COR, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af +.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 +.set CYREG_PICU15_DISABLE_COR, 0x400045af +.set CYDEV_MFGCFG_BASE, 0x40004600 +.set CYDEV_MFGCFG_SIZE, 0x000000ed +.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 +.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 +.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 +.set CYREG_DAC0_TR, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 +.set CYREG_DAC1_TR, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 +.set CYREG_DAC2_TR, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 +.set CYREG_DAC3_TR, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 +.set CYREG_NPUMP_DSM_TR0, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 +.set CYREG_NPUMP_SC_TR0, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 +.set CYREG_NPUMP_OPAMP_TR0, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 +.set CYREG_SAR0_TR0, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 +.set CYREG_SAR1_TR0, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_TR0, 0x40004620 +.set CYREG_OPAMP0_TR1, 0x40004621 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_TR0, 0x40004622 +.set CYREG_OPAMP1_TR1, 0x40004623 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_TR0, 0x40004624 +.set CYREG_OPAMP2_TR1, 0x40004625 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_TR0, 0x40004626 +.set CYREG_OPAMP3_TR1, 0x40004627 +.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 +.set CYREG_CMP0_TR0, 0x40004630 +.set CYREG_CMP0_TR1, 0x40004631 +.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 +.set CYREG_CMP1_TR0, 0x40004632 +.set CYREG_CMP1_TR1, 0x40004633 +.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 +.set CYREG_CMP2_TR0, 0x40004634 +.set CYREG_CMP2_TR1, 0x40004635 +.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 +.set CYREG_CMP3_TR0, 0x40004636 +.set CYREG_CMP3_TR1, 0x40004637 +.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b +.set CYREG_PWRSYS_HIB_TR0, 0x40004680 +.set CYREG_PWRSYS_HIB_TR1, 0x40004681 +.set CYREG_PWRSYS_I2C_TR, 0x40004682 +.set CYREG_PWRSYS_SLP_TR, 0x40004683 +.set CYREG_PWRSYS_BUZZ_TR, 0x40004684 +.set CYREG_PWRSYS_WAKE_TR0, 0x40004685 +.set CYREG_PWRSYS_WAKE_TR1, 0x40004686 +.set CYREG_PWRSYS_BREF_TR, 0x40004687 +.set CYREG_PWRSYS_BG_TR, 0x40004688 +.set CYREG_PWRSYS_WAKE_TR2, 0x40004689 +.set CYREG_PWRSYS_WAKE_TR3, 0x4000468a +.set CYDEV_MFGCFG_ILO_BASE, 0x40004690 +.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 +.set CYREG_ILO_TR0, 0x40004690 +.set CYREG_ILO_TR1, 0x40004691 +.set CYDEV_MFGCFG_X32_BASE, 0x40004698 +.set CYDEV_MFGCFG_X32_SIZE, 0x00000001 +.set CYREG_X32_TR, 0x40004698 +.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 +.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 +.set CYREG_IMO_TR0, 0x400046a0 +.set CYREG_IMO_TR1, 0x400046a1 +.set CYREG_IMO_GAIN, 0x400046a2 +.set CYREG_IMO_C36M, 0x400046a3 +.set CYREG_IMO_TR2, 0x400046a4 +.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 +.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 +.set CYREG_XMHZ_TR, 0x400046a8 +.set CYREG_MFGCFG_DLY, 0x400046c0 +.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 +.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d +.set CYREG_MLOGIC_DMPSTR, 0x400046e2 +.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 +.set CYREG_MLOGIC_SEG_CR, 0x400046e4 +.set CYREG_MLOGIC_SEG_CFG0, 0x400046e5 +.set CYREG_MLOGIC_DEBUG, 0x400046e8 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 +.set CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea +.set CYREG_MLOGIC_REV_ID, 0x400046ec +.set CYDEV_RESET_BASE, 0x400046f0 +.set CYDEV_RESET_SIZE, 0x0000000f +.set CYREG_RESET_IPOR_CR0, 0x400046f0 +.set CYREG_RESET_IPOR_CR1, 0x400046f1 +.set CYREG_RESET_IPOR_CR2, 0x400046f2 +.set CYREG_RESET_IPOR_CR3, 0x400046f3 +.set CYREG_RESET_CR0, 0x400046f4 +.set CYREG_RESET_CR1, 0x400046f5 +.set CYREG_RESET_CR2, 0x400046f6 +.set CYREG_RESET_CR3, 0x400046f7 +.set CYREG_RESET_CR4, 0x400046f8 +.set CYREG_RESET_CR5, 0x400046f9 +.set CYREG_RESET_SR0, 0x400046fa +.set CYREG_RESET_SR1, 0x400046fb +.set CYREG_RESET_SR2, 0x400046fc +.set CYREG_RESET_SR3, 0x400046fd +.set CYREG_RESET_TR, 0x400046fe +.set CYDEV_SPC_BASE, 0x40004700 +.set CYDEV_SPC_SIZE, 0x00000100 +.set CYREG_SPC_FM_EE_CR, 0x40004700 +.set CYREG_SPC_FM_EE_WAKE_CNT, 0x40004701 +.set CYREG_SPC_EE_SCR, 0x40004702 +.set CYREG_SPC_EE_ERR, 0x40004703 +.set CYREG_SPC_CPU_DATA, 0x40004720 +.set CYREG_SPC_DMA_DATA, 0x40004721 +.set CYREG_SPC_SR, 0x40004722 +.set CYREG_SPC_CR, 0x40004723 +.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 +.set CYREG_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 +.set CYREG_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 +.set CYDEV_CACHE_BASE, 0x40004800 +.set CYDEV_CACHE_SIZE, 0x0000009c +.set CYREG_CACHE_CC_CTL, 0x40004800 +.set CYREG_CACHE_ECC_CORR, 0x40004880 +.set CYREG_CACHE_ECC_ERR, 0x40004888 +.set CYREG_CACHE_FLASH_ERR, 0x40004890 +.set CYREG_CACHE_HITMISS, 0x40004898 +.set CYDEV_I2C_BASE, 0x40004900 +.set CYDEV_I2C_SIZE, 0x000000e1 +.set CYREG_I2C_XCFG, 0x400049c8 +.set CYREG_I2C_ADR, 0x400049ca +.set CYREG_I2C_CFG, 0x400049d6 +.set CYREG_I2C_CSR, 0x400049d7 +.set CYREG_I2C_D, 0x400049d8 +.set CYREG_I2C_MCSR, 0x400049d9 +.set CYREG_I2C_CLK_DIV1, 0x400049db +.set CYREG_I2C_CLK_DIV2, 0x400049dc +.set CYREG_I2C_TMOUT_CSR, 0x400049dd +.set CYREG_I2C_TMOUT_SR, 0x400049de +.set CYREG_I2C_TMOUT_CFG0, 0x400049df +.set CYREG_I2C_TMOUT_CFG1, 0x400049e0 +.set CYDEV_DEC_BASE, 0x40004e00 +.set CYDEV_DEC_SIZE, 0x00000015 +.set CYREG_DEC_CR, 0x40004e00 +.set CYREG_DEC_SR, 0x40004e01 +.set CYREG_DEC_SHIFT1, 0x40004e02 +.set CYREG_DEC_SHIFT2, 0x40004e03 +.set CYREG_DEC_DR2, 0x40004e04 +.set CYREG_DEC_DR2H, 0x40004e05 +.set CYREG_DEC_DR1, 0x40004e06 +.set CYREG_DEC_OCOR, 0x40004e08 +.set CYREG_DEC_OCORM, 0x40004e09 +.set CYREG_DEC_OCORH, 0x40004e0a +.set CYREG_DEC_GCOR, 0x40004e0c +.set CYREG_DEC_GCORH, 0x40004e0d +.set CYREG_DEC_GVAL, 0x40004e0e +.set CYREG_DEC_OUTSAMP, 0x40004e10 +.set CYREG_DEC_OUTSAMPM, 0x40004e11 +.set CYREG_DEC_OUTSAMPH, 0x40004e12 +.set CYREG_DEC_OUTSAMPS, 0x40004e13 +.set CYREG_DEC_COHER, 0x40004e14 +.set CYDEV_TMR0_BASE, 0x40004f00 +.set CYDEV_TMR0_SIZE, 0x0000000c +.set CYREG_TMR0_CFG0, 0x40004f00 +.set CYREG_TMR0_CFG1, 0x40004f01 +.set CYREG_TMR0_CFG2, 0x40004f02 +.set CYREG_TMR0_SR0, 0x40004f03 +.set CYREG_TMR0_PER0, 0x40004f04 +.set CYREG_TMR0_PER1, 0x40004f05 +.set CYREG_TMR0_CNT_CMP0, 0x40004f06 +.set CYREG_TMR0_CNT_CMP1, 0x40004f07 +.set CYREG_TMR0_CAP0, 0x40004f08 +.set CYREG_TMR0_CAP1, 0x40004f09 +.set CYREG_TMR0_RT0, 0x40004f0a +.set CYREG_TMR0_RT1, 0x40004f0b +.set CYDEV_TMR1_BASE, 0x40004f0c +.set CYDEV_TMR1_SIZE, 0x0000000c +.set CYREG_TMR1_CFG0, 0x40004f0c +.set CYREG_TMR1_CFG1, 0x40004f0d +.set CYREG_TMR1_CFG2, 0x40004f0e +.set CYREG_TMR1_SR0, 0x40004f0f +.set CYREG_TMR1_PER0, 0x40004f10 +.set CYREG_TMR1_PER1, 0x40004f11 +.set CYREG_TMR1_CNT_CMP0, 0x40004f12 +.set CYREG_TMR1_CNT_CMP1, 0x40004f13 +.set CYREG_TMR1_CAP0, 0x40004f14 +.set CYREG_TMR1_CAP1, 0x40004f15 +.set CYREG_TMR1_RT0, 0x40004f16 +.set CYREG_TMR1_RT1, 0x40004f17 +.set CYDEV_TMR2_BASE, 0x40004f18 +.set CYDEV_TMR2_SIZE, 0x0000000c +.set CYREG_TMR2_CFG0, 0x40004f18 +.set CYREG_TMR2_CFG1, 0x40004f19 +.set CYREG_TMR2_CFG2, 0x40004f1a +.set CYREG_TMR2_SR0, 0x40004f1b +.set CYREG_TMR2_PER0, 0x40004f1c +.set CYREG_TMR2_PER1, 0x40004f1d +.set CYREG_TMR2_CNT_CMP0, 0x40004f1e +.set CYREG_TMR2_CNT_CMP1, 0x40004f1f +.set CYREG_TMR2_CAP0, 0x40004f20 +.set CYREG_TMR2_CAP1, 0x40004f21 +.set CYREG_TMR2_RT0, 0x40004f22 +.set CYREG_TMR2_RT1, 0x40004f23 +.set CYDEV_TMR3_BASE, 0x40004f24 +.set CYDEV_TMR3_SIZE, 0x0000000c +.set CYREG_TMR3_CFG0, 0x40004f24 +.set CYREG_TMR3_CFG1, 0x40004f25 +.set CYREG_TMR3_CFG2, 0x40004f26 +.set CYREG_TMR3_SR0, 0x40004f27 +.set CYREG_TMR3_PER0, 0x40004f28 +.set CYREG_TMR3_PER1, 0x40004f29 +.set CYREG_TMR3_CNT_CMP0, 0x40004f2a +.set CYREG_TMR3_CNT_CMP1, 0x40004f2b +.set CYREG_TMR3_CAP0, 0x40004f2c +.set CYREG_TMR3_CAP1, 0x40004f2d +.set CYREG_TMR3_RT0, 0x40004f2e +.set CYREG_TMR3_RT1, 0x40004f2f +.set CYDEV_IO_BASE, 0x40005000 +.set CYDEV_IO_SIZE, 0x00000200 +.set CYDEV_IO_PC_BASE, 0x40005000 +.set CYDEV_IO_PC_SIZE, 0x00000080 +.set CYDEV_IO_PC_PRT0_BASE, 0x40005000 +.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 +.set CYREG_PRT0_PC0, 0x40005000 +.set CYREG_PRT0_PC1, 0x40005001 +.set CYREG_PRT0_PC2, 0x40005002 +.set CYREG_PRT0_PC3, 0x40005003 +.set CYREG_PRT0_PC4, 0x40005004 +.set CYREG_PRT0_PC5, 0x40005005 +.set CYREG_PRT0_PC6, 0x40005006 +.set CYREG_PRT0_PC7, 0x40005007 +.set CYDEV_IO_PC_PRT1_BASE, 0x40005008 +.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 +.set CYREG_PRT1_PC0, 0x40005008 +.set CYREG_PRT1_PC1, 0x40005009 +.set CYREG_PRT1_PC2, 0x4000500a +.set CYREG_PRT1_PC3, 0x4000500b +.set CYREG_PRT1_PC4, 0x4000500c +.set CYREG_PRT1_PC5, 0x4000500d +.set CYREG_PRT1_PC6, 0x4000500e +.set CYREG_PRT1_PC7, 0x4000500f +.set CYDEV_IO_PC_PRT2_BASE, 0x40005010 +.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 +.set CYREG_PRT2_PC0, 0x40005010 +.set CYREG_PRT2_PC1, 0x40005011 +.set CYREG_PRT2_PC2, 0x40005012 +.set CYREG_PRT2_PC3, 0x40005013 +.set CYREG_PRT2_PC4, 0x40005014 +.set CYREG_PRT2_PC5, 0x40005015 +.set CYREG_PRT2_PC6, 0x40005016 +.set CYREG_PRT2_PC7, 0x40005017 +.set CYDEV_IO_PC_PRT3_BASE, 0x40005018 +.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 +.set CYREG_PRT3_PC0, 0x40005018 +.set CYREG_PRT3_PC1, 0x40005019 +.set CYREG_PRT3_PC2, 0x4000501a +.set CYREG_PRT3_PC3, 0x4000501b +.set CYREG_PRT3_PC4, 0x4000501c +.set CYREG_PRT3_PC5, 0x4000501d +.set CYREG_PRT3_PC6, 0x4000501e +.set CYREG_PRT3_PC7, 0x4000501f +.set CYDEV_IO_PC_PRT4_BASE, 0x40005020 +.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 +.set CYREG_PRT4_PC0, 0x40005020 +.set CYREG_PRT4_PC1, 0x40005021 +.set CYREG_PRT4_PC2, 0x40005022 +.set CYREG_PRT4_PC3, 0x40005023 +.set CYREG_PRT4_PC4, 0x40005024 +.set CYREG_PRT4_PC5, 0x40005025 +.set CYREG_PRT4_PC6, 0x40005026 +.set CYREG_PRT4_PC7, 0x40005027 +.set CYDEV_IO_PC_PRT5_BASE, 0x40005028 +.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 +.set CYREG_PRT5_PC0, 0x40005028 +.set CYREG_PRT5_PC1, 0x40005029 +.set CYREG_PRT5_PC2, 0x4000502a +.set CYREG_PRT5_PC3, 0x4000502b +.set CYREG_PRT5_PC4, 0x4000502c +.set CYREG_PRT5_PC5, 0x4000502d +.set CYREG_PRT5_PC6, 0x4000502e +.set CYREG_PRT5_PC7, 0x4000502f +.set CYDEV_IO_PC_PRT6_BASE, 0x40005030 +.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 +.set CYREG_PRT6_PC0, 0x40005030 +.set CYREG_PRT6_PC1, 0x40005031 +.set CYREG_PRT6_PC2, 0x40005032 +.set CYREG_PRT6_PC3, 0x40005033 +.set CYREG_PRT6_PC4, 0x40005034 +.set CYREG_PRT6_PC5, 0x40005035 +.set CYREG_PRT6_PC6, 0x40005036 +.set CYREG_PRT6_PC7, 0x40005037 +.set CYDEV_IO_PC_PRT12_BASE, 0x40005060 +.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 +.set CYREG_PRT12_PC0, 0x40005060 +.set CYREG_PRT12_PC1, 0x40005061 +.set CYREG_PRT12_PC2, 0x40005062 +.set CYREG_PRT12_PC3, 0x40005063 +.set CYREG_PRT12_PC4, 0x40005064 +.set CYREG_PRT12_PC5, 0x40005065 +.set CYREG_PRT12_PC6, 0x40005066 +.set CYREG_PRT12_PC7, 0x40005067 +.set CYDEV_IO_PC_PRT15_BASE, 0x40005078 +.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 +.set CYREG_IO_PC_PRT15_PC0, 0x40005078 +.set CYREG_IO_PC_PRT15_PC1, 0x40005079 +.set CYREG_IO_PC_PRT15_PC2, 0x4000507a +.set CYREG_IO_PC_PRT15_PC3, 0x4000507b +.set CYREG_IO_PC_PRT15_PC4, 0x4000507c +.set CYREG_IO_PC_PRT15_PC5, 0x4000507d +.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 +.set CYREG_IO_PC_PRT15_7_6_PC0, 0x4000507e +.set CYREG_IO_PC_PRT15_7_6_PC1, 0x4000507f +.set CYDEV_IO_DR_BASE, 0x40005080 +.set CYDEV_IO_DR_SIZE, 0x00000010 +.set CYDEV_IO_DR_PRT0_BASE, 0x40005080 +.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 +.set CYREG_PRT0_DR_ALIAS, 0x40005080 +.set CYDEV_IO_DR_PRT1_BASE, 0x40005081 +.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 +.set CYREG_PRT1_DR_ALIAS, 0x40005081 +.set CYDEV_IO_DR_PRT2_BASE, 0x40005082 +.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 +.set CYREG_PRT2_DR_ALIAS, 0x40005082 +.set CYDEV_IO_DR_PRT3_BASE, 0x40005083 +.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 +.set CYREG_PRT3_DR_ALIAS, 0x40005083 +.set CYDEV_IO_DR_PRT4_BASE, 0x40005084 +.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 +.set CYREG_PRT4_DR_ALIAS, 0x40005084 +.set CYDEV_IO_DR_PRT5_BASE, 0x40005085 +.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 +.set CYREG_PRT5_DR_ALIAS, 0x40005085 +.set CYDEV_IO_DR_PRT6_BASE, 0x40005086 +.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 +.set CYREG_PRT6_DR_ALIAS, 0x40005086 +.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c +.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 +.set CYREG_PRT12_DR_ALIAS, 0x4000508c +.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f +.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 +.set CYREG_PRT15_DR_15_ALIAS, 0x4000508f +.set CYDEV_IO_PS_BASE, 0x40005090 +.set CYDEV_IO_PS_SIZE, 0x00000010 +.set CYDEV_IO_PS_PRT0_BASE, 0x40005090 +.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 +.set CYREG_PRT0_PS_ALIAS, 0x40005090 +.set CYDEV_IO_PS_PRT1_BASE, 0x40005091 +.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 +.set CYREG_PRT1_PS_ALIAS, 0x40005091 +.set CYDEV_IO_PS_PRT2_BASE, 0x40005092 +.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 +.set CYREG_PRT2_PS_ALIAS, 0x40005092 +.set CYDEV_IO_PS_PRT3_BASE, 0x40005093 +.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 +.set CYREG_PRT3_PS_ALIAS, 0x40005093 +.set CYDEV_IO_PS_PRT4_BASE, 0x40005094 +.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 +.set CYREG_PRT4_PS_ALIAS, 0x40005094 +.set CYDEV_IO_PS_PRT5_BASE, 0x40005095 +.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 +.set CYREG_PRT5_PS_ALIAS, 0x40005095 +.set CYDEV_IO_PS_PRT6_BASE, 0x40005096 +.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 +.set CYREG_PRT6_PS_ALIAS, 0x40005096 +.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c +.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 +.set CYREG_PRT12_PS_ALIAS, 0x4000509c +.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f +.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 +.set CYREG_PRT15_PS15_ALIAS, 0x4000509f +.set CYDEV_IO_PRT_BASE, 0x40005100 +.set CYDEV_IO_PRT_SIZE, 0x00000100 +.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 +.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 +.set CYREG_PRT0_DR, 0x40005100 +.set CYREG_PRT0_PS, 0x40005101 +.set CYREG_PRT0_DM0, 0x40005102 +.set CYREG_PRT0_DM1, 0x40005103 +.set CYREG_PRT0_DM2, 0x40005104 +.set CYREG_PRT0_SLW, 0x40005105 +.set CYREG_PRT0_BYP, 0x40005106 +.set CYREG_PRT0_BIE, 0x40005107 +.set CYREG_PRT0_INP_DIS, 0x40005108 +.set CYREG_PRT0_CTL, 0x40005109 +.set CYREG_PRT0_PRT, 0x4000510a +.set CYREG_PRT0_BIT_MASK, 0x4000510b +.set CYREG_PRT0_AMUX, 0x4000510c +.set CYREG_PRT0_AG, 0x4000510d +.set CYREG_PRT0_LCD_COM_SEG, 0x4000510e +.set CYREG_PRT0_LCD_EN, 0x4000510f +.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 +.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 +.set CYREG_PRT1_DR, 0x40005110 +.set CYREG_PRT1_PS, 0x40005111 +.set CYREG_PRT1_DM0, 0x40005112 +.set CYREG_PRT1_DM1, 0x40005113 +.set CYREG_PRT1_DM2, 0x40005114 +.set CYREG_PRT1_SLW, 0x40005115 +.set CYREG_PRT1_BYP, 0x40005116 +.set CYREG_PRT1_BIE, 0x40005117 +.set CYREG_PRT1_INP_DIS, 0x40005118 +.set CYREG_PRT1_CTL, 0x40005119 +.set CYREG_PRT1_PRT, 0x4000511a +.set CYREG_PRT1_BIT_MASK, 0x4000511b +.set CYREG_PRT1_AMUX, 0x4000511c +.set CYREG_PRT1_AG, 0x4000511d +.set CYREG_PRT1_LCD_COM_SEG, 0x4000511e +.set CYREG_PRT1_LCD_EN, 0x4000511f +.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 +.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 +.set CYREG_PRT2_DR, 0x40005120 +.set CYREG_PRT2_PS, 0x40005121 +.set CYREG_PRT2_DM0, 0x40005122 +.set CYREG_PRT2_DM1, 0x40005123 +.set CYREG_PRT2_DM2, 0x40005124 +.set CYREG_PRT2_SLW, 0x40005125 +.set CYREG_PRT2_BYP, 0x40005126 +.set CYREG_PRT2_BIE, 0x40005127 +.set CYREG_PRT2_INP_DIS, 0x40005128 +.set CYREG_PRT2_CTL, 0x40005129 +.set CYREG_PRT2_PRT, 0x4000512a +.set CYREG_PRT2_BIT_MASK, 0x4000512b +.set CYREG_PRT2_AMUX, 0x4000512c +.set CYREG_PRT2_AG, 0x4000512d +.set CYREG_PRT2_LCD_COM_SEG, 0x4000512e +.set CYREG_PRT2_LCD_EN, 0x4000512f +.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 +.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 +.set CYREG_PRT3_DR, 0x40005130 +.set CYREG_PRT3_PS, 0x40005131 +.set CYREG_PRT3_DM0, 0x40005132 +.set CYREG_PRT3_DM1, 0x40005133 +.set CYREG_PRT3_DM2, 0x40005134 +.set CYREG_PRT3_SLW, 0x40005135 +.set CYREG_PRT3_BYP, 0x40005136 +.set CYREG_PRT3_BIE, 0x40005137 +.set CYREG_PRT3_INP_DIS, 0x40005138 +.set CYREG_PRT3_CTL, 0x40005139 +.set CYREG_PRT3_PRT, 0x4000513a +.set CYREG_PRT3_BIT_MASK, 0x4000513b +.set CYREG_PRT3_AMUX, 0x4000513c +.set CYREG_PRT3_AG, 0x4000513d +.set CYREG_PRT3_LCD_COM_SEG, 0x4000513e +.set CYREG_PRT3_LCD_EN, 0x4000513f +.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 +.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 +.set CYREG_PRT4_DR, 0x40005140 +.set CYREG_PRT4_PS, 0x40005141 +.set CYREG_PRT4_DM0, 0x40005142 +.set CYREG_PRT4_DM1, 0x40005143 +.set CYREG_PRT4_DM2, 0x40005144 +.set CYREG_PRT4_SLW, 0x40005145 +.set CYREG_PRT4_BYP, 0x40005146 +.set CYREG_PRT4_BIE, 0x40005147 +.set CYREG_PRT4_INP_DIS, 0x40005148 +.set CYREG_PRT4_CTL, 0x40005149 +.set CYREG_PRT4_PRT, 0x4000514a +.set CYREG_PRT4_BIT_MASK, 0x4000514b +.set CYREG_PRT4_AMUX, 0x4000514c +.set CYREG_PRT4_AG, 0x4000514d +.set CYREG_PRT4_LCD_COM_SEG, 0x4000514e +.set CYREG_PRT4_LCD_EN, 0x4000514f +.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 +.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 +.set CYREG_PRT5_DR, 0x40005150 +.set CYREG_PRT5_PS, 0x40005151 +.set CYREG_PRT5_DM0, 0x40005152 +.set CYREG_PRT5_DM1, 0x40005153 +.set CYREG_PRT5_DM2, 0x40005154 +.set CYREG_PRT5_SLW, 0x40005155 +.set CYREG_PRT5_BYP, 0x40005156 +.set CYREG_PRT5_BIE, 0x40005157 +.set CYREG_PRT5_INP_DIS, 0x40005158 +.set CYREG_PRT5_CTL, 0x40005159 +.set CYREG_PRT5_PRT, 0x4000515a +.set CYREG_PRT5_BIT_MASK, 0x4000515b +.set CYREG_PRT5_AMUX, 0x4000515c +.set CYREG_PRT5_AG, 0x4000515d +.set CYREG_PRT5_LCD_COM_SEG, 0x4000515e +.set CYREG_PRT5_LCD_EN, 0x4000515f +.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 +.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 +.set CYREG_PRT6_DR, 0x40005160 +.set CYREG_PRT6_PS, 0x40005161 +.set CYREG_PRT6_DM0, 0x40005162 +.set CYREG_PRT6_DM1, 0x40005163 +.set CYREG_PRT6_DM2, 0x40005164 +.set CYREG_PRT6_SLW, 0x40005165 +.set CYREG_PRT6_BYP, 0x40005166 +.set CYREG_PRT6_BIE, 0x40005167 +.set CYREG_PRT6_INP_DIS, 0x40005168 +.set CYREG_PRT6_CTL, 0x40005169 +.set CYREG_PRT6_PRT, 0x4000516a +.set CYREG_PRT6_BIT_MASK, 0x4000516b +.set CYREG_PRT6_AMUX, 0x4000516c +.set CYREG_PRT6_AG, 0x4000516d +.set CYREG_PRT6_LCD_COM_SEG, 0x4000516e +.set CYREG_PRT6_LCD_EN, 0x4000516f +.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 +.set CYREG_PRT12_DR, 0x400051c0 +.set CYREG_PRT12_PS, 0x400051c1 +.set CYREG_PRT12_DM0, 0x400051c2 +.set CYREG_PRT12_DM1, 0x400051c3 +.set CYREG_PRT12_DM2, 0x400051c4 +.set CYREG_PRT12_SLW, 0x400051c5 +.set CYREG_PRT12_BYP, 0x400051c6 +.set CYREG_PRT12_BIE, 0x400051c7 +.set CYREG_PRT12_INP_DIS, 0x400051c8 +.set CYREG_PRT12_SIO_HYST_EN, 0x400051c9 +.set CYREG_PRT12_PRT, 0x400051ca +.set CYREG_PRT12_BIT_MASK, 0x400051cb +.set CYREG_PRT12_SIO_REG_HIFREQ, 0x400051cc +.set CYREG_PRT12_AG, 0x400051cd +.set CYREG_PRT12_SIO_CFG, 0x400051ce +.set CYREG_PRT12_SIO_DIFF, 0x400051cf +.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 +.set CYREG_PRT15_DR, 0x400051f0 +.set CYREG_PRT15_PS, 0x400051f1 +.set CYREG_PRT15_DM0, 0x400051f2 +.set CYREG_PRT15_DM1, 0x400051f3 +.set CYREG_PRT15_DM2, 0x400051f4 +.set CYREG_PRT15_SLW, 0x400051f5 +.set CYREG_PRT15_BYP, 0x400051f6 +.set CYREG_PRT15_BIE, 0x400051f7 +.set CYREG_PRT15_INP_DIS, 0x400051f8 +.set CYREG_PRT15_CTL, 0x400051f9 +.set CYREG_PRT15_PRT, 0x400051fa +.set CYREG_PRT15_BIT_MASK, 0x400051fb +.set CYREG_PRT15_AMUX, 0x400051fc +.set CYREG_PRT15_AG, 0x400051fd +.set CYREG_PRT15_LCD_COM_SEG, 0x400051fe +.set CYREG_PRT15_LCD_EN, 0x400051ff +.set CYDEV_PRTDSI_BASE, 0x40005200 +.set CYDEV_PRTDSI_SIZE, 0x0000007f +.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 +.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 +.set CYREG_PRT0_OUT_SEL0, 0x40005200 +.set CYREG_PRT0_OUT_SEL1, 0x40005201 +.set CYREG_PRT0_OE_SEL0, 0x40005202 +.set CYREG_PRT0_OE_SEL1, 0x40005203 +.set CYREG_PRT0_DBL_SYNC_IN, 0x40005204 +.set CYREG_PRT0_SYNC_OUT, 0x40005205 +.set CYREG_PRT0_CAPS_SEL, 0x40005206 +.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 +.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 +.set CYREG_PRT1_OUT_SEL0, 0x40005208 +.set CYREG_PRT1_OUT_SEL1, 0x40005209 +.set CYREG_PRT1_OE_SEL0, 0x4000520a +.set CYREG_PRT1_OE_SEL1, 0x4000520b +.set CYREG_PRT1_DBL_SYNC_IN, 0x4000520c +.set CYREG_PRT1_SYNC_OUT, 0x4000520d +.set CYREG_PRT1_CAPS_SEL, 0x4000520e +.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 +.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 +.set CYREG_PRT2_OUT_SEL0, 0x40005210 +.set CYREG_PRT2_OUT_SEL1, 0x40005211 +.set CYREG_PRT2_OE_SEL0, 0x40005212 +.set CYREG_PRT2_OE_SEL1, 0x40005213 +.set CYREG_PRT2_DBL_SYNC_IN, 0x40005214 +.set CYREG_PRT2_SYNC_OUT, 0x40005215 +.set CYREG_PRT2_CAPS_SEL, 0x40005216 +.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 +.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 +.set CYREG_PRT3_OUT_SEL0, 0x40005218 +.set CYREG_PRT3_OUT_SEL1, 0x40005219 +.set CYREG_PRT3_OE_SEL0, 0x4000521a +.set CYREG_PRT3_OE_SEL1, 0x4000521b +.set CYREG_PRT3_DBL_SYNC_IN, 0x4000521c +.set CYREG_PRT3_SYNC_OUT, 0x4000521d +.set CYREG_PRT3_CAPS_SEL, 0x4000521e +.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 +.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 +.set CYREG_PRT4_OUT_SEL0, 0x40005220 +.set CYREG_PRT4_OUT_SEL1, 0x40005221 +.set CYREG_PRT4_OE_SEL0, 0x40005222 +.set CYREG_PRT4_OE_SEL1, 0x40005223 +.set CYREG_PRT4_DBL_SYNC_IN, 0x40005224 +.set CYREG_PRT4_SYNC_OUT, 0x40005225 +.set CYREG_PRT4_CAPS_SEL, 0x40005226 +.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 +.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 +.set CYREG_PRT5_OUT_SEL0, 0x40005228 +.set CYREG_PRT5_OUT_SEL1, 0x40005229 +.set CYREG_PRT5_OE_SEL0, 0x4000522a +.set CYREG_PRT5_OE_SEL1, 0x4000522b +.set CYREG_PRT5_DBL_SYNC_IN, 0x4000522c +.set CYREG_PRT5_SYNC_OUT, 0x4000522d +.set CYREG_PRT5_CAPS_SEL, 0x4000522e +.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 +.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 +.set CYREG_PRT6_OUT_SEL0, 0x40005230 +.set CYREG_PRT6_OUT_SEL1, 0x40005231 +.set CYREG_PRT6_OE_SEL0, 0x40005232 +.set CYREG_PRT6_OE_SEL1, 0x40005233 +.set CYREG_PRT6_DBL_SYNC_IN, 0x40005234 +.set CYREG_PRT6_SYNC_OUT, 0x40005235 +.set CYREG_PRT6_CAPS_SEL, 0x40005236 +.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 +.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 +.set CYREG_PRT12_OUT_SEL0, 0x40005260 +.set CYREG_PRT12_OUT_SEL1, 0x40005261 +.set CYREG_PRT12_OE_SEL0, 0x40005262 +.set CYREG_PRT12_OE_SEL1, 0x40005263 +.set CYREG_PRT12_DBL_SYNC_IN, 0x40005264 +.set CYREG_PRT12_SYNC_OUT, 0x40005265 +.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 +.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 +.set CYREG_PRT15_OUT_SEL0, 0x40005278 +.set CYREG_PRT15_OUT_SEL1, 0x40005279 +.set CYREG_PRT15_OE_SEL0, 0x4000527a +.set CYREG_PRT15_OE_SEL1, 0x4000527b +.set CYREG_PRT15_DBL_SYNC_IN, 0x4000527c +.set CYREG_PRT15_SYNC_OUT, 0x4000527d +.set CYREG_PRT15_CAPS_SEL, 0x4000527e +.set CYDEV_EMIF_BASE, 0x40005400 +.set CYDEV_EMIF_SIZE, 0x00000007 +.set CYREG_EMIF_NO_UDB, 0x40005400 +.set CYREG_EMIF_RP_WAIT_STATES, 0x40005401 +.set CYREG_EMIF_MEM_DWN, 0x40005402 +.set CYREG_EMIF_MEMCLK_DIV, 0x40005403 +.set CYREG_EMIF_CLOCK_EN, 0x40005404 +.set CYREG_EMIF_EM_TYPE, 0x40005405 +.set CYREG_EMIF_WP_WAIT_STATES, 0x40005406 +.set CYDEV_ANAIF_BASE, 0x40005800 +.set CYDEV_ANAIF_SIZE, 0x000003a9 +.set CYDEV_ANAIF_CFG_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f +.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 +.set CYREG_SC0_CR0, 0x40005800 +.set CYREG_SC0_CR1, 0x40005801 +.set CYREG_SC0_CR2, 0x40005802 +.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 +.set CYREG_SC1_CR0, 0x40005804 +.set CYREG_SC1_CR1, 0x40005805 +.set CYREG_SC1_CR2, 0x40005806 +.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 +.set CYREG_SC2_CR0, 0x40005808 +.set CYREG_SC2_CR1, 0x40005809 +.set CYREG_SC2_CR2, 0x4000580a +.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 +.set CYREG_SC3_CR0, 0x4000580c +.set CYREG_SC3_CR1, 0x4000580d +.set CYREG_SC3_CR2, 0x4000580e +.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 +.set CYREG_DAC0_CR0, 0x40005820 +.set CYREG_DAC0_CR1, 0x40005821 +.set CYREG_DAC0_TST, 0x40005822 +.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 +.set CYREG_DAC1_CR0, 0x40005824 +.set CYREG_DAC1_CR1, 0x40005825 +.set CYREG_DAC1_TST, 0x40005826 +.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 +.set CYREG_DAC2_CR0, 0x40005828 +.set CYREG_DAC2_CR1, 0x40005829 +.set CYREG_DAC2_TST, 0x4000582a +.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 +.set CYREG_DAC3_CR0, 0x4000582c +.set CYREG_DAC3_CR1, 0x4000582d +.set CYREG_DAC3_TST, 0x4000582e +.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 +.set CYREG_CMP0_CR, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 +.set CYREG_CMP1_CR, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 +.set CYREG_CMP2_CR, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 +.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 +.set CYREG_CMP3_CR, 0x40005843 +.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 +.set CYREG_LUT0_CR, 0x40005848 +.set CYREG_LUT0_MX, 0x40005849 +.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 +.set CYREG_LUT1_CR, 0x4000584a +.set CYREG_LUT1_MX, 0x4000584b +.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 +.set CYREG_LUT2_CR, 0x4000584c +.set CYREG_LUT2_MX, 0x4000584d +.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 +.set CYREG_LUT3_CR, 0x4000584e +.set CYREG_LUT3_MX, 0x4000584f +.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_CR, 0x40005858 +.set CYREG_OPAMP0_RSVD, 0x40005859 +.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_CR, 0x4000585a +.set CYREG_OPAMP1_RSVD, 0x4000585b +.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_CR, 0x4000585c +.set CYREG_OPAMP2_RSVD, 0x4000585d +.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_CR, 0x4000585e +.set CYREG_OPAMP3_RSVD, 0x4000585f +.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 +.set CYREG_LCDDAC_CR0, 0x40005868 +.set CYREG_LCDDAC_CR1, 0x40005869 +.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 +.set CYREG_LCDDRV_CR, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b +.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 +.set CYREG_LCDTMR_CFG, 0x4000586b +.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 +.set CYREG_BG_CR0, 0x4000586c +.set CYREG_BG_RSVD, 0x4000586d +.set CYREG_BG_DFT0, 0x4000586e +.set CYREG_BG_DFT1, 0x4000586f +.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 +.set CYREG_CAPSL_CFG0, 0x40005870 +.set CYREG_CAPSL_CFG1, 0x40005871 +.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 +.set CYREG_CAPSR_CFG0, 0x40005872 +.set CYREG_CAPSR_CFG1, 0x40005873 +.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 +.set CYREG_PUMP_CR0, 0x40005876 +.set CYREG_PUMP_CR1, 0x40005877 +.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 +.set CYREG_LPF0_CR0, 0x40005878 +.set CYREG_LPF0_RSVD, 0x40005879 +.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 +.set CYREG_LPF1_CR0, 0x4000587a +.set CYREG_LPF1_RSVD, 0x4000587b +.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c +.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 +.set CYREG_ANAIF_CFG_MISC_CR0, 0x4000587c +.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 +.set CYREG_DSM0_CR0, 0x40005880 +.set CYREG_DSM0_CR1, 0x40005881 +.set CYREG_DSM0_CR2, 0x40005882 +.set CYREG_DSM0_CR3, 0x40005883 +.set CYREG_DSM0_CR4, 0x40005884 +.set CYREG_DSM0_CR5, 0x40005885 +.set CYREG_DSM0_CR6, 0x40005886 +.set CYREG_DSM0_CR7, 0x40005887 +.set CYREG_DSM0_CR8, 0x40005888 +.set CYREG_DSM0_CR9, 0x40005889 +.set CYREG_DSM0_CR10, 0x4000588a +.set CYREG_DSM0_CR11, 0x4000588b +.set CYREG_DSM0_CR12, 0x4000588c +.set CYREG_DSM0_CR13, 0x4000588d +.set CYREG_DSM0_CR14, 0x4000588e +.set CYREG_DSM0_CR15, 0x4000588f +.set CYREG_DSM0_CR16, 0x40005890 +.set CYREG_DSM0_CR17, 0x40005891 +.set CYREG_DSM0_REF0, 0x40005892 +.set CYREG_DSM0_REF1, 0x40005893 +.set CYREG_DSM0_REF2, 0x40005894 +.set CYREG_DSM0_REF3, 0x40005895 +.set CYREG_DSM0_DEM0, 0x40005896 +.set CYREG_DSM0_DEM1, 0x40005897 +.set CYREG_DSM0_TST0, 0x40005898 +.set CYREG_DSM0_TST1, 0x40005899 +.set CYREG_DSM0_BUF0, 0x4000589a +.set CYREG_DSM0_BUF1, 0x4000589b +.set CYREG_DSM0_BUF2, 0x4000589c +.set CYREG_DSM0_BUF3, 0x4000589d +.set CYREG_DSM0_MISC, 0x4000589e +.set CYREG_DSM0_RSVD1, 0x4000589f +.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 +.set CYREG_SAR0_CSR0, 0x40005900 +.set CYREG_SAR0_CSR1, 0x40005901 +.set CYREG_SAR0_CSR2, 0x40005902 +.set CYREG_SAR0_CSR3, 0x40005903 +.set CYREG_SAR0_CSR4, 0x40005904 +.set CYREG_SAR0_CSR5, 0x40005905 +.set CYREG_SAR0_CSR6, 0x40005906 +.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 +.set CYREG_SAR1_CSR0, 0x40005908 +.set CYREG_SAR1_CSR1, 0x40005909 +.set CYREG_SAR1_CSR2, 0x4000590a +.set CYREG_SAR1_CSR3, 0x4000590b +.set CYREG_SAR1_CSR4, 0x4000590c +.set CYREG_SAR1_CSR5, 0x4000590d +.set CYREG_SAR1_CSR6, 0x4000590e +.set CYDEV_ANAIF_RT_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SIZE, 0x00000162 +.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d +.set CYREG_SC0_SW0, 0x40005a00 +.set CYREG_SC0_SW2, 0x40005a02 +.set CYREG_SC0_SW3, 0x40005a03 +.set CYREG_SC0_SW4, 0x40005a04 +.set CYREG_SC0_SW6, 0x40005a06 +.set CYREG_SC0_SW7, 0x40005a07 +.set CYREG_SC0_SW8, 0x40005a08 +.set CYREG_SC0_SW10, 0x40005a0a +.set CYREG_SC0_CLK, 0x40005a0b +.set CYREG_SC0_BST, 0x40005a0c +.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d +.set CYREG_SC1_SW0, 0x40005a10 +.set CYREG_SC1_SW2, 0x40005a12 +.set CYREG_SC1_SW3, 0x40005a13 +.set CYREG_SC1_SW4, 0x40005a14 +.set CYREG_SC1_SW6, 0x40005a16 +.set CYREG_SC1_SW7, 0x40005a17 +.set CYREG_SC1_SW8, 0x40005a18 +.set CYREG_SC1_SW10, 0x40005a1a +.set CYREG_SC1_CLK, 0x40005a1b +.set CYREG_SC1_BST, 0x40005a1c +.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d +.set CYREG_SC2_SW0, 0x40005a20 +.set CYREG_SC2_SW2, 0x40005a22 +.set CYREG_SC2_SW3, 0x40005a23 +.set CYREG_SC2_SW4, 0x40005a24 +.set CYREG_SC2_SW6, 0x40005a26 +.set CYREG_SC2_SW7, 0x40005a27 +.set CYREG_SC2_SW8, 0x40005a28 +.set CYREG_SC2_SW10, 0x40005a2a +.set CYREG_SC2_CLK, 0x40005a2b +.set CYREG_SC2_BST, 0x40005a2c +.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d +.set CYREG_SC3_SW0, 0x40005a30 +.set CYREG_SC3_SW2, 0x40005a32 +.set CYREG_SC3_SW3, 0x40005a33 +.set CYREG_SC3_SW4, 0x40005a34 +.set CYREG_SC3_SW6, 0x40005a36 +.set CYREG_SC3_SW7, 0x40005a37 +.set CYREG_SC3_SW8, 0x40005a38 +.set CYREG_SC3_SW10, 0x40005a3a +.set CYREG_SC3_CLK, 0x40005a3b +.set CYREG_SC3_BST, 0x40005a3c +.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 +.set CYREG_DAC0_SW0, 0x40005a80 +.set CYREG_DAC0_SW2, 0x40005a82 +.set CYREG_DAC0_SW3, 0x40005a83 +.set CYREG_DAC0_SW4, 0x40005a84 +.set CYREG_DAC0_STROBE, 0x40005a87 +.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 +.set CYREG_DAC1_SW0, 0x40005a88 +.set CYREG_DAC1_SW2, 0x40005a8a +.set CYREG_DAC1_SW3, 0x40005a8b +.set CYREG_DAC1_SW4, 0x40005a8c +.set CYREG_DAC1_STROBE, 0x40005a8f +.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 +.set CYREG_DAC2_SW0, 0x40005a90 +.set CYREG_DAC2_SW2, 0x40005a92 +.set CYREG_DAC2_SW3, 0x40005a93 +.set CYREG_DAC2_SW4, 0x40005a94 +.set CYREG_DAC2_STROBE, 0x40005a97 +.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 +.set CYREG_DAC3_SW0, 0x40005a98 +.set CYREG_DAC3_SW2, 0x40005a9a +.set CYREG_DAC3_SW3, 0x40005a9b +.set CYREG_DAC3_SW4, 0x40005a9c +.set CYREG_DAC3_STROBE, 0x40005a9f +.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 +.set CYREG_CMP0_SW0, 0x40005ac0 +.set CYREG_CMP0_SW2, 0x40005ac2 +.set CYREG_CMP0_SW3, 0x40005ac3 +.set CYREG_CMP0_SW4, 0x40005ac4 +.set CYREG_CMP0_SW6, 0x40005ac6 +.set CYREG_CMP0_CLK, 0x40005ac7 +.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 +.set CYREG_CMP1_SW0, 0x40005ac8 +.set CYREG_CMP1_SW2, 0x40005aca +.set CYREG_CMP1_SW3, 0x40005acb +.set CYREG_CMP1_SW4, 0x40005acc +.set CYREG_CMP1_SW6, 0x40005ace +.set CYREG_CMP1_CLK, 0x40005acf +.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 +.set CYREG_CMP2_SW0, 0x40005ad0 +.set CYREG_CMP2_SW2, 0x40005ad2 +.set CYREG_CMP2_SW3, 0x40005ad3 +.set CYREG_CMP2_SW4, 0x40005ad4 +.set CYREG_CMP2_SW6, 0x40005ad6 +.set CYREG_CMP2_CLK, 0x40005ad7 +.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 +.set CYREG_CMP3_SW0, 0x40005ad8 +.set CYREG_CMP3_SW2, 0x40005ada +.set CYREG_CMP3_SW3, 0x40005adb +.set CYREG_CMP3_SW4, 0x40005adc +.set CYREG_CMP3_SW6, 0x40005ade +.set CYREG_CMP3_CLK, 0x40005adf +.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 +.set CYREG_DSM0_SW0, 0x40005b00 +.set CYREG_DSM0_SW2, 0x40005b02 +.set CYREG_DSM0_SW3, 0x40005b03 +.set CYREG_DSM0_SW4, 0x40005b04 +.set CYREG_DSM0_SW6, 0x40005b06 +.set CYREG_DSM0_CLK, 0x40005b07 +.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 +.set CYREG_SAR0_SW0, 0x40005b20 +.set CYREG_SAR0_SW2, 0x40005b22 +.set CYREG_SAR0_SW3, 0x40005b23 +.set CYREG_SAR0_SW4, 0x40005b24 +.set CYREG_SAR0_SW6, 0x40005b26 +.set CYREG_SAR0_CLK, 0x40005b27 +.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 +.set CYREG_SAR1_SW0, 0x40005b28 +.set CYREG_SAR1_SW2, 0x40005b2a +.set CYREG_SAR1_SW3, 0x40005b2b +.set CYREG_SAR1_SW4, 0x40005b2c +.set CYREG_SAR1_SW6, 0x40005b2e +.set CYREG_SAR1_CLK, 0x40005b2f +.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_MX, 0x40005b40 +.set CYREG_OPAMP0_SW, 0x40005b41 +.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_MX, 0x40005b42 +.set CYREG_OPAMP1_SW, 0x40005b43 +.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_MX, 0x40005b44 +.set CYREG_OPAMP2_SW, 0x40005b45 +.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_MX, 0x40005b46 +.set CYREG_OPAMP3_SW, 0x40005b47 +.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 +.set CYREG_LCDDAC_SW0, 0x40005b50 +.set CYREG_LCDDAC_SW1, 0x40005b51 +.set CYREG_LCDDAC_SW2, 0x40005b52 +.set CYREG_LCDDAC_SW3, 0x40005b53 +.set CYREG_LCDDAC_SW4, 0x40005b54 +.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 +.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 +.set CYREG_SC_MISC, 0x40005b56 +.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 +.set CYREG_BUS_SW0, 0x40005b58 +.set CYREG_BUS_SW2, 0x40005b5a +.set CYREG_BUS_SW3, 0x40005b5b +.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 +.set CYREG_DFT_CR0, 0x40005b5c +.set CYREG_DFT_CR1, 0x40005b5d +.set CYREG_DFT_CR2, 0x40005b5e +.set CYREG_DFT_CR3, 0x40005b5f +.set CYREG_DFT_CR4, 0x40005b60 +.set CYREG_DFT_CR5, 0x40005b61 +.set CYDEV_ANAIF_WRK_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_SIZE, 0x00000029 +.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 +.set CYREG_DAC0_D, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 +.set CYREG_DAC1_D, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 +.set CYREG_DAC2_D, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 +.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 +.set CYREG_DAC3_D, 0x40005b83 +.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 +.set CYREG_DSM0_OUT0, 0x40005b88 +.set CYREG_DSM0_OUT1, 0x40005b89 +.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 +.set CYREG_LUT_SR, 0x40005b90 +.set CYREG_LUT_WRK1, 0x40005b91 +.set CYREG_LUT_MSK, 0x40005b92 +.set CYREG_LUT_CLK, 0x40005b93 +.set CYREG_LUT_CPTR, 0x40005b94 +.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 +.set CYREG_CMP_WRK, 0x40005b96 +.set CYREG_CMP_TST, 0x40005b97 +.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 +.set CYREG_SC_SR, 0x40005b98 +.set CYREG_SC_WRK1, 0x40005b99 +.set CYREG_SC_MSK, 0x40005b9a +.set CYREG_SC_CMPINV, 0x40005b9b +.set CYREG_SC_CPTR, 0x40005b9c +.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 +.set CYREG_SAR0_WRK0, 0x40005ba0 +.set CYREG_SAR0_WRK1, 0x40005ba1 +.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 +.set CYREG_SAR1_WRK0, 0x40005ba2 +.set CYREG_SAR1_WRK1, 0x40005ba3 +.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 +.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 +.set CYREG_ANAIF_WRK_SARS_SOF, 0x40005ba8 +.set CYDEV_USB_BASE, 0x40006000 +.set CYDEV_USB_SIZE, 0x00000300 +.set CYREG_USB_EP0_DR0, 0x40006000 +.set CYREG_USB_EP0_DR1, 0x40006001 +.set CYREG_USB_EP0_DR2, 0x40006002 +.set CYREG_USB_EP0_DR3, 0x40006003 +.set CYREG_USB_EP0_DR4, 0x40006004 +.set CYREG_USB_EP0_DR5, 0x40006005 +.set CYREG_USB_EP0_DR6, 0x40006006 +.set CYREG_USB_EP0_DR7, 0x40006007 +.set CYREG_USB_CR0, 0x40006008 +.set CYREG_USB_CR1, 0x40006009 +.set CYREG_USB_SIE_EP_INT_EN, 0x4000600a +.set CYREG_USB_SIE_EP_INT_SR, 0x4000600b +.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c +.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP1_CNT0, 0x4000600c +.set CYREG_USB_SIE_EP1_CNT1, 0x4000600d +.set CYREG_USB_SIE_EP1_CR0, 0x4000600e +.set CYREG_USB_USBIO_CR0, 0x40006010 +.set CYREG_USB_USBIO_CR1, 0x40006012 +.set CYREG_USB_DYN_RECONFIG, 0x40006014 +.set CYREG_USB_SOF0, 0x40006018 +.set CYREG_USB_SOF1, 0x40006019 +.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c +.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP2_CNT0, 0x4000601c +.set CYREG_USB_SIE_EP2_CNT1, 0x4000601d +.set CYREG_USB_SIE_EP2_CR0, 0x4000601e +.set CYREG_USB_EP0_CR, 0x40006028 +.set CYREG_USB_EP0_CNT, 0x40006029 +.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c +.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP3_CNT0, 0x4000602c +.set CYREG_USB_SIE_EP3_CNT1, 0x4000602d +.set CYREG_USB_SIE_EP3_CR0, 0x4000602e +.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c +.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP4_CNT0, 0x4000603c +.set CYREG_USB_SIE_EP4_CNT1, 0x4000603d +.set CYREG_USB_SIE_EP4_CR0, 0x4000603e +.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c +.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP5_CNT0, 0x4000604c +.set CYREG_USB_SIE_EP5_CNT1, 0x4000604d +.set CYREG_USB_SIE_EP5_CR0, 0x4000604e +.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c +.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP6_CNT0, 0x4000605c +.set CYREG_USB_SIE_EP6_CNT1, 0x4000605d +.set CYREG_USB_SIE_EP6_CR0, 0x4000605e +.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c +.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP7_CNT0, 0x4000606c +.set CYREG_USB_SIE_EP7_CNT1, 0x4000606d +.set CYREG_USB_SIE_EP7_CR0, 0x4000606e +.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c +.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP8_CNT0, 0x4000607c +.set CYREG_USB_SIE_EP8_CNT1, 0x4000607d +.set CYREG_USB_SIE_EP8_CR0, 0x4000607e +.set CYDEV_USB_ARB_EP1_BASE, 0x40006080 +.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP1_CFG, 0x40006080 +.set CYREG_USB_ARB_EP1_INT_EN, 0x40006081 +.set CYREG_USB_ARB_EP1_SR, 0x40006082 +.set CYDEV_USB_ARB_RW1_BASE, 0x40006084 +.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW1_WA, 0x40006084 +.set CYREG_USB_ARB_RW1_WA_MSB, 0x40006085 +.set CYREG_USB_ARB_RW1_RA, 0x40006086 +.set CYREG_USB_ARB_RW1_RA_MSB, 0x40006087 +.set CYREG_USB_ARB_RW1_DR, 0x40006088 +.set CYREG_USB_BUF_SIZE, 0x4000608c +.set CYREG_USB_EP_ACTIVE, 0x4000608e +.set CYREG_USB_EP_TYPE, 0x4000608f +.set CYDEV_USB_ARB_EP2_BASE, 0x40006090 +.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP2_CFG, 0x40006090 +.set CYREG_USB_ARB_EP2_INT_EN, 0x40006091 +.set CYREG_USB_ARB_EP2_SR, 0x40006092 +.set CYDEV_USB_ARB_RW2_BASE, 0x40006094 +.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW2_WA, 0x40006094 +.set CYREG_USB_ARB_RW2_WA_MSB, 0x40006095 +.set CYREG_USB_ARB_RW2_RA, 0x40006096 +.set CYREG_USB_ARB_RW2_RA_MSB, 0x40006097 +.set CYREG_USB_ARB_RW2_DR, 0x40006098 +.set CYREG_USB_ARB_CFG, 0x4000609c +.set CYREG_USB_USB_CLK_EN, 0x4000609d +.set CYREG_USB_ARB_INT_EN, 0x4000609e +.set CYREG_USB_ARB_INT_SR, 0x4000609f +.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 +.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP3_CFG, 0x400060a0 +.set CYREG_USB_ARB_EP3_INT_EN, 0x400060a1 +.set CYREG_USB_ARB_EP3_SR, 0x400060a2 +.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 +.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW3_WA, 0x400060a4 +.set CYREG_USB_ARB_RW3_WA_MSB, 0x400060a5 +.set CYREG_USB_ARB_RW3_RA, 0x400060a6 +.set CYREG_USB_ARB_RW3_RA_MSB, 0x400060a7 +.set CYREG_USB_ARB_RW3_DR, 0x400060a8 +.set CYREG_USB_CWA, 0x400060ac +.set CYREG_USB_CWA_MSB, 0x400060ad +.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 +.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP4_CFG, 0x400060b0 +.set CYREG_USB_ARB_EP4_INT_EN, 0x400060b1 +.set CYREG_USB_ARB_EP4_SR, 0x400060b2 +.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 +.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW4_WA, 0x400060b4 +.set CYREG_USB_ARB_RW4_WA_MSB, 0x400060b5 +.set CYREG_USB_ARB_RW4_RA, 0x400060b6 +.set CYREG_USB_ARB_RW4_RA_MSB, 0x400060b7 +.set CYREG_USB_ARB_RW4_DR, 0x400060b8 +.set CYREG_USB_DMA_THRES, 0x400060bc +.set CYREG_USB_DMA_THRES_MSB, 0x400060bd +.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 +.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP5_CFG, 0x400060c0 +.set CYREG_USB_ARB_EP5_INT_EN, 0x400060c1 +.set CYREG_USB_ARB_EP5_SR, 0x400060c2 +.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 +.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW5_WA, 0x400060c4 +.set CYREG_USB_ARB_RW5_WA_MSB, 0x400060c5 +.set CYREG_USB_ARB_RW5_RA, 0x400060c6 +.set CYREG_USB_ARB_RW5_RA_MSB, 0x400060c7 +.set CYREG_USB_ARB_RW5_DR, 0x400060c8 +.set CYREG_USB_BUS_RST_CNT, 0x400060cc +.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 +.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP6_CFG, 0x400060d0 +.set CYREG_USB_ARB_EP6_INT_EN, 0x400060d1 +.set CYREG_USB_ARB_EP6_SR, 0x400060d2 +.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 +.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW6_WA, 0x400060d4 +.set CYREG_USB_ARB_RW6_WA_MSB, 0x400060d5 +.set CYREG_USB_ARB_RW6_RA, 0x400060d6 +.set CYREG_USB_ARB_RW6_RA_MSB, 0x400060d7 +.set CYREG_USB_ARB_RW6_DR, 0x400060d8 +.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 +.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP7_CFG, 0x400060e0 +.set CYREG_USB_ARB_EP7_INT_EN, 0x400060e1 +.set CYREG_USB_ARB_EP7_SR, 0x400060e2 +.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 +.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW7_WA, 0x400060e4 +.set CYREG_USB_ARB_RW7_WA_MSB, 0x400060e5 +.set CYREG_USB_ARB_RW7_RA, 0x400060e6 +.set CYREG_USB_ARB_RW7_RA_MSB, 0x400060e7 +.set CYREG_USB_ARB_RW7_DR, 0x400060e8 +.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 +.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP8_CFG, 0x400060f0 +.set CYREG_USB_ARB_EP8_INT_EN, 0x400060f1 +.set CYREG_USB_ARB_EP8_SR, 0x400060f2 +.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 +.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW8_WA, 0x400060f4 +.set CYREG_USB_ARB_RW8_WA_MSB, 0x400060f5 +.set CYREG_USB_ARB_RW8_RA, 0x400060f6 +.set CYREG_USB_ARB_RW8_RA_MSB, 0x400060f7 +.set CYREG_USB_ARB_RW8_DR, 0x400060f8 +.set CYDEV_USB_MEM_BASE, 0x40006100 +.set CYDEV_USB_MEM_SIZE, 0x00000200 +.set CYREG_USB_MEM_DATA_MBASE, 0x40006100 +.set CYREG_USB_MEM_DATA_MSIZE, 0x00000200 +.set CYDEV_UWRK_BASE, 0x40006400 +.set CYDEV_UWRK_SIZE, 0x00000b60 +.set CYDEV_UWRK_UWRK8_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 +.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 +.set CYREG_B0_UDB00_A0, 0x40006400 +.set CYREG_B0_UDB01_A0, 0x40006401 +.set CYREG_B0_UDB02_A0, 0x40006402 +.set CYREG_B0_UDB03_A0, 0x40006403 +.set CYREG_B0_UDB04_A0, 0x40006404 +.set CYREG_B0_UDB05_A0, 0x40006405 +.set CYREG_B0_UDB06_A0, 0x40006406 +.set CYREG_B0_UDB07_A0, 0x40006407 +.set CYREG_B0_UDB08_A0, 0x40006408 +.set CYREG_B0_UDB09_A0, 0x40006409 +.set CYREG_B0_UDB10_A0, 0x4000640a +.set CYREG_B0_UDB11_A0, 0x4000640b +.set CYREG_B0_UDB12_A0, 0x4000640c +.set CYREG_B0_UDB13_A0, 0x4000640d +.set CYREG_B0_UDB14_A0, 0x4000640e +.set CYREG_B0_UDB15_A0, 0x4000640f +.set CYREG_B0_UDB00_A1, 0x40006410 +.set CYREG_B0_UDB01_A1, 0x40006411 +.set CYREG_B0_UDB02_A1, 0x40006412 +.set CYREG_B0_UDB03_A1, 0x40006413 +.set CYREG_B0_UDB04_A1, 0x40006414 +.set CYREG_B0_UDB05_A1, 0x40006415 +.set CYREG_B0_UDB06_A1, 0x40006416 +.set CYREG_B0_UDB07_A1, 0x40006417 +.set CYREG_B0_UDB08_A1, 0x40006418 +.set CYREG_B0_UDB09_A1, 0x40006419 +.set CYREG_B0_UDB10_A1, 0x4000641a +.set CYREG_B0_UDB11_A1, 0x4000641b +.set CYREG_B0_UDB12_A1, 0x4000641c +.set CYREG_B0_UDB13_A1, 0x4000641d +.set CYREG_B0_UDB14_A1, 0x4000641e +.set CYREG_B0_UDB15_A1, 0x4000641f +.set CYREG_B0_UDB00_D0, 0x40006420 +.set CYREG_B0_UDB01_D0, 0x40006421 +.set CYREG_B0_UDB02_D0, 0x40006422 +.set CYREG_B0_UDB03_D0, 0x40006423 +.set CYREG_B0_UDB04_D0, 0x40006424 +.set CYREG_B0_UDB05_D0, 0x40006425 +.set CYREG_B0_UDB06_D0, 0x40006426 +.set CYREG_B0_UDB07_D0, 0x40006427 +.set CYREG_B0_UDB08_D0, 0x40006428 +.set CYREG_B0_UDB09_D0, 0x40006429 +.set CYREG_B0_UDB10_D0, 0x4000642a +.set CYREG_B0_UDB11_D0, 0x4000642b +.set CYREG_B0_UDB12_D0, 0x4000642c +.set CYREG_B0_UDB13_D0, 0x4000642d +.set CYREG_B0_UDB14_D0, 0x4000642e +.set CYREG_B0_UDB15_D0, 0x4000642f +.set CYREG_B0_UDB00_D1, 0x40006430 +.set CYREG_B0_UDB01_D1, 0x40006431 +.set CYREG_B0_UDB02_D1, 0x40006432 +.set CYREG_B0_UDB03_D1, 0x40006433 +.set CYREG_B0_UDB04_D1, 0x40006434 +.set CYREG_B0_UDB05_D1, 0x40006435 +.set CYREG_B0_UDB06_D1, 0x40006436 +.set CYREG_B0_UDB07_D1, 0x40006437 +.set CYREG_B0_UDB08_D1, 0x40006438 +.set CYREG_B0_UDB09_D1, 0x40006439 +.set CYREG_B0_UDB10_D1, 0x4000643a +.set CYREG_B0_UDB11_D1, 0x4000643b +.set CYREG_B0_UDB12_D1, 0x4000643c +.set CYREG_B0_UDB13_D1, 0x4000643d +.set CYREG_B0_UDB14_D1, 0x4000643e +.set CYREG_B0_UDB15_D1, 0x4000643f +.set CYREG_B0_UDB00_F0, 0x40006440 +.set CYREG_B0_UDB01_F0, 0x40006441 +.set CYREG_B0_UDB02_F0, 0x40006442 +.set CYREG_B0_UDB03_F0, 0x40006443 +.set CYREG_B0_UDB04_F0, 0x40006444 +.set CYREG_B0_UDB05_F0, 0x40006445 +.set CYREG_B0_UDB06_F0, 0x40006446 +.set CYREG_B0_UDB07_F0, 0x40006447 +.set CYREG_B0_UDB08_F0, 0x40006448 +.set CYREG_B0_UDB09_F0, 0x40006449 +.set CYREG_B0_UDB10_F0, 0x4000644a +.set CYREG_B0_UDB11_F0, 0x4000644b +.set CYREG_B0_UDB12_F0, 0x4000644c +.set CYREG_B0_UDB13_F0, 0x4000644d +.set CYREG_B0_UDB14_F0, 0x4000644e +.set CYREG_B0_UDB15_F0, 0x4000644f +.set CYREG_B0_UDB00_F1, 0x40006450 +.set CYREG_B0_UDB01_F1, 0x40006451 +.set CYREG_B0_UDB02_F1, 0x40006452 +.set CYREG_B0_UDB03_F1, 0x40006453 +.set CYREG_B0_UDB04_F1, 0x40006454 +.set CYREG_B0_UDB05_F1, 0x40006455 +.set CYREG_B0_UDB06_F1, 0x40006456 +.set CYREG_B0_UDB07_F1, 0x40006457 +.set CYREG_B0_UDB08_F1, 0x40006458 +.set CYREG_B0_UDB09_F1, 0x40006459 +.set CYREG_B0_UDB10_F1, 0x4000645a +.set CYREG_B0_UDB11_F1, 0x4000645b +.set CYREG_B0_UDB12_F1, 0x4000645c +.set CYREG_B0_UDB13_F1, 0x4000645d +.set CYREG_B0_UDB14_F1, 0x4000645e +.set CYREG_B0_UDB15_F1, 0x4000645f +.set CYREG_B0_UDB00_ST, 0x40006460 +.set CYREG_B0_UDB01_ST, 0x40006461 +.set CYREG_B0_UDB02_ST, 0x40006462 +.set CYREG_B0_UDB03_ST, 0x40006463 +.set CYREG_B0_UDB04_ST, 0x40006464 +.set CYREG_B0_UDB05_ST, 0x40006465 +.set CYREG_B0_UDB06_ST, 0x40006466 +.set CYREG_B0_UDB07_ST, 0x40006467 +.set CYREG_B0_UDB08_ST, 0x40006468 +.set CYREG_B0_UDB09_ST, 0x40006469 +.set CYREG_B0_UDB10_ST, 0x4000646a +.set CYREG_B0_UDB11_ST, 0x4000646b +.set CYREG_B0_UDB12_ST, 0x4000646c +.set CYREG_B0_UDB13_ST, 0x4000646d +.set CYREG_B0_UDB14_ST, 0x4000646e +.set CYREG_B0_UDB15_ST, 0x4000646f +.set CYREG_B0_UDB00_CTL, 0x40006470 +.set CYREG_B0_UDB01_CTL, 0x40006471 +.set CYREG_B0_UDB02_CTL, 0x40006472 +.set CYREG_B0_UDB03_CTL, 0x40006473 +.set CYREG_B0_UDB04_CTL, 0x40006474 +.set CYREG_B0_UDB05_CTL, 0x40006475 +.set CYREG_B0_UDB06_CTL, 0x40006476 +.set CYREG_B0_UDB07_CTL, 0x40006477 +.set CYREG_B0_UDB08_CTL, 0x40006478 +.set CYREG_B0_UDB09_CTL, 0x40006479 +.set CYREG_B0_UDB10_CTL, 0x4000647a +.set CYREG_B0_UDB11_CTL, 0x4000647b +.set CYREG_B0_UDB12_CTL, 0x4000647c +.set CYREG_B0_UDB13_CTL, 0x4000647d +.set CYREG_B0_UDB14_CTL, 0x4000647e +.set CYREG_B0_UDB15_CTL, 0x4000647f +.set CYREG_B0_UDB00_MSK, 0x40006480 +.set CYREG_B0_UDB01_MSK, 0x40006481 +.set CYREG_B0_UDB02_MSK, 0x40006482 +.set CYREG_B0_UDB03_MSK, 0x40006483 +.set CYREG_B0_UDB04_MSK, 0x40006484 +.set CYREG_B0_UDB05_MSK, 0x40006485 +.set CYREG_B0_UDB06_MSK, 0x40006486 +.set CYREG_B0_UDB07_MSK, 0x40006487 +.set CYREG_B0_UDB08_MSK, 0x40006488 +.set CYREG_B0_UDB09_MSK, 0x40006489 +.set CYREG_B0_UDB10_MSK, 0x4000648a +.set CYREG_B0_UDB11_MSK, 0x4000648b +.set CYREG_B0_UDB12_MSK, 0x4000648c +.set CYREG_B0_UDB13_MSK, 0x4000648d +.set CYREG_B0_UDB14_MSK, 0x4000648e +.set CYREG_B0_UDB15_MSK, 0x4000648f +.set CYREG_B0_UDB00_ACTL, 0x40006490 +.set CYREG_B0_UDB01_ACTL, 0x40006491 +.set CYREG_B0_UDB02_ACTL, 0x40006492 +.set CYREG_B0_UDB03_ACTL, 0x40006493 +.set CYREG_B0_UDB04_ACTL, 0x40006494 +.set CYREG_B0_UDB05_ACTL, 0x40006495 +.set CYREG_B0_UDB06_ACTL, 0x40006496 +.set CYREG_B0_UDB07_ACTL, 0x40006497 +.set CYREG_B0_UDB08_ACTL, 0x40006498 +.set CYREG_B0_UDB09_ACTL, 0x40006499 +.set CYREG_B0_UDB10_ACTL, 0x4000649a +.set CYREG_B0_UDB11_ACTL, 0x4000649b +.set CYREG_B0_UDB12_ACTL, 0x4000649c +.set CYREG_B0_UDB13_ACTL, 0x4000649d +.set CYREG_B0_UDB14_ACTL, 0x4000649e +.set CYREG_B0_UDB15_ACTL, 0x4000649f +.set CYREG_B0_UDB00_MC, 0x400064a0 +.set CYREG_B0_UDB01_MC, 0x400064a1 +.set CYREG_B0_UDB02_MC, 0x400064a2 +.set CYREG_B0_UDB03_MC, 0x400064a3 +.set CYREG_B0_UDB04_MC, 0x400064a4 +.set CYREG_B0_UDB05_MC, 0x400064a5 +.set CYREG_B0_UDB06_MC, 0x400064a6 +.set CYREG_B0_UDB07_MC, 0x400064a7 +.set CYREG_B0_UDB08_MC, 0x400064a8 +.set CYREG_B0_UDB09_MC, 0x400064a9 +.set CYREG_B0_UDB10_MC, 0x400064aa +.set CYREG_B0_UDB11_MC, 0x400064ab +.set CYREG_B0_UDB12_MC, 0x400064ac +.set CYREG_B0_UDB13_MC, 0x400064ad +.set CYREG_B0_UDB14_MC, 0x400064ae +.set CYREG_B0_UDB15_MC, 0x400064af +.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 +.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 +.set CYREG_B1_UDB04_A0, 0x40006504 +.set CYREG_B1_UDB05_A0, 0x40006505 +.set CYREG_B1_UDB06_A0, 0x40006506 +.set CYREG_B1_UDB07_A0, 0x40006507 +.set CYREG_B1_UDB08_A0, 0x40006508 +.set CYREG_B1_UDB09_A0, 0x40006509 +.set CYREG_B1_UDB10_A0, 0x4000650a +.set CYREG_B1_UDB11_A0, 0x4000650b +.set CYREG_B1_UDB04_A1, 0x40006514 +.set CYREG_B1_UDB05_A1, 0x40006515 +.set CYREG_B1_UDB06_A1, 0x40006516 +.set CYREG_B1_UDB07_A1, 0x40006517 +.set CYREG_B1_UDB08_A1, 0x40006518 +.set CYREG_B1_UDB09_A1, 0x40006519 +.set CYREG_B1_UDB10_A1, 0x4000651a +.set CYREG_B1_UDB11_A1, 0x4000651b +.set CYREG_B1_UDB04_D0, 0x40006524 +.set CYREG_B1_UDB05_D0, 0x40006525 +.set CYREG_B1_UDB06_D0, 0x40006526 +.set CYREG_B1_UDB07_D0, 0x40006527 +.set CYREG_B1_UDB08_D0, 0x40006528 +.set CYREG_B1_UDB09_D0, 0x40006529 +.set CYREG_B1_UDB10_D0, 0x4000652a +.set CYREG_B1_UDB11_D0, 0x4000652b +.set CYREG_B1_UDB04_D1, 0x40006534 +.set CYREG_B1_UDB05_D1, 0x40006535 +.set CYREG_B1_UDB06_D1, 0x40006536 +.set CYREG_B1_UDB07_D1, 0x40006537 +.set CYREG_B1_UDB08_D1, 0x40006538 +.set CYREG_B1_UDB09_D1, 0x40006539 +.set CYREG_B1_UDB10_D1, 0x4000653a +.set CYREG_B1_UDB11_D1, 0x4000653b +.set CYREG_B1_UDB04_F0, 0x40006544 +.set CYREG_B1_UDB05_F0, 0x40006545 +.set CYREG_B1_UDB06_F0, 0x40006546 +.set CYREG_B1_UDB07_F0, 0x40006547 +.set CYREG_B1_UDB08_F0, 0x40006548 +.set CYREG_B1_UDB09_F0, 0x40006549 +.set CYREG_B1_UDB10_F0, 0x4000654a +.set CYREG_B1_UDB11_F0, 0x4000654b +.set CYREG_B1_UDB04_F1, 0x40006554 +.set CYREG_B1_UDB05_F1, 0x40006555 +.set CYREG_B1_UDB06_F1, 0x40006556 +.set CYREG_B1_UDB07_F1, 0x40006557 +.set CYREG_B1_UDB08_F1, 0x40006558 +.set CYREG_B1_UDB09_F1, 0x40006559 +.set CYREG_B1_UDB10_F1, 0x4000655a +.set CYREG_B1_UDB11_F1, 0x4000655b +.set CYREG_B1_UDB04_ST, 0x40006564 +.set CYREG_B1_UDB05_ST, 0x40006565 +.set CYREG_B1_UDB06_ST, 0x40006566 +.set CYREG_B1_UDB07_ST, 0x40006567 +.set CYREG_B1_UDB08_ST, 0x40006568 +.set CYREG_B1_UDB09_ST, 0x40006569 +.set CYREG_B1_UDB10_ST, 0x4000656a +.set CYREG_B1_UDB11_ST, 0x4000656b +.set CYREG_B1_UDB04_CTL, 0x40006574 +.set CYREG_B1_UDB05_CTL, 0x40006575 +.set CYREG_B1_UDB06_CTL, 0x40006576 +.set CYREG_B1_UDB07_CTL, 0x40006577 +.set CYREG_B1_UDB08_CTL, 0x40006578 +.set CYREG_B1_UDB09_CTL, 0x40006579 +.set CYREG_B1_UDB10_CTL, 0x4000657a +.set CYREG_B1_UDB11_CTL, 0x4000657b +.set CYREG_B1_UDB04_MSK, 0x40006584 +.set CYREG_B1_UDB05_MSK, 0x40006585 +.set CYREG_B1_UDB06_MSK, 0x40006586 +.set CYREG_B1_UDB07_MSK, 0x40006587 +.set CYREG_B1_UDB08_MSK, 0x40006588 +.set CYREG_B1_UDB09_MSK, 0x40006589 +.set CYREG_B1_UDB10_MSK, 0x4000658a +.set CYREG_B1_UDB11_MSK, 0x4000658b +.set CYREG_B1_UDB04_ACTL, 0x40006594 +.set CYREG_B1_UDB05_ACTL, 0x40006595 +.set CYREG_B1_UDB06_ACTL, 0x40006596 +.set CYREG_B1_UDB07_ACTL, 0x40006597 +.set CYREG_B1_UDB08_ACTL, 0x40006598 +.set CYREG_B1_UDB09_ACTL, 0x40006599 +.set CYREG_B1_UDB10_ACTL, 0x4000659a +.set CYREG_B1_UDB11_ACTL, 0x4000659b +.set CYREG_B1_UDB04_MC, 0x400065a4 +.set CYREG_B1_UDB05_MC, 0x400065a5 +.set CYREG_B1_UDB06_MC, 0x400065a6 +.set CYREG_B1_UDB07_MC, 0x400065a7 +.set CYREG_B1_UDB08_MC, 0x400065a8 +.set CYREG_B1_UDB09_MC, 0x400065a9 +.set CYREG_B1_UDB10_MC, 0x400065aa +.set CYREG_B1_UDB11_MC, 0x400065ab +.set CYDEV_UWRK_UWRK16_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 +.set CYREG_B0_UDB00_A0_A1, 0x40006800 +.set CYREG_B0_UDB01_A0_A1, 0x40006802 +.set CYREG_B0_UDB02_A0_A1, 0x40006804 +.set CYREG_B0_UDB03_A0_A1, 0x40006806 +.set CYREG_B0_UDB04_A0_A1, 0x40006808 +.set CYREG_B0_UDB05_A0_A1, 0x4000680a +.set CYREG_B0_UDB06_A0_A1, 0x4000680c +.set CYREG_B0_UDB07_A0_A1, 0x4000680e +.set CYREG_B0_UDB08_A0_A1, 0x40006810 +.set CYREG_B0_UDB09_A0_A1, 0x40006812 +.set CYREG_B0_UDB10_A0_A1, 0x40006814 +.set CYREG_B0_UDB11_A0_A1, 0x40006816 +.set CYREG_B0_UDB12_A0_A1, 0x40006818 +.set CYREG_B0_UDB13_A0_A1, 0x4000681a +.set CYREG_B0_UDB14_A0_A1, 0x4000681c +.set CYREG_B0_UDB15_A0_A1, 0x4000681e +.set CYREG_B0_UDB00_D0_D1, 0x40006840 +.set CYREG_B0_UDB01_D0_D1, 0x40006842 +.set CYREG_B0_UDB02_D0_D1, 0x40006844 +.set CYREG_B0_UDB03_D0_D1, 0x40006846 +.set CYREG_B0_UDB04_D0_D1, 0x40006848 +.set CYREG_B0_UDB05_D0_D1, 0x4000684a +.set CYREG_B0_UDB06_D0_D1, 0x4000684c +.set CYREG_B0_UDB07_D0_D1, 0x4000684e +.set CYREG_B0_UDB08_D0_D1, 0x40006850 +.set CYREG_B0_UDB09_D0_D1, 0x40006852 +.set CYREG_B0_UDB10_D0_D1, 0x40006854 +.set CYREG_B0_UDB11_D0_D1, 0x40006856 +.set CYREG_B0_UDB12_D0_D1, 0x40006858 +.set CYREG_B0_UDB13_D0_D1, 0x4000685a +.set CYREG_B0_UDB14_D0_D1, 0x4000685c +.set CYREG_B0_UDB15_D0_D1, 0x4000685e +.set CYREG_B0_UDB00_F0_F1, 0x40006880 +.set CYREG_B0_UDB01_F0_F1, 0x40006882 +.set CYREG_B0_UDB02_F0_F1, 0x40006884 +.set CYREG_B0_UDB03_F0_F1, 0x40006886 +.set CYREG_B0_UDB04_F0_F1, 0x40006888 +.set CYREG_B0_UDB05_F0_F1, 0x4000688a +.set CYREG_B0_UDB06_F0_F1, 0x4000688c +.set CYREG_B0_UDB07_F0_F1, 0x4000688e +.set CYREG_B0_UDB08_F0_F1, 0x40006890 +.set CYREG_B0_UDB09_F0_F1, 0x40006892 +.set CYREG_B0_UDB10_F0_F1, 0x40006894 +.set CYREG_B0_UDB11_F0_F1, 0x40006896 +.set CYREG_B0_UDB12_F0_F1, 0x40006898 +.set CYREG_B0_UDB13_F0_F1, 0x4000689a +.set CYREG_B0_UDB14_F0_F1, 0x4000689c +.set CYREG_B0_UDB15_F0_F1, 0x4000689e +.set CYREG_B0_UDB00_ST_CTL, 0x400068c0 +.set CYREG_B0_UDB01_ST_CTL, 0x400068c2 +.set CYREG_B0_UDB02_ST_CTL, 0x400068c4 +.set CYREG_B0_UDB03_ST_CTL, 0x400068c6 +.set CYREG_B0_UDB04_ST_CTL, 0x400068c8 +.set CYREG_B0_UDB05_ST_CTL, 0x400068ca +.set CYREG_B0_UDB06_ST_CTL, 0x400068cc +.set CYREG_B0_UDB07_ST_CTL, 0x400068ce +.set CYREG_B0_UDB08_ST_CTL, 0x400068d0 +.set CYREG_B0_UDB09_ST_CTL, 0x400068d2 +.set CYREG_B0_UDB10_ST_CTL, 0x400068d4 +.set CYREG_B0_UDB11_ST_CTL, 0x400068d6 +.set CYREG_B0_UDB12_ST_CTL, 0x400068d8 +.set CYREG_B0_UDB13_ST_CTL, 0x400068da +.set CYREG_B0_UDB14_ST_CTL, 0x400068dc +.set CYREG_B0_UDB15_ST_CTL, 0x400068de +.set CYREG_B0_UDB00_MSK_ACTL, 0x40006900 +.set CYREG_B0_UDB01_MSK_ACTL, 0x40006902 +.set CYREG_B0_UDB02_MSK_ACTL, 0x40006904 +.set CYREG_B0_UDB03_MSK_ACTL, 0x40006906 +.set CYREG_B0_UDB04_MSK_ACTL, 0x40006908 +.set CYREG_B0_UDB05_MSK_ACTL, 0x4000690a +.set CYREG_B0_UDB06_MSK_ACTL, 0x4000690c +.set CYREG_B0_UDB07_MSK_ACTL, 0x4000690e +.set CYREG_B0_UDB08_MSK_ACTL, 0x40006910 +.set CYREG_B0_UDB09_MSK_ACTL, 0x40006912 +.set CYREG_B0_UDB10_MSK_ACTL, 0x40006914 +.set CYREG_B0_UDB11_MSK_ACTL, 0x40006916 +.set CYREG_B0_UDB12_MSK_ACTL, 0x40006918 +.set CYREG_B0_UDB13_MSK_ACTL, 0x4000691a +.set CYREG_B0_UDB14_MSK_ACTL, 0x4000691c +.set CYREG_B0_UDB15_MSK_ACTL, 0x4000691e +.set CYREG_B0_UDB00_MC_00, 0x40006940 +.set CYREG_B0_UDB01_MC_00, 0x40006942 +.set CYREG_B0_UDB02_MC_00, 0x40006944 +.set CYREG_B0_UDB03_MC_00, 0x40006946 +.set CYREG_B0_UDB04_MC_00, 0x40006948 +.set CYREG_B0_UDB05_MC_00, 0x4000694a +.set CYREG_B0_UDB06_MC_00, 0x4000694c +.set CYREG_B0_UDB07_MC_00, 0x4000694e +.set CYREG_B0_UDB08_MC_00, 0x40006950 +.set CYREG_B0_UDB09_MC_00, 0x40006952 +.set CYREG_B0_UDB10_MC_00, 0x40006954 +.set CYREG_B0_UDB11_MC_00, 0x40006956 +.set CYREG_B0_UDB12_MC_00, 0x40006958 +.set CYREG_B0_UDB13_MC_00, 0x4000695a +.set CYREG_B0_UDB14_MC_00, 0x4000695c +.set CYREG_B0_UDB15_MC_00, 0x4000695e +.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 +.set CYREG_B1_UDB04_A0_A1, 0x40006a08 +.set CYREG_B1_UDB05_A0_A1, 0x40006a0a +.set CYREG_B1_UDB06_A0_A1, 0x40006a0c +.set CYREG_B1_UDB07_A0_A1, 0x40006a0e +.set CYREG_B1_UDB08_A0_A1, 0x40006a10 +.set CYREG_B1_UDB09_A0_A1, 0x40006a12 +.set CYREG_B1_UDB10_A0_A1, 0x40006a14 +.set CYREG_B1_UDB11_A0_A1, 0x40006a16 +.set CYREG_B1_UDB04_D0_D1, 0x40006a48 +.set CYREG_B1_UDB05_D0_D1, 0x40006a4a +.set CYREG_B1_UDB06_D0_D1, 0x40006a4c +.set CYREG_B1_UDB07_D0_D1, 0x40006a4e +.set CYREG_B1_UDB08_D0_D1, 0x40006a50 +.set CYREG_B1_UDB09_D0_D1, 0x40006a52 +.set CYREG_B1_UDB10_D0_D1, 0x40006a54 +.set CYREG_B1_UDB11_D0_D1, 0x40006a56 +.set CYREG_B1_UDB04_F0_F1, 0x40006a88 +.set CYREG_B1_UDB05_F0_F1, 0x40006a8a +.set CYREG_B1_UDB06_F0_F1, 0x40006a8c +.set CYREG_B1_UDB07_F0_F1, 0x40006a8e +.set CYREG_B1_UDB08_F0_F1, 0x40006a90 +.set CYREG_B1_UDB09_F0_F1, 0x40006a92 +.set CYREG_B1_UDB10_F0_F1, 0x40006a94 +.set CYREG_B1_UDB11_F0_F1, 0x40006a96 +.set CYREG_B1_UDB04_ST_CTL, 0x40006ac8 +.set CYREG_B1_UDB05_ST_CTL, 0x40006aca +.set CYREG_B1_UDB06_ST_CTL, 0x40006acc +.set CYREG_B1_UDB07_ST_CTL, 0x40006ace +.set CYREG_B1_UDB08_ST_CTL, 0x40006ad0 +.set CYREG_B1_UDB09_ST_CTL, 0x40006ad2 +.set CYREG_B1_UDB10_ST_CTL, 0x40006ad4 +.set CYREG_B1_UDB11_ST_CTL, 0x40006ad6 +.set CYREG_B1_UDB04_MSK_ACTL, 0x40006b08 +.set CYREG_B1_UDB05_MSK_ACTL, 0x40006b0a +.set CYREG_B1_UDB06_MSK_ACTL, 0x40006b0c +.set CYREG_B1_UDB07_MSK_ACTL, 0x40006b0e +.set CYREG_B1_UDB08_MSK_ACTL, 0x40006b10 +.set CYREG_B1_UDB09_MSK_ACTL, 0x40006b12 +.set CYREG_B1_UDB10_MSK_ACTL, 0x40006b14 +.set CYREG_B1_UDB11_MSK_ACTL, 0x40006b16 +.set CYREG_B1_UDB04_MC_00, 0x40006b48 +.set CYREG_B1_UDB05_MC_00, 0x40006b4a +.set CYREG_B1_UDB06_MC_00, 0x40006b4c +.set CYREG_B1_UDB07_MC_00, 0x40006b4e +.set CYREG_B1_UDB08_MC_00, 0x40006b50 +.set CYREG_B1_UDB09_MC_00, 0x40006b52 +.set CYREG_B1_UDB10_MC_00, 0x40006b54 +.set CYREG_B1_UDB11_MC_00, 0x40006b56 +.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e +.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e +.set CYREG_B0_UDB00_01_A0, 0x40006800 +.set CYREG_B0_UDB01_02_A0, 0x40006802 +.set CYREG_B0_UDB02_03_A0, 0x40006804 +.set CYREG_B0_UDB03_04_A0, 0x40006806 +.set CYREG_B0_UDB04_05_A0, 0x40006808 +.set CYREG_B0_UDB05_06_A0, 0x4000680a +.set CYREG_B0_UDB06_07_A0, 0x4000680c +.set CYREG_B0_UDB07_08_A0, 0x4000680e +.set CYREG_B0_UDB08_09_A0, 0x40006810 +.set CYREG_B0_UDB09_10_A0, 0x40006812 +.set CYREG_B0_UDB10_11_A0, 0x40006814 +.set CYREG_B0_UDB11_12_A0, 0x40006816 +.set CYREG_B0_UDB12_13_A0, 0x40006818 +.set CYREG_B0_UDB13_14_A0, 0x4000681a +.set CYREG_B0_UDB14_15_A0, 0x4000681c +.set CYREG_B0_UDB00_01_A1, 0x40006820 +.set CYREG_B0_UDB01_02_A1, 0x40006822 +.set CYREG_B0_UDB02_03_A1, 0x40006824 +.set CYREG_B0_UDB03_04_A1, 0x40006826 +.set CYREG_B0_UDB04_05_A1, 0x40006828 +.set CYREG_B0_UDB05_06_A1, 0x4000682a +.set CYREG_B0_UDB06_07_A1, 0x4000682c +.set CYREG_B0_UDB07_08_A1, 0x4000682e +.set CYREG_B0_UDB08_09_A1, 0x40006830 +.set CYREG_B0_UDB09_10_A1, 0x40006832 +.set CYREG_B0_UDB10_11_A1, 0x40006834 +.set CYREG_B0_UDB11_12_A1, 0x40006836 +.set CYREG_B0_UDB12_13_A1, 0x40006838 +.set CYREG_B0_UDB13_14_A1, 0x4000683a +.set CYREG_B0_UDB14_15_A1, 0x4000683c +.set CYREG_B0_UDB00_01_D0, 0x40006840 +.set CYREG_B0_UDB01_02_D0, 0x40006842 +.set CYREG_B0_UDB02_03_D0, 0x40006844 +.set CYREG_B0_UDB03_04_D0, 0x40006846 +.set CYREG_B0_UDB04_05_D0, 0x40006848 +.set CYREG_B0_UDB05_06_D0, 0x4000684a +.set CYREG_B0_UDB06_07_D0, 0x4000684c +.set CYREG_B0_UDB07_08_D0, 0x4000684e +.set CYREG_B0_UDB08_09_D0, 0x40006850 +.set CYREG_B0_UDB09_10_D0, 0x40006852 +.set CYREG_B0_UDB10_11_D0, 0x40006854 +.set CYREG_B0_UDB11_12_D0, 0x40006856 +.set CYREG_B0_UDB12_13_D0, 0x40006858 +.set CYREG_B0_UDB13_14_D0, 0x4000685a +.set CYREG_B0_UDB14_15_D0, 0x4000685c +.set CYREG_B0_UDB00_01_D1, 0x40006860 +.set CYREG_B0_UDB01_02_D1, 0x40006862 +.set CYREG_B0_UDB02_03_D1, 0x40006864 +.set CYREG_B0_UDB03_04_D1, 0x40006866 +.set CYREG_B0_UDB04_05_D1, 0x40006868 +.set CYREG_B0_UDB05_06_D1, 0x4000686a +.set CYREG_B0_UDB06_07_D1, 0x4000686c +.set CYREG_B0_UDB07_08_D1, 0x4000686e +.set CYREG_B0_UDB08_09_D1, 0x40006870 +.set CYREG_B0_UDB09_10_D1, 0x40006872 +.set CYREG_B0_UDB10_11_D1, 0x40006874 +.set CYREG_B0_UDB11_12_D1, 0x40006876 +.set CYREG_B0_UDB12_13_D1, 0x40006878 +.set CYREG_B0_UDB13_14_D1, 0x4000687a +.set CYREG_B0_UDB14_15_D1, 0x4000687c +.set CYREG_B0_UDB00_01_F0, 0x40006880 +.set CYREG_B0_UDB01_02_F0, 0x40006882 +.set CYREG_B0_UDB02_03_F0, 0x40006884 +.set CYREG_B0_UDB03_04_F0, 0x40006886 +.set CYREG_B0_UDB04_05_F0, 0x40006888 +.set CYREG_B0_UDB05_06_F0, 0x4000688a +.set CYREG_B0_UDB06_07_F0, 0x4000688c +.set CYREG_B0_UDB07_08_F0, 0x4000688e +.set CYREG_B0_UDB08_09_F0, 0x40006890 +.set CYREG_B0_UDB09_10_F0, 0x40006892 +.set CYREG_B0_UDB10_11_F0, 0x40006894 +.set CYREG_B0_UDB11_12_F0, 0x40006896 +.set CYREG_B0_UDB12_13_F0, 0x40006898 +.set CYREG_B0_UDB13_14_F0, 0x4000689a +.set CYREG_B0_UDB14_15_F0, 0x4000689c +.set CYREG_B0_UDB00_01_F1, 0x400068a0 +.set CYREG_B0_UDB01_02_F1, 0x400068a2 +.set CYREG_B0_UDB02_03_F1, 0x400068a4 +.set CYREG_B0_UDB03_04_F1, 0x400068a6 +.set CYREG_B0_UDB04_05_F1, 0x400068a8 +.set CYREG_B0_UDB05_06_F1, 0x400068aa +.set CYREG_B0_UDB06_07_F1, 0x400068ac +.set CYREG_B0_UDB07_08_F1, 0x400068ae +.set CYREG_B0_UDB08_09_F1, 0x400068b0 +.set CYREG_B0_UDB09_10_F1, 0x400068b2 +.set CYREG_B0_UDB10_11_F1, 0x400068b4 +.set CYREG_B0_UDB11_12_F1, 0x400068b6 +.set CYREG_B0_UDB12_13_F1, 0x400068b8 +.set CYREG_B0_UDB13_14_F1, 0x400068ba +.set CYREG_B0_UDB14_15_F1, 0x400068bc +.set CYREG_B0_UDB00_01_ST, 0x400068c0 +.set CYREG_B0_UDB01_02_ST, 0x400068c2 +.set CYREG_B0_UDB02_03_ST, 0x400068c4 +.set CYREG_B0_UDB03_04_ST, 0x400068c6 +.set CYREG_B0_UDB04_05_ST, 0x400068c8 +.set CYREG_B0_UDB05_06_ST, 0x400068ca +.set CYREG_B0_UDB06_07_ST, 0x400068cc +.set CYREG_B0_UDB07_08_ST, 0x400068ce +.set CYREG_B0_UDB08_09_ST, 0x400068d0 +.set CYREG_B0_UDB09_10_ST, 0x400068d2 +.set CYREG_B0_UDB10_11_ST, 0x400068d4 +.set CYREG_B0_UDB11_12_ST, 0x400068d6 +.set CYREG_B0_UDB12_13_ST, 0x400068d8 +.set CYREG_B0_UDB13_14_ST, 0x400068da +.set CYREG_B0_UDB14_15_ST, 0x400068dc +.set CYREG_B0_UDB00_01_CTL, 0x400068e0 +.set CYREG_B0_UDB01_02_CTL, 0x400068e2 +.set CYREG_B0_UDB02_03_CTL, 0x400068e4 +.set CYREG_B0_UDB03_04_CTL, 0x400068e6 +.set CYREG_B0_UDB04_05_CTL, 0x400068e8 +.set CYREG_B0_UDB05_06_CTL, 0x400068ea +.set CYREG_B0_UDB06_07_CTL, 0x400068ec +.set CYREG_B0_UDB07_08_CTL, 0x400068ee +.set CYREG_B0_UDB08_09_CTL, 0x400068f0 +.set CYREG_B0_UDB09_10_CTL, 0x400068f2 +.set CYREG_B0_UDB10_11_CTL, 0x400068f4 +.set CYREG_B0_UDB11_12_CTL, 0x400068f6 +.set CYREG_B0_UDB12_13_CTL, 0x400068f8 +.set CYREG_B0_UDB13_14_CTL, 0x400068fa +.set CYREG_B0_UDB14_15_CTL, 0x400068fc +.set CYREG_B0_UDB00_01_MSK, 0x40006900 +.set CYREG_B0_UDB01_02_MSK, 0x40006902 +.set CYREG_B0_UDB02_03_MSK, 0x40006904 +.set CYREG_B0_UDB03_04_MSK, 0x40006906 +.set CYREG_B0_UDB04_05_MSK, 0x40006908 +.set CYREG_B0_UDB05_06_MSK, 0x4000690a +.set CYREG_B0_UDB06_07_MSK, 0x4000690c +.set CYREG_B0_UDB07_08_MSK, 0x4000690e +.set CYREG_B0_UDB08_09_MSK, 0x40006910 +.set CYREG_B0_UDB09_10_MSK, 0x40006912 +.set CYREG_B0_UDB10_11_MSK, 0x40006914 +.set CYREG_B0_UDB11_12_MSK, 0x40006916 +.set CYREG_B0_UDB12_13_MSK, 0x40006918 +.set CYREG_B0_UDB13_14_MSK, 0x4000691a +.set CYREG_B0_UDB14_15_MSK, 0x4000691c +.set CYREG_B0_UDB00_01_ACTL, 0x40006920 +.set CYREG_B0_UDB01_02_ACTL, 0x40006922 +.set CYREG_B0_UDB02_03_ACTL, 0x40006924 +.set CYREG_B0_UDB03_04_ACTL, 0x40006926 +.set CYREG_B0_UDB04_05_ACTL, 0x40006928 +.set CYREG_B0_UDB05_06_ACTL, 0x4000692a +.set CYREG_B0_UDB06_07_ACTL, 0x4000692c +.set CYREG_B0_UDB07_08_ACTL, 0x4000692e +.set CYREG_B0_UDB08_09_ACTL, 0x40006930 +.set CYREG_B0_UDB09_10_ACTL, 0x40006932 +.set CYREG_B0_UDB10_11_ACTL, 0x40006934 +.set CYREG_B0_UDB11_12_ACTL, 0x40006936 +.set CYREG_B0_UDB12_13_ACTL, 0x40006938 +.set CYREG_B0_UDB13_14_ACTL, 0x4000693a +.set CYREG_B0_UDB14_15_ACTL, 0x4000693c +.set CYREG_B0_UDB00_01_MC, 0x40006940 +.set CYREG_B0_UDB01_02_MC, 0x40006942 +.set CYREG_B0_UDB02_03_MC, 0x40006944 +.set CYREG_B0_UDB03_04_MC, 0x40006946 +.set CYREG_B0_UDB04_05_MC, 0x40006948 +.set CYREG_B0_UDB05_06_MC, 0x4000694a +.set CYREG_B0_UDB06_07_MC, 0x4000694c +.set CYREG_B0_UDB07_08_MC, 0x4000694e +.set CYREG_B0_UDB08_09_MC, 0x40006950 +.set CYREG_B0_UDB09_10_MC, 0x40006952 +.set CYREG_B0_UDB10_11_MC, 0x40006954 +.set CYREG_B0_UDB11_12_MC, 0x40006956 +.set CYREG_B0_UDB12_13_MC, 0x40006958 +.set CYREG_B0_UDB13_14_MC, 0x4000695a +.set CYREG_B0_UDB14_15_MC, 0x4000695c +.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e +.set CYREG_B1_UDB04_05_A0, 0x40006a08 +.set CYREG_B1_UDB05_06_A0, 0x40006a0a +.set CYREG_B1_UDB06_07_A0, 0x40006a0c +.set CYREG_B1_UDB07_08_A0, 0x40006a0e +.set CYREG_B1_UDB08_09_A0, 0x40006a10 +.set CYREG_B1_UDB09_10_A0, 0x40006a12 +.set CYREG_B1_UDB10_11_A0, 0x40006a14 +.set CYREG_B1_UDB11_12_A0, 0x40006a16 +.set CYREG_B1_UDB04_05_A1, 0x40006a28 +.set CYREG_B1_UDB05_06_A1, 0x40006a2a +.set CYREG_B1_UDB06_07_A1, 0x40006a2c +.set CYREG_B1_UDB07_08_A1, 0x40006a2e +.set CYREG_B1_UDB08_09_A1, 0x40006a30 +.set CYREG_B1_UDB09_10_A1, 0x40006a32 +.set CYREG_B1_UDB10_11_A1, 0x40006a34 +.set CYREG_B1_UDB11_12_A1, 0x40006a36 +.set CYREG_B1_UDB04_05_D0, 0x40006a48 +.set CYREG_B1_UDB05_06_D0, 0x40006a4a +.set CYREG_B1_UDB06_07_D0, 0x40006a4c +.set CYREG_B1_UDB07_08_D0, 0x40006a4e +.set CYREG_B1_UDB08_09_D0, 0x40006a50 +.set CYREG_B1_UDB09_10_D0, 0x40006a52 +.set CYREG_B1_UDB10_11_D0, 0x40006a54 +.set CYREG_B1_UDB11_12_D0, 0x40006a56 +.set CYREG_B1_UDB04_05_D1, 0x40006a68 +.set CYREG_B1_UDB05_06_D1, 0x40006a6a +.set CYREG_B1_UDB06_07_D1, 0x40006a6c +.set CYREG_B1_UDB07_08_D1, 0x40006a6e +.set CYREG_B1_UDB08_09_D1, 0x40006a70 +.set CYREG_B1_UDB09_10_D1, 0x40006a72 +.set CYREG_B1_UDB10_11_D1, 0x40006a74 +.set CYREG_B1_UDB11_12_D1, 0x40006a76 +.set CYREG_B1_UDB04_05_F0, 0x40006a88 +.set CYREG_B1_UDB05_06_F0, 0x40006a8a +.set CYREG_B1_UDB06_07_F0, 0x40006a8c +.set CYREG_B1_UDB07_08_F0, 0x40006a8e +.set CYREG_B1_UDB08_09_F0, 0x40006a90 +.set CYREG_B1_UDB09_10_F0, 0x40006a92 +.set CYREG_B1_UDB10_11_F0, 0x40006a94 +.set CYREG_B1_UDB11_12_F0, 0x40006a96 +.set CYREG_B1_UDB04_05_F1, 0x40006aa8 +.set CYREG_B1_UDB05_06_F1, 0x40006aaa +.set CYREG_B1_UDB06_07_F1, 0x40006aac +.set CYREG_B1_UDB07_08_F1, 0x40006aae +.set CYREG_B1_UDB08_09_F1, 0x40006ab0 +.set CYREG_B1_UDB09_10_F1, 0x40006ab2 +.set CYREG_B1_UDB10_11_F1, 0x40006ab4 +.set CYREG_B1_UDB11_12_F1, 0x40006ab6 +.set CYREG_B1_UDB04_05_ST, 0x40006ac8 +.set CYREG_B1_UDB05_06_ST, 0x40006aca +.set CYREG_B1_UDB06_07_ST, 0x40006acc +.set CYREG_B1_UDB07_08_ST, 0x40006ace +.set CYREG_B1_UDB08_09_ST, 0x40006ad0 +.set CYREG_B1_UDB09_10_ST, 0x40006ad2 +.set CYREG_B1_UDB10_11_ST, 0x40006ad4 +.set CYREG_B1_UDB11_12_ST, 0x40006ad6 +.set CYREG_B1_UDB04_05_CTL, 0x40006ae8 +.set CYREG_B1_UDB05_06_CTL, 0x40006aea +.set CYREG_B1_UDB06_07_CTL, 0x40006aec +.set CYREG_B1_UDB07_08_CTL, 0x40006aee +.set CYREG_B1_UDB08_09_CTL, 0x40006af0 +.set CYREG_B1_UDB09_10_CTL, 0x40006af2 +.set CYREG_B1_UDB10_11_CTL, 0x40006af4 +.set CYREG_B1_UDB11_12_CTL, 0x40006af6 +.set CYREG_B1_UDB04_05_MSK, 0x40006b08 +.set CYREG_B1_UDB05_06_MSK, 0x40006b0a +.set CYREG_B1_UDB06_07_MSK, 0x40006b0c +.set CYREG_B1_UDB07_08_MSK, 0x40006b0e +.set CYREG_B1_UDB08_09_MSK, 0x40006b10 +.set CYREG_B1_UDB09_10_MSK, 0x40006b12 +.set CYREG_B1_UDB10_11_MSK, 0x40006b14 +.set CYREG_B1_UDB11_12_MSK, 0x40006b16 +.set CYREG_B1_UDB04_05_ACTL, 0x40006b28 +.set CYREG_B1_UDB05_06_ACTL, 0x40006b2a +.set CYREG_B1_UDB06_07_ACTL, 0x40006b2c +.set CYREG_B1_UDB07_08_ACTL, 0x40006b2e +.set CYREG_B1_UDB08_09_ACTL, 0x40006b30 +.set CYREG_B1_UDB09_10_ACTL, 0x40006b32 +.set CYREG_B1_UDB10_11_ACTL, 0x40006b34 +.set CYREG_B1_UDB11_12_ACTL, 0x40006b36 +.set CYREG_B1_UDB04_05_MC, 0x40006b48 +.set CYREG_B1_UDB05_06_MC, 0x40006b4a +.set CYREG_B1_UDB06_07_MC, 0x40006b4c +.set CYREG_B1_UDB07_08_MC, 0x40006b4e +.set CYREG_B1_UDB08_09_MC, 0x40006b50 +.set CYREG_B1_UDB09_10_MC, 0x40006b52 +.set CYREG_B1_UDB10_11_MC, 0x40006b54 +.set CYREG_B1_UDB11_12_MC, 0x40006b56 +.set CYDEV_PHUB_BASE, 0x40007000 +.set CYDEV_PHUB_SIZE, 0x00000c00 +.set CYREG_PHUB_CFG, 0x40007000 +.set CYREG_PHUB_ERR, 0x40007004 +.set CYREG_PHUB_ERR_ADR, 0x40007008 +.set CYDEV_PHUB_CH0_BASE, 0x40007010 +.set CYDEV_PHUB_CH0_SIZE, 0x0000000c +.set CYREG_PHUB_CH0_BASIC_CFG, 0x40007010 +.set CYREG_PHUB_CH0_ACTION, 0x40007014 +.set CYREG_PHUB_CH0_BASIC_STATUS, 0x40007018 +.set CYDEV_PHUB_CH1_BASE, 0x40007020 +.set CYDEV_PHUB_CH1_SIZE, 0x0000000c +.set CYREG_PHUB_CH1_BASIC_CFG, 0x40007020 +.set CYREG_PHUB_CH1_ACTION, 0x40007024 +.set CYREG_PHUB_CH1_BASIC_STATUS, 0x40007028 +.set CYDEV_PHUB_CH2_BASE, 0x40007030 +.set CYDEV_PHUB_CH2_SIZE, 0x0000000c +.set CYREG_PHUB_CH2_BASIC_CFG, 0x40007030 +.set CYREG_PHUB_CH2_ACTION, 0x40007034 +.set CYREG_PHUB_CH2_BASIC_STATUS, 0x40007038 +.set CYDEV_PHUB_CH3_BASE, 0x40007040 +.set CYDEV_PHUB_CH3_SIZE, 0x0000000c +.set CYREG_PHUB_CH3_BASIC_CFG, 0x40007040 +.set CYREG_PHUB_CH3_ACTION, 0x40007044 +.set CYREG_PHUB_CH3_BASIC_STATUS, 0x40007048 +.set CYDEV_PHUB_CH4_BASE, 0x40007050 +.set CYDEV_PHUB_CH4_SIZE, 0x0000000c +.set CYREG_PHUB_CH4_BASIC_CFG, 0x40007050 +.set CYREG_PHUB_CH4_ACTION, 0x40007054 +.set CYREG_PHUB_CH4_BASIC_STATUS, 0x40007058 +.set CYDEV_PHUB_CH5_BASE, 0x40007060 +.set CYDEV_PHUB_CH5_SIZE, 0x0000000c +.set CYREG_PHUB_CH5_BASIC_CFG, 0x40007060 +.set CYREG_PHUB_CH5_ACTION, 0x40007064 +.set CYREG_PHUB_CH5_BASIC_STATUS, 0x40007068 +.set CYDEV_PHUB_CH6_BASE, 0x40007070 +.set CYDEV_PHUB_CH6_SIZE, 0x0000000c +.set CYREG_PHUB_CH6_BASIC_CFG, 0x40007070 +.set CYREG_PHUB_CH6_ACTION, 0x40007074 +.set CYREG_PHUB_CH6_BASIC_STATUS, 0x40007078 +.set CYDEV_PHUB_CH7_BASE, 0x40007080 +.set CYDEV_PHUB_CH7_SIZE, 0x0000000c +.set CYREG_PHUB_CH7_BASIC_CFG, 0x40007080 +.set CYREG_PHUB_CH7_ACTION, 0x40007084 +.set CYREG_PHUB_CH7_BASIC_STATUS, 0x40007088 +.set CYDEV_PHUB_CH8_BASE, 0x40007090 +.set CYDEV_PHUB_CH8_SIZE, 0x0000000c +.set CYREG_PHUB_CH8_BASIC_CFG, 0x40007090 +.set CYREG_PHUB_CH8_ACTION, 0x40007094 +.set CYREG_PHUB_CH8_BASIC_STATUS, 0x40007098 +.set CYDEV_PHUB_CH9_BASE, 0x400070a0 +.set CYDEV_PHUB_CH9_SIZE, 0x0000000c +.set CYREG_PHUB_CH9_BASIC_CFG, 0x400070a0 +.set CYREG_PHUB_CH9_ACTION, 0x400070a4 +.set CYREG_PHUB_CH9_BASIC_STATUS, 0x400070a8 +.set CYDEV_PHUB_CH10_BASE, 0x400070b0 +.set CYDEV_PHUB_CH10_SIZE, 0x0000000c +.set CYREG_PHUB_CH10_BASIC_CFG, 0x400070b0 +.set CYREG_PHUB_CH10_ACTION, 0x400070b4 +.set CYREG_PHUB_CH10_BASIC_STATUS, 0x400070b8 +.set CYDEV_PHUB_CH11_BASE, 0x400070c0 +.set CYDEV_PHUB_CH11_SIZE, 0x0000000c +.set CYREG_PHUB_CH11_BASIC_CFG, 0x400070c0 +.set CYREG_PHUB_CH11_ACTION, 0x400070c4 +.set CYREG_PHUB_CH11_BASIC_STATUS, 0x400070c8 +.set CYDEV_PHUB_CH12_BASE, 0x400070d0 +.set CYDEV_PHUB_CH12_SIZE, 0x0000000c +.set CYREG_PHUB_CH12_BASIC_CFG, 0x400070d0 +.set CYREG_PHUB_CH12_ACTION, 0x400070d4 +.set CYREG_PHUB_CH12_BASIC_STATUS, 0x400070d8 +.set CYDEV_PHUB_CH13_BASE, 0x400070e0 +.set CYDEV_PHUB_CH13_SIZE, 0x0000000c +.set CYREG_PHUB_CH13_BASIC_CFG, 0x400070e0 +.set CYREG_PHUB_CH13_ACTION, 0x400070e4 +.set CYREG_PHUB_CH13_BASIC_STATUS, 0x400070e8 +.set CYDEV_PHUB_CH14_BASE, 0x400070f0 +.set CYDEV_PHUB_CH14_SIZE, 0x0000000c +.set CYREG_PHUB_CH14_BASIC_CFG, 0x400070f0 +.set CYREG_PHUB_CH14_ACTION, 0x400070f4 +.set CYREG_PHUB_CH14_BASIC_STATUS, 0x400070f8 +.set CYDEV_PHUB_CH15_BASE, 0x40007100 +.set CYDEV_PHUB_CH15_SIZE, 0x0000000c +.set CYREG_PHUB_CH15_BASIC_CFG, 0x40007100 +.set CYREG_PHUB_CH15_ACTION, 0x40007104 +.set CYREG_PHUB_CH15_BASIC_STATUS, 0x40007108 +.set CYDEV_PHUB_CH16_BASE, 0x40007110 +.set CYDEV_PHUB_CH16_SIZE, 0x0000000c +.set CYREG_PHUB_CH16_BASIC_CFG, 0x40007110 +.set CYREG_PHUB_CH16_ACTION, 0x40007114 +.set CYREG_PHUB_CH16_BASIC_STATUS, 0x40007118 +.set CYDEV_PHUB_CH17_BASE, 0x40007120 +.set CYDEV_PHUB_CH17_SIZE, 0x0000000c +.set CYREG_PHUB_CH17_BASIC_CFG, 0x40007120 +.set CYREG_PHUB_CH17_ACTION, 0x40007124 +.set CYREG_PHUB_CH17_BASIC_STATUS, 0x40007128 +.set CYDEV_PHUB_CH18_BASE, 0x40007130 +.set CYDEV_PHUB_CH18_SIZE, 0x0000000c +.set CYREG_PHUB_CH18_BASIC_CFG, 0x40007130 +.set CYREG_PHUB_CH18_ACTION, 0x40007134 +.set CYREG_PHUB_CH18_BASIC_STATUS, 0x40007138 +.set CYDEV_PHUB_CH19_BASE, 0x40007140 +.set CYDEV_PHUB_CH19_SIZE, 0x0000000c +.set CYREG_PHUB_CH19_BASIC_CFG, 0x40007140 +.set CYREG_PHUB_CH19_ACTION, 0x40007144 +.set CYREG_PHUB_CH19_BASIC_STATUS, 0x40007148 +.set CYDEV_PHUB_CH20_BASE, 0x40007150 +.set CYDEV_PHUB_CH20_SIZE, 0x0000000c +.set CYREG_PHUB_CH20_BASIC_CFG, 0x40007150 +.set CYREG_PHUB_CH20_ACTION, 0x40007154 +.set CYREG_PHUB_CH20_BASIC_STATUS, 0x40007158 +.set CYDEV_PHUB_CH21_BASE, 0x40007160 +.set CYDEV_PHUB_CH21_SIZE, 0x0000000c +.set CYREG_PHUB_CH21_BASIC_CFG, 0x40007160 +.set CYREG_PHUB_CH21_ACTION, 0x40007164 +.set CYREG_PHUB_CH21_BASIC_STATUS, 0x40007168 +.set CYDEV_PHUB_CH22_BASE, 0x40007170 +.set CYDEV_PHUB_CH22_SIZE, 0x0000000c +.set CYREG_PHUB_CH22_BASIC_CFG, 0x40007170 +.set CYREG_PHUB_CH22_ACTION, 0x40007174 +.set CYREG_PHUB_CH22_BASIC_STATUS, 0x40007178 +.set CYDEV_PHUB_CH23_BASE, 0x40007180 +.set CYDEV_PHUB_CH23_SIZE, 0x0000000c +.set CYREG_PHUB_CH23_BASIC_CFG, 0x40007180 +.set CYREG_PHUB_CH23_ACTION, 0x40007184 +.set CYREG_PHUB_CH23_BASIC_STATUS, 0x40007188 +.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM0_CFG0, 0x40007600 +.set CYREG_PHUB_CFGMEM0_CFG1, 0x40007604 +.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM1_CFG0, 0x40007608 +.set CYREG_PHUB_CFGMEM1_CFG1, 0x4000760c +.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM2_CFG0, 0x40007610 +.set CYREG_PHUB_CFGMEM2_CFG1, 0x40007614 +.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM3_CFG0, 0x40007618 +.set CYREG_PHUB_CFGMEM3_CFG1, 0x4000761c +.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM4_CFG0, 0x40007620 +.set CYREG_PHUB_CFGMEM4_CFG1, 0x40007624 +.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM5_CFG0, 0x40007628 +.set CYREG_PHUB_CFGMEM5_CFG1, 0x4000762c +.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM6_CFG0, 0x40007630 +.set CYREG_PHUB_CFGMEM6_CFG1, 0x40007634 +.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM7_CFG0, 0x40007638 +.set CYREG_PHUB_CFGMEM7_CFG1, 0x4000763c +.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM8_CFG0, 0x40007640 +.set CYREG_PHUB_CFGMEM8_CFG1, 0x40007644 +.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM9_CFG0, 0x40007648 +.set CYREG_PHUB_CFGMEM9_CFG1, 0x4000764c +.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM10_CFG0, 0x40007650 +.set CYREG_PHUB_CFGMEM10_CFG1, 0x40007654 +.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM11_CFG0, 0x40007658 +.set CYREG_PHUB_CFGMEM11_CFG1, 0x4000765c +.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM12_CFG0, 0x40007660 +.set CYREG_PHUB_CFGMEM12_CFG1, 0x40007664 +.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM13_CFG0, 0x40007668 +.set CYREG_PHUB_CFGMEM13_CFG1, 0x4000766c +.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM14_CFG0, 0x40007670 +.set CYREG_PHUB_CFGMEM14_CFG1, 0x40007674 +.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM15_CFG0, 0x40007678 +.set CYREG_PHUB_CFGMEM15_CFG1, 0x4000767c +.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM16_CFG0, 0x40007680 +.set CYREG_PHUB_CFGMEM16_CFG1, 0x40007684 +.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM17_CFG0, 0x40007688 +.set CYREG_PHUB_CFGMEM17_CFG1, 0x4000768c +.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM18_CFG0, 0x40007690 +.set CYREG_PHUB_CFGMEM18_CFG1, 0x40007694 +.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM19_CFG0, 0x40007698 +.set CYREG_PHUB_CFGMEM19_CFG1, 0x4000769c +.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM20_CFG0, 0x400076a0 +.set CYREG_PHUB_CFGMEM20_CFG1, 0x400076a4 +.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM21_CFG0, 0x400076a8 +.set CYREG_PHUB_CFGMEM21_CFG1, 0x400076ac +.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM22_CFG0, 0x400076b0 +.set CYREG_PHUB_CFGMEM22_CFG1, 0x400076b4 +.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM23_CFG0, 0x400076b8 +.set CYREG_PHUB_CFGMEM23_CFG1, 0x400076bc +.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 +.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM0_ORIG_TD0, 0x40007800 +.set CYREG_PHUB_TDMEM0_ORIG_TD1, 0x40007804 +.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 +.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM1_ORIG_TD0, 0x40007808 +.set CYREG_PHUB_TDMEM1_ORIG_TD1, 0x4000780c +.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 +.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM2_ORIG_TD0, 0x40007810 +.set CYREG_PHUB_TDMEM2_ORIG_TD1, 0x40007814 +.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 +.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM3_ORIG_TD0, 0x40007818 +.set CYREG_PHUB_TDMEM3_ORIG_TD1, 0x4000781c +.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 +.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM4_ORIG_TD0, 0x40007820 +.set CYREG_PHUB_TDMEM4_ORIG_TD1, 0x40007824 +.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 +.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM5_ORIG_TD0, 0x40007828 +.set CYREG_PHUB_TDMEM5_ORIG_TD1, 0x4000782c +.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 +.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM6_ORIG_TD0, 0x40007830 +.set CYREG_PHUB_TDMEM6_ORIG_TD1, 0x40007834 +.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 +.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM7_ORIG_TD0, 0x40007838 +.set CYREG_PHUB_TDMEM7_ORIG_TD1, 0x4000783c +.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 +.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM8_ORIG_TD0, 0x40007840 +.set CYREG_PHUB_TDMEM8_ORIG_TD1, 0x40007844 +.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 +.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM9_ORIG_TD0, 0x40007848 +.set CYREG_PHUB_TDMEM9_ORIG_TD1, 0x4000784c +.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 +.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM10_ORIG_TD0, 0x40007850 +.set CYREG_PHUB_TDMEM10_ORIG_TD1, 0x40007854 +.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 +.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM11_ORIG_TD0, 0x40007858 +.set CYREG_PHUB_TDMEM11_ORIG_TD1, 0x4000785c +.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 +.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM12_ORIG_TD0, 0x40007860 +.set CYREG_PHUB_TDMEM12_ORIG_TD1, 0x40007864 +.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 +.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM13_ORIG_TD0, 0x40007868 +.set CYREG_PHUB_TDMEM13_ORIG_TD1, 0x4000786c +.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 +.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM14_ORIG_TD0, 0x40007870 +.set CYREG_PHUB_TDMEM14_ORIG_TD1, 0x40007874 +.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 +.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM15_ORIG_TD0, 0x40007878 +.set CYREG_PHUB_TDMEM15_ORIG_TD1, 0x4000787c +.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 +.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM16_ORIG_TD0, 0x40007880 +.set CYREG_PHUB_TDMEM16_ORIG_TD1, 0x40007884 +.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 +.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM17_ORIG_TD0, 0x40007888 +.set CYREG_PHUB_TDMEM17_ORIG_TD1, 0x4000788c +.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 +.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM18_ORIG_TD0, 0x40007890 +.set CYREG_PHUB_TDMEM18_ORIG_TD1, 0x40007894 +.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 +.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM19_ORIG_TD0, 0x40007898 +.set CYREG_PHUB_TDMEM19_ORIG_TD1, 0x4000789c +.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 +.set CYREG_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 +.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 +.set CYREG_PHUB_TDMEM21_ORIG_TD1, 0x400078ac +.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 +.set CYREG_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 +.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 +.set CYREG_PHUB_TDMEM23_ORIG_TD1, 0x400078bc +.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 +.set CYREG_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 +.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 +.set CYREG_PHUB_TDMEM25_ORIG_TD1, 0x400078cc +.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 +.set CYREG_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 +.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 +.set CYREG_PHUB_TDMEM27_ORIG_TD1, 0x400078dc +.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 +.set CYREG_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 +.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 +.set CYREG_PHUB_TDMEM29_ORIG_TD1, 0x400078ec +.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 +.set CYREG_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 +.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 +.set CYREG_PHUB_TDMEM31_ORIG_TD1, 0x400078fc +.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 +.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM32_ORIG_TD0, 0x40007900 +.set CYREG_PHUB_TDMEM32_ORIG_TD1, 0x40007904 +.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 +.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM33_ORIG_TD0, 0x40007908 +.set CYREG_PHUB_TDMEM33_ORIG_TD1, 0x4000790c +.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 +.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM34_ORIG_TD0, 0x40007910 +.set CYREG_PHUB_TDMEM34_ORIG_TD1, 0x40007914 +.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 +.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM35_ORIG_TD0, 0x40007918 +.set CYREG_PHUB_TDMEM35_ORIG_TD1, 0x4000791c +.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 +.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM36_ORIG_TD0, 0x40007920 +.set CYREG_PHUB_TDMEM36_ORIG_TD1, 0x40007924 +.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 +.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM37_ORIG_TD0, 0x40007928 +.set CYREG_PHUB_TDMEM37_ORIG_TD1, 0x4000792c +.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 +.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM38_ORIG_TD0, 0x40007930 +.set CYREG_PHUB_TDMEM38_ORIG_TD1, 0x40007934 +.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 +.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM39_ORIG_TD0, 0x40007938 +.set CYREG_PHUB_TDMEM39_ORIG_TD1, 0x4000793c +.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 +.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM40_ORIG_TD0, 0x40007940 +.set CYREG_PHUB_TDMEM40_ORIG_TD1, 0x40007944 +.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 +.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM41_ORIG_TD0, 0x40007948 +.set CYREG_PHUB_TDMEM41_ORIG_TD1, 0x4000794c +.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 +.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM42_ORIG_TD0, 0x40007950 +.set CYREG_PHUB_TDMEM42_ORIG_TD1, 0x40007954 +.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 +.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM43_ORIG_TD0, 0x40007958 +.set CYREG_PHUB_TDMEM43_ORIG_TD1, 0x4000795c +.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 +.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM44_ORIG_TD0, 0x40007960 +.set CYREG_PHUB_TDMEM44_ORIG_TD1, 0x40007964 +.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 +.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM45_ORIG_TD0, 0x40007968 +.set CYREG_PHUB_TDMEM45_ORIG_TD1, 0x4000796c +.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 +.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM46_ORIG_TD0, 0x40007970 +.set CYREG_PHUB_TDMEM46_ORIG_TD1, 0x40007974 +.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 +.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM47_ORIG_TD0, 0x40007978 +.set CYREG_PHUB_TDMEM47_ORIG_TD1, 0x4000797c +.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 +.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM48_ORIG_TD0, 0x40007980 +.set CYREG_PHUB_TDMEM48_ORIG_TD1, 0x40007984 +.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 +.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM49_ORIG_TD0, 0x40007988 +.set CYREG_PHUB_TDMEM49_ORIG_TD1, 0x4000798c +.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 +.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM50_ORIG_TD0, 0x40007990 +.set CYREG_PHUB_TDMEM50_ORIG_TD1, 0x40007994 +.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 +.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM51_ORIG_TD0, 0x40007998 +.set CYREG_PHUB_TDMEM51_ORIG_TD1, 0x4000799c +.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 +.set CYREG_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 +.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 +.set CYREG_PHUB_TDMEM53_ORIG_TD1, 0x400079ac +.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 +.set CYREG_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 +.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 +.set CYREG_PHUB_TDMEM55_ORIG_TD1, 0x400079bc +.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 +.set CYREG_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 +.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 +.set CYREG_PHUB_TDMEM57_ORIG_TD1, 0x400079cc +.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 +.set CYREG_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 +.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 +.set CYREG_PHUB_TDMEM59_ORIG_TD1, 0x400079dc +.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 +.set CYREG_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 +.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 +.set CYREG_PHUB_TDMEM61_ORIG_TD1, 0x400079ec +.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 +.set CYREG_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 +.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 +.set CYREG_PHUB_TDMEM63_ORIG_TD1, 0x400079fc +.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 +.set CYREG_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 +.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 +.set CYREG_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c +.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 +.set CYREG_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 +.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 +.set CYREG_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c +.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 +.set CYREG_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 +.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 +.set CYREG_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c +.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 +.set CYREG_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 +.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 +.set CYREG_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c +.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 +.set CYREG_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 +.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 +.set CYREG_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c +.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 +.set CYREG_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 +.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 +.set CYREG_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c +.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 +.set CYREG_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 +.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 +.set CYREG_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c +.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 +.set CYREG_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 +.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 +.set CYREG_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c +.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 +.set CYREG_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 +.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 +.set CYREG_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c +.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 +.set CYREG_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 +.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 +.set CYREG_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c +.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 +.set CYREG_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 +.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 +.set CYREG_PHUB_TDMEM85_ORIG_TD1, 0x40007aac +.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 +.set CYREG_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 +.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 +.set CYREG_PHUB_TDMEM87_ORIG_TD1, 0x40007abc +.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 +.set CYREG_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 +.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 +.set CYREG_PHUB_TDMEM89_ORIG_TD1, 0x40007acc +.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 +.set CYREG_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 +.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 +.set CYREG_PHUB_TDMEM91_ORIG_TD1, 0x40007adc +.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 +.set CYREG_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 +.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 +.set CYREG_PHUB_TDMEM93_ORIG_TD1, 0x40007aec +.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 +.set CYREG_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 +.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 +.set CYREG_PHUB_TDMEM95_ORIG_TD1, 0x40007afc +.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 +.set CYREG_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 +.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 +.set CYREG_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c +.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 +.set CYREG_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 +.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 +.set CYREG_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c +.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 +.set CYREG_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 +.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 +.set CYREG_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c +.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 +.set CYREG_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 +.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 +.set CYREG_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c +.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 +.set CYREG_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 +.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 +.set CYREG_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c +.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 +.set CYREG_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 +.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 +.set CYREG_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c +.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 +.set CYREG_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 +.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 +.set CYREG_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c +.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 +.set CYREG_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 +.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 +.set CYREG_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c +.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 +.set CYREG_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 +.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 +.set CYREG_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c +.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 +.set CYREG_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 +.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 +.set CYREG_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c +.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 +.set CYREG_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 +.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 +.set CYREG_PHUB_TDMEM117_ORIG_TD1, 0x40007bac +.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 +.set CYREG_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 +.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 +.set CYREG_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc +.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 +.set CYREG_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 +.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 +.set CYREG_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc +.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 +.set CYREG_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 +.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 +.set CYREG_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc +.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 +.set CYREG_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 +.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 +.set CYREG_PHUB_TDMEM125_ORIG_TD1, 0x40007bec +.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 +.set CYREG_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 +.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 +.set CYREG_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc +.set CYDEV_EE_BASE, 0x40008000 +.set CYDEV_EE_SIZE, 0x00000800 +.set CYREG_EE_DATA_MBASE, 0x40008000 +.set CYREG_EE_DATA_MSIZE, 0x00000800 +.set CYDEV_CAN0_BASE, 0x4000a000 +.set CYDEV_CAN0_SIZE, 0x000002a0 +.set CYDEV_CAN0_CSR_BASE, 0x4000a000 +.set CYDEV_CAN0_CSR_SIZE, 0x00000018 +.set CYREG_CAN0_CSR_INT_SR, 0x4000a000 +.set CYREG_CAN0_CSR_INT_EN, 0x4000a004 +.set CYREG_CAN0_CSR_BUF_SR, 0x4000a008 +.set CYREG_CAN0_CSR_ERR_SR, 0x4000a00c +.set CYREG_CAN0_CSR_CMD, 0x4000a010 +.set CYREG_CAN0_CSR_CFG, 0x4000a014 +.set CYDEV_CAN0_TX0_BASE, 0x4000a020 +.set CYDEV_CAN0_TX0_SIZE, 0x00000010 +.set CYREG_CAN0_TX0_CMD, 0x4000a020 +.set CYREG_CAN0_TX0_ID, 0x4000a024 +.set CYREG_CAN0_TX0_DH, 0x4000a028 +.set CYREG_CAN0_TX0_DL, 0x4000a02c +.set CYDEV_CAN0_TX1_BASE, 0x4000a030 +.set CYDEV_CAN0_TX1_SIZE, 0x00000010 +.set CYREG_CAN0_TX1_CMD, 0x4000a030 +.set CYREG_CAN0_TX1_ID, 0x4000a034 +.set CYREG_CAN0_TX1_DH, 0x4000a038 +.set CYREG_CAN0_TX1_DL, 0x4000a03c +.set CYDEV_CAN0_TX2_BASE, 0x4000a040 +.set CYDEV_CAN0_TX2_SIZE, 0x00000010 +.set CYREG_CAN0_TX2_CMD, 0x4000a040 +.set CYREG_CAN0_TX2_ID, 0x4000a044 +.set CYREG_CAN0_TX2_DH, 0x4000a048 +.set CYREG_CAN0_TX2_DL, 0x4000a04c +.set CYDEV_CAN0_TX3_BASE, 0x4000a050 +.set CYDEV_CAN0_TX3_SIZE, 0x00000010 +.set CYREG_CAN0_TX3_CMD, 0x4000a050 +.set CYREG_CAN0_TX3_ID, 0x4000a054 +.set CYREG_CAN0_TX3_DH, 0x4000a058 +.set CYREG_CAN0_TX3_DL, 0x4000a05c +.set CYDEV_CAN0_TX4_BASE, 0x4000a060 +.set CYDEV_CAN0_TX4_SIZE, 0x00000010 +.set CYREG_CAN0_TX4_CMD, 0x4000a060 +.set CYREG_CAN0_TX4_ID, 0x4000a064 +.set CYREG_CAN0_TX4_DH, 0x4000a068 +.set CYREG_CAN0_TX4_DL, 0x4000a06c +.set CYDEV_CAN0_TX5_BASE, 0x4000a070 +.set CYDEV_CAN0_TX5_SIZE, 0x00000010 +.set CYREG_CAN0_TX5_CMD, 0x4000a070 +.set CYREG_CAN0_TX5_ID, 0x4000a074 +.set CYREG_CAN0_TX5_DH, 0x4000a078 +.set CYREG_CAN0_TX5_DL, 0x4000a07c +.set CYDEV_CAN0_TX6_BASE, 0x4000a080 +.set CYDEV_CAN0_TX6_SIZE, 0x00000010 +.set CYREG_CAN0_TX6_CMD, 0x4000a080 +.set CYREG_CAN0_TX6_ID, 0x4000a084 +.set CYREG_CAN0_TX6_DH, 0x4000a088 +.set CYREG_CAN0_TX6_DL, 0x4000a08c +.set CYDEV_CAN0_TX7_BASE, 0x4000a090 +.set CYDEV_CAN0_TX7_SIZE, 0x00000010 +.set CYREG_CAN0_TX7_CMD, 0x4000a090 +.set CYREG_CAN0_TX7_ID, 0x4000a094 +.set CYREG_CAN0_TX7_DH, 0x4000a098 +.set CYREG_CAN0_TX7_DL, 0x4000a09c +.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 +.set CYDEV_CAN0_RX0_SIZE, 0x00000020 +.set CYREG_CAN0_RX0_CMD, 0x4000a0a0 +.set CYREG_CAN0_RX0_ID, 0x4000a0a4 +.set CYREG_CAN0_RX0_DH, 0x4000a0a8 +.set CYREG_CAN0_RX0_DL, 0x4000a0ac +.set CYREG_CAN0_RX0_AMR, 0x4000a0b0 +.set CYREG_CAN0_RX0_ACR, 0x4000a0b4 +.set CYREG_CAN0_RX0_AMRD, 0x4000a0b8 +.set CYREG_CAN0_RX0_ACRD, 0x4000a0bc +.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 +.set CYDEV_CAN0_RX1_SIZE, 0x00000020 +.set CYREG_CAN0_RX1_CMD, 0x4000a0c0 +.set CYREG_CAN0_RX1_ID, 0x4000a0c4 +.set CYREG_CAN0_RX1_DH, 0x4000a0c8 +.set CYREG_CAN0_RX1_DL, 0x4000a0cc +.set CYREG_CAN0_RX1_AMR, 0x4000a0d0 +.set CYREG_CAN0_RX1_ACR, 0x4000a0d4 +.set CYREG_CAN0_RX1_AMRD, 0x4000a0d8 +.set CYREG_CAN0_RX1_ACRD, 0x4000a0dc +.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 +.set CYDEV_CAN0_RX2_SIZE, 0x00000020 +.set CYREG_CAN0_RX2_CMD, 0x4000a0e0 +.set CYREG_CAN0_RX2_ID, 0x4000a0e4 +.set CYREG_CAN0_RX2_DH, 0x4000a0e8 +.set CYREG_CAN0_RX2_DL, 0x4000a0ec +.set CYREG_CAN0_RX2_AMR, 0x4000a0f0 +.set CYREG_CAN0_RX2_ACR, 0x4000a0f4 +.set CYREG_CAN0_RX2_AMRD, 0x4000a0f8 +.set CYREG_CAN0_RX2_ACRD, 0x4000a0fc +.set CYDEV_CAN0_RX3_BASE, 0x4000a100 +.set CYDEV_CAN0_RX3_SIZE, 0x00000020 +.set CYREG_CAN0_RX3_CMD, 0x4000a100 +.set CYREG_CAN0_RX3_ID, 0x4000a104 +.set CYREG_CAN0_RX3_DH, 0x4000a108 +.set CYREG_CAN0_RX3_DL, 0x4000a10c +.set CYREG_CAN0_RX3_AMR, 0x4000a110 +.set CYREG_CAN0_RX3_ACR, 0x4000a114 +.set CYREG_CAN0_RX3_AMRD, 0x4000a118 +.set CYREG_CAN0_RX3_ACRD, 0x4000a11c +.set CYDEV_CAN0_RX4_BASE, 0x4000a120 +.set CYDEV_CAN0_RX4_SIZE, 0x00000020 +.set CYREG_CAN0_RX4_CMD, 0x4000a120 +.set CYREG_CAN0_RX4_ID, 0x4000a124 +.set CYREG_CAN0_RX4_DH, 0x4000a128 +.set CYREG_CAN0_RX4_DL, 0x4000a12c +.set CYREG_CAN0_RX4_AMR, 0x4000a130 +.set CYREG_CAN0_RX4_ACR, 0x4000a134 +.set CYREG_CAN0_RX4_AMRD, 0x4000a138 +.set CYREG_CAN0_RX4_ACRD, 0x4000a13c +.set CYDEV_CAN0_RX5_BASE, 0x4000a140 +.set CYDEV_CAN0_RX5_SIZE, 0x00000020 +.set CYREG_CAN0_RX5_CMD, 0x4000a140 +.set CYREG_CAN0_RX5_ID, 0x4000a144 +.set CYREG_CAN0_RX5_DH, 0x4000a148 +.set CYREG_CAN0_RX5_DL, 0x4000a14c +.set CYREG_CAN0_RX5_AMR, 0x4000a150 +.set CYREG_CAN0_RX5_ACR, 0x4000a154 +.set CYREG_CAN0_RX5_AMRD, 0x4000a158 +.set CYREG_CAN0_RX5_ACRD, 0x4000a15c +.set CYDEV_CAN0_RX6_BASE, 0x4000a160 +.set CYDEV_CAN0_RX6_SIZE, 0x00000020 +.set CYREG_CAN0_RX6_CMD, 0x4000a160 +.set CYREG_CAN0_RX6_ID, 0x4000a164 +.set CYREG_CAN0_RX6_DH, 0x4000a168 +.set CYREG_CAN0_RX6_DL, 0x4000a16c +.set CYREG_CAN0_RX6_AMR, 0x4000a170 +.set CYREG_CAN0_RX6_ACR, 0x4000a174 +.set CYREG_CAN0_RX6_AMRD, 0x4000a178 +.set CYREG_CAN0_RX6_ACRD, 0x4000a17c +.set CYDEV_CAN0_RX7_BASE, 0x4000a180 +.set CYDEV_CAN0_RX7_SIZE, 0x00000020 +.set CYREG_CAN0_RX7_CMD, 0x4000a180 +.set CYREG_CAN0_RX7_ID, 0x4000a184 +.set CYREG_CAN0_RX7_DH, 0x4000a188 +.set CYREG_CAN0_RX7_DL, 0x4000a18c +.set CYREG_CAN0_RX7_AMR, 0x4000a190 +.set CYREG_CAN0_RX7_ACR, 0x4000a194 +.set CYREG_CAN0_RX7_AMRD, 0x4000a198 +.set CYREG_CAN0_RX7_ACRD, 0x4000a19c +.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 +.set CYDEV_CAN0_RX8_SIZE, 0x00000020 +.set CYREG_CAN0_RX8_CMD, 0x4000a1a0 +.set CYREG_CAN0_RX8_ID, 0x4000a1a4 +.set CYREG_CAN0_RX8_DH, 0x4000a1a8 +.set CYREG_CAN0_RX8_DL, 0x4000a1ac +.set CYREG_CAN0_RX8_AMR, 0x4000a1b0 +.set CYREG_CAN0_RX8_ACR, 0x4000a1b4 +.set CYREG_CAN0_RX8_AMRD, 0x4000a1b8 +.set CYREG_CAN0_RX8_ACRD, 0x4000a1bc +.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 +.set CYDEV_CAN0_RX9_SIZE, 0x00000020 +.set CYREG_CAN0_RX9_CMD, 0x4000a1c0 +.set CYREG_CAN0_RX9_ID, 0x4000a1c4 +.set CYREG_CAN0_RX9_DH, 0x4000a1c8 +.set CYREG_CAN0_RX9_DL, 0x4000a1cc +.set CYREG_CAN0_RX9_AMR, 0x4000a1d0 +.set CYREG_CAN0_RX9_ACR, 0x4000a1d4 +.set CYREG_CAN0_RX9_AMRD, 0x4000a1d8 +.set CYREG_CAN0_RX9_ACRD, 0x4000a1dc +.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 +.set CYDEV_CAN0_RX10_SIZE, 0x00000020 +.set CYREG_CAN0_RX10_CMD, 0x4000a1e0 +.set CYREG_CAN0_RX10_ID, 0x4000a1e4 +.set CYREG_CAN0_RX10_DH, 0x4000a1e8 +.set CYREG_CAN0_RX10_DL, 0x4000a1ec +.set CYREG_CAN0_RX10_AMR, 0x4000a1f0 +.set CYREG_CAN0_RX10_ACR, 0x4000a1f4 +.set CYREG_CAN0_RX10_AMRD, 0x4000a1f8 +.set CYREG_CAN0_RX10_ACRD, 0x4000a1fc +.set CYDEV_CAN0_RX11_BASE, 0x4000a200 +.set CYDEV_CAN0_RX11_SIZE, 0x00000020 +.set CYREG_CAN0_RX11_CMD, 0x4000a200 +.set CYREG_CAN0_RX11_ID, 0x4000a204 +.set CYREG_CAN0_RX11_DH, 0x4000a208 +.set CYREG_CAN0_RX11_DL, 0x4000a20c +.set CYREG_CAN0_RX11_AMR, 0x4000a210 +.set CYREG_CAN0_RX11_ACR, 0x4000a214 +.set CYREG_CAN0_RX11_AMRD, 0x4000a218 +.set CYREG_CAN0_RX11_ACRD, 0x4000a21c +.set CYDEV_CAN0_RX12_BASE, 0x4000a220 +.set CYDEV_CAN0_RX12_SIZE, 0x00000020 +.set CYREG_CAN0_RX12_CMD, 0x4000a220 +.set CYREG_CAN0_RX12_ID, 0x4000a224 +.set CYREG_CAN0_RX12_DH, 0x4000a228 +.set CYREG_CAN0_RX12_DL, 0x4000a22c +.set CYREG_CAN0_RX12_AMR, 0x4000a230 +.set CYREG_CAN0_RX12_ACR, 0x4000a234 +.set CYREG_CAN0_RX12_AMRD, 0x4000a238 +.set CYREG_CAN0_RX12_ACRD, 0x4000a23c +.set CYDEV_CAN0_RX13_BASE, 0x4000a240 +.set CYDEV_CAN0_RX13_SIZE, 0x00000020 +.set CYREG_CAN0_RX13_CMD, 0x4000a240 +.set CYREG_CAN0_RX13_ID, 0x4000a244 +.set CYREG_CAN0_RX13_DH, 0x4000a248 +.set CYREG_CAN0_RX13_DL, 0x4000a24c +.set CYREG_CAN0_RX13_AMR, 0x4000a250 +.set CYREG_CAN0_RX13_ACR, 0x4000a254 +.set CYREG_CAN0_RX13_AMRD, 0x4000a258 +.set CYREG_CAN0_RX13_ACRD, 0x4000a25c +.set CYDEV_CAN0_RX14_BASE, 0x4000a260 +.set CYDEV_CAN0_RX14_SIZE, 0x00000020 +.set CYREG_CAN0_RX14_CMD, 0x4000a260 +.set CYREG_CAN0_RX14_ID, 0x4000a264 +.set CYREG_CAN0_RX14_DH, 0x4000a268 +.set CYREG_CAN0_RX14_DL, 0x4000a26c +.set CYREG_CAN0_RX14_AMR, 0x4000a270 +.set CYREG_CAN0_RX14_ACR, 0x4000a274 +.set CYREG_CAN0_RX14_AMRD, 0x4000a278 +.set CYREG_CAN0_RX14_ACRD, 0x4000a27c +.set CYDEV_CAN0_RX15_BASE, 0x4000a280 +.set CYDEV_CAN0_RX15_SIZE, 0x00000020 +.set CYREG_CAN0_RX15_CMD, 0x4000a280 +.set CYREG_CAN0_RX15_ID, 0x4000a284 +.set CYREG_CAN0_RX15_DH, 0x4000a288 +.set CYREG_CAN0_RX15_DL, 0x4000a28c +.set CYREG_CAN0_RX15_AMR, 0x4000a290 +.set CYREG_CAN0_RX15_ACR, 0x4000a294 +.set CYREG_CAN0_RX15_AMRD, 0x4000a298 +.set CYREG_CAN0_RX15_ACRD, 0x4000a29c +.set CYDEV_DFB0_BASE, 0x4000c000 +.set CYDEV_DFB0_SIZE, 0x000007b5 +.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 +.set CYREG_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 +.set CYREG_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 +.set CYREG_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 +.set CYREG_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 +.set CYREG_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 +.set CYREG_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 +.set CYREG_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 +.set CYREG_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 +.set CYREG_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 +.set CYREG_DFB0_CR, 0x4000c780 +.set CYREG_DFB0_SR, 0x4000c784 +.set CYREG_DFB0_RAM_EN, 0x4000c788 +.set CYREG_DFB0_RAM_DIR, 0x4000c78c +.set CYREG_DFB0_SEMA, 0x4000c790 +.set CYREG_DFB0_DSI_CTRL, 0x4000c794 +.set CYREG_DFB0_INT_CTRL, 0x4000c798 +.set CYREG_DFB0_DMA_CTRL, 0x4000c79c +.set CYREG_DFB0_STAGEA, 0x4000c7a0 +.set CYREG_DFB0_STAGEAM, 0x4000c7a1 +.set CYREG_DFB0_STAGEAH, 0x4000c7a2 +.set CYREG_DFB0_STAGEB, 0x4000c7a4 +.set CYREG_DFB0_STAGEBM, 0x4000c7a5 +.set CYREG_DFB0_STAGEBH, 0x4000c7a6 +.set CYREG_DFB0_HOLDA, 0x4000c7a8 +.set CYREG_DFB0_HOLDAM, 0x4000c7a9 +.set CYREG_DFB0_HOLDAH, 0x4000c7aa +.set CYREG_DFB0_HOLDAS, 0x4000c7ab +.set CYREG_DFB0_HOLDB, 0x4000c7ac +.set CYREG_DFB0_HOLDBM, 0x4000c7ad +.set CYREG_DFB0_HOLDBH, 0x4000c7ae +.set CYREG_DFB0_HOLDBS, 0x4000c7af +.set CYREG_DFB0_COHER, 0x4000c7b0 +.set CYREG_DFB0_DALIGN, 0x4000c7b4 +.set CYDEV_UCFG_BASE, 0x40010000 +.set CYDEV_UCFG_SIZE, 0x00005040 +.set CYDEV_UCFG_B0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_SIZE, 0x00000fef +.set CYDEV_UCFG_B0_P0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 +.set CYREG_B0_P0_U0_PLD_IT0, 0x40010000 +.set CYREG_B0_P0_U0_PLD_IT1, 0x40010004 +.set CYREG_B0_P0_U0_PLD_IT2, 0x40010008 +.set CYREG_B0_P0_U0_PLD_IT3, 0x4001000c +.set CYREG_B0_P0_U0_PLD_IT4, 0x40010010 +.set CYREG_B0_P0_U0_PLD_IT5, 0x40010014 +.set CYREG_B0_P0_U0_PLD_IT6, 0x40010018 +.set CYREG_B0_P0_U0_PLD_IT7, 0x4001001c +.set CYREG_B0_P0_U0_PLD_IT8, 0x40010020 +.set CYREG_B0_P0_U0_PLD_IT9, 0x40010024 +.set CYREG_B0_P0_U0_PLD_IT10, 0x40010028 +.set CYREG_B0_P0_U0_PLD_IT11, 0x4001002c +.set CYREG_B0_P0_U0_PLD_ORT0, 0x40010030 +.set CYREG_B0_P0_U0_PLD_ORT1, 0x40010032 +.set CYREG_B0_P0_U0_PLD_ORT2, 0x40010034 +.set CYREG_B0_P0_U0_PLD_ORT3, 0x40010036 +.set CYREG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 +.set CYREG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a +.set CYREG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c +.set CYREG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e +.set CYREG_B0_P0_U0_CFG0, 0x40010040 +.set CYREG_B0_P0_U0_CFG1, 0x40010041 +.set CYREG_B0_P0_U0_CFG2, 0x40010042 +.set CYREG_B0_P0_U0_CFG3, 0x40010043 +.set CYREG_B0_P0_U0_CFG4, 0x40010044 +.set CYREG_B0_P0_U0_CFG5, 0x40010045 +.set CYREG_B0_P0_U0_CFG6, 0x40010046 +.set CYREG_B0_P0_U0_CFG7, 0x40010047 +.set CYREG_B0_P0_U0_CFG8, 0x40010048 +.set CYREG_B0_P0_U0_CFG9, 0x40010049 +.set CYREG_B0_P0_U0_CFG10, 0x4001004a +.set CYREG_B0_P0_U0_CFG11, 0x4001004b +.set CYREG_B0_P0_U0_CFG12, 0x4001004c +.set CYREG_B0_P0_U0_CFG13, 0x4001004d +.set CYREG_B0_P0_U0_CFG14, 0x4001004e +.set CYREG_B0_P0_U0_CFG15, 0x4001004f +.set CYREG_B0_P0_U0_CFG16, 0x40010050 +.set CYREG_B0_P0_U0_CFG17, 0x40010051 +.set CYREG_B0_P0_U0_CFG18, 0x40010052 +.set CYREG_B0_P0_U0_CFG19, 0x40010053 +.set CYREG_B0_P0_U0_CFG20, 0x40010054 +.set CYREG_B0_P0_U0_CFG21, 0x40010055 +.set CYREG_B0_P0_U0_CFG22, 0x40010056 +.set CYREG_B0_P0_U0_CFG23, 0x40010057 +.set CYREG_B0_P0_U0_CFG24, 0x40010058 +.set CYREG_B0_P0_U0_CFG25, 0x40010059 +.set CYREG_B0_P0_U0_CFG26, 0x4001005a +.set CYREG_B0_P0_U0_CFG27, 0x4001005b +.set CYREG_B0_P0_U0_CFG28, 0x4001005c +.set CYREG_B0_P0_U0_CFG29, 0x4001005d +.set CYREG_B0_P0_U0_CFG30, 0x4001005e +.set CYREG_B0_P0_U0_CFG31, 0x4001005f +.set CYREG_B0_P0_U0_DCFG0, 0x40010060 +.set CYREG_B0_P0_U0_DCFG1, 0x40010062 +.set CYREG_B0_P0_U0_DCFG2, 0x40010064 +.set CYREG_B0_P0_U0_DCFG3, 0x40010066 +.set CYREG_B0_P0_U0_DCFG4, 0x40010068 +.set CYREG_B0_P0_U0_DCFG5, 0x4001006a +.set CYREG_B0_P0_U0_DCFG6, 0x4001006c +.set CYREG_B0_P0_U0_DCFG7, 0x4001006e +.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 +.set CYREG_B0_P0_U1_PLD_IT0, 0x40010080 +.set CYREG_B0_P0_U1_PLD_IT1, 0x40010084 +.set CYREG_B0_P0_U1_PLD_IT2, 0x40010088 +.set CYREG_B0_P0_U1_PLD_IT3, 0x4001008c +.set CYREG_B0_P0_U1_PLD_IT4, 0x40010090 +.set CYREG_B0_P0_U1_PLD_IT5, 0x40010094 +.set CYREG_B0_P0_U1_PLD_IT6, 0x40010098 +.set CYREG_B0_P0_U1_PLD_IT7, 0x4001009c +.set CYREG_B0_P0_U1_PLD_IT8, 0x400100a0 +.set CYREG_B0_P0_U1_PLD_IT9, 0x400100a4 +.set CYREG_B0_P0_U1_PLD_IT10, 0x400100a8 +.set CYREG_B0_P0_U1_PLD_IT11, 0x400100ac +.set CYREG_B0_P0_U1_PLD_ORT0, 0x400100b0 +.set CYREG_B0_P0_U1_PLD_ORT1, 0x400100b2 +.set CYREG_B0_P0_U1_PLD_ORT2, 0x400100b4 +.set CYREG_B0_P0_U1_PLD_ORT3, 0x400100b6 +.set CYREG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 +.set CYREG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba +.set CYREG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc +.set CYREG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be +.set CYREG_B0_P0_U1_CFG0, 0x400100c0 +.set CYREG_B0_P0_U1_CFG1, 0x400100c1 +.set CYREG_B0_P0_U1_CFG2, 0x400100c2 +.set CYREG_B0_P0_U1_CFG3, 0x400100c3 +.set CYREG_B0_P0_U1_CFG4, 0x400100c4 +.set CYREG_B0_P0_U1_CFG5, 0x400100c5 +.set CYREG_B0_P0_U1_CFG6, 0x400100c6 +.set CYREG_B0_P0_U1_CFG7, 0x400100c7 +.set CYREG_B0_P0_U1_CFG8, 0x400100c8 +.set CYREG_B0_P0_U1_CFG9, 0x400100c9 +.set CYREG_B0_P0_U1_CFG10, 0x400100ca +.set CYREG_B0_P0_U1_CFG11, 0x400100cb +.set CYREG_B0_P0_U1_CFG12, 0x400100cc +.set CYREG_B0_P0_U1_CFG13, 0x400100cd +.set CYREG_B0_P0_U1_CFG14, 0x400100ce +.set CYREG_B0_P0_U1_CFG15, 0x400100cf +.set CYREG_B0_P0_U1_CFG16, 0x400100d0 +.set CYREG_B0_P0_U1_CFG17, 0x400100d1 +.set CYREG_B0_P0_U1_CFG18, 0x400100d2 +.set CYREG_B0_P0_U1_CFG19, 0x400100d3 +.set CYREG_B0_P0_U1_CFG20, 0x400100d4 +.set CYREG_B0_P0_U1_CFG21, 0x400100d5 +.set CYREG_B0_P0_U1_CFG22, 0x400100d6 +.set CYREG_B0_P0_U1_CFG23, 0x400100d7 +.set CYREG_B0_P0_U1_CFG24, 0x400100d8 +.set CYREG_B0_P0_U1_CFG25, 0x400100d9 +.set CYREG_B0_P0_U1_CFG26, 0x400100da +.set CYREG_B0_P0_U1_CFG27, 0x400100db +.set CYREG_B0_P0_U1_CFG28, 0x400100dc +.set CYREG_B0_P0_U1_CFG29, 0x400100dd +.set CYREG_B0_P0_U1_CFG30, 0x400100de +.set CYREG_B0_P0_U1_CFG31, 0x400100df +.set CYREG_B0_P0_U1_DCFG0, 0x400100e0 +.set CYREG_B0_P0_U1_DCFG1, 0x400100e2 +.set CYREG_B0_P0_U1_DCFG2, 0x400100e4 +.set CYREG_B0_P0_U1_DCFG3, 0x400100e6 +.set CYREG_B0_P0_U1_DCFG4, 0x400100e8 +.set CYREG_B0_P0_U1_DCFG5, 0x400100ea +.set CYREG_B0_P0_U1_DCFG6, 0x400100ec +.set CYREG_B0_P0_U1_DCFG7, 0x400100ee +.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 +.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P1_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 +.set CYREG_B0_P1_U0_PLD_IT0, 0x40010200 +.set CYREG_B0_P1_U0_PLD_IT1, 0x40010204 +.set CYREG_B0_P1_U0_PLD_IT2, 0x40010208 +.set CYREG_B0_P1_U0_PLD_IT3, 0x4001020c +.set CYREG_B0_P1_U0_PLD_IT4, 0x40010210 +.set CYREG_B0_P1_U0_PLD_IT5, 0x40010214 +.set CYREG_B0_P1_U0_PLD_IT6, 0x40010218 +.set CYREG_B0_P1_U0_PLD_IT7, 0x4001021c +.set CYREG_B0_P1_U0_PLD_IT8, 0x40010220 +.set CYREG_B0_P1_U0_PLD_IT9, 0x40010224 +.set CYREG_B0_P1_U0_PLD_IT10, 0x40010228 +.set CYREG_B0_P1_U0_PLD_IT11, 0x4001022c +.set CYREG_B0_P1_U0_PLD_ORT0, 0x40010230 +.set CYREG_B0_P1_U0_PLD_ORT1, 0x40010232 +.set CYREG_B0_P1_U0_PLD_ORT2, 0x40010234 +.set CYREG_B0_P1_U0_PLD_ORT3, 0x40010236 +.set CYREG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 +.set CYREG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a +.set CYREG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c +.set CYREG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e +.set CYREG_B0_P1_U0_CFG0, 0x40010240 +.set CYREG_B0_P1_U0_CFG1, 0x40010241 +.set CYREG_B0_P1_U0_CFG2, 0x40010242 +.set CYREG_B0_P1_U0_CFG3, 0x40010243 +.set CYREG_B0_P1_U0_CFG4, 0x40010244 +.set CYREG_B0_P1_U0_CFG5, 0x40010245 +.set CYREG_B0_P1_U0_CFG6, 0x40010246 +.set CYREG_B0_P1_U0_CFG7, 0x40010247 +.set CYREG_B0_P1_U0_CFG8, 0x40010248 +.set CYREG_B0_P1_U0_CFG9, 0x40010249 +.set CYREG_B0_P1_U0_CFG10, 0x4001024a +.set CYREG_B0_P1_U0_CFG11, 0x4001024b +.set CYREG_B0_P1_U0_CFG12, 0x4001024c +.set CYREG_B0_P1_U0_CFG13, 0x4001024d +.set CYREG_B0_P1_U0_CFG14, 0x4001024e +.set CYREG_B0_P1_U0_CFG15, 0x4001024f +.set CYREG_B0_P1_U0_CFG16, 0x40010250 +.set CYREG_B0_P1_U0_CFG17, 0x40010251 +.set CYREG_B0_P1_U0_CFG18, 0x40010252 +.set CYREG_B0_P1_U0_CFG19, 0x40010253 +.set CYREG_B0_P1_U0_CFG20, 0x40010254 +.set CYREG_B0_P1_U0_CFG21, 0x40010255 +.set CYREG_B0_P1_U0_CFG22, 0x40010256 +.set CYREG_B0_P1_U0_CFG23, 0x40010257 +.set CYREG_B0_P1_U0_CFG24, 0x40010258 +.set CYREG_B0_P1_U0_CFG25, 0x40010259 +.set CYREG_B0_P1_U0_CFG26, 0x4001025a +.set CYREG_B0_P1_U0_CFG27, 0x4001025b +.set CYREG_B0_P1_U0_CFG28, 0x4001025c +.set CYREG_B0_P1_U0_CFG29, 0x4001025d +.set CYREG_B0_P1_U0_CFG30, 0x4001025e +.set CYREG_B0_P1_U0_CFG31, 0x4001025f +.set CYREG_B0_P1_U0_DCFG0, 0x40010260 +.set CYREG_B0_P1_U0_DCFG1, 0x40010262 +.set CYREG_B0_P1_U0_DCFG2, 0x40010264 +.set CYREG_B0_P1_U0_DCFG3, 0x40010266 +.set CYREG_B0_P1_U0_DCFG4, 0x40010268 +.set CYREG_B0_P1_U0_DCFG5, 0x4001026a +.set CYREG_B0_P1_U0_DCFG6, 0x4001026c +.set CYREG_B0_P1_U0_DCFG7, 0x4001026e +.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 +.set CYREG_B0_P1_U1_PLD_IT0, 0x40010280 +.set CYREG_B0_P1_U1_PLD_IT1, 0x40010284 +.set CYREG_B0_P1_U1_PLD_IT2, 0x40010288 +.set CYREG_B0_P1_U1_PLD_IT3, 0x4001028c +.set CYREG_B0_P1_U1_PLD_IT4, 0x40010290 +.set CYREG_B0_P1_U1_PLD_IT5, 0x40010294 +.set CYREG_B0_P1_U1_PLD_IT6, 0x40010298 +.set CYREG_B0_P1_U1_PLD_IT7, 0x4001029c +.set CYREG_B0_P1_U1_PLD_IT8, 0x400102a0 +.set CYREG_B0_P1_U1_PLD_IT9, 0x400102a4 +.set CYREG_B0_P1_U1_PLD_IT10, 0x400102a8 +.set CYREG_B0_P1_U1_PLD_IT11, 0x400102ac +.set CYREG_B0_P1_U1_PLD_ORT0, 0x400102b0 +.set CYREG_B0_P1_U1_PLD_ORT1, 0x400102b2 +.set CYREG_B0_P1_U1_PLD_ORT2, 0x400102b4 +.set CYREG_B0_P1_U1_PLD_ORT3, 0x400102b6 +.set CYREG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 +.set CYREG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba +.set CYREG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc +.set CYREG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be +.set CYREG_B0_P1_U1_CFG0, 0x400102c0 +.set CYREG_B0_P1_U1_CFG1, 0x400102c1 +.set CYREG_B0_P1_U1_CFG2, 0x400102c2 +.set CYREG_B0_P1_U1_CFG3, 0x400102c3 +.set CYREG_B0_P1_U1_CFG4, 0x400102c4 +.set CYREG_B0_P1_U1_CFG5, 0x400102c5 +.set CYREG_B0_P1_U1_CFG6, 0x400102c6 +.set CYREG_B0_P1_U1_CFG7, 0x400102c7 +.set CYREG_B0_P1_U1_CFG8, 0x400102c8 +.set CYREG_B0_P1_U1_CFG9, 0x400102c9 +.set CYREG_B0_P1_U1_CFG10, 0x400102ca +.set CYREG_B0_P1_U1_CFG11, 0x400102cb +.set CYREG_B0_P1_U1_CFG12, 0x400102cc +.set CYREG_B0_P1_U1_CFG13, 0x400102cd +.set CYREG_B0_P1_U1_CFG14, 0x400102ce +.set CYREG_B0_P1_U1_CFG15, 0x400102cf +.set CYREG_B0_P1_U1_CFG16, 0x400102d0 +.set CYREG_B0_P1_U1_CFG17, 0x400102d1 +.set CYREG_B0_P1_U1_CFG18, 0x400102d2 +.set CYREG_B0_P1_U1_CFG19, 0x400102d3 +.set CYREG_B0_P1_U1_CFG20, 0x400102d4 +.set CYREG_B0_P1_U1_CFG21, 0x400102d5 +.set CYREG_B0_P1_U1_CFG22, 0x400102d6 +.set CYREG_B0_P1_U1_CFG23, 0x400102d7 +.set CYREG_B0_P1_U1_CFG24, 0x400102d8 +.set CYREG_B0_P1_U1_CFG25, 0x400102d9 +.set CYREG_B0_P1_U1_CFG26, 0x400102da +.set CYREG_B0_P1_U1_CFG27, 0x400102db +.set CYREG_B0_P1_U1_CFG28, 0x400102dc +.set CYREG_B0_P1_U1_CFG29, 0x400102dd +.set CYREG_B0_P1_U1_CFG30, 0x400102de +.set CYREG_B0_P1_U1_CFG31, 0x400102df +.set CYREG_B0_P1_U1_DCFG0, 0x400102e0 +.set CYREG_B0_P1_U1_DCFG1, 0x400102e2 +.set CYREG_B0_P1_U1_DCFG2, 0x400102e4 +.set CYREG_B0_P1_U1_DCFG3, 0x400102e6 +.set CYREG_B0_P1_U1_DCFG4, 0x400102e8 +.set CYREG_B0_P1_U1_DCFG5, 0x400102ea +.set CYREG_B0_P1_U1_DCFG6, 0x400102ec +.set CYREG_B0_P1_U1_DCFG7, 0x400102ee +.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 +.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P2_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 +.set CYREG_B0_P2_U0_PLD_IT0, 0x40010400 +.set CYREG_B0_P2_U0_PLD_IT1, 0x40010404 +.set CYREG_B0_P2_U0_PLD_IT2, 0x40010408 +.set CYREG_B0_P2_U0_PLD_IT3, 0x4001040c +.set CYREG_B0_P2_U0_PLD_IT4, 0x40010410 +.set CYREG_B0_P2_U0_PLD_IT5, 0x40010414 +.set CYREG_B0_P2_U0_PLD_IT6, 0x40010418 +.set CYREG_B0_P2_U0_PLD_IT7, 0x4001041c +.set CYREG_B0_P2_U0_PLD_IT8, 0x40010420 +.set CYREG_B0_P2_U0_PLD_IT9, 0x40010424 +.set CYREG_B0_P2_U0_PLD_IT10, 0x40010428 +.set CYREG_B0_P2_U0_PLD_IT11, 0x4001042c +.set CYREG_B0_P2_U0_PLD_ORT0, 0x40010430 +.set CYREG_B0_P2_U0_PLD_ORT1, 0x40010432 +.set CYREG_B0_P2_U0_PLD_ORT2, 0x40010434 +.set CYREG_B0_P2_U0_PLD_ORT3, 0x40010436 +.set CYREG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 +.set CYREG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a +.set CYREG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c +.set CYREG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e +.set CYREG_B0_P2_U0_CFG0, 0x40010440 +.set CYREG_B0_P2_U0_CFG1, 0x40010441 +.set CYREG_B0_P2_U0_CFG2, 0x40010442 +.set CYREG_B0_P2_U0_CFG3, 0x40010443 +.set CYREG_B0_P2_U0_CFG4, 0x40010444 +.set CYREG_B0_P2_U0_CFG5, 0x40010445 +.set CYREG_B0_P2_U0_CFG6, 0x40010446 +.set CYREG_B0_P2_U0_CFG7, 0x40010447 +.set CYREG_B0_P2_U0_CFG8, 0x40010448 +.set CYREG_B0_P2_U0_CFG9, 0x40010449 +.set CYREG_B0_P2_U0_CFG10, 0x4001044a +.set CYREG_B0_P2_U0_CFG11, 0x4001044b +.set CYREG_B0_P2_U0_CFG12, 0x4001044c +.set CYREG_B0_P2_U0_CFG13, 0x4001044d +.set CYREG_B0_P2_U0_CFG14, 0x4001044e +.set CYREG_B0_P2_U0_CFG15, 0x4001044f +.set CYREG_B0_P2_U0_CFG16, 0x40010450 +.set CYREG_B0_P2_U0_CFG17, 0x40010451 +.set CYREG_B0_P2_U0_CFG18, 0x40010452 +.set CYREG_B0_P2_U0_CFG19, 0x40010453 +.set CYREG_B0_P2_U0_CFG20, 0x40010454 +.set CYREG_B0_P2_U0_CFG21, 0x40010455 +.set CYREG_B0_P2_U0_CFG22, 0x40010456 +.set CYREG_B0_P2_U0_CFG23, 0x40010457 +.set CYREG_B0_P2_U0_CFG24, 0x40010458 +.set CYREG_B0_P2_U0_CFG25, 0x40010459 +.set CYREG_B0_P2_U0_CFG26, 0x4001045a +.set CYREG_B0_P2_U0_CFG27, 0x4001045b +.set CYREG_B0_P2_U0_CFG28, 0x4001045c +.set CYREG_B0_P2_U0_CFG29, 0x4001045d +.set CYREG_B0_P2_U0_CFG30, 0x4001045e +.set CYREG_B0_P2_U0_CFG31, 0x4001045f +.set CYREG_B0_P2_U0_DCFG0, 0x40010460 +.set CYREG_B0_P2_U0_DCFG1, 0x40010462 +.set CYREG_B0_P2_U0_DCFG2, 0x40010464 +.set CYREG_B0_P2_U0_DCFG3, 0x40010466 +.set CYREG_B0_P2_U0_DCFG4, 0x40010468 +.set CYREG_B0_P2_U0_DCFG5, 0x4001046a +.set CYREG_B0_P2_U0_DCFG6, 0x4001046c +.set CYREG_B0_P2_U0_DCFG7, 0x4001046e +.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 +.set CYREG_B0_P2_U1_PLD_IT0, 0x40010480 +.set CYREG_B0_P2_U1_PLD_IT1, 0x40010484 +.set CYREG_B0_P2_U1_PLD_IT2, 0x40010488 +.set CYREG_B0_P2_U1_PLD_IT3, 0x4001048c +.set CYREG_B0_P2_U1_PLD_IT4, 0x40010490 +.set CYREG_B0_P2_U1_PLD_IT5, 0x40010494 +.set CYREG_B0_P2_U1_PLD_IT6, 0x40010498 +.set CYREG_B0_P2_U1_PLD_IT7, 0x4001049c +.set CYREG_B0_P2_U1_PLD_IT8, 0x400104a0 +.set CYREG_B0_P2_U1_PLD_IT9, 0x400104a4 +.set CYREG_B0_P2_U1_PLD_IT10, 0x400104a8 +.set CYREG_B0_P2_U1_PLD_IT11, 0x400104ac +.set CYREG_B0_P2_U1_PLD_ORT0, 0x400104b0 +.set CYREG_B0_P2_U1_PLD_ORT1, 0x400104b2 +.set CYREG_B0_P2_U1_PLD_ORT2, 0x400104b4 +.set CYREG_B0_P2_U1_PLD_ORT3, 0x400104b6 +.set CYREG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 +.set CYREG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba +.set CYREG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc +.set CYREG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be +.set CYREG_B0_P2_U1_CFG0, 0x400104c0 +.set CYREG_B0_P2_U1_CFG1, 0x400104c1 +.set CYREG_B0_P2_U1_CFG2, 0x400104c2 +.set CYREG_B0_P2_U1_CFG3, 0x400104c3 +.set CYREG_B0_P2_U1_CFG4, 0x400104c4 +.set CYREG_B0_P2_U1_CFG5, 0x400104c5 +.set CYREG_B0_P2_U1_CFG6, 0x400104c6 +.set CYREG_B0_P2_U1_CFG7, 0x400104c7 +.set CYREG_B0_P2_U1_CFG8, 0x400104c8 +.set CYREG_B0_P2_U1_CFG9, 0x400104c9 +.set CYREG_B0_P2_U1_CFG10, 0x400104ca +.set CYREG_B0_P2_U1_CFG11, 0x400104cb +.set CYREG_B0_P2_U1_CFG12, 0x400104cc +.set CYREG_B0_P2_U1_CFG13, 0x400104cd +.set CYREG_B0_P2_U1_CFG14, 0x400104ce +.set CYREG_B0_P2_U1_CFG15, 0x400104cf +.set CYREG_B0_P2_U1_CFG16, 0x400104d0 +.set CYREG_B0_P2_U1_CFG17, 0x400104d1 +.set CYREG_B0_P2_U1_CFG18, 0x400104d2 +.set CYREG_B0_P2_U1_CFG19, 0x400104d3 +.set CYREG_B0_P2_U1_CFG20, 0x400104d4 +.set CYREG_B0_P2_U1_CFG21, 0x400104d5 +.set CYREG_B0_P2_U1_CFG22, 0x400104d6 +.set CYREG_B0_P2_U1_CFG23, 0x400104d7 +.set CYREG_B0_P2_U1_CFG24, 0x400104d8 +.set CYREG_B0_P2_U1_CFG25, 0x400104d9 +.set CYREG_B0_P2_U1_CFG26, 0x400104da +.set CYREG_B0_P2_U1_CFG27, 0x400104db +.set CYREG_B0_P2_U1_CFG28, 0x400104dc +.set CYREG_B0_P2_U1_CFG29, 0x400104dd +.set CYREG_B0_P2_U1_CFG30, 0x400104de +.set CYREG_B0_P2_U1_CFG31, 0x400104df +.set CYREG_B0_P2_U1_DCFG0, 0x400104e0 +.set CYREG_B0_P2_U1_DCFG1, 0x400104e2 +.set CYREG_B0_P2_U1_DCFG2, 0x400104e4 +.set CYREG_B0_P2_U1_DCFG3, 0x400104e6 +.set CYREG_B0_P2_U1_DCFG4, 0x400104e8 +.set CYREG_B0_P2_U1_DCFG5, 0x400104ea +.set CYREG_B0_P2_U1_DCFG6, 0x400104ec +.set CYREG_B0_P2_U1_DCFG7, 0x400104ee +.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 +.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P3_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 +.set CYREG_B0_P3_U0_PLD_IT0, 0x40010600 +.set CYREG_B0_P3_U0_PLD_IT1, 0x40010604 +.set CYREG_B0_P3_U0_PLD_IT2, 0x40010608 +.set CYREG_B0_P3_U0_PLD_IT3, 0x4001060c +.set CYREG_B0_P3_U0_PLD_IT4, 0x40010610 +.set CYREG_B0_P3_U0_PLD_IT5, 0x40010614 +.set CYREG_B0_P3_U0_PLD_IT6, 0x40010618 +.set CYREG_B0_P3_U0_PLD_IT7, 0x4001061c +.set CYREG_B0_P3_U0_PLD_IT8, 0x40010620 +.set CYREG_B0_P3_U0_PLD_IT9, 0x40010624 +.set CYREG_B0_P3_U0_PLD_IT10, 0x40010628 +.set CYREG_B0_P3_U0_PLD_IT11, 0x4001062c +.set CYREG_B0_P3_U0_PLD_ORT0, 0x40010630 +.set CYREG_B0_P3_U0_PLD_ORT1, 0x40010632 +.set CYREG_B0_P3_U0_PLD_ORT2, 0x40010634 +.set CYREG_B0_P3_U0_PLD_ORT3, 0x40010636 +.set CYREG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 +.set CYREG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a +.set CYREG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c +.set CYREG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e +.set CYREG_B0_P3_U0_CFG0, 0x40010640 +.set CYREG_B0_P3_U0_CFG1, 0x40010641 +.set CYREG_B0_P3_U0_CFG2, 0x40010642 +.set CYREG_B0_P3_U0_CFG3, 0x40010643 +.set CYREG_B0_P3_U0_CFG4, 0x40010644 +.set CYREG_B0_P3_U0_CFG5, 0x40010645 +.set CYREG_B0_P3_U0_CFG6, 0x40010646 +.set CYREG_B0_P3_U0_CFG7, 0x40010647 +.set CYREG_B0_P3_U0_CFG8, 0x40010648 +.set CYREG_B0_P3_U0_CFG9, 0x40010649 +.set CYREG_B0_P3_U0_CFG10, 0x4001064a +.set CYREG_B0_P3_U0_CFG11, 0x4001064b +.set CYREG_B0_P3_U0_CFG12, 0x4001064c +.set CYREG_B0_P3_U0_CFG13, 0x4001064d +.set CYREG_B0_P3_U0_CFG14, 0x4001064e +.set CYREG_B0_P3_U0_CFG15, 0x4001064f +.set CYREG_B0_P3_U0_CFG16, 0x40010650 +.set CYREG_B0_P3_U0_CFG17, 0x40010651 +.set CYREG_B0_P3_U0_CFG18, 0x40010652 +.set CYREG_B0_P3_U0_CFG19, 0x40010653 +.set CYREG_B0_P3_U0_CFG20, 0x40010654 +.set CYREG_B0_P3_U0_CFG21, 0x40010655 +.set CYREG_B0_P3_U0_CFG22, 0x40010656 +.set CYREG_B0_P3_U0_CFG23, 0x40010657 +.set CYREG_B0_P3_U0_CFG24, 0x40010658 +.set CYREG_B0_P3_U0_CFG25, 0x40010659 +.set CYREG_B0_P3_U0_CFG26, 0x4001065a +.set CYREG_B0_P3_U0_CFG27, 0x4001065b +.set CYREG_B0_P3_U0_CFG28, 0x4001065c +.set CYREG_B0_P3_U0_CFG29, 0x4001065d +.set CYREG_B0_P3_U0_CFG30, 0x4001065e +.set CYREG_B0_P3_U0_CFG31, 0x4001065f +.set CYREG_B0_P3_U0_DCFG0, 0x40010660 +.set CYREG_B0_P3_U0_DCFG1, 0x40010662 +.set CYREG_B0_P3_U0_DCFG2, 0x40010664 +.set CYREG_B0_P3_U0_DCFG3, 0x40010666 +.set CYREG_B0_P3_U0_DCFG4, 0x40010668 +.set CYREG_B0_P3_U0_DCFG5, 0x4001066a +.set CYREG_B0_P3_U0_DCFG6, 0x4001066c +.set CYREG_B0_P3_U0_DCFG7, 0x4001066e +.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 +.set CYREG_B0_P3_U1_PLD_IT0, 0x40010680 +.set CYREG_B0_P3_U1_PLD_IT1, 0x40010684 +.set CYREG_B0_P3_U1_PLD_IT2, 0x40010688 +.set CYREG_B0_P3_U1_PLD_IT3, 0x4001068c +.set CYREG_B0_P3_U1_PLD_IT4, 0x40010690 +.set CYREG_B0_P3_U1_PLD_IT5, 0x40010694 +.set CYREG_B0_P3_U1_PLD_IT6, 0x40010698 +.set CYREG_B0_P3_U1_PLD_IT7, 0x4001069c +.set CYREG_B0_P3_U1_PLD_IT8, 0x400106a0 +.set CYREG_B0_P3_U1_PLD_IT9, 0x400106a4 +.set CYREG_B0_P3_U1_PLD_IT10, 0x400106a8 +.set CYREG_B0_P3_U1_PLD_IT11, 0x400106ac +.set CYREG_B0_P3_U1_PLD_ORT0, 0x400106b0 +.set CYREG_B0_P3_U1_PLD_ORT1, 0x400106b2 +.set CYREG_B0_P3_U1_PLD_ORT2, 0x400106b4 +.set CYREG_B0_P3_U1_PLD_ORT3, 0x400106b6 +.set CYREG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 +.set CYREG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba +.set CYREG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc +.set CYREG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be +.set CYREG_B0_P3_U1_CFG0, 0x400106c0 +.set CYREG_B0_P3_U1_CFG1, 0x400106c1 +.set CYREG_B0_P3_U1_CFG2, 0x400106c2 +.set CYREG_B0_P3_U1_CFG3, 0x400106c3 +.set CYREG_B0_P3_U1_CFG4, 0x400106c4 +.set CYREG_B0_P3_U1_CFG5, 0x400106c5 +.set CYREG_B0_P3_U1_CFG6, 0x400106c6 +.set CYREG_B0_P3_U1_CFG7, 0x400106c7 +.set CYREG_B0_P3_U1_CFG8, 0x400106c8 +.set CYREG_B0_P3_U1_CFG9, 0x400106c9 +.set CYREG_B0_P3_U1_CFG10, 0x400106ca +.set CYREG_B0_P3_U1_CFG11, 0x400106cb +.set CYREG_B0_P3_U1_CFG12, 0x400106cc +.set CYREG_B0_P3_U1_CFG13, 0x400106cd +.set CYREG_B0_P3_U1_CFG14, 0x400106ce +.set CYREG_B0_P3_U1_CFG15, 0x400106cf +.set CYREG_B0_P3_U1_CFG16, 0x400106d0 +.set CYREG_B0_P3_U1_CFG17, 0x400106d1 +.set CYREG_B0_P3_U1_CFG18, 0x400106d2 +.set CYREG_B0_P3_U1_CFG19, 0x400106d3 +.set CYREG_B0_P3_U1_CFG20, 0x400106d4 +.set CYREG_B0_P3_U1_CFG21, 0x400106d5 +.set CYREG_B0_P3_U1_CFG22, 0x400106d6 +.set CYREG_B0_P3_U1_CFG23, 0x400106d7 +.set CYREG_B0_P3_U1_CFG24, 0x400106d8 +.set CYREG_B0_P3_U1_CFG25, 0x400106d9 +.set CYREG_B0_P3_U1_CFG26, 0x400106da +.set CYREG_B0_P3_U1_CFG27, 0x400106db +.set CYREG_B0_P3_U1_CFG28, 0x400106dc +.set CYREG_B0_P3_U1_CFG29, 0x400106dd +.set CYREG_B0_P3_U1_CFG30, 0x400106de +.set CYREG_B0_P3_U1_CFG31, 0x400106df +.set CYREG_B0_P3_U1_DCFG0, 0x400106e0 +.set CYREG_B0_P3_U1_DCFG1, 0x400106e2 +.set CYREG_B0_P3_U1_DCFG2, 0x400106e4 +.set CYREG_B0_P3_U1_DCFG3, 0x400106e6 +.set CYREG_B0_P3_U1_DCFG4, 0x400106e8 +.set CYREG_B0_P3_U1_DCFG5, 0x400106ea +.set CYREG_B0_P3_U1_DCFG6, 0x400106ec +.set CYREG_B0_P3_U1_DCFG7, 0x400106ee +.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 +.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P4_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 +.set CYREG_B0_P4_U0_PLD_IT0, 0x40010800 +.set CYREG_B0_P4_U0_PLD_IT1, 0x40010804 +.set CYREG_B0_P4_U0_PLD_IT2, 0x40010808 +.set CYREG_B0_P4_U0_PLD_IT3, 0x4001080c +.set CYREG_B0_P4_U0_PLD_IT4, 0x40010810 +.set CYREG_B0_P4_U0_PLD_IT5, 0x40010814 +.set CYREG_B0_P4_U0_PLD_IT6, 0x40010818 +.set CYREG_B0_P4_U0_PLD_IT7, 0x4001081c +.set CYREG_B0_P4_U0_PLD_IT8, 0x40010820 +.set CYREG_B0_P4_U0_PLD_IT9, 0x40010824 +.set CYREG_B0_P4_U0_PLD_IT10, 0x40010828 +.set CYREG_B0_P4_U0_PLD_IT11, 0x4001082c +.set CYREG_B0_P4_U0_PLD_ORT0, 0x40010830 +.set CYREG_B0_P4_U0_PLD_ORT1, 0x40010832 +.set CYREG_B0_P4_U0_PLD_ORT2, 0x40010834 +.set CYREG_B0_P4_U0_PLD_ORT3, 0x40010836 +.set CYREG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 +.set CYREG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a +.set CYREG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c +.set CYREG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e +.set CYREG_B0_P4_U0_CFG0, 0x40010840 +.set CYREG_B0_P4_U0_CFG1, 0x40010841 +.set CYREG_B0_P4_U0_CFG2, 0x40010842 +.set CYREG_B0_P4_U0_CFG3, 0x40010843 +.set CYREG_B0_P4_U0_CFG4, 0x40010844 +.set CYREG_B0_P4_U0_CFG5, 0x40010845 +.set CYREG_B0_P4_U0_CFG6, 0x40010846 +.set CYREG_B0_P4_U0_CFG7, 0x40010847 +.set CYREG_B0_P4_U0_CFG8, 0x40010848 +.set CYREG_B0_P4_U0_CFG9, 0x40010849 +.set CYREG_B0_P4_U0_CFG10, 0x4001084a +.set CYREG_B0_P4_U0_CFG11, 0x4001084b +.set CYREG_B0_P4_U0_CFG12, 0x4001084c +.set CYREG_B0_P4_U0_CFG13, 0x4001084d +.set CYREG_B0_P4_U0_CFG14, 0x4001084e +.set CYREG_B0_P4_U0_CFG15, 0x4001084f +.set CYREG_B0_P4_U0_CFG16, 0x40010850 +.set CYREG_B0_P4_U0_CFG17, 0x40010851 +.set CYREG_B0_P4_U0_CFG18, 0x40010852 +.set CYREG_B0_P4_U0_CFG19, 0x40010853 +.set CYREG_B0_P4_U0_CFG20, 0x40010854 +.set CYREG_B0_P4_U0_CFG21, 0x40010855 +.set CYREG_B0_P4_U0_CFG22, 0x40010856 +.set CYREG_B0_P4_U0_CFG23, 0x40010857 +.set CYREG_B0_P4_U0_CFG24, 0x40010858 +.set CYREG_B0_P4_U0_CFG25, 0x40010859 +.set CYREG_B0_P4_U0_CFG26, 0x4001085a +.set CYREG_B0_P4_U0_CFG27, 0x4001085b +.set CYREG_B0_P4_U0_CFG28, 0x4001085c +.set CYREG_B0_P4_U0_CFG29, 0x4001085d +.set CYREG_B0_P4_U0_CFG30, 0x4001085e +.set CYREG_B0_P4_U0_CFG31, 0x4001085f +.set CYREG_B0_P4_U0_DCFG0, 0x40010860 +.set CYREG_B0_P4_U0_DCFG1, 0x40010862 +.set CYREG_B0_P4_U0_DCFG2, 0x40010864 +.set CYREG_B0_P4_U0_DCFG3, 0x40010866 +.set CYREG_B0_P4_U0_DCFG4, 0x40010868 +.set CYREG_B0_P4_U0_DCFG5, 0x4001086a +.set CYREG_B0_P4_U0_DCFG6, 0x4001086c +.set CYREG_B0_P4_U0_DCFG7, 0x4001086e +.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 +.set CYREG_B0_P4_U1_PLD_IT0, 0x40010880 +.set CYREG_B0_P4_U1_PLD_IT1, 0x40010884 +.set CYREG_B0_P4_U1_PLD_IT2, 0x40010888 +.set CYREG_B0_P4_U1_PLD_IT3, 0x4001088c +.set CYREG_B0_P4_U1_PLD_IT4, 0x40010890 +.set CYREG_B0_P4_U1_PLD_IT5, 0x40010894 +.set CYREG_B0_P4_U1_PLD_IT6, 0x40010898 +.set CYREG_B0_P4_U1_PLD_IT7, 0x4001089c +.set CYREG_B0_P4_U1_PLD_IT8, 0x400108a0 +.set CYREG_B0_P4_U1_PLD_IT9, 0x400108a4 +.set CYREG_B0_P4_U1_PLD_IT10, 0x400108a8 +.set CYREG_B0_P4_U1_PLD_IT11, 0x400108ac +.set CYREG_B0_P4_U1_PLD_ORT0, 0x400108b0 +.set CYREG_B0_P4_U1_PLD_ORT1, 0x400108b2 +.set CYREG_B0_P4_U1_PLD_ORT2, 0x400108b4 +.set CYREG_B0_P4_U1_PLD_ORT3, 0x400108b6 +.set CYREG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 +.set CYREG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba +.set CYREG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc +.set CYREG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be +.set CYREG_B0_P4_U1_CFG0, 0x400108c0 +.set CYREG_B0_P4_U1_CFG1, 0x400108c1 +.set CYREG_B0_P4_U1_CFG2, 0x400108c2 +.set CYREG_B0_P4_U1_CFG3, 0x400108c3 +.set CYREG_B0_P4_U1_CFG4, 0x400108c4 +.set CYREG_B0_P4_U1_CFG5, 0x400108c5 +.set CYREG_B0_P4_U1_CFG6, 0x400108c6 +.set CYREG_B0_P4_U1_CFG7, 0x400108c7 +.set CYREG_B0_P4_U1_CFG8, 0x400108c8 +.set CYREG_B0_P4_U1_CFG9, 0x400108c9 +.set CYREG_B0_P4_U1_CFG10, 0x400108ca +.set CYREG_B0_P4_U1_CFG11, 0x400108cb +.set CYREG_B0_P4_U1_CFG12, 0x400108cc +.set CYREG_B0_P4_U1_CFG13, 0x400108cd +.set CYREG_B0_P4_U1_CFG14, 0x400108ce +.set CYREG_B0_P4_U1_CFG15, 0x400108cf +.set CYREG_B0_P4_U1_CFG16, 0x400108d0 +.set CYREG_B0_P4_U1_CFG17, 0x400108d1 +.set CYREG_B0_P4_U1_CFG18, 0x400108d2 +.set CYREG_B0_P4_U1_CFG19, 0x400108d3 +.set CYREG_B0_P4_U1_CFG20, 0x400108d4 +.set CYREG_B0_P4_U1_CFG21, 0x400108d5 +.set CYREG_B0_P4_U1_CFG22, 0x400108d6 +.set CYREG_B0_P4_U1_CFG23, 0x400108d7 +.set CYREG_B0_P4_U1_CFG24, 0x400108d8 +.set CYREG_B0_P4_U1_CFG25, 0x400108d9 +.set CYREG_B0_P4_U1_CFG26, 0x400108da +.set CYREG_B0_P4_U1_CFG27, 0x400108db +.set CYREG_B0_P4_U1_CFG28, 0x400108dc +.set CYREG_B0_P4_U1_CFG29, 0x400108dd +.set CYREG_B0_P4_U1_CFG30, 0x400108de +.set CYREG_B0_P4_U1_CFG31, 0x400108df +.set CYREG_B0_P4_U1_DCFG0, 0x400108e0 +.set CYREG_B0_P4_U1_DCFG1, 0x400108e2 +.set CYREG_B0_P4_U1_DCFG2, 0x400108e4 +.set CYREG_B0_P4_U1_DCFG3, 0x400108e6 +.set CYREG_B0_P4_U1_DCFG4, 0x400108e8 +.set CYREG_B0_P4_U1_DCFG5, 0x400108ea +.set CYREG_B0_P4_U1_DCFG6, 0x400108ec +.set CYREG_B0_P4_U1_DCFG7, 0x400108ee +.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 +.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 +.set CYREG_B0_P5_U0_PLD_IT0, 0x40010a00 +.set CYREG_B0_P5_U0_PLD_IT1, 0x40010a04 +.set CYREG_B0_P5_U0_PLD_IT2, 0x40010a08 +.set CYREG_B0_P5_U0_PLD_IT3, 0x40010a0c +.set CYREG_B0_P5_U0_PLD_IT4, 0x40010a10 +.set CYREG_B0_P5_U0_PLD_IT5, 0x40010a14 +.set CYREG_B0_P5_U0_PLD_IT6, 0x40010a18 +.set CYREG_B0_P5_U0_PLD_IT7, 0x40010a1c +.set CYREG_B0_P5_U0_PLD_IT8, 0x40010a20 +.set CYREG_B0_P5_U0_PLD_IT9, 0x40010a24 +.set CYREG_B0_P5_U0_PLD_IT10, 0x40010a28 +.set CYREG_B0_P5_U0_PLD_IT11, 0x40010a2c +.set CYREG_B0_P5_U0_PLD_ORT0, 0x40010a30 +.set CYREG_B0_P5_U0_PLD_ORT1, 0x40010a32 +.set CYREG_B0_P5_U0_PLD_ORT2, 0x40010a34 +.set CYREG_B0_P5_U0_PLD_ORT3, 0x40010a36 +.set CYREG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 +.set CYREG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a +.set CYREG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c +.set CYREG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e +.set CYREG_B0_P5_U0_CFG0, 0x40010a40 +.set CYREG_B0_P5_U0_CFG1, 0x40010a41 +.set CYREG_B0_P5_U0_CFG2, 0x40010a42 +.set CYREG_B0_P5_U0_CFG3, 0x40010a43 +.set CYREG_B0_P5_U0_CFG4, 0x40010a44 +.set CYREG_B0_P5_U0_CFG5, 0x40010a45 +.set CYREG_B0_P5_U0_CFG6, 0x40010a46 +.set CYREG_B0_P5_U0_CFG7, 0x40010a47 +.set CYREG_B0_P5_U0_CFG8, 0x40010a48 +.set CYREG_B0_P5_U0_CFG9, 0x40010a49 +.set CYREG_B0_P5_U0_CFG10, 0x40010a4a +.set CYREG_B0_P5_U0_CFG11, 0x40010a4b +.set CYREG_B0_P5_U0_CFG12, 0x40010a4c +.set CYREG_B0_P5_U0_CFG13, 0x40010a4d +.set CYREG_B0_P5_U0_CFG14, 0x40010a4e +.set CYREG_B0_P5_U0_CFG15, 0x40010a4f +.set CYREG_B0_P5_U0_CFG16, 0x40010a50 +.set CYREG_B0_P5_U0_CFG17, 0x40010a51 +.set CYREG_B0_P5_U0_CFG18, 0x40010a52 +.set CYREG_B0_P5_U0_CFG19, 0x40010a53 +.set CYREG_B0_P5_U0_CFG20, 0x40010a54 +.set CYREG_B0_P5_U0_CFG21, 0x40010a55 +.set CYREG_B0_P5_U0_CFG22, 0x40010a56 +.set CYREG_B0_P5_U0_CFG23, 0x40010a57 +.set CYREG_B0_P5_U0_CFG24, 0x40010a58 +.set CYREG_B0_P5_U0_CFG25, 0x40010a59 +.set CYREG_B0_P5_U0_CFG26, 0x40010a5a +.set CYREG_B0_P5_U0_CFG27, 0x40010a5b +.set CYREG_B0_P5_U0_CFG28, 0x40010a5c +.set CYREG_B0_P5_U0_CFG29, 0x40010a5d +.set CYREG_B0_P5_U0_CFG30, 0x40010a5e +.set CYREG_B0_P5_U0_CFG31, 0x40010a5f +.set CYREG_B0_P5_U0_DCFG0, 0x40010a60 +.set CYREG_B0_P5_U0_DCFG1, 0x40010a62 +.set CYREG_B0_P5_U0_DCFG2, 0x40010a64 +.set CYREG_B0_P5_U0_DCFG3, 0x40010a66 +.set CYREG_B0_P5_U0_DCFG4, 0x40010a68 +.set CYREG_B0_P5_U0_DCFG5, 0x40010a6a +.set CYREG_B0_P5_U0_DCFG6, 0x40010a6c +.set CYREG_B0_P5_U0_DCFG7, 0x40010a6e +.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 +.set CYREG_B0_P5_U1_PLD_IT0, 0x40010a80 +.set CYREG_B0_P5_U1_PLD_IT1, 0x40010a84 +.set CYREG_B0_P5_U1_PLD_IT2, 0x40010a88 +.set CYREG_B0_P5_U1_PLD_IT3, 0x40010a8c +.set CYREG_B0_P5_U1_PLD_IT4, 0x40010a90 +.set CYREG_B0_P5_U1_PLD_IT5, 0x40010a94 +.set CYREG_B0_P5_U1_PLD_IT6, 0x40010a98 +.set CYREG_B0_P5_U1_PLD_IT7, 0x40010a9c +.set CYREG_B0_P5_U1_PLD_IT8, 0x40010aa0 +.set CYREG_B0_P5_U1_PLD_IT9, 0x40010aa4 +.set CYREG_B0_P5_U1_PLD_IT10, 0x40010aa8 +.set CYREG_B0_P5_U1_PLD_IT11, 0x40010aac +.set CYREG_B0_P5_U1_PLD_ORT0, 0x40010ab0 +.set CYREG_B0_P5_U1_PLD_ORT1, 0x40010ab2 +.set CYREG_B0_P5_U1_PLD_ORT2, 0x40010ab4 +.set CYREG_B0_P5_U1_PLD_ORT3, 0x40010ab6 +.set CYREG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 +.set CYREG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba +.set CYREG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc +.set CYREG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe +.set CYREG_B0_P5_U1_CFG0, 0x40010ac0 +.set CYREG_B0_P5_U1_CFG1, 0x40010ac1 +.set CYREG_B0_P5_U1_CFG2, 0x40010ac2 +.set CYREG_B0_P5_U1_CFG3, 0x40010ac3 +.set CYREG_B0_P5_U1_CFG4, 0x40010ac4 +.set CYREG_B0_P5_U1_CFG5, 0x40010ac5 +.set CYREG_B0_P5_U1_CFG6, 0x40010ac6 +.set CYREG_B0_P5_U1_CFG7, 0x40010ac7 +.set CYREG_B0_P5_U1_CFG8, 0x40010ac8 +.set CYREG_B0_P5_U1_CFG9, 0x40010ac9 +.set CYREG_B0_P5_U1_CFG10, 0x40010aca +.set CYREG_B0_P5_U1_CFG11, 0x40010acb +.set CYREG_B0_P5_U1_CFG12, 0x40010acc +.set CYREG_B0_P5_U1_CFG13, 0x40010acd +.set CYREG_B0_P5_U1_CFG14, 0x40010ace +.set CYREG_B0_P5_U1_CFG15, 0x40010acf +.set CYREG_B0_P5_U1_CFG16, 0x40010ad0 +.set CYREG_B0_P5_U1_CFG17, 0x40010ad1 +.set CYREG_B0_P5_U1_CFG18, 0x40010ad2 +.set CYREG_B0_P5_U1_CFG19, 0x40010ad3 +.set CYREG_B0_P5_U1_CFG20, 0x40010ad4 +.set CYREG_B0_P5_U1_CFG21, 0x40010ad5 +.set CYREG_B0_P5_U1_CFG22, 0x40010ad6 +.set CYREG_B0_P5_U1_CFG23, 0x40010ad7 +.set CYREG_B0_P5_U1_CFG24, 0x40010ad8 +.set CYREG_B0_P5_U1_CFG25, 0x40010ad9 +.set CYREG_B0_P5_U1_CFG26, 0x40010ada +.set CYREG_B0_P5_U1_CFG27, 0x40010adb +.set CYREG_B0_P5_U1_CFG28, 0x40010adc +.set CYREG_B0_P5_U1_CFG29, 0x40010add +.set CYREG_B0_P5_U1_CFG30, 0x40010ade +.set CYREG_B0_P5_U1_CFG31, 0x40010adf +.set CYREG_B0_P5_U1_DCFG0, 0x40010ae0 +.set CYREG_B0_P5_U1_DCFG1, 0x40010ae2 +.set CYREG_B0_P5_U1_DCFG2, 0x40010ae4 +.set CYREG_B0_P5_U1_DCFG3, 0x40010ae6 +.set CYREG_B0_P5_U1_DCFG4, 0x40010ae8 +.set CYREG_B0_P5_U1_DCFG5, 0x40010aea +.set CYREG_B0_P5_U1_DCFG6, 0x40010aec +.set CYREG_B0_P5_U1_DCFG7, 0x40010aee +.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 +.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 +.set CYREG_B0_P6_U0_PLD_IT0, 0x40010c00 +.set CYREG_B0_P6_U0_PLD_IT1, 0x40010c04 +.set CYREG_B0_P6_U0_PLD_IT2, 0x40010c08 +.set CYREG_B0_P6_U0_PLD_IT3, 0x40010c0c +.set CYREG_B0_P6_U0_PLD_IT4, 0x40010c10 +.set CYREG_B0_P6_U0_PLD_IT5, 0x40010c14 +.set CYREG_B0_P6_U0_PLD_IT6, 0x40010c18 +.set CYREG_B0_P6_U0_PLD_IT7, 0x40010c1c +.set CYREG_B0_P6_U0_PLD_IT8, 0x40010c20 +.set CYREG_B0_P6_U0_PLD_IT9, 0x40010c24 +.set CYREG_B0_P6_U0_PLD_IT10, 0x40010c28 +.set CYREG_B0_P6_U0_PLD_IT11, 0x40010c2c +.set CYREG_B0_P6_U0_PLD_ORT0, 0x40010c30 +.set CYREG_B0_P6_U0_PLD_ORT1, 0x40010c32 +.set CYREG_B0_P6_U0_PLD_ORT2, 0x40010c34 +.set CYREG_B0_P6_U0_PLD_ORT3, 0x40010c36 +.set CYREG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 +.set CYREG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a +.set CYREG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c +.set CYREG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e +.set CYREG_B0_P6_U0_CFG0, 0x40010c40 +.set CYREG_B0_P6_U0_CFG1, 0x40010c41 +.set CYREG_B0_P6_U0_CFG2, 0x40010c42 +.set CYREG_B0_P6_U0_CFG3, 0x40010c43 +.set CYREG_B0_P6_U0_CFG4, 0x40010c44 +.set CYREG_B0_P6_U0_CFG5, 0x40010c45 +.set CYREG_B0_P6_U0_CFG6, 0x40010c46 +.set CYREG_B0_P6_U0_CFG7, 0x40010c47 +.set CYREG_B0_P6_U0_CFG8, 0x40010c48 +.set CYREG_B0_P6_U0_CFG9, 0x40010c49 +.set CYREG_B0_P6_U0_CFG10, 0x40010c4a +.set CYREG_B0_P6_U0_CFG11, 0x40010c4b +.set CYREG_B0_P6_U0_CFG12, 0x40010c4c +.set CYREG_B0_P6_U0_CFG13, 0x40010c4d +.set CYREG_B0_P6_U0_CFG14, 0x40010c4e +.set CYREG_B0_P6_U0_CFG15, 0x40010c4f +.set CYREG_B0_P6_U0_CFG16, 0x40010c50 +.set CYREG_B0_P6_U0_CFG17, 0x40010c51 +.set CYREG_B0_P6_U0_CFG18, 0x40010c52 +.set CYREG_B0_P6_U0_CFG19, 0x40010c53 +.set CYREG_B0_P6_U0_CFG20, 0x40010c54 +.set CYREG_B0_P6_U0_CFG21, 0x40010c55 +.set CYREG_B0_P6_U0_CFG22, 0x40010c56 +.set CYREG_B0_P6_U0_CFG23, 0x40010c57 +.set CYREG_B0_P6_U0_CFG24, 0x40010c58 +.set CYREG_B0_P6_U0_CFG25, 0x40010c59 +.set CYREG_B0_P6_U0_CFG26, 0x40010c5a +.set CYREG_B0_P6_U0_CFG27, 0x40010c5b +.set CYREG_B0_P6_U0_CFG28, 0x40010c5c +.set CYREG_B0_P6_U0_CFG29, 0x40010c5d +.set CYREG_B0_P6_U0_CFG30, 0x40010c5e +.set CYREG_B0_P6_U0_CFG31, 0x40010c5f +.set CYREG_B0_P6_U0_DCFG0, 0x40010c60 +.set CYREG_B0_P6_U0_DCFG1, 0x40010c62 +.set CYREG_B0_P6_U0_DCFG2, 0x40010c64 +.set CYREG_B0_P6_U0_DCFG3, 0x40010c66 +.set CYREG_B0_P6_U0_DCFG4, 0x40010c68 +.set CYREG_B0_P6_U0_DCFG5, 0x40010c6a +.set CYREG_B0_P6_U0_DCFG6, 0x40010c6c +.set CYREG_B0_P6_U0_DCFG7, 0x40010c6e +.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 +.set CYREG_B0_P6_U1_PLD_IT0, 0x40010c80 +.set CYREG_B0_P6_U1_PLD_IT1, 0x40010c84 +.set CYREG_B0_P6_U1_PLD_IT2, 0x40010c88 +.set CYREG_B0_P6_U1_PLD_IT3, 0x40010c8c +.set CYREG_B0_P6_U1_PLD_IT4, 0x40010c90 +.set CYREG_B0_P6_U1_PLD_IT5, 0x40010c94 +.set CYREG_B0_P6_U1_PLD_IT6, 0x40010c98 +.set CYREG_B0_P6_U1_PLD_IT7, 0x40010c9c +.set CYREG_B0_P6_U1_PLD_IT8, 0x40010ca0 +.set CYREG_B0_P6_U1_PLD_IT9, 0x40010ca4 +.set CYREG_B0_P6_U1_PLD_IT10, 0x40010ca8 +.set CYREG_B0_P6_U1_PLD_IT11, 0x40010cac +.set CYREG_B0_P6_U1_PLD_ORT0, 0x40010cb0 +.set CYREG_B0_P6_U1_PLD_ORT1, 0x40010cb2 +.set CYREG_B0_P6_U1_PLD_ORT2, 0x40010cb4 +.set CYREG_B0_P6_U1_PLD_ORT3, 0x40010cb6 +.set CYREG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 +.set CYREG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba +.set CYREG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc +.set CYREG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe +.set CYREG_B0_P6_U1_CFG0, 0x40010cc0 +.set CYREG_B0_P6_U1_CFG1, 0x40010cc1 +.set CYREG_B0_P6_U1_CFG2, 0x40010cc2 +.set CYREG_B0_P6_U1_CFG3, 0x40010cc3 +.set CYREG_B0_P6_U1_CFG4, 0x40010cc4 +.set CYREG_B0_P6_U1_CFG5, 0x40010cc5 +.set CYREG_B0_P6_U1_CFG6, 0x40010cc6 +.set CYREG_B0_P6_U1_CFG7, 0x40010cc7 +.set CYREG_B0_P6_U1_CFG8, 0x40010cc8 +.set CYREG_B0_P6_U1_CFG9, 0x40010cc9 +.set CYREG_B0_P6_U1_CFG10, 0x40010cca +.set CYREG_B0_P6_U1_CFG11, 0x40010ccb +.set CYREG_B0_P6_U1_CFG12, 0x40010ccc +.set CYREG_B0_P6_U1_CFG13, 0x40010ccd +.set CYREG_B0_P6_U1_CFG14, 0x40010cce +.set CYREG_B0_P6_U1_CFG15, 0x40010ccf +.set CYREG_B0_P6_U1_CFG16, 0x40010cd0 +.set CYREG_B0_P6_U1_CFG17, 0x40010cd1 +.set CYREG_B0_P6_U1_CFG18, 0x40010cd2 +.set CYREG_B0_P6_U1_CFG19, 0x40010cd3 +.set CYREG_B0_P6_U1_CFG20, 0x40010cd4 +.set CYREG_B0_P6_U1_CFG21, 0x40010cd5 +.set CYREG_B0_P6_U1_CFG22, 0x40010cd6 +.set CYREG_B0_P6_U1_CFG23, 0x40010cd7 +.set CYREG_B0_P6_U1_CFG24, 0x40010cd8 +.set CYREG_B0_P6_U1_CFG25, 0x40010cd9 +.set CYREG_B0_P6_U1_CFG26, 0x40010cda +.set CYREG_B0_P6_U1_CFG27, 0x40010cdb +.set CYREG_B0_P6_U1_CFG28, 0x40010cdc +.set CYREG_B0_P6_U1_CFG29, 0x40010cdd +.set CYREG_B0_P6_U1_CFG30, 0x40010cde +.set CYREG_B0_P6_U1_CFG31, 0x40010cdf +.set CYREG_B0_P6_U1_DCFG0, 0x40010ce0 +.set CYREG_B0_P6_U1_DCFG1, 0x40010ce2 +.set CYREG_B0_P6_U1_DCFG2, 0x40010ce4 +.set CYREG_B0_P6_U1_DCFG3, 0x40010ce6 +.set CYREG_B0_P6_U1_DCFG4, 0x40010ce8 +.set CYREG_B0_P6_U1_DCFG5, 0x40010cea +.set CYREG_B0_P6_U1_DCFG6, 0x40010cec +.set CYREG_B0_P6_U1_DCFG7, 0x40010cee +.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 +.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 +.set CYREG_B0_P7_U0_PLD_IT0, 0x40010e00 +.set CYREG_B0_P7_U0_PLD_IT1, 0x40010e04 +.set CYREG_B0_P7_U0_PLD_IT2, 0x40010e08 +.set CYREG_B0_P7_U0_PLD_IT3, 0x40010e0c +.set CYREG_B0_P7_U0_PLD_IT4, 0x40010e10 +.set CYREG_B0_P7_U0_PLD_IT5, 0x40010e14 +.set CYREG_B0_P7_U0_PLD_IT6, 0x40010e18 +.set CYREG_B0_P7_U0_PLD_IT7, 0x40010e1c +.set CYREG_B0_P7_U0_PLD_IT8, 0x40010e20 +.set CYREG_B0_P7_U0_PLD_IT9, 0x40010e24 +.set CYREG_B0_P7_U0_PLD_IT10, 0x40010e28 +.set CYREG_B0_P7_U0_PLD_IT11, 0x40010e2c +.set CYREG_B0_P7_U0_PLD_ORT0, 0x40010e30 +.set CYREG_B0_P7_U0_PLD_ORT1, 0x40010e32 +.set CYREG_B0_P7_U0_PLD_ORT2, 0x40010e34 +.set CYREG_B0_P7_U0_PLD_ORT3, 0x40010e36 +.set CYREG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 +.set CYREG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a +.set CYREG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c +.set CYREG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e +.set CYREG_B0_P7_U0_CFG0, 0x40010e40 +.set CYREG_B0_P7_U0_CFG1, 0x40010e41 +.set CYREG_B0_P7_U0_CFG2, 0x40010e42 +.set CYREG_B0_P7_U0_CFG3, 0x40010e43 +.set CYREG_B0_P7_U0_CFG4, 0x40010e44 +.set CYREG_B0_P7_U0_CFG5, 0x40010e45 +.set CYREG_B0_P7_U0_CFG6, 0x40010e46 +.set CYREG_B0_P7_U0_CFG7, 0x40010e47 +.set CYREG_B0_P7_U0_CFG8, 0x40010e48 +.set CYREG_B0_P7_U0_CFG9, 0x40010e49 +.set CYREG_B0_P7_U0_CFG10, 0x40010e4a +.set CYREG_B0_P7_U0_CFG11, 0x40010e4b +.set CYREG_B0_P7_U0_CFG12, 0x40010e4c +.set CYREG_B0_P7_U0_CFG13, 0x40010e4d +.set CYREG_B0_P7_U0_CFG14, 0x40010e4e +.set CYREG_B0_P7_U0_CFG15, 0x40010e4f +.set CYREG_B0_P7_U0_CFG16, 0x40010e50 +.set CYREG_B0_P7_U0_CFG17, 0x40010e51 +.set CYREG_B0_P7_U0_CFG18, 0x40010e52 +.set CYREG_B0_P7_U0_CFG19, 0x40010e53 +.set CYREG_B0_P7_U0_CFG20, 0x40010e54 +.set CYREG_B0_P7_U0_CFG21, 0x40010e55 +.set CYREG_B0_P7_U0_CFG22, 0x40010e56 +.set CYREG_B0_P7_U0_CFG23, 0x40010e57 +.set CYREG_B0_P7_U0_CFG24, 0x40010e58 +.set CYREG_B0_P7_U0_CFG25, 0x40010e59 +.set CYREG_B0_P7_U0_CFG26, 0x40010e5a +.set CYREG_B0_P7_U0_CFG27, 0x40010e5b +.set CYREG_B0_P7_U0_CFG28, 0x40010e5c +.set CYREG_B0_P7_U0_CFG29, 0x40010e5d +.set CYREG_B0_P7_U0_CFG30, 0x40010e5e +.set CYREG_B0_P7_U0_CFG31, 0x40010e5f +.set CYREG_B0_P7_U0_DCFG0, 0x40010e60 +.set CYREG_B0_P7_U0_DCFG1, 0x40010e62 +.set CYREG_B0_P7_U0_DCFG2, 0x40010e64 +.set CYREG_B0_P7_U0_DCFG3, 0x40010e66 +.set CYREG_B0_P7_U0_DCFG4, 0x40010e68 +.set CYREG_B0_P7_U0_DCFG5, 0x40010e6a +.set CYREG_B0_P7_U0_DCFG6, 0x40010e6c +.set CYREG_B0_P7_U0_DCFG7, 0x40010e6e +.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 +.set CYREG_B0_P7_U1_PLD_IT0, 0x40010e80 +.set CYREG_B0_P7_U1_PLD_IT1, 0x40010e84 +.set CYREG_B0_P7_U1_PLD_IT2, 0x40010e88 +.set CYREG_B0_P7_U1_PLD_IT3, 0x40010e8c +.set CYREG_B0_P7_U1_PLD_IT4, 0x40010e90 +.set CYREG_B0_P7_U1_PLD_IT5, 0x40010e94 +.set CYREG_B0_P7_U1_PLD_IT6, 0x40010e98 +.set CYREG_B0_P7_U1_PLD_IT7, 0x40010e9c +.set CYREG_B0_P7_U1_PLD_IT8, 0x40010ea0 +.set CYREG_B0_P7_U1_PLD_IT9, 0x40010ea4 +.set CYREG_B0_P7_U1_PLD_IT10, 0x40010ea8 +.set CYREG_B0_P7_U1_PLD_IT11, 0x40010eac +.set CYREG_B0_P7_U1_PLD_ORT0, 0x40010eb0 +.set CYREG_B0_P7_U1_PLD_ORT1, 0x40010eb2 +.set CYREG_B0_P7_U1_PLD_ORT2, 0x40010eb4 +.set CYREG_B0_P7_U1_PLD_ORT3, 0x40010eb6 +.set CYREG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 +.set CYREG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba +.set CYREG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc +.set CYREG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe +.set CYREG_B0_P7_U1_CFG0, 0x40010ec0 +.set CYREG_B0_P7_U1_CFG1, 0x40010ec1 +.set CYREG_B0_P7_U1_CFG2, 0x40010ec2 +.set CYREG_B0_P7_U1_CFG3, 0x40010ec3 +.set CYREG_B0_P7_U1_CFG4, 0x40010ec4 +.set CYREG_B0_P7_U1_CFG5, 0x40010ec5 +.set CYREG_B0_P7_U1_CFG6, 0x40010ec6 +.set CYREG_B0_P7_U1_CFG7, 0x40010ec7 +.set CYREG_B0_P7_U1_CFG8, 0x40010ec8 +.set CYREG_B0_P7_U1_CFG9, 0x40010ec9 +.set CYREG_B0_P7_U1_CFG10, 0x40010eca +.set CYREG_B0_P7_U1_CFG11, 0x40010ecb +.set CYREG_B0_P7_U1_CFG12, 0x40010ecc +.set CYREG_B0_P7_U1_CFG13, 0x40010ecd +.set CYREG_B0_P7_U1_CFG14, 0x40010ece +.set CYREG_B0_P7_U1_CFG15, 0x40010ecf +.set CYREG_B0_P7_U1_CFG16, 0x40010ed0 +.set CYREG_B0_P7_U1_CFG17, 0x40010ed1 +.set CYREG_B0_P7_U1_CFG18, 0x40010ed2 +.set CYREG_B0_P7_U1_CFG19, 0x40010ed3 +.set CYREG_B0_P7_U1_CFG20, 0x40010ed4 +.set CYREG_B0_P7_U1_CFG21, 0x40010ed5 +.set CYREG_B0_P7_U1_CFG22, 0x40010ed6 +.set CYREG_B0_P7_U1_CFG23, 0x40010ed7 +.set CYREG_B0_P7_U1_CFG24, 0x40010ed8 +.set CYREG_B0_P7_U1_CFG25, 0x40010ed9 +.set CYREG_B0_P7_U1_CFG26, 0x40010eda +.set CYREG_B0_P7_U1_CFG27, 0x40010edb +.set CYREG_B0_P7_U1_CFG28, 0x40010edc +.set CYREG_B0_P7_U1_CFG29, 0x40010edd +.set CYREG_B0_P7_U1_CFG30, 0x40010ede +.set CYREG_B0_P7_U1_CFG31, 0x40010edf +.set CYREG_B0_P7_U1_DCFG0, 0x40010ee0 +.set CYREG_B0_P7_U1_DCFG1, 0x40010ee2 +.set CYREG_B0_P7_U1_DCFG2, 0x40010ee4 +.set CYREG_B0_P7_U1_DCFG3, 0x40010ee6 +.set CYREG_B0_P7_U1_DCFG4, 0x40010ee8 +.set CYREG_B0_P7_U1_DCFG5, 0x40010eea +.set CYREG_B0_P7_U1_DCFG6, 0x40010eec +.set CYREG_B0_P7_U1_DCFG7, 0x40010eee +.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 +.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_BASE, 0x40011000 +.set CYDEV_UCFG_B1_SIZE, 0x00000fef +.set CYDEV_UCFG_B1_P2_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 +.set CYREG_B1_P2_U0_PLD_IT0, 0x40011400 +.set CYREG_B1_P2_U0_PLD_IT1, 0x40011404 +.set CYREG_B1_P2_U0_PLD_IT2, 0x40011408 +.set CYREG_B1_P2_U0_PLD_IT3, 0x4001140c +.set CYREG_B1_P2_U0_PLD_IT4, 0x40011410 +.set CYREG_B1_P2_U0_PLD_IT5, 0x40011414 +.set CYREG_B1_P2_U0_PLD_IT6, 0x40011418 +.set CYREG_B1_P2_U0_PLD_IT7, 0x4001141c +.set CYREG_B1_P2_U0_PLD_IT8, 0x40011420 +.set CYREG_B1_P2_U0_PLD_IT9, 0x40011424 +.set CYREG_B1_P2_U0_PLD_IT10, 0x40011428 +.set CYREG_B1_P2_U0_PLD_IT11, 0x4001142c +.set CYREG_B1_P2_U0_PLD_ORT0, 0x40011430 +.set CYREG_B1_P2_U0_PLD_ORT1, 0x40011432 +.set CYREG_B1_P2_U0_PLD_ORT2, 0x40011434 +.set CYREG_B1_P2_U0_PLD_ORT3, 0x40011436 +.set CYREG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 +.set CYREG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a +.set CYREG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c +.set CYREG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e +.set CYREG_B1_P2_U0_CFG0, 0x40011440 +.set CYREG_B1_P2_U0_CFG1, 0x40011441 +.set CYREG_B1_P2_U0_CFG2, 0x40011442 +.set CYREG_B1_P2_U0_CFG3, 0x40011443 +.set CYREG_B1_P2_U0_CFG4, 0x40011444 +.set CYREG_B1_P2_U0_CFG5, 0x40011445 +.set CYREG_B1_P2_U0_CFG6, 0x40011446 +.set CYREG_B1_P2_U0_CFG7, 0x40011447 +.set CYREG_B1_P2_U0_CFG8, 0x40011448 +.set CYREG_B1_P2_U0_CFG9, 0x40011449 +.set CYREG_B1_P2_U0_CFG10, 0x4001144a +.set CYREG_B1_P2_U0_CFG11, 0x4001144b +.set CYREG_B1_P2_U0_CFG12, 0x4001144c +.set CYREG_B1_P2_U0_CFG13, 0x4001144d +.set CYREG_B1_P2_U0_CFG14, 0x4001144e +.set CYREG_B1_P2_U0_CFG15, 0x4001144f +.set CYREG_B1_P2_U0_CFG16, 0x40011450 +.set CYREG_B1_P2_U0_CFG17, 0x40011451 +.set CYREG_B1_P2_U0_CFG18, 0x40011452 +.set CYREG_B1_P2_U0_CFG19, 0x40011453 +.set CYREG_B1_P2_U0_CFG20, 0x40011454 +.set CYREG_B1_P2_U0_CFG21, 0x40011455 +.set CYREG_B1_P2_U0_CFG22, 0x40011456 +.set CYREG_B1_P2_U0_CFG23, 0x40011457 +.set CYREG_B1_P2_U0_CFG24, 0x40011458 +.set CYREG_B1_P2_U0_CFG25, 0x40011459 +.set CYREG_B1_P2_U0_CFG26, 0x4001145a +.set CYREG_B1_P2_U0_CFG27, 0x4001145b +.set CYREG_B1_P2_U0_CFG28, 0x4001145c +.set CYREG_B1_P2_U0_CFG29, 0x4001145d +.set CYREG_B1_P2_U0_CFG30, 0x4001145e +.set CYREG_B1_P2_U0_CFG31, 0x4001145f +.set CYREG_B1_P2_U0_DCFG0, 0x40011460 +.set CYREG_B1_P2_U0_DCFG1, 0x40011462 +.set CYREG_B1_P2_U0_DCFG2, 0x40011464 +.set CYREG_B1_P2_U0_DCFG3, 0x40011466 +.set CYREG_B1_P2_U0_DCFG4, 0x40011468 +.set CYREG_B1_P2_U0_DCFG5, 0x4001146a +.set CYREG_B1_P2_U0_DCFG6, 0x4001146c +.set CYREG_B1_P2_U0_DCFG7, 0x4001146e +.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 +.set CYREG_B1_P2_U1_PLD_IT0, 0x40011480 +.set CYREG_B1_P2_U1_PLD_IT1, 0x40011484 +.set CYREG_B1_P2_U1_PLD_IT2, 0x40011488 +.set CYREG_B1_P2_U1_PLD_IT3, 0x4001148c +.set CYREG_B1_P2_U1_PLD_IT4, 0x40011490 +.set CYREG_B1_P2_U1_PLD_IT5, 0x40011494 +.set CYREG_B1_P2_U1_PLD_IT6, 0x40011498 +.set CYREG_B1_P2_U1_PLD_IT7, 0x4001149c +.set CYREG_B1_P2_U1_PLD_IT8, 0x400114a0 +.set CYREG_B1_P2_U1_PLD_IT9, 0x400114a4 +.set CYREG_B1_P2_U1_PLD_IT10, 0x400114a8 +.set CYREG_B1_P2_U1_PLD_IT11, 0x400114ac +.set CYREG_B1_P2_U1_PLD_ORT0, 0x400114b0 +.set CYREG_B1_P2_U1_PLD_ORT1, 0x400114b2 +.set CYREG_B1_P2_U1_PLD_ORT2, 0x400114b4 +.set CYREG_B1_P2_U1_PLD_ORT3, 0x400114b6 +.set CYREG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 +.set CYREG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba +.set CYREG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc +.set CYREG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be +.set CYREG_B1_P2_U1_CFG0, 0x400114c0 +.set CYREG_B1_P2_U1_CFG1, 0x400114c1 +.set CYREG_B1_P2_U1_CFG2, 0x400114c2 +.set CYREG_B1_P2_U1_CFG3, 0x400114c3 +.set CYREG_B1_P2_U1_CFG4, 0x400114c4 +.set CYREG_B1_P2_U1_CFG5, 0x400114c5 +.set CYREG_B1_P2_U1_CFG6, 0x400114c6 +.set CYREG_B1_P2_U1_CFG7, 0x400114c7 +.set CYREG_B1_P2_U1_CFG8, 0x400114c8 +.set CYREG_B1_P2_U1_CFG9, 0x400114c9 +.set CYREG_B1_P2_U1_CFG10, 0x400114ca +.set CYREG_B1_P2_U1_CFG11, 0x400114cb +.set CYREG_B1_P2_U1_CFG12, 0x400114cc +.set CYREG_B1_P2_U1_CFG13, 0x400114cd +.set CYREG_B1_P2_U1_CFG14, 0x400114ce +.set CYREG_B1_P2_U1_CFG15, 0x400114cf +.set CYREG_B1_P2_U1_CFG16, 0x400114d0 +.set CYREG_B1_P2_U1_CFG17, 0x400114d1 +.set CYREG_B1_P2_U1_CFG18, 0x400114d2 +.set CYREG_B1_P2_U1_CFG19, 0x400114d3 +.set CYREG_B1_P2_U1_CFG20, 0x400114d4 +.set CYREG_B1_P2_U1_CFG21, 0x400114d5 +.set CYREG_B1_P2_U1_CFG22, 0x400114d6 +.set CYREG_B1_P2_U1_CFG23, 0x400114d7 +.set CYREG_B1_P2_U1_CFG24, 0x400114d8 +.set CYREG_B1_P2_U1_CFG25, 0x400114d9 +.set CYREG_B1_P2_U1_CFG26, 0x400114da +.set CYREG_B1_P2_U1_CFG27, 0x400114db +.set CYREG_B1_P2_U1_CFG28, 0x400114dc +.set CYREG_B1_P2_U1_CFG29, 0x400114dd +.set CYREG_B1_P2_U1_CFG30, 0x400114de +.set CYREG_B1_P2_U1_CFG31, 0x400114df +.set CYREG_B1_P2_U1_DCFG0, 0x400114e0 +.set CYREG_B1_P2_U1_DCFG1, 0x400114e2 +.set CYREG_B1_P2_U1_DCFG2, 0x400114e4 +.set CYREG_B1_P2_U1_DCFG3, 0x400114e6 +.set CYREG_B1_P2_U1_DCFG4, 0x400114e8 +.set CYREG_B1_P2_U1_DCFG5, 0x400114ea +.set CYREG_B1_P2_U1_DCFG6, 0x400114ec +.set CYREG_B1_P2_U1_DCFG7, 0x400114ee +.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 +.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P3_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 +.set CYREG_B1_P3_U0_PLD_IT0, 0x40011600 +.set CYREG_B1_P3_U0_PLD_IT1, 0x40011604 +.set CYREG_B1_P3_U0_PLD_IT2, 0x40011608 +.set CYREG_B1_P3_U0_PLD_IT3, 0x4001160c +.set CYREG_B1_P3_U0_PLD_IT4, 0x40011610 +.set CYREG_B1_P3_U0_PLD_IT5, 0x40011614 +.set CYREG_B1_P3_U0_PLD_IT6, 0x40011618 +.set CYREG_B1_P3_U0_PLD_IT7, 0x4001161c +.set CYREG_B1_P3_U0_PLD_IT8, 0x40011620 +.set CYREG_B1_P3_U0_PLD_IT9, 0x40011624 +.set CYREG_B1_P3_U0_PLD_IT10, 0x40011628 +.set CYREG_B1_P3_U0_PLD_IT11, 0x4001162c +.set CYREG_B1_P3_U0_PLD_ORT0, 0x40011630 +.set CYREG_B1_P3_U0_PLD_ORT1, 0x40011632 +.set CYREG_B1_P3_U0_PLD_ORT2, 0x40011634 +.set CYREG_B1_P3_U0_PLD_ORT3, 0x40011636 +.set CYREG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 +.set CYREG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a +.set CYREG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c +.set CYREG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e +.set CYREG_B1_P3_U0_CFG0, 0x40011640 +.set CYREG_B1_P3_U0_CFG1, 0x40011641 +.set CYREG_B1_P3_U0_CFG2, 0x40011642 +.set CYREG_B1_P3_U0_CFG3, 0x40011643 +.set CYREG_B1_P3_U0_CFG4, 0x40011644 +.set CYREG_B1_P3_U0_CFG5, 0x40011645 +.set CYREG_B1_P3_U0_CFG6, 0x40011646 +.set CYREG_B1_P3_U0_CFG7, 0x40011647 +.set CYREG_B1_P3_U0_CFG8, 0x40011648 +.set CYREG_B1_P3_U0_CFG9, 0x40011649 +.set CYREG_B1_P3_U0_CFG10, 0x4001164a +.set CYREG_B1_P3_U0_CFG11, 0x4001164b +.set CYREG_B1_P3_U0_CFG12, 0x4001164c +.set CYREG_B1_P3_U0_CFG13, 0x4001164d +.set CYREG_B1_P3_U0_CFG14, 0x4001164e +.set CYREG_B1_P3_U0_CFG15, 0x4001164f +.set CYREG_B1_P3_U0_CFG16, 0x40011650 +.set CYREG_B1_P3_U0_CFG17, 0x40011651 +.set CYREG_B1_P3_U0_CFG18, 0x40011652 +.set CYREG_B1_P3_U0_CFG19, 0x40011653 +.set CYREG_B1_P3_U0_CFG20, 0x40011654 +.set CYREG_B1_P3_U0_CFG21, 0x40011655 +.set CYREG_B1_P3_U0_CFG22, 0x40011656 +.set CYREG_B1_P3_U0_CFG23, 0x40011657 +.set CYREG_B1_P3_U0_CFG24, 0x40011658 +.set CYREG_B1_P3_U0_CFG25, 0x40011659 +.set CYREG_B1_P3_U0_CFG26, 0x4001165a +.set CYREG_B1_P3_U0_CFG27, 0x4001165b +.set CYREG_B1_P3_U0_CFG28, 0x4001165c +.set CYREG_B1_P3_U0_CFG29, 0x4001165d +.set CYREG_B1_P3_U0_CFG30, 0x4001165e +.set CYREG_B1_P3_U0_CFG31, 0x4001165f +.set CYREG_B1_P3_U0_DCFG0, 0x40011660 +.set CYREG_B1_P3_U0_DCFG1, 0x40011662 +.set CYREG_B1_P3_U0_DCFG2, 0x40011664 +.set CYREG_B1_P3_U0_DCFG3, 0x40011666 +.set CYREG_B1_P3_U0_DCFG4, 0x40011668 +.set CYREG_B1_P3_U0_DCFG5, 0x4001166a +.set CYREG_B1_P3_U0_DCFG6, 0x4001166c +.set CYREG_B1_P3_U0_DCFG7, 0x4001166e +.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 +.set CYREG_B1_P3_U1_PLD_IT0, 0x40011680 +.set CYREG_B1_P3_U1_PLD_IT1, 0x40011684 +.set CYREG_B1_P3_U1_PLD_IT2, 0x40011688 +.set CYREG_B1_P3_U1_PLD_IT3, 0x4001168c +.set CYREG_B1_P3_U1_PLD_IT4, 0x40011690 +.set CYREG_B1_P3_U1_PLD_IT5, 0x40011694 +.set CYREG_B1_P3_U1_PLD_IT6, 0x40011698 +.set CYREG_B1_P3_U1_PLD_IT7, 0x4001169c +.set CYREG_B1_P3_U1_PLD_IT8, 0x400116a0 +.set CYREG_B1_P3_U1_PLD_IT9, 0x400116a4 +.set CYREG_B1_P3_U1_PLD_IT10, 0x400116a8 +.set CYREG_B1_P3_U1_PLD_IT11, 0x400116ac +.set CYREG_B1_P3_U1_PLD_ORT0, 0x400116b0 +.set CYREG_B1_P3_U1_PLD_ORT1, 0x400116b2 +.set CYREG_B1_P3_U1_PLD_ORT2, 0x400116b4 +.set CYREG_B1_P3_U1_PLD_ORT3, 0x400116b6 +.set CYREG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 +.set CYREG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba +.set CYREG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc +.set CYREG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be +.set CYREG_B1_P3_U1_CFG0, 0x400116c0 +.set CYREG_B1_P3_U1_CFG1, 0x400116c1 +.set CYREG_B1_P3_U1_CFG2, 0x400116c2 +.set CYREG_B1_P3_U1_CFG3, 0x400116c3 +.set CYREG_B1_P3_U1_CFG4, 0x400116c4 +.set CYREG_B1_P3_U1_CFG5, 0x400116c5 +.set CYREG_B1_P3_U1_CFG6, 0x400116c6 +.set CYREG_B1_P3_U1_CFG7, 0x400116c7 +.set CYREG_B1_P3_U1_CFG8, 0x400116c8 +.set CYREG_B1_P3_U1_CFG9, 0x400116c9 +.set CYREG_B1_P3_U1_CFG10, 0x400116ca +.set CYREG_B1_P3_U1_CFG11, 0x400116cb +.set CYREG_B1_P3_U1_CFG12, 0x400116cc +.set CYREG_B1_P3_U1_CFG13, 0x400116cd +.set CYREG_B1_P3_U1_CFG14, 0x400116ce +.set CYREG_B1_P3_U1_CFG15, 0x400116cf +.set CYREG_B1_P3_U1_CFG16, 0x400116d0 +.set CYREG_B1_P3_U1_CFG17, 0x400116d1 +.set CYREG_B1_P3_U1_CFG18, 0x400116d2 +.set CYREG_B1_P3_U1_CFG19, 0x400116d3 +.set CYREG_B1_P3_U1_CFG20, 0x400116d4 +.set CYREG_B1_P3_U1_CFG21, 0x400116d5 +.set CYREG_B1_P3_U1_CFG22, 0x400116d6 +.set CYREG_B1_P3_U1_CFG23, 0x400116d7 +.set CYREG_B1_P3_U1_CFG24, 0x400116d8 +.set CYREG_B1_P3_U1_CFG25, 0x400116d9 +.set CYREG_B1_P3_U1_CFG26, 0x400116da +.set CYREG_B1_P3_U1_CFG27, 0x400116db +.set CYREG_B1_P3_U1_CFG28, 0x400116dc +.set CYREG_B1_P3_U1_CFG29, 0x400116dd +.set CYREG_B1_P3_U1_CFG30, 0x400116de +.set CYREG_B1_P3_U1_CFG31, 0x400116df +.set CYREG_B1_P3_U1_DCFG0, 0x400116e0 +.set CYREG_B1_P3_U1_DCFG1, 0x400116e2 +.set CYREG_B1_P3_U1_DCFG2, 0x400116e4 +.set CYREG_B1_P3_U1_DCFG3, 0x400116e6 +.set CYREG_B1_P3_U1_DCFG4, 0x400116e8 +.set CYREG_B1_P3_U1_DCFG5, 0x400116ea +.set CYREG_B1_P3_U1_DCFG6, 0x400116ec +.set CYREG_B1_P3_U1_DCFG7, 0x400116ee +.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 +.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P4_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 +.set CYREG_B1_P4_U0_PLD_IT0, 0x40011800 +.set CYREG_B1_P4_U0_PLD_IT1, 0x40011804 +.set CYREG_B1_P4_U0_PLD_IT2, 0x40011808 +.set CYREG_B1_P4_U0_PLD_IT3, 0x4001180c +.set CYREG_B1_P4_U0_PLD_IT4, 0x40011810 +.set CYREG_B1_P4_U0_PLD_IT5, 0x40011814 +.set CYREG_B1_P4_U0_PLD_IT6, 0x40011818 +.set CYREG_B1_P4_U0_PLD_IT7, 0x4001181c +.set CYREG_B1_P4_U0_PLD_IT8, 0x40011820 +.set CYREG_B1_P4_U0_PLD_IT9, 0x40011824 +.set CYREG_B1_P4_U0_PLD_IT10, 0x40011828 +.set CYREG_B1_P4_U0_PLD_IT11, 0x4001182c +.set CYREG_B1_P4_U0_PLD_ORT0, 0x40011830 +.set CYREG_B1_P4_U0_PLD_ORT1, 0x40011832 +.set CYREG_B1_P4_U0_PLD_ORT2, 0x40011834 +.set CYREG_B1_P4_U0_PLD_ORT3, 0x40011836 +.set CYREG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 +.set CYREG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a +.set CYREG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c +.set CYREG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e +.set CYREG_B1_P4_U0_CFG0, 0x40011840 +.set CYREG_B1_P4_U0_CFG1, 0x40011841 +.set CYREG_B1_P4_U0_CFG2, 0x40011842 +.set CYREG_B1_P4_U0_CFG3, 0x40011843 +.set CYREG_B1_P4_U0_CFG4, 0x40011844 +.set CYREG_B1_P4_U0_CFG5, 0x40011845 +.set CYREG_B1_P4_U0_CFG6, 0x40011846 +.set CYREG_B1_P4_U0_CFG7, 0x40011847 +.set CYREG_B1_P4_U0_CFG8, 0x40011848 +.set CYREG_B1_P4_U0_CFG9, 0x40011849 +.set CYREG_B1_P4_U0_CFG10, 0x4001184a +.set CYREG_B1_P4_U0_CFG11, 0x4001184b +.set CYREG_B1_P4_U0_CFG12, 0x4001184c +.set CYREG_B1_P4_U0_CFG13, 0x4001184d +.set CYREG_B1_P4_U0_CFG14, 0x4001184e +.set CYREG_B1_P4_U0_CFG15, 0x4001184f +.set CYREG_B1_P4_U0_CFG16, 0x40011850 +.set CYREG_B1_P4_U0_CFG17, 0x40011851 +.set CYREG_B1_P4_U0_CFG18, 0x40011852 +.set CYREG_B1_P4_U0_CFG19, 0x40011853 +.set CYREG_B1_P4_U0_CFG20, 0x40011854 +.set CYREG_B1_P4_U0_CFG21, 0x40011855 +.set CYREG_B1_P4_U0_CFG22, 0x40011856 +.set CYREG_B1_P4_U0_CFG23, 0x40011857 +.set CYREG_B1_P4_U0_CFG24, 0x40011858 +.set CYREG_B1_P4_U0_CFG25, 0x40011859 +.set CYREG_B1_P4_U0_CFG26, 0x4001185a +.set CYREG_B1_P4_U0_CFG27, 0x4001185b +.set CYREG_B1_P4_U0_CFG28, 0x4001185c +.set CYREG_B1_P4_U0_CFG29, 0x4001185d +.set CYREG_B1_P4_U0_CFG30, 0x4001185e +.set CYREG_B1_P4_U0_CFG31, 0x4001185f +.set CYREG_B1_P4_U0_DCFG0, 0x40011860 +.set CYREG_B1_P4_U0_DCFG1, 0x40011862 +.set CYREG_B1_P4_U0_DCFG2, 0x40011864 +.set CYREG_B1_P4_U0_DCFG3, 0x40011866 +.set CYREG_B1_P4_U0_DCFG4, 0x40011868 +.set CYREG_B1_P4_U0_DCFG5, 0x4001186a +.set CYREG_B1_P4_U0_DCFG6, 0x4001186c +.set CYREG_B1_P4_U0_DCFG7, 0x4001186e +.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 +.set CYREG_B1_P4_U1_PLD_IT0, 0x40011880 +.set CYREG_B1_P4_U1_PLD_IT1, 0x40011884 +.set CYREG_B1_P4_U1_PLD_IT2, 0x40011888 +.set CYREG_B1_P4_U1_PLD_IT3, 0x4001188c +.set CYREG_B1_P4_U1_PLD_IT4, 0x40011890 +.set CYREG_B1_P4_U1_PLD_IT5, 0x40011894 +.set CYREG_B1_P4_U1_PLD_IT6, 0x40011898 +.set CYREG_B1_P4_U1_PLD_IT7, 0x4001189c +.set CYREG_B1_P4_U1_PLD_IT8, 0x400118a0 +.set CYREG_B1_P4_U1_PLD_IT9, 0x400118a4 +.set CYREG_B1_P4_U1_PLD_IT10, 0x400118a8 +.set CYREG_B1_P4_U1_PLD_IT11, 0x400118ac +.set CYREG_B1_P4_U1_PLD_ORT0, 0x400118b0 +.set CYREG_B1_P4_U1_PLD_ORT1, 0x400118b2 +.set CYREG_B1_P4_U1_PLD_ORT2, 0x400118b4 +.set CYREG_B1_P4_U1_PLD_ORT3, 0x400118b6 +.set CYREG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 +.set CYREG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba +.set CYREG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc +.set CYREG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be +.set CYREG_B1_P4_U1_CFG0, 0x400118c0 +.set CYREG_B1_P4_U1_CFG1, 0x400118c1 +.set CYREG_B1_P4_U1_CFG2, 0x400118c2 +.set CYREG_B1_P4_U1_CFG3, 0x400118c3 +.set CYREG_B1_P4_U1_CFG4, 0x400118c4 +.set CYREG_B1_P4_U1_CFG5, 0x400118c5 +.set CYREG_B1_P4_U1_CFG6, 0x400118c6 +.set CYREG_B1_P4_U1_CFG7, 0x400118c7 +.set CYREG_B1_P4_U1_CFG8, 0x400118c8 +.set CYREG_B1_P4_U1_CFG9, 0x400118c9 +.set CYREG_B1_P4_U1_CFG10, 0x400118ca +.set CYREG_B1_P4_U1_CFG11, 0x400118cb +.set CYREG_B1_P4_U1_CFG12, 0x400118cc +.set CYREG_B1_P4_U1_CFG13, 0x400118cd +.set CYREG_B1_P4_U1_CFG14, 0x400118ce +.set CYREG_B1_P4_U1_CFG15, 0x400118cf +.set CYREG_B1_P4_U1_CFG16, 0x400118d0 +.set CYREG_B1_P4_U1_CFG17, 0x400118d1 +.set CYREG_B1_P4_U1_CFG18, 0x400118d2 +.set CYREG_B1_P4_U1_CFG19, 0x400118d3 +.set CYREG_B1_P4_U1_CFG20, 0x400118d4 +.set CYREG_B1_P4_U1_CFG21, 0x400118d5 +.set CYREG_B1_P4_U1_CFG22, 0x400118d6 +.set CYREG_B1_P4_U1_CFG23, 0x400118d7 +.set CYREG_B1_P4_U1_CFG24, 0x400118d8 +.set CYREG_B1_P4_U1_CFG25, 0x400118d9 +.set CYREG_B1_P4_U1_CFG26, 0x400118da +.set CYREG_B1_P4_U1_CFG27, 0x400118db +.set CYREG_B1_P4_U1_CFG28, 0x400118dc +.set CYREG_B1_P4_U1_CFG29, 0x400118dd +.set CYREG_B1_P4_U1_CFG30, 0x400118de +.set CYREG_B1_P4_U1_CFG31, 0x400118df +.set CYREG_B1_P4_U1_DCFG0, 0x400118e0 +.set CYREG_B1_P4_U1_DCFG1, 0x400118e2 +.set CYREG_B1_P4_U1_DCFG2, 0x400118e4 +.set CYREG_B1_P4_U1_DCFG3, 0x400118e6 +.set CYREG_B1_P4_U1_DCFG4, 0x400118e8 +.set CYREG_B1_P4_U1_DCFG5, 0x400118ea +.set CYREG_B1_P4_U1_DCFG6, 0x400118ec +.set CYREG_B1_P4_U1_DCFG7, 0x400118ee +.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 +.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 +.set CYREG_B1_P5_U0_PLD_IT0, 0x40011a00 +.set CYREG_B1_P5_U0_PLD_IT1, 0x40011a04 +.set CYREG_B1_P5_U0_PLD_IT2, 0x40011a08 +.set CYREG_B1_P5_U0_PLD_IT3, 0x40011a0c +.set CYREG_B1_P5_U0_PLD_IT4, 0x40011a10 +.set CYREG_B1_P5_U0_PLD_IT5, 0x40011a14 +.set CYREG_B1_P5_U0_PLD_IT6, 0x40011a18 +.set CYREG_B1_P5_U0_PLD_IT7, 0x40011a1c +.set CYREG_B1_P5_U0_PLD_IT8, 0x40011a20 +.set CYREG_B1_P5_U0_PLD_IT9, 0x40011a24 +.set CYREG_B1_P5_U0_PLD_IT10, 0x40011a28 +.set CYREG_B1_P5_U0_PLD_IT11, 0x40011a2c +.set CYREG_B1_P5_U0_PLD_ORT0, 0x40011a30 +.set CYREG_B1_P5_U0_PLD_ORT1, 0x40011a32 +.set CYREG_B1_P5_U0_PLD_ORT2, 0x40011a34 +.set CYREG_B1_P5_U0_PLD_ORT3, 0x40011a36 +.set CYREG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 +.set CYREG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a +.set CYREG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c +.set CYREG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e +.set CYREG_B1_P5_U0_CFG0, 0x40011a40 +.set CYREG_B1_P5_U0_CFG1, 0x40011a41 +.set CYREG_B1_P5_U0_CFG2, 0x40011a42 +.set CYREG_B1_P5_U0_CFG3, 0x40011a43 +.set CYREG_B1_P5_U0_CFG4, 0x40011a44 +.set CYREG_B1_P5_U0_CFG5, 0x40011a45 +.set CYREG_B1_P5_U0_CFG6, 0x40011a46 +.set CYREG_B1_P5_U0_CFG7, 0x40011a47 +.set CYREG_B1_P5_U0_CFG8, 0x40011a48 +.set CYREG_B1_P5_U0_CFG9, 0x40011a49 +.set CYREG_B1_P5_U0_CFG10, 0x40011a4a +.set CYREG_B1_P5_U0_CFG11, 0x40011a4b +.set CYREG_B1_P5_U0_CFG12, 0x40011a4c +.set CYREG_B1_P5_U0_CFG13, 0x40011a4d +.set CYREG_B1_P5_U0_CFG14, 0x40011a4e +.set CYREG_B1_P5_U0_CFG15, 0x40011a4f +.set CYREG_B1_P5_U0_CFG16, 0x40011a50 +.set CYREG_B1_P5_U0_CFG17, 0x40011a51 +.set CYREG_B1_P5_U0_CFG18, 0x40011a52 +.set CYREG_B1_P5_U0_CFG19, 0x40011a53 +.set CYREG_B1_P5_U0_CFG20, 0x40011a54 +.set CYREG_B1_P5_U0_CFG21, 0x40011a55 +.set CYREG_B1_P5_U0_CFG22, 0x40011a56 +.set CYREG_B1_P5_U0_CFG23, 0x40011a57 +.set CYREG_B1_P5_U0_CFG24, 0x40011a58 +.set CYREG_B1_P5_U0_CFG25, 0x40011a59 +.set CYREG_B1_P5_U0_CFG26, 0x40011a5a +.set CYREG_B1_P5_U0_CFG27, 0x40011a5b +.set CYREG_B1_P5_U0_CFG28, 0x40011a5c +.set CYREG_B1_P5_U0_CFG29, 0x40011a5d +.set CYREG_B1_P5_U0_CFG30, 0x40011a5e +.set CYREG_B1_P5_U0_CFG31, 0x40011a5f +.set CYREG_B1_P5_U0_DCFG0, 0x40011a60 +.set CYREG_B1_P5_U0_DCFG1, 0x40011a62 +.set CYREG_B1_P5_U0_DCFG2, 0x40011a64 +.set CYREG_B1_P5_U0_DCFG3, 0x40011a66 +.set CYREG_B1_P5_U0_DCFG4, 0x40011a68 +.set CYREG_B1_P5_U0_DCFG5, 0x40011a6a +.set CYREG_B1_P5_U0_DCFG6, 0x40011a6c +.set CYREG_B1_P5_U0_DCFG7, 0x40011a6e +.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 +.set CYREG_B1_P5_U1_PLD_IT0, 0x40011a80 +.set CYREG_B1_P5_U1_PLD_IT1, 0x40011a84 +.set CYREG_B1_P5_U1_PLD_IT2, 0x40011a88 +.set CYREG_B1_P5_U1_PLD_IT3, 0x40011a8c +.set CYREG_B1_P5_U1_PLD_IT4, 0x40011a90 +.set CYREG_B1_P5_U1_PLD_IT5, 0x40011a94 +.set CYREG_B1_P5_U1_PLD_IT6, 0x40011a98 +.set CYREG_B1_P5_U1_PLD_IT7, 0x40011a9c +.set CYREG_B1_P5_U1_PLD_IT8, 0x40011aa0 +.set CYREG_B1_P5_U1_PLD_IT9, 0x40011aa4 +.set CYREG_B1_P5_U1_PLD_IT10, 0x40011aa8 +.set CYREG_B1_P5_U1_PLD_IT11, 0x40011aac +.set CYREG_B1_P5_U1_PLD_ORT0, 0x40011ab0 +.set CYREG_B1_P5_U1_PLD_ORT1, 0x40011ab2 +.set CYREG_B1_P5_U1_PLD_ORT2, 0x40011ab4 +.set CYREG_B1_P5_U1_PLD_ORT3, 0x40011ab6 +.set CYREG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 +.set CYREG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba +.set CYREG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc +.set CYREG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe +.set CYREG_B1_P5_U1_CFG0, 0x40011ac0 +.set CYREG_B1_P5_U1_CFG1, 0x40011ac1 +.set CYREG_B1_P5_U1_CFG2, 0x40011ac2 +.set CYREG_B1_P5_U1_CFG3, 0x40011ac3 +.set CYREG_B1_P5_U1_CFG4, 0x40011ac4 +.set CYREG_B1_P5_U1_CFG5, 0x40011ac5 +.set CYREG_B1_P5_U1_CFG6, 0x40011ac6 +.set CYREG_B1_P5_U1_CFG7, 0x40011ac7 +.set CYREG_B1_P5_U1_CFG8, 0x40011ac8 +.set CYREG_B1_P5_U1_CFG9, 0x40011ac9 +.set CYREG_B1_P5_U1_CFG10, 0x40011aca +.set CYREG_B1_P5_U1_CFG11, 0x40011acb +.set CYREG_B1_P5_U1_CFG12, 0x40011acc +.set CYREG_B1_P5_U1_CFG13, 0x40011acd +.set CYREG_B1_P5_U1_CFG14, 0x40011ace +.set CYREG_B1_P5_U1_CFG15, 0x40011acf +.set CYREG_B1_P5_U1_CFG16, 0x40011ad0 +.set CYREG_B1_P5_U1_CFG17, 0x40011ad1 +.set CYREG_B1_P5_U1_CFG18, 0x40011ad2 +.set CYREG_B1_P5_U1_CFG19, 0x40011ad3 +.set CYREG_B1_P5_U1_CFG20, 0x40011ad4 +.set CYREG_B1_P5_U1_CFG21, 0x40011ad5 +.set CYREG_B1_P5_U1_CFG22, 0x40011ad6 +.set CYREG_B1_P5_U1_CFG23, 0x40011ad7 +.set CYREG_B1_P5_U1_CFG24, 0x40011ad8 +.set CYREG_B1_P5_U1_CFG25, 0x40011ad9 +.set CYREG_B1_P5_U1_CFG26, 0x40011ada +.set CYREG_B1_P5_U1_CFG27, 0x40011adb +.set CYREG_B1_P5_U1_CFG28, 0x40011adc +.set CYREG_B1_P5_U1_CFG29, 0x40011add +.set CYREG_B1_P5_U1_CFG30, 0x40011ade +.set CYREG_B1_P5_U1_CFG31, 0x40011adf +.set CYREG_B1_P5_U1_DCFG0, 0x40011ae0 +.set CYREG_B1_P5_U1_DCFG1, 0x40011ae2 +.set CYREG_B1_P5_U1_DCFG2, 0x40011ae4 +.set CYREG_B1_P5_U1_DCFG3, 0x40011ae6 +.set CYREG_B1_P5_U1_DCFG4, 0x40011ae8 +.set CYREG_B1_P5_U1_DCFG5, 0x40011aea +.set CYREG_B1_P5_U1_DCFG6, 0x40011aec +.set CYREG_B1_P5_U1_DCFG7, 0x40011aee +.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 +.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI0_BASE, 0x40014000 +.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI1_BASE, 0x40014100 +.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI2_BASE, 0x40014200 +.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI3_BASE, 0x40014300 +.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI4_BASE, 0x40014400 +.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI5_BASE, 0x40014500 +.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI6_BASE, 0x40014600 +.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI7_BASE, 0x40014700 +.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI8_BASE, 0x40014800 +.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI9_BASE, 0x40014900 +.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI12_BASE, 0x40014c00 +.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI13_BASE, 0x40014d00 +.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef +.set CYDEV_UCFG_BCTL0_BASE, 0x40015000 +.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 +.set CYREG_BCTL0_MDCLK_EN, 0x40015000 +.set CYREG_BCTL0_MBCLK_EN, 0x40015001 +.set CYREG_BCTL0_WAIT_CFG, 0x40015002 +.set CYREG_BCTL0_BANK_CTL, 0x40015003 +.set CYREG_BCTL0_UDB_TEST_3, 0x40015007 +.set CYREG_BCTL0_DCLK_EN0, 0x40015008 +.set CYREG_BCTL0_BCLK_EN0, 0x40015009 +.set CYREG_BCTL0_DCLK_EN1, 0x4001500a +.set CYREG_BCTL0_BCLK_EN1, 0x4001500b +.set CYREG_BCTL0_DCLK_EN2, 0x4001500c +.set CYREG_BCTL0_BCLK_EN2, 0x4001500d +.set CYREG_BCTL0_DCLK_EN3, 0x4001500e +.set CYREG_BCTL0_BCLK_EN3, 0x4001500f +.set CYDEV_UCFG_BCTL1_BASE, 0x40015010 +.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 +.set CYREG_BCTL1_MDCLK_EN, 0x40015010 +.set CYREG_BCTL1_MBCLK_EN, 0x40015011 +.set CYREG_BCTL1_WAIT_CFG, 0x40015012 +.set CYREG_BCTL1_BANK_CTL, 0x40015013 +.set CYREG_BCTL1_UDB_TEST_3, 0x40015017 +.set CYREG_BCTL1_DCLK_EN0, 0x40015018 +.set CYREG_BCTL1_BCLK_EN0, 0x40015019 +.set CYREG_BCTL1_DCLK_EN1, 0x4001501a +.set CYREG_BCTL1_BCLK_EN1, 0x4001501b +.set CYREG_BCTL1_DCLK_EN2, 0x4001501c +.set CYREG_BCTL1_BCLK_EN2, 0x4001501d +.set CYREG_BCTL1_DCLK_EN3, 0x4001501e +.set CYREG_BCTL1_BCLK_EN3, 0x4001501f +.set CYDEV_IDMUX_BASE, 0x40015100 +.set CYDEV_IDMUX_SIZE, 0x00000016 +.set CYREG_IDMUX_IRQ_CTL0, 0x40015100 +.set CYREG_IDMUX_IRQ_CTL1, 0x40015101 +.set CYREG_IDMUX_IRQ_CTL2, 0x40015102 +.set CYREG_IDMUX_IRQ_CTL3, 0x40015103 +.set CYREG_IDMUX_IRQ_CTL4, 0x40015104 +.set CYREG_IDMUX_IRQ_CTL5, 0x40015105 +.set CYREG_IDMUX_IRQ_CTL6, 0x40015106 +.set CYREG_IDMUX_IRQ_CTL7, 0x40015107 +.set CYREG_IDMUX_DRQ_CTL0, 0x40015110 +.set CYREG_IDMUX_DRQ_CTL1, 0x40015111 +.set CYREG_IDMUX_DRQ_CTL2, 0x40015112 +.set CYREG_IDMUX_DRQ_CTL3, 0x40015113 +.set CYREG_IDMUX_DRQ_CTL4, 0x40015114 +.set CYREG_IDMUX_DRQ_CTL5, 0x40015115 +.set CYDEV_CACHERAM_BASE, 0x40030000 +.set CYDEV_CACHERAM_SIZE, 0x00000400 +.set CYREG_CACHERAM_DATA_MBASE, 0x40030000 +.set CYREG_CACHERAM_DATA_MSIZE, 0x00000400 +.set CYDEV_SFR_BASE, 0x40050100 +.set CYDEV_SFR_SIZE, 0x000000fb +.set CYREG_SFR_GPIO0, 0x40050180 +.set CYREG_SFR_GPIRD0, 0x40050189 +.set CYREG_SFR_GPIO0_SEL, 0x4005018a +.set CYREG_SFR_GPIO1, 0x40050190 +.set CYREG_SFR_GPIRD1, 0x40050191 +.set CYREG_SFR_GPIO2, 0x40050198 +.set CYREG_SFR_GPIRD2, 0x40050199 +.set CYREG_SFR_GPIO2_SEL, 0x4005019a +.set CYREG_SFR_GPIO1_SEL, 0x400501a2 +.set CYREG_SFR_GPIO3, 0x400501b0 +.set CYREG_SFR_GPIRD3, 0x400501b1 +.set CYREG_SFR_GPIO3_SEL, 0x400501b2 +.set CYREG_SFR_GPIO4, 0x400501c0 +.set CYREG_SFR_GPIRD4, 0x400501c1 +.set CYREG_SFR_GPIO4_SEL, 0x400501c2 +.set CYREG_SFR_GPIO5, 0x400501c8 +.set CYREG_SFR_GPIRD5, 0x400501c9 +.set CYREG_SFR_GPIO5_SEL, 0x400501ca +.set CYREG_SFR_GPIO6, 0x400501d8 +.set CYREG_SFR_GPIRD6, 0x400501d9 +.set CYREG_SFR_GPIO6_SEL, 0x400501da +.set CYREG_SFR_GPIO12, 0x400501e8 +.set CYREG_SFR_GPIRD12, 0x400501e9 +.set CYREG_SFR_GPIO12_SEL, 0x400501f2 +.set CYREG_SFR_GPIO15, 0x400501f8 +.set CYREG_SFR_GPIRD15, 0x400501f9 +.set CYREG_SFR_GPIO15_SEL, 0x400501fa +.set CYDEV_P3BA_BASE, 0x40050300 +.set CYDEV_P3BA_SIZE, 0x0000002b +.set CYREG_P3BA_Y_START, 0x40050300 +.set CYREG_P3BA_YROLL, 0x40050301 +.set CYREG_P3BA_YCFG, 0x40050302 +.set CYREG_P3BA_X_START1, 0x40050303 +.set CYREG_P3BA_X_START2, 0x40050304 +.set CYREG_P3BA_XROLL1, 0x40050305 +.set CYREG_P3BA_XROLL2, 0x40050306 +.set CYREG_P3BA_XINC, 0x40050307 +.set CYREG_P3BA_XCFG, 0x40050308 +.set CYREG_P3BA_OFFSETADDR1, 0x40050309 +.set CYREG_P3BA_OFFSETADDR2, 0x4005030a +.set CYREG_P3BA_OFFSETADDR3, 0x4005030b +.set CYREG_P3BA_ABSADDR1, 0x4005030c +.set CYREG_P3BA_ABSADDR2, 0x4005030d +.set CYREG_P3BA_ABSADDR3, 0x4005030e +.set CYREG_P3BA_ABSADDR4, 0x4005030f +.set CYREG_P3BA_DATCFG1, 0x40050310 +.set CYREG_P3BA_DATCFG2, 0x40050311 +.set CYREG_P3BA_CMP_RSLT1, 0x40050314 +.set CYREG_P3BA_CMP_RSLT2, 0x40050315 +.set CYREG_P3BA_CMP_RSLT3, 0x40050316 +.set CYREG_P3BA_CMP_RSLT4, 0x40050317 +.set CYREG_P3BA_DATA_REG1, 0x40050318 +.set CYREG_P3BA_DATA_REG2, 0x40050319 +.set CYREG_P3BA_DATA_REG3, 0x4005031a +.set CYREG_P3BA_DATA_REG4, 0x4005031b +.set CYREG_P3BA_EXP_DATA1, 0x4005031c +.set CYREG_P3BA_EXP_DATA2, 0x4005031d +.set CYREG_P3BA_EXP_DATA3, 0x4005031e +.set CYREG_P3BA_EXP_DATA4, 0x4005031f +.set CYREG_P3BA_MSTR_HRDATA1, 0x40050320 +.set CYREG_P3BA_MSTR_HRDATA2, 0x40050321 +.set CYREG_P3BA_MSTR_HRDATA3, 0x40050322 +.set CYREG_P3BA_MSTR_HRDATA4, 0x40050323 +.set CYREG_P3BA_BIST_EN, 0x40050324 +.set CYREG_P3BA_PHUB_MASTER_SSR, 0x40050325 +.set CYREG_P3BA_SEQCFG1, 0x40050326 +.set CYREG_P3BA_SEQCFG2, 0x40050327 +.set CYREG_P3BA_Y_CURR, 0x40050328 +.set CYREG_P3BA_X_CURR1, 0x40050329 +.set CYREG_P3BA_X_CURR2, 0x4005032a +.set CYDEV_PANTHER_BASE, 0x40080000 +.set CYDEV_PANTHER_SIZE, 0x00000020 +.set CYREG_PANTHER_STCALIB_CFG, 0x40080000 +.set CYREG_PANTHER_WAITPIPE, 0x40080004 +.set CYREG_PANTHER_TRACE_CFG, 0x40080008 +.set CYREG_PANTHER_DBG_CFG, 0x4008000c +.set CYREG_PANTHER_CM3_LCKRST_STAT, 0x40080018 +.set CYREG_PANTHER_DEVICE_ID, 0x4008001c +.set CYDEV_FLSECC_BASE, 0x48000000 +.set CYDEV_FLSECC_SIZE, 0x00008000 +.set CYREG_FLSECC_DATA_MBASE, 0x48000000 +.set CYREG_FLSECC_DATA_MSIZE, 0x00008000 +.set CYDEV_FLSHID_BASE, 0x49000000 +.set CYDEV_FLSHID_SIZE, 0x00000200 +.set CYREG_FLSHID_RSVD_MBASE, 0x49000000 +.set CYREG_FLSHID_RSVD_MSIZE, 0x00000080 +.set CYREG_FLSHID_CUST_MDATA_MBASE, 0x49000080 +.set CYREG_FLSHID_CUST_MDATA_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 +.set CYREG_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 +.set CYREG_FLSHID_CUST_TABLES_X_LOC, 0x49000101 +.set CYREG_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 +.set CYREG_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 +.set CYREG_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 +.set CYREG_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 +.set CYREG_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 +.set CYREG_FLSHID_CUST_TABLES_MINOR, 0x49000107 +.set CYREG_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 +.set CYREG_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 +.set CYREG_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a +.set CYREG_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b +.set CYREG_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c +.set CYREG_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d +.set CYREG_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e +.set CYREG_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f +.set CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 +.set CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 +.set CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 +.set CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 +.set CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 +.set CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 +.set CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 +.set CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 +.set CYREG_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 +.set CYREG_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 +.set CYREG_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a +.set CYREG_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b +.set CYREG_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c +.set CYREG_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d +.set CYREG_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e +.set CYREG_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f +.set CYREG_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a +.set CYREG_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b +.set CYREG_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c +.set CYREG_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d +.set CYREG_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e +.set CYREG_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f +.set CYREG_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a +.set CYREG_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b +.set CYREG_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c +.set CYREG_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d +.set CYREG_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e +.set CYREG_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f +.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 +.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 +.set CYREG_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 +.set CYREG_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac +.set CYREG_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae +.set CYREG_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 +.set CYREG_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 +.set CYREG_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 +.set CYREG_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 +.set CYREG_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 +.set CYREG_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba +.set CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce +.set CYDEV_EXTMEM_BASE, 0x60000000 +.set CYDEV_EXTMEM_SIZE, 0x00800000 +.set CYREG_EXTMEM_DATA_MBASE, 0x60000000 +.set CYREG_EXTMEM_DATA_MSIZE, 0x00800000 +.set CYDEV_ITM_BASE, 0xe0000000 +.set CYDEV_ITM_SIZE, 0x00001000 +.set CYREG_ITM_TRACE_EN, 0xe0000e00 +.set CYREG_ITM_TRACE_PRIVILEGE, 0xe0000e40 +.set CYREG_ITM_TRACE_CTRL, 0xe0000e80 +.set CYREG_ITM_LOCK_ACCESS, 0xe0000fb0 +.set CYREG_ITM_LOCK_STATUS, 0xe0000fb4 +.set CYREG_ITM_PID4, 0xe0000fd0 +.set CYREG_ITM_PID5, 0xe0000fd4 +.set CYREG_ITM_PID6, 0xe0000fd8 +.set CYREG_ITM_PID7, 0xe0000fdc +.set CYREG_ITM_PID0, 0xe0000fe0 +.set CYREG_ITM_PID1, 0xe0000fe4 +.set CYREG_ITM_PID2, 0xe0000fe8 +.set CYREG_ITM_PID3, 0xe0000fec +.set CYREG_ITM_CID0, 0xe0000ff0 +.set CYREG_ITM_CID1, 0xe0000ff4 +.set CYREG_ITM_CID2, 0xe0000ff8 +.set CYREG_ITM_CID3, 0xe0000ffc +.set CYDEV_DWT_BASE, 0xe0001000 +.set CYDEV_DWT_SIZE, 0x0000005c +.set CYREG_DWT_CTRL, 0xe0001000 +.set CYREG_DWT_CYCLE_COUNT, 0xe0001004 +.set CYREG_DWT_CPI_COUNT, 0xe0001008 +.set CYREG_DWT_EXC_OVHD_COUNT, 0xe000100c +.set CYREG_DWT_SLEEP_COUNT, 0xe0001010 +.set CYREG_DWT_LSU_COUNT, 0xe0001014 +.set CYREG_DWT_FOLD_COUNT, 0xe0001018 +.set CYREG_DWT_PC_SAMPLE, 0xe000101c +.set CYREG_DWT_COMP_0, 0xe0001020 +.set CYREG_DWT_MASK_0, 0xe0001024 +.set CYREG_DWT_FUNCTION_0, 0xe0001028 +.set CYREG_DWT_COMP_1, 0xe0001030 +.set CYREG_DWT_MASK_1, 0xe0001034 +.set CYREG_DWT_FUNCTION_1, 0xe0001038 +.set CYREG_DWT_COMP_2, 0xe0001040 +.set CYREG_DWT_MASK_2, 0xe0001044 +.set CYREG_DWT_FUNCTION_2, 0xe0001048 +.set CYREG_DWT_COMP_3, 0xe0001050 +.set CYREG_DWT_MASK_3, 0xe0001054 +.set CYREG_DWT_FUNCTION_3, 0xe0001058 +.set CYDEV_FPB_BASE, 0xe0002000 +.set CYDEV_FPB_SIZE, 0x00001000 +.set CYREG_FPB_CTRL, 0xe0002000 +.set CYREG_FPB_REMAP, 0xe0002004 +.set CYREG_FPB_FP_COMP_0, 0xe0002008 +.set CYREG_FPB_FP_COMP_1, 0xe000200c +.set CYREG_FPB_FP_COMP_2, 0xe0002010 +.set CYREG_FPB_FP_COMP_3, 0xe0002014 +.set CYREG_FPB_FP_COMP_4, 0xe0002018 +.set CYREG_FPB_FP_COMP_5, 0xe000201c +.set CYREG_FPB_FP_COMP_6, 0xe0002020 +.set CYREG_FPB_FP_COMP_7, 0xe0002024 +.set CYREG_FPB_PID4, 0xe0002fd0 +.set CYREG_FPB_PID5, 0xe0002fd4 +.set CYREG_FPB_PID6, 0xe0002fd8 +.set CYREG_FPB_PID7, 0xe0002fdc +.set CYREG_FPB_PID0, 0xe0002fe0 +.set CYREG_FPB_PID1, 0xe0002fe4 +.set CYREG_FPB_PID2, 0xe0002fe8 +.set CYREG_FPB_PID3, 0xe0002fec +.set CYREG_FPB_CID0, 0xe0002ff0 +.set CYREG_FPB_CID1, 0xe0002ff4 +.set CYREG_FPB_CID2, 0xe0002ff8 +.set CYREG_FPB_CID3, 0xe0002ffc +.set CYDEV_NVIC_BASE, 0xe000e000 +.set CYDEV_NVIC_SIZE, 0x00000d3c +.set CYREG_NVIC_INT_CTL_TYPE, 0xe000e004 +.set CYREG_NVIC_SYSTICK_CTL, 0xe000e010 +.set CYREG_NVIC_SYSTICK_RELOAD, 0xe000e014 +.set CYREG_NVIC_SYSTICK_CURRENT, 0xe000e018 +.set CYREG_NVIC_SYSTICK_CAL, 0xe000e01c +.set CYREG_NVIC_SETENA0, 0xe000e100 +.set CYREG_NVIC_CLRENA0, 0xe000e180 +.set CYREG_NVIC_SETPEND0, 0xe000e200 +.set CYREG_NVIC_CLRPEND0, 0xe000e280 +.set CYREG_NVIC_ACTIVE0, 0xe000e300 +.set CYREG_NVIC_PRI_0, 0xe000e400 +.set CYREG_NVIC_PRI_1, 0xe000e401 +.set CYREG_NVIC_PRI_2, 0xe000e402 +.set CYREG_NVIC_PRI_3, 0xe000e403 +.set CYREG_NVIC_PRI_4, 0xe000e404 +.set CYREG_NVIC_PRI_5, 0xe000e405 +.set CYREG_NVIC_PRI_6, 0xe000e406 +.set CYREG_NVIC_PRI_7, 0xe000e407 +.set CYREG_NVIC_PRI_8, 0xe000e408 +.set CYREG_NVIC_PRI_9, 0xe000e409 +.set CYREG_NVIC_PRI_10, 0xe000e40a +.set CYREG_NVIC_PRI_11, 0xe000e40b +.set CYREG_NVIC_PRI_12, 0xe000e40c +.set CYREG_NVIC_PRI_13, 0xe000e40d +.set CYREG_NVIC_PRI_14, 0xe000e40e +.set CYREG_NVIC_PRI_15, 0xe000e40f +.set CYREG_NVIC_PRI_16, 0xe000e410 +.set CYREG_NVIC_PRI_17, 0xe000e411 +.set CYREG_NVIC_PRI_18, 0xe000e412 +.set CYREG_NVIC_PRI_19, 0xe000e413 +.set CYREG_NVIC_PRI_20, 0xe000e414 +.set CYREG_NVIC_PRI_21, 0xe000e415 +.set CYREG_NVIC_PRI_22, 0xe000e416 +.set CYREG_NVIC_PRI_23, 0xe000e417 +.set CYREG_NVIC_PRI_24, 0xe000e418 +.set CYREG_NVIC_PRI_25, 0xe000e419 +.set CYREG_NVIC_PRI_26, 0xe000e41a +.set CYREG_NVIC_PRI_27, 0xe000e41b +.set CYREG_NVIC_PRI_28, 0xe000e41c +.set CYREG_NVIC_PRI_29, 0xe000e41d +.set CYREG_NVIC_PRI_30, 0xe000e41e +.set CYREG_NVIC_PRI_31, 0xe000e41f +.set CYREG_NVIC_CPUID_BASE, 0xe000ed00 +.set CYREG_NVIC_INTR_CTRL_STATE, 0xe000ed04 +.set CYREG_NVIC_VECT_OFFSET, 0xe000ed08 +.set CYREG_NVIC_APPLN_INTR, 0xe000ed0c +.set CYREG_NVIC_SYSTEM_CONTROL, 0xe000ed10 +.set CYREG_NVIC_CFG_CONTROL, 0xe000ed14 +.set CYREG_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 +.set CYREG_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c +.set CYREG_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 +.set CYREG_NVIC_SYS_HANDLER_CSR, 0xe000ed24 +.set CYREG_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 +.set CYREG_NVIC_BUS_FAULT_STATUS, 0xe000ed29 +.set CYREG_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a +.set CYREG_NVIC_HARD_FAULT_STATUS, 0xe000ed2c +.set CYREG_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 +.set CYREG_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 +.set CYREG_NVIC_BUS_FAULT_ADD, 0xe000ed38 +.set CYDEV_CORE_DBG_BASE, 0xe000edf0 +.set CYDEV_CORE_DBG_SIZE, 0x00000010 +.set CYREG_CORE_DBG_DBG_HLT_CS, 0xe000edf0 +.set CYREG_CORE_DBG_DBG_REG_SEL, 0xe000edf4 +.set CYREG_CORE_DBG_DBG_REG_DATA, 0xe000edf8 +.set CYREG_CORE_DBG_EXC_MON_CTL, 0xe000edfc +.set CYDEV_TPIU_BASE, 0xe0040000 +.set CYDEV_TPIU_SIZE, 0x00001000 +.set CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 +.set CYREG_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 +.set CYREG_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 +.set CYREG_TPIU_PROTOCOL, 0xe00400f0 +.set CYREG_TPIU_FORM_FLUSH_STAT, 0xe0040300 +.set CYREG_TPIU_FORM_FLUSH_CTRL, 0xe0040304 +.set CYREG_TPIU_TRIGGER, 0xe0040ee8 +.set CYREG_TPIU_ITETMDATA, 0xe0040eec +.set CYREG_TPIU_ITATBCTR2, 0xe0040ef0 +.set CYREG_TPIU_ITATBCTR0, 0xe0040ef8 +.set CYREG_TPIU_ITITMDATA, 0xe0040efc +.set CYREG_TPIU_ITCTRL, 0xe0040f00 +.set CYREG_TPIU_DEVID, 0xe0040fc8 +.set CYREG_TPIU_DEVTYPE, 0xe0040fcc +.set CYREG_TPIU_PID4, 0xe0040fd0 +.set CYREG_TPIU_PID5, 0xe0040fd4 +.set CYREG_TPIU_PID6, 0xe0040fd8 +.set CYREG_TPIU_PID7, 0xe0040fdc +.set CYREG_TPIU_PID0, 0xe0040fe0 +.set CYREG_TPIU_PID1, 0xe0040fe4 +.set CYREG_TPIU_PID2, 0xe0040fe8 +.set CYREG_TPIU_PID3, 0xe0040fec +.set CYREG_TPIU_CID0, 0xe0040ff0 +.set CYREG_TPIU_CID1, 0xe0040ff4 +.set CYREG_TPIU_CID2, 0xe0040ff8 +.set CYREG_TPIU_CID3, 0xe0040ffc +.set CYDEV_ETM_BASE, 0xe0041000 +.set CYDEV_ETM_SIZE, 0x00001000 +.set CYREG_ETM_CTL, 0xe0041000 +.set CYREG_ETM_CFG_CODE, 0xe0041004 +.set CYREG_ETM_TRIG_EVENT, 0xe0041008 +.set CYREG_ETM_STATUS, 0xe0041010 +.set CYREG_ETM_SYS_CFG, 0xe0041014 +.set CYREG_ETM_TRACE_ENB_EVENT, 0xe0041020 +.set CYREG_ETM_TRACE_EN_CTRL1, 0xe0041024 +.set CYREG_ETM_FIFOFULL_LEVEL, 0xe004102c +.set CYREG_ETM_SYNC_FREQ, 0xe00411e0 +.set CYREG_ETM_ETM_ID, 0xe00411e4 +.set CYREG_ETM_CFG_CODE_EXT, 0xe00411e8 +.set CYREG_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 +.set CYREG_ETM_CS_TRACE_ID, 0xe0041200 +.set CYREG_ETM_OS_LOCK_ACCESS, 0xe0041300 +.set CYREG_ETM_OS_LOCK_STATUS, 0xe0041304 +.set CYREG_ETM_PDSR, 0xe0041314 +.set CYREG_ETM_ITMISCIN, 0xe0041ee0 +.set CYREG_ETM_ITTRIGOUT, 0xe0041ee8 +.set CYREG_ETM_ITATBCTR2, 0xe0041ef0 +.set CYREG_ETM_ITATBCTR0, 0xe0041ef8 +.set CYREG_ETM_INT_MODE_CTRL, 0xe0041f00 +.set CYREG_ETM_CLM_TAG_SET, 0xe0041fa0 +.set CYREG_ETM_CLM_TAG_CLR, 0xe0041fa4 +.set CYREG_ETM_LOCK_ACCESS, 0xe0041fb0 +.set CYREG_ETM_LOCK_STATUS, 0xe0041fb4 +.set CYREG_ETM_AUTH_STATUS, 0xe0041fb8 +.set CYREG_ETM_DEV_TYPE, 0xe0041fcc +.set CYREG_ETM_PID4, 0xe0041fd0 +.set CYREG_ETM_PID5, 0xe0041fd4 +.set CYREG_ETM_PID6, 0xe0041fd8 +.set CYREG_ETM_PID7, 0xe0041fdc +.set CYREG_ETM_PID0, 0xe0041fe0 +.set CYREG_ETM_PID1, 0xe0041fe4 +.set CYREG_ETM_PID2, 0xe0041fe8 +.set CYREG_ETM_PID3, 0xe0041fec +.set CYREG_ETM_CID0, 0xe0041ff0 +.set CYREG_ETM_CID1, 0xe0041ff4 +.set CYREG_ETM_CID2, 0xe0041ff8 +.set CYREG_ETM_CID3, 0xe0041ffc +.set CYDEV_ROM_TABLE_BASE, 0xe00ff000 +.set CYDEV_ROM_TABLE_SIZE, 0x00001000 +.set CYREG_ROM_TABLE_NVIC, 0xe00ff000 +.set CYREG_ROM_TABLE_DWT, 0xe00ff004 +.set CYREG_ROM_TABLE_FPB, 0xe00ff008 +.set CYREG_ROM_TABLE_ITM, 0xe00ff00c +.set CYREG_ROM_TABLE_TPIU, 0xe00ff010 +.set CYREG_ROM_TABLE_ETM, 0xe00ff014 +.set CYREG_ROM_TABLE_END, 0xe00ff018 +.set CYREG_ROM_TABLE_MEMTYPE, 0xe00fffcc +.set CYREG_ROM_TABLE_PID4, 0xe00fffd0 +.set CYREG_ROM_TABLE_PID5, 0xe00fffd4 +.set CYREG_ROM_TABLE_PID6, 0xe00fffd8 +.set CYREG_ROM_TABLE_PID7, 0xe00fffdc +.set CYREG_ROM_TABLE_PID0, 0xe00fffe0 +.set CYREG_ROM_TABLE_PID1, 0xe00fffe4 +.set CYREG_ROM_TABLE_PID2, 0xe00fffe8 +.set CYREG_ROM_TABLE_PID3, 0xe00fffec +.set CYREG_ROM_TABLE_CID0, 0xe00ffff0 +.set CYREG_ROM_TABLE_CID1, 0xe00ffff4 +.set CYREG_ROM_TABLE_CID2, 0xe00ffff8 +.set CYREG_ROM_TABLE_CID3, 0xe00ffffc +.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE +.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE +.set CYDEV_FLS_SECTOR_SIZE, 0x00010000 +.set CYDEV_FLS_ROW_SIZE, 0x00000100 +.set CYDEV_ECC_SECTOR_SIZE, 0x00002000 +.set CYDEV_ECC_ROW_SIZE, 0x00000020 +.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 +.set CYDEV_EEPROM_ROW_SIZE, 0x00000010 +.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE +.set CYCLK_LD_DISABLE, 0x00000004 +.set CYCLK_LD_SYNC_EN, 0x00000002 +.set CYCLK_LD_LOAD, 0x00000001 +.set CYCLK_PIPE, 0x00000080 +.set CYCLK_SSS, 0x00000040 +.set CYCLK_EARLY, 0x00000020 +.set CYCLK_DUTY, 0x00000010 +.set CYCLK_SYNC, 0x00000008 +.set CYCLK_SRC_SEL_CLK_SYNC_D, 0 +.set CYCLK_SRC_SEL_SYNC_DIG, 0 +.set CYCLK_SRC_SEL_IMO, 1 +.set CYCLK_SRC_SEL_XTAL_MHZ, 2 +.set CYCLK_SRC_SEL_XTALM, 2 +.set CYCLK_SRC_SEL_ILO, 3 +.set CYCLK_SRC_SEL_PLL, 4 +.set CYCLK_SRC_SEL_XTAL_KHZ, 5 +.set CYCLK_SRC_SEL_XTALK, 5 +.set CYCLK_SRC_SEL_DSI_G, 6 +.set CYCLK_SRC_SEL_DSI_D, 7 +.set CYCLK_SRC_SEL_CLK_SYNC_A, 0 +.set CYCLK_SRC_SEL_DSI_A, 7 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc new file mode 100644 index 0000000..3c00a5d --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -0,0 +1,16039 @@ +; +; FILENAME: cydevicerv.inc +; OBSOLETE: Do not use this file. Use the _trm version instead. +; PSoC Creator 2.2 Component Pack 6 +; +; DESCRIPTION: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00040000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_DATA_MBASE +CYDEV_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_DATA_MSIZE +CYDEV_FLASH_DATA_MSIZE EQU 0x00040000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MBASE +CYDEV_SRAM_CODE64K_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MSIZE +CYDEV_SRAM_CODE64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MBASE +CYDEV_SRAM_CODE32K_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MSIZE +CYDEV_SRAM_CODE32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MBASE +CYDEV_SRAM_CODE16K_MBASE EQU 0x1fffe000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MSIZE +CYDEV_SRAM_CODE16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE_MBASE +CYDEV_SRAM_CODE_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE_MSIZE +CYDEV_SRAM_CODE_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA_MBASE +CYDEV_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA_MSIZE +CYDEV_SRAM_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MBASE +CYDEV_SRAM_DATA16K_MBASE EQU 0x20001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MSIZE +CYDEV_SRAM_DATA16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MBASE +CYDEV_SRAM_DATA32K_MBASE EQU 0x20002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MSIZE +CYDEV_SRAM_DATA32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MBASE +CYDEV_SRAM_DATA64K_MBASE EQU 0x20004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MSIZE +CYDEV_SRAM_DATA64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_BASE +CYDEV_DMA_BASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SIZE +CYDEV_DMA_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MBASE +CYDEV_DMA_SRAM64K_MBASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MSIZE +CYDEV_DMA_SRAM64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MBASE +CYDEV_DMA_SRAM32K_MBASE EQU 0x2000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MSIZE +CYDEV_DMA_SRAM32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MBASE +CYDEV_DMA_SRAM16K_MBASE EQU 0x2000e000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MSIZE +CYDEV_DMA_SRAM16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM_MBASE +CYDEV_DMA_SRAM_MBASE EQU 0x2000f000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM_MSIZE +CYDEV_DMA_SRAM_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BASE +CYDEV_CLKDIST_BASE EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_SIZE +CYDEV_CLKDIST_SIZE EQU 0x00000110 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_CR +CYDEV_CLKDIST_CR EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_LD +CYDEV_CLKDIST_LD EQU 0x40004001 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_WRK0 +CYDEV_CLKDIST_WRK0 EQU 0x40004002 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_WRK1 +CYDEV_CLKDIST_WRK1 EQU 0x40004003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_MSTR0 +CYDEV_CLKDIST_MSTR0 EQU 0x40004004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_MSTR1 +CYDEV_CLKDIST_MSTR1 EQU 0x40004005 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG0 +CYDEV_CLKDIST_BCFG0 EQU 0x40004006 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG1 +CYDEV_CLKDIST_BCFG1 EQU 0x40004007 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG2 +CYDEV_CLKDIST_BCFG2 EQU 0x40004008 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_UCFG +CYDEV_CLKDIST_UCFG EQU 0x40004009 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DLY0 +CYDEV_CLKDIST_DLY0 EQU 0x4000400a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DLY1 +CYDEV_CLKDIST_DLY1 EQU 0x4000400b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DMASK +CYDEV_CLKDIST_DMASK EQU 0x40004010 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_AMASK +CYDEV_CLKDIST_AMASK EQU 0x40004014 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE +CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE +CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG0 +CYDEV_CLKDIST_DCFG0_CFG0 EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG1 +CYDEV_CLKDIST_DCFG0_CFG1 EQU 0x40004081 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG2 +CYDEV_CLKDIST_DCFG0_CFG2 EQU 0x40004082 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE +CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE +CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG0 +CYDEV_CLKDIST_DCFG1_CFG0 EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG1 +CYDEV_CLKDIST_DCFG1_CFG1 EQU 0x40004085 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG2 +CYDEV_CLKDIST_DCFG1_CFG2 EQU 0x40004086 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE +CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE +CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG0 +CYDEV_CLKDIST_DCFG2_CFG0 EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG1 +CYDEV_CLKDIST_DCFG2_CFG1 EQU 0x40004089 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG2 +CYDEV_CLKDIST_DCFG2_CFG2 EQU 0x4000408a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE +CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE +CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG0 +CYDEV_CLKDIST_DCFG3_CFG0 EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG1 +CYDEV_CLKDIST_DCFG3_CFG1 EQU 0x4000408d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG2 +CYDEV_CLKDIST_DCFG3_CFG2 EQU 0x4000408e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE +CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE +CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG0 +CYDEV_CLKDIST_DCFG4_CFG0 EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG1 +CYDEV_CLKDIST_DCFG4_CFG1 EQU 0x40004091 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG2 +CYDEV_CLKDIST_DCFG4_CFG2 EQU 0x40004092 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE +CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE +CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG0 +CYDEV_CLKDIST_DCFG5_CFG0 EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG1 +CYDEV_CLKDIST_DCFG5_CFG1 EQU 0x40004095 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG2 +CYDEV_CLKDIST_DCFG5_CFG2 EQU 0x40004096 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE +CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE +CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG0 +CYDEV_CLKDIST_DCFG6_CFG0 EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG1 +CYDEV_CLKDIST_DCFG6_CFG1 EQU 0x40004099 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG2 +CYDEV_CLKDIST_DCFG6_CFG2 EQU 0x4000409a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE +CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE +CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG0 +CYDEV_CLKDIST_DCFG7_CFG0 EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG1 +CYDEV_CLKDIST_DCFG7_CFG1 EQU 0x4000409d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG2 +CYDEV_CLKDIST_DCFG7_CFG2 EQU 0x4000409e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE +CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE +CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG0 +CYDEV_CLKDIST_ACFG0_CFG0 EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG1 +CYDEV_CLKDIST_ACFG0_CFG1 EQU 0x40004101 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG2 +CYDEV_CLKDIST_ACFG0_CFG2 EQU 0x40004102 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG3 +CYDEV_CLKDIST_ACFG0_CFG3 EQU 0x40004103 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE +CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE +CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG0 +CYDEV_CLKDIST_ACFG1_CFG0 EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG1 +CYDEV_CLKDIST_ACFG1_CFG1 EQU 0x40004105 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG2 +CYDEV_CLKDIST_ACFG1_CFG2 EQU 0x40004106 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG3 +CYDEV_CLKDIST_ACFG1_CFG3 EQU 0x40004107 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE +CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE +CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG0 +CYDEV_CLKDIST_ACFG2_CFG0 EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG1 +CYDEV_CLKDIST_ACFG2_CFG1 EQU 0x40004109 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG2 +CYDEV_CLKDIST_ACFG2_CFG2 EQU 0x4000410a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG3 +CYDEV_CLKDIST_ACFG2_CFG3 EQU 0x4000410b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE +CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE +CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG0 +CYDEV_CLKDIST_ACFG3_CFG0 EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG1 +CYDEV_CLKDIST_ACFG3_CFG1 EQU 0x4000410d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG2 +CYDEV_CLKDIST_ACFG3_CFG2 EQU 0x4000410e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG3 +CYDEV_CLKDIST_ACFG3_CFG3 EQU 0x4000410f + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_BASE +CYDEV_FASTCLK_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_SIZE +CYDEV_FASTCLK_SIZE EQU 0x00000026 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE +CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE +CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_CR +CYDEV_FASTCLK_IMO_CR EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE +CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE +CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CSR +CYDEV_FASTCLK_XMHZ_CSR EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG0 +CYDEV_FASTCLK_XMHZ_CFG0 EQU 0x40004212 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG1 +CYDEV_FASTCLK_XMHZ_CFG1 EQU 0x40004213 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE +CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE +CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG0 +CYDEV_FASTCLK_PLL_CFG0 EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG1 +CYDEV_FASTCLK_PLL_CFG1 EQU 0x40004221 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_P +CYDEV_FASTCLK_PLL_P EQU 0x40004222 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_Q +CYDEV_FASTCLK_PLL_Q EQU 0x40004223 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SR +CYDEV_FASTCLK_PLL_SR EQU 0x40004225 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_BASE +CYDEV_SLOWCLK_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE +CYDEV_SLOWCLK_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE +CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE +CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR0 +CYDEV_SLOWCLK_ILO_CR0 EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR1 +CYDEV_SLOWCLK_ILO_CR1 EQU 0x40004301 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE +CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE +CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CR +CYDEV_SLOWCLK_X32_CR EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CFG +CYDEV_SLOWCLK_X32_CFG EQU 0x40004309 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_TST +CYDEV_SLOWCLK_X32_TST EQU 0x4000430a + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_BASE +CYDEV_BOOST_BASE EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SIZE +CYDEV_BOOST_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR0 +CYDEV_BOOST_CR0 EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR1 +CYDEV_BOOST_CR1 EQU 0x40004321 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR2 +CYDEV_BOOST_CR2 EQU 0x40004322 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR3 +CYDEV_BOOST_CR3 EQU 0x40004323 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SR +CYDEV_BOOST_SR EQU 0x40004324 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR4 +CYDEV_BOOST_CR4 EQU 0x40004325 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SR2 +CYDEV_BOOST_SR2 EQU 0x40004326 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_BASE +CYDEV_PWRSYS_BASE EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_SIZE +CYDEV_PWRSYS_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_CR0 +CYDEV_PWRSYS_CR0 EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_CR1 +CYDEV_PWRSYS_CR1 EQU 0x40004331 + ENDIF + IF :LNOT::DEF:CYDEV_PM_BASE +CYDEV_PM_BASE EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_SIZE +CYDEV_PM_SIZE EQU 0x00000057 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG0 +CYDEV_PM_TW_CFG0 EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG1 +CYDEV_PM_TW_CFG1 EQU 0x40004381 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG2 +CYDEV_PM_TW_CFG2 EQU 0x40004382 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WDT_CFG +CYDEV_PM_WDT_CFG EQU 0x40004383 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WDT_CR +CYDEV_PM_WDT_CR EQU 0x40004384 + ENDIF + IF :LNOT::DEF:CYDEV_PM_INT_SR +CYDEV_PM_INT_SR EQU 0x40004390 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CFG0 +CYDEV_PM_MODE_CFG0 EQU 0x40004391 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CFG1 +CYDEV_PM_MODE_CFG1 EQU 0x40004392 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CSR +CYDEV_PM_MODE_CSR EQU 0x40004393 + ENDIF + IF :LNOT::DEF:CYDEV_PM_USB_CR0 +CYDEV_PM_USB_CR0 EQU 0x40004394 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG0 +CYDEV_PM_WAKEUP_CFG0 EQU 0x40004398 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG1 +CYDEV_PM_WAKEUP_CFG1 EQU 0x40004399 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG2 +CYDEV_PM_WAKEUP_CFG2 EQU 0x4000439a + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_BASE +CYDEV_PM_ACT_BASE EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_SIZE +CYDEV_PM_ACT_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG0 +CYDEV_PM_ACT_CFG0 EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG1 +CYDEV_PM_ACT_CFG1 EQU 0x400043a1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG2 +CYDEV_PM_ACT_CFG2 EQU 0x400043a2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG3 +CYDEV_PM_ACT_CFG3 EQU 0x400043a3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG4 +CYDEV_PM_ACT_CFG4 EQU 0x400043a4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG5 +CYDEV_PM_ACT_CFG5 EQU 0x400043a5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG6 +CYDEV_PM_ACT_CFG6 EQU 0x400043a6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG7 +CYDEV_PM_ACT_CFG7 EQU 0x400043a7 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG8 +CYDEV_PM_ACT_CFG8 EQU 0x400043a8 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG9 +CYDEV_PM_ACT_CFG9 EQU 0x400043a9 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG10 +CYDEV_PM_ACT_CFG10 EQU 0x400043aa + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG11 +CYDEV_PM_ACT_CFG11 EQU 0x400043ab + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG12 +CYDEV_PM_ACT_CFG12 EQU 0x400043ac + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG13 +CYDEV_PM_ACT_CFG13 EQU 0x400043ad + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_BASE +CYDEV_PM_STBY_BASE EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_SIZE +CYDEV_PM_STBY_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG0 +CYDEV_PM_STBY_CFG0 EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG1 +CYDEV_PM_STBY_CFG1 EQU 0x400043b1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG2 +CYDEV_PM_STBY_CFG2 EQU 0x400043b2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG3 +CYDEV_PM_STBY_CFG3 EQU 0x400043b3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG4 +CYDEV_PM_STBY_CFG4 EQU 0x400043b4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG5 +CYDEV_PM_STBY_CFG5 EQU 0x400043b5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG6 +CYDEV_PM_STBY_CFG6 EQU 0x400043b6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG7 +CYDEV_PM_STBY_CFG7 EQU 0x400043b7 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG8 +CYDEV_PM_STBY_CFG8 EQU 0x400043b8 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG9 +CYDEV_PM_STBY_CFG9 EQU 0x400043b9 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG10 +CYDEV_PM_STBY_CFG10 EQU 0x400043ba + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG11 +CYDEV_PM_STBY_CFG11 EQU 0x400043bb + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG12 +CYDEV_PM_STBY_CFG12 EQU 0x400043bc + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG13 +CYDEV_PM_STBY_CFG13 EQU 0x400043bd + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE +CYDEV_PM_AVAIL_BASE EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE +CYDEV_PM_AVAIL_SIZE EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR0 +CYDEV_PM_AVAIL_CR0 EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR1 +CYDEV_PM_AVAIL_CR1 EQU 0x400043c1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR2 +CYDEV_PM_AVAIL_CR2 EQU 0x400043c2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR3 +CYDEV_PM_AVAIL_CR3 EQU 0x400043c3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR4 +CYDEV_PM_AVAIL_CR4 EQU 0x400043c4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR5 +CYDEV_PM_AVAIL_CR5 EQU 0x400043c5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR6 +CYDEV_PM_AVAIL_CR6 EQU 0x400043c6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR0 +CYDEV_PM_AVAIL_SR0 EQU 0x400043d0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR1 +CYDEV_PM_AVAIL_SR1 EQU 0x400043d1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR2 +CYDEV_PM_AVAIL_SR2 EQU 0x400043d2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR3 +CYDEV_PM_AVAIL_SR3 EQU 0x400043d3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR4 +CYDEV_PM_AVAIL_SR4 EQU 0x400043d4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR5 +CYDEV_PM_AVAIL_SR5 EQU 0x400043d5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR6 +CYDEV_PM_AVAIL_SR6 EQU 0x400043d6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_BASE +CYDEV_PICU_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SIZE +CYDEV_PICU_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE +CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE +CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE +CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE +CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 EQU 0x40004501 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 EQU 0x40004502 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 EQU 0x40004503 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 EQU 0x40004504 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 EQU 0x40004505 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 EQU 0x40004506 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 EQU 0x40004507 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE +CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE +CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 EQU 0x40004509 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 EQU 0x4000450a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 EQU 0x4000450b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 EQU 0x4000450c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 EQU 0x4000450d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 EQU 0x4000450e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 EQU 0x4000450f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE +CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE +CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 EQU 0x40004511 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 EQU 0x40004512 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 EQU 0x40004513 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 EQU 0x40004514 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 EQU 0x40004515 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 EQU 0x40004516 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 EQU 0x40004517 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE +CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE +CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 EQU 0x40004519 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 EQU 0x4000451a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 EQU 0x4000451b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 EQU 0x4000451c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 EQU 0x4000451d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 EQU 0x4000451e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 EQU 0x4000451f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE +CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE +CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 EQU 0x40004521 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 EQU 0x40004522 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 EQU 0x40004523 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 EQU 0x40004524 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 EQU 0x40004525 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 EQU 0x40004526 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 EQU 0x40004527 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE +CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE +CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 EQU 0x40004529 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 EQU 0x4000452a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 EQU 0x4000452b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 EQU 0x4000452c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 EQU 0x4000452d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 EQU 0x4000452e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 EQU 0x4000452f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE +CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE +CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 EQU 0x40004531 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 EQU 0x40004532 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 EQU 0x40004533 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 EQU 0x40004534 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 EQU 0x40004535 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 EQU 0x40004536 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 EQU 0x40004537 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE +CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE +CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 EQU 0x40004561 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 EQU 0x40004562 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 EQU 0x40004563 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 EQU 0x40004564 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 EQU 0x40004565 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 EQU 0x40004566 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 EQU 0x40004567 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE +CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE +CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 EQU 0x40004579 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 EQU 0x4000457a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 EQU 0x4000457b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 EQU 0x4000457c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 EQU 0x4000457d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 EQU 0x4000457e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 EQU 0x4000457f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_BASE +CYDEV_PICU_STAT_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE +CYDEV_PICU_STAT_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE +CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE +CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_INTSTAT +CYDEV_PICU_STAT_PICU0_INTSTAT EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE +CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE +CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_INTSTAT +CYDEV_PICU_STAT_PICU1_INTSTAT EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE +CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE +CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_INTSTAT +CYDEV_PICU_STAT_PICU2_INTSTAT EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE +CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE +CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_INTSTAT +CYDEV_PICU_STAT_PICU3_INTSTAT EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE +CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE +CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_INTSTAT +CYDEV_PICU_STAT_PICU4_INTSTAT EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE +CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE +CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_INTSTAT +CYDEV_PICU_STAT_PICU5_INTSTAT EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE +CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE +CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_INTSTAT +CYDEV_PICU_STAT_PICU6_INTSTAT EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE +CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE +CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_INTSTAT +CYDEV_PICU_STAT_PICU12_INTSTAT EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE +CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE +CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_INTSTAT +CYDEV_PICU_STAT_PICU15_INTSTAT EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE +CYDEV_PICU_SNAP_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE +CYDEV_PICU_SNAP_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE +CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE +CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SNAP +CYDEV_PICU_SNAP_PICU0_SNAP EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE +CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE +CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SNAP +CYDEV_PICU_SNAP_PICU1_SNAP EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE +CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE +CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SNAP +CYDEV_PICU_SNAP_PICU2_SNAP EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE +CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE +CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SNAP +CYDEV_PICU_SNAP_PICU3_SNAP EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE +CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE +CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SNAP +CYDEV_PICU_SNAP_PICU4_SNAP EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE +CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE +CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SNAP +CYDEV_PICU_SNAP_PICU5_SNAP EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE +CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE +CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SNAP +CYDEV_PICU_SNAP_PICU6_SNAP EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE +CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE +CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SNAP +CYDEV_PICU_SNAP_PICU12_SNAP EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE +CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE +CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SNAP_15 +CYDEV_PICU_SNAP_PICU_15_SNAP_15 EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE +CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE +CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE +CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE +CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE +CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE +CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE +CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE +CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE +CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE +CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE +CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE +CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE +CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE +CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE +CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE +CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE +CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE +CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE +CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE +CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_BASE +CYDEV_MFGCFG_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_SIZE +CYDEV_MFGCFG_SIZE EQU 0x000000ed + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE +CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE +CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE +CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE +CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_TR +CYDEV_MFGCFG_ANAIF_DAC0_TR EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE +CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE +CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_TR +CYDEV_MFGCFG_ANAIF_DAC1_TR EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE +CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE +CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_TR +CYDEV_MFGCFG_ANAIF_DAC2_TR EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE +CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE +CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_TR +CYDEV_MFGCFG_ANAIF_DAC3_TR EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE +CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE +CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_TR0 +CYDEV_MFGCFG_ANAIF_SAR0_TR0 EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE +CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE +CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_TR0 +CYDEV_MFGCFG_ANAIF_SAR1_TR0 EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE +CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 EQU 0x40004621 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE +CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 EQU 0x40004623 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE +CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 EQU 0x40004625 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE +CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 EQU 0x40004627 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE +CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE +CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR0 +CYDEV_MFGCFG_ANAIF_CMP0_TR0 EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR1 +CYDEV_MFGCFG_ANAIF_CMP0_TR1 EQU 0x40004631 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE +CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE +CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR0 +CYDEV_MFGCFG_ANAIF_CMP1_TR0 EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR1 +CYDEV_MFGCFG_ANAIF_CMP1_TR1 EQU 0x40004633 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE +CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE +CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR0 +CYDEV_MFGCFG_ANAIF_CMP2_TR0 EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR1 +CYDEV_MFGCFG_ANAIF_CMP2_TR1 EQU 0x40004635 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE +CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE +CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR0 +CYDEV_MFGCFG_ANAIF_CMP3_TR0 EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR1 +CYDEV_MFGCFG_ANAIF_CMP3_TR1 EQU 0x40004637 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE +CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE +CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR0 +CYDEV_MFGCFG_PWRSYS_HIB_TR0 EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR1 +CYDEV_MFGCFG_PWRSYS_HIB_TR1 EQU 0x40004681 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_I2C_TR +CYDEV_MFGCFG_PWRSYS_I2C_TR EQU 0x40004682 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SLP_TR +CYDEV_MFGCFG_PWRSYS_SLP_TR EQU 0x40004683 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BUZZ_TR +CYDEV_MFGCFG_PWRSYS_BUZZ_TR EQU 0x40004684 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR0 +CYDEV_MFGCFG_PWRSYS_WAKE_TR0 EQU 0x40004685 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR1 +CYDEV_MFGCFG_PWRSYS_WAKE_TR1 EQU 0x40004686 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BREF_TR +CYDEV_MFGCFG_PWRSYS_BREF_TR EQU 0x40004687 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BG_TR +CYDEV_MFGCFG_PWRSYS_BG_TR EQU 0x40004688 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR2 +CYDEV_MFGCFG_PWRSYS_WAKE_TR2 EQU 0x40004689 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR3 +CYDEV_MFGCFG_PWRSYS_WAKE_TR3 EQU 0x4000468a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE +CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE +CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR0 +CYDEV_MFGCFG_ILO_TR0 EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR1 +CYDEV_MFGCFG_ILO_TR1 EQU 0x40004691 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE +CYDEV_MFGCFG_X32_BASE EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE +CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_TR +CYDEV_MFGCFG_X32_TR EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE +CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE +CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR0 +CYDEV_MFGCFG_IMO_TR0 EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR1 +CYDEV_MFGCFG_IMO_TR1 EQU 0x400046a1 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_GAIN +CYDEV_MFGCFG_IMO_GAIN EQU 0x400046a2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_C36M +CYDEV_MFGCFG_IMO_C36M EQU 0x400046a3 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR2 +CYDEV_MFGCFG_IMO_TR2 EQU 0x400046a4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE +CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE +CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_TR +CYDEV_MFGCFG_XMHZ_TR EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_DLY +CYDEV_MFGCFG_DLY EQU 0x400046c0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE +CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE +CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DMPSTR +CYDEV_MFGCFG_MLOGIC_DMPSTR EQU 0x400046e2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE +CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE +CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CR +CYDEV_MFGCFG_MLOGIC_SEG_CR EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CFG0 +CYDEV_MFGCFG_MLOGIC_SEG_CFG0 EQU 0x400046e5 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DEBUG +CYDEV_MFGCFG_MLOGIC_DEBUG EQU 0x400046e8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR +CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_REV_ID +CYDEV_MFGCFG_MLOGIC_REV_ID EQU 0x400046ec + ENDIF + IF :LNOT::DEF:CYDEV_RESET_BASE +CYDEV_RESET_BASE EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SIZE +CYDEV_RESET_SIZE EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR0 +CYDEV_RESET_IPOR_CR0 EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR1 +CYDEV_RESET_IPOR_CR1 EQU 0x400046f1 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR2 +CYDEV_RESET_IPOR_CR2 EQU 0x400046f2 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR3 +CYDEV_RESET_IPOR_CR3 EQU 0x400046f3 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR0 +CYDEV_RESET_CR0 EQU 0x400046f4 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR1 +CYDEV_RESET_CR1 EQU 0x400046f5 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR2 +CYDEV_RESET_CR2 EQU 0x400046f6 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR3 +CYDEV_RESET_CR3 EQU 0x400046f7 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR4 +CYDEV_RESET_CR4 EQU 0x400046f8 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR5 +CYDEV_RESET_CR5 EQU 0x400046f9 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR0 +CYDEV_RESET_SR0 EQU 0x400046fa + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR1 +CYDEV_RESET_SR1 EQU 0x400046fb + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR2 +CYDEV_RESET_SR2 EQU 0x400046fc + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR3 +CYDEV_RESET_SR3 EQU 0x400046fd + ENDIF + IF :LNOT::DEF:CYDEV_RESET_TR +CYDEV_RESET_TR EQU 0x400046fe + ENDIF + IF :LNOT::DEF:CYDEV_SPC_BASE +CYDEV_SPC_BASE EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SIZE +CYDEV_SPC_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_FM_EE_CR +CYDEV_SPC_FM_EE_CR EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_FM_EE_WAKE_CNT +CYDEV_SPC_FM_EE_WAKE_CNT EQU 0x40004701 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_EE_SCR +CYDEV_SPC_EE_SCR EQU 0x40004702 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_EE_ERR +CYDEV_SPC_EE_ERR EQU 0x40004703 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_CPU_DATA +CYDEV_SPC_CPU_DATA EQU 0x40004720 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMA_DATA +CYDEV_SPC_DMA_DATA EQU 0x40004721 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SR +CYDEV_SPC_SR EQU 0x40004722 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_CR +CYDEV_SPC_CR EQU 0x40004723 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE +CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE +CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MBASE +CYDEV_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MSIZE +CYDEV_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_BASE +CYDEV_CACHE_BASE EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_SIZE +CYDEV_CACHE_SIZE EQU 0x0000009c + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_CC_CTL +CYDEV_CACHE_CC_CTL EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_ECC_CORR +CYDEV_CACHE_ECC_CORR EQU 0x40004880 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_ECC_ERR +CYDEV_CACHE_ECC_ERR EQU 0x40004888 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_FLASH_ERR +CYDEV_CACHE_FLASH_ERR EQU 0x40004890 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_HITMISS +CYDEV_CACHE_HITMISS EQU 0x40004898 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_BASE +CYDEV_I2C_BASE EQU 0x40004900 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_SIZE +CYDEV_I2C_SIZE EQU 0x000000e1 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_XCFG +CYDEV_I2C_XCFG EQU 0x400049c8 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_ADR +CYDEV_I2C_ADR EQU 0x400049ca + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CFG +CYDEV_I2C_CFG EQU 0x400049d6 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CSR +CYDEV_I2C_CSR EQU 0x400049d7 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_D +CYDEV_I2C_D EQU 0x400049d8 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_MCSR +CYDEV_I2C_MCSR EQU 0x400049d9 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CLK_DIV1 +CYDEV_I2C_CLK_DIV1 EQU 0x400049db + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CLK_DIV2 +CYDEV_I2C_CLK_DIV2 EQU 0x400049dc + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CSR +CYDEV_I2C_TMOUT_CSR EQU 0x400049dd + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_SR +CYDEV_I2C_TMOUT_SR EQU 0x400049de + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG0 +CYDEV_I2C_TMOUT_CFG0 EQU 0x400049df + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG1 +CYDEV_I2C_TMOUT_CFG1 EQU 0x400049e0 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_BASE +CYDEV_DEC_BASE EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SIZE +CYDEV_DEC_SIZE EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_CR +CYDEV_DEC_CR EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SR +CYDEV_DEC_SR EQU 0x40004e01 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SHIFT1 +CYDEV_DEC_SHIFT1 EQU 0x40004e02 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SHIFT2 +CYDEV_DEC_SHIFT2 EQU 0x40004e03 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR2 +CYDEV_DEC_DR2 EQU 0x40004e04 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR2H +CYDEV_DEC_DR2H EQU 0x40004e05 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR1 +CYDEV_DEC_DR1 EQU 0x40004e06 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCOR +CYDEV_DEC_OCOR EQU 0x40004e08 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCORM +CYDEV_DEC_OCORM EQU 0x40004e09 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCORH +CYDEV_DEC_OCORH EQU 0x40004e0a + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GCOR +CYDEV_DEC_GCOR EQU 0x40004e0c + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GCORH +CYDEV_DEC_GCORH EQU 0x40004e0d + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GVAL +CYDEV_DEC_GVAL EQU 0x40004e0e + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMP +CYDEV_DEC_OUTSAMP EQU 0x40004e10 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPM +CYDEV_DEC_OUTSAMPM EQU 0x40004e11 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPH +CYDEV_DEC_OUTSAMPH EQU 0x40004e12 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPS +CYDEV_DEC_OUTSAMPS EQU 0x40004e13 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_COHER +CYDEV_DEC_COHER EQU 0x40004e14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_BASE +CYDEV_TMR0_BASE EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SIZE +CYDEV_TMR0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG0 +CYDEV_TMR0_CFG0 EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG1 +CYDEV_TMR0_CFG1 EQU 0x40004f01 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG2 +CYDEV_TMR0_CFG2 EQU 0x40004f02 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SR0 +CYDEV_TMR0_SR0 EQU 0x40004f03 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_PER0 +CYDEV_TMR0_PER0 EQU 0x40004f04 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_PER1 +CYDEV_TMR0_PER1 EQU 0x40004f05 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP0 +CYDEV_TMR0_CNT_CMP0 EQU 0x40004f06 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP1 +CYDEV_TMR0_CNT_CMP1 EQU 0x40004f07 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CAP0 +CYDEV_TMR0_CAP0 EQU 0x40004f08 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CAP1 +CYDEV_TMR0_CAP1 EQU 0x40004f09 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_RT0 +CYDEV_TMR0_RT0 EQU 0x40004f0a + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_RT1 +CYDEV_TMR0_RT1 EQU 0x40004f0b + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_BASE +CYDEV_TMR1_BASE EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SIZE +CYDEV_TMR1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG0 +CYDEV_TMR1_CFG0 EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG1 +CYDEV_TMR1_CFG1 EQU 0x40004f0d + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG2 +CYDEV_TMR1_CFG2 EQU 0x40004f0e + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SR0 +CYDEV_TMR1_SR0 EQU 0x40004f0f + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_PER0 +CYDEV_TMR1_PER0 EQU 0x40004f10 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_PER1 +CYDEV_TMR1_PER1 EQU 0x40004f11 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP0 +CYDEV_TMR1_CNT_CMP0 EQU 0x40004f12 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP1 +CYDEV_TMR1_CNT_CMP1 EQU 0x40004f13 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CAP0 +CYDEV_TMR1_CAP0 EQU 0x40004f14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CAP1 +CYDEV_TMR1_CAP1 EQU 0x40004f15 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_RT0 +CYDEV_TMR1_RT0 EQU 0x40004f16 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_RT1 +CYDEV_TMR1_RT1 EQU 0x40004f17 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_BASE +CYDEV_TMR2_BASE EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SIZE +CYDEV_TMR2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG0 +CYDEV_TMR2_CFG0 EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG1 +CYDEV_TMR2_CFG1 EQU 0x40004f19 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG2 +CYDEV_TMR2_CFG2 EQU 0x40004f1a + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SR0 +CYDEV_TMR2_SR0 EQU 0x40004f1b + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_PER0 +CYDEV_TMR2_PER0 EQU 0x40004f1c + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_PER1 +CYDEV_TMR2_PER1 EQU 0x40004f1d + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP0 +CYDEV_TMR2_CNT_CMP0 EQU 0x40004f1e + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP1 +CYDEV_TMR2_CNT_CMP1 EQU 0x40004f1f + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CAP0 +CYDEV_TMR2_CAP0 EQU 0x40004f20 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CAP1 +CYDEV_TMR2_CAP1 EQU 0x40004f21 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_RT0 +CYDEV_TMR2_RT0 EQU 0x40004f22 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_RT1 +CYDEV_TMR2_RT1 EQU 0x40004f23 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_BASE +CYDEV_TMR3_BASE EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SIZE +CYDEV_TMR3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG0 +CYDEV_TMR3_CFG0 EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG1 +CYDEV_TMR3_CFG1 EQU 0x40004f25 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG2 +CYDEV_TMR3_CFG2 EQU 0x40004f26 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SR0 +CYDEV_TMR3_SR0 EQU 0x40004f27 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_PER0 +CYDEV_TMR3_PER0 EQU 0x40004f28 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_PER1 +CYDEV_TMR3_PER1 EQU 0x40004f29 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP0 +CYDEV_TMR3_CNT_CMP0 EQU 0x40004f2a + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP1 +CYDEV_TMR3_CNT_CMP1 EQU 0x40004f2b + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CAP0 +CYDEV_TMR3_CAP0 EQU 0x40004f2c + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CAP1 +CYDEV_TMR3_CAP1 EQU 0x40004f2d + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_RT0 +CYDEV_TMR3_RT0 EQU 0x40004f2e + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_RT1 +CYDEV_TMR3_RT1 EQU 0x40004f2f + ENDIF + IF :LNOT::DEF:CYDEV_IO_BASE +CYDEV_IO_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_SIZE +CYDEV_IO_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_BASE +CYDEV_IO_PC_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_SIZE +CYDEV_IO_PC_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE +CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE +CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC0 +CYDEV_IO_PC_PRT0_PC0 EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC1 +CYDEV_IO_PC_PRT0_PC1 EQU 0x40005001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC2 +CYDEV_IO_PC_PRT0_PC2 EQU 0x40005002 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC3 +CYDEV_IO_PC_PRT0_PC3 EQU 0x40005003 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC4 +CYDEV_IO_PC_PRT0_PC4 EQU 0x40005004 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC5 +CYDEV_IO_PC_PRT0_PC5 EQU 0x40005005 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC6 +CYDEV_IO_PC_PRT0_PC6 EQU 0x40005006 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC7 +CYDEV_IO_PC_PRT0_PC7 EQU 0x40005007 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE +CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE +CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC0 +CYDEV_IO_PC_PRT1_PC0 EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC1 +CYDEV_IO_PC_PRT1_PC1 EQU 0x40005009 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC2 +CYDEV_IO_PC_PRT1_PC2 EQU 0x4000500a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC3 +CYDEV_IO_PC_PRT1_PC3 EQU 0x4000500b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC4 +CYDEV_IO_PC_PRT1_PC4 EQU 0x4000500c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC5 +CYDEV_IO_PC_PRT1_PC5 EQU 0x4000500d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC6 +CYDEV_IO_PC_PRT1_PC6 EQU 0x4000500e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC7 +CYDEV_IO_PC_PRT1_PC7 EQU 0x4000500f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE +CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE +CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC0 +CYDEV_IO_PC_PRT2_PC0 EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC1 +CYDEV_IO_PC_PRT2_PC1 EQU 0x40005011 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC2 +CYDEV_IO_PC_PRT2_PC2 EQU 0x40005012 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC3 +CYDEV_IO_PC_PRT2_PC3 EQU 0x40005013 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC4 +CYDEV_IO_PC_PRT2_PC4 EQU 0x40005014 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC5 +CYDEV_IO_PC_PRT2_PC5 EQU 0x40005015 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC6 +CYDEV_IO_PC_PRT2_PC6 EQU 0x40005016 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC7 +CYDEV_IO_PC_PRT2_PC7 EQU 0x40005017 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE +CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE +CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC0 +CYDEV_IO_PC_PRT3_PC0 EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC1 +CYDEV_IO_PC_PRT3_PC1 EQU 0x40005019 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC2 +CYDEV_IO_PC_PRT3_PC2 EQU 0x4000501a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC3 +CYDEV_IO_PC_PRT3_PC3 EQU 0x4000501b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC4 +CYDEV_IO_PC_PRT3_PC4 EQU 0x4000501c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC5 +CYDEV_IO_PC_PRT3_PC5 EQU 0x4000501d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC6 +CYDEV_IO_PC_PRT3_PC6 EQU 0x4000501e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC7 +CYDEV_IO_PC_PRT3_PC7 EQU 0x4000501f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE +CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE +CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC0 +CYDEV_IO_PC_PRT4_PC0 EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC1 +CYDEV_IO_PC_PRT4_PC1 EQU 0x40005021 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC2 +CYDEV_IO_PC_PRT4_PC2 EQU 0x40005022 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC3 +CYDEV_IO_PC_PRT4_PC3 EQU 0x40005023 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC4 +CYDEV_IO_PC_PRT4_PC4 EQU 0x40005024 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC5 +CYDEV_IO_PC_PRT4_PC5 EQU 0x40005025 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC6 +CYDEV_IO_PC_PRT4_PC6 EQU 0x40005026 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC7 +CYDEV_IO_PC_PRT4_PC7 EQU 0x40005027 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE +CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE +CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC0 +CYDEV_IO_PC_PRT5_PC0 EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC1 +CYDEV_IO_PC_PRT5_PC1 EQU 0x40005029 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC2 +CYDEV_IO_PC_PRT5_PC2 EQU 0x4000502a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC3 +CYDEV_IO_PC_PRT5_PC3 EQU 0x4000502b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC4 +CYDEV_IO_PC_PRT5_PC4 EQU 0x4000502c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC5 +CYDEV_IO_PC_PRT5_PC5 EQU 0x4000502d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC6 +CYDEV_IO_PC_PRT5_PC6 EQU 0x4000502e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC7 +CYDEV_IO_PC_PRT5_PC7 EQU 0x4000502f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE +CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE +CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC0 +CYDEV_IO_PC_PRT6_PC0 EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC1 +CYDEV_IO_PC_PRT6_PC1 EQU 0x40005031 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC2 +CYDEV_IO_PC_PRT6_PC2 EQU 0x40005032 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC3 +CYDEV_IO_PC_PRT6_PC3 EQU 0x40005033 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC4 +CYDEV_IO_PC_PRT6_PC4 EQU 0x40005034 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC5 +CYDEV_IO_PC_PRT6_PC5 EQU 0x40005035 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC6 +CYDEV_IO_PC_PRT6_PC6 EQU 0x40005036 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC7 +CYDEV_IO_PC_PRT6_PC7 EQU 0x40005037 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE +CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE +CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC0 +CYDEV_IO_PC_PRT12_PC0 EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC1 +CYDEV_IO_PC_PRT12_PC1 EQU 0x40005061 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC2 +CYDEV_IO_PC_PRT12_PC2 EQU 0x40005062 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC3 +CYDEV_IO_PC_PRT12_PC3 EQU 0x40005063 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC4 +CYDEV_IO_PC_PRT12_PC4 EQU 0x40005064 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC5 +CYDEV_IO_PC_PRT12_PC5 EQU 0x40005065 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC6 +CYDEV_IO_PC_PRT12_PC6 EQU 0x40005066 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC7 +CYDEV_IO_PC_PRT12_PC7 EQU 0x40005067 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE +CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE +CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC0 +CYDEV_IO_PC_PRT15_PC0 EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC1 +CYDEV_IO_PC_PRT15_PC1 EQU 0x40005079 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC2 +CYDEV_IO_PC_PRT15_PC2 EQU 0x4000507a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC3 +CYDEV_IO_PC_PRT15_PC3 EQU 0x4000507b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC4 +CYDEV_IO_PC_PRT15_PC4 EQU 0x4000507c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC5 +CYDEV_IO_PC_PRT15_PC5 EQU 0x4000507d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE +CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE +CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC0 +CYDEV_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC1 +CYDEV_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_BASE +CYDEV_IO_DR_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_SIZE +CYDEV_IO_DR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE +CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE +CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_DR_ALIAS +CYDEV_IO_DR_PRT0_DR_ALIAS EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE +CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE +CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_DR_ALIAS +CYDEV_IO_DR_PRT1_DR_ALIAS EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE +CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE +CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_DR_ALIAS +CYDEV_IO_DR_PRT2_DR_ALIAS EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE +CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE +CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_DR_ALIAS +CYDEV_IO_DR_PRT3_DR_ALIAS EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE +CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE +CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_DR_ALIAS +CYDEV_IO_DR_PRT4_DR_ALIAS EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE +CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE +CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_DR_ALIAS +CYDEV_IO_DR_PRT5_DR_ALIAS EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE +CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE +CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_DR_ALIAS +CYDEV_IO_DR_PRT6_DR_ALIAS EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE +CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE +CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_DR_ALIAS +CYDEV_IO_DR_PRT12_DR_ALIAS EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE +CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE +CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_DR_15_ALIAS +CYDEV_IO_DR_PRT15_DR_15_ALIAS EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_BASE +CYDEV_IO_PS_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_SIZE +CYDEV_IO_PS_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE +CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE +CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_PS_ALIAS +CYDEV_IO_PS_PRT0_PS_ALIAS EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE +CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE +CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_PS_ALIAS +CYDEV_IO_PS_PRT1_PS_ALIAS EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE +CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE +CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_PS_ALIAS +CYDEV_IO_PS_PRT2_PS_ALIAS EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE +CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE +CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_PS_ALIAS +CYDEV_IO_PS_PRT3_PS_ALIAS EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE +CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE +CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_PS_ALIAS +CYDEV_IO_PS_PRT4_PS_ALIAS EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE +CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE +CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_PS_ALIAS +CYDEV_IO_PS_PRT5_PS_ALIAS EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE +CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE +CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_PS_ALIAS +CYDEV_IO_PS_PRT6_PS_ALIAS EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE +CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE +CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_PS_ALIAS +CYDEV_IO_PS_PRT12_PS_ALIAS EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE +CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE +CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_PS15_ALIAS +CYDEV_IO_PS_PRT15_PS15_ALIAS EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_BASE +CYDEV_IO_PRT_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_SIZE +CYDEV_IO_PRT_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE +CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE +CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DR +CYDEV_IO_PRT_PRT0_DR EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PS +CYDEV_IO_PRT_PRT0_PS EQU 0x40005101 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM0 +CYDEV_IO_PRT_PRT0_DM0 EQU 0x40005102 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM1 +CYDEV_IO_PRT_PRT0_DM1 EQU 0x40005103 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM2 +CYDEV_IO_PRT_PRT0_DM2 EQU 0x40005104 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SLW +CYDEV_IO_PRT_PRT0_SLW EQU 0x40005105 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BYP +CYDEV_IO_PRT_PRT0_BYP EQU 0x40005106 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIE +CYDEV_IO_PRT_PRT0_BIE EQU 0x40005107 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_INP_DIS +CYDEV_IO_PRT_PRT0_INP_DIS EQU 0x40005108 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_CTL +CYDEV_IO_PRT_PRT0_CTL EQU 0x40005109 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PRT +CYDEV_IO_PRT_PRT0_PRT EQU 0x4000510a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIT_MASK +CYDEV_IO_PRT_PRT0_BIT_MASK EQU 0x4000510b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AMUX +CYDEV_IO_PRT_PRT0_AMUX EQU 0x4000510c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AG +CYDEV_IO_PRT_PRT0_AG EQU 0x4000510d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_COM_SEG +CYDEV_IO_PRT_PRT0_LCD_COM_SEG EQU 0x4000510e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_EN +CYDEV_IO_PRT_PRT0_LCD_EN EQU 0x4000510f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE +CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE +CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DR +CYDEV_IO_PRT_PRT1_DR EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PS +CYDEV_IO_PRT_PRT1_PS EQU 0x40005111 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM0 +CYDEV_IO_PRT_PRT1_DM0 EQU 0x40005112 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM1 +CYDEV_IO_PRT_PRT1_DM1 EQU 0x40005113 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM2 +CYDEV_IO_PRT_PRT1_DM2 EQU 0x40005114 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SLW +CYDEV_IO_PRT_PRT1_SLW EQU 0x40005115 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BYP +CYDEV_IO_PRT_PRT1_BYP EQU 0x40005116 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIE +CYDEV_IO_PRT_PRT1_BIE EQU 0x40005117 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_INP_DIS +CYDEV_IO_PRT_PRT1_INP_DIS EQU 0x40005118 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_CTL +CYDEV_IO_PRT_PRT1_CTL EQU 0x40005119 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PRT +CYDEV_IO_PRT_PRT1_PRT EQU 0x4000511a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIT_MASK +CYDEV_IO_PRT_PRT1_BIT_MASK EQU 0x4000511b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AMUX +CYDEV_IO_PRT_PRT1_AMUX EQU 0x4000511c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AG +CYDEV_IO_PRT_PRT1_AG EQU 0x4000511d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_COM_SEG +CYDEV_IO_PRT_PRT1_LCD_COM_SEG EQU 0x4000511e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_EN +CYDEV_IO_PRT_PRT1_LCD_EN EQU 0x4000511f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE +CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE +CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DR +CYDEV_IO_PRT_PRT2_DR EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PS +CYDEV_IO_PRT_PRT2_PS EQU 0x40005121 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM0 +CYDEV_IO_PRT_PRT2_DM0 EQU 0x40005122 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM1 +CYDEV_IO_PRT_PRT2_DM1 EQU 0x40005123 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM2 +CYDEV_IO_PRT_PRT2_DM2 EQU 0x40005124 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SLW +CYDEV_IO_PRT_PRT2_SLW EQU 0x40005125 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BYP +CYDEV_IO_PRT_PRT2_BYP EQU 0x40005126 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIE +CYDEV_IO_PRT_PRT2_BIE EQU 0x40005127 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_INP_DIS +CYDEV_IO_PRT_PRT2_INP_DIS EQU 0x40005128 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_CTL +CYDEV_IO_PRT_PRT2_CTL EQU 0x40005129 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PRT +CYDEV_IO_PRT_PRT2_PRT EQU 0x4000512a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIT_MASK +CYDEV_IO_PRT_PRT2_BIT_MASK EQU 0x4000512b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AMUX +CYDEV_IO_PRT_PRT2_AMUX EQU 0x4000512c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AG +CYDEV_IO_PRT_PRT2_AG EQU 0x4000512d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_COM_SEG +CYDEV_IO_PRT_PRT2_LCD_COM_SEG EQU 0x4000512e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_EN +CYDEV_IO_PRT_PRT2_LCD_EN EQU 0x4000512f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE +CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE +CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DR +CYDEV_IO_PRT_PRT3_DR EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PS +CYDEV_IO_PRT_PRT3_PS EQU 0x40005131 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM0 +CYDEV_IO_PRT_PRT3_DM0 EQU 0x40005132 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM1 +CYDEV_IO_PRT_PRT3_DM1 EQU 0x40005133 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM2 +CYDEV_IO_PRT_PRT3_DM2 EQU 0x40005134 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SLW +CYDEV_IO_PRT_PRT3_SLW EQU 0x40005135 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BYP +CYDEV_IO_PRT_PRT3_BYP EQU 0x40005136 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIE +CYDEV_IO_PRT_PRT3_BIE EQU 0x40005137 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_INP_DIS +CYDEV_IO_PRT_PRT3_INP_DIS EQU 0x40005138 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_CTL +CYDEV_IO_PRT_PRT3_CTL EQU 0x40005139 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PRT +CYDEV_IO_PRT_PRT3_PRT EQU 0x4000513a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIT_MASK +CYDEV_IO_PRT_PRT3_BIT_MASK EQU 0x4000513b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AMUX +CYDEV_IO_PRT_PRT3_AMUX EQU 0x4000513c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AG +CYDEV_IO_PRT_PRT3_AG EQU 0x4000513d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_COM_SEG +CYDEV_IO_PRT_PRT3_LCD_COM_SEG EQU 0x4000513e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_EN +CYDEV_IO_PRT_PRT3_LCD_EN EQU 0x4000513f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE +CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE +CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DR +CYDEV_IO_PRT_PRT4_DR EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PS +CYDEV_IO_PRT_PRT4_PS EQU 0x40005141 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM0 +CYDEV_IO_PRT_PRT4_DM0 EQU 0x40005142 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM1 +CYDEV_IO_PRT_PRT4_DM1 EQU 0x40005143 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM2 +CYDEV_IO_PRT_PRT4_DM2 EQU 0x40005144 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SLW +CYDEV_IO_PRT_PRT4_SLW EQU 0x40005145 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BYP +CYDEV_IO_PRT_PRT4_BYP EQU 0x40005146 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIE +CYDEV_IO_PRT_PRT4_BIE EQU 0x40005147 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_INP_DIS +CYDEV_IO_PRT_PRT4_INP_DIS EQU 0x40005148 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_CTL +CYDEV_IO_PRT_PRT4_CTL EQU 0x40005149 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PRT +CYDEV_IO_PRT_PRT4_PRT EQU 0x4000514a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIT_MASK +CYDEV_IO_PRT_PRT4_BIT_MASK EQU 0x4000514b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AMUX +CYDEV_IO_PRT_PRT4_AMUX EQU 0x4000514c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AG +CYDEV_IO_PRT_PRT4_AG EQU 0x4000514d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_COM_SEG +CYDEV_IO_PRT_PRT4_LCD_COM_SEG EQU 0x4000514e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_EN +CYDEV_IO_PRT_PRT4_LCD_EN EQU 0x4000514f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE +CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE +CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DR +CYDEV_IO_PRT_PRT5_DR EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PS +CYDEV_IO_PRT_PRT5_PS EQU 0x40005151 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM0 +CYDEV_IO_PRT_PRT5_DM0 EQU 0x40005152 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM1 +CYDEV_IO_PRT_PRT5_DM1 EQU 0x40005153 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM2 +CYDEV_IO_PRT_PRT5_DM2 EQU 0x40005154 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SLW +CYDEV_IO_PRT_PRT5_SLW EQU 0x40005155 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BYP +CYDEV_IO_PRT_PRT5_BYP EQU 0x40005156 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIE +CYDEV_IO_PRT_PRT5_BIE EQU 0x40005157 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_INP_DIS +CYDEV_IO_PRT_PRT5_INP_DIS EQU 0x40005158 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_CTL +CYDEV_IO_PRT_PRT5_CTL EQU 0x40005159 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PRT +CYDEV_IO_PRT_PRT5_PRT EQU 0x4000515a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIT_MASK +CYDEV_IO_PRT_PRT5_BIT_MASK EQU 0x4000515b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AMUX +CYDEV_IO_PRT_PRT5_AMUX EQU 0x4000515c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AG +CYDEV_IO_PRT_PRT5_AG EQU 0x4000515d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_COM_SEG +CYDEV_IO_PRT_PRT5_LCD_COM_SEG EQU 0x4000515e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_EN +CYDEV_IO_PRT_PRT5_LCD_EN EQU 0x4000515f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE +CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE +CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DR +CYDEV_IO_PRT_PRT6_DR EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PS +CYDEV_IO_PRT_PRT6_PS EQU 0x40005161 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM0 +CYDEV_IO_PRT_PRT6_DM0 EQU 0x40005162 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM1 +CYDEV_IO_PRT_PRT6_DM1 EQU 0x40005163 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM2 +CYDEV_IO_PRT_PRT6_DM2 EQU 0x40005164 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SLW +CYDEV_IO_PRT_PRT6_SLW EQU 0x40005165 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BYP +CYDEV_IO_PRT_PRT6_BYP EQU 0x40005166 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIE +CYDEV_IO_PRT_PRT6_BIE EQU 0x40005167 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_INP_DIS +CYDEV_IO_PRT_PRT6_INP_DIS EQU 0x40005168 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_CTL +CYDEV_IO_PRT_PRT6_CTL EQU 0x40005169 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PRT +CYDEV_IO_PRT_PRT6_PRT EQU 0x4000516a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIT_MASK +CYDEV_IO_PRT_PRT6_BIT_MASK EQU 0x4000516b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AMUX +CYDEV_IO_PRT_PRT6_AMUX EQU 0x4000516c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AG +CYDEV_IO_PRT_PRT6_AG EQU 0x4000516d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_COM_SEG +CYDEV_IO_PRT_PRT6_LCD_COM_SEG EQU 0x4000516e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_EN +CYDEV_IO_PRT_PRT6_LCD_EN EQU 0x4000516f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE +CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE +CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DR +CYDEV_IO_PRT_PRT12_DR EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PS +CYDEV_IO_PRT_PRT12_PS EQU 0x400051c1 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM0 +CYDEV_IO_PRT_PRT12_DM0 EQU 0x400051c2 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM1 +CYDEV_IO_PRT_PRT12_DM1 EQU 0x400051c3 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM2 +CYDEV_IO_PRT_PRT12_DM2 EQU 0x400051c4 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SLW +CYDEV_IO_PRT_PRT12_SLW EQU 0x400051c5 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BYP +CYDEV_IO_PRT_PRT12_BYP EQU 0x400051c6 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIE +CYDEV_IO_PRT_PRT12_BIE EQU 0x400051c7 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_INP_DIS +CYDEV_IO_PRT_PRT12_INP_DIS EQU 0x400051c8 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_HYST_EN +CYDEV_IO_PRT_PRT12_SIO_HYST_EN EQU 0x400051c9 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PRT +CYDEV_IO_PRT_PRT12_PRT EQU 0x400051ca + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIT_MASK +CYDEV_IO_PRT_PRT12_BIT_MASK EQU 0x400051cb + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ +CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ EQU 0x400051cc + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_AG +CYDEV_IO_PRT_PRT12_AG EQU 0x400051cd + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_CFG +CYDEV_IO_PRT_PRT12_SIO_CFG EQU 0x400051ce + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_DIFF +CYDEV_IO_PRT_PRT12_SIO_DIFF EQU 0x400051cf + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE +CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE +CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DR +CYDEV_IO_PRT_PRT15_DR EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PS +CYDEV_IO_PRT_PRT15_PS EQU 0x400051f1 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM0 +CYDEV_IO_PRT_PRT15_DM0 EQU 0x400051f2 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM1 +CYDEV_IO_PRT_PRT15_DM1 EQU 0x400051f3 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM2 +CYDEV_IO_PRT_PRT15_DM2 EQU 0x400051f4 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SLW +CYDEV_IO_PRT_PRT15_SLW EQU 0x400051f5 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BYP +CYDEV_IO_PRT_PRT15_BYP EQU 0x400051f6 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIE +CYDEV_IO_PRT_PRT15_BIE EQU 0x400051f7 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_INP_DIS +CYDEV_IO_PRT_PRT15_INP_DIS EQU 0x400051f8 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_CTL +CYDEV_IO_PRT_PRT15_CTL EQU 0x400051f9 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PRT +CYDEV_IO_PRT_PRT15_PRT EQU 0x400051fa + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIT_MASK +CYDEV_IO_PRT_PRT15_BIT_MASK EQU 0x400051fb + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AMUX +CYDEV_IO_PRT_PRT15_AMUX EQU 0x400051fc + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AG +CYDEV_IO_PRT_PRT15_AG EQU 0x400051fd + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_COM_SEG +CYDEV_IO_PRT_PRT15_LCD_COM_SEG EQU 0x400051fe + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_EN +CYDEV_IO_PRT_PRT15_LCD_EN EQU 0x400051ff + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_BASE +CYDEV_PRTDSI_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_SIZE +CYDEV_PRTDSI_SIZE EQU 0x0000007f + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE +CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE +CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL0 +CYDEV_PRTDSI_PRT0_OUT_SEL0 EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL1 +CYDEV_PRTDSI_PRT0_OUT_SEL1 EQU 0x40005201 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL0 +CYDEV_PRTDSI_PRT0_OE_SEL0 EQU 0x40005202 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL1 +CYDEV_PRTDSI_PRT0_OE_SEL1 EQU 0x40005203 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_DBL_SYNC_IN +CYDEV_PRTDSI_PRT0_DBL_SYNC_IN EQU 0x40005204 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SYNC_OUT +CYDEV_PRTDSI_PRT0_SYNC_OUT EQU 0x40005205 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_CAPS_SEL +CYDEV_PRTDSI_PRT0_CAPS_SEL EQU 0x40005206 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE +CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE +CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL0 +CYDEV_PRTDSI_PRT1_OUT_SEL0 EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL1 +CYDEV_PRTDSI_PRT1_OUT_SEL1 EQU 0x40005209 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL0 +CYDEV_PRTDSI_PRT1_OE_SEL0 EQU 0x4000520a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL1 +CYDEV_PRTDSI_PRT1_OE_SEL1 EQU 0x4000520b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_DBL_SYNC_IN +CYDEV_PRTDSI_PRT1_DBL_SYNC_IN EQU 0x4000520c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SYNC_OUT +CYDEV_PRTDSI_PRT1_SYNC_OUT EQU 0x4000520d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_CAPS_SEL +CYDEV_PRTDSI_PRT1_CAPS_SEL EQU 0x4000520e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE +CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE +CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL0 +CYDEV_PRTDSI_PRT2_OUT_SEL0 EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL1 +CYDEV_PRTDSI_PRT2_OUT_SEL1 EQU 0x40005211 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL0 +CYDEV_PRTDSI_PRT2_OE_SEL0 EQU 0x40005212 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL1 +CYDEV_PRTDSI_PRT2_OE_SEL1 EQU 0x40005213 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_DBL_SYNC_IN +CYDEV_PRTDSI_PRT2_DBL_SYNC_IN EQU 0x40005214 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SYNC_OUT +CYDEV_PRTDSI_PRT2_SYNC_OUT EQU 0x40005215 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_CAPS_SEL +CYDEV_PRTDSI_PRT2_CAPS_SEL EQU 0x40005216 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE +CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE +CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL0 +CYDEV_PRTDSI_PRT3_OUT_SEL0 EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL1 +CYDEV_PRTDSI_PRT3_OUT_SEL1 EQU 0x40005219 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL0 +CYDEV_PRTDSI_PRT3_OE_SEL0 EQU 0x4000521a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL1 +CYDEV_PRTDSI_PRT3_OE_SEL1 EQU 0x4000521b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_DBL_SYNC_IN +CYDEV_PRTDSI_PRT3_DBL_SYNC_IN EQU 0x4000521c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SYNC_OUT +CYDEV_PRTDSI_PRT3_SYNC_OUT EQU 0x4000521d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_CAPS_SEL +CYDEV_PRTDSI_PRT3_CAPS_SEL EQU 0x4000521e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE +CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE +CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL0 +CYDEV_PRTDSI_PRT4_OUT_SEL0 EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL1 +CYDEV_PRTDSI_PRT4_OUT_SEL1 EQU 0x40005221 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL0 +CYDEV_PRTDSI_PRT4_OE_SEL0 EQU 0x40005222 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL1 +CYDEV_PRTDSI_PRT4_OE_SEL1 EQU 0x40005223 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_DBL_SYNC_IN +CYDEV_PRTDSI_PRT4_DBL_SYNC_IN EQU 0x40005224 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SYNC_OUT +CYDEV_PRTDSI_PRT4_SYNC_OUT EQU 0x40005225 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_CAPS_SEL +CYDEV_PRTDSI_PRT4_CAPS_SEL EQU 0x40005226 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE +CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE +CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL0 +CYDEV_PRTDSI_PRT5_OUT_SEL0 EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL1 +CYDEV_PRTDSI_PRT5_OUT_SEL1 EQU 0x40005229 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL0 +CYDEV_PRTDSI_PRT5_OE_SEL0 EQU 0x4000522a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL1 +CYDEV_PRTDSI_PRT5_OE_SEL1 EQU 0x4000522b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_DBL_SYNC_IN +CYDEV_PRTDSI_PRT5_DBL_SYNC_IN EQU 0x4000522c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SYNC_OUT +CYDEV_PRTDSI_PRT5_SYNC_OUT EQU 0x4000522d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_CAPS_SEL +CYDEV_PRTDSI_PRT5_CAPS_SEL EQU 0x4000522e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE +CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE +CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL0 +CYDEV_PRTDSI_PRT6_OUT_SEL0 EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL1 +CYDEV_PRTDSI_PRT6_OUT_SEL1 EQU 0x40005231 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL0 +CYDEV_PRTDSI_PRT6_OE_SEL0 EQU 0x40005232 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL1 +CYDEV_PRTDSI_PRT6_OE_SEL1 EQU 0x40005233 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_DBL_SYNC_IN +CYDEV_PRTDSI_PRT6_DBL_SYNC_IN EQU 0x40005234 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SYNC_OUT +CYDEV_PRTDSI_PRT6_SYNC_OUT EQU 0x40005235 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_CAPS_SEL +CYDEV_PRTDSI_PRT6_CAPS_SEL EQU 0x40005236 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE +CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE +CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL0 +CYDEV_PRTDSI_PRT12_OUT_SEL0 EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL1 +CYDEV_PRTDSI_PRT12_OUT_SEL1 EQU 0x40005261 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL0 +CYDEV_PRTDSI_PRT12_OE_SEL0 EQU 0x40005262 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL1 +CYDEV_PRTDSI_PRT12_OE_SEL1 EQU 0x40005263 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_DBL_SYNC_IN +CYDEV_PRTDSI_PRT12_DBL_SYNC_IN EQU 0x40005264 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SYNC_OUT +CYDEV_PRTDSI_PRT12_SYNC_OUT EQU 0x40005265 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE +CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE +CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL0 +CYDEV_PRTDSI_PRT15_OUT_SEL0 EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL1 +CYDEV_PRTDSI_PRT15_OUT_SEL1 EQU 0x40005279 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL0 +CYDEV_PRTDSI_PRT15_OE_SEL0 EQU 0x4000527a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL1 +CYDEV_PRTDSI_PRT15_OE_SEL1 EQU 0x4000527b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_DBL_SYNC_IN +CYDEV_PRTDSI_PRT15_DBL_SYNC_IN EQU 0x4000527c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SYNC_OUT +CYDEV_PRTDSI_PRT15_SYNC_OUT EQU 0x4000527d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_CAPS_SEL +CYDEV_PRTDSI_PRT15_CAPS_SEL EQU 0x4000527e + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_BASE +CYDEV_EMIF_BASE EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_SIZE +CYDEV_EMIF_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_NO_UDB +CYDEV_EMIF_NO_UDB EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_RP_WAIT_STATES +CYDEV_EMIF_RP_WAIT_STATES EQU 0x40005401 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_MEM_DWN +CYDEV_EMIF_MEM_DWN EQU 0x40005402 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_MEMCLK_DIV +CYDEV_EMIF_MEMCLK_DIV EQU 0x40005403 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_CLOCK_EN +CYDEV_EMIF_CLOCK_EN EQU 0x40005404 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_EM_TYPE +CYDEV_EMIF_EM_TYPE EQU 0x40005405 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_WP_WAIT_STATES +CYDEV_EMIF_WP_WAIT_STATES EQU 0x40005406 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_BASE +CYDEV_ANAIF_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_SIZE +CYDEV_ANAIF_SIZE EQU 0x000003a9 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE +CYDEV_ANAIF_CFG_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE +CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE +CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE +CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR0 +CYDEV_ANAIF_CFG_SC0_CR0 EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR1 +CYDEV_ANAIF_CFG_SC0_CR1 EQU 0x40005801 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR2 +CYDEV_ANAIF_CFG_SC0_CR2 EQU 0x40005802 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE +CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE +CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR0 +CYDEV_ANAIF_CFG_SC1_CR0 EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR1 +CYDEV_ANAIF_CFG_SC1_CR1 EQU 0x40005805 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR2 +CYDEV_ANAIF_CFG_SC1_CR2 EQU 0x40005806 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE +CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE +CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR0 +CYDEV_ANAIF_CFG_SC2_CR0 EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR1 +CYDEV_ANAIF_CFG_SC2_CR1 EQU 0x40005809 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR2 +CYDEV_ANAIF_CFG_SC2_CR2 EQU 0x4000580a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE +CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE +CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR0 +CYDEV_ANAIF_CFG_SC3_CR0 EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR1 +CYDEV_ANAIF_CFG_SC3_CR1 EQU 0x4000580d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR2 +CYDEV_ANAIF_CFG_SC3_CR2 EQU 0x4000580e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE +CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE +CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR0 +CYDEV_ANAIF_CFG_DAC0_CR0 EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR1 +CYDEV_ANAIF_CFG_DAC0_CR1 EQU 0x40005821 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_TST +CYDEV_ANAIF_CFG_DAC0_TST EQU 0x40005822 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE +CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE +CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR0 +CYDEV_ANAIF_CFG_DAC1_CR0 EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR1 +CYDEV_ANAIF_CFG_DAC1_CR1 EQU 0x40005825 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_TST +CYDEV_ANAIF_CFG_DAC1_TST EQU 0x40005826 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE +CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE +CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR0 +CYDEV_ANAIF_CFG_DAC2_CR0 EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR1 +CYDEV_ANAIF_CFG_DAC2_CR1 EQU 0x40005829 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_TST +CYDEV_ANAIF_CFG_DAC2_TST EQU 0x4000582a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE +CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE +CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR0 +CYDEV_ANAIF_CFG_DAC3_CR0 EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR1 +CYDEV_ANAIF_CFG_DAC3_CR1 EQU 0x4000582d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_TST +CYDEV_ANAIF_CFG_DAC3_TST EQU 0x4000582e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE +CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE +CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_CR +CYDEV_ANAIF_CFG_CMP0_CR EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE +CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE +CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_CR +CYDEV_ANAIF_CFG_CMP1_CR EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE +CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE +CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_CR +CYDEV_ANAIF_CFG_CMP2_CR EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE +CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE +CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_CR +CYDEV_ANAIF_CFG_CMP3_CR EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE +CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE +CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_CR +CYDEV_ANAIF_CFG_LUT0_CR EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_MX +CYDEV_ANAIF_CFG_LUT0_MX EQU 0x40005849 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE +CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE +CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_CR +CYDEV_ANAIF_CFG_LUT1_CR EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_MX +CYDEV_ANAIF_CFG_LUT1_MX EQU 0x4000584b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE +CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE +CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_CR +CYDEV_ANAIF_CFG_LUT2_CR EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_MX +CYDEV_ANAIF_CFG_LUT2_MX EQU 0x4000584d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE +CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE +CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_CR +CYDEV_ANAIF_CFG_LUT3_CR EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_MX +CYDEV_ANAIF_CFG_LUT3_MX EQU 0x4000584f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE +CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE +CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_CR +CYDEV_ANAIF_CFG_OPAMP0_CR EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_RSVD +CYDEV_ANAIF_CFG_OPAMP0_RSVD EQU 0x40005859 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE +CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE +CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_CR +CYDEV_ANAIF_CFG_OPAMP1_CR EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_RSVD +CYDEV_ANAIF_CFG_OPAMP1_RSVD EQU 0x4000585b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE +CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE +CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_CR +CYDEV_ANAIF_CFG_OPAMP2_CR EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_RSVD +CYDEV_ANAIF_CFG_OPAMP2_RSVD EQU 0x4000585d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE +CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE +CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_CR +CYDEV_ANAIF_CFG_OPAMP3_CR EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_RSVD +CYDEV_ANAIF_CFG_OPAMP3_RSVD EQU 0x4000585f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE +CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE +CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR0 +CYDEV_ANAIF_CFG_LCDDAC_CR0 EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR1 +CYDEV_ANAIF_CFG_LCDDAC_CR1 EQU 0x40005869 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE +CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE +CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_CR +CYDEV_ANAIF_CFG_LCDDRV_CR EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE +CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE +CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_CFG +CYDEV_ANAIF_CFG_LCDTMR_CFG EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE +CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE +CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_CR0 +CYDEV_ANAIF_CFG_BG_CR0 EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_RSVD +CYDEV_ANAIF_CFG_BG_RSVD EQU 0x4000586d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT0 +CYDEV_ANAIF_CFG_BG_DFT0 EQU 0x4000586e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT1 +CYDEV_ANAIF_CFG_BG_DFT1 EQU 0x4000586f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE +CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE +CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG0 +CYDEV_ANAIF_CFG_CAPSL_CFG0 EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG1 +CYDEV_ANAIF_CFG_CAPSL_CFG1 EQU 0x40005871 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE +CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE +CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG0 +CYDEV_ANAIF_CFG_CAPSR_CFG0 EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG1 +CYDEV_ANAIF_CFG_CAPSR_CFG1 EQU 0x40005873 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE +CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE +CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR0 +CYDEV_ANAIF_CFG_PUMP_CR0 EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR1 +CYDEV_ANAIF_CFG_PUMP_CR1 EQU 0x40005877 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE +CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE +CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_CR0 +CYDEV_ANAIF_CFG_LPF0_CR0 EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_RSVD +CYDEV_ANAIF_CFG_LPF0_RSVD EQU 0x40005879 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE +CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE +CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_CR0 +CYDEV_ANAIF_CFG_LPF1_CR0 EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_RSVD +CYDEV_ANAIF_CFG_LPF1_RSVD EQU 0x4000587b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE +CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE +CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_CR0 +CYDEV_ANAIF_CFG_MISC_CR0 EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE +CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE +CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR0 +CYDEV_ANAIF_CFG_DSM0_CR0 EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR1 +CYDEV_ANAIF_CFG_DSM0_CR1 EQU 0x40005881 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR2 +CYDEV_ANAIF_CFG_DSM0_CR2 EQU 0x40005882 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR3 +CYDEV_ANAIF_CFG_DSM0_CR3 EQU 0x40005883 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR4 +CYDEV_ANAIF_CFG_DSM0_CR4 EQU 0x40005884 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR5 +CYDEV_ANAIF_CFG_DSM0_CR5 EQU 0x40005885 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR6 +CYDEV_ANAIF_CFG_DSM0_CR6 EQU 0x40005886 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR7 +CYDEV_ANAIF_CFG_DSM0_CR7 EQU 0x40005887 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR8 +CYDEV_ANAIF_CFG_DSM0_CR8 EQU 0x40005888 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR9 +CYDEV_ANAIF_CFG_DSM0_CR9 EQU 0x40005889 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR10 +CYDEV_ANAIF_CFG_DSM0_CR10 EQU 0x4000588a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR11 +CYDEV_ANAIF_CFG_DSM0_CR11 EQU 0x4000588b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR12 +CYDEV_ANAIF_CFG_DSM0_CR12 EQU 0x4000588c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR13 +CYDEV_ANAIF_CFG_DSM0_CR13 EQU 0x4000588d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR14 +CYDEV_ANAIF_CFG_DSM0_CR14 EQU 0x4000588e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR15 +CYDEV_ANAIF_CFG_DSM0_CR15 EQU 0x4000588f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR16 +CYDEV_ANAIF_CFG_DSM0_CR16 EQU 0x40005890 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR17 +CYDEV_ANAIF_CFG_DSM0_CR17 EQU 0x40005891 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF0 +CYDEV_ANAIF_CFG_DSM0_REF0 EQU 0x40005892 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF1 +CYDEV_ANAIF_CFG_DSM0_REF1 EQU 0x40005893 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF2 +CYDEV_ANAIF_CFG_DSM0_REF2 EQU 0x40005894 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF3 +CYDEV_ANAIF_CFG_DSM0_REF3 EQU 0x40005895 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM0 +CYDEV_ANAIF_CFG_DSM0_DEM0 EQU 0x40005896 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM1 +CYDEV_ANAIF_CFG_DSM0_DEM1 EQU 0x40005897 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST0 +CYDEV_ANAIF_CFG_DSM0_TST0 EQU 0x40005898 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST1 +CYDEV_ANAIF_CFG_DSM0_TST1 EQU 0x40005899 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF0 +CYDEV_ANAIF_CFG_DSM0_BUF0 EQU 0x4000589a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF1 +CYDEV_ANAIF_CFG_DSM0_BUF1 EQU 0x4000589b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF2 +CYDEV_ANAIF_CFG_DSM0_BUF2 EQU 0x4000589c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF3 +CYDEV_ANAIF_CFG_DSM0_BUF3 EQU 0x4000589d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_MISC +CYDEV_ANAIF_CFG_DSM0_MISC EQU 0x4000589e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_RSVD1 +CYDEV_ANAIF_CFG_DSM0_RSVD1 EQU 0x4000589f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE +CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE +CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR0 +CYDEV_ANAIF_CFG_SAR0_CSR0 EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR1 +CYDEV_ANAIF_CFG_SAR0_CSR1 EQU 0x40005901 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR2 +CYDEV_ANAIF_CFG_SAR0_CSR2 EQU 0x40005902 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR3 +CYDEV_ANAIF_CFG_SAR0_CSR3 EQU 0x40005903 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR4 +CYDEV_ANAIF_CFG_SAR0_CSR4 EQU 0x40005904 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR5 +CYDEV_ANAIF_CFG_SAR0_CSR5 EQU 0x40005905 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR6 +CYDEV_ANAIF_CFG_SAR0_CSR6 EQU 0x40005906 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE +CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE +CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR0 +CYDEV_ANAIF_CFG_SAR1_CSR0 EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR1 +CYDEV_ANAIF_CFG_SAR1_CSR1 EQU 0x40005909 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR2 +CYDEV_ANAIF_CFG_SAR1_CSR2 EQU 0x4000590a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR3 +CYDEV_ANAIF_CFG_SAR1_CSR3 EQU 0x4000590b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR4 +CYDEV_ANAIF_CFG_SAR1_CSR4 EQU 0x4000590c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR5 +CYDEV_ANAIF_CFG_SAR1_CSR5 EQU 0x4000590d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR6 +CYDEV_ANAIF_CFG_SAR1_CSR6 EQU 0x4000590e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE +CYDEV_ANAIF_RT_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE +CYDEV_ANAIF_RT_SIZE EQU 0x00000162 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE +CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE +CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW0 +CYDEV_ANAIF_RT_SC0_SW0 EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW2 +CYDEV_ANAIF_RT_SC0_SW2 EQU 0x40005a02 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW3 +CYDEV_ANAIF_RT_SC0_SW3 EQU 0x40005a03 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW4 +CYDEV_ANAIF_RT_SC0_SW4 EQU 0x40005a04 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW6 +CYDEV_ANAIF_RT_SC0_SW6 EQU 0x40005a06 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW7 +CYDEV_ANAIF_RT_SC0_SW7 EQU 0x40005a07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW8 +CYDEV_ANAIF_RT_SC0_SW8 EQU 0x40005a08 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW10 +CYDEV_ANAIF_RT_SC0_SW10 EQU 0x40005a0a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_CLK +CYDEV_ANAIF_RT_SC0_CLK EQU 0x40005a0b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BST +CYDEV_ANAIF_RT_SC0_BST EQU 0x40005a0c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE +CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE +CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW0 +CYDEV_ANAIF_RT_SC1_SW0 EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW2 +CYDEV_ANAIF_RT_SC1_SW2 EQU 0x40005a12 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW3 +CYDEV_ANAIF_RT_SC1_SW3 EQU 0x40005a13 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW4 +CYDEV_ANAIF_RT_SC1_SW4 EQU 0x40005a14 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW6 +CYDEV_ANAIF_RT_SC1_SW6 EQU 0x40005a16 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW7 +CYDEV_ANAIF_RT_SC1_SW7 EQU 0x40005a17 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW8 +CYDEV_ANAIF_RT_SC1_SW8 EQU 0x40005a18 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW10 +CYDEV_ANAIF_RT_SC1_SW10 EQU 0x40005a1a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_CLK +CYDEV_ANAIF_RT_SC1_CLK EQU 0x40005a1b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BST +CYDEV_ANAIF_RT_SC1_BST EQU 0x40005a1c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE +CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE +CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW0 +CYDEV_ANAIF_RT_SC2_SW0 EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW2 +CYDEV_ANAIF_RT_SC2_SW2 EQU 0x40005a22 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW3 +CYDEV_ANAIF_RT_SC2_SW3 EQU 0x40005a23 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW4 +CYDEV_ANAIF_RT_SC2_SW4 EQU 0x40005a24 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW6 +CYDEV_ANAIF_RT_SC2_SW6 EQU 0x40005a26 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW7 +CYDEV_ANAIF_RT_SC2_SW7 EQU 0x40005a27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW8 +CYDEV_ANAIF_RT_SC2_SW8 EQU 0x40005a28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW10 +CYDEV_ANAIF_RT_SC2_SW10 EQU 0x40005a2a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_CLK +CYDEV_ANAIF_RT_SC2_CLK EQU 0x40005a2b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BST +CYDEV_ANAIF_RT_SC2_BST EQU 0x40005a2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE +CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE +CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW0 +CYDEV_ANAIF_RT_SC3_SW0 EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW2 +CYDEV_ANAIF_RT_SC3_SW2 EQU 0x40005a32 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW3 +CYDEV_ANAIF_RT_SC3_SW3 EQU 0x40005a33 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW4 +CYDEV_ANAIF_RT_SC3_SW4 EQU 0x40005a34 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW6 +CYDEV_ANAIF_RT_SC3_SW6 EQU 0x40005a36 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW7 +CYDEV_ANAIF_RT_SC3_SW7 EQU 0x40005a37 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW8 +CYDEV_ANAIF_RT_SC3_SW8 EQU 0x40005a38 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW10 +CYDEV_ANAIF_RT_SC3_SW10 EQU 0x40005a3a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_CLK +CYDEV_ANAIF_RT_SC3_CLK EQU 0x40005a3b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BST +CYDEV_ANAIF_RT_SC3_BST EQU 0x40005a3c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE +CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE +CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW0 +CYDEV_ANAIF_RT_DAC0_SW0 EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW2 +CYDEV_ANAIF_RT_DAC0_SW2 EQU 0x40005a82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW3 +CYDEV_ANAIF_RT_DAC0_SW3 EQU 0x40005a83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW4 +CYDEV_ANAIF_RT_DAC0_SW4 EQU 0x40005a84 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_STROBE +CYDEV_ANAIF_RT_DAC0_STROBE EQU 0x40005a87 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE +CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE +CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW0 +CYDEV_ANAIF_RT_DAC1_SW0 EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW2 +CYDEV_ANAIF_RT_DAC1_SW2 EQU 0x40005a8a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW3 +CYDEV_ANAIF_RT_DAC1_SW3 EQU 0x40005a8b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW4 +CYDEV_ANAIF_RT_DAC1_SW4 EQU 0x40005a8c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_STROBE +CYDEV_ANAIF_RT_DAC1_STROBE EQU 0x40005a8f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE +CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE +CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW0 +CYDEV_ANAIF_RT_DAC2_SW0 EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW2 +CYDEV_ANAIF_RT_DAC2_SW2 EQU 0x40005a92 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW3 +CYDEV_ANAIF_RT_DAC2_SW3 EQU 0x40005a93 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW4 +CYDEV_ANAIF_RT_DAC2_SW4 EQU 0x40005a94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_STROBE +CYDEV_ANAIF_RT_DAC2_STROBE EQU 0x40005a97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE +CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE +CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW0 +CYDEV_ANAIF_RT_DAC3_SW0 EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW2 +CYDEV_ANAIF_RT_DAC3_SW2 EQU 0x40005a9a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW3 +CYDEV_ANAIF_RT_DAC3_SW3 EQU 0x40005a9b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW4 +CYDEV_ANAIF_RT_DAC3_SW4 EQU 0x40005a9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_STROBE +CYDEV_ANAIF_RT_DAC3_STROBE EQU 0x40005a9f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE +CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE +CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW0 +CYDEV_ANAIF_RT_CMP0_SW0 EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW2 +CYDEV_ANAIF_RT_CMP0_SW2 EQU 0x40005ac2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW3 +CYDEV_ANAIF_RT_CMP0_SW3 EQU 0x40005ac3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW4 +CYDEV_ANAIF_RT_CMP0_SW4 EQU 0x40005ac4 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW6 +CYDEV_ANAIF_RT_CMP0_SW6 EQU 0x40005ac6 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_CLK +CYDEV_ANAIF_RT_CMP0_CLK EQU 0x40005ac7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE +CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE +CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW0 +CYDEV_ANAIF_RT_CMP1_SW0 EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW2 +CYDEV_ANAIF_RT_CMP1_SW2 EQU 0x40005aca + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW3 +CYDEV_ANAIF_RT_CMP1_SW3 EQU 0x40005acb + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW4 +CYDEV_ANAIF_RT_CMP1_SW4 EQU 0x40005acc + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW6 +CYDEV_ANAIF_RT_CMP1_SW6 EQU 0x40005ace + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_CLK +CYDEV_ANAIF_RT_CMP1_CLK EQU 0x40005acf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE +CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE +CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW0 +CYDEV_ANAIF_RT_CMP2_SW0 EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW2 +CYDEV_ANAIF_RT_CMP2_SW2 EQU 0x40005ad2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW3 +CYDEV_ANAIF_RT_CMP2_SW3 EQU 0x40005ad3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW4 +CYDEV_ANAIF_RT_CMP2_SW4 EQU 0x40005ad4 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW6 +CYDEV_ANAIF_RT_CMP2_SW6 EQU 0x40005ad6 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_CLK +CYDEV_ANAIF_RT_CMP2_CLK EQU 0x40005ad7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE +CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE +CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW0 +CYDEV_ANAIF_RT_CMP3_SW0 EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW2 +CYDEV_ANAIF_RT_CMP3_SW2 EQU 0x40005ada + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW3 +CYDEV_ANAIF_RT_CMP3_SW3 EQU 0x40005adb + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW4 +CYDEV_ANAIF_RT_CMP3_SW4 EQU 0x40005adc + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW6 +CYDEV_ANAIF_RT_CMP3_SW6 EQU 0x40005ade + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_CLK +CYDEV_ANAIF_RT_CMP3_CLK EQU 0x40005adf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE +CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE +CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW0 +CYDEV_ANAIF_RT_DSM0_SW0 EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW2 +CYDEV_ANAIF_RT_DSM0_SW2 EQU 0x40005b02 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW3 +CYDEV_ANAIF_RT_DSM0_SW3 EQU 0x40005b03 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW4 +CYDEV_ANAIF_RT_DSM0_SW4 EQU 0x40005b04 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW6 +CYDEV_ANAIF_RT_DSM0_SW6 EQU 0x40005b06 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_CLK +CYDEV_ANAIF_RT_DSM0_CLK EQU 0x40005b07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE +CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE +CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW0 +CYDEV_ANAIF_RT_SAR0_SW0 EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW2 +CYDEV_ANAIF_RT_SAR0_SW2 EQU 0x40005b22 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW3 +CYDEV_ANAIF_RT_SAR0_SW3 EQU 0x40005b23 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW4 +CYDEV_ANAIF_RT_SAR0_SW4 EQU 0x40005b24 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW6 +CYDEV_ANAIF_RT_SAR0_SW6 EQU 0x40005b26 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_CLK +CYDEV_ANAIF_RT_SAR0_CLK EQU 0x40005b27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE +CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE +CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW0 +CYDEV_ANAIF_RT_SAR1_SW0 EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW2 +CYDEV_ANAIF_RT_SAR1_SW2 EQU 0x40005b2a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW3 +CYDEV_ANAIF_RT_SAR1_SW3 EQU 0x40005b2b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW4 +CYDEV_ANAIF_RT_SAR1_SW4 EQU 0x40005b2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW6 +CYDEV_ANAIF_RT_SAR1_SW6 EQU 0x40005b2e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_CLK +CYDEV_ANAIF_RT_SAR1_CLK EQU 0x40005b2f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE +CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE +CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_MX +CYDEV_ANAIF_RT_OPAMP0_MX EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SW +CYDEV_ANAIF_RT_OPAMP0_SW EQU 0x40005b41 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE +CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE +CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_MX +CYDEV_ANAIF_RT_OPAMP1_MX EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SW +CYDEV_ANAIF_RT_OPAMP1_SW EQU 0x40005b43 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE +CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE +CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_MX +CYDEV_ANAIF_RT_OPAMP2_MX EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SW +CYDEV_ANAIF_RT_OPAMP2_SW EQU 0x40005b45 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE +CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE +CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_MX +CYDEV_ANAIF_RT_OPAMP3_MX EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SW +CYDEV_ANAIF_RT_OPAMP3_SW EQU 0x40005b47 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE +CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE +CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW0 +CYDEV_ANAIF_RT_LCDDAC_SW0 EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW1 +CYDEV_ANAIF_RT_LCDDAC_SW1 EQU 0x40005b51 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW2 +CYDEV_ANAIF_RT_LCDDAC_SW2 EQU 0x40005b52 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW3 +CYDEV_ANAIF_RT_LCDDAC_SW3 EQU 0x40005b53 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW4 +CYDEV_ANAIF_RT_LCDDAC_SW4 EQU 0x40005b54 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE +CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE +CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_MISC +CYDEV_ANAIF_RT_SC_MISC EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE +CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE +CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW0 +CYDEV_ANAIF_RT_BUS_SW0 EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW2 +CYDEV_ANAIF_RT_BUS_SW2 EQU 0x40005b5a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW3 +CYDEV_ANAIF_RT_BUS_SW3 EQU 0x40005b5b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE +CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE +CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR0 +CYDEV_ANAIF_RT_DFT_CR0 EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR1 +CYDEV_ANAIF_RT_DFT_CR1 EQU 0x40005b5d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR2 +CYDEV_ANAIF_RT_DFT_CR2 EQU 0x40005b5e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR3 +CYDEV_ANAIF_RT_DFT_CR3 EQU 0x40005b5f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR4 +CYDEV_ANAIF_RT_DFT_CR4 EQU 0x40005b60 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR5 +CYDEV_ANAIF_RT_DFT_CR5 EQU 0x40005b61 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE +CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE +CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE +CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE +CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_D +CYDEV_ANAIF_WRK_DAC0_D EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE +CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE +CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_D +CYDEV_ANAIF_WRK_DAC1_D EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE +CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE +CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_D +CYDEV_ANAIF_WRK_DAC2_D EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE +CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE +CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_D +CYDEV_ANAIF_WRK_DAC3_D EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE +CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE +CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT0 +CYDEV_ANAIF_WRK_DSM0_OUT0 EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT1 +CYDEV_ANAIF_WRK_DSM0_OUT1 EQU 0x40005b89 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE +CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE +CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SR +CYDEV_ANAIF_WRK_LUT_SR EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_WRK1 +CYDEV_ANAIF_WRK_LUT_WRK1 EQU 0x40005b91 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_MSK +CYDEV_ANAIF_WRK_LUT_MSK EQU 0x40005b92 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CLK +CYDEV_ANAIF_WRK_LUT_CLK EQU 0x40005b93 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CPTR +CYDEV_ANAIF_WRK_LUT_CPTR EQU 0x40005b94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE +CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE +CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_WRK +CYDEV_ANAIF_WRK_CMP_WRK EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_TST +CYDEV_ANAIF_WRK_CMP_TST EQU 0x40005b97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE +CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE +CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SR +CYDEV_ANAIF_WRK_SC_SR EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_WRK1 +CYDEV_ANAIF_WRK_SC_WRK1 EQU 0x40005b99 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_MSK +CYDEV_ANAIF_WRK_SC_MSK EQU 0x40005b9a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CMPINV +CYDEV_ANAIF_WRK_SC_CMPINV EQU 0x40005b9b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CPTR +CYDEV_ANAIF_WRK_SC_CPTR EQU 0x40005b9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE +CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE +CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK0 +CYDEV_ANAIF_WRK_SAR0_WRK0 EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK1 +CYDEV_ANAIF_WRK_SAR0_WRK1 EQU 0x40005ba1 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE +CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE +CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK0 +CYDEV_ANAIF_WRK_SAR1_WRK0 EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK1 +CYDEV_ANAIF_WRK_SAR1_WRK1 EQU 0x40005ba3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE +CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE +CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SOF +CYDEV_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BASE +CYDEV_USB_BASE EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIZE +CYDEV_USB_SIZE EQU 0x00000300 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR0 +CYDEV_USB_EP0_DR0 EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR1 +CYDEV_USB_EP0_DR1 EQU 0x40006001 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR2 +CYDEV_USB_EP0_DR2 EQU 0x40006002 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR3 +CYDEV_USB_EP0_DR3 EQU 0x40006003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR4 +CYDEV_USB_EP0_DR4 EQU 0x40006004 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR5 +CYDEV_USB_EP0_DR5 EQU 0x40006005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR6 +CYDEV_USB_EP0_DR6 EQU 0x40006006 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR7 +CYDEV_USB_EP0_DR7 EQU 0x40006007 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CR0 +CYDEV_USB_CR0 EQU 0x40006008 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CR1 +CYDEV_USB_CR1 EQU 0x40006009 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_EN +CYDEV_USB_SIE_EP_INT_EN EQU 0x4000600a + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_SR +CYDEV_USB_SIE_EP_INT_SR EQU 0x4000600b + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE +CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE +CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT0 +CYDEV_USB_SIE_EP1_CNT0 EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT1 +CYDEV_USB_SIE_EP1_CNT1 EQU 0x4000600d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CR0 +CYDEV_USB_SIE_EP1_CR0 EQU 0x4000600e + ENDIF + IF :LNOT::DEF:CYDEV_USB_USBIO_CR0 +CYDEV_USB_USBIO_CR0 EQU 0x40006010 + ENDIF + IF :LNOT::DEF:CYDEV_USB_USBIO_CR1 +CYDEV_USB_USBIO_CR1 EQU 0x40006012 + ENDIF + IF :LNOT::DEF:CYDEV_USB_DYN_RECONFIG +CYDEV_USB_DYN_RECONFIG EQU 0x40006014 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SOF0 +CYDEV_USB_SOF0 EQU 0x40006018 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SOF1 +CYDEV_USB_SOF1 EQU 0x40006019 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE +CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE +CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT0 +CYDEV_USB_SIE_EP2_CNT0 EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT1 +CYDEV_USB_SIE_EP2_CNT1 EQU 0x4000601d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CR0 +CYDEV_USB_SIE_EP2_CR0 EQU 0x4000601e + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_CR +CYDEV_USB_EP0_CR EQU 0x40006028 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_CNT +CYDEV_USB_EP0_CNT EQU 0x40006029 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE +CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE +CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT0 +CYDEV_USB_SIE_EP3_CNT0 EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT1 +CYDEV_USB_SIE_EP3_CNT1 EQU 0x4000602d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CR0 +CYDEV_USB_SIE_EP3_CR0 EQU 0x4000602e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE +CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE +CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT0 +CYDEV_USB_SIE_EP4_CNT0 EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT1 +CYDEV_USB_SIE_EP4_CNT1 EQU 0x4000603d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CR0 +CYDEV_USB_SIE_EP4_CR0 EQU 0x4000603e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE +CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE +CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT0 +CYDEV_USB_SIE_EP5_CNT0 EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT1 +CYDEV_USB_SIE_EP5_CNT1 EQU 0x4000604d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CR0 +CYDEV_USB_SIE_EP5_CR0 EQU 0x4000604e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE +CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE +CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT0 +CYDEV_USB_SIE_EP6_CNT0 EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT1 +CYDEV_USB_SIE_EP6_CNT1 EQU 0x4000605d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CR0 +CYDEV_USB_SIE_EP6_CR0 EQU 0x4000605e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE +CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE +CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT0 +CYDEV_USB_SIE_EP7_CNT0 EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT1 +CYDEV_USB_SIE_EP7_CNT1 EQU 0x4000606d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CR0 +CYDEV_USB_SIE_EP7_CR0 EQU 0x4000606e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE +CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE +CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT0 +CYDEV_USB_SIE_EP8_CNT0 EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT1 +CYDEV_USB_SIE_EP8_CNT1 EQU 0x4000607d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CR0 +CYDEV_USB_SIE_EP8_CR0 EQU 0x4000607e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE +CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE +CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_CFG +CYDEV_USB_ARB_EP1_CFG EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_INT_EN +CYDEV_USB_ARB_EP1_INT_EN EQU 0x40006081 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SR +CYDEV_USB_ARB_EP1_SR EQU 0x40006082 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE +CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE +CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA +CYDEV_USB_ARB_RW1_WA EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA_MSB +CYDEV_USB_ARB_RW1_WA_MSB EQU 0x40006085 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA +CYDEV_USB_ARB_RW1_RA EQU 0x40006086 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA_MSB +CYDEV_USB_ARB_RW1_RA_MSB EQU 0x40006087 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_DR +CYDEV_USB_ARB_RW1_DR EQU 0x40006088 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BUF_SIZE +CYDEV_USB_BUF_SIZE EQU 0x4000608c + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP_ACTIVE +CYDEV_USB_EP_ACTIVE EQU 0x4000608e + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP_TYPE +CYDEV_USB_EP_TYPE EQU 0x4000608f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE +CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE +CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_CFG +CYDEV_USB_ARB_EP2_CFG EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_INT_EN +CYDEV_USB_ARB_EP2_INT_EN EQU 0x40006091 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SR +CYDEV_USB_ARB_EP2_SR EQU 0x40006092 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE +CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE +CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA +CYDEV_USB_ARB_RW2_WA EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA_MSB +CYDEV_USB_ARB_RW2_WA_MSB EQU 0x40006095 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA +CYDEV_USB_ARB_RW2_RA EQU 0x40006096 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA_MSB +CYDEV_USB_ARB_RW2_RA_MSB EQU 0x40006097 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_DR +CYDEV_USB_ARB_RW2_DR EQU 0x40006098 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_CFG +CYDEV_USB_ARB_CFG EQU 0x4000609c + ENDIF + IF :LNOT::DEF:CYDEV_USB_USB_CLK_EN +CYDEV_USB_USB_CLK_EN EQU 0x4000609d + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_INT_EN +CYDEV_USB_ARB_INT_EN EQU 0x4000609e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_INT_SR +CYDEV_USB_ARB_INT_SR EQU 0x4000609f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE +CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE +CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_CFG +CYDEV_USB_ARB_EP3_CFG EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_INT_EN +CYDEV_USB_ARB_EP3_INT_EN EQU 0x400060a1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SR +CYDEV_USB_ARB_EP3_SR EQU 0x400060a2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE +CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE +CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA +CYDEV_USB_ARB_RW3_WA EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA_MSB +CYDEV_USB_ARB_RW3_WA_MSB EQU 0x400060a5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA +CYDEV_USB_ARB_RW3_RA EQU 0x400060a6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA_MSB +CYDEV_USB_ARB_RW3_RA_MSB EQU 0x400060a7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_DR +CYDEV_USB_ARB_RW3_DR EQU 0x400060a8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CWA +CYDEV_USB_CWA EQU 0x400060ac + ENDIF + IF :LNOT::DEF:CYDEV_USB_CWA_MSB +CYDEV_USB_CWA_MSB EQU 0x400060ad + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE +CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE +CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_CFG +CYDEV_USB_ARB_EP4_CFG EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_INT_EN +CYDEV_USB_ARB_EP4_INT_EN EQU 0x400060b1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SR +CYDEV_USB_ARB_EP4_SR EQU 0x400060b2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE +CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE +CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA +CYDEV_USB_ARB_RW4_WA EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA_MSB +CYDEV_USB_ARB_RW4_WA_MSB EQU 0x400060b5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA +CYDEV_USB_ARB_RW4_RA EQU 0x400060b6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA_MSB +CYDEV_USB_ARB_RW4_RA_MSB EQU 0x400060b7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_DR +CYDEV_USB_ARB_RW4_DR EQU 0x400060b8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_DMA_THRES +CYDEV_USB_DMA_THRES EQU 0x400060bc + ENDIF + IF :LNOT::DEF:CYDEV_USB_DMA_THRES_MSB +CYDEV_USB_DMA_THRES_MSB EQU 0x400060bd + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE +CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE +CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_CFG +CYDEV_USB_ARB_EP5_CFG EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_INT_EN +CYDEV_USB_ARB_EP5_INT_EN EQU 0x400060c1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SR +CYDEV_USB_ARB_EP5_SR EQU 0x400060c2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE +CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE +CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA +CYDEV_USB_ARB_RW5_WA EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA_MSB +CYDEV_USB_ARB_RW5_WA_MSB EQU 0x400060c5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA +CYDEV_USB_ARB_RW5_RA EQU 0x400060c6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA_MSB +CYDEV_USB_ARB_RW5_RA_MSB EQU 0x400060c7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_DR +CYDEV_USB_ARB_RW5_DR EQU 0x400060c8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BUS_RST_CNT +CYDEV_USB_BUS_RST_CNT EQU 0x400060cc + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE +CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE +CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_CFG +CYDEV_USB_ARB_EP6_CFG EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_INT_EN +CYDEV_USB_ARB_EP6_INT_EN EQU 0x400060d1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SR +CYDEV_USB_ARB_EP6_SR EQU 0x400060d2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE +CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE +CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA +CYDEV_USB_ARB_RW6_WA EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA_MSB +CYDEV_USB_ARB_RW6_WA_MSB EQU 0x400060d5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA +CYDEV_USB_ARB_RW6_RA EQU 0x400060d6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA_MSB +CYDEV_USB_ARB_RW6_RA_MSB EQU 0x400060d7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_DR +CYDEV_USB_ARB_RW6_DR EQU 0x400060d8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE +CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE +CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_CFG +CYDEV_USB_ARB_EP7_CFG EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_INT_EN +CYDEV_USB_ARB_EP7_INT_EN EQU 0x400060e1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SR +CYDEV_USB_ARB_EP7_SR EQU 0x400060e2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE +CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE +CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA +CYDEV_USB_ARB_RW7_WA EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA_MSB +CYDEV_USB_ARB_RW7_WA_MSB EQU 0x400060e5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA +CYDEV_USB_ARB_RW7_RA EQU 0x400060e6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA_MSB +CYDEV_USB_ARB_RW7_RA_MSB EQU 0x400060e7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_DR +CYDEV_USB_ARB_RW7_DR EQU 0x400060e8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE +CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE +CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_CFG +CYDEV_USB_ARB_EP8_CFG EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_INT_EN +CYDEV_USB_ARB_EP8_INT_EN EQU 0x400060f1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SR +CYDEV_USB_ARB_EP8_SR EQU 0x400060f2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE +CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE +CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA +CYDEV_USB_ARB_RW8_WA EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA_MSB +CYDEV_USB_ARB_RW8_WA_MSB EQU 0x400060f5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA +CYDEV_USB_ARB_RW8_RA EQU 0x400060f6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA_MSB +CYDEV_USB_ARB_RW8_RA_MSB EQU 0x400060f7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_DR +CYDEV_USB_ARB_RW8_DR EQU 0x400060f8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_BASE +CYDEV_USB_MEM_BASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_SIZE +CYDEV_USB_MEM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MBASE +CYDEV_USB_MEM_DATA_MBASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MSIZE +CYDEV_USB_MEM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_BASE +CYDEV_UWRK_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_SIZE +CYDEV_UWRK_SIZE EQU 0x00000b60 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE +CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE +CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE +CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE +CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A0 +CYDEV_UWRK_UWRK8_B0_UDB00_A0 EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A0 +CYDEV_UWRK_UWRK8_B0_UDB01_A0 EQU 0x40006401 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A0 +CYDEV_UWRK_UWRK8_B0_UDB02_A0 EQU 0x40006402 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A0 +CYDEV_UWRK_UWRK8_B0_UDB03_A0 EQU 0x40006403 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A0 +CYDEV_UWRK_UWRK8_B0_UDB04_A0 EQU 0x40006404 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A0 +CYDEV_UWRK_UWRK8_B0_UDB05_A0 EQU 0x40006405 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A0 +CYDEV_UWRK_UWRK8_B0_UDB06_A0 EQU 0x40006406 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A0 +CYDEV_UWRK_UWRK8_B0_UDB07_A0 EQU 0x40006407 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A0 +CYDEV_UWRK_UWRK8_B0_UDB08_A0 EQU 0x40006408 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A0 +CYDEV_UWRK_UWRK8_B0_UDB09_A0 EQU 0x40006409 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A0 +CYDEV_UWRK_UWRK8_B0_UDB10_A0 EQU 0x4000640a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A0 +CYDEV_UWRK_UWRK8_B0_UDB11_A0 EQU 0x4000640b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A0 +CYDEV_UWRK_UWRK8_B0_UDB12_A0 EQU 0x4000640c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A0 +CYDEV_UWRK_UWRK8_B0_UDB13_A0 EQU 0x4000640d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A0 +CYDEV_UWRK_UWRK8_B0_UDB14_A0 EQU 0x4000640e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A0 +CYDEV_UWRK_UWRK8_B0_UDB15_A0 EQU 0x4000640f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A1 +CYDEV_UWRK_UWRK8_B0_UDB00_A1 EQU 0x40006410 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A1 +CYDEV_UWRK_UWRK8_B0_UDB01_A1 EQU 0x40006411 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A1 +CYDEV_UWRK_UWRK8_B0_UDB02_A1 EQU 0x40006412 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A1 +CYDEV_UWRK_UWRK8_B0_UDB03_A1 EQU 0x40006413 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A1 +CYDEV_UWRK_UWRK8_B0_UDB04_A1 EQU 0x40006414 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A1 +CYDEV_UWRK_UWRK8_B0_UDB05_A1 EQU 0x40006415 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A1 +CYDEV_UWRK_UWRK8_B0_UDB06_A1 EQU 0x40006416 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A1 +CYDEV_UWRK_UWRK8_B0_UDB07_A1 EQU 0x40006417 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A1 +CYDEV_UWRK_UWRK8_B0_UDB08_A1 EQU 0x40006418 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A1 +CYDEV_UWRK_UWRK8_B0_UDB09_A1 EQU 0x40006419 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A1 +CYDEV_UWRK_UWRK8_B0_UDB10_A1 EQU 0x4000641a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A1 +CYDEV_UWRK_UWRK8_B0_UDB11_A1 EQU 0x4000641b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A1 +CYDEV_UWRK_UWRK8_B0_UDB12_A1 EQU 0x4000641c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A1 +CYDEV_UWRK_UWRK8_B0_UDB13_A1 EQU 0x4000641d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A1 +CYDEV_UWRK_UWRK8_B0_UDB14_A1 EQU 0x4000641e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A1 +CYDEV_UWRK_UWRK8_B0_UDB15_A1 EQU 0x4000641f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D0 +CYDEV_UWRK_UWRK8_B0_UDB00_D0 EQU 0x40006420 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D0 +CYDEV_UWRK_UWRK8_B0_UDB01_D0 EQU 0x40006421 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D0 +CYDEV_UWRK_UWRK8_B0_UDB02_D0 EQU 0x40006422 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D0 +CYDEV_UWRK_UWRK8_B0_UDB03_D0 EQU 0x40006423 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D0 +CYDEV_UWRK_UWRK8_B0_UDB04_D0 EQU 0x40006424 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D0 +CYDEV_UWRK_UWRK8_B0_UDB05_D0 EQU 0x40006425 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D0 +CYDEV_UWRK_UWRK8_B0_UDB06_D0 EQU 0x40006426 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D0 +CYDEV_UWRK_UWRK8_B0_UDB07_D0 EQU 0x40006427 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D0 +CYDEV_UWRK_UWRK8_B0_UDB08_D0 EQU 0x40006428 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D0 +CYDEV_UWRK_UWRK8_B0_UDB09_D0 EQU 0x40006429 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D0 +CYDEV_UWRK_UWRK8_B0_UDB10_D0 EQU 0x4000642a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D0 +CYDEV_UWRK_UWRK8_B0_UDB11_D0 EQU 0x4000642b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D0 +CYDEV_UWRK_UWRK8_B0_UDB12_D0 EQU 0x4000642c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D0 +CYDEV_UWRK_UWRK8_B0_UDB13_D0 EQU 0x4000642d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D0 +CYDEV_UWRK_UWRK8_B0_UDB14_D0 EQU 0x4000642e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D0 +CYDEV_UWRK_UWRK8_B0_UDB15_D0 EQU 0x4000642f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D1 +CYDEV_UWRK_UWRK8_B0_UDB00_D1 EQU 0x40006430 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D1 +CYDEV_UWRK_UWRK8_B0_UDB01_D1 EQU 0x40006431 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D1 +CYDEV_UWRK_UWRK8_B0_UDB02_D1 EQU 0x40006432 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D1 +CYDEV_UWRK_UWRK8_B0_UDB03_D1 EQU 0x40006433 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D1 +CYDEV_UWRK_UWRK8_B0_UDB04_D1 EQU 0x40006434 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D1 +CYDEV_UWRK_UWRK8_B0_UDB05_D1 EQU 0x40006435 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D1 +CYDEV_UWRK_UWRK8_B0_UDB06_D1 EQU 0x40006436 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D1 +CYDEV_UWRK_UWRK8_B0_UDB07_D1 EQU 0x40006437 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D1 +CYDEV_UWRK_UWRK8_B0_UDB08_D1 EQU 0x40006438 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D1 +CYDEV_UWRK_UWRK8_B0_UDB09_D1 EQU 0x40006439 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D1 +CYDEV_UWRK_UWRK8_B0_UDB10_D1 EQU 0x4000643a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D1 +CYDEV_UWRK_UWRK8_B0_UDB11_D1 EQU 0x4000643b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D1 +CYDEV_UWRK_UWRK8_B0_UDB12_D1 EQU 0x4000643c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D1 +CYDEV_UWRK_UWRK8_B0_UDB13_D1 EQU 0x4000643d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D1 +CYDEV_UWRK_UWRK8_B0_UDB14_D1 EQU 0x4000643e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D1 +CYDEV_UWRK_UWRK8_B0_UDB15_D1 EQU 0x4000643f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F0 +CYDEV_UWRK_UWRK8_B0_UDB00_F0 EQU 0x40006440 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F0 +CYDEV_UWRK_UWRK8_B0_UDB01_F0 EQU 0x40006441 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F0 +CYDEV_UWRK_UWRK8_B0_UDB02_F0 EQU 0x40006442 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F0 +CYDEV_UWRK_UWRK8_B0_UDB03_F0 EQU 0x40006443 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F0 +CYDEV_UWRK_UWRK8_B0_UDB04_F0 EQU 0x40006444 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F0 +CYDEV_UWRK_UWRK8_B0_UDB05_F0 EQU 0x40006445 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F0 +CYDEV_UWRK_UWRK8_B0_UDB06_F0 EQU 0x40006446 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F0 +CYDEV_UWRK_UWRK8_B0_UDB07_F0 EQU 0x40006447 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F0 +CYDEV_UWRK_UWRK8_B0_UDB08_F0 EQU 0x40006448 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F0 +CYDEV_UWRK_UWRK8_B0_UDB09_F0 EQU 0x40006449 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F0 +CYDEV_UWRK_UWRK8_B0_UDB10_F0 EQU 0x4000644a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F0 +CYDEV_UWRK_UWRK8_B0_UDB11_F0 EQU 0x4000644b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F0 +CYDEV_UWRK_UWRK8_B0_UDB12_F0 EQU 0x4000644c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F0 +CYDEV_UWRK_UWRK8_B0_UDB13_F0 EQU 0x4000644d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F0 +CYDEV_UWRK_UWRK8_B0_UDB14_F0 EQU 0x4000644e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F0 +CYDEV_UWRK_UWRK8_B0_UDB15_F0 EQU 0x4000644f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F1 +CYDEV_UWRK_UWRK8_B0_UDB00_F1 EQU 0x40006450 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F1 +CYDEV_UWRK_UWRK8_B0_UDB01_F1 EQU 0x40006451 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F1 +CYDEV_UWRK_UWRK8_B0_UDB02_F1 EQU 0x40006452 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F1 +CYDEV_UWRK_UWRK8_B0_UDB03_F1 EQU 0x40006453 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F1 +CYDEV_UWRK_UWRK8_B0_UDB04_F1 EQU 0x40006454 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F1 +CYDEV_UWRK_UWRK8_B0_UDB05_F1 EQU 0x40006455 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F1 +CYDEV_UWRK_UWRK8_B0_UDB06_F1 EQU 0x40006456 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F1 +CYDEV_UWRK_UWRK8_B0_UDB07_F1 EQU 0x40006457 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F1 +CYDEV_UWRK_UWRK8_B0_UDB08_F1 EQU 0x40006458 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F1 +CYDEV_UWRK_UWRK8_B0_UDB09_F1 EQU 0x40006459 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F1 +CYDEV_UWRK_UWRK8_B0_UDB10_F1 EQU 0x4000645a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F1 +CYDEV_UWRK_UWRK8_B0_UDB11_F1 EQU 0x4000645b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F1 +CYDEV_UWRK_UWRK8_B0_UDB12_F1 EQU 0x4000645c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F1 +CYDEV_UWRK_UWRK8_B0_UDB13_F1 EQU 0x4000645d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F1 +CYDEV_UWRK_UWRK8_B0_UDB14_F1 EQU 0x4000645e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F1 +CYDEV_UWRK_UWRK8_B0_UDB15_F1 EQU 0x4000645f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ST +CYDEV_UWRK_UWRK8_B0_UDB00_ST EQU 0x40006460 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ST +CYDEV_UWRK_UWRK8_B0_UDB01_ST EQU 0x40006461 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ST +CYDEV_UWRK_UWRK8_B0_UDB02_ST EQU 0x40006462 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ST +CYDEV_UWRK_UWRK8_B0_UDB03_ST EQU 0x40006463 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ST +CYDEV_UWRK_UWRK8_B0_UDB04_ST EQU 0x40006464 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ST +CYDEV_UWRK_UWRK8_B0_UDB05_ST EQU 0x40006465 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ST +CYDEV_UWRK_UWRK8_B0_UDB06_ST EQU 0x40006466 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ST +CYDEV_UWRK_UWRK8_B0_UDB07_ST EQU 0x40006467 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ST +CYDEV_UWRK_UWRK8_B0_UDB08_ST EQU 0x40006468 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ST +CYDEV_UWRK_UWRK8_B0_UDB09_ST EQU 0x40006469 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ST +CYDEV_UWRK_UWRK8_B0_UDB10_ST EQU 0x4000646a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ST +CYDEV_UWRK_UWRK8_B0_UDB11_ST EQU 0x4000646b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ST +CYDEV_UWRK_UWRK8_B0_UDB12_ST EQU 0x4000646c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ST +CYDEV_UWRK_UWRK8_B0_UDB13_ST EQU 0x4000646d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ST +CYDEV_UWRK_UWRK8_B0_UDB14_ST EQU 0x4000646e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ST +CYDEV_UWRK_UWRK8_B0_UDB15_ST EQU 0x4000646f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_CTL +CYDEV_UWRK_UWRK8_B0_UDB00_CTL EQU 0x40006470 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_CTL +CYDEV_UWRK_UWRK8_B0_UDB01_CTL EQU 0x40006471 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_CTL +CYDEV_UWRK_UWRK8_B0_UDB02_CTL EQU 0x40006472 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_CTL +CYDEV_UWRK_UWRK8_B0_UDB03_CTL EQU 0x40006473 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_CTL +CYDEV_UWRK_UWRK8_B0_UDB04_CTL EQU 0x40006474 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_CTL +CYDEV_UWRK_UWRK8_B0_UDB05_CTL EQU 0x40006475 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_CTL +CYDEV_UWRK_UWRK8_B0_UDB06_CTL EQU 0x40006476 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_CTL +CYDEV_UWRK_UWRK8_B0_UDB07_CTL EQU 0x40006477 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_CTL +CYDEV_UWRK_UWRK8_B0_UDB08_CTL EQU 0x40006478 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_CTL +CYDEV_UWRK_UWRK8_B0_UDB09_CTL EQU 0x40006479 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_CTL +CYDEV_UWRK_UWRK8_B0_UDB10_CTL EQU 0x4000647a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_CTL +CYDEV_UWRK_UWRK8_B0_UDB11_CTL EQU 0x4000647b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_CTL +CYDEV_UWRK_UWRK8_B0_UDB12_CTL EQU 0x4000647c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_CTL +CYDEV_UWRK_UWRK8_B0_UDB13_CTL EQU 0x4000647d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_CTL +CYDEV_UWRK_UWRK8_B0_UDB14_CTL EQU 0x4000647e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_CTL +CYDEV_UWRK_UWRK8_B0_UDB15_CTL EQU 0x4000647f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MSK +CYDEV_UWRK_UWRK8_B0_UDB00_MSK EQU 0x40006480 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MSK +CYDEV_UWRK_UWRK8_B0_UDB01_MSK EQU 0x40006481 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MSK +CYDEV_UWRK_UWRK8_B0_UDB02_MSK EQU 0x40006482 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MSK +CYDEV_UWRK_UWRK8_B0_UDB03_MSK EQU 0x40006483 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MSK +CYDEV_UWRK_UWRK8_B0_UDB04_MSK EQU 0x40006484 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MSK +CYDEV_UWRK_UWRK8_B0_UDB05_MSK EQU 0x40006485 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MSK +CYDEV_UWRK_UWRK8_B0_UDB06_MSK EQU 0x40006486 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MSK +CYDEV_UWRK_UWRK8_B0_UDB07_MSK EQU 0x40006487 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MSK +CYDEV_UWRK_UWRK8_B0_UDB08_MSK EQU 0x40006488 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MSK +CYDEV_UWRK_UWRK8_B0_UDB09_MSK EQU 0x40006489 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MSK +CYDEV_UWRK_UWRK8_B0_UDB10_MSK EQU 0x4000648a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MSK +CYDEV_UWRK_UWRK8_B0_UDB11_MSK EQU 0x4000648b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MSK +CYDEV_UWRK_UWRK8_B0_UDB12_MSK EQU 0x4000648c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MSK +CYDEV_UWRK_UWRK8_B0_UDB13_MSK EQU 0x4000648d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MSK +CYDEV_UWRK_UWRK8_B0_UDB14_MSK EQU 0x4000648e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MSK +CYDEV_UWRK_UWRK8_B0_UDB15_MSK EQU 0x4000648f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ACTL +CYDEV_UWRK_UWRK8_B0_UDB00_ACTL EQU 0x40006490 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ACTL +CYDEV_UWRK_UWRK8_B0_UDB01_ACTL EQU 0x40006491 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ACTL +CYDEV_UWRK_UWRK8_B0_UDB02_ACTL EQU 0x40006492 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ACTL +CYDEV_UWRK_UWRK8_B0_UDB03_ACTL EQU 0x40006493 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ACTL +CYDEV_UWRK_UWRK8_B0_UDB04_ACTL EQU 0x40006494 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ACTL +CYDEV_UWRK_UWRK8_B0_UDB05_ACTL EQU 0x40006495 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ACTL +CYDEV_UWRK_UWRK8_B0_UDB06_ACTL EQU 0x40006496 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ACTL +CYDEV_UWRK_UWRK8_B0_UDB07_ACTL EQU 0x40006497 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ACTL +CYDEV_UWRK_UWRK8_B0_UDB08_ACTL EQU 0x40006498 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ACTL +CYDEV_UWRK_UWRK8_B0_UDB09_ACTL EQU 0x40006499 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ACTL +CYDEV_UWRK_UWRK8_B0_UDB10_ACTL EQU 0x4000649a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ACTL +CYDEV_UWRK_UWRK8_B0_UDB11_ACTL EQU 0x4000649b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ACTL +CYDEV_UWRK_UWRK8_B0_UDB12_ACTL EQU 0x4000649c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ACTL +CYDEV_UWRK_UWRK8_B0_UDB13_ACTL EQU 0x4000649d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ACTL +CYDEV_UWRK_UWRK8_B0_UDB14_ACTL EQU 0x4000649e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ACTL +CYDEV_UWRK_UWRK8_B0_UDB15_ACTL EQU 0x4000649f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MC +CYDEV_UWRK_UWRK8_B0_UDB00_MC EQU 0x400064a0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MC +CYDEV_UWRK_UWRK8_B0_UDB01_MC EQU 0x400064a1 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MC +CYDEV_UWRK_UWRK8_B0_UDB02_MC EQU 0x400064a2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MC +CYDEV_UWRK_UWRK8_B0_UDB03_MC EQU 0x400064a3 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MC +CYDEV_UWRK_UWRK8_B0_UDB04_MC EQU 0x400064a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MC +CYDEV_UWRK_UWRK8_B0_UDB05_MC EQU 0x400064a5 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MC +CYDEV_UWRK_UWRK8_B0_UDB06_MC EQU 0x400064a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MC +CYDEV_UWRK_UWRK8_B0_UDB07_MC EQU 0x400064a7 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MC +CYDEV_UWRK_UWRK8_B0_UDB08_MC EQU 0x400064a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MC +CYDEV_UWRK_UWRK8_B0_UDB09_MC EQU 0x400064a9 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MC +CYDEV_UWRK_UWRK8_B0_UDB10_MC EQU 0x400064aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MC +CYDEV_UWRK_UWRK8_B0_UDB11_MC EQU 0x400064ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MC +CYDEV_UWRK_UWRK8_B0_UDB12_MC EQU 0x400064ac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MC +CYDEV_UWRK_UWRK8_B0_UDB13_MC EQU 0x400064ad + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MC +CYDEV_UWRK_UWRK8_B0_UDB14_MC EQU 0x400064ae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MC +CYDEV_UWRK_UWRK8_B0_UDB15_MC EQU 0x400064af + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE +CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE +CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A0 +CYDEV_UWRK_UWRK8_B1_UDB04_A0 EQU 0x40006504 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A0 +CYDEV_UWRK_UWRK8_B1_UDB05_A0 EQU 0x40006505 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A0 +CYDEV_UWRK_UWRK8_B1_UDB06_A0 EQU 0x40006506 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A0 +CYDEV_UWRK_UWRK8_B1_UDB07_A0 EQU 0x40006507 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A0 +CYDEV_UWRK_UWRK8_B1_UDB08_A0 EQU 0x40006508 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A0 +CYDEV_UWRK_UWRK8_B1_UDB09_A0 EQU 0x40006509 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A0 +CYDEV_UWRK_UWRK8_B1_UDB10_A0 EQU 0x4000650a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A0 +CYDEV_UWRK_UWRK8_B1_UDB11_A0 EQU 0x4000650b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A1 +CYDEV_UWRK_UWRK8_B1_UDB04_A1 EQU 0x40006514 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A1 +CYDEV_UWRK_UWRK8_B1_UDB05_A1 EQU 0x40006515 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A1 +CYDEV_UWRK_UWRK8_B1_UDB06_A1 EQU 0x40006516 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A1 +CYDEV_UWRK_UWRK8_B1_UDB07_A1 EQU 0x40006517 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A1 +CYDEV_UWRK_UWRK8_B1_UDB08_A1 EQU 0x40006518 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A1 +CYDEV_UWRK_UWRK8_B1_UDB09_A1 EQU 0x40006519 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A1 +CYDEV_UWRK_UWRK8_B1_UDB10_A1 EQU 0x4000651a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A1 +CYDEV_UWRK_UWRK8_B1_UDB11_A1 EQU 0x4000651b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D0 +CYDEV_UWRK_UWRK8_B1_UDB04_D0 EQU 0x40006524 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D0 +CYDEV_UWRK_UWRK8_B1_UDB05_D0 EQU 0x40006525 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D0 +CYDEV_UWRK_UWRK8_B1_UDB06_D0 EQU 0x40006526 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D0 +CYDEV_UWRK_UWRK8_B1_UDB07_D0 EQU 0x40006527 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D0 +CYDEV_UWRK_UWRK8_B1_UDB08_D0 EQU 0x40006528 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D0 +CYDEV_UWRK_UWRK8_B1_UDB09_D0 EQU 0x40006529 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D0 +CYDEV_UWRK_UWRK8_B1_UDB10_D0 EQU 0x4000652a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D0 +CYDEV_UWRK_UWRK8_B1_UDB11_D0 EQU 0x4000652b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D1 +CYDEV_UWRK_UWRK8_B1_UDB04_D1 EQU 0x40006534 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D1 +CYDEV_UWRK_UWRK8_B1_UDB05_D1 EQU 0x40006535 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D1 +CYDEV_UWRK_UWRK8_B1_UDB06_D1 EQU 0x40006536 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D1 +CYDEV_UWRK_UWRK8_B1_UDB07_D1 EQU 0x40006537 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D1 +CYDEV_UWRK_UWRK8_B1_UDB08_D1 EQU 0x40006538 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D1 +CYDEV_UWRK_UWRK8_B1_UDB09_D1 EQU 0x40006539 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D1 +CYDEV_UWRK_UWRK8_B1_UDB10_D1 EQU 0x4000653a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D1 +CYDEV_UWRK_UWRK8_B1_UDB11_D1 EQU 0x4000653b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F0 +CYDEV_UWRK_UWRK8_B1_UDB04_F0 EQU 0x40006544 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F0 +CYDEV_UWRK_UWRK8_B1_UDB05_F0 EQU 0x40006545 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F0 +CYDEV_UWRK_UWRK8_B1_UDB06_F0 EQU 0x40006546 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F0 +CYDEV_UWRK_UWRK8_B1_UDB07_F0 EQU 0x40006547 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F0 +CYDEV_UWRK_UWRK8_B1_UDB08_F0 EQU 0x40006548 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F0 +CYDEV_UWRK_UWRK8_B1_UDB09_F0 EQU 0x40006549 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F0 +CYDEV_UWRK_UWRK8_B1_UDB10_F0 EQU 0x4000654a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F0 +CYDEV_UWRK_UWRK8_B1_UDB11_F0 EQU 0x4000654b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F1 +CYDEV_UWRK_UWRK8_B1_UDB04_F1 EQU 0x40006554 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F1 +CYDEV_UWRK_UWRK8_B1_UDB05_F1 EQU 0x40006555 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F1 +CYDEV_UWRK_UWRK8_B1_UDB06_F1 EQU 0x40006556 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F1 +CYDEV_UWRK_UWRK8_B1_UDB07_F1 EQU 0x40006557 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F1 +CYDEV_UWRK_UWRK8_B1_UDB08_F1 EQU 0x40006558 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F1 +CYDEV_UWRK_UWRK8_B1_UDB09_F1 EQU 0x40006559 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F1 +CYDEV_UWRK_UWRK8_B1_UDB10_F1 EQU 0x4000655a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F1 +CYDEV_UWRK_UWRK8_B1_UDB11_F1 EQU 0x4000655b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ST +CYDEV_UWRK_UWRK8_B1_UDB04_ST EQU 0x40006564 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ST +CYDEV_UWRK_UWRK8_B1_UDB05_ST EQU 0x40006565 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ST +CYDEV_UWRK_UWRK8_B1_UDB06_ST EQU 0x40006566 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ST +CYDEV_UWRK_UWRK8_B1_UDB07_ST EQU 0x40006567 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ST +CYDEV_UWRK_UWRK8_B1_UDB08_ST EQU 0x40006568 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ST +CYDEV_UWRK_UWRK8_B1_UDB09_ST EQU 0x40006569 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ST +CYDEV_UWRK_UWRK8_B1_UDB10_ST EQU 0x4000656a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ST +CYDEV_UWRK_UWRK8_B1_UDB11_ST EQU 0x4000656b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_CTL +CYDEV_UWRK_UWRK8_B1_UDB04_CTL EQU 0x40006574 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_CTL +CYDEV_UWRK_UWRK8_B1_UDB05_CTL EQU 0x40006575 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_CTL +CYDEV_UWRK_UWRK8_B1_UDB06_CTL EQU 0x40006576 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_CTL +CYDEV_UWRK_UWRK8_B1_UDB07_CTL EQU 0x40006577 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_CTL +CYDEV_UWRK_UWRK8_B1_UDB08_CTL EQU 0x40006578 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_CTL +CYDEV_UWRK_UWRK8_B1_UDB09_CTL EQU 0x40006579 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_CTL +CYDEV_UWRK_UWRK8_B1_UDB10_CTL EQU 0x4000657a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_CTL +CYDEV_UWRK_UWRK8_B1_UDB11_CTL EQU 0x4000657b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MSK +CYDEV_UWRK_UWRK8_B1_UDB04_MSK EQU 0x40006584 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MSK +CYDEV_UWRK_UWRK8_B1_UDB05_MSK EQU 0x40006585 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MSK +CYDEV_UWRK_UWRK8_B1_UDB06_MSK EQU 0x40006586 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MSK +CYDEV_UWRK_UWRK8_B1_UDB07_MSK EQU 0x40006587 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MSK +CYDEV_UWRK_UWRK8_B1_UDB08_MSK EQU 0x40006588 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MSK +CYDEV_UWRK_UWRK8_B1_UDB09_MSK EQU 0x40006589 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MSK +CYDEV_UWRK_UWRK8_B1_UDB10_MSK EQU 0x4000658a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MSK +CYDEV_UWRK_UWRK8_B1_UDB11_MSK EQU 0x4000658b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ACTL +CYDEV_UWRK_UWRK8_B1_UDB04_ACTL EQU 0x40006594 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ACTL +CYDEV_UWRK_UWRK8_B1_UDB05_ACTL EQU 0x40006595 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ACTL +CYDEV_UWRK_UWRK8_B1_UDB06_ACTL EQU 0x40006596 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ACTL +CYDEV_UWRK_UWRK8_B1_UDB07_ACTL EQU 0x40006597 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ACTL +CYDEV_UWRK_UWRK8_B1_UDB08_ACTL EQU 0x40006598 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ACTL +CYDEV_UWRK_UWRK8_B1_UDB09_ACTL EQU 0x40006599 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ACTL +CYDEV_UWRK_UWRK8_B1_UDB10_ACTL EQU 0x4000659a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ACTL +CYDEV_UWRK_UWRK8_B1_UDB11_ACTL EQU 0x4000659b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MC +CYDEV_UWRK_UWRK8_B1_UDB04_MC EQU 0x400065a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MC +CYDEV_UWRK_UWRK8_B1_UDB05_MC EQU 0x400065a5 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MC +CYDEV_UWRK_UWRK8_B1_UDB06_MC EQU 0x400065a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MC +CYDEV_UWRK_UWRK8_B1_UDB07_MC EQU 0x400065a7 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MC +CYDEV_UWRK_UWRK8_B1_UDB08_MC EQU 0x400065a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MC +CYDEV_UWRK_UWRK8_B1_UDB09_MC EQU 0x400065a9 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MC +CYDEV_UWRK_UWRK8_B1_UDB10_MC EQU 0x400065aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MC +CYDEV_UWRK_UWRK8_B1_UDB11_MC EQU 0x400065ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE +CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE +CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE +CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE +CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE +CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE +CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 EQU 0x4000681e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 EQU 0x4000685e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 EQU 0x4000689e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL EQU 0x400068de + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL EQU 0x4000691e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 EQU 0x4000695e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE +CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE +CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE +CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE +CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE +CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE +CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 EQU 0x40006820 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 EQU 0x40006822 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 EQU 0x40006824 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 EQU 0x40006826 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 EQU 0x40006828 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 EQU 0x4000682a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 EQU 0x4000682c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 EQU 0x4000682e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 EQU 0x40006830 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 EQU 0x40006832 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 EQU 0x40006834 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 EQU 0x40006836 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 EQU 0x40006838 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 EQU 0x4000683a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 EQU 0x4000683c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 EQU 0x40006860 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 EQU 0x40006862 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 EQU 0x40006864 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 EQU 0x40006866 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 EQU 0x40006868 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 EQU 0x4000686a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 EQU 0x4000686c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 EQU 0x4000686e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 EQU 0x40006870 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 EQU 0x40006872 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 EQU 0x40006874 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 EQU 0x40006876 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 EQU 0x40006878 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 EQU 0x4000687a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 EQU 0x4000687c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 EQU 0x400068a0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 EQU 0x400068a2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 EQU 0x400068a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 EQU 0x400068a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 EQU 0x400068a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 EQU 0x400068aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 EQU 0x400068ac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 EQU 0x400068ae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 EQU 0x400068b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 EQU 0x400068b2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 EQU 0x400068b4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 EQU 0x400068b6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 EQU 0x400068b8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 EQU 0x400068ba + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 EQU 0x400068bc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL EQU 0x400068e0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL EQU 0x400068e2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL EQU 0x400068e4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL EQU 0x400068e6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL EQU 0x400068e8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL EQU 0x400068ea + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL EQU 0x400068ec + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL EQU 0x400068ee + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL EQU 0x400068f0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL EQU 0x400068f2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL EQU 0x400068f4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL EQU 0x400068f6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL EQU 0x400068f8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL EQU 0x400068fa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL EQU 0x400068fc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL EQU 0x40006920 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL EQU 0x40006922 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL EQU 0x40006924 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL EQU 0x40006926 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL EQU 0x40006928 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL EQU 0x4000692a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL EQU 0x4000692c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL EQU 0x4000692e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL EQU 0x40006930 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL EQU 0x40006932 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL EQU 0x40006934 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL EQU 0x40006936 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL EQU 0x40006938 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL EQU 0x4000693a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL EQU 0x4000693c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE +CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE +CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 EQU 0x40006a28 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 EQU 0x40006a2a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 EQU 0x40006a2c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 EQU 0x40006a2e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 EQU 0x40006a30 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 EQU 0x40006a32 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 EQU 0x40006a34 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 EQU 0x40006a36 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 EQU 0x40006a68 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 EQU 0x40006a6a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 EQU 0x40006a6c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 EQU 0x40006a6e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 EQU 0x40006a70 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 EQU 0x40006a72 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 EQU 0x40006a74 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 EQU 0x40006a76 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 EQU 0x40006aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 EQU 0x40006aaa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 EQU 0x40006aac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 EQU 0x40006aae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 EQU 0x40006ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 EQU 0x40006ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 EQU 0x40006ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 EQU 0x40006ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL EQU 0x40006ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL EQU 0x40006aea + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL EQU 0x40006aec + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL EQU 0x40006aee + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL EQU 0x40006af0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL EQU 0x40006af2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL EQU 0x40006af4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL EQU 0x40006af6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL EQU 0x40006b28 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL EQU 0x40006b2a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL EQU 0x40006b2c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL EQU 0x40006b2e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL EQU 0x40006b30 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL EQU 0x40006b32 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL EQU 0x40006b34 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL EQU 0x40006b36 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_BASE +CYDEV_PHUB_BASE EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_SIZE +CYDEV_PHUB_SIZE EQU 0x00000c00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFG +CYDEV_PHUB_CFG EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_ERR +CYDEV_PHUB_ERR EQU 0x40007004 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_ERR_ADR +CYDEV_PHUB_ERR_ADR EQU 0x40007008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE +CYDEV_PHUB_CH0_BASE EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE +CYDEV_PHUB_CH0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_CFG +CYDEV_PHUB_CH0_BASIC_CFG EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_ACTION +CYDEV_PHUB_CH0_ACTION EQU 0x40007014 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_STATUS +CYDEV_PHUB_CH0_BASIC_STATUS EQU 0x40007018 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE +CYDEV_PHUB_CH1_BASE EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE +CYDEV_PHUB_CH1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_CFG +CYDEV_PHUB_CH1_BASIC_CFG EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_ACTION +CYDEV_PHUB_CH1_ACTION EQU 0x40007024 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_STATUS +CYDEV_PHUB_CH1_BASIC_STATUS EQU 0x40007028 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE +CYDEV_PHUB_CH2_BASE EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE +CYDEV_PHUB_CH2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_CFG +CYDEV_PHUB_CH2_BASIC_CFG EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_ACTION +CYDEV_PHUB_CH2_ACTION EQU 0x40007034 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_STATUS +CYDEV_PHUB_CH2_BASIC_STATUS EQU 0x40007038 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE +CYDEV_PHUB_CH3_BASE EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE +CYDEV_PHUB_CH3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_CFG +CYDEV_PHUB_CH3_BASIC_CFG EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_ACTION +CYDEV_PHUB_CH3_ACTION EQU 0x40007044 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_STATUS +CYDEV_PHUB_CH3_BASIC_STATUS EQU 0x40007048 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE +CYDEV_PHUB_CH4_BASE EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE +CYDEV_PHUB_CH4_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_CFG +CYDEV_PHUB_CH4_BASIC_CFG EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_ACTION +CYDEV_PHUB_CH4_ACTION EQU 0x40007054 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_STATUS +CYDEV_PHUB_CH4_BASIC_STATUS EQU 0x40007058 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE +CYDEV_PHUB_CH5_BASE EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE +CYDEV_PHUB_CH5_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_CFG +CYDEV_PHUB_CH5_BASIC_CFG EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_ACTION +CYDEV_PHUB_CH5_ACTION EQU 0x40007064 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_STATUS +CYDEV_PHUB_CH5_BASIC_STATUS EQU 0x40007068 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE +CYDEV_PHUB_CH6_BASE EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE +CYDEV_PHUB_CH6_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_CFG +CYDEV_PHUB_CH6_BASIC_CFG EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_ACTION +CYDEV_PHUB_CH6_ACTION EQU 0x40007074 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_STATUS +CYDEV_PHUB_CH6_BASIC_STATUS EQU 0x40007078 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE +CYDEV_PHUB_CH7_BASE EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE +CYDEV_PHUB_CH7_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_CFG +CYDEV_PHUB_CH7_BASIC_CFG EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_ACTION +CYDEV_PHUB_CH7_ACTION EQU 0x40007084 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_STATUS +CYDEV_PHUB_CH7_BASIC_STATUS EQU 0x40007088 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE +CYDEV_PHUB_CH8_BASE EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE +CYDEV_PHUB_CH8_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_CFG +CYDEV_PHUB_CH8_BASIC_CFG EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_ACTION +CYDEV_PHUB_CH8_ACTION EQU 0x40007094 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_STATUS +CYDEV_PHUB_CH8_BASIC_STATUS EQU 0x40007098 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE +CYDEV_PHUB_CH9_BASE EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE +CYDEV_PHUB_CH9_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_CFG +CYDEV_PHUB_CH9_BASIC_CFG EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_ACTION +CYDEV_PHUB_CH9_ACTION EQU 0x400070a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_STATUS +CYDEV_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE +CYDEV_PHUB_CH10_BASE EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE +CYDEV_PHUB_CH10_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_CFG +CYDEV_PHUB_CH10_BASIC_CFG EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_ACTION +CYDEV_PHUB_CH10_ACTION EQU 0x400070b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_STATUS +CYDEV_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE +CYDEV_PHUB_CH11_BASE EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE +CYDEV_PHUB_CH11_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_CFG +CYDEV_PHUB_CH11_BASIC_CFG EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_ACTION +CYDEV_PHUB_CH11_ACTION EQU 0x400070c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_STATUS +CYDEV_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE +CYDEV_PHUB_CH12_BASE EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE +CYDEV_PHUB_CH12_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_CFG +CYDEV_PHUB_CH12_BASIC_CFG EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_ACTION +CYDEV_PHUB_CH12_ACTION EQU 0x400070d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_STATUS +CYDEV_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE +CYDEV_PHUB_CH13_BASE EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE +CYDEV_PHUB_CH13_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_CFG +CYDEV_PHUB_CH13_BASIC_CFG EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_ACTION +CYDEV_PHUB_CH13_ACTION EQU 0x400070e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_STATUS +CYDEV_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE +CYDEV_PHUB_CH14_BASE EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE +CYDEV_PHUB_CH14_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_CFG +CYDEV_PHUB_CH14_BASIC_CFG EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_ACTION +CYDEV_PHUB_CH14_ACTION EQU 0x400070f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_STATUS +CYDEV_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE +CYDEV_PHUB_CH15_BASE EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE +CYDEV_PHUB_CH15_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_CFG +CYDEV_PHUB_CH15_BASIC_CFG EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_ACTION +CYDEV_PHUB_CH15_ACTION EQU 0x40007104 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_STATUS +CYDEV_PHUB_CH15_BASIC_STATUS EQU 0x40007108 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE +CYDEV_PHUB_CH16_BASE EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE +CYDEV_PHUB_CH16_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_CFG +CYDEV_PHUB_CH16_BASIC_CFG EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_ACTION +CYDEV_PHUB_CH16_ACTION EQU 0x40007114 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_STATUS +CYDEV_PHUB_CH16_BASIC_STATUS EQU 0x40007118 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE +CYDEV_PHUB_CH17_BASE EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE +CYDEV_PHUB_CH17_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_CFG +CYDEV_PHUB_CH17_BASIC_CFG EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_ACTION +CYDEV_PHUB_CH17_ACTION EQU 0x40007124 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_STATUS +CYDEV_PHUB_CH17_BASIC_STATUS EQU 0x40007128 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE +CYDEV_PHUB_CH18_BASE EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE +CYDEV_PHUB_CH18_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_CFG +CYDEV_PHUB_CH18_BASIC_CFG EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_ACTION +CYDEV_PHUB_CH18_ACTION EQU 0x40007134 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_STATUS +CYDEV_PHUB_CH18_BASIC_STATUS EQU 0x40007138 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE +CYDEV_PHUB_CH19_BASE EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE +CYDEV_PHUB_CH19_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_CFG +CYDEV_PHUB_CH19_BASIC_CFG EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_ACTION +CYDEV_PHUB_CH19_ACTION EQU 0x40007144 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_STATUS +CYDEV_PHUB_CH19_BASIC_STATUS EQU 0x40007148 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE +CYDEV_PHUB_CH20_BASE EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE +CYDEV_PHUB_CH20_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_CFG +CYDEV_PHUB_CH20_BASIC_CFG EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_ACTION +CYDEV_PHUB_CH20_ACTION EQU 0x40007154 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_STATUS +CYDEV_PHUB_CH20_BASIC_STATUS EQU 0x40007158 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE +CYDEV_PHUB_CH21_BASE EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE +CYDEV_PHUB_CH21_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_CFG +CYDEV_PHUB_CH21_BASIC_CFG EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_ACTION +CYDEV_PHUB_CH21_ACTION EQU 0x40007164 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_STATUS +CYDEV_PHUB_CH21_BASIC_STATUS EQU 0x40007168 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE +CYDEV_PHUB_CH22_BASE EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE +CYDEV_PHUB_CH22_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_CFG +CYDEV_PHUB_CH22_BASIC_CFG EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_ACTION +CYDEV_PHUB_CH22_ACTION EQU 0x40007174 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_STATUS +CYDEV_PHUB_CH22_BASIC_STATUS EQU 0x40007178 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE +CYDEV_PHUB_CH23_BASE EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE +CYDEV_PHUB_CH23_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_CFG +CYDEV_PHUB_CH23_BASIC_CFG EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_ACTION +CYDEV_PHUB_CH23_ACTION EQU 0x40007184 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_STATUS +CYDEV_PHUB_CH23_BASIC_STATUS EQU 0x40007188 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE +CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE +CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG0 +CYDEV_PHUB_CFGMEM0_CFG0 EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG1 +CYDEV_PHUB_CFGMEM0_CFG1 EQU 0x40007604 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE +CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE +CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG0 +CYDEV_PHUB_CFGMEM1_CFG0 EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG1 +CYDEV_PHUB_CFGMEM1_CFG1 EQU 0x4000760c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE +CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE +CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG0 +CYDEV_PHUB_CFGMEM2_CFG0 EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG1 +CYDEV_PHUB_CFGMEM2_CFG1 EQU 0x40007614 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE +CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE +CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG0 +CYDEV_PHUB_CFGMEM3_CFG0 EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG1 +CYDEV_PHUB_CFGMEM3_CFG1 EQU 0x4000761c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE +CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE +CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG0 +CYDEV_PHUB_CFGMEM4_CFG0 EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG1 +CYDEV_PHUB_CFGMEM4_CFG1 EQU 0x40007624 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE +CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE +CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG0 +CYDEV_PHUB_CFGMEM5_CFG0 EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG1 +CYDEV_PHUB_CFGMEM5_CFG1 EQU 0x4000762c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE +CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE +CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG0 +CYDEV_PHUB_CFGMEM6_CFG0 EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG1 +CYDEV_PHUB_CFGMEM6_CFG1 EQU 0x40007634 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE +CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE +CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG0 +CYDEV_PHUB_CFGMEM7_CFG0 EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG1 +CYDEV_PHUB_CFGMEM7_CFG1 EQU 0x4000763c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE +CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE +CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG0 +CYDEV_PHUB_CFGMEM8_CFG0 EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG1 +CYDEV_PHUB_CFGMEM8_CFG1 EQU 0x40007644 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE +CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE +CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG0 +CYDEV_PHUB_CFGMEM9_CFG0 EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG1 +CYDEV_PHUB_CFGMEM9_CFG1 EQU 0x4000764c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE +CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE +CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG0 +CYDEV_PHUB_CFGMEM10_CFG0 EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG1 +CYDEV_PHUB_CFGMEM10_CFG1 EQU 0x40007654 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE +CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE +CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG0 +CYDEV_PHUB_CFGMEM11_CFG0 EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG1 +CYDEV_PHUB_CFGMEM11_CFG1 EQU 0x4000765c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE +CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE +CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG0 +CYDEV_PHUB_CFGMEM12_CFG0 EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG1 +CYDEV_PHUB_CFGMEM12_CFG1 EQU 0x40007664 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE +CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE +CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG0 +CYDEV_PHUB_CFGMEM13_CFG0 EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG1 +CYDEV_PHUB_CFGMEM13_CFG1 EQU 0x4000766c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE +CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE +CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG0 +CYDEV_PHUB_CFGMEM14_CFG0 EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG1 +CYDEV_PHUB_CFGMEM14_CFG1 EQU 0x40007674 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE +CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE +CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG0 +CYDEV_PHUB_CFGMEM15_CFG0 EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG1 +CYDEV_PHUB_CFGMEM15_CFG1 EQU 0x4000767c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE +CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE +CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG0 +CYDEV_PHUB_CFGMEM16_CFG0 EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG1 +CYDEV_PHUB_CFGMEM16_CFG1 EQU 0x40007684 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE +CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE +CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG0 +CYDEV_PHUB_CFGMEM17_CFG0 EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG1 +CYDEV_PHUB_CFGMEM17_CFG1 EQU 0x4000768c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE +CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE +CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG0 +CYDEV_PHUB_CFGMEM18_CFG0 EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG1 +CYDEV_PHUB_CFGMEM18_CFG1 EQU 0x40007694 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE +CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE +CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG0 +CYDEV_PHUB_CFGMEM19_CFG0 EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG1 +CYDEV_PHUB_CFGMEM19_CFG1 EQU 0x4000769c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE +CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE +CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG0 +CYDEV_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG1 +CYDEV_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE +CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE +CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG0 +CYDEV_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG1 +CYDEV_PHUB_CFGMEM21_CFG1 EQU 0x400076ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE +CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE +CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG0 +CYDEV_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG1 +CYDEV_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE +CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE +CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG0 +CYDEV_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG1 +CYDEV_PHUB_CFGMEM23_CFG1 EQU 0x400076bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE +CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE +CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD0 +CYDEV_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD1 +CYDEV_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE +CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE +CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD0 +CYDEV_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD1 +CYDEV_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE +CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE +CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD0 +CYDEV_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD1 +CYDEV_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE +CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE +CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD0 +CYDEV_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD1 +CYDEV_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE +CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE +CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD0 +CYDEV_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD1 +CYDEV_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE +CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE +CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD0 +CYDEV_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD1 +CYDEV_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE +CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE +CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD0 +CYDEV_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD1 +CYDEV_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE +CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE +CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD0 +CYDEV_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD1 +CYDEV_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE +CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE +CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD0 +CYDEV_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD1 +CYDEV_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE +CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE +CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD0 +CYDEV_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD1 +CYDEV_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE +CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE +CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD0 +CYDEV_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD1 +CYDEV_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE +CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE +CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD0 +CYDEV_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD1 +CYDEV_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE +CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE +CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD0 +CYDEV_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD1 +CYDEV_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE +CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE +CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD0 +CYDEV_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD1 +CYDEV_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE +CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE +CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD0 +CYDEV_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD1 +CYDEV_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE +CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE +CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD0 +CYDEV_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD1 +CYDEV_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE +CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE +CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD0 +CYDEV_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD1 +CYDEV_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE +CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE +CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD0 +CYDEV_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD1 +CYDEV_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE +CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE +CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD0 +CYDEV_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD1 +CYDEV_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE +CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE +CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD0 +CYDEV_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD1 +CYDEV_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE +CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE +CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD0 +CYDEV_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD1 +CYDEV_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE +CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE +CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD0 +CYDEV_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD1 +CYDEV_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE +CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE +CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD0 +CYDEV_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD1 +CYDEV_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE +CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE +CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD0 +CYDEV_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD1 +CYDEV_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE +CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE +CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD0 +CYDEV_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD1 +CYDEV_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE +CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE +CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD0 +CYDEV_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD1 +CYDEV_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE +CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE +CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD0 +CYDEV_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD1 +CYDEV_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE +CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE +CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD0 +CYDEV_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD1 +CYDEV_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE +CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE +CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD0 +CYDEV_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD1 +CYDEV_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE +CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE +CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD0 +CYDEV_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD1 +CYDEV_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE +CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE +CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD0 +CYDEV_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD1 +CYDEV_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE +CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE +CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD0 +CYDEV_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD1 +CYDEV_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE +CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE +CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD0 +CYDEV_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD1 +CYDEV_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE +CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE +CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD0 +CYDEV_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD1 +CYDEV_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE +CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE +CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD0 +CYDEV_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD1 +CYDEV_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE +CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE +CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD0 +CYDEV_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD1 +CYDEV_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE +CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE +CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD0 +CYDEV_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD1 +CYDEV_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE +CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE +CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD0 +CYDEV_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD1 +CYDEV_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE +CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE +CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD0 +CYDEV_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD1 +CYDEV_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE +CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE +CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD0 +CYDEV_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD1 +CYDEV_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE +CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE +CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD0 +CYDEV_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD1 +CYDEV_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE +CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE +CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD0 +CYDEV_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD1 +CYDEV_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE +CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE +CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD0 +CYDEV_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD1 +CYDEV_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE +CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE +CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD0 +CYDEV_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD1 +CYDEV_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE +CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE +CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD0 +CYDEV_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD1 +CYDEV_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE +CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE +CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD0 +CYDEV_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD1 +CYDEV_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE +CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE +CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD0 +CYDEV_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD1 +CYDEV_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE +CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE +CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD0 +CYDEV_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD1 +CYDEV_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE +CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE +CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD0 +CYDEV_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD1 +CYDEV_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE +CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE +CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD0 +CYDEV_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD1 +CYDEV_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE +CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE +CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD0 +CYDEV_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD1 +CYDEV_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE +CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE +CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD0 +CYDEV_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD1 +CYDEV_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE +CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE +CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD0 +CYDEV_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD1 +CYDEV_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE +CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE +CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD0 +CYDEV_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD1 +CYDEV_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE +CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE +CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD0 +CYDEV_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD1 +CYDEV_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE +CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE +CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD0 +CYDEV_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD1 +CYDEV_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE +CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE +CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD0 +CYDEV_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD1 +CYDEV_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE +CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE +CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD0 +CYDEV_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD1 +CYDEV_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE +CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE +CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD0 +CYDEV_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD1 +CYDEV_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE +CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE +CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD0 +CYDEV_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD1 +CYDEV_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE +CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE +CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD0 +CYDEV_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD1 +CYDEV_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE +CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE +CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD0 +CYDEV_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD1 +CYDEV_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE +CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE +CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD0 +CYDEV_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD1 +CYDEV_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE +CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE +CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD0 +CYDEV_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD1 +CYDEV_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE +CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE +CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD0 +CYDEV_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD1 +CYDEV_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE +CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE +CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD0 +CYDEV_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD1 +CYDEV_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE +CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE +CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD0 +CYDEV_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD1 +CYDEV_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE +CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE +CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD0 +CYDEV_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD1 +CYDEV_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE +CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE +CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD0 +CYDEV_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD1 +CYDEV_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE +CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE +CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD0 +CYDEV_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD1 +CYDEV_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE +CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE +CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD0 +CYDEV_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD1 +CYDEV_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE +CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE +CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD0 +CYDEV_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD1 +CYDEV_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE +CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE +CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD0 +CYDEV_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD1 +CYDEV_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE +CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE +CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD0 +CYDEV_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD1 +CYDEV_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE +CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE +CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD0 +CYDEV_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD1 +CYDEV_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE +CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE +CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD0 +CYDEV_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD1 +CYDEV_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE +CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE +CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD0 +CYDEV_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD1 +CYDEV_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE +CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE +CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD0 +CYDEV_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD1 +CYDEV_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE +CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE +CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD0 +CYDEV_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD1 +CYDEV_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE +CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE +CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD0 +CYDEV_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD1 +CYDEV_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE +CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE +CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD0 +CYDEV_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD1 +CYDEV_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE +CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE +CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD0 +CYDEV_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD1 +CYDEV_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE +CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE +CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD0 +CYDEV_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD1 +CYDEV_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE +CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE +CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD0 +CYDEV_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD1 +CYDEV_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE +CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE +CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD0 +CYDEV_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD1 +CYDEV_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE +CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE +CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD0 +CYDEV_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD1 +CYDEV_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE +CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE +CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD0 +CYDEV_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD1 +CYDEV_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE +CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE +CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD0 +CYDEV_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD1 +CYDEV_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE +CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE +CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD0 +CYDEV_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD1 +CYDEV_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE +CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE +CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD0 +CYDEV_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD1 +CYDEV_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE +CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE +CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD0 +CYDEV_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD1 +CYDEV_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE +CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE +CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD0 +CYDEV_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD1 +CYDEV_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE +CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE +CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD0 +CYDEV_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD1 +CYDEV_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE +CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE +CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD0 +CYDEV_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD1 +CYDEV_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE +CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE +CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD0 +CYDEV_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD1 +CYDEV_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE +CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE +CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD0 +CYDEV_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD1 +CYDEV_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE +CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE +CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD0 +CYDEV_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD1 +CYDEV_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE +CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE +CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD0 +CYDEV_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD1 +CYDEV_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE +CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE +CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD0 +CYDEV_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD1 +CYDEV_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE +CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE +CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD0 +CYDEV_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD1 +CYDEV_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE +CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE +CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD0 +CYDEV_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD1 +CYDEV_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE +CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE +CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD0 +CYDEV_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD1 +CYDEV_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE +CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE +CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD0 +CYDEV_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD1 +CYDEV_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE +CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE +CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD0 +CYDEV_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD1 +CYDEV_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE +CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE +CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD0 +CYDEV_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD1 +CYDEV_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE +CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE +CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD0 +CYDEV_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD1 +CYDEV_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE +CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE +CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD0 +CYDEV_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD1 +CYDEV_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE +CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE +CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD0 +CYDEV_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD1 +CYDEV_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE +CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE +CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD0 +CYDEV_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD1 +CYDEV_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE +CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE +CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD0 +CYDEV_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD1 +CYDEV_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE +CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE +CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD0 +CYDEV_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD1 +CYDEV_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE +CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE +CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD0 +CYDEV_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD1 +CYDEV_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE +CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE +CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD0 +CYDEV_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD1 +CYDEV_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE +CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE +CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD0 +CYDEV_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD1 +CYDEV_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE +CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE +CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD0 +CYDEV_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD1 +CYDEV_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE +CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE +CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD0 +CYDEV_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD1 +CYDEV_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE +CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE +CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD0 +CYDEV_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD1 +CYDEV_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE +CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE +CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD0 +CYDEV_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD1 +CYDEV_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE +CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE +CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD0 +CYDEV_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD1 +CYDEV_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE +CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE +CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD0 +CYDEV_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD1 +CYDEV_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE +CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE +CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD0 +CYDEV_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD1 +CYDEV_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE +CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE +CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD0 +CYDEV_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD1 +CYDEV_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE +CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE +CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD0 +CYDEV_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD1 +CYDEV_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE +CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE +CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD0 +CYDEV_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD1 +CYDEV_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE +CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE +CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD0 +CYDEV_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD1 +CYDEV_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE +CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE +CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD0 +CYDEV_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD1 +CYDEV_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE +CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE +CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD0 +CYDEV_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD1 +CYDEV_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE +CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE +CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD0 +CYDEV_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD1 +CYDEV_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc + ENDIF + IF :LNOT::DEF:CYDEV_EE_BASE +CYDEV_EE_BASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_SIZE +CYDEV_EE_SIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_EE_DATA_MBASE +CYDEV_EE_DATA_MBASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_DATA_MSIZE +CYDEV_EE_DATA_MSIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_BASE +CYDEV_CAN0_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_SIZE +CYDEV_CAN0_SIZE EQU 0x000002a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE +CYDEV_CAN0_CSR_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE +CYDEV_CAN0_CSR_SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_SR +CYDEV_CAN0_CSR_INT_SR EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_EN +CYDEV_CAN0_CSR_INT_EN EQU 0x4000a004 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BUF_SR +CYDEV_CAN0_CSR_BUF_SR EQU 0x4000a008 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_ERR_SR +CYDEV_CAN0_CSR_ERR_SR EQU 0x4000a00c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_CMD +CYDEV_CAN0_CSR_CMD EQU 0x4000a010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_CFG +CYDEV_CAN0_CSR_CFG EQU 0x4000a014 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE +CYDEV_CAN0_TX0_BASE EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE +CYDEV_CAN0_TX0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_CMD +CYDEV_CAN0_TX0_CMD EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_ID +CYDEV_CAN0_TX0_ID EQU 0x4000a024 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_DH +CYDEV_CAN0_TX0_DH EQU 0x4000a028 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_DL +CYDEV_CAN0_TX0_DL EQU 0x4000a02c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE +CYDEV_CAN0_TX1_BASE EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE +CYDEV_CAN0_TX1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_CMD +CYDEV_CAN0_TX1_CMD EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_ID +CYDEV_CAN0_TX1_ID EQU 0x4000a034 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_DH +CYDEV_CAN0_TX1_DH EQU 0x4000a038 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_DL +CYDEV_CAN0_TX1_DL EQU 0x4000a03c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE +CYDEV_CAN0_TX2_BASE EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE +CYDEV_CAN0_TX2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_CMD +CYDEV_CAN0_TX2_CMD EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_ID +CYDEV_CAN0_TX2_ID EQU 0x4000a044 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_DH +CYDEV_CAN0_TX2_DH EQU 0x4000a048 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_DL +CYDEV_CAN0_TX2_DL EQU 0x4000a04c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE +CYDEV_CAN0_TX3_BASE EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE +CYDEV_CAN0_TX3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_CMD +CYDEV_CAN0_TX3_CMD EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_ID +CYDEV_CAN0_TX3_ID EQU 0x4000a054 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_DH +CYDEV_CAN0_TX3_DH EQU 0x4000a058 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_DL +CYDEV_CAN0_TX3_DL EQU 0x4000a05c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE +CYDEV_CAN0_TX4_BASE EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE +CYDEV_CAN0_TX4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_CMD +CYDEV_CAN0_TX4_CMD EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_ID +CYDEV_CAN0_TX4_ID EQU 0x4000a064 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_DH +CYDEV_CAN0_TX4_DH EQU 0x4000a068 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_DL +CYDEV_CAN0_TX4_DL EQU 0x4000a06c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE +CYDEV_CAN0_TX5_BASE EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE +CYDEV_CAN0_TX5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_CMD +CYDEV_CAN0_TX5_CMD EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_ID +CYDEV_CAN0_TX5_ID EQU 0x4000a074 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_DH +CYDEV_CAN0_TX5_DH EQU 0x4000a078 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_DL +CYDEV_CAN0_TX5_DL EQU 0x4000a07c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE +CYDEV_CAN0_TX6_BASE EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE +CYDEV_CAN0_TX6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_CMD +CYDEV_CAN0_TX6_CMD EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_ID +CYDEV_CAN0_TX6_ID EQU 0x4000a084 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_DH +CYDEV_CAN0_TX6_DH EQU 0x4000a088 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_DL +CYDEV_CAN0_TX6_DL EQU 0x4000a08c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE +CYDEV_CAN0_TX7_BASE EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE +CYDEV_CAN0_TX7_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_CMD +CYDEV_CAN0_TX7_CMD EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_ID +CYDEV_CAN0_TX7_ID EQU 0x4000a094 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_DH +CYDEV_CAN0_TX7_DH EQU 0x4000a098 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_DL +CYDEV_CAN0_TX7_DL EQU 0x4000a09c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE +CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE +CYDEV_CAN0_RX0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_CMD +CYDEV_CAN0_RX0_CMD EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ID +CYDEV_CAN0_RX0_ID EQU 0x4000a0a4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_DH +CYDEV_CAN0_RX0_DH EQU 0x4000a0a8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_DL +CYDEV_CAN0_RX0_DL EQU 0x4000a0ac + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_AMR +CYDEV_CAN0_RX0_AMR EQU 0x4000a0b0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ACR +CYDEV_CAN0_RX0_ACR EQU 0x4000a0b4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_AMRD +CYDEV_CAN0_RX0_AMRD EQU 0x4000a0b8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ACRD +CYDEV_CAN0_RX0_ACRD EQU 0x4000a0bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE +CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE +CYDEV_CAN0_RX1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_CMD +CYDEV_CAN0_RX1_CMD EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ID +CYDEV_CAN0_RX1_ID EQU 0x4000a0c4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_DH +CYDEV_CAN0_RX1_DH EQU 0x4000a0c8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_DL +CYDEV_CAN0_RX1_DL EQU 0x4000a0cc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_AMR +CYDEV_CAN0_RX1_AMR EQU 0x4000a0d0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ACR +CYDEV_CAN0_RX1_ACR EQU 0x4000a0d4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_AMRD +CYDEV_CAN0_RX1_AMRD EQU 0x4000a0d8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ACRD +CYDEV_CAN0_RX1_ACRD EQU 0x4000a0dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE +CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE +CYDEV_CAN0_RX2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_CMD +CYDEV_CAN0_RX2_CMD EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ID +CYDEV_CAN0_RX2_ID EQU 0x4000a0e4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_DH +CYDEV_CAN0_RX2_DH EQU 0x4000a0e8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_DL +CYDEV_CAN0_RX2_DL EQU 0x4000a0ec + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_AMR +CYDEV_CAN0_RX2_AMR EQU 0x4000a0f0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ACR +CYDEV_CAN0_RX2_ACR EQU 0x4000a0f4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_AMRD +CYDEV_CAN0_RX2_AMRD EQU 0x4000a0f8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ACRD +CYDEV_CAN0_RX2_ACRD EQU 0x4000a0fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE +CYDEV_CAN0_RX3_BASE EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE +CYDEV_CAN0_RX3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_CMD +CYDEV_CAN0_RX3_CMD EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ID +CYDEV_CAN0_RX3_ID EQU 0x4000a104 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_DH +CYDEV_CAN0_RX3_DH EQU 0x4000a108 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_DL +CYDEV_CAN0_RX3_DL EQU 0x4000a10c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_AMR +CYDEV_CAN0_RX3_AMR EQU 0x4000a110 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ACR +CYDEV_CAN0_RX3_ACR EQU 0x4000a114 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_AMRD +CYDEV_CAN0_RX3_AMRD EQU 0x4000a118 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ACRD +CYDEV_CAN0_RX3_ACRD EQU 0x4000a11c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE +CYDEV_CAN0_RX4_BASE EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE +CYDEV_CAN0_RX4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_CMD +CYDEV_CAN0_RX4_CMD EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ID +CYDEV_CAN0_RX4_ID EQU 0x4000a124 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_DH +CYDEV_CAN0_RX4_DH EQU 0x4000a128 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_DL +CYDEV_CAN0_RX4_DL EQU 0x4000a12c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_AMR +CYDEV_CAN0_RX4_AMR EQU 0x4000a130 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ACR +CYDEV_CAN0_RX4_ACR EQU 0x4000a134 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_AMRD +CYDEV_CAN0_RX4_AMRD EQU 0x4000a138 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ACRD +CYDEV_CAN0_RX4_ACRD EQU 0x4000a13c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE +CYDEV_CAN0_RX5_BASE EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE +CYDEV_CAN0_RX5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_CMD +CYDEV_CAN0_RX5_CMD EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ID +CYDEV_CAN0_RX5_ID EQU 0x4000a144 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_DH +CYDEV_CAN0_RX5_DH EQU 0x4000a148 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_DL +CYDEV_CAN0_RX5_DL EQU 0x4000a14c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_AMR +CYDEV_CAN0_RX5_AMR EQU 0x4000a150 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ACR +CYDEV_CAN0_RX5_ACR EQU 0x4000a154 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_AMRD +CYDEV_CAN0_RX5_AMRD EQU 0x4000a158 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ACRD +CYDEV_CAN0_RX5_ACRD EQU 0x4000a15c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE +CYDEV_CAN0_RX6_BASE EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE +CYDEV_CAN0_RX6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_CMD +CYDEV_CAN0_RX6_CMD EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ID +CYDEV_CAN0_RX6_ID EQU 0x4000a164 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_DH +CYDEV_CAN0_RX6_DH EQU 0x4000a168 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_DL +CYDEV_CAN0_RX6_DL EQU 0x4000a16c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_AMR +CYDEV_CAN0_RX6_AMR EQU 0x4000a170 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ACR +CYDEV_CAN0_RX6_ACR EQU 0x4000a174 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_AMRD +CYDEV_CAN0_RX6_AMRD EQU 0x4000a178 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ACRD +CYDEV_CAN0_RX6_ACRD EQU 0x4000a17c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE +CYDEV_CAN0_RX7_BASE EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE +CYDEV_CAN0_RX7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_CMD +CYDEV_CAN0_RX7_CMD EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ID +CYDEV_CAN0_RX7_ID EQU 0x4000a184 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_DH +CYDEV_CAN0_RX7_DH EQU 0x4000a188 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_DL +CYDEV_CAN0_RX7_DL EQU 0x4000a18c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_AMR +CYDEV_CAN0_RX7_AMR EQU 0x4000a190 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ACR +CYDEV_CAN0_RX7_ACR EQU 0x4000a194 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_AMRD +CYDEV_CAN0_RX7_AMRD EQU 0x4000a198 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ACRD +CYDEV_CAN0_RX7_ACRD EQU 0x4000a19c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE +CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE +CYDEV_CAN0_RX8_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_CMD +CYDEV_CAN0_RX8_CMD EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ID +CYDEV_CAN0_RX8_ID EQU 0x4000a1a4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_DH +CYDEV_CAN0_RX8_DH EQU 0x4000a1a8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_DL +CYDEV_CAN0_RX8_DL EQU 0x4000a1ac + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_AMR +CYDEV_CAN0_RX8_AMR EQU 0x4000a1b0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ACR +CYDEV_CAN0_RX8_ACR EQU 0x4000a1b4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_AMRD +CYDEV_CAN0_RX8_AMRD EQU 0x4000a1b8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ACRD +CYDEV_CAN0_RX8_ACRD EQU 0x4000a1bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE +CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE +CYDEV_CAN0_RX9_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_CMD +CYDEV_CAN0_RX9_CMD EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ID +CYDEV_CAN0_RX9_ID EQU 0x4000a1c4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_DH +CYDEV_CAN0_RX9_DH EQU 0x4000a1c8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_DL +CYDEV_CAN0_RX9_DL EQU 0x4000a1cc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_AMR +CYDEV_CAN0_RX9_AMR EQU 0x4000a1d0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ACR +CYDEV_CAN0_RX9_ACR EQU 0x4000a1d4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_AMRD +CYDEV_CAN0_RX9_AMRD EQU 0x4000a1d8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ACRD +CYDEV_CAN0_RX9_ACRD EQU 0x4000a1dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE +CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE +CYDEV_CAN0_RX10_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_CMD +CYDEV_CAN0_RX10_CMD EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ID +CYDEV_CAN0_RX10_ID EQU 0x4000a1e4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_DH +CYDEV_CAN0_RX10_DH EQU 0x4000a1e8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_DL +CYDEV_CAN0_RX10_DL EQU 0x4000a1ec + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_AMR +CYDEV_CAN0_RX10_AMR EQU 0x4000a1f0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ACR +CYDEV_CAN0_RX10_ACR EQU 0x4000a1f4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_AMRD +CYDEV_CAN0_RX10_AMRD EQU 0x4000a1f8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ACRD +CYDEV_CAN0_RX10_ACRD EQU 0x4000a1fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE +CYDEV_CAN0_RX11_BASE EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE +CYDEV_CAN0_RX11_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_CMD +CYDEV_CAN0_RX11_CMD EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ID +CYDEV_CAN0_RX11_ID EQU 0x4000a204 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_DH +CYDEV_CAN0_RX11_DH EQU 0x4000a208 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_DL +CYDEV_CAN0_RX11_DL EQU 0x4000a20c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_AMR +CYDEV_CAN0_RX11_AMR EQU 0x4000a210 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ACR +CYDEV_CAN0_RX11_ACR EQU 0x4000a214 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_AMRD +CYDEV_CAN0_RX11_AMRD EQU 0x4000a218 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ACRD +CYDEV_CAN0_RX11_ACRD EQU 0x4000a21c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE +CYDEV_CAN0_RX12_BASE EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE +CYDEV_CAN0_RX12_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_CMD +CYDEV_CAN0_RX12_CMD EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ID +CYDEV_CAN0_RX12_ID EQU 0x4000a224 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_DH +CYDEV_CAN0_RX12_DH EQU 0x4000a228 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_DL +CYDEV_CAN0_RX12_DL EQU 0x4000a22c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_AMR +CYDEV_CAN0_RX12_AMR EQU 0x4000a230 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ACR +CYDEV_CAN0_RX12_ACR EQU 0x4000a234 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_AMRD +CYDEV_CAN0_RX12_AMRD EQU 0x4000a238 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ACRD +CYDEV_CAN0_RX12_ACRD EQU 0x4000a23c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE +CYDEV_CAN0_RX13_BASE EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE +CYDEV_CAN0_RX13_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_CMD +CYDEV_CAN0_RX13_CMD EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ID +CYDEV_CAN0_RX13_ID EQU 0x4000a244 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_DH +CYDEV_CAN0_RX13_DH EQU 0x4000a248 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_DL +CYDEV_CAN0_RX13_DL EQU 0x4000a24c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_AMR +CYDEV_CAN0_RX13_AMR EQU 0x4000a250 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ACR +CYDEV_CAN0_RX13_ACR EQU 0x4000a254 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_AMRD +CYDEV_CAN0_RX13_AMRD EQU 0x4000a258 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ACRD +CYDEV_CAN0_RX13_ACRD EQU 0x4000a25c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE +CYDEV_CAN0_RX14_BASE EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE +CYDEV_CAN0_RX14_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_CMD +CYDEV_CAN0_RX14_CMD EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ID +CYDEV_CAN0_RX14_ID EQU 0x4000a264 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_DH +CYDEV_CAN0_RX14_DH EQU 0x4000a268 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_DL +CYDEV_CAN0_RX14_DL EQU 0x4000a26c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_AMR +CYDEV_CAN0_RX14_AMR EQU 0x4000a270 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ACR +CYDEV_CAN0_RX14_ACR EQU 0x4000a274 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_AMRD +CYDEV_CAN0_RX14_AMRD EQU 0x4000a278 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ACRD +CYDEV_CAN0_RX14_ACRD EQU 0x4000a27c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE +CYDEV_CAN0_RX15_BASE EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE +CYDEV_CAN0_RX15_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_CMD +CYDEV_CAN0_RX15_CMD EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ID +CYDEV_CAN0_RX15_ID EQU 0x4000a284 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_DH +CYDEV_CAN0_RX15_DH EQU 0x4000a288 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_DL +CYDEV_CAN0_RX15_DL EQU 0x4000a28c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_AMR +CYDEV_CAN0_RX15_AMR EQU 0x4000a290 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ACR +CYDEV_CAN0_RX15_ACR EQU 0x4000a294 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_AMRD +CYDEV_CAN0_RX15_AMRD EQU 0x4000a298 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ACRD +CYDEV_CAN0_RX15_ACRD EQU 0x4000a29c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_BASE +CYDEV_DFB0_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SIZE +CYDEV_DFB0_SIZE EQU 0x000007b5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE +CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE +CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MBASE +CYDEV_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MSIZE +CYDEV_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE +CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE +CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MBASE +CYDEV_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MSIZE +CYDEV_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE +CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE +CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MBASE +CYDEV_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MSIZE +CYDEV_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE +CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE +CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MBASE +CYDEV_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MSIZE +CYDEV_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE +CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE +CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MBASE +CYDEV_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MSIZE +CYDEV_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE +CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE +CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MBASE +CYDEV_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MSIZE +CYDEV_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CR +CYDEV_DFB0_CR EQU 0x4000c780 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SR +CYDEV_DFB0_SR EQU 0x4000c784 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_RAM_EN +CYDEV_DFB0_RAM_EN EQU 0x4000c788 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_RAM_DIR +CYDEV_DFB0_RAM_DIR EQU 0x4000c78c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SEMA +CYDEV_DFB0_SEMA EQU 0x4000c790 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DSI_CTRL +CYDEV_DFB0_DSI_CTRL EQU 0x4000c794 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_INT_CTRL +CYDEV_DFB0_INT_CTRL EQU 0x4000c798 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DMA_CTRL +CYDEV_DFB0_DMA_CTRL EQU 0x4000c79c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEA +CYDEV_DFB0_STAGEA EQU 0x4000c7a0 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEAM +CYDEV_DFB0_STAGEAM EQU 0x4000c7a1 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEAH +CYDEV_DFB0_STAGEAH EQU 0x4000c7a2 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEB +CYDEV_DFB0_STAGEB EQU 0x4000c7a4 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEBM +CYDEV_DFB0_STAGEBM EQU 0x4000c7a5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEBH +CYDEV_DFB0_STAGEBH EQU 0x4000c7a6 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDA +CYDEV_DFB0_HOLDA EQU 0x4000c7a8 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAM +CYDEV_DFB0_HOLDAM EQU 0x4000c7a9 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAH +CYDEV_DFB0_HOLDAH EQU 0x4000c7aa + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAS +CYDEV_DFB0_HOLDAS EQU 0x4000c7ab + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDB +CYDEV_DFB0_HOLDB EQU 0x4000c7ac + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBM +CYDEV_DFB0_HOLDBM EQU 0x4000c7ad + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBH +CYDEV_DFB0_HOLDBH EQU 0x4000c7ae + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBS +CYDEV_DFB0_HOLDBS EQU 0x4000c7af + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_COHER +CYDEV_DFB0_COHER EQU 0x4000c7b0 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DALIGN +CYDEV_DFB0_DALIGN EQU 0x4000c7b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BASE +CYDEV_UCFG_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_SIZE +CYDEV_UCFG_SIZE EQU 0x00005040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_BASE +CYDEV_UCFG_B0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE +CYDEV_UCFG_B0_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE +CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE +CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE +CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE +CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT0 +CYDEV_UCFG_B0_P0_U0_PLD_IT0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT1 +CYDEV_UCFG_B0_P0_U0_PLD_IT1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT2 +CYDEV_UCFG_B0_P0_U0_PLD_IT2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT3 +CYDEV_UCFG_B0_P0_U0_PLD_IT3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT4 +CYDEV_UCFG_B0_P0_U0_PLD_IT4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT5 +CYDEV_UCFG_B0_P0_U0_PLD_IT5 EQU 0x40010014 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT6 +CYDEV_UCFG_B0_P0_U0_PLD_IT6 EQU 0x40010018 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT7 +CYDEV_UCFG_B0_P0_U0_PLD_IT7 EQU 0x4001001c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT8 +CYDEV_UCFG_B0_P0_U0_PLD_IT8 EQU 0x40010020 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT9 +CYDEV_UCFG_B0_P0_U0_PLD_IT9 EQU 0x40010024 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT10 +CYDEV_UCFG_B0_P0_U0_PLD_IT10 EQU 0x40010028 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT11 +CYDEV_UCFG_B0_P0_U0_PLD_IT11 EQU 0x4001002c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT0 +CYDEV_UCFG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT1 +CYDEV_UCFG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT2 +CYDEV_UCFG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT3 +CYDEV_UCFG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG0 +CYDEV_UCFG_B0_P0_U0_CFG0 EQU 0x40010040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG1 +CYDEV_UCFG_B0_P0_U0_CFG1 EQU 0x40010041 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG2 +CYDEV_UCFG_B0_P0_U0_CFG2 EQU 0x40010042 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG3 +CYDEV_UCFG_B0_P0_U0_CFG3 EQU 0x40010043 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG4 +CYDEV_UCFG_B0_P0_U0_CFG4 EQU 0x40010044 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG5 +CYDEV_UCFG_B0_P0_U0_CFG5 EQU 0x40010045 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG6 +CYDEV_UCFG_B0_P0_U0_CFG6 EQU 0x40010046 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG7 +CYDEV_UCFG_B0_P0_U0_CFG7 EQU 0x40010047 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG8 +CYDEV_UCFG_B0_P0_U0_CFG8 EQU 0x40010048 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG9 +CYDEV_UCFG_B0_P0_U0_CFG9 EQU 0x40010049 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG10 +CYDEV_UCFG_B0_P0_U0_CFG10 EQU 0x4001004a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG11 +CYDEV_UCFG_B0_P0_U0_CFG11 EQU 0x4001004b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG12 +CYDEV_UCFG_B0_P0_U0_CFG12 EQU 0x4001004c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG13 +CYDEV_UCFG_B0_P0_U0_CFG13 EQU 0x4001004d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG14 +CYDEV_UCFG_B0_P0_U0_CFG14 EQU 0x4001004e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG15 +CYDEV_UCFG_B0_P0_U0_CFG15 EQU 0x4001004f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG16 +CYDEV_UCFG_B0_P0_U0_CFG16 EQU 0x40010050 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG17 +CYDEV_UCFG_B0_P0_U0_CFG17 EQU 0x40010051 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG18 +CYDEV_UCFG_B0_P0_U0_CFG18 EQU 0x40010052 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG19 +CYDEV_UCFG_B0_P0_U0_CFG19 EQU 0x40010053 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG20 +CYDEV_UCFG_B0_P0_U0_CFG20 EQU 0x40010054 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG21 +CYDEV_UCFG_B0_P0_U0_CFG21 EQU 0x40010055 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG22 +CYDEV_UCFG_B0_P0_U0_CFG22 EQU 0x40010056 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG23 +CYDEV_UCFG_B0_P0_U0_CFG23 EQU 0x40010057 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG24 +CYDEV_UCFG_B0_P0_U0_CFG24 EQU 0x40010058 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG25 +CYDEV_UCFG_B0_P0_U0_CFG25 EQU 0x40010059 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG26 +CYDEV_UCFG_B0_P0_U0_CFG26 EQU 0x4001005a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG27 +CYDEV_UCFG_B0_P0_U0_CFG27 EQU 0x4001005b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG28 +CYDEV_UCFG_B0_P0_U0_CFG28 EQU 0x4001005c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG29 +CYDEV_UCFG_B0_P0_U0_CFG29 EQU 0x4001005d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG30 +CYDEV_UCFG_B0_P0_U0_CFG30 EQU 0x4001005e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG31 +CYDEV_UCFG_B0_P0_U0_CFG31 EQU 0x4001005f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG0 +CYDEV_UCFG_B0_P0_U0_DCFG0 EQU 0x40010060 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG1 +CYDEV_UCFG_B0_P0_U0_DCFG1 EQU 0x40010062 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG2 +CYDEV_UCFG_B0_P0_U0_DCFG2 EQU 0x40010064 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG3 +CYDEV_UCFG_B0_P0_U0_DCFG3 EQU 0x40010066 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG4 +CYDEV_UCFG_B0_P0_U0_DCFG4 EQU 0x40010068 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG5 +CYDEV_UCFG_B0_P0_U0_DCFG5 EQU 0x4001006a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG6 +CYDEV_UCFG_B0_P0_U0_DCFG6 EQU 0x4001006c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG7 +CYDEV_UCFG_B0_P0_U0_DCFG7 EQU 0x4001006e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE +CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE +CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT0 +CYDEV_UCFG_B0_P0_U1_PLD_IT0 EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT1 +CYDEV_UCFG_B0_P0_U1_PLD_IT1 EQU 0x40010084 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT2 +CYDEV_UCFG_B0_P0_U1_PLD_IT2 EQU 0x40010088 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT3 +CYDEV_UCFG_B0_P0_U1_PLD_IT3 EQU 0x4001008c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT4 +CYDEV_UCFG_B0_P0_U1_PLD_IT4 EQU 0x40010090 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT5 +CYDEV_UCFG_B0_P0_U1_PLD_IT5 EQU 0x40010094 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT6 +CYDEV_UCFG_B0_P0_U1_PLD_IT6 EQU 0x40010098 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT7 +CYDEV_UCFG_B0_P0_U1_PLD_IT7 EQU 0x4001009c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT8 +CYDEV_UCFG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT9 +CYDEV_UCFG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT10 +CYDEV_UCFG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT11 +CYDEV_UCFG_B0_P0_U1_PLD_IT11 EQU 0x400100ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT0 +CYDEV_UCFG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT1 +CYDEV_UCFG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT2 +CYDEV_UCFG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT3 +CYDEV_UCFG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG0 +CYDEV_UCFG_B0_P0_U1_CFG0 EQU 0x400100c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG1 +CYDEV_UCFG_B0_P0_U1_CFG1 EQU 0x400100c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG2 +CYDEV_UCFG_B0_P0_U1_CFG2 EQU 0x400100c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG3 +CYDEV_UCFG_B0_P0_U1_CFG3 EQU 0x400100c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG4 +CYDEV_UCFG_B0_P0_U1_CFG4 EQU 0x400100c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG5 +CYDEV_UCFG_B0_P0_U1_CFG5 EQU 0x400100c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG6 +CYDEV_UCFG_B0_P0_U1_CFG6 EQU 0x400100c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG7 +CYDEV_UCFG_B0_P0_U1_CFG7 EQU 0x400100c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG8 +CYDEV_UCFG_B0_P0_U1_CFG8 EQU 0x400100c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG9 +CYDEV_UCFG_B0_P0_U1_CFG9 EQU 0x400100c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG10 +CYDEV_UCFG_B0_P0_U1_CFG10 EQU 0x400100ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG11 +CYDEV_UCFG_B0_P0_U1_CFG11 EQU 0x400100cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG12 +CYDEV_UCFG_B0_P0_U1_CFG12 EQU 0x400100cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG13 +CYDEV_UCFG_B0_P0_U1_CFG13 EQU 0x400100cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG14 +CYDEV_UCFG_B0_P0_U1_CFG14 EQU 0x400100ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG15 +CYDEV_UCFG_B0_P0_U1_CFG15 EQU 0x400100cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG16 +CYDEV_UCFG_B0_P0_U1_CFG16 EQU 0x400100d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG17 +CYDEV_UCFG_B0_P0_U1_CFG17 EQU 0x400100d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG18 +CYDEV_UCFG_B0_P0_U1_CFG18 EQU 0x400100d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG19 +CYDEV_UCFG_B0_P0_U1_CFG19 EQU 0x400100d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG20 +CYDEV_UCFG_B0_P0_U1_CFG20 EQU 0x400100d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG21 +CYDEV_UCFG_B0_P0_U1_CFG21 EQU 0x400100d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG22 +CYDEV_UCFG_B0_P0_U1_CFG22 EQU 0x400100d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG23 +CYDEV_UCFG_B0_P0_U1_CFG23 EQU 0x400100d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG24 +CYDEV_UCFG_B0_P0_U1_CFG24 EQU 0x400100d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG25 +CYDEV_UCFG_B0_P0_U1_CFG25 EQU 0x400100d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG26 +CYDEV_UCFG_B0_P0_U1_CFG26 EQU 0x400100da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG27 +CYDEV_UCFG_B0_P0_U1_CFG27 EQU 0x400100db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG28 +CYDEV_UCFG_B0_P0_U1_CFG28 EQU 0x400100dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG29 +CYDEV_UCFG_B0_P0_U1_CFG29 EQU 0x400100dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG30 +CYDEV_UCFG_B0_P0_U1_CFG30 EQU 0x400100de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG31 +CYDEV_UCFG_B0_P0_U1_CFG31 EQU 0x400100df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG0 +CYDEV_UCFG_B0_P0_U1_DCFG0 EQU 0x400100e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG1 +CYDEV_UCFG_B0_P0_U1_DCFG1 EQU 0x400100e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG2 +CYDEV_UCFG_B0_P0_U1_DCFG2 EQU 0x400100e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG3 +CYDEV_UCFG_B0_P0_U1_DCFG3 EQU 0x400100e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG4 +CYDEV_UCFG_B0_P0_U1_DCFG4 EQU 0x400100e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG5 +CYDEV_UCFG_B0_P0_U1_DCFG5 EQU 0x400100ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG6 +CYDEV_UCFG_B0_P0_U1_DCFG6 EQU 0x400100ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG7 +CYDEV_UCFG_B0_P0_U1_DCFG7 EQU 0x400100ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE +CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE +CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE +CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE +CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE +CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE +CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT0 +CYDEV_UCFG_B0_P1_U0_PLD_IT0 EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT1 +CYDEV_UCFG_B0_P1_U0_PLD_IT1 EQU 0x40010204 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT2 +CYDEV_UCFG_B0_P1_U0_PLD_IT2 EQU 0x40010208 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT3 +CYDEV_UCFG_B0_P1_U0_PLD_IT3 EQU 0x4001020c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT4 +CYDEV_UCFG_B0_P1_U0_PLD_IT4 EQU 0x40010210 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT5 +CYDEV_UCFG_B0_P1_U0_PLD_IT5 EQU 0x40010214 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT6 +CYDEV_UCFG_B0_P1_U0_PLD_IT6 EQU 0x40010218 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT7 +CYDEV_UCFG_B0_P1_U0_PLD_IT7 EQU 0x4001021c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT8 +CYDEV_UCFG_B0_P1_U0_PLD_IT8 EQU 0x40010220 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT9 +CYDEV_UCFG_B0_P1_U0_PLD_IT9 EQU 0x40010224 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT10 +CYDEV_UCFG_B0_P1_U0_PLD_IT10 EQU 0x40010228 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT11 +CYDEV_UCFG_B0_P1_U0_PLD_IT11 EQU 0x4001022c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT0 +CYDEV_UCFG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT1 +CYDEV_UCFG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT2 +CYDEV_UCFG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT3 +CYDEV_UCFG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG0 +CYDEV_UCFG_B0_P1_U0_CFG0 EQU 0x40010240 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG1 +CYDEV_UCFG_B0_P1_U0_CFG1 EQU 0x40010241 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG2 +CYDEV_UCFG_B0_P1_U0_CFG2 EQU 0x40010242 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG3 +CYDEV_UCFG_B0_P1_U0_CFG3 EQU 0x40010243 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG4 +CYDEV_UCFG_B0_P1_U0_CFG4 EQU 0x40010244 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG5 +CYDEV_UCFG_B0_P1_U0_CFG5 EQU 0x40010245 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG6 +CYDEV_UCFG_B0_P1_U0_CFG6 EQU 0x40010246 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG7 +CYDEV_UCFG_B0_P1_U0_CFG7 EQU 0x40010247 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG8 +CYDEV_UCFG_B0_P1_U0_CFG8 EQU 0x40010248 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG9 +CYDEV_UCFG_B0_P1_U0_CFG9 EQU 0x40010249 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG10 +CYDEV_UCFG_B0_P1_U0_CFG10 EQU 0x4001024a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG11 +CYDEV_UCFG_B0_P1_U0_CFG11 EQU 0x4001024b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG12 +CYDEV_UCFG_B0_P1_U0_CFG12 EQU 0x4001024c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG13 +CYDEV_UCFG_B0_P1_U0_CFG13 EQU 0x4001024d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG14 +CYDEV_UCFG_B0_P1_U0_CFG14 EQU 0x4001024e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG15 +CYDEV_UCFG_B0_P1_U0_CFG15 EQU 0x4001024f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG16 +CYDEV_UCFG_B0_P1_U0_CFG16 EQU 0x40010250 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG17 +CYDEV_UCFG_B0_P1_U0_CFG17 EQU 0x40010251 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG18 +CYDEV_UCFG_B0_P1_U0_CFG18 EQU 0x40010252 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG19 +CYDEV_UCFG_B0_P1_U0_CFG19 EQU 0x40010253 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG20 +CYDEV_UCFG_B0_P1_U0_CFG20 EQU 0x40010254 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG21 +CYDEV_UCFG_B0_P1_U0_CFG21 EQU 0x40010255 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG22 +CYDEV_UCFG_B0_P1_U0_CFG22 EQU 0x40010256 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG23 +CYDEV_UCFG_B0_P1_U0_CFG23 EQU 0x40010257 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG24 +CYDEV_UCFG_B0_P1_U0_CFG24 EQU 0x40010258 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG25 +CYDEV_UCFG_B0_P1_U0_CFG25 EQU 0x40010259 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG26 +CYDEV_UCFG_B0_P1_U0_CFG26 EQU 0x4001025a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG27 +CYDEV_UCFG_B0_P1_U0_CFG27 EQU 0x4001025b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG28 +CYDEV_UCFG_B0_P1_U0_CFG28 EQU 0x4001025c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG29 +CYDEV_UCFG_B0_P1_U0_CFG29 EQU 0x4001025d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG30 +CYDEV_UCFG_B0_P1_U0_CFG30 EQU 0x4001025e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG31 +CYDEV_UCFG_B0_P1_U0_CFG31 EQU 0x4001025f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG0 +CYDEV_UCFG_B0_P1_U0_DCFG0 EQU 0x40010260 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG1 +CYDEV_UCFG_B0_P1_U0_DCFG1 EQU 0x40010262 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG2 +CYDEV_UCFG_B0_P1_U0_DCFG2 EQU 0x40010264 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG3 +CYDEV_UCFG_B0_P1_U0_DCFG3 EQU 0x40010266 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG4 +CYDEV_UCFG_B0_P1_U0_DCFG4 EQU 0x40010268 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG5 +CYDEV_UCFG_B0_P1_U0_DCFG5 EQU 0x4001026a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG6 +CYDEV_UCFG_B0_P1_U0_DCFG6 EQU 0x4001026c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG7 +CYDEV_UCFG_B0_P1_U0_DCFG7 EQU 0x4001026e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE +CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE +CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT0 +CYDEV_UCFG_B0_P1_U1_PLD_IT0 EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT1 +CYDEV_UCFG_B0_P1_U1_PLD_IT1 EQU 0x40010284 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT2 +CYDEV_UCFG_B0_P1_U1_PLD_IT2 EQU 0x40010288 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT3 +CYDEV_UCFG_B0_P1_U1_PLD_IT3 EQU 0x4001028c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT4 +CYDEV_UCFG_B0_P1_U1_PLD_IT4 EQU 0x40010290 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT5 +CYDEV_UCFG_B0_P1_U1_PLD_IT5 EQU 0x40010294 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT6 +CYDEV_UCFG_B0_P1_U1_PLD_IT6 EQU 0x40010298 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT7 +CYDEV_UCFG_B0_P1_U1_PLD_IT7 EQU 0x4001029c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT8 +CYDEV_UCFG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT9 +CYDEV_UCFG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT10 +CYDEV_UCFG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT11 +CYDEV_UCFG_B0_P1_U1_PLD_IT11 EQU 0x400102ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT0 +CYDEV_UCFG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT1 +CYDEV_UCFG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT2 +CYDEV_UCFG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT3 +CYDEV_UCFG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG0 +CYDEV_UCFG_B0_P1_U1_CFG0 EQU 0x400102c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG1 +CYDEV_UCFG_B0_P1_U1_CFG1 EQU 0x400102c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG2 +CYDEV_UCFG_B0_P1_U1_CFG2 EQU 0x400102c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG3 +CYDEV_UCFG_B0_P1_U1_CFG3 EQU 0x400102c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG4 +CYDEV_UCFG_B0_P1_U1_CFG4 EQU 0x400102c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG5 +CYDEV_UCFG_B0_P1_U1_CFG5 EQU 0x400102c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG6 +CYDEV_UCFG_B0_P1_U1_CFG6 EQU 0x400102c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG7 +CYDEV_UCFG_B0_P1_U1_CFG7 EQU 0x400102c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG8 +CYDEV_UCFG_B0_P1_U1_CFG8 EQU 0x400102c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG9 +CYDEV_UCFG_B0_P1_U1_CFG9 EQU 0x400102c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG10 +CYDEV_UCFG_B0_P1_U1_CFG10 EQU 0x400102ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG11 +CYDEV_UCFG_B0_P1_U1_CFG11 EQU 0x400102cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG12 +CYDEV_UCFG_B0_P1_U1_CFG12 EQU 0x400102cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG13 +CYDEV_UCFG_B0_P1_U1_CFG13 EQU 0x400102cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG14 +CYDEV_UCFG_B0_P1_U1_CFG14 EQU 0x400102ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG15 +CYDEV_UCFG_B0_P1_U1_CFG15 EQU 0x400102cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG16 +CYDEV_UCFG_B0_P1_U1_CFG16 EQU 0x400102d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG17 +CYDEV_UCFG_B0_P1_U1_CFG17 EQU 0x400102d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG18 +CYDEV_UCFG_B0_P1_U1_CFG18 EQU 0x400102d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG19 +CYDEV_UCFG_B0_P1_U1_CFG19 EQU 0x400102d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG20 +CYDEV_UCFG_B0_P1_U1_CFG20 EQU 0x400102d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG21 +CYDEV_UCFG_B0_P1_U1_CFG21 EQU 0x400102d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG22 +CYDEV_UCFG_B0_P1_U1_CFG22 EQU 0x400102d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG23 +CYDEV_UCFG_B0_P1_U1_CFG23 EQU 0x400102d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG24 +CYDEV_UCFG_B0_P1_U1_CFG24 EQU 0x400102d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG25 +CYDEV_UCFG_B0_P1_U1_CFG25 EQU 0x400102d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG26 +CYDEV_UCFG_B0_P1_U1_CFG26 EQU 0x400102da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG27 +CYDEV_UCFG_B0_P1_U1_CFG27 EQU 0x400102db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG28 +CYDEV_UCFG_B0_P1_U1_CFG28 EQU 0x400102dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG29 +CYDEV_UCFG_B0_P1_U1_CFG29 EQU 0x400102dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG30 +CYDEV_UCFG_B0_P1_U1_CFG30 EQU 0x400102de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG31 +CYDEV_UCFG_B0_P1_U1_CFG31 EQU 0x400102df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG0 +CYDEV_UCFG_B0_P1_U1_DCFG0 EQU 0x400102e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG1 +CYDEV_UCFG_B0_P1_U1_DCFG1 EQU 0x400102e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG2 +CYDEV_UCFG_B0_P1_U1_DCFG2 EQU 0x400102e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG3 +CYDEV_UCFG_B0_P1_U1_DCFG3 EQU 0x400102e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG4 +CYDEV_UCFG_B0_P1_U1_DCFG4 EQU 0x400102e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG5 +CYDEV_UCFG_B0_P1_U1_DCFG5 EQU 0x400102ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG6 +CYDEV_UCFG_B0_P1_U1_DCFG6 EQU 0x400102ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG7 +CYDEV_UCFG_B0_P1_U1_DCFG7 EQU 0x400102ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE +CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE +CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE +CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE +CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE +CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE +CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT0 +CYDEV_UCFG_B0_P2_U0_PLD_IT0 EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT1 +CYDEV_UCFG_B0_P2_U0_PLD_IT1 EQU 0x40010404 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT2 +CYDEV_UCFG_B0_P2_U0_PLD_IT2 EQU 0x40010408 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT3 +CYDEV_UCFG_B0_P2_U0_PLD_IT3 EQU 0x4001040c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT4 +CYDEV_UCFG_B0_P2_U0_PLD_IT4 EQU 0x40010410 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT5 +CYDEV_UCFG_B0_P2_U0_PLD_IT5 EQU 0x40010414 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT6 +CYDEV_UCFG_B0_P2_U0_PLD_IT6 EQU 0x40010418 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT7 +CYDEV_UCFG_B0_P2_U0_PLD_IT7 EQU 0x4001041c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT8 +CYDEV_UCFG_B0_P2_U0_PLD_IT8 EQU 0x40010420 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT9 +CYDEV_UCFG_B0_P2_U0_PLD_IT9 EQU 0x40010424 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT10 +CYDEV_UCFG_B0_P2_U0_PLD_IT10 EQU 0x40010428 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT11 +CYDEV_UCFG_B0_P2_U0_PLD_IT11 EQU 0x4001042c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT0 +CYDEV_UCFG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT1 +CYDEV_UCFG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT2 +CYDEV_UCFG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT3 +CYDEV_UCFG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG0 +CYDEV_UCFG_B0_P2_U0_CFG0 EQU 0x40010440 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG1 +CYDEV_UCFG_B0_P2_U0_CFG1 EQU 0x40010441 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG2 +CYDEV_UCFG_B0_P2_U0_CFG2 EQU 0x40010442 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG3 +CYDEV_UCFG_B0_P2_U0_CFG3 EQU 0x40010443 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG4 +CYDEV_UCFG_B0_P2_U0_CFG4 EQU 0x40010444 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG5 +CYDEV_UCFG_B0_P2_U0_CFG5 EQU 0x40010445 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG6 +CYDEV_UCFG_B0_P2_U0_CFG6 EQU 0x40010446 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG7 +CYDEV_UCFG_B0_P2_U0_CFG7 EQU 0x40010447 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG8 +CYDEV_UCFG_B0_P2_U0_CFG8 EQU 0x40010448 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG9 +CYDEV_UCFG_B0_P2_U0_CFG9 EQU 0x40010449 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG10 +CYDEV_UCFG_B0_P2_U0_CFG10 EQU 0x4001044a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG11 +CYDEV_UCFG_B0_P2_U0_CFG11 EQU 0x4001044b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG12 +CYDEV_UCFG_B0_P2_U0_CFG12 EQU 0x4001044c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG13 +CYDEV_UCFG_B0_P2_U0_CFG13 EQU 0x4001044d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG14 +CYDEV_UCFG_B0_P2_U0_CFG14 EQU 0x4001044e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG15 +CYDEV_UCFG_B0_P2_U0_CFG15 EQU 0x4001044f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG16 +CYDEV_UCFG_B0_P2_U0_CFG16 EQU 0x40010450 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG17 +CYDEV_UCFG_B0_P2_U0_CFG17 EQU 0x40010451 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG18 +CYDEV_UCFG_B0_P2_U0_CFG18 EQU 0x40010452 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG19 +CYDEV_UCFG_B0_P2_U0_CFG19 EQU 0x40010453 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG20 +CYDEV_UCFG_B0_P2_U0_CFG20 EQU 0x40010454 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG21 +CYDEV_UCFG_B0_P2_U0_CFG21 EQU 0x40010455 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG22 +CYDEV_UCFG_B0_P2_U0_CFG22 EQU 0x40010456 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG23 +CYDEV_UCFG_B0_P2_U0_CFG23 EQU 0x40010457 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG24 +CYDEV_UCFG_B0_P2_U0_CFG24 EQU 0x40010458 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG25 +CYDEV_UCFG_B0_P2_U0_CFG25 EQU 0x40010459 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG26 +CYDEV_UCFG_B0_P2_U0_CFG26 EQU 0x4001045a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG27 +CYDEV_UCFG_B0_P2_U0_CFG27 EQU 0x4001045b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG28 +CYDEV_UCFG_B0_P2_U0_CFG28 EQU 0x4001045c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG29 +CYDEV_UCFG_B0_P2_U0_CFG29 EQU 0x4001045d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG30 +CYDEV_UCFG_B0_P2_U0_CFG30 EQU 0x4001045e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG31 +CYDEV_UCFG_B0_P2_U0_CFG31 EQU 0x4001045f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG0 +CYDEV_UCFG_B0_P2_U0_DCFG0 EQU 0x40010460 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG1 +CYDEV_UCFG_B0_P2_U0_DCFG1 EQU 0x40010462 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG2 +CYDEV_UCFG_B0_P2_U0_DCFG2 EQU 0x40010464 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG3 +CYDEV_UCFG_B0_P2_U0_DCFG3 EQU 0x40010466 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG4 +CYDEV_UCFG_B0_P2_U0_DCFG4 EQU 0x40010468 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG5 +CYDEV_UCFG_B0_P2_U0_DCFG5 EQU 0x4001046a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG6 +CYDEV_UCFG_B0_P2_U0_DCFG6 EQU 0x4001046c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG7 +CYDEV_UCFG_B0_P2_U0_DCFG7 EQU 0x4001046e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE +CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE +CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT0 +CYDEV_UCFG_B0_P2_U1_PLD_IT0 EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT1 +CYDEV_UCFG_B0_P2_U1_PLD_IT1 EQU 0x40010484 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT2 +CYDEV_UCFG_B0_P2_U1_PLD_IT2 EQU 0x40010488 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT3 +CYDEV_UCFG_B0_P2_U1_PLD_IT3 EQU 0x4001048c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT4 +CYDEV_UCFG_B0_P2_U1_PLD_IT4 EQU 0x40010490 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT5 +CYDEV_UCFG_B0_P2_U1_PLD_IT5 EQU 0x40010494 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT6 +CYDEV_UCFG_B0_P2_U1_PLD_IT6 EQU 0x40010498 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT7 +CYDEV_UCFG_B0_P2_U1_PLD_IT7 EQU 0x4001049c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT8 +CYDEV_UCFG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT9 +CYDEV_UCFG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT10 +CYDEV_UCFG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT11 +CYDEV_UCFG_B0_P2_U1_PLD_IT11 EQU 0x400104ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT0 +CYDEV_UCFG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT1 +CYDEV_UCFG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT2 +CYDEV_UCFG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT3 +CYDEV_UCFG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG0 +CYDEV_UCFG_B0_P2_U1_CFG0 EQU 0x400104c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG1 +CYDEV_UCFG_B0_P2_U1_CFG1 EQU 0x400104c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG2 +CYDEV_UCFG_B0_P2_U1_CFG2 EQU 0x400104c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG3 +CYDEV_UCFG_B0_P2_U1_CFG3 EQU 0x400104c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG4 +CYDEV_UCFG_B0_P2_U1_CFG4 EQU 0x400104c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG5 +CYDEV_UCFG_B0_P2_U1_CFG5 EQU 0x400104c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG6 +CYDEV_UCFG_B0_P2_U1_CFG6 EQU 0x400104c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG7 +CYDEV_UCFG_B0_P2_U1_CFG7 EQU 0x400104c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG8 +CYDEV_UCFG_B0_P2_U1_CFG8 EQU 0x400104c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG9 +CYDEV_UCFG_B0_P2_U1_CFG9 EQU 0x400104c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG10 +CYDEV_UCFG_B0_P2_U1_CFG10 EQU 0x400104ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG11 +CYDEV_UCFG_B0_P2_U1_CFG11 EQU 0x400104cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG12 +CYDEV_UCFG_B0_P2_U1_CFG12 EQU 0x400104cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG13 +CYDEV_UCFG_B0_P2_U1_CFG13 EQU 0x400104cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG14 +CYDEV_UCFG_B0_P2_U1_CFG14 EQU 0x400104ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG15 +CYDEV_UCFG_B0_P2_U1_CFG15 EQU 0x400104cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG16 +CYDEV_UCFG_B0_P2_U1_CFG16 EQU 0x400104d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG17 +CYDEV_UCFG_B0_P2_U1_CFG17 EQU 0x400104d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG18 +CYDEV_UCFG_B0_P2_U1_CFG18 EQU 0x400104d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG19 +CYDEV_UCFG_B0_P2_U1_CFG19 EQU 0x400104d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG20 +CYDEV_UCFG_B0_P2_U1_CFG20 EQU 0x400104d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG21 +CYDEV_UCFG_B0_P2_U1_CFG21 EQU 0x400104d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG22 +CYDEV_UCFG_B0_P2_U1_CFG22 EQU 0x400104d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG23 +CYDEV_UCFG_B0_P2_U1_CFG23 EQU 0x400104d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG24 +CYDEV_UCFG_B0_P2_U1_CFG24 EQU 0x400104d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG25 +CYDEV_UCFG_B0_P2_U1_CFG25 EQU 0x400104d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG26 +CYDEV_UCFG_B0_P2_U1_CFG26 EQU 0x400104da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG27 +CYDEV_UCFG_B0_P2_U1_CFG27 EQU 0x400104db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG28 +CYDEV_UCFG_B0_P2_U1_CFG28 EQU 0x400104dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG29 +CYDEV_UCFG_B0_P2_U1_CFG29 EQU 0x400104dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG30 +CYDEV_UCFG_B0_P2_U1_CFG30 EQU 0x400104de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG31 +CYDEV_UCFG_B0_P2_U1_CFG31 EQU 0x400104df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG0 +CYDEV_UCFG_B0_P2_U1_DCFG0 EQU 0x400104e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG1 +CYDEV_UCFG_B0_P2_U1_DCFG1 EQU 0x400104e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG2 +CYDEV_UCFG_B0_P2_U1_DCFG2 EQU 0x400104e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG3 +CYDEV_UCFG_B0_P2_U1_DCFG3 EQU 0x400104e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG4 +CYDEV_UCFG_B0_P2_U1_DCFG4 EQU 0x400104e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG5 +CYDEV_UCFG_B0_P2_U1_DCFG5 EQU 0x400104ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG6 +CYDEV_UCFG_B0_P2_U1_DCFG6 EQU 0x400104ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG7 +CYDEV_UCFG_B0_P2_U1_DCFG7 EQU 0x400104ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE +CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE +CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE +CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE +CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE +CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE +CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT0 +CYDEV_UCFG_B0_P3_U0_PLD_IT0 EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT1 +CYDEV_UCFG_B0_P3_U0_PLD_IT1 EQU 0x40010604 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT2 +CYDEV_UCFG_B0_P3_U0_PLD_IT2 EQU 0x40010608 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT3 +CYDEV_UCFG_B0_P3_U0_PLD_IT3 EQU 0x4001060c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT4 +CYDEV_UCFG_B0_P3_U0_PLD_IT4 EQU 0x40010610 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT5 +CYDEV_UCFG_B0_P3_U0_PLD_IT5 EQU 0x40010614 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT6 +CYDEV_UCFG_B0_P3_U0_PLD_IT6 EQU 0x40010618 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT7 +CYDEV_UCFG_B0_P3_U0_PLD_IT7 EQU 0x4001061c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT8 +CYDEV_UCFG_B0_P3_U0_PLD_IT8 EQU 0x40010620 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT9 +CYDEV_UCFG_B0_P3_U0_PLD_IT9 EQU 0x40010624 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT10 +CYDEV_UCFG_B0_P3_U0_PLD_IT10 EQU 0x40010628 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT11 +CYDEV_UCFG_B0_P3_U0_PLD_IT11 EQU 0x4001062c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT0 +CYDEV_UCFG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT1 +CYDEV_UCFG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT2 +CYDEV_UCFG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT3 +CYDEV_UCFG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG0 +CYDEV_UCFG_B0_P3_U0_CFG0 EQU 0x40010640 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG1 +CYDEV_UCFG_B0_P3_U0_CFG1 EQU 0x40010641 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG2 +CYDEV_UCFG_B0_P3_U0_CFG2 EQU 0x40010642 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG3 +CYDEV_UCFG_B0_P3_U0_CFG3 EQU 0x40010643 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG4 +CYDEV_UCFG_B0_P3_U0_CFG4 EQU 0x40010644 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG5 +CYDEV_UCFG_B0_P3_U0_CFG5 EQU 0x40010645 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG6 +CYDEV_UCFG_B0_P3_U0_CFG6 EQU 0x40010646 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG7 +CYDEV_UCFG_B0_P3_U0_CFG7 EQU 0x40010647 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG8 +CYDEV_UCFG_B0_P3_U0_CFG8 EQU 0x40010648 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG9 +CYDEV_UCFG_B0_P3_U0_CFG9 EQU 0x40010649 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG10 +CYDEV_UCFG_B0_P3_U0_CFG10 EQU 0x4001064a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG11 +CYDEV_UCFG_B0_P3_U0_CFG11 EQU 0x4001064b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG12 +CYDEV_UCFG_B0_P3_U0_CFG12 EQU 0x4001064c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG13 +CYDEV_UCFG_B0_P3_U0_CFG13 EQU 0x4001064d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG14 +CYDEV_UCFG_B0_P3_U0_CFG14 EQU 0x4001064e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG15 +CYDEV_UCFG_B0_P3_U0_CFG15 EQU 0x4001064f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG16 +CYDEV_UCFG_B0_P3_U0_CFG16 EQU 0x40010650 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG17 +CYDEV_UCFG_B0_P3_U0_CFG17 EQU 0x40010651 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG18 +CYDEV_UCFG_B0_P3_U0_CFG18 EQU 0x40010652 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG19 +CYDEV_UCFG_B0_P3_U0_CFG19 EQU 0x40010653 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG20 +CYDEV_UCFG_B0_P3_U0_CFG20 EQU 0x40010654 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG21 +CYDEV_UCFG_B0_P3_U0_CFG21 EQU 0x40010655 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG22 +CYDEV_UCFG_B0_P3_U0_CFG22 EQU 0x40010656 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG23 +CYDEV_UCFG_B0_P3_U0_CFG23 EQU 0x40010657 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG24 +CYDEV_UCFG_B0_P3_U0_CFG24 EQU 0x40010658 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG25 +CYDEV_UCFG_B0_P3_U0_CFG25 EQU 0x40010659 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG26 +CYDEV_UCFG_B0_P3_U0_CFG26 EQU 0x4001065a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG27 +CYDEV_UCFG_B0_P3_U0_CFG27 EQU 0x4001065b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG28 +CYDEV_UCFG_B0_P3_U0_CFG28 EQU 0x4001065c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG29 +CYDEV_UCFG_B0_P3_U0_CFG29 EQU 0x4001065d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG30 +CYDEV_UCFG_B0_P3_U0_CFG30 EQU 0x4001065e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG31 +CYDEV_UCFG_B0_P3_U0_CFG31 EQU 0x4001065f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG0 +CYDEV_UCFG_B0_P3_U0_DCFG0 EQU 0x40010660 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG1 +CYDEV_UCFG_B0_P3_U0_DCFG1 EQU 0x40010662 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG2 +CYDEV_UCFG_B0_P3_U0_DCFG2 EQU 0x40010664 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG3 +CYDEV_UCFG_B0_P3_U0_DCFG3 EQU 0x40010666 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG4 +CYDEV_UCFG_B0_P3_U0_DCFG4 EQU 0x40010668 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG5 +CYDEV_UCFG_B0_P3_U0_DCFG5 EQU 0x4001066a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG6 +CYDEV_UCFG_B0_P3_U0_DCFG6 EQU 0x4001066c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG7 +CYDEV_UCFG_B0_P3_U0_DCFG7 EQU 0x4001066e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE +CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE +CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT0 +CYDEV_UCFG_B0_P3_U1_PLD_IT0 EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT1 +CYDEV_UCFG_B0_P3_U1_PLD_IT1 EQU 0x40010684 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT2 +CYDEV_UCFG_B0_P3_U1_PLD_IT2 EQU 0x40010688 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT3 +CYDEV_UCFG_B0_P3_U1_PLD_IT3 EQU 0x4001068c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT4 +CYDEV_UCFG_B0_P3_U1_PLD_IT4 EQU 0x40010690 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT5 +CYDEV_UCFG_B0_P3_U1_PLD_IT5 EQU 0x40010694 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT6 +CYDEV_UCFG_B0_P3_U1_PLD_IT6 EQU 0x40010698 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT7 +CYDEV_UCFG_B0_P3_U1_PLD_IT7 EQU 0x4001069c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT8 +CYDEV_UCFG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT9 +CYDEV_UCFG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT10 +CYDEV_UCFG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT11 +CYDEV_UCFG_B0_P3_U1_PLD_IT11 EQU 0x400106ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT0 +CYDEV_UCFG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT1 +CYDEV_UCFG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT2 +CYDEV_UCFG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT3 +CYDEV_UCFG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG0 +CYDEV_UCFG_B0_P3_U1_CFG0 EQU 0x400106c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG1 +CYDEV_UCFG_B0_P3_U1_CFG1 EQU 0x400106c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG2 +CYDEV_UCFG_B0_P3_U1_CFG2 EQU 0x400106c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG3 +CYDEV_UCFG_B0_P3_U1_CFG3 EQU 0x400106c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG4 +CYDEV_UCFG_B0_P3_U1_CFG4 EQU 0x400106c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG5 +CYDEV_UCFG_B0_P3_U1_CFG5 EQU 0x400106c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG6 +CYDEV_UCFG_B0_P3_U1_CFG6 EQU 0x400106c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG7 +CYDEV_UCFG_B0_P3_U1_CFG7 EQU 0x400106c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG8 +CYDEV_UCFG_B0_P3_U1_CFG8 EQU 0x400106c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG9 +CYDEV_UCFG_B0_P3_U1_CFG9 EQU 0x400106c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG10 +CYDEV_UCFG_B0_P3_U1_CFG10 EQU 0x400106ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG11 +CYDEV_UCFG_B0_P3_U1_CFG11 EQU 0x400106cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG12 +CYDEV_UCFG_B0_P3_U1_CFG12 EQU 0x400106cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG13 +CYDEV_UCFG_B0_P3_U1_CFG13 EQU 0x400106cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG14 +CYDEV_UCFG_B0_P3_U1_CFG14 EQU 0x400106ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG15 +CYDEV_UCFG_B0_P3_U1_CFG15 EQU 0x400106cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG16 +CYDEV_UCFG_B0_P3_U1_CFG16 EQU 0x400106d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG17 +CYDEV_UCFG_B0_P3_U1_CFG17 EQU 0x400106d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG18 +CYDEV_UCFG_B0_P3_U1_CFG18 EQU 0x400106d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG19 +CYDEV_UCFG_B0_P3_U1_CFG19 EQU 0x400106d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG20 +CYDEV_UCFG_B0_P3_U1_CFG20 EQU 0x400106d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG21 +CYDEV_UCFG_B0_P3_U1_CFG21 EQU 0x400106d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG22 +CYDEV_UCFG_B0_P3_U1_CFG22 EQU 0x400106d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG23 +CYDEV_UCFG_B0_P3_U1_CFG23 EQU 0x400106d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG24 +CYDEV_UCFG_B0_P3_U1_CFG24 EQU 0x400106d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG25 +CYDEV_UCFG_B0_P3_U1_CFG25 EQU 0x400106d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG26 +CYDEV_UCFG_B0_P3_U1_CFG26 EQU 0x400106da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG27 +CYDEV_UCFG_B0_P3_U1_CFG27 EQU 0x400106db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG28 +CYDEV_UCFG_B0_P3_U1_CFG28 EQU 0x400106dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG29 +CYDEV_UCFG_B0_P3_U1_CFG29 EQU 0x400106dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG30 +CYDEV_UCFG_B0_P3_U1_CFG30 EQU 0x400106de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG31 +CYDEV_UCFG_B0_P3_U1_CFG31 EQU 0x400106df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG0 +CYDEV_UCFG_B0_P3_U1_DCFG0 EQU 0x400106e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG1 +CYDEV_UCFG_B0_P3_U1_DCFG1 EQU 0x400106e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG2 +CYDEV_UCFG_B0_P3_U1_DCFG2 EQU 0x400106e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG3 +CYDEV_UCFG_B0_P3_U1_DCFG3 EQU 0x400106e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG4 +CYDEV_UCFG_B0_P3_U1_DCFG4 EQU 0x400106e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG5 +CYDEV_UCFG_B0_P3_U1_DCFG5 EQU 0x400106ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG6 +CYDEV_UCFG_B0_P3_U1_DCFG6 EQU 0x400106ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG7 +CYDEV_UCFG_B0_P3_U1_DCFG7 EQU 0x400106ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE +CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE +CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE +CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE +CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE +CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE +CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT0 +CYDEV_UCFG_B0_P4_U0_PLD_IT0 EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT1 +CYDEV_UCFG_B0_P4_U0_PLD_IT1 EQU 0x40010804 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT2 +CYDEV_UCFG_B0_P4_U0_PLD_IT2 EQU 0x40010808 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT3 +CYDEV_UCFG_B0_P4_U0_PLD_IT3 EQU 0x4001080c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT4 +CYDEV_UCFG_B0_P4_U0_PLD_IT4 EQU 0x40010810 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT5 +CYDEV_UCFG_B0_P4_U0_PLD_IT5 EQU 0x40010814 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT6 +CYDEV_UCFG_B0_P4_U0_PLD_IT6 EQU 0x40010818 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT7 +CYDEV_UCFG_B0_P4_U0_PLD_IT7 EQU 0x4001081c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT8 +CYDEV_UCFG_B0_P4_U0_PLD_IT8 EQU 0x40010820 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT9 +CYDEV_UCFG_B0_P4_U0_PLD_IT9 EQU 0x40010824 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT10 +CYDEV_UCFG_B0_P4_U0_PLD_IT10 EQU 0x40010828 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT11 +CYDEV_UCFG_B0_P4_U0_PLD_IT11 EQU 0x4001082c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT0 +CYDEV_UCFG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT1 +CYDEV_UCFG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT2 +CYDEV_UCFG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT3 +CYDEV_UCFG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG0 +CYDEV_UCFG_B0_P4_U0_CFG0 EQU 0x40010840 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG1 +CYDEV_UCFG_B0_P4_U0_CFG1 EQU 0x40010841 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG2 +CYDEV_UCFG_B0_P4_U0_CFG2 EQU 0x40010842 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG3 +CYDEV_UCFG_B0_P4_U0_CFG3 EQU 0x40010843 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG4 +CYDEV_UCFG_B0_P4_U0_CFG4 EQU 0x40010844 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG5 +CYDEV_UCFG_B0_P4_U0_CFG5 EQU 0x40010845 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG6 +CYDEV_UCFG_B0_P4_U0_CFG6 EQU 0x40010846 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG7 +CYDEV_UCFG_B0_P4_U0_CFG7 EQU 0x40010847 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG8 +CYDEV_UCFG_B0_P4_U0_CFG8 EQU 0x40010848 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG9 +CYDEV_UCFG_B0_P4_U0_CFG9 EQU 0x40010849 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG10 +CYDEV_UCFG_B0_P4_U0_CFG10 EQU 0x4001084a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG11 +CYDEV_UCFG_B0_P4_U0_CFG11 EQU 0x4001084b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG12 +CYDEV_UCFG_B0_P4_U0_CFG12 EQU 0x4001084c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG13 +CYDEV_UCFG_B0_P4_U0_CFG13 EQU 0x4001084d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG14 +CYDEV_UCFG_B0_P4_U0_CFG14 EQU 0x4001084e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG15 +CYDEV_UCFG_B0_P4_U0_CFG15 EQU 0x4001084f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG16 +CYDEV_UCFG_B0_P4_U0_CFG16 EQU 0x40010850 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG17 +CYDEV_UCFG_B0_P4_U0_CFG17 EQU 0x40010851 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG18 +CYDEV_UCFG_B0_P4_U0_CFG18 EQU 0x40010852 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG19 +CYDEV_UCFG_B0_P4_U0_CFG19 EQU 0x40010853 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG20 +CYDEV_UCFG_B0_P4_U0_CFG20 EQU 0x40010854 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG21 +CYDEV_UCFG_B0_P4_U0_CFG21 EQU 0x40010855 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG22 +CYDEV_UCFG_B0_P4_U0_CFG22 EQU 0x40010856 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG23 +CYDEV_UCFG_B0_P4_U0_CFG23 EQU 0x40010857 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG24 +CYDEV_UCFG_B0_P4_U0_CFG24 EQU 0x40010858 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG25 +CYDEV_UCFG_B0_P4_U0_CFG25 EQU 0x40010859 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG26 +CYDEV_UCFG_B0_P4_U0_CFG26 EQU 0x4001085a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG27 +CYDEV_UCFG_B0_P4_U0_CFG27 EQU 0x4001085b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG28 +CYDEV_UCFG_B0_P4_U0_CFG28 EQU 0x4001085c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG29 +CYDEV_UCFG_B0_P4_U0_CFG29 EQU 0x4001085d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG30 +CYDEV_UCFG_B0_P4_U0_CFG30 EQU 0x4001085e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG31 +CYDEV_UCFG_B0_P4_U0_CFG31 EQU 0x4001085f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG0 +CYDEV_UCFG_B0_P4_U0_DCFG0 EQU 0x40010860 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG1 +CYDEV_UCFG_B0_P4_U0_DCFG1 EQU 0x40010862 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG2 +CYDEV_UCFG_B0_P4_U0_DCFG2 EQU 0x40010864 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG3 +CYDEV_UCFG_B0_P4_U0_DCFG3 EQU 0x40010866 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG4 +CYDEV_UCFG_B0_P4_U0_DCFG4 EQU 0x40010868 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG5 +CYDEV_UCFG_B0_P4_U0_DCFG5 EQU 0x4001086a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG6 +CYDEV_UCFG_B0_P4_U0_DCFG6 EQU 0x4001086c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG7 +CYDEV_UCFG_B0_P4_U0_DCFG7 EQU 0x4001086e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE +CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE +CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT0 +CYDEV_UCFG_B0_P4_U1_PLD_IT0 EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT1 +CYDEV_UCFG_B0_P4_U1_PLD_IT1 EQU 0x40010884 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT2 +CYDEV_UCFG_B0_P4_U1_PLD_IT2 EQU 0x40010888 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT3 +CYDEV_UCFG_B0_P4_U1_PLD_IT3 EQU 0x4001088c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT4 +CYDEV_UCFG_B0_P4_U1_PLD_IT4 EQU 0x40010890 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT5 +CYDEV_UCFG_B0_P4_U1_PLD_IT5 EQU 0x40010894 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT6 +CYDEV_UCFG_B0_P4_U1_PLD_IT6 EQU 0x40010898 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT7 +CYDEV_UCFG_B0_P4_U1_PLD_IT7 EQU 0x4001089c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT8 +CYDEV_UCFG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT9 +CYDEV_UCFG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT10 +CYDEV_UCFG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT11 +CYDEV_UCFG_B0_P4_U1_PLD_IT11 EQU 0x400108ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT0 +CYDEV_UCFG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT1 +CYDEV_UCFG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT2 +CYDEV_UCFG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT3 +CYDEV_UCFG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG0 +CYDEV_UCFG_B0_P4_U1_CFG0 EQU 0x400108c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG1 +CYDEV_UCFG_B0_P4_U1_CFG1 EQU 0x400108c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG2 +CYDEV_UCFG_B0_P4_U1_CFG2 EQU 0x400108c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG3 +CYDEV_UCFG_B0_P4_U1_CFG3 EQU 0x400108c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG4 +CYDEV_UCFG_B0_P4_U1_CFG4 EQU 0x400108c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG5 +CYDEV_UCFG_B0_P4_U1_CFG5 EQU 0x400108c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG6 +CYDEV_UCFG_B0_P4_U1_CFG6 EQU 0x400108c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG7 +CYDEV_UCFG_B0_P4_U1_CFG7 EQU 0x400108c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG8 +CYDEV_UCFG_B0_P4_U1_CFG8 EQU 0x400108c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG9 +CYDEV_UCFG_B0_P4_U1_CFG9 EQU 0x400108c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG10 +CYDEV_UCFG_B0_P4_U1_CFG10 EQU 0x400108ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG11 +CYDEV_UCFG_B0_P4_U1_CFG11 EQU 0x400108cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG12 +CYDEV_UCFG_B0_P4_U1_CFG12 EQU 0x400108cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG13 +CYDEV_UCFG_B0_P4_U1_CFG13 EQU 0x400108cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG14 +CYDEV_UCFG_B0_P4_U1_CFG14 EQU 0x400108ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG15 +CYDEV_UCFG_B0_P4_U1_CFG15 EQU 0x400108cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG16 +CYDEV_UCFG_B0_P4_U1_CFG16 EQU 0x400108d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG17 +CYDEV_UCFG_B0_P4_U1_CFG17 EQU 0x400108d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG18 +CYDEV_UCFG_B0_P4_U1_CFG18 EQU 0x400108d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG19 +CYDEV_UCFG_B0_P4_U1_CFG19 EQU 0x400108d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG20 +CYDEV_UCFG_B0_P4_U1_CFG20 EQU 0x400108d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG21 +CYDEV_UCFG_B0_P4_U1_CFG21 EQU 0x400108d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG22 +CYDEV_UCFG_B0_P4_U1_CFG22 EQU 0x400108d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG23 +CYDEV_UCFG_B0_P4_U1_CFG23 EQU 0x400108d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG24 +CYDEV_UCFG_B0_P4_U1_CFG24 EQU 0x400108d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG25 +CYDEV_UCFG_B0_P4_U1_CFG25 EQU 0x400108d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG26 +CYDEV_UCFG_B0_P4_U1_CFG26 EQU 0x400108da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG27 +CYDEV_UCFG_B0_P4_U1_CFG27 EQU 0x400108db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG28 +CYDEV_UCFG_B0_P4_U1_CFG28 EQU 0x400108dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG29 +CYDEV_UCFG_B0_P4_U1_CFG29 EQU 0x400108dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG30 +CYDEV_UCFG_B0_P4_U1_CFG30 EQU 0x400108de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG31 +CYDEV_UCFG_B0_P4_U1_CFG31 EQU 0x400108df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG0 +CYDEV_UCFG_B0_P4_U1_DCFG0 EQU 0x400108e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG1 +CYDEV_UCFG_B0_P4_U1_DCFG1 EQU 0x400108e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG2 +CYDEV_UCFG_B0_P4_U1_DCFG2 EQU 0x400108e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG3 +CYDEV_UCFG_B0_P4_U1_DCFG3 EQU 0x400108e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG4 +CYDEV_UCFG_B0_P4_U1_DCFG4 EQU 0x400108e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG5 +CYDEV_UCFG_B0_P4_U1_DCFG5 EQU 0x400108ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG6 +CYDEV_UCFG_B0_P4_U1_DCFG6 EQU 0x400108ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG7 +CYDEV_UCFG_B0_P4_U1_DCFG7 EQU 0x400108ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE +CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE +CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE +CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE +CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE +CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE +CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT0 +CYDEV_UCFG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT1 +CYDEV_UCFG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT2 +CYDEV_UCFG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT3 +CYDEV_UCFG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT4 +CYDEV_UCFG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT5 +CYDEV_UCFG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT6 +CYDEV_UCFG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT7 +CYDEV_UCFG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT8 +CYDEV_UCFG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT9 +CYDEV_UCFG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT10 +CYDEV_UCFG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT11 +CYDEV_UCFG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT0 +CYDEV_UCFG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT1 +CYDEV_UCFG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT2 +CYDEV_UCFG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT3 +CYDEV_UCFG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG0 +CYDEV_UCFG_B0_P5_U0_CFG0 EQU 0x40010a40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG1 +CYDEV_UCFG_B0_P5_U0_CFG1 EQU 0x40010a41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG2 +CYDEV_UCFG_B0_P5_U0_CFG2 EQU 0x40010a42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG3 +CYDEV_UCFG_B0_P5_U0_CFG3 EQU 0x40010a43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG4 +CYDEV_UCFG_B0_P5_U0_CFG4 EQU 0x40010a44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG5 +CYDEV_UCFG_B0_P5_U0_CFG5 EQU 0x40010a45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG6 +CYDEV_UCFG_B0_P5_U0_CFG6 EQU 0x40010a46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG7 +CYDEV_UCFG_B0_P5_U0_CFG7 EQU 0x40010a47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG8 +CYDEV_UCFG_B0_P5_U0_CFG8 EQU 0x40010a48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG9 +CYDEV_UCFG_B0_P5_U0_CFG9 EQU 0x40010a49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG10 +CYDEV_UCFG_B0_P5_U0_CFG10 EQU 0x40010a4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG11 +CYDEV_UCFG_B0_P5_U0_CFG11 EQU 0x40010a4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG12 +CYDEV_UCFG_B0_P5_U0_CFG12 EQU 0x40010a4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG13 +CYDEV_UCFG_B0_P5_U0_CFG13 EQU 0x40010a4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG14 +CYDEV_UCFG_B0_P5_U0_CFG14 EQU 0x40010a4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG15 +CYDEV_UCFG_B0_P5_U0_CFG15 EQU 0x40010a4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG16 +CYDEV_UCFG_B0_P5_U0_CFG16 EQU 0x40010a50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG17 +CYDEV_UCFG_B0_P5_U0_CFG17 EQU 0x40010a51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG18 +CYDEV_UCFG_B0_P5_U0_CFG18 EQU 0x40010a52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG19 +CYDEV_UCFG_B0_P5_U0_CFG19 EQU 0x40010a53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG20 +CYDEV_UCFG_B0_P5_U0_CFG20 EQU 0x40010a54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG21 +CYDEV_UCFG_B0_P5_U0_CFG21 EQU 0x40010a55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG22 +CYDEV_UCFG_B0_P5_U0_CFG22 EQU 0x40010a56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG23 +CYDEV_UCFG_B0_P5_U0_CFG23 EQU 0x40010a57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG24 +CYDEV_UCFG_B0_P5_U0_CFG24 EQU 0x40010a58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG25 +CYDEV_UCFG_B0_P5_U0_CFG25 EQU 0x40010a59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG26 +CYDEV_UCFG_B0_P5_U0_CFG26 EQU 0x40010a5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG27 +CYDEV_UCFG_B0_P5_U0_CFG27 EQU 0x40010a5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG28 +CYDEV_UCFG_B0_P5_U0_CFG28 EQU 0x40010a5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG29 +CYDEV_UCFG_B0_P5_U0_CFG29 EQU 0x40010a5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG30 +CYDEV_UCFG_B0_P5_U0_CFG30 EQU 0x40010a5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG31 +CYDEV_UCFG_B0_P5_U0_CFG31 EQU 0x40010a5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG0 +CYDEV_UCFG_B0_P5_U0_DCFG0 EQU 0x40010a60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG1 +CYDEV_UCFG_B0_P5_U0_DCFG1 EQU 0x40010a62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG2 +CYDEV_UCFG_B0_P5_U0_DCFG2 EQU 0x40010a64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG3 +CYDEV_UCFG_B0_P5_U0_DCFG3 EQU 0x40010a66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG4 +CYDEV_UCFG_B0_P5_U0_DCFG4 EQU 0x40010a68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG5 +CYDEV_UCFG_B0_P5_U0_DCFG5 EQU 0x40010a6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG6 +CYDEV_UCFG_B0_P5_U0_DCFG6 EQU 0x40010a6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG7 +CYDEV_UCFG_B0_P5_U0_DCFG7 EQU 0x40010a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE +CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE +CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT0 +CYDEV_UCFG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT1 +CYDEV_UCFG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT2 +CYDEV_UCFG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT3 +CYDEV_UCFG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT4 +CYDEV_UCFG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT5 +CYDEV_UCFG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT6 +CYDEV_UCFG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT7 +CYDEV_UCFG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT8 +CYDEV_UCFG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT9 +CYDEV_UCFG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT10 +CYDEV_UCFG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT11 +CYDEV_UCFG_B0_P5_U1_PLD_IT11 EQU 0x40010aac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT0 +CYDEV_UCFG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT1 +CYDEV_UCFG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT2 +CYDEV_UCFG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT3 +CYDEV_UCFG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG0 +CYDEV_UCFG_B0_P5_U1_CFG0 EQU 0x40010ac0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG1 +CYDEV_UCFG_B0_P5_U1_CFG1 EQU 0x40010ac1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG2 +CYDEV_UCFG_B0_P5_U1_CFG2 EQU 0x40010ac2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG3 +CYDEV_UCFG_B0_P5_U1_CFG3 EQU 0x40010ac3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG4 +CYDEV_UCFG_B0_P5_U1_CFG4 EQU 0x40010ac4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG5 +CYDEV_UCFG_B0_P5_U1_CFG5 EQU 0x40010ac5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG6 +CYDEV_UCFG_B0_P5_U1_CFG6 EQU 0x40010ac6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG7 +CYDEV_UCFG_B0_P5_U1_CFG7 EQU 0x40010ac7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG8 +CYDEV_UCFG_B0_P5_U1_CFG8 EQU 0x40010ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG9 +CYDEV_UCFG_B0_P5_U1_CFG9 EQU 0x40010ac9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG10 +CYDEV_UCFG_B0_P5_U1_CFG10 EQU 0x40010aca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG11 +CYDEV_UCFG_B0_P5_U1_CFG11 EQU 0x40010acb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG12 +CYDEV_UCFG_B0_P5_U1_CFG12 EQU 0x40010acc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG13 +CYDEV_UCFG_B0_P5_U1_CFG13 EQU 0x40010acd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG14 +CYDEV_UCFG_B0_P5_U1_CFG14 EQU 0x40010ace + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG15 +CYDEV_UCFG_B0_P5_U1_CFG15 EQU 0x40010acf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG16 +CYDEV_UCFG_B0_P5_U1_CFG16 EQU 0x40010ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG17 +CYDEV_UCFG_B0_P5_U1_CFG17 EQU 0x40010ad1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG18 +CYDEV_UCFG_B0_P5_U1_CFG18 EQU 0x40010ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG19 +CYDEV_UCFG_B0_P5_U1_CFG19 EQU 0x40010ad3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG20 +CYDEV_UCFG_B0_P5_U1_CFG20 EQU 0x40010ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG21 +CYDEV_UCFG_B0_P5_U1_CFG21 EQU 0x40010ad5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG22 +CYDEV_UCFG_B0_P5_U1_CFG22 EQU 0x40010ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG23 +CYDEV_UCFG_B0_P5_U1_CFG23 EQU 0x40010ad7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG24 +CYDEV_UCFG_B0_P5_U1_CFG24 EQU 0x40010ad8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG25 +CYDEV_UCFG_B0_P5_U1_CFG25 EQU 0x40010ad9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG26 +CYDEV_UCFG_B0_P5_U1_CFG26 EQU 0x40010ada + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG27 +CYDEV_UCFG_B0_P5_U1_CFG27 EQU 0x40010adb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG28 +CYDEV_UCFG_B0_P5_U1_CFG28 EQU 0x40010adc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG29 +CYDEV_UCFG_B0_P5_U1_CFG29 EQU 0x40010add + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG30 +CYDEV_UCFG_B0_P5_U1_CFG30 EQU 0x40010ade + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG31 +CYDEV_UCFG_B0_P5_U1_CFG31 EQU 0x40010adf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG0 +CYDEV_UCFG_B0_P5_U1_DCFG0 EQU 0x40010ae0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG1 +CYDEV_UCFG_B0_P5_U1_DCFG1 EQU 0x40010ae2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG2 +CYDEV_UCFG_B0_P5_U1_DCFG2 EQU 0x40010ae4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG3 +CYDEV_UCFG_B0_P5_U1_DCFG3 EQU 0x40010ae6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG4 +CYDEV_UCFG_B0_P5_U1_DCFG4 EQU 0x40010ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG5 +CYDEV_UCFG_B0_P5_U1_DCFG5 EQU 0x40010aea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG6 +CYDEV_UCFG_B0_P5_U1_DCFG6 EQU 0x40010aec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG7 +CYDEV_UCFG_B0_P5_U1_DCFG7 EQU 0x40010aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE +CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE +CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE +CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE +CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE +CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE +CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT0 +CYDEV_UCFG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT1 +CYDEV_UCFG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT2 +CYDEV_UCFG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT3 +CYDEV_UCFG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT4 +CYDEV_UCFG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT5 +CYDEV_UCFG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT6 +CYDEV_UCFG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT7 +CYDEV_UCFG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT8 +CYDEV_UCFG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT9 +CYDEV_UCFG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT10 +CYDEV_UCFG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT11 +CYDEV_UCFG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT0 +CYDEV_UCFG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT1 +CYDEV_UCFG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT2 +CYDEV_UCFG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT3 +CYDEV_UCFG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG0 +CYDEV_UCFG_B0_P6_U0_CFG0 EQU 0x40010c40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG1 +CYDEV_UCFG_B0_P6_U0_CFG1 EQU 0x40010c41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG2 +CYDEV_UCFG_B0_P6_U0_CFG2 EQU 0x40010c42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG3 +CYDEV_UCFG_B0_P6_U0_CFG3 EQU 0x40010c43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG4 +CYDEV_UCFG_B0_P6_U0_CFG4 EQU 0x40010c44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG5 +CYDEV_UCFG_B0_P6_U0_CFG5 EQU 0x40010c45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG6 +CYDEV_UCFG_B0_P6_U0_CFG6 EQU 0x40010c46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG7 +CYDEV_UCFG_B0_P6_U0_CFG7 EQU 0x40010c47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG8 +CYDEV_UCFG_B0_P6_U0_CFG8 EQU 0x40010c48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG9 +CYDEV_UCFG_B0_P6_U0_CFG9 EQU 0x40010c49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG10 +CYDEV_UCFG_B0_P6_U0_CFG10 EQU 0x40010c4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG11 +CYDEV_UCFG_B0_P6_U0_CFG11 EQU 0x40010c4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG12 +CYDEV_UCFG_B0_P6_U0_CFG12 EQU 0x40010c4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG13 +CYDEV_UCFG_B0_P6_U0_CFG13 EQU 0x40010c4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG14 +CYDEV_UCFG_B0_P6_U0_CFG14 EQU 0x40010c4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG15 +CYDEV_UCFG_B0_P6_U0_CFG15 EQU 0x40010c4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG16 +CYDEV_UCFG_B0_P6_U0_CFG16 EQU 0x40010c50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG17 +CYDEV_UCFG_B0_P6_U0_CFG17 EQU 0x40010c51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG18 +CYDEV_UCFG_B0_P6_U0_CFG18 EQU 0x40010c52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG19 +CYDEV_UCFG_B0_P6_U0_CFG19 EQU 0x40010c53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG20 +CYDEV_UCFG_B0_P6_U0_CFG20 EQU 0x40010c54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG21 +CYDEV_UCFG_B0_P6_U0_CFG21 EQU 0x40010c55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG22 +CYDEV_UCFG_B0_P6_U0_CFG22 EQU 0x40010c56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG23 +CYDEV_UCFG_B0_P6_U0_CFG23 EQU 0x40010c57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG24 +CYDEV_UCFG_B0_P6_U0_CFG24 EQU 0x40010c58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG25 +CYDEV_UCFG_B0_P6_U0_CFG25 EQU 0x40010c59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG26 +CYDEV_UCFG_B0_P6_U0_CFG26 EQU 0x40010c5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG27 +CYDEV_UCFG_B0_P6_U0_CFG27 EQU 0x40010c5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG28 +CYDEV_UCFG_B0_P6_U0_CFG28 EQU 0x40010c5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG29 +CYDEV_UCFG_B0_P6_U0_CFG29 EQU 0x40010c5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG30 +CYDEV_UCFG_B0_P6_U0_CFG30 EQU 0x40010c5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG31 +CYDEV_UCFG_B0_P6_U0_CFG31 EQU 0x40010c5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG0 +CYDEV_UCFG_B0_P6_U0_DCFG0 EQU 0x40010c60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG1 +CYDEV_UCFG_B0_P6_U0_DCFG1 EQU 0x40010c62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG2 +CYDEV_UCFG_B0_P6_U0_DCFG2 EQU 0x40010c64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG3 +CYDEV_UCFG_B0_P6_U0_DCFG3 EQU 0x40010c66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG4 +CYDEV_UCFG_B0_P6_U0_DCFG4 EQU 0x40010c68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG5 +CYDEV_UCFG_B0_P6_U0_DCFG5 EQU 0x40010c6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG6 +CYDEV_UCFG_B0_P6_U0_DCFG6 EQU 0x40010c6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG7 +CYDEV_UCFG_B0_P6_U0_DCFG7 EQU 0x40010c6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE +CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE +CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT0 +CYDEV_UCFG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT1 +CYDEV_UCFG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT2 +CYDEV_UCFG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT3 +CYDEV_UCFG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT4 +CYDEV_UCFG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT5 +CYDEV_UCFG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT6 +CYDEV_UCFG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT7 +CYDEV_UCFG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT8 +CYDEV_UCFG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT9 +CYDEV_UCFG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT10 +CYDEV_UCFG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT11 +CYDEV_UCFG_B0_P6_U1_PLD_IT11 EQU 0x40010cac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT0 +CYDEV_UCFG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT1 +CYDEV_UCFG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT2 +CYDEV_UCFG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT3 +CYDEV_UCFG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG0 +CYDEV_UCFG_B0_P6_U1_CFG0 EQU 0x40010cc0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG1 +CYDEV_UCFG_B0_P6_U1_CFG1 EQU 0x40010cc1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG2 +CYDEV_UCFG_B0_P6_U1_CFG2 EQU 0x40010cc2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG3 +CYDEV_UCFG_B0_P6_U1_CFG3 EQU 0x40010cc3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG4 +CYDEV_UCFG_B0_P6_U1_CFG4 EQU 0x40010cc4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG5 +CYDEV_UCFG_B0_P6_U1_CFG5 EQU 0x40010cc5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG6 +CYDEV_UCFG_B0_P6_U1_CFG6 EQU 0x40010cc6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG7 +CYDEV_UCFG_B0_P6_U1_CFG7 EQU 0x40010cc7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG8 +CYDEV_UCFG_B0_P6_U1_CFG8 EQU 0x40010cc8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG9 +CYDEV_UCFG_B0_P6_U1_CFG9 EQU 0x40010cc9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG10 +CYDEV_UCFG_B0_P6_U1_CFG10 EQU 0x40010cca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG11 +CYDEV_UCFG_B0_P6_U1_CFG11 EQU 0x40010ccb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG12 +CYDEV_UCFG_B0_P6_U1_CFG12 EQU 0x40010ccc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG13 +CYDEV_UCFG_B0_P6_U1_CFG13 EQU 0x40010ccd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG14 +CYDEV_UCFG_B0_P6_U1_CFG14 EQU 0x40010cce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG15 +CYDEV_UCFG_B0_P6_U1_CFG15 EQU 0x40010ccf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG16 +CYDEV_UCFG_B0_P6_U1_CFG16 EQU 0x40010cd0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG17 +CYDEV_UCFG_B0_P6_U1_CFG17 EQU 0x40010cd1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG18 +CYDEV_UCFG_B0_P6_U1_CFG18 EQU 0x40010cd2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG19 +CYDEV_UCFG_B0_P6_U1_CFG19 EQU 0x40010cd3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG20 +CYDEV_UCFG_B0_P6_U1_CFG20 EQU 0x40010cd4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG21 +CYDEV_UCFG_B0_P6_U1_CFG21 EQU 0x40010cd5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG22 +CYDEV_UCFG_B0_P6_U1_CFG22 EQU 0x40010cd6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG23 +CYDEV_UCFG_B0_P6_U1_CFG23 EQU 0x40010cd7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG24 +CYDEV_UCFG_B0_P6_U1_CFG24 EQU 0x40010cd8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG25 +CYDEV_UCFG_B0_P6_U1_CFG25 EQU 0x40010cd9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG26 +CYDEV_UCFG_B0_P6_U1_CFG26 EQU 0x40010cda + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG27 +CYDEV_UCFG_B0_P6_U1_CFG27 EQU 0x40010cdb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG28 +CYDEV_UCFG_B0_P6_U1_CFG28 EQU 0x40010cdc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG29 +CYDEV_UCFG_B0_P6_U1_CFG29 EQU 0x40010cdd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG30 +CYDEV_UCFG_B0_P6_U1_CFG30 EQU 0x40010cde + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG31 +CYDEV_UCFG_B0_P6_U1_CFG31 EQU 0x40010cdf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG0 +CYDEV_UCFG_B0_P6_U1_DCFG0 EQU 0x40010ce0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG1 +CYDEV_UCFG_B0_P6_U1_DCFG1 EQU 0x40010ce2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG2 +CYDEV_UCFG_B0_P6_U1_DCFG2 EQU 0x40010ce4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG3 +CYDEV_UCFG_B0_P6_U1_DCFG3 EQU 0x40010ce6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG4 +CYDEV_UCFG_B0_P6_U1_DCFG4 EQU 0x40010ce8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG5 +CYDEV_UCFG_B0_P6_U1_DCFG5 EQU 0x40010cea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG6 +CYDEV_UCFG_B0_P6_U1_DCFG6 EQU 0x40010cec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG7 +CYDEV_UCFG_B0_P6_U1_DCFG7 EQU 0x40010cee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE +CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE +CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE +CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE +CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE +CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE +CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT0 +CYDEV_UCFG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT1 +CYDEV_UCFG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT2 +CYDEV_UCFG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT3 +CYDEV_UCFG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT4 +CYDEV_UCFG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT5 +CYDEV_UCFG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT6 +CYDEV_UCFG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT7 +CYDEV_UCFG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT8 +CYDEV_UCFG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT9 +CYDEV_UCFG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT10 +CYDEV_UCFG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT11 +CYDEV_UCFG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT0 +CYDEV_UCFG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT1 +CYDEV_UCFG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT2 +CYDEV_UCFG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT3 +CYDEV_UCFG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG0 +CYDEV_UCFG_B0_P7_U0_CFG0 EQU 0x40010e40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG1 +CYDEV_UCFG_B0_P7_U0_CFG1 EQU 0x40010e41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG2 +CYDEV_UCFG_B0_P7_U0_CFG2 EQU 0x40010e42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG3 +CYDEV_UCFG_B0_P7_U0_CFG3 EQU 0x40010e43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG4 +CYDEV_UCFG_B0_P7_U0_CFG4 EQU 0x40010e44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG5 +CYDEV_UCFG_B0_P7_U0_CFG5 EQU 0x40010e45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG6 +CYDEV_UCFG_B0_P7_U0_CFG6 EQU 0x40010e46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG7 +CYDEV_UCFG_B0_P7_U0_CFG7 EQU 0x40010e47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG8 +CYDEV_UCFG_B0_P7_U0_CFG8 EQU 0x40010e48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG9 +CYDEV_UCFG_B0_P7_U0_CFG9 EQU 0x40010e49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG10 +CYDEV_UCFG_B0_P7_U0_CFG10 EQU 0x40010e4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG11 +CYDEV_UCFG_B0_P7_U0_CFG11 EQU 0x40010e4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG12 +CYDEV_UCFG_B0_P7_U0_CFG12 EQU 0x40010e4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG13 +CYDEV_UCFG_B0_P7_U0_CFG13 EQU 0x40010e4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG14 +CYDEV_UCFG_B0_P7_U0_CFG14 EQU 0x40010e4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG15 +CYDEV_UCFG_B0_P7_U0_CFG15 EQU 0x40010e4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG16 +CYDEV_UCFG_B0_P7_U0_CFG16 EQU 0x40010e50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG17 +CYDEV_UCFG_B0_P7_U0_CFG17 EQU 0x40010e51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG18 +CYDEV_UCFG_B0_P7_U0_CFG18 EQU 0x40010e52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG19 +CYDEV_UCFG_B0_P7_U0_CFG19 EQU 0x40010e53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG20 +CYDEV_UCFG_B0_P7_U0_CFG20 EQU 0x40010e54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG21 +CYDEV_UCFG_B0_P7_U0_CFG21 EQU 0x40010e55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG22 +CYDEV_UCFG_B0_P7_U0_CFG22 EQU 0x40010e56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG23 +CYDEV_UCFG_B0_P7_U0_CFG23 EQU 0x40010e57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG24 +CYDEV_UCFG_B0_P7_U0_CFG24 EQU 0x40010e58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG25 +CYDEV_UCFG_B0_P7_U0_CFG25 EQU 0x40010e59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG26 +CYDEV_UCFG_B0_P7_U0_CFG26 EQU 0x40010e5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG27 +CYDEV_UCFG_B0_P7_U0_CFG27 EQU 0x40010e5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG28 +CYDEV_UCFG_B0_P7_U0_CFG28 EQU 0x40010e5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG29 +CYDEV_UCFG_B0_P7_U0_CFG29 EQU 0x40010e5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG30 +CYDEV_UCFG_B0_P7_U0_CFG30 EQU 0x40010e5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG31 +CYDEV_UCFG_B0_P7_U0_CFG31 EQU 0x40010e5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG0 +CYDEV_UCFG_B0_P7_U0_DCFG0 EQU 0x40010e60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG1 +CYDEV_UCFG_B0_P7_U0_DCFG1 EQU 0x40010e62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG2 +CYDEV_UCFG_B0_P7_U0_DCFG2 EQU 0x40010e64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG3 +CYDEV_UCFG_B0_P7_U0_DCFG3 EQU 0x40010e66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG4 +CYDEV_UCFG_B0_P7_U0_DCFG4 EQU 0x40010e68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG5 +CYDEV_UCFG_B0_P7_U0_DCFG5 EQU 0x40010e6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG6 +CYDEV_UCFG_B0_P7_U0_DCFG6 EQU 0x40010e6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG7 +CYDEV_UCFG_B0_P7_U0_DCFG7 EQU 0x40010e6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE +CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE +CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT0 +CYDEV_UCFG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT1 +CYDEV_UCFG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT2 +CYDEV_UCFG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT3 +CYDEV_UCFG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT4 +CYDEV_UCFG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT5 +CYDEV_UCFG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT6 +CYDEV_UCFG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT7 +CYDEV_UCFG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT8 +CYDEV_UCFG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT9 +CYDEV_UCFG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT10 +CYDEV_UCFG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT11 +CYDEV_UCFG_B0_P7_U1_PLD_IT11 EQU 0x40010eac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT0 +CYDEV_UCFG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT1 +CYDEV_UCFG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT2 +CYDEV_UCFG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT3 +CYDEV_UCFG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG0 +CYDEV_UCFG_B0_P7_U1_CFG0 EQU 0x40010ec0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG1 +CYDEV_UCFG_B0_P7_U1_CFG1 EQU 0x40010ec1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG2 +CYDEV_UCFG_B0_P7_U1_CFG2 EQU 0x40010ec2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG3 +CYDEV_UCFG_B0_P7_U1_CFG3 EQU 0x40010ec3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG4 +CYDEV_UCFG_B0_P7_U1_CFG4 EQU 0x40010ec4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG5 +CYDEV_UCFG_B0_P7_U1_CFG5 EQU 0x40010ec5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG6 +CYDEV_UCFG_B0_P7_U1_CFG6 EQU 0x40010ec6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG7 +CYDEV_UCFG_B0_P7_U1_CFG7 EQU 0x40010ec7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG8 +CYDEV_UCFG_B0_P7_U1_CFG8 EQU 0x40010ec8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG9 +CYDEV_UCFG_B0_P7_U1_CFG9 EQU 0x40010ec9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG10 +CYDEV_UCFG_B0_P7_U1_CFG10 EQU 0x40010eca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG11 +CYDEV_UCFG_B0_P7_U1_CFG11 EQU 0x40010ecb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG12 +CYDEV_UCFG_B0_P7_U1_CFG12 EQU 0x40010ecc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG13 +CYDEV_UCFG_B0_P7_U1_CFG13 EQU 0x40010ecd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG14 +CYDEV_UCFG_B0_P7_U1_CFG14 EQU 0x40010ece + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG15 +CYDEV_UCFG_B0_P7_U1_CFG15 EQU 0x40010ecf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG16 +CYDEV_UCFG_B0_P7_U1_CFG16 EQU 0x40010ed0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG17 +CYDEV_UCFG_B0_P7_U1_CFG17 EQU 0x40010ed1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG18 +CYDEV_UCFG_B0_P7_U1_CFG18 EQU 0x40010ed2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG19 +CYDEV_UCFG_B0_P7_U1_CFG19 EQU 0x40010ed3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG20 +CYDEV_UCFG_B0_P7_U1_CFG20 EQU 0x40010ed4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG21 +CYDEV_UCFG_B0_P7_U1_CFG21 EQU 0x40010ed5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG22 +CYDEV_UCFG_B0_P7_U1_CFG22 EQU 0x40010ed6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG23 +CYDEV_UCFG_B0_P7_U1_CFG23 EQU 0x40010ed7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG24 +CYDEV_UCFG_B0_P7_U1_CFG24 EQU 0x40010ed8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG25 +CYDEV_UCFG_B0_P7_U1_CFG25 EQU 0x40010ed9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG26 +CYDEV_UCFG_B0_P7_U1_CFG26 EQU 0x40010eda + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG27 +CYDEV_UCFG_B0_P7_U1_CFG27 EQU 0x40010edb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG28 +CYDEV_UCFG_B0_P7_U1_CFG28 EQU 0x40010edc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG29 +CYDEV_UCFG_B0_P7_U1_CFG29 EQU 0x40010edd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG30 +CYDEV_UCFG_B0_P7_U1_CFG30 EQU 0x40010ede + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG31 +CYDEV_UCFG_B0_P7_U1_CFG31 EQU 0x40010edf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG0 +CYDEV_UCFG_B0_P7_U1_DCFG0 EQU 0x40010ee0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG1 +CYDEV_UCFG_B0_P7_U1_DCFG1 EQU 0x40010ee2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG2 +CYDEV_UCFG_B0_P7_U1_DCFG2 EQU 0x40010ee4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG3 +CYDEV_UCFG_B0_P7_U1_DCFG3 EQU 0x40010ee6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG4 +CYDEV_UCFG_B0_P7_U1_DCFG4 EQU 0x40010ee8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG5 +CYDEV_UCFG_B0_P7_U1_DCFG5 EQU 0x40010eea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG6 +CYDEV_UCFG_B0_P7_U1_DCFG6 EQU 0x40010eec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG7 +CYDEV_UCFG_B0_P7_U1_DCFG7 EQU 0x40010eee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE +CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE +CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_BASE +CYDEV_UCFG_B1_BASE EQU 0x40011000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE +CYDEV_UCFG_B1_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE +CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE +CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE +CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE +CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT0 +CYDEV_UCFG_B1_P2_U0_PLD_IT0 EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT1 +CYDEV_UCFG_B1_P2_U0_PLD_IT1 EQU 0x40011404 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT2 +CYDEV_UCFG_B1_P2_U0_PLD_IT2 EQU 0x40011408 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT3 +CYDEV_UCFG_B1_P2_U0_PLD_IT3 EQU 0x4001140c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT4 +CYDEV_UCFG_B1_P2_U0_PLD_IT4 EQU 0x40011410 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT5 +CYDEV_UCFG_B1_P2_U0_PLD_IT5 EQU 0x40011414 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT6 +CYDEV_UCFG_B1_P2_U0_PLD_IT6 EQU 0x40011418 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT7 +CYDEV_UCFG_B1_P2_U0_PLD_IT7 EQU 0x4001141c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT8 +CYDEV_UCFG_B1_P2_U0_PLD_IT8 EQU 0x40011420 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT9 +CYDEV_UCFG_B1_P2_U0_PLD_IT9 EQU 0x40011424 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT10 +CYDEV_UCFG_B1_P2_U0_PLD_IT10 EQU 0x40011428 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT11 +CYDEV_UCFG_B1_P2_U0_PLD_IT11 EQU 0x4001142c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT0 +CYDEV_UCFG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT1 +CYDEV_UCFG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT2 +CYDEV_UCFG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT3 +CYDEV_UCFG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG0 +CYDEV_UCFG_B1_P2_U0_CFG0 EQU 0x40011440 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG1 +CYDEV_UCFG_B1_P2_U0_CFG1 EQU 0x40011441 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG2 +CYDEV_UCFG_B1_P2_U0_CFG2 EQU 0x40011442 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG3 +CYDEV_UCFG_B1_P2_U0_CFG3 EQU 0x40011443 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG4 +CYDEV_UCFG_B1_P2_U0_CFG4 EQU 0x40011444 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG5 +CYDEV_UCFG_B1_P2_U0_CFG5 EQU 0x40011445 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG6 +CYDEV_UCFG_B1_P2_U0_CFG6 EQU 0x40011446 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG7 +CYDEV_UCFG_B1_P2_U0_CFG7 EQU 0x40011447 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG8 +CYDEV_UCFG_B1_P2_U0_CFG8 EQU 0x40011448 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG9 +CYDEV_UCFG_B1_P2_U0_CFG9 EQU 0x40011449 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG10 +CYDEV_UCFG_B1_P2_U0_CFG10 EQU 0x4001144a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG11 +CYDEV_UCFG_B1_P2_U0_CFG11 EQU 0x4001144b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG12 +CYDEV_UCFG_B1_P2_U0_CFG12 EQU 0x4001144c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG13 +CYDEV_UCFG_B1_P2_U0_CFG13 EQU 0x4001144d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG14 +CYDEV_UCFG_B1_P2_U0_CFG14 EQU 0x4001144e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG15 +CYDEV_UCFG_B1_P2_U0_CFG15 EQU 0x4001144f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG16 +CYDEV_UCFG_B1_P2_U0_CFG16 EQU 0x40011450 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG17 +CYDEV_UCFG_B1_P2_U0_CFG17 EQU 0x40011451 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG18 +CYDEV_UCFG_B1_P2_U0_CFG18 EQU 0x40011452 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG19 +CYDEV_UCFG_B1_P2_U0_CFG19 EQU 0x40011453 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG20 +CYDEV_UCFG_B1_P2_U0_CFG20 EQU 0x40011454 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG21 +CYDEV_UCFG_B1_P2_U0_CFG21 EQU 0x40011455 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG22 +CYDEV_UCFG_B1_P2_U0_CFG22 EQU 0x40011456 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG23 +CYDEV_UCFG_B1_P2_U0_CFG23 EQU 0x40011457 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG24 +CYDEV_UCFG_B1_P2_U0_CFG24 EQU 0x40011458 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG25 +CYDEV_UCFG_B1_P2_U0_CFG25 EQU 0x40011459 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG26 +CYDEV_UCFG_B1_P2_U0_CFG26 EQU 0x4001145a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG27 +CYDEV_UCFG_B1_P2_U0_CFG27 EQU 0x4001145b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG28 +CYDEV_UCFG_B1_P2_U0_CFG28 EQU 0x4001145c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG29 +CYDEV_UCFG_B1_P2_U0_CFG29 EQU 0x4001145d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG30 +CYDEV_UCFG_B1_P2_U0_CFG30 EQU 0x4001145e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG31 +CYDEV_UCFG_B1_P2_U0_CFG31 EQU 0x4001145f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG0 +CYDEV_UCFG_B1_P2_U0_DCFG0 EQU 0x40011460 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG1 +CYDEV_UCFG_B1_P2_U0_DCFG1 EQU 0x40011462 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG2 +CYDEV_UCFG_B1_P2_U0_DCFG2 EQU 0x40011464 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG3 +CYDEV_UCFG_B1_P2_U0_DCFG3 EQU 0x40011466 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG4 +CYDEV_UCFG_B1_P2_U0_DCFG4 EQU 0x40011468 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG5 +CYDEV_UCFG_B1_P2_U0_DCFG5 EQU 0x4001146a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG6 +CYDEV_UCFG_B1_P2_U0_DCFG6 EQU 0x4001146c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG7 +CYDEV_UCFG_B1_P2_U0_DCFG7 EQU 0x4001146e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE +CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE +CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT0 +CYDEV_UCFG_B1_P2_U1_PLD_IT0 EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT1 +CYDEV_UCFG_B1_P2_U1_PLD_IT1 EQU 0x40011484 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT2 +CYDEV_UCFG_B1_P2_U1_PLD_IT2 EQU 0x40011488 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT3 +CYDEV_UCFG_B1_P2_U1_PLD_IT3 EQU 0x4001148c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT4 +CYDEV_UCFG_B1_P2_U1_PLD_IT4 EQU 0x40011490 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT5 +CYDEV_UCFG_B1_P2_U1_PLD_IT5 EQU 0x40011494 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT6 +CYDEV_UCFG_B1_P2_U1_PLD_IT6 EQU 0x40011498 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT7 +CYDEV_UCFG_B1_P2_U1_PLD_IT7 EQU 0x4001149c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT8 +CYDEV_UCFG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT9 +CYDEV_UCFG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT10 +CYDEV_UCFG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT11 +CYDEV_UCFG_B1_P2_U1_PLD_IT11 EQU 0x400114ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT0 +CYDEV_UCFG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT1 +CYDEV_UCFG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT2 +CYDEV_UCFG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT3 +CYDEV_UCFG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG0 +CYDEV_UCFG_B1_P2_U1_CFG0 EQU 0x400114c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG1 +CYDEV_UCFG_B1_P2_U1_CFG1 EQU 0x400114c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG2 +CYDEV_UCFG_B1_P2_U1_CFG2 EQU 0x400114c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG3 +CYDEV_UCFG_B1_P2_U1_CFG3 EQU 0x400114c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG4 +CYDEV_UCFG_B1_P2_U1_CFG4 EQU 0x400114c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG5 +CYDEV_UCFG_B1_P2_U1_CFG5 EQU 0x400114c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG6 +CYDEV_UCFG_B1_P2_U1_CFG6 EQU 0x400114c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG7 +CYDEV_UCFG_B1_P2_U1_CFG7 EQU 0x400114c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG8 +CYDEV_UCFG_B1_P2_U1_CFG8 EQU 0x400114c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG9 +CYDEV_UCFG_B1_P2_U1_CFG9 EQU 0x400114c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG10 +CYDEV_UCFG_B1_P2_U1_CFG10 EQU 0x400114ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG11 +CYDEV_UCFG_B1_P2_U1_CFG11 EQU 0x400114cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG12 +CYDEV_UCFG_B1_P2_U1_CFG12 EQU 0x400114cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG13 +CYDEV_UCFG_B1_P2_U1_CFG13 EQU 0x400114cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG14 +CYDEV_UCFG_B1_P2_U1_CFG14 EQU 0x400114ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG15 +CYDEV_UCFG_B1_P2_U1_CFG15 EQU 0x400114cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG16 +CYDEV_UCFG_B1_P2_U1_CFG16 EQU 0x400114d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG17 +CYDEV_UCFG_B1_P2_U1_CFG17 EQU 0x400114d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG18 +CYDEV_UCFG_B1_P2_U1_CFG18 EQU 0x400114d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG19 +CYDEV_UCFG_B1_P2_U1_CFG19 EQU 0x400114d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG20 +CYDEV_UCFG_B1_P2_U1_CFG20 EQU 0x400114d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG21 +CYDEV_UCFG_B1_P2_U1_CFG21 EQU 0x400114d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG22 +CYDEV_UCFG_B1_P2_U1_CFG22 EQU 0x400114d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG23 +CYDEV_UCFG_B1_P2_U1_CFG23 EQU 0x400114d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG24 +CYDEV_UCFG_B1_P2_U1_CFG24 EQU 0x400114d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG25 +CYDEV_UCFG_B1_P2_U1_CFG25 EQU 0x400114d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG26 +CYDEV_UCFG_B1_P2_U1_CFG26 EQU 0x400114da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG27 +CYDEV_UCFG_B1_P2_U1_CFG27 EQU 0x400114db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG28 +CYDEV_UCFG_B1_P2_U1_CFG28 EQU 0x400114dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG29 +CYDEV_UCFG_B1_P2_U1_CFG29 EQU 0x400114dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG30 +CYDEV_UCFG_B1_P2_U1_CFG30 EQU 0x400114de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG31 +CYDEV_UCFG_B1_P2_U1_CFG31 EQU 0x400114df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG0 +CYDEV_UCFG_B1_P2_U1_DCFG0 EQU 0x400114e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG1 +CYDEV_UCFG_B1_P2_U1_DCFG1 EQU 0x400114e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG2 +CYDEV_UCFG_B1_P2_U1_DCFG2 EQU 0x400114e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG3 +CYDEV_UCFG_B1_P2_U1_DCFG3 EQU 0x400114e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG4 +CYDEV_UCFG_B1_P2_U1_DCFG4 EQU 0x400114e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG5 +CYDEV_UCFG_B1_P2_U1_DCFG5 EQU 0x400114ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG6 +CYDEV_UCFG_B1_P2_U1_DCFG6 EQU 0x400114ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG7 +CYDEV_UCFG_B1_P2_U1_DCFG7 EQU 0x400114ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE +CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE +CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE +CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE +CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE +CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE +CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT0 +CYDEV_UCFG_B1_P3_U0_PLD_IT0 EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT1 +CYDEV_UCFG_B1_P3_U0_PLD_IT1 EQU 0x40011604 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT2 +CYDEV_UCFG_B1_P3_U0_PLD_IT2 EQU 0x40011608 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT3 +CYDEV_UCFG_B1_P3_U0_PLD_IT3 EQU 0x4001160c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT4 +CYDEV_UCFG_B1_P3_U0_PLD_IT4 EQU 0x40011610 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT5 +CYDEV_UCFG_B1_P3_U0_PLD_IT5 EQU 0x40011614 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT6 +CYDEV_UCFG_B1_P3_U0_PLD_IT6 EQU 0x40011618 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT7 +CYDEV_UCFG_B1_P3_U0_PLD_IT7 EQU 0x4001161c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT8 +CYDEV_UCFG_B1_P3_U0_PLD_IT8 EQU 0x40011620 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT9 +CYDEV_UCFG_B1_P3_U0_PLD_IT9 EQU 0x40011624 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT10 +CYDEV_UCFG_B1_P3_U0_PLD_IT10 EQU 0x40011628 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT11 +CYDEV_UCFG_B1_P3_U0_PLD_IT11 EQU 0x4001162c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT0 +CYDEV_UCFG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT1 +CYDEV_UCFG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT2 +CYDEV_UCFG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT3 +CYDEV_UCFG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG0 +CYDEV_UCFG_B1_P3_U0_CFG0 EQU 0x40011640 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG1 +CYDEV_UCFG_B1_P3_U0_CFG1 EQU 0x40011641 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG2 +CYDEV_UCFG_B1_P3_U0_CFG2 EQU 0x40011642 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG3 +CYDEV_UCFG_B1_P3_U0_CFG3 EQU 0x40011643 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG4 +CYDEV_UCFG_B1_P3_U0_CFG4 EQU 0x40011644 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG5 +CYDEV_UCFG_B1_P3_U0_CFG5 EQU 0x40011645 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG6 +CYDEV_UCFG_B1_P3_U0_CFG6 EQU 0x40011646 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG7 +CYDEV_UCFG_B1_P3_U0_CFG7 EQU 0x40011647 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG8 +CYDEV_UCFG_B1_P3_U0_CFG8 EQU 0x40011648 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG9 +CYDEV_UCFG_B1_P3_U0_CFG9 EQU 0x40011649 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG10 +CYDEV_UCFG_B1_P3_U0_CFG10 EQU 0x4001164a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG11 +CYDEV_UCFG_B1_P3_U0_CFG11 EQU 0x4001164b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG12 +CYDEV_UCFG_B1_P3_U0_CFG12 EQU 0x4001164c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG13 +CYDEV_UCFG_B1_P3_U0_CFG13 EQU 0x4001164d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG14 +CYDEV_UCFG_B1_P3_U0_CFG14 EQU 0x4001164e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG15 +CYDEV_UCFG_B1_P3_U0_CFG15 EQU 0x4001164f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG16 +CYDEV_UCFG_B1_P3_U0_CFG16 EQU 0x40011650 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG17 +CYDEV_UCFG_B1_P3_U0_CFG17 EQU 0x40011651 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG18 +CYDEV_UCFG_B1_P3_U0_CFG18 EQU 0x40011652 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG19 +CYDEV_UCFG_B1_P3_U0_CFG19 EQU 0x40011653 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG20 +CYDEV_UCFG_B1_P3_U0_CFG20 EQU 0x40011654 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG21 +CYDEV_UCFG_B1_P3_U0_CFG21 EQU 0x40011655 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG22 +CYDEV_UCFG_B1_P3_U0_CFG22 EQU 0x40011656 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG23 +CYDEV_UCFG_B1_P3_U0_CFG23 EQU 0x40011657 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG24 +CYDEV_UCFG_B1_P3_U0_CFG24 EQU 0x40011658 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG25 +CYDEV_UCFG_B1_P3_U0_CFG25 EQU 0x40011659 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG26 +CYDEV_UCFG_B1_P3_U0_CFG26 EQU 0x4001165a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG27 +CYDEV_UCFG_B1_P3_U0_CFG27 EQU 0x4001165b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG28 +CYDEV_UCFG_B1_P3_U0_CFG28 EQU 0x4001165c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG29 +CYDEV_UCFG_B1_P3_U0_CFG29 EQU 0x4001165d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG30 +CYDEV_UCFG_B1_P3_U0_CFG30 EQU 0x4001165e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG31 +CYDEV_UCFG_B1_P3_U0_CFG31 EQU 0x4001165f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG0 +CYDEV_UCFG_B1_P3_U0_DCFG0 EQU 0x40011660 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG1 +CYDEV_UCFG_B1_P3_U0_DCFG1 EQU 0x40011662 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG2 +CYDEV_UCFG_B1_P3_U0_DCFG2 EQU 0x40011664 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG3 +CYDEV_UCFG_B1_P3_U0_DCFG3 EQU 0x40011666 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG4 +CYDEV_UCFG_B1_P3_U0_DCFG4 EQU 0x40011668 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG5 +CYDEV_UCFG_B1_P3_U0_DCFG5 EQU 0x4001166a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG6 +CYDEV_UCFG_B1_P3_U0_DCFG6 EQU 0x4001166c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG7 +CYDEV_UCFG_B1_P3_U0_DCFG7 EQU 0x4001166e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE +CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE +CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT0 +CYDEV_UCFG_B1_P3_U1_PLD_IT0 EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT1 +CYDEV_UCFG_B1_P3_U1_PLD_IT1 EQU 0x40011684 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT2 +CYDEV_UCFG_B1_P3_U1_PLD_IT2 EQU 0x40011688 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT3 +CYDEV_UCFG_B1_P3_U1_PLD_IT3 EQU 0x4001168c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT4 +CYDEV_UCFG_B1_P3_U1_PLD_IT4 EQU 0x40011690 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT5 +CYDEV_UCFG_B1_P3_U1_PLD_IT5 EQU 0x40011694 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT6 +CYDEV_UCFG_B1_P3_U1_PLD_IT6 EQU 0x40011698 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT7 +CYDEV_UCFG_B1_P3_U1_PLD_IT7 EQU 0x4001169c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT8 +CYDEV_UCFG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT9 +CYDEV_UCFG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT10 +CYDEV_UCFG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT11 +CYDEV_UCFG_B1_P3_U1_PLD_IT11 EQU 0x400116ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT0 +CYDEV_UCFG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT1 +CYDEV_UCFG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT2 +CYDEV_UCFG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT3 +CYDEV_UCFG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG0 +CYDEV_UCFG_B1_P3_U1_CFG0 EQU 0x400116c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG1 +CYDEV_UCFG_B1_P3_U1_CFG1 EQU 0x400116c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG2 +CYDEV_UCFG_B1_P3_U1_CFG2 EQU 0x400116c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG3 +CYDEV_UCFG_B1_P3_U1_CFG3 EQU 0x400116c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG4 +CYDEV_UCFG_B1_P3_U1_CFG4 EQU 0x400116c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG5 +CYDEV_UCFG_B1_P3_U1_CFG5 EQU 0x400116c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG6 +CYDEV_UCFG_B1_P3_U1_CFG6 EQU 0x400116c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG7 +CYDEV_UCFG_B1_P3_U1_CFG7 EQU 0x400116c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG8 +CYDEV_UCFG_B1_P3_U1_CFG8 EQU 0x400116c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG9 +CYDEV_UCFG_B1_P3_U1_CFG9 EQU 0x400116c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG10 +CYDEV_UCFG_B1_P3_U1_CFG10 EQU 0x400116ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG11 +CYDEV_UCFG_B1_P3_U1_CFG11 EQU 0x400116cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG12 +CYDEV_UCFG_B1_P3_U1_CFG12 EQU 0x400116cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG13 +CYDEV_UCFG_B1_P3_U1_CFG13 EQU 0x400116cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG14 +CYDEV_UCFG_B1_P3_U1_CFG14 EQU 0x400116ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG15 +CYDEV_UCFG_B1_P3_U1_CFG15 EQU 0x400116cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG16 +CYDEV_UCFG_B1_P3_U1_CFG16 EQU 0x400116d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG17 +CYDEV_UCFG_B1_P3_U1_CFG17 EQU 0x400116d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG18 +CYDEV_UCFG_B1_P3_U1_CFG18 EQU 0x400116d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG19 +CYDEV_UCFG_B1_P3_U1_CFG19 EQU 0x400116d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG20 +CYDEV_UCFG_B1_P3_U1_CFG20 EQU 0x400116d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG21 +CYDEV_UCFG_B1_P3_U1_CFG21 EQU 0x400116d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG22 +CYDEV_UCFG_B1_P3_U1_CFG22 EQU 0x400116d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG23 +CYDEV_UCFG_B1_P3_U1_CFG23 EQU 0x400116d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG24 +CYDEV_UCFG_B1_P3_U1_CFG24 EQU 0x400116d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG25 +CYDEV_UCFG_B1_P3_U1_CFG25 EQU 0x400116d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG26 +CYDEV_UCFG_B1_P3_U1_CFG26 EQU 0x400116da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG27 +CYDEV_UCFG_B1_P3_U1_CFG27 EQU 0x400116db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG28 +CYDEV_UCFG_B1_P3_U1_CFG28 EQU 0x400116dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG29 +CYDEV_UCFG_B1_P3_U1_CFG29 EQU 0x400116dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG30 +CYDEV_UCFG_B1_P3_U1_CFG30 EQU 0x400116de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG31 +CYDEV_UCFG_B1_P3_U1_CFG31 EQU 0x400116df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG0 +CYDEV_UCFG_B1_P3_U1_DCFG0 EQU 0x400116e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG1 +CYDEV_UCFG_B1_P3_U1_DCFG1 EQU 0x400116e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG2 +CYDEV_UCFG_B1_P3_U1_DCFG2 EQU 0x400116e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG3 +CYDEV_UCFG_B1_P3_U1_DCFG3 EQU 0x400116e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG4 +CYDEV_UCFG_B1_P3_U1_DCFG4 EQU 0x400116e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG5 +CYDEV_UCFG_B1_P3_U1_DCFG5 EQU 0x400116ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG6 +CYDEV_UCFG_B1_P3_U1_DCFG6 EQU 0x400116ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG7 +CYDEV_UCFG_B1_P3_U1_DCFG7 EQU 0x400116ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE +CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE +CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE +CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE +CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE +CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE +CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT0 +CYDEV_UCFG_B1_P4_U0_PLD_IT0 EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT1 +CYDEV_UCFG_B1_P4_U0_PLD_IT1 EQU 0x40011804 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT2 +CYDEV_UCFG_B1_P4_U0_PLD_IT2 EQU 0x40011808 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT3 +CYDEV_UCFG_B1_P4_U0_PLD_IT3 EQU 0x4001180c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT4 +CYDEV_UCFG_B1_P4_U0_PLD_IT4 EQU 0x40011810 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT5 +CYDEV_UCFG_B1_P4_U0_PLD_IT5 EQU 0x40011814 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT6 +CYDEV_UCFG_B1_P4_U0_PLD_IT6 EQU 0x40011818 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT7 +CYDEV_UCFG_B1_P4_U0_PLD_IT7 EQU 0x4001181c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT8 +CYDEV_UCFG_B1_P4_U0_PLD_IT8 EQU 0x40011820 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT9 +CYDEV_UCFG_B1_P4_U0_PLD_IT9 EQU 0x40011824 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT10 +CYDEV_UCFG_B1_P4_U0_PLD_IT10 EQU 0x40011828 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT11 +CYDEV_UCFG_B1_P4_U0_PLD_IT11 EQU 0x4001182c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT0 +CYDEV_UCFG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT1 +CYDEV_UCFG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT2 +CYDEV_UCFG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT3 +CYDEV_UCFG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG0 +CYDEV_UCFG_B1_P4_U0_CFG0 EQU 0x40011840 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG1 +CYDEV_UCFG_B1_P4_U0_CFG1 EQU 0x40011841 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG2 +CYDEV_UCFG_B1_P4_U0_CFG2 EQU 0x40011842 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG3 +CYDEV_UCFG_B1_P4_U0_CFG3 EQU 0x40011843 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG4 +CYDEV_UCFG_B1_P4_U0_CFG4 EQU 0x40011844 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG5 +CYDEV_UCFG_B1_P4_U0_CFG5 EQU 0x40011845 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG6 +CYDEV_UCFG_B1_P4_U0_CFG6 EQU 0x40011846 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG7 +CYDEV_UCFG_B1_P4_U0_CFG7 EQU 0x40011847 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG8 +CYDEV_UCFG_B1_P4_U0_CFG8 EQU 0x40011848 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG9 +CYDEV_UCFG_B1_P4_U0_CFG9 EQU 0x40011849 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG10 +CYDEV_UCFG_B1_P4_U0_CFG10 EQU 0x4001184a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG11 +CYDEV_UCFG_B1_P4_U0_CFG11 EQU 0x4001184b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG12 +CYDEV_UCFG_B1_P4_U0_CFG12 EQU 0x4001184c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG13 +CYDEV_UCFG_B1_P4_U0_CFG13 EQU 0x4001184d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG14 +CYDEV_UCFG_B1_P4_U0_CFG14 EQU 0x4001184e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG15 +CYDEV_UCFG_B1_P4_U0_CFG15 EQU 0x4001184f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG16 +CYDEV_UCFG_B1_P4_U0_CFG16 EQU 0x40011850 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG17 +CYDEV_UCFG_B1_P4_U0_CFG17 EQU 0x40011851 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG18 +CYDEV_UCFG_B1_P4_U0_CFG18 EQU 0x40011852 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG19 +CYDEV_UCFG_B1_P4_U0_CFG19 EQU 0x40011853 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG20 +CYDEV_UCFG_B1_P4_U0_CFG20 EQU 0x40011854 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG21 +CYDEV_UCFG_B1_P4_U0_CFG21 EQU 0x40011855 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG22 +CYDEV_UCFG_B1_P4_U0_CFG22 EQU 0x40011856 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG23 +CYDEV_UCFG_B1_P4_U0_CFG23 EQU 0x40011857 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG24 +CYDEV_UCFG_B1_P4_U0_CFG24 EQU 0x40011858 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG25 +CYDEV_UCFG_B1_P4_U0_CFG25 EQU 0x40011859 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG26 +CYDEV_UCFG_B1_P4_U0_CFG26 EQU 0x4001185a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG27 +CYDEV_UCFG_B1_P4_U0_CFG27 EQU 0x4001185b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG28 +CYDEV_UCFG_B1_P4_U0_CFG28 EQU 0x4001185c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG29 +CYDEV_UCFG_B1_P4_U0_CFG29 EQU 0x4001185d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG30 +CYDEV_UCFG_B1_P4_U0_CFG30 EQU 0x4001185e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG31 +CYDEV_UCFG_B1_P4_U0_CFG31 EQU 0x4001185f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG0 +CYDEV_UCFG_B1_P4_U0_DCFG0 EQU 0x40011860 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG1 +CYDEV_UCFG_B1_P4_U0_DCFG1 EQU 0x40011862 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG2 +CYDEV_UCFG_B1_P4_U0_DCFG2 EQU 0x40011864 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG3 +CYDEV_UCFG_B1_P4_U0_DCFG3 EQU 0x40011866 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG4 +CYDEV_UCFG_B1_P4_U0_DCFG4 EQU 0x40011868 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG5 +CYDEV_UCFG_B1_P4_U0_DCFG5 EQU 0x4001186a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG6 +CYDEV_UCFG_B1_P4_U0_DCFG6 EQU 0x4001186c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG7 +CYDEV_UCFG_B1_P4_U0_DCFG7 EQU 0x4001186e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE +CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE +CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT0 +CYDEV_UCFG_B1_P4_U1_PLD_IT0 EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT1 +CYDEV_UCFG_B1_P4_U1_PLD_IT1 EQU 0x40011884 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT2 +CYDEV_UCFG_B1_P4_U1_PLD_IT2 EQU 0x40011888 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT3 +CYDEV_UCFG_B1_P4_U1_PLD_IT3 EQU 0x4001188c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT4 +CYDEV_UCFG_B1_P4_U1_PLD_IT4 EQU 0x40011890 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT5 +CYDEV_UCFG_B1_P4_U1_PLD_IT5 EQU 0x40011894 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT6 +CYDEV_UCFG_B1_P4_U1_PLD_IT6 EQU 0x40011898 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT7 +CYDEV_UCFG_B1_P4_U1_PLD_IT7 EQU 0x4001189c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT8 +CYDEV_UCFG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT9 +CYDEV_UCFG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT10 +CYDEV_UCFG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT11 +CYDEV_UCFG_B1_P4_U1_PLD_IT11 EQU 0x400118ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT0 +CYDEV_UCFG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT1 +CYDEV_UCFG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT2 +CYDEV_UCFG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT3 +CYDEV_UCFG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG0 +CYDEV_UCFG_B1_P4_U1_CFG0 EQU 0x400118c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG1 +CYDEV_UCFG_B1_P4_U1_CFG1 EQU 0x400118c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG2 +CYDEV_UCFG_B1_P4_U1_CFG2 EQU 0x400118c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG3 +CYDEV_UCFG_B1_P4_U1_CFG3 EQU 0x400118c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG4 +CYDEV_UCFG_B1_P4_U1_CFG4 EQU 0x400118c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG5 +CYDEV_UCFG_B1_P4_U1_CFG5 EQU 0x400118c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG6 +CYDEV_UCFG_B1_P4_U1_CFG6 EQU 0x400118c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG7 +CYDEV_UCFG_B1_P4_U1_CFG7 EQU 0x400118c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG8 +CYDEV_UCFG_B1_P4_U1_CFG8 EQU 0x400118c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG9 +CYDEV_UCFG_B1_P4_U1_CFG9 EQU 0x400118c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG10 +CYDEV_UCFG_B1_P4_U1_CFG10 EQU 0x400118ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG11 +CYDEV_UCFG_B1_P4_U1_CFG11 EQU 0x400118cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG12 +CYDEV_UCFG_B1_P4_U1_CFG12 EQU 0x400118cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG13 +CYDEV_UCFG_B1_P4_U1_CFG13 EQU 0x400118cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG14 +CYDEV_UCFG_B1_P4_U1_CFG14 EQU 0x400118ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG15 +CYDEV_UCFG_B1_P4_U1_CFG15 EQU 0x400118cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG16 +CYDEV_UCFG_B1_P4_U1_CFG16 EQU 0x400118d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG17 +CYDEV_UCFG_B1_P4_U1_CFG17 EQU 0x400118d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG18 +CYDEV_UCFG_B1_P4_U1_CFG18 EQU 0x400118d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG19 +CYDEV_UCFG_B1_P4_U1_CFG19 EQU 0x400118d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG20 +CYDEV_UCFG_B1_P4_U1_CFG20 EQU 0x400118d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG21 +CYDEV_UCFG_B1_P4_U1_CFG21 EQU 0x400118d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG22 +CYDEV_UCFG_B1_P4_U1_CFG22 EQU 0x400118d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG23 +CYDEV_UCFG_B1_P4_U1_CFG23 EQU 0x400118d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG24 +CYDEV_UCFG_B1_P4_U1_CFG24 EQU 0x400118d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG25 +CYDEV_UCFG_B1_P4_U1_CFG25 EQU 0x400118d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG26 +CYDEV_UCFG_B1_P4_U1_CFG26 EQU 0x400118da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG27 +CYDEV_UCFG_B1_P4_U1_CFG27 EQU 0x400118db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG28 +CYDEV_UCFG_B1_P4_U1_CFG28 EQU 0x400118dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG29 +CYDEV_UCFG_B1_P4_U1_CFG29 EQU 0x400118dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG30 +CYDEV_UCFG_B1_P4_U1_CFG30 EQU 0x400118de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG31 +CYDEV_UCFG_B1_P4_U1_CFG31 EQU 0x400118df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG0 +CYDEV_UCFG_B1_P4_U1_DCFG0 EQU 0x400118e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG1 +CYDEV_UCFG_B1_P4_U1_DCFG1 EQU 0x400118e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG2 +CYDEV_UCFG_B1_P4_U1_DCFG2 EQU 0x400118e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG3 +CYDEV_UCFG_B1_P4_U1_DCFG3 EQU 0x400118e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG4 +CYDEV_UCFG_B1_P4_U1_DCFG4 EQU 0x400118e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG5 +CYDEV_UCFG_B1_P4_U1_DCFG5 EQU 0x400118ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG6 +CYDEV_UCFG_B1_P4_U1_DCFG6 EQU 0x400118ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG7 +CYDEV_UCFG_B1_P4_U1_DCFG7 EQU 0x400118ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE +CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE +CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE +CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE +CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE +CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE +CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT0 +CYDEV_UCFG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT1 +CYDEV_UCFG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT2 +CYDEV_UCFG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT3 +CYDEV_UCFG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT4 +CYDEV_UCFG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT5 +CYDEV_UCFG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT6 +CYDEV_UCFG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT7 +CYDEV_UCFG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT8 +CYDEV_UCFG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT9 +CYDEV_UCFG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT10 +CYDEV_UCFG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT11 +CYDEV_UCFG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT0 +CYDEV_UCFG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT1 +CYDEV_UCFG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT2 +CYDEV_UCFG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT3 +CYDEV_UCFG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG0 +CYDEV_UCFG_B1_P5_U0_CFG0 EQU 0x40011a40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG1 +CYDEV_UCFG_B1_P5_U0_CFG1 EQU 0x40011a41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG2 +CYDEV_UCFG_B1_P5_U0_CFG2 EQU 0x40011a42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG3 +CYDEV_UCFG_B1_P5_U0_CFG3 EQU 0x40011a43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG4 +CYDEV_UCFG_B1_P5_U0_CFG4 EQU 0x40011a44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG5 +CYDEV_UCFG_B1_P5_U0_CFG5 EQU 0x40011a45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG6 +CYDEV_UCFG_B1_P5_U0_CFG6 EQU 0x40011a46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG7 +CYDEV_UCFG_B1_P5_U0_CFG7 EQU 0x40011a47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG8 +CYDEV_UCFG_B1_P5_U0_CFG8 EQU 0x40011a48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG9 +CYDEV_UCFG_B1_P5_U0_CFG9 EQU 0x40011a49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG10 +CYDEV_UCFG_B1_P5_U0_CFG10 EQU 0x40011a4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG11 +CYDEV_UCFG_B1_P5_U0_CFG11 EQU 0x40011a4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG12 +CYDEV_UCFG_B1_P5_U0_CFG12 EQU 0x40011a4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG13 +CYDEV_UCFG_B1_P5_U0_CFG13 EQU 0x40011a4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG14 +CYDEV_UCFG_B1_P5_U0_CFG14 EQU 0x40011a4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG15 +CYDEV_UCFG_B1_P5_U0_CFG15 EQU 0x40011a4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG16 +CYDEV_UCFG_B1_P5_U0_CFG16 EQU 0x40011a50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG17 +CYDEV_UCFG_B1_P5_U0_CFG17 EQU 0x40011a51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG18 +CYDEV_UCFG_B1_P5_U0_CFG18 EQU 0x40011a52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG19 +CYDEV_UCFG_B1_P5_U0_CFG19 EQU 0x40011a53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG20 +CYDEV_UCFG_B1_P5_U0_CFG20 EQU 0x40011a54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG21 +CYDEV_UCFG_B1_P5_U0_CFG21 EQU 0x40011a55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG22 +CYDEV_UCFG_B1_P5_U0_CFG22 EQU 0x40011a56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG23 +CYDEV_UCFG_B1_P5_U0_CFG23 EQU 0x40011a57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG24 +CYDEV_UCFG_B1_P5_U0_CFG24 EQU 0x40011a58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG25 +CYDEV_UCFG_B1_P5_U0_CFG25 EQU 0x40011a59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG26 +CYDEV_UCFG_B1_P5_U0_CFG26 EQU 0x40011a5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG27 +CYDEV_UCFG_B1_P5_U0_CFG27 EQU 0x40011a5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG28 +CYDEV_UCFG_B1_P5_U0_CFG28 EQU 0x40011a5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG29 +CYDEV_UCFG_B1_P5_U0_CFG29 EQU 0x40011a5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG30 +CYDEV_UCFG_B1_P5_U0_CFG30 EQU 0x40011a5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG31 +CYDEV_UCFG_B1_P5_U0_CFG31 EQU 0x40011a5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG0 +CYDEV_UCFG_B1_P5_U0_DCFG0 EQU 0x40011a60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG1 +CYDEV_UCFG_B1_P5_U0_DCFG1 EQU 0x40011a62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG2 +CYDEV_UCFG_B1_P5_U0_DCFG2 EQU 0x40011a64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG3 +CYDEV_UCFG_B1_P5_U0_DCFG3 EQU 0x40011a66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG4 +CYDEV_UCFG_B1_P5_U0_DCFG4 EQU 0x40011a68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG5 +CYDEV_UCFG_B1_P5_U0_DCFG5 EQU 0x40011a6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG6 +CYDEV_UCFG_B1_P5_U0_DCFG6 EQU 0x40011a6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG7 +CYDEV_UCFG_B1_P5_U0_DCFG7 EQU 0x40011a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE +CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE +CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT0 +CYDEV_UCFG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT1 +CYDEV_UCFG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT2 +CYDEV_UCFG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT3 +CYDEV_UCFG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT4 +CYDEV_UCFG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT5 +CYDEV_UCFG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT6 +CYDEV_UCFG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT7 +CYDEV_UCFG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT8 +CYDEV_UCFG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT9 +CYDEV_UCFG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT10 +CYDEV_UCFG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT11 +CYDEV_UCFG_B1_P5_U1_PLD_IT11 EQU 0x40011aac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT0 +CYDEV_UCFG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT1 +CYDEV_UCFG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT2 +CYDEV_UCFG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT3 +CYDEV_UCFG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG0 +CYDEV_UCFG_B1_P5_U1_CFG0 EQU 0x40011ac0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG1 +CYDEV_UCFG_B1_P5_U1_CFG1 EQU 0x40011ac1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG2 +CYDEV_UCFG_B1_P5_U1_CFG2 EQU 0x40011ac2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG3 +CYDEV_UCFG_B1_P5_U1_CFG3 EQU 0x40011ac3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG4 +CYDEV_UCFG_B1_P5_U1_CFG4 EQU 0x40011ac4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG5 +CYDEV_UCFG_B1_P5_U1_CFG5 EQU 0x40011ac5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG6 +CYDEV_UCFG_B1_P5_U1_CFG6 EQU 0x40011ac6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG7 +CYDEV_UCFG_B1_P5_U1_CFG7 EQU 0x40011ac7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG8 +CYDEV_UCFG_B1_P5_U1_CFG8 EQU 0x40011ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG9 +CYDEV_UCFG_B1_P5_U1_CFG9 EQU 0x40011ac9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG10 +CYDEV_UCFG_B1_P5_U1_CFG10 EQU 0x40011aca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG11 +CYDEV_UCFG_B1_P5_U1_CFG11 EQU 0x40011acb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG12 +CYDEV_UCFG_B1_P5_U1_CFG12 EQU 0x40011acc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG13 +CYDEV_UCFG_B1_P5_U1_CFG13 EQU 0x40011acd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG14 +CYDEV_UCFG_B1_P5_U1_CFG14 EQU 0x40011ace + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG15 +CYDEV_UCFG_B1_P5_U1_CFG15 EQU 0x40011acf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG16 +CYDEV_UCFG_B1_P5_U1_CFG16 EQU 0x40011ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG17 +CYDEV_UCFG_B1_P5_U1_CFG17 EQU 0x40011ad1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG18 +CYDEV_UCFG_B1_P5_U1_CFG18 EQU 0x40011ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG19 +CYDEV_UCFG_B1_P5_U1_CFG19 EQU 0x40011ad3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG20 +CYDEV_UCFG_B1_P5_U1_CFG20 EQU 0x40011ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG21 +CYDEV_UCFG_B1_P5_U1_CFG21 EQU 0x40011ad5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG22 +CYDEV_UCFG_B1_P5_U1_CFG22 EQU 0x40011ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG23 +CYDEV_UCFG_B1_P5_U1_CFG23 EQU 0x40011ad7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG24 +CYDEV_UCFG_B1_P5_U1_CFG24 EQU 0x40011ad8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG25 +CYDEV_UCFG_B1_P5_U1_CFG25 EQU 0x40011ad9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG26 +CYDEV_UCFG_B1_P5_U1_CFG26 EQU 0x40011ada + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG27 +CYDEV_UCFG_B1_P5_U1_CFG27 EQU 0x40011adb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG28 +CYDEV_UCFG_B1_P5_U1_CFG28 EQU 0x40011adc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG29 +CYDEV_UCFG_B1_P5_U1_CFG29 EQU 0x40011add + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG30 +CYDEV_UCFG_B1_P5_U1_CFG30 EQU 0x40011ade + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG31 +CYDEV_UCFG_B1_P5_U1_CFG31 EQU 0x40011adf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG0 +CYDEV_UCFG_B1_P5_U1_DCFG0 EQU 0x40011ae0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG1 +CYDEV_UCFG_B1_P5_U1_DCFG1 EQU 0x40011ae2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG2 +CYDEV_UCFG_B1_P5_U1_DCFG2 EQU 0x40011ae4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG3 +CYDEV_UCFG_B1_P5_U1_DCFG3 EQU 0x40011ae6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG4 +CYDEV_UCFG_B1_P5_U1_DCFG4 EQU 0x40011ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG5 +CYDEV_UCFG_B1_P5_U1_DCFG5 EQU 0x40011aea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG6 +CYDEV_UCFG_B1_P5_U1_DCFG6 EQU 0x40011aec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG7 +CYDEV_UCFG_B1_P5_U1_DCFG7 EQU 0x40011aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE +CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE +CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE +CYDEV_UCFG_DSI0_BASE EQU 0x40014000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE +CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE +CYDEV_UCFG_DSI1_BASE EQU 0x40014100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE +CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE +CYDEV_UCFG_DSI2_BASE EQU 0x40014200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE +CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE +CYDEV_UCFG_DSI3_BASE EQU 0x40014300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE +CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE +CYDEV_UCFG_DSI4_BASE EQU 0x40014400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE +CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE +CYDEV_UCFG_DSI5_BASE EQU 0x40014500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE +CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE +CYDEV_UCFG_DSI6_BASE EQU 0x40014600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE +CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE +CYDEV_UCFG_DSI7_BASE EQU 0x40014700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE +CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE +CYDEV_UCFG_DSI8_BASE EQU 0x40014800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE +CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE +CYDEV_UCFG_DSI9_BASE EQU 0x40014900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE +CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE +CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE +CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE +CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE +CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE +CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE +CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MDCLK_EN +CYDEV_UCFG_BCTL0_MDCLK_EN EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MBCLK_EN +CYDEV_UCFG_BCTL0_MBCLK_EN EQU 0x40015001 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_WAIT_CFG +CYDEV_UCFG_BCTL0_WAIT_CFG EQU 0x40015002 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BANK_CTL +CYDEV_UCFG_BCTL0_BANK_CTL EQU 0x40015003 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_UDB_TEST_3 +CYDEV_UCFG_BCTL0_UDB_TEST_3 EQU 0x40015007 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN0 +CYDEV_UCFG_BCTL0_DCLK_EN0 EQU 0x40015008 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN0 +CYDEV_UCFG_BCTL0_BCLK_EN0 EQU 0x40015009 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN1 +CYDEV_UCFG_BCTL0_DCLK_EN1 EQU 0x4001500a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN1 +CYDEV_UCFG_BCTL0_BCLK_EN1 EQU 0x4001500b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN2 +CYDEV_UCFG_BCTL0_DCLK_EN2 EQU 0x4001500c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN2 +CYDEV_UCFG_BCTL0_BCLK_EN2 EQU 0x4001500d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN3 +CYDEV_UCFG_BCTL0_DCLK_EN3 EQU 0x4001500e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN3 +CYDEV_UCFG_BCTL0_BCLK_EN3 EQU 0x4001500f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE +CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE +CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MDCLK_EN +CYDEV_UCFG_BCTL1_MDCLK_EN EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MBCLK_EN +CYDEV_UCFG_BCTL1_MBCLK_EN EQU 0x40015011 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_WAIT_CFG +CYDEV_UCFG_BCTL1_WAIT_CFG EQU 0x40015012 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BANK_CTL +CYDEV_UCFG_BCTL1_BANK_CTL EQU 0x40015013 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_UDB_TEST_3 +CYDEV_UCFG_BCTL1_UDB_TEST_3 EQU 0x40015017 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN0 +CYDEV_UCFG_BCTL1_DCLK_EN0 EQU 0x40015018 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN0 +CYDEV_UCFG_BCTL1_BCLK_EN0 EQU 0x40015019 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN1 +CYDEV_UCFG_BCTL1_DCLK_EN1 EQU 0x4001501a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN1 +CYDEV_UCFG_BCTL1_BCLK_EN1 EQU 0x4001501b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN2 +CYDEV_UCFG_BCTL1_DCLK_EN2 EQU 0x4001501c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN2 +CYDEV_UCFG_BCTL1_BCLK_EN2 EQU 0x4001501d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN3 +CYDEV_UCFG_BCTL1_DCLK_EN3 EQU 0x4001501e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN3 +CYDEV_UCFG_BCTL1_BCLK_EN3 EQU 0x4001501f + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_BASE +CYDEV_IDMUX_BASE EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_SIZE +CYDEV_IDMUX_SIZE EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL0 +CYDEV_IDMUX_IRQ_CTL0 EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL1 +CYDEV_IDMUX_IRQ_CTL1 EQU 0x40015101 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL2 +CYDEV_IDMUX_IRQ_CTL2 EQU 0x40015102 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL3 +CYDEV_IDMUX_IRQ_CTL3 EQU 0x40015103 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL4 +CYDEV_IDMUX_IRQ_CTL4 EQU 0x40015104 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL5 +CYDEV_IDMUX_IRQ_CTL5 EQU 0x40015105 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL6 +CYDEV_IDMUX_IRQ_CTL6 EQU 0x40015106 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL7 +CYDEV_IDMUX_IRQ_CTL7 EQU 0x40015107 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL0 +CYDEV_IDMUX_DRQ_CTL0 EQU 0x40015110 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL1 +CYDEV_IDMUX_DRQ_CTL1 EQU 0x40015111 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL2 +CYDEV_IDMUX_DRQ_CTL2 EQU 0x40015112 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL3 +CYDEV_IDMUX_DRQ_CTL3 EQU 0x40015113 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL4 +CYDEV_IDMUX_DRQ_CTL4 EQU 0x40015114 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL5 +CYDEV_IDMUX_DRQ_CTL5 EQU 0x40015115 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_BASE +CYDEV_CACHERAM_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_SIZE +CYDEV_CACHERAM_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MBASE +CYDEV_CACHERAM_DATA_MBASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MSIZE +CYDEV_CACHERAM_DATA_MSIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_BASE +CYDEV_SFR_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_SIZE +CYDEV_SFR_SIZE EQU 0x000000fb + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO0 +CYDEV_SFR_GPIO0 EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD0 +CYDEV_SFR_GPIRD0 EQU 0x40050189 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO0_SEL +CYDEV_SFR_GPIO0_SEL EQU 0x4005018a + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO1 +CYDEV_SFR_GPIO1 EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD1 +CYDEV_SFR_GPIRD1 EQU 0x40050191 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO2 +CYDEV_SFR_GPIO2 EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD2 +CYDEV_SFR_GPIRD2 EQU 0x40050199 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO2_SEL +CYDEV_SFR_GPIO2_SEL EQU 0x4005019a + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO1_SEL +CYDEV_SFR_GPIO1_SEL EQU 0x400501a2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO3 +CYDEV_SFR_GPIO3 EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD3 +CYDEV_SFR_GPIRD3 EQU 0x400501b1 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO3_SEL +CYDEV_SFR_GPIO3_SEL EQU 0x400501b2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO4 +CYDEV_SFR_GPIO4 EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD4 +CYDEV_SFR_GPIRD4 EQU 0x400501c1 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO4_SEL +CYDEV_SFR_GPIO4_SEL EQU 0x400501c2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO5 +CYDEV_SFR_GPIO5 EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD5 +CYDEV_SFR_GPIRD5 EQU 0x400501c9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO5_SEL +CYDEV_SFR_GPIO5_SEL EQU 0x400501ca + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO6 +CYDEV_SFR_GPIO6 EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD6 +CYDEV_SFR_GPIRD6 EQU 0x400501d9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO6_SEL +CYDEV_SFR_GPIO6_SEL EQU 0x400501da + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO12 +CYDEV_SFR_GPIO12 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD12 +CYDEV_SFR_GPIRD12 EQU 0x400501e9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO12_SEL +CYDEV_SFR_GPIO12_SEL EQU 0x400501f2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO15 +CYDEV_SFR_GPIO15 EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD15 +CYDEV_SFR_GPIRD15 EQU 0x400501f9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO15_SEL +CYDEV_SFR_GPIO15_SEL EQU 0x400501fa + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BASE +CYDEV_P3BA_BASE EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SIZE +CYDEV_P3BA_SIZE EQU 0x0000002b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_Y_START +CYDEV_P3BA_Y_START EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_YROLL +CYDEV_P3BA_YROLL EQU 0x40050301 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_YCFG +CYDEV_P3BA_YCFG EQU 0x40050302 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_START1 +CYDEV_P3BA_X_START1 EQU 0x40050303 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_START2 +CYDEV_P3BA_X_START2 EQU 0x40050304 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XROLL1 +CYDEV_P3BA_XROLL1 EQU 0x40050305 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XROLL2 +CYDEV_P3BA_XROLL2 EQU 0x40050306 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XINC +CYDEV_P3BA_XINC EQU 0x40050307 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XCFG +CYDEV_P3BA_XCFG EQU 0x40050308 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR1 +CYDEV_P3BA_OFFSETADDR1 EQU 0x40050309 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR2 +CYDEV_P3BA_OFFSETADDR2 EQU 0x4005030a + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR3 +CYDEV_P3BA_OFFSETADDR3 EQU 0x4005030b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR1 +CYDEV_P3BA_ABSADDR1 EQU 0x4005030c + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR2 +CYDEV_P3BA_ABSADDR2 EQU 0x4005030d + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR3 +CYDEV_P3BA_ABSADDR3 EQU 0x4005030e + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR4 +CYDEV_P3BA_ABSADDR4 EQU 0x4005030f + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATCFG1 +CYDEV_P3BA_DATCFG1 EQU 0x40050310 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATCFG2 +CYDEV_P3BA_DATCFG2 EQU 0x40050311 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT1 +CYDEV_P3BA_CMP_RSLT1 EQU 0x40050314 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT2 +CYDEV_P3BA_CMP_RSLT2 EQU 0x40050315 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT3 +CYDEV_P3BA_CMP_RSLT3 EQU 0x40050316 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT4 +CYDEV_P3BA_CMP_RSLT4 EQU 0x40050317 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG1 +CYDEV_P3BA_DATA_REG1 EQU 0x40050318 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG2 +CYDEV_P3BA_DATA_REG2 EQU 0x40050319 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG3 +CYDEV_P3BA_DATA_REG3 EQU 0x4005031a + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG4 +CYDEV_P3BA_DATA_REG4 EQU 0x4005031b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA1 +CYDEV_P3BA_EXP_DATA1 EQU 0x4005031c + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA2 +CYDEV_P3BA_EXP_DATA2 EQU 0x4005031d + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA3 +CYDEV_P3BA_EXP_DATA3 EQU 0x4005031e + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA4 +CYDEV_P3BA_EXP_DATA4 EQU 0x4005031f + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA1 +CYDEV_P3BA_MSTR_HRDATA1 EQU 0x40050320 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA2 +CYDEV_P3BA_MSTR_HRDATA2 EQU 0x40050321 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA3 +CYDEV_P3BA_MSTR_HRDATA3 EQU 0x40050322 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA4 +CYDEV_P3BA_MSTR_HRDATA4 EQU 0x40050323 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BIST_EN +CYDEV_P3BA_BIST_EN EQU 0x40050324 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_PHUB_MASTER_SSR +CYDEV_P3BA_PHUB_MASTER_SSR EQU 0x40050325 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SEQCFG1 +CYDEV_P3BA_SEQCFG1 EQU 0x40050326 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SEQCFG2 +CYDEV_P3BA_SEQCFG2 EQU 0x40050327 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_Y_CURR +CYDEV_P3BA_Y_CURR EQU 0x40050328 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_CURR1 +CYDEV_P3BA_X_CURR1 EQU 0x40050329 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_CURR2 +CYDEV_P3BA_X_CURR2 EQU 0x4005032a + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_BASE +CYDEV_PANTHER_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_SIZE +CYDEV_PANTHER_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_STCALIB_CFG +CYDEV_PANTHER_STCALIB_CFG EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_WAITPIPE +CYDEV_PANTHER_WAITPIPE EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_TRACE_CFG +CYDEV_PANTHER_TRACE_CFG EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_DBG_CFG +CYDEV_PANTHER_DBG_CFG EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_CM3_LCKRST_STAT +CYDEV_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_DEVICE_ID +CYDEV_PANTHER_DEVICE_ID EQU 0x4008001c + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_BASE +CYDEV_FLSECC_BASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_SIZE +CYDEV_FLSECC_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_DATA_MBASE +CYDEV_FLSECC_DATA_MBASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_DATA_MSIZE +CYDEV_FLSECC_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_BASE +CYDEV_FLSHID_BASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_SIZE +CYDEV_FLSHID_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MBASE +CYDEV_FLSHID_RSVD_MBASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MSIZE +CYDEV_FLSHID_RSVD_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MBASE +CYDEV_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MSIZE +CYDEV_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE +CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE +CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_Y_LOC +CYDEV_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_X_LOC +CYDEV_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WAFER_NUM +CYDEV_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_LSB +CYDEV_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_MSB +CYDEV_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WRK_WK +CYDEV_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_FAB_YR +CYDEV_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_MINOR +CYDEV_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_USB +CYDEV_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M1 +CYDEV_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M2 +CYDEV_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M3 +CYDEV_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M4 +CYDEV_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M5 +CYDEV_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M6 +CYDEV_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M7 +CYDEV_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M8 +CYDEV_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M1 +CYDEV_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M2 +CYDEV_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M3 +CYDEV_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M4 +CYDEV_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M5 +CYDEV_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M6 +CYDEV_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M7 +CYDEV_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M8 +CYDEV_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M1 +CYDEV_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M2 +CYDEV_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M3 +CYDEV_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M4 +CYDEV_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M5 +CYDEV_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M6 +CYDEV_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M7 +CYDEV_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M8 +CYDEV_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M1 +CYDEV_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M2 +CYDEV_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M3 +CYDEV_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M4 +CYDEV_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M5 +CYDEV_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M6 +CYDEV_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M7 +CYDEV_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M8 +CYDEV_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M1 +CYDEV_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M2 +CYDEV_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M3 +CYDEV_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M4 +CYDEV_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M5 +CYDEV_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M6 +CYDEV_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M7 +CYDEV_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M8 +CYDEV_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE +CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE +CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_IMO_TR1 +CYDEV_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR0 +CYDEV_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR0 +CYDEV_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR0 +CYDEV_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR0 +CYDEV_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR1 +CYDEV_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR1 +CYDEV_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR1 +CYDEV_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR1 +CYDEV_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM +CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_BASE +CYDEV_EXTMEM_BASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_SIZE +CYDEV_EXTMEM_SIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MBASE +CYDEV_EXTMEM_DATA_MBASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MSIZE +CYDEV_EXTMEM_DATA_MSIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_BASE +CYDEV_ITM_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_SIZE +CYDEV_ITM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_EN +CYDEV_ITM_TRACE_EN EQU 0xe0000e00 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_PRIVILEGE +CYDEV_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_CTRL +CYDEV_ITM_TRACE_CTRL EQU 0xe0000e80 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_LOCK_ACCESS +CYDEV_ITM_LOCK_ACCESS EQU 0xe0000fb0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_LOCK_STATUS +CYDEV_ITM_LOCK_STATUS EQU 0xe0000fb4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID4 +CYDEV_ITM_PID4 EQU 0xe0000fd0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID5 +CYDEV_ITM_PID5 EQU 0xe0000fd4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID6 +CYDEV_ITM_PID6 EQU 0xe0000fd8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID7 +CYDEV_ITM_PID7 EQU 0xe0000fdc + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID0 +CYDEV_ITM_PID0 EQU 0xe0000fe0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID1 +CYDEV_ITM_PID1 EQU 0xe0000fe4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID2 +CYDEV_ITM_PID2 EQU 0xe0000fe8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID3 +CYDEV_ITM_PID3 EQU 0xe0000fec + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID0 +CYDEV_ITM_CID0 EQU 0xe0000ff0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID1 +CYDEV_ITM_CID1 EQU 0xe0000ff4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID2 +CYDEV_ITM_CID2 EQU 0xe0000ff8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID3 +CYDEV_ITM_CID3 EQU 0xe0000ffc + ENDIF + IF :LNOT::DEF:CYDEV_DWT_BASE +CYDEV_DWT_BASE EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SIZE +CYDEV_DWT_SIZE EQU 0x0000005c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CTRL +CYDEV_DWT_CTRL EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CYCLE_COUNT +CYDEV_DWT_CYCLE_COUNT EQU 0xe0001004 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CPI_COUNT +CYDEV_DWT_CPI_COUNT EQU 0xe0001008 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_EXC_OVHD_COUNT +CYDEV_DWT_EXC_OVHD_COUNT EQU 0xe000100c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SLEEP_COUNT +CYDEV_DWT_SLEEP_COUNT EQU 0xe0001010 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_LSU_COUNT +CYDEV_DWT_LSU_COUNT EQU 0xe0001014 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FOLD_COUNT +CYDEV_DWT_FOLD_COUNT EQU 0xe0001018 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_PC_SAMPLE +CYDEV_DWT_PC_SAMPLE EQU 0xe000101c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_0 +CYDEV_DWT_COMP_0 EQU 0xe0001020 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_0 +CYDEV_DWT_MASK_0 EQU 0xe0001024 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_0 +CYDEV_DWT_FUNCTION_0 EQU 0xe0001028 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_1 +CYDEV_DWT_COMP_1 EQU 0xe0001030 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_1 +CYDEV_DWT_MASK_1 EQU 0xe0001034 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_1 +CYDEV_DWT_FUNCTION_1 EQU 0xe0001038 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_2 +CYDEV_DWT_COMP_2 EQU 0xe0001040 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_2 +CYDEV_DWT_MASK_2 EQU 0xe0001044 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_2 +CYDEV_DWT_FUNCTION_2 EQU 0xe0001048 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_3 +CYDEV_DWT_COMP_3 EQU 0xe0001050 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_3 +CYDEV_DWT_MASK_3 EQU 0xe0001054 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_3 +CYDEV_DWT_FUNCTION_3 EQU 0xe0001058 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_BASE +CYDEV_FPB_BASE EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_SIZE +CYDEV_FPB_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CTRL +CYDEV_FPB_CTRL EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_REMAP +CYDEV_FPB_REMAP EQU 0xe0002004 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_0 +CYDEV_FPB_FP_COMP_0 EQU 0xe0002008 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_1 +CYDEV_FPB_FP_COMP_1 EQU 0xe000200c + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_2 +CYDEV_FPB_FP_COMP_2 EQU 0xe0002010 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_3 +CYDEV_FPB_FP_COMP_3 EQU 0xe0002014 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_4 +CYDEV_FPB_FP_COMP_4 EQU 0xe0002018 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_5 +CYDEV_FPB_FP_COMP_5 EQU 0xe000201c + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_6 +CYDEV_FPB_FP_COMP_6 EQU 0xe0002020 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_7 +CYDEV_FPB_FP_COMP_7 EQU 0xe0002024 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID4 +CYDEV_FPB_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID5 +CYDEV_FPB_PID5 EQU 0xe0002fd4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID6 +CYDEV_FPB_PID6 EQU 0xe0002fd8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID7 +CYDEV_FPB_PID7 EQU 0xe0002fdc + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID0 +CYDEV_FPB_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID1 +CYDEV_FPB_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID2 +CYDEV_FPB_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID3 +CYDEV_FPB_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID0 +CYDEV_FPB_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID1 +CYDEV_FPB_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID2 +CYDEV_FPB_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID3 +CYDEV_FPB_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BASE +CYDEV_NVIC_BASE EQU 0xe000e000 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SIZE +CYDEV_NVIC_SIZE EQU 0x00000d3c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_INT_CTL_TYPE +CYDEV_NVIC_INT_CTL_TYPE EQU 0xe000e004 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CTL +CYDEV_NVIC_SYSTICK_CTL EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_RELOAD +CYDEV_NVIC_SYSTICK_RELOAD EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CURRENT +CYDEV_NVIC_SYSTICK_CURRENT EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CAL +CYDEV_NVIC_SYSTICK_CAL EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SETENA0 +CYDEV_NVIC_SETENA0 EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CLRENA0 +CYDEV_NVIC_CLRENA0 EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SETPEND0 +CYDEV_NVIC_SETPEND0 EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CLRPEND0 +CYDEV_NVIC_CLRPEND0 EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_ACTIVE0 +CYDEV_NVIC_ACTIVE0 EQU 0xe000e300 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_0 +CYDEV_NVIC_PRI_0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_1 +CYDEV_NVIC_PRI_1 EQU 0xe000e401 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_2 +CYDEV_NVIC_PRI_2 EQU 0xe000e402 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_3 +CYDEV_NVIC_PRI_3 EQU 0xe000e403 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_4 +CYDEV_NVIC_PRI_4 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_5 +CYDEV_NVIC_PRI_5 EQU 0xe000e405 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_6 +CYDEV_NVIC_PRI_6 EQU 0xe000e406 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_7 +CYDEV_NVIC_PRI_7 EQU 0xe000e407 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_8 +CYDEV_NVIC_PRI_8 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_9 +CYDEV_NVIC_PRI_9 EQU 0xe000e409 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_10 +CYDEV_NVIC_PRI_10 EQU 0xe000e40a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_11 +CYDEV_NVIC_PRI_11 EQU 0xe000e40b + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_12 +CYDEV_NVIC_PRI_12 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_13 +CYDEV_NVIC_PRI_13 EQU 0xe000e40d + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_14 +CYDEV_NVIC_PRI_14 EQU 0xe000e40e + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_15 +CYDEV_NVIC_PRI_15 EQU 0xe000e40f + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_16 +CYDEV_NVIC_PRI_16 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_17 +CYDEV_NVIC_PRI_17 EQU 0xe000e411 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_18 +CYDEV_NVIC_PRI_18 EQU 0xe000e412 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_19 +CYDEV_NVIC_PRI_19 EQU 0xe000e413 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_20 +CYDEV_NVIC_PRI_20 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_21 +CYDEV_NVIC_PRI_21 EQU 0xe000e415 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_22 +CYDEV_NVIC_PRI_22 EQU 0xe000e416 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_23 +CYDEV_NVIC_PRI_23 EQU 0xe000e417 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_24 +CYDEV_NVIC_PRI_24 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_25 +CYDEV_NVIC_PRI_25 EQU 0xe000e419 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_26 +CYDEV_NVIC_PRI_26 EQU 0xe000e41a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_27 +CYDEV_NVIC_PRI_27 EQU 0xe000e41b + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_28 +CYDEV_NVIC_PRI_28 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_29 +CYDEV_NVIC_PRI_29 EQU 0xe000e41d + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_30 +CYDEV_NVIC_PRI_30 EQU 0xe000e41e + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_31 +CYDEV_NVIC_PRI_31 EQU 0xe000e41f + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CPUID_BASE +CYDEV_NVIC_CPUID_BASE EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_INTR_CTRL_STATE +CYDEV_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_VECT_OFFSET +CYDEV_NVIC_VECT_OFFSET EQU 0xe000ed08 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_APPLN_INTR +CYDEV_NVIC_APPLN_INTR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTEM_CONTROL +CYDEV_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CFG_CONTROL +CYDEV_NVIC_CFG_CONTROL EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 +CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 +CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 +CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_HANDLER_CSR +CYDEV_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_STATUS +CYDEV_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_STATUS +CYDEV_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_USAGE_FAULT_STATUS +CYDEV_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_HARD_FAULT_STATUS +CYDEV_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_DEBUG_FAULT_STATUS +CYDEV_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_ADD +CYDEV_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_ADD +CYDEV_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_BASE +CYDEV_CORE_DBG_BASE EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE +CYDEV_CORE_DBG_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_HLT_CS +CYDEV_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_SEL +CYDEV_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_DATA +CYDEV_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_EXC_MON_CTL +CYDEV_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_BASE +CYDEV_TPIU_BASE EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SIZE +CYDEV_TPIU_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ +CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CURRENT_SYNC_PRT_SZ +CYDEV_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ASYNC_CLK_PRESCALER +CYDEV_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PROTOCOL +CYDEV_TPIU_PROTOCOL EQU 0xe00400f0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_STAT +CYDEV_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_CTRL +CYDEV_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_TRIGGER +CYDEV_TPIU_TRIGGER EQU 0xe0040ee8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITETMDATA +CYDEV_TPIU_ITETMDATA EQU 0xe0040eec + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR2 +CYDEV_TPIU_ITATBCTR2 EQU 0xe0040ef0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR0 +CYDEV_TPIU_ITATBCTR0 EQU 0xe0040ef8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITITMDATA +CYDEV_TPIU_ITITMDATA EQU 0xe0040efc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITCTRL +CYDEV_TPIU_ITCTRL EQU 0xe0040f00 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_DEVID +CYDEV_TPIU_DEVID EQU 0xe0040fc8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_DEVTYPE +CYDEV_TPIU_DEVTYPE EQU 0xe0040fcc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID4 +CYDEV_TPIU_PID4 EQU 0xe0040fd0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID5 +CYDEV_TPIU_PID5 EQU 0xe0040fd4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID6 +CYDEV_TPIU_PID6 EQU 0xe0040fd8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID7 +CYDEV_TPIU_PID7 EQU 0xe0040fdc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID0 +CYDEV_TPIU_PID0 EQU 0xe0040fe0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID1 +CYDEV_TPIU_PID1 EQU 0xe0040fe4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID2 +CYDEV_TPIU_PID2 EQU 0xe0040fe8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID3 +CYDEV_TPIU_PID3 EQU 0xe0040fec + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID0 +CYDEV_TPIU_CID0 EQU 0xe0040ff0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID1 +CYDEV_TPIU_CID1 EQU 0xe0040ff4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID2 +CYDEV_TPIU_CID2 EQU 0xe0040ff8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID3 +CYDEV_TPIU_CID3 EQU 0xe0040ffc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_BASE +CYDEV_ETM_BASE EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SIZE +CYDEV_ETM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CTL +CYDEV_ETM_CTL EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CFG_CODE +CYDEV_ETM_CFG_CODE EQU 0xe0041004 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRIG_EVENT +CYDEV_ETM_TRIG_EVENT EQU 0xe0041008 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_STATUS +CYDEV_ETM_STATUS EQU 0xe0041010 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SYS_CFG +CYDEV_ETM_SYS_CFG EQU 0xe0041014 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRACE_ENB_EVENT +CYDEV_ETM_TRACE_ENB_EVENT EQU 0xe0041020 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRACE_EN_CTRL1 +CYDEV_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_FIFOFULL_LEVEL +CYDEV_ETM_FIFOFULL_LEVEL EQU 0xe004102c + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SYNC_FREQ +CYDEV_ETM_SYNC_FREQ EQU 0xe00411e0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ETM_ID +CYDEV_ETM_ETM_ID EQU 0xe00411e4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CFG_CODE_EXT +CYDEV_ETM_CFG_CODE_EXT EQU 0xe00411e8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TR_SS_EMBICE_CTRL +CYDEV_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CS_TRACE_ID +CYDEV_ETM_CS_TRACE_ID EQU 0xe0041200 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_ACCESS +CYDEV_ETM_OS_LOCK_ACCESS EQU 0xe0041300 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_STATUS +CYDEV_ETM_OS_LOCK_STATUS EQU 0xe0041304 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PDSR +CYDEV_ETM_PDSR EQU 0xe0041314 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITMISCIN +CYDEV_ETM_ITMISCIN EQU 0xe0041ee0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITTRIGOUT +CYDEV_ETM_ITTRIGOUT EQU 0xe0041ee8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITATBCTR2 +CYDEV_ETM_ITATBCTR2 EQU 0xe0041ef0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITATBCTR0 +CYDEV_ETM_ITATBCTR0 EQU 0xe0041ef8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_INT_MODE_CTRL +CYDEV_ETM_INT_MODE_CTRL EQU 0xe0041f00 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_SET +CYDEV_ETM_CLM_TAG_SET EQU 0xe0041fa0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_CLR +CYDEV_ETM_CLM_TAG_CLR EQU 0xe0041fa4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_LOCK_ACCESS +CYDEV_ETM_LOCK_ACCESS EQU 0xe0041fb0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_LOCK_STATUS +CYDEV_ETM_LOCK_STATUS EQU 0xe0041fb4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_AUTH_STATUS +CYDEV_ETM_AUTH_STATUS EQU 0xe0041fb8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_DEV_TYPE +CYDEV_ETM_DEV_TYPE EQU 0xe0041fcc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID4 +CYDEV_ETM_PID4 EQU 0xe0041fd0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID5 +CYDEV_ETM_PID5 EQU 0xe0041fd4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID6 +CYDEV_ETM_PID6 EQU 0xe0041fd8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID7 +CYDEV_ETM_PID7 EQU 0xe0041fdc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID0 +CYDEV_ETM_PID0 EQU 0xe0041fe0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID1 +CYDEV_ETM_PID1 EQU 0xe0041fe4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID2 +CYDEV_ETM_PID2 EQU 0xe0041fe8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID3 +CYDEV_ETM_PID3 EQU 0xe0041fec + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID0 +CYDEV_ETM_CID0 EQU 0xe0041ff0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID1 +CYDEV_ETM_CID1 EQU 0xe0041ff4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID2 +CYDEV_ETM_CID2 EQU 0xe0041ff8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID3 +CYDEV_ETM_CID3 EQU 0xe0041ffc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE +CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE +CYDEV_ROM_TABLE_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_NVIC +CYDEV_ROM_TABLE_NVIC EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_DWT +CYDEV_ROM_TABLE_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_FPB +CYDEV_ROM_TABLE_FPB EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_ITM +CYDEV_ROM_TABLE_ITM EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_TPIU +CYDEV_ROM_TABLE_TPIU EQU 0xe00ff010 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_ETM +CYDEV_ROM_TABLE_ETM EQU 0xe00ff014 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_END +CYDEV_ROM_TABLE_END EQU 0xe00ff018 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_MEMTYPE +CYDEV_ROM_TABLE_MEMTYPE EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID4 +CYDEV_ROM_TABLE_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID5 +CYDEV_ROM_TABLE_PID5 EQU 0xe00fffd4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID6 +CYDEV_ROM_TABLE_PID6 EQU 0xe00fffd8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID7 +CYDEV_ROM_TABLE_PID7 EQU 0xe00fffdc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID0 +CYDEV_ROM_TABLE_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID1 +CYDEV_ROM_TABLE_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID2 +CYDEV_ROM_TABLE_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID3 +CYDEV_ROM_TABLE_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID0 +CYDEV_ROM_TABLE_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID1 +CYDEV_ROM_TABLE_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID2 +CYDEV_ROM_TABLE_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID3 +CYDEV_ROM_TABLE_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SIZE +CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE + ENDIF + IF :LNOT::DEF:CYDEV_ECC_BASE +CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE +CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE +CYDEV_ECC_ROW_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE +CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE +CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PERIPH_BASE +CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE + ENDIF + IF :LNOT::DEF:CYCLK_LD_DISABLE +CYCLK_LD_DISABLE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYCLK_LD_SYNC_EN +CYCLK_LD_SYNC_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYCLK_LD_LOAD +CYCLK_LD_LOAD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYCLK_PIPE +CYCLK_PIPE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYCLK_SSS +CYCLK_SSS EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYCLK_EARLY +CYCLK_EARLY EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYCLK_DUTY +CYCLK_DUTY EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYCLK_SYNC +CYCLK_SYNC EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D +CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG +CYCLK_SRC_SEL_SYNC_DIG EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_IMO +CYCLK_SRC_SEL_IMO EQU 1 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ +CYCLK_SRC_SEL_XTAL_MHZ EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM +CYCLK_SRC_SEL_XTALM EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_ILO +CYCLK_SRC_SEL_ILO EQU 3 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_PLL +CYCLK_SRC_SEL_PLL EQU 4 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ +CYCLK_SRC_SEL_XTAL_KHZ EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK +CYCLK_SRC_SEL_XTALK EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G +CYCLK_SRC_SEL_DSI_G EQU 6 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D +CYCLK_SRC_SEL_DSI_D EQU 7 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A +CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A +CYCLK_SRC_SEL_DSI_A EQU 7 + ENDIF + END diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc new file mode 100644 index 0000000..9d0ef51 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -0,0 +1,16039 @@ +; +; FILENAME: cydevicerv_trm.inc +; +; PSoC Creator 2.2 Component Pack 6 +; +; DESCRIPTION: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00040000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MBASE +CYREG_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MSIZE +CYREG_FLASH_DATA_MSIZE EQU 0x00040000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE64K_MBASE +CYREG_SRAM_CODE64K_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE64K_MSIZE +CYREG_SRAM_CODE64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE32K_MBASE +CYREG_SRAM_CODE32K_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE32K_MSIZE +CYREG_SRAM_CODE32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE16K_MBASE +CYREG_SRAM_CODE16K_MBASE EQU 0x1fffe000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE16K_MSIZE +CYREG_SRAM_CODE16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE_MBASE +CYREG_SRAM_CODE_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE_MSIZE +CYREG_SRAM_CODE_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MBASE +CYREG_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MSIZE +CYREG_SRAM_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA16K_MBASE +CYREG_SRAM_DATA16K_MBASE EQU 0x20001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA16K_MSIZE +CYREG_SRAM_DATA16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA32K_MBASE +CYREG_SRAM_DATA32K_MBASE EQU 0x20002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA32K_MSIZE +CYREG_SRAM_DATA32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA64K_MBASE +CYREG_SRAM_DATA64K_MBASE EQU 0x20004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA64K_MSIZE +CYREG_SRAM_DATA64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_BASE +CYDEV_DMA_BASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SIZE +CYDEV_DMA_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM64K_MBASE +CYREG_DMA_SRAM64K_MBASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM64K_MSIZE +CYREG_DMA_SRAM64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM32K_MBASE +CYREG_DMA_SRAM32K_MBASE EQU 0x2000c000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM32K_MSIZE +CYREG_DMA_SRAM32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM16K_MBASE +CYREG_DMA_SRAM16K_MBASE EQU 0x2000e000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM16K_MSIZE +CYREG_DMA_SRAM16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM_MBASE +CYREG_DMA_SRAM_MBASE EQU 0x2000f000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM_MSIZE +CYREG_DMA_SRAM_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BASE +CYDEV_CLKDIST_BASE EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_SIZE +CYDEV_CLKDIST_SIZE EQU 0x00000110 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_CR +CYREG_CLKDIST_CR EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_LD +CYREG_CLKDIST_LD EQU 0x40004001 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_WRK0 +CYREG_CLKDIST_WRK0 EQU 0x40004002 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_WRK1 +CYREG_CLKDIST_WRK1 EQU 0x40004003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_MSTR0 +CYREG_CLKDIST_MSTR0 EQU 0x40004004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_MSTR1 +CYREG_CLKDIST_MSTR1 EQU 0x40004005 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG0 +CYREG_CLKDIST_BCFG0 EQU 0x40004006 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG1 +CYREG_CLKDIST_BCFG1 EQU 0x40004007 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG2 +CYREG_CLKDIST_BCFG2 EQU 0x40004008 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_UCFG +CYREG_CLKDIST_UCFG EQU 0x40004009 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DLY0 +CYREG_CLKDIST_DLY0 EQU 0x4000400a + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DLY1 +CYREG_CLKDIST_DLY1 EQU 0x4000400b + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DMASK +CYREG_CLKDIST_DMASK EQU 0x40004010 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_AMASK +CYREG_CLKDIST_AMASK EQU 0x40004014 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE +CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE +CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG0 +CYREG_CLKDIST_DCFG0_CFG0 EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG1 +CYREG_CLKDIST_DCFG0_CFG1 EQU 0x40004081 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG2 +CYREG_CLKDIST_DCFG0_CFG2 EQU 0x40004082 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE +CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE +CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG0 +CYREG_CLKDIST_DCFG1_CFG0 EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG1 +CYREG_CLKDIST_DCFG1_CFG1 EQU 0x40004085 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG2 +CYREG_CLKDIST_DCFG1_CFG2 EQU 0x40004086 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE +CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE +CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG0 +CYREG_CLKDIST_DCFG2_CFG0 EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG1 +CYREG_CLKDIST_DCFG2_CFG1 EQU 0x40004089 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG2 +CYREG_CLKDIST_DCFG2_CFG2 EQU 0x4000408a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE +CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE +CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG0 +CYREG_CLKDIST_DCFG3_CFG0 EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG1 +CYREG_CLKDIST_DCFG3_CFG1 EQU 0x4000408d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG2 +CYREG_CLKDIST_DCFG3_CFG2 EQU 0x4000408e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE +CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE +CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG0 +CYREG_CLKDIST_DCFG4_CFG0 EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG1 +CYREG_CLKDIST_DCFG4_CFG1 EQU 0x40004091 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG2 +CYREG_CLKDIST_DCFG4_CFG2 EQU 0x40004092 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE +CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE +CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG0 +CYREG_CLKDIST_DCFG5_CFG0 EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG1 +CYREG_CLKDIST_DCFG5_CFG1 EQU 0x40004095 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG2 +CYREG_CLKDIST_DCFG5_CFG2 EQU 0x40004096 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE +CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE +CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG0 +CYREG_CLKDIST_DCFG6_CFG0 EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG1 +CYREG_CLKDIST_DCFG6_CFG1 EQU 0x40004099 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG2 +CYREG_CLKDIST_DCFG6_CFG2 EQU 0x4000409a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE +CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE +CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG0 +CYREG_CLKDIST_DCFG7_CFG0 EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG1 +CYREG_CLKDIST_DCFG7_CFG1 EQU 0x4000409d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG2 +CYREG_CLKDIST_DCFG7_CFG2 EQU 0x4000409e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE +CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE +CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG0 +CYREG_CLKDIST_ACFG0_CFG0 EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG1 +CYREG_CLKDIST_ACFG0_CFG1 EQU 0x40004101 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG2 +CYREG_CLKDIST_ACFG0_CFG2 EQU 0x40004102 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG3 +CYREG_CLKDIST_ACFG0_CFG3 EQU 0x40004103 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE +CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE +CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG0 +CYREG_CLKDIST_ACFG1_CFG0 EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG1 +CYREG_CLKDIST_ACFG1_CFG1 EQU 0x40004105 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG2 +CYREG_CLKDIST_ACFG1_CFG2 EQU 0x40004106 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG3 +CYREG_CLKDIST_ACFG1_CFG3 EQU 0x40004107 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE +CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE +CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG0 +CYREG_CLKDIST_ACFG2_CFG0 EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG1 +CYREG_CLKDIST_ACFG2_CFG1 EQU 0x40004109 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG2 +CYREG_CLKDIST_ACFG2_CFG2 EQU 0x4000410a + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG3 +CYREG_CLKDIST_ACFG2_CFG3 EQU 0x4000410b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE +CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE +CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG0 +CYREG_CLKDIST_ACFG3_CFG0 EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG1 +CYREG_CLKDIST_ACFG3_CFG1 EQU 0x4000410d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG2 +CYREG_CLKDIST_ACFG3_CFG2 EQU 0x4000410e + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG3 +CYREG_CLKDIST_ACFG3_CFG3 EQU 0x4000410f + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_BASE +CYDEV_FASTCLK_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_SIZE +CYDEV_FASTCLK_SIZE EQU 0x00000026 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE +CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE +CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_IMO_CR +CYREG_FASTCLK_IMO_CR EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE +CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE +CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CSR +CYREG_FASTCLK_XMHZ_CSR EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG0 +CYREG_FASTCLK_XMHZ_CFG0 EQU 0x40004212 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG1 +CYREG_FASTCLK_XMHZ_CFG1 EQU 0x40004213 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE +CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE +CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG0 +CYREG_FASTCLK_PLL_CFG0 EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG1 +CYREG_FASTCLK_PLL_CFG1 EQU 0x40004221 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_P +CYREG_FASTCLK_PLL_P EQU 0x40004222 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_Q +CYREG_FASTCLK_PLL_Q EQU 0x40004223 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_SR +CYREG_FASTCLK_PLL_SR EQU 0x40004225 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_BASE +CYDEV_SLOWCLK_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE +CYDEV_SLOWCLK_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE +CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE +CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR0 +CYREG_SLOWCLK_ILO_CR0 EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR1 +CYREG_SLOWCLK_ILO_CR1 EQU 0x40004301 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE +CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE +CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_CR +CYREG_SLOWCLK_X32_CR EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_CFG +CYREG_SLOWCLK_X32_CFG EQU 0x40004309 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_TST +CYREG_SLOWCLK_X32_TST EQU 0x4000430a + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_BASE +CYDEV_BOOST_BASE EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SIZE +CYDEV_BOOST_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR0 +CYREG_BOOST_CR0 EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR1 +CYREG_BOOST_CR1 EQU 0x40004321 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR2 +CYREG_BOOST_CR2 EQU 0x40004322 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR3 +CYREG_BOOST_CR3 EQU 0x40004323 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_SR +CYREG_BOOST_SR EQU 0x40004324 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR4 +CYREG_BOOST_CR4 EQU 0x40004325 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_SR2 +CYREG_BOOST_SR2 EQU 0x40004326 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_BASE +CYDEV_PWRSYS_BASE EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_SIZE +CYDEV_PWRSYS_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_CR0 +CYREG_PWRSYS_CR0 EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_CR1 +CYREG_PWRSYS_CR1 EQU 0x40004331 + ENDIF + IF :LNOT::DEF:CYDEV_PM_BASE +CYDEV_PM_BASE EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_SIZE +CYDEV_PM_SIZE EQU 0x00000057 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG0 +CYREG_PM_TW_CFG0 EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG1 +CYREG_PM_TW_CFG1 EQU 0x40004381 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG2 +CYREG_PM_TW_CFG2 EQU 0x40004382 + ENDIF + IF :LNOT::DEF:CYREG_PM_WDT_CFG +CYREG_PM_WDT_CFG EQU 0x40004383 + ENDIF + IF :LNOT::DEF:CYREG_PM_WDT_CR +CYREG_PM_WDT_CR EQU 0x40004384 + ENDIF + IF :LNOT::DEF:CYREG_PM_INT_SR +CYREG_PM_INT_SR EQU 0x40004390 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CFG0 +CYREG_PM_MODE_CFG0 EQU 0x40004391 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CFG1 +CYREG_PM_MODE_CFG1 EQU 0x40004392 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CSR +CYREG_PM_MODE_CSR EQU 0x40004393 + ENDIF + IF :LNOT::DEF:CYREG_PM_USB_CR0 +CYREG_PM_USB_CR0 EQU 0x40004394 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG0 +CYREG_PM_WAKEUP_CFG0 EQU 0x40004398 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG1 +CYREG_PM_WAKEUP_CFG1 EQU 0x40004399 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG2 +CYREG_PM_WAKEUP_CFG2 EQU 0x4000439a + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_BASE +CYDEV_PM_ACT_BASE EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_SIZE +CYDEV_PM_ACT_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG0 +CYREG_PM_ACT_CFG0 EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG1 +CYREG_PM_ACT_CFG1 EQU 0x400043a1 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG2 +CYREG_PM_ACT_CFG2 EQU 0x400043a2 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG3 +CYREG_PM_ACT_CFG3 EQU 0x400043a3 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG4 +CYREG_PM_ACT_CFG4 EQU 0x400043a4 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG5 +CYREG_PM_ACT_CFG5 EQU 0x400043a5 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG6 +CYREG_PM_ACT_CFG6 EQU 0x400043a6 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG7 +CYREG_PM_ACT_CFG7 EQU 0x400043a7 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG8 +CYREG_PM_ACT_CFG8 EQU 0x400043a8 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG9 +CYREG_PM_ACT_CFG9 EQU 0x400043a9 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG10 +CYREG_PM_ACT_CFG10 EQU 0x400043aa + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG11 +CYREG_PM_ACT_CFG11 EQU 0x400043ab + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG12 +CYREG_PM_ACT_CFG12 EQU 0x400043ac + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG13 +CYREG_PM_ACT_CFG13 EQU 0x400043ad + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_BASE +CYDEV_PM_STBY_BASE EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_SIZE +CYDEV_PM_STBY_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG0 +CYREG_PM_STBY_CFG0 EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG1 +CYREG_PM_STBY_CFG1 EQU 0x400043b1 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG2 +CYREG_PM_STBY_CFG2 EQU 0x400043b2 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG3 +CYREG_PM_STBY_CFG3 EQU 0x400043b3 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG4 +CYREG_PM_STBY_CFG4 EQU 0x400043b4 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG5 +CYREG_PM_STBY_CFG5 EQU 0x400043b5 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG6 +CYREG_PM_STBY_CFG6 EQU 0x400043b6 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG7 +CYREG_PM_STBY_CFG7 EQU 0x400043b7 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG8 +CYREG_PM_STBY_CFG8 EQU 0x400043b8 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG9 +CYREG_PM_STBY_CFG9 EQU 0x400043b9 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG10 +CYREG_PM_STBY_CFG10 EQU 0x400043ba + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG11 +CYREG_PM_STBY_CFG11 EQU 0x400043bb + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG12 +CYREG_PM_STBY_CFG12 EQU 0x400043bc + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG13 +CYREG_PM_STBY_CFG13 EQU 0x400043bd + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE +CYDEV_PM_AVAIL_BASE EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE +CYDEV_PM_AVAIL_SIZE EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR0 +CYREG_PM_AVAIL_CR0 EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR1 +CYREG_PM_AVAIL_CR1 EQU 0x400043c1 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR2 +CYREG_PM_AVAIL_CR2 EQU 0x400043c2 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR3 +CYREG_PM_AVAIL_CR3 EQU 0x400043c3 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR4 +CYREG_PM_AVAIL_CR4 EQU 0x400043c4 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR5 +CYREG_PM_AVAIL_CR5 EQU 0x400043c5 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR6 +CYREG_PM_AVAIL_CR6 EQU 0x400043c6 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR0 +CYREG_PM_AVAIL_SR0 EQU 0x400043d0 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR1 +CYREG_PM_AVAIL_SR1 EQU 0x400043d1 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR2 +CYREG_PM_AVAIL_SR2 EQU 0x400043d2 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR3 +CYREG_PM_AVAIL_SR3 EQU 0x400043d3 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR4 +CYREG_PM_AVAIL_SR4 EQU 0x400043d4 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR5 +CYREG_PM_AVAIL_SR5 EQU 0x400043d5 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR6 +CYREG_PM_AVAIL_SR6 EQU 0x400043d6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_BASE +CYDEV_PICU_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SIZE +CYDEV_PICU_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE +CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE +CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE +CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE +CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE0 +CYREG_PICU0_INTTYPE0 EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE1 +CYREG_PICU0_INTTYPE1 EQU 0x40004501 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE2 +CYREG_PICU0_INTTYPE2 EQU 0x40004502 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE3 +CYREG_PICU0_INTTYPE3 EQU 0x40004503 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE4 +CYREG_PICU0_INTTYPE4 EQU 0x40004504 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE5 +CYREG_PICU0_INTTYPE5 EQU 0x40004505 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE6 +CYREG_PICU0_INTTYPE6 EQU 0x40004506 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE7 +CYREG_PICU0_INTTYPE7 EQU 0x40004507 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE +CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE +CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE0 +CYREG_PICU1_INTTYPE0 EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE1 +CYREG_PICU1_INTTYPE1 EQU 0x40004509 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE2 +CYREG_PICU1_INTTYPE2 EQU 0x4000450a + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE3 +CYREG_PICU1_INTTYPE3 EQU 0x4000450b + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE4 +CYREG_PICU1_INTTYPE4 EQU 0x4000450c + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE5 +CYREG_PICU1_INTTYPE5 EQU 0x4000450d + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE6 +CYREG_PICU1_INTTYPE6 EQU 0x4000450e + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE7 +CYREG_PICU1_INTTYPE7 EQU 0x4000450f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE +CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE +CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE0 +CYREG_PICU2_INTTYPE0 EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE1 +CYREG_PICU2_INTTYPE1 EQU 0x40004511 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE2 +CYREG_PICU2_INTTYPE2 EQU 0x40004512 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE3 +CYREG_PICU2_INTTYPE3 EQU 0x40004513 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE4 +CYREG_PICU2_INTTYPE4 EQU 0x40004514 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE5 +CYREG_PICU2_INTTYPE5 EQU 0x40004515 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE6 +CYREG_PICU2_INTTYPE6 EQU 0x40004516 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE7 +CYREG_PICU2_INTTYPE7 EQU 0x40004517 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE +CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE +CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE0 +CYREG_PICU3_INTTYPE0 EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE1 +CYREG_PICU3_INTTYPE1 EQU 0x40004519 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE2 +CYREG_PICU3_INTTYPE2 EQU 0x4000451a + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE3 +CYREG_PICU3_INTTYPE3 EQU 0x4000451b + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE4 +CYREG_PICU3_INTTYPE4 EQU 0x4000451c + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE5 +CYREG_PICU3_INTTYPE5 EQU 0x4000451d + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE6 +CYREG_PICU3_INTTYPE6 EQU 0x4000451e + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE7 +CYREG_PICU3_INTTYPE7 EQU 0x4000451f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE +CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE +CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE0 +CYREG_PICU4_INTTYPE0 EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE1 +CYREG_PICU4_INTTYPE1 EQU 0x40004521 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE2 +CYREG_PICU4_INTTYPE2 EQU 0x40004522 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE3 +CYREG_PICU4_INTTYPE3 EQU 0x40004523 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE4 +CYREG_PICU4_INTTYPE4 EQU 0x40004524 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE5 +CYREG_PICU4_INTTYPE5 EQU 0x40004525 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE6 +CYREG_PICU4_INTTYPE6 EQU 0x40004526 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE7 +CYREG_PICU4_INTTYPE7 EQU 0x40004527 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE +CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE +CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE0 +CYREG_PICU5_INTTYPE0 EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE1 +CYREG_PICU5_INTTYPE1 EQU 0x40004529 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE2 +CYREG_PICU5_INTTYPE2 EQU 0x4000452a + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE3 +CYREG_PICU5_INTTYPE3 EQU 0x4000452b + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE4 +CYREG_PICU5_INTTYPE4 EQU 0x4000452c + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE5 +CYREG_PICU5_INTTYPE5 EQU 0x4000452d + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE6 +CYREG_PICU5_INTTYPE6 EQU 0x4000452e + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE7 +CYREG_PICU5_INTTYPE7 EQU 0x4000452f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE +CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE +CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE0 +CYREG_PICU6_INTTYPE0 EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE1 +CYREG_PICU6_INTTYPE1 EQU 0x40004531 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE2 +CYREG_PICU6_INTTYPE2 EQU 0x40004532 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE3 +CYREG_PICU6_INTTYPE3 EQU 0x40004533 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE4 +CYREG_PICU6_INTTYPE4 EQU 0x40004534 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE5 +CYREG_PICU6_INTTYPE5 EQU 0x40004535 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE6 +CYREG_PICU6_INTTYPE6 EQU 0x40004536 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE7 +CYREG_PICU6_INTTYPE7 EQU 0x40004537 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE +CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE +CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE0 +CYREG_PICU12_INTTYPE0 EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE1 +CYREG_PICU12_INTTYPE1 EQU 0x40004561 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE2 +CYREG_PICU12_INTTYPE2 EQU 0x40004562 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE3 +CYREG_PICU12_INTTYPE3 EQU 0x40004563 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE4 +CYREG_PICU12_INTTYPE4 EQU 0x40004564 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE5 +CYREG_PICU12_INTTYPE5 EQU 0x40004565 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE6 +CYREG_PICU12_INTTYPE6 EQU 0x40004566 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE7 +CYREG_PICU12_INTTYPE7 EQU 0x40004567 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE +CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE +CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE0 +CYREG_PICU15_INTTYPE0 EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE1 +CYREG_PICU15_INTTYPE1 EQU 0x40004579 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE2 +CYREG_PICU15_INTTYPE2 EQU 0x4000457a + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE3 +CYREG_PICU15_INTTYPE3 EQU 0x4000457b + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE4 +CYREG_PICU15_INTTYPE4 EQU 0x4000457c + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE5 +CYREG_PICU15_INTTYPE5 EQU 0x4000457d + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE6 +CYREG_PICU15_INTTYPE6 EQU 0x4000457e + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE7 +CYREG_PICU15_INTTYPE7 EQU 0x4000457f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_BASE +CYDEV_PICU_STAT_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE +CYDEV_PICU_STAT_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE +CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE +CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTSTAT +CYREG_PICU0_INTSTAT EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE +CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE +CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTSTAT +CYREG_PICU1_INTSTAT EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE +CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE +CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTSTAT +CYREG_PICU2_INTSTAT EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE +CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE +CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTSTAT +CYREG_PICU3_INTSTAT EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE +CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE +CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTSTAT +CYREG_PICU4_INTSTAT EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE +CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE +CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTSTAT +CYREG_PICU5_INTSTAT EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE +CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE +CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTSTAT +CYREG_PICU6_INTSTAT EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE +CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE +CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTSTAT +CYREG_PICU12_INTSTAT EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE +CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE +CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTSTAT +CYREG_PICU15_INTSTAT EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE +CYDEV_PICU_SNAP_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE +CYDEV_PICU_SNAP_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE +CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE +CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_SNAP +CYREG_PICU0_SNAP EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE +CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE +CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_SNAP +CYREG_PICU1_SNAP EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE +CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE +CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_SNAP +CYREG_PICU2_SNAP EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE +CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE +CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_SNAP +CYREG_PICU3_SNAP EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE +CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE +CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_SNAP +CYREG_PICU4_SNAP EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE +CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE +CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_SNAP +CYREG_PICU5_SNAP EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE +CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE +CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_SNAP +CYREG_PICU6_SNAP EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE +CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE +CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_SNAP +CYREG_PICU12_SNAP EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE +CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE +CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU_15_SNAP_15 +CYREG_PICU_15_SNAP_15 EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE +CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE +CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE +CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE +CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_DISABLE_COR +CYREG_PICU0_DISABLE_COR EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE +CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE +CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_DISABLE_COR +CYREG_PICU1_DISABLE_COR EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE +CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE +CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_DISABLE_COR +CYREG_PICU2_DISABLE_COR EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE +CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE +CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_DISABLE_COR +CYREG_PICU3_DISABLE_COR EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE +CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE +CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_DISABLE_COR +CYREG_PICU4_DISABLE_COR EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE +CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE +CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_DISABLE_COR +CYREG_PICU5_DISABLE_COR EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE +CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE +CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_DISABLE_COR +CYREG_PICU6_DISABLE_COR EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE +CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE +CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_DISABLE_COR +CYREG_PICU12_DISABLE_COR EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE +CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE +CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_DISABLE_COR +CYREG_PICU15_DISABLE_COR EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_BASE +CYDEV_MFGCFG_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_SIZE +CYDEV_MFGCFG_SIZE EQU 0x000000ed + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE +CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE +CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE +CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE +CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_TR +CYREG_DAC0_TR EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE +CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE +CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_TR +CYREG_DAC1_TR EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE +CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE +CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_TR +CYREG_DAC2_TR EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE +CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE +CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_TR +CYREG_DAC3_TR EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_DSM_TR0 +CYREG_NPUMP_DSM_TR0 EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_SC_TR0 +CYREG_NPUMP_SC_TR0 EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_OPAMP_TR0 +CYREG_NPUMP_OPAMP_TR0 EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE +CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE +CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_TR0 +CYREG_SAR0_TR0 EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE +CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE +CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_TR0 +CYREG_SAR1_TR0 EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE +CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_TR0 +CYREG_OPAMP0_TR0 EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_TR1 +CYREG_OPAMP0_TR1 EQU 0x40004621 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE +CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_TR0 +CYREG_OPAMP1_TR0 EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_TR1 +CYREG_OPAMP1_TR1 EQU 0x40004623 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE +CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_TR0 +CYREG_OPAMP2_TR0 EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_TR1 +CYREG_OPAMP2_TR1 EQU 0x40004625 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE +CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_TR0 +CYREG_OPAMP3_TR0 EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_TR1 +CYREG_OPAMP3_TR1 EQU 0x40004627 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE +CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE +CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_TR0 +CYREG_CMP0_TR0 EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_TR1 +CYREG_CMP0_TR1 EQU 0x40004631 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE +CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE +CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_TR0 +CYREG_CMP1_TR0 EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_TR1 +CYREG_CMP1_TR1 EQU 0x40004633 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE +CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE +CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_TR0 +CYREG_CMP2_TR0 EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_TR1 +CYREG_CMP2_TR1 EQU 0x40004635 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE +CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE +CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_TR0 +CYREG_CMP3_TR0 EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_TR1 +CYREG_CMP3_TR1 EQU 0x40004637 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE +CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE +CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR0 +CYREG_PWRSYS_HIB_TR0 EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR1 +CYREG_PWRSYS_HIB_TR1 EQU 0x40004681 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_I2C_TR +CYREG_PWRSYS_I2C_TR EQU 0x40004682 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_SLP_TR +CYREG_PWRSYS_SLP_TR EQU 0x40004683 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BUZZ_TR +CYREG_PWRSYS_BUZZ_TR EQU 0x40004684 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR0 +CYREG_PWRSYS_WAKE_TR0 EQU 0x40004685 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR1 +CYREG_PWRSYS_WAKE_TR1 EQU 0x40004686 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BREF_TR +CYREG_PWRSYS_BREF_TR EQU 0x40004687 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BG_TR +CYREG_PWRSYS_BG_TR EQU 0x40004688 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR2 +CYREG_PWRSYS_WAKE_TR2 EQU 0x40004689 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR3 +CYREG_PWRSYS_WAKE_TR3 EQU 0x4000468a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE +CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE +CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_ILO_TR0 +CYREG_ILO_TR0 EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYREG_ILO_TR1 +CYREG_ILO_TR1 EQU 0x40004691 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE +CYDEV_MFGCFG_X32_BASE EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE +CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_X32_TR +CYREG_X32_TR EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE +CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE +CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR0 +CYREG_IMO_TR0 EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR1 +CYREG_IMO_TR1 EQU 0x400046a1 + ENDIF + IF :LNOT::DEF:CYREG_IMO_GAIN +CYREG_IMO_GAIN EQU 0x400046a2 + ENDIF + IF :LNOT::DEF:CYREG_IMO_C36M +CYREG_IMO_C36M EQU 0x400046a3 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR2 +CYREG_IMO_TR2 EQU 0x400046a4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE +CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE +CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_XMHZ_TR +CYREG_XMHZ_TR EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYREG_MFGCFG_DLY +CYREG_MFGCFG_DLY EQU 0x400046c0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE +CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE +CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_DMPSTR +CYREG_MLOGIC_DMPSTR EQU 0x400046e2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE +CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE +CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_SEG_CR +CYREG_MLOGIC_SEG_CR EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_SEG_CFG0 +CYREG_MLOGIC_SEG_CFG0 EQU 0x400046e5 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_DEBUG +CYREG_MLOGIC_DEBUG EQU 0x400046e8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_CPU_SCR_CPU_SCR +CYREG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_REV_ID +CYREG_MLOGIC_REV_ID EQU 0x400046ec + ENDIF + IF :LNOT::DEF:CYDEV_RESET_BASE +CYDEV_RESET_BASE EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SIZE +CYDEV_RESET_SIZE EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR0 +CYREG_RESET_IPOR_CR0 EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR1 +CYREG_RESET_IPOR_CR1 EQU 0x400046f1 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR2 +CYREG_RESET_IPOR_CR2 EQU 0x400046f2 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR3 +CYREG_RESET_IPOR_CR3 EQU 0x400046f3 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR0 +CYREG_RESET_CR0 EQU 0x400046f4 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR1 +CYREG_RESET_CR1 EQU 0x400046f5 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR2 +CYREG_RESET_CR2 EQU 0x400046f6 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR3 +CYREG_RESET_CR3 EQU 0x400046f7 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR4 +CYREG_RESET_CR4 EQU 0x400046f8 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR5 +CYREG_RESET_CR5 EQU 0x400046f9 + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR0 +CYREG_RESET_SR0 EQU 0x400046fa + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR1 +CYREG_RESET_SR1 EQU 0x400046fb + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR2 +CYREG_RESET_SR2 EQU 0x400046fc + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR3 +CYREG_RESET_SR3 EQU 0x400046fd + ENDIF + IF :LNOT::DEF:CYREG_RESET_TR +CYREG_RESET_TR EQU 0x400046fe + ENDIF + IF :LNOT::DEF:CYDEV_SPC_BASE +CYDEV_SPC_BASE EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SIZE +CYDEV_SPC_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_SPC_FM_EE_CR +CYREG_SPC_FM_EE_CR EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYREG_SPC_FM_EE_WAKE_CNT +CYREG_SPC_FM_EE_WAKE_CNT EQU 0x40004701 + ENDIF + IF :LNOT::DEF:CYREG_SPC_EE_SCR +CYREG_SPC_EE_SCR EQU 0x40004702 + ENDIF + IF :LNOT::DEF:CYREG_SPC_EE_ERR +CYREG_SPC_EE_ERR EQU 0x40004703 + ENDIF + IF :LNOT::DEF:CYREG_SPC_CPU_DATA +CYREG_SPC_CPU_DATA EQU 0x40004720 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMA_DATA +CYREG_SPC_DMA_DATA EQU 0x40004721 + ENDIF + IF :LNOT::DEF:CYREG_SPC_SR +CYREG_SPC_SR EQU 0x40004722 + ENDIF + IF :LNOT::DEF:CYREG_SPC_CR +CYREG_SPC_CR EQU 0x40004723 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE +CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE +CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MBASE +CYREG_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MSIZE +CYREG_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_BASE +CYDEV_CACHE_BASE EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_SIZE +CYDEV_CACHE_SIZE EQU 0x0000009c + ENDIF + IF :LNOT::DEF:CYREG_CACHE_CC_CTL +CYREG_CACHE_CC_CTL EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_ECC_CORR +CYREG_CACHE_ECC_CORR EQU 0x40004880 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_ECC_ERR +CYREG_CACHE_ECC_ERR EQU 0x40004888 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_FLASH_ERR +CYREG_CACHE_FLASH_ERR EQU 0x40004890 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_HITMISS +CYREG_CACHE_HITMISS EQU 0x40004898 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_BASE +CYDEV_I2C_BASE EQU 0x40004900 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_SIZE +CYDEV_I2C_SIZE EQU 0x000000e1 + ENDIF + IF :LNOT::DEF:CYREG_I2C_XCFG +CYREG_I2C_XCFG EQU 0x400049c8 + ENDIF + IF :LNOT::DEF:CYREG_I2C_ADR +CYREG_I2C_ADR EQU 0x400049ca + ENDIF + IF :LNOT::DEF:CYREG_I2C_CFG +CYREG_I2C_CFG EQU 0x400049d6 + ENDIF + IF :LNOT::DEF:CYREG_I2C_CSR +CYREG_I2C_CSR EQU 0x400049d7 + ENDIF + IF :LNOT::DEF:CYREG_I2C_D +CYREG_I2C_D EQU 0x400049d8 + ENDIF + IF :LNOT::DEF:CYREG_I2C_MCSR +CYREG_I2C_MCSR EQU 0x400049d9 + ENDIF + IF :LNOT::DEF:CYREG_I2C_CLK_DIV1 +CYREG_I2C_CLK_DIV1 EQU 0x400049db + ENDIF + IF :LNOT::DEF:CYREG_I2C_CLK_DIV2 +CYREG_I2C_CLK_DIV2 EQU 0x400049dc + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CSR +CYREG_I2C_TMOUT_CSR EQU 0x400049dd + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_SR +CYREG_I2C_TMOUT_SR EQU 0x400049de + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG0 +CYREG_I2C_TMOUT_CFG0 EQU 0x400049df + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG1 +CYREG_I2C_TMOUT_CFG1 EQU 0x400049e0 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_BASE +CYDEV_DEC_BASE EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SIZE +CYDEV_DEC_SIZE EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYREG_DEC_CR +CYREG_DEC_CR EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SR +CYREG_DEC_SR EQU 0x40004e01 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SHIFT1 +CYREG_DEC_SHIFT1 EQU 0x40004e02 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SHIFT2 +CYREG_DEC_SHIFT2 EQU 0x40004e03 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR2 +CYREG_DEC_DR2 EQU 0x40004e04 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR2H +CYREG_DEC_DR2H EQU 0x40004e05 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR1 +CYREG_DEC_DR1 EQU 0x40004e06 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCOR +CYREG_DEC_OCOR EQU 0x40004e08 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCORM +CYREG_DEC_OCORM EQU 0x40004e09 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCORH +CYREG_DEC_OCORH EQU 0x40004e0a + ENDIF + IF :LNOT::DEF:CYREG_DEC_GCOR +CYREG_DEC_GCOR EQU 0x40004e0c + ENDIF + IF :LNOT::DEF:CYREG_DEC_GCORH +CYREG_DEC_GCORH EQU 0x40004e0d + ENDIF + IF :LNOT::DEF:CYREG_DEC_GVAL +CYREG_DEC_GVAL EQU 0x40004e0e + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMP +CYREG_DEC_OUTSAMP EQU 0x40004e10 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPM +CYREG_DEC_OUTSAMPM EQU 0x40004e11 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPH +CYREG_DEC_OUTSAMPH EQU 0x40004e12 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPS +CYREG_DEC_OUTSAMPS EQU 0x40004e13 + ENDIF + IF :LNOT::DEF:CYREG_DEC_COHER +CYREG_DEC_COHER EQU 0x40004e14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_BASE +CYDEV_TMR0_BASE EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SIZE +CYDEV_TMR0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG0 +CYREG_TMR0_CFG0 EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG1 +CYREG_TMR0_CFG1 EQU 0x40004f01 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG2 +CYREG_TMR0_CFG2 EQU 0x40004f02 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_SR0 +CYREG_TMR0_SR0 EQU 0x40004f03 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_PER0 +CYREG_TMR0_PER0 EQU 0x40004f04 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_PER1 +CYREG_TMR0_PER1 EQU 0x40004f05 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CNT_CMP0 +CYREG_TMR0_CNT_CMP0 EQU 0x40004f06 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CNT_CMP1 +CYREG_TMR0_CNT_CMP1 EQU 0x40004f07 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CAP0 +CYREG_TMR0_CAP0 EQU 0x40004f08 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CAP1 +CYREG_TMR0_CAP1 EQU 0x40004f09 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_RT0 +CYREG_TMR0_RT0 EQU 0x40004f0a + ENDIF + IF :LNOT::DEF:CYREG_TMR0_RT1 +CYREG_TMR0_RT1 EQU 0x40004f0b + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_BASE +CYDEV_TMR1_BASE EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SIZE +CYDEV_TMR1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG0 +CYREG_TMR1_CFG0 EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG1 +CYREG_TMR1_CFG1 EQU 0x40004f0d + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG2 +CYREG_TMR1_CFG2 EQU 0x40004f0e + ENDIF + IF :LNOT::DEF:CYREG_TMR1_SR0 +CYREG_TMR1_SR0 EQU 0x40004f0f + ENDIF + IF :LNOT::DEF:CYREG_TMR1_PER0 +CYREG_TMR1_PER0 EQU 0x40004f10 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_PER1 +CYREG_TMR1_PER1 EQU 0x40004f11 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CNT_CMP0 +CYREG_TMR1_CNT_CMP0 EQU 0x40004f12 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CNT_CMP1 +CYREG_TMR1_CNT_CMP1 EQU 0x40004f13 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CAP0 +CYREG_TMR1_CAP0 EQU 0x40004f14 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CAP1 +CYREG_TMR1_CAP1 EQU 0x40004f15 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_RT0 +CYREG_TMR1_RT0 EQU 0x40004f16 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_RT1 +CYREG_TMR1_RT1 EQU 0x40004f17 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_BASE +CYDEV_TMR2_BASE EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SIZE +CYDEV_TMR2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG0 +CYREG_TMR2_CFG0 EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG1 +CYREG_TMR2_CFG1 EQU 0x40004f19 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG2 +CYREG_TMR2_CFG2 EQU 0x40004f1a + ENDIF + IF :LNOT::DEF:CYREG_TMR2_SR0 +CYREG_TMR2_SR0 EQU 0x40004f1b + ENDIF + IF :LNOT::DEF:CYREG_TMR2_PER0 +CYREG_TMR2_PER0 EQU 0x40004f1c + ENDIF + IF :LNOT::DEF:CYREG_TMR2_PER1 +CYREG_TMR2_PER1 EQU 0x40004f1d + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CNT_CMP0 +CYREG_TMR2_CNT_CMP0 EQU 0x40004f1e + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CNT_CMP1 +CYREG_TMR2_CNT_CMP1 EQU 0x40004f1f + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CAP0 +CYREG_TMR2_CAP0 EQU 0x40004f20 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CAP1 +CYREG_TMR2_CAP1 EQU 0x40004f21 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_RT0 +CYREG_TMR2_RT0 EQU 0x40004f22 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_RT1 +CYREG_TMR2_RT1 EQU 0x40004f23 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_BASE +CYDEV_TMR3_BASE EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SIZE +CYDEV_TMR3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG0 +CYREG_TMR3_CFG0 EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG1 +CYREG_TMR3_CFG1 EQU 0x40004f25 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG2 +CYREG_TMR3_CFG2 EQU 0x40004f26 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_SR0 +CYREG_TMR3_SR0 EQU 0x40004f27 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_PER0 +CYREG_TMR3_PER0 EQU 0x40004f28 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_PER1 +CYREG_TMR3_PER1 EQU 0x40004f29 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CNT_CMP0 +CYREG_TMR3_CNT_CMP0 EQU 0x40004f2a + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CNT_CMP1 +CYREG_TMR3_CNT_CMP1 EQU 0x40004f2b + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CAP0 +CYREG_TMR3_CAP0 EQU 0x40004f2c + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CAP1 +CYREG_TMR3_CAP1 EQU 0x40004f2d + ENDIF + IF :LNOT::DEF:CYREG_TMR3_RT0 +CYREG_TMR3_RT0 EQU 0x40004f2e + ENDIF + IF :LNOT::DEF:CYREG_TMR3_RT1 +CYREG_TMR3_RT1 EQU 0x40004f2f + ENDIF + IF :LNOT::DEF:CYDEV_IO_BASE +CYDEV_IO_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_SIZE +CYDEV_IO_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_BASE +CYDEV_IO_PC_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_SIZE +CYDEV_IO_PC_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE +CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE +CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC0 +CYREG_PRT0_PC0 EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC1 +CYREG_PRT0_PC1 EQU 0x40005001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC2 +CYREG_PRT0_PC2 EQU 0x40005002 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC3 +CYREG_PRT0_PC3 EQU 0x40005003 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC4 +CYREG_PRT0_PC4 EQU 0x40005004 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC5 +CYREG_PRT0_PC5 EQU 0x40005005 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC6 +CYREG_PRT0_PC6 EQU 0x40005006 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC7 +CYREG_PRT0_PC7 EQU 0x40005007 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE +CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE +CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC0 +CYREG_PRT1_PC0 EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC1 +CYREG_PRT1_PC1 EQU 0x40005009 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC2 +CYREG_PRT1_PC2 EQU 0x4000500a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC3 +CYREG_PRT1_PC3 EQU 0x4000500b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC4 +CYREG_PRT1_PC4 EQU 0x4000500c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC5 +CYREG_PRT1_PC5 EQU 0x4000500d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC6 +CYREG_PRT1_PC6 EQU 0x4000500e + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC7 +CYREG_PRT1_PC7 EQU 0x4000500f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE +CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE +CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC0 +CYREG_PRT2_PC0 EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC1 +CYREG_PRT2_PC1 EQU 0x40005011 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC2 +CYREG_PRT2_PC2 EQU 0x40005012 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC3 +CYREG_PRT2_PC3 EQU 0x40005013 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC4 +CYREG_PRT2_PC4 EQU 0x40005014 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC5 +CYREG_PRT2_PC5 EQU 0x40005015 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC6 +CYREG_PRT2_PC6 EQU 0x40005016 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC7 +CYREG_PRT2_PC7 EQU 0x40005017 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE +CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE +CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC0 +CYREG_PRT3_PC0 EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC1 +CYREG_PRT3_PC1 EQU 0x40005019 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC2 +CYREG_PRT3_PC2 EQU 0x4000501a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC3 +CYREG_PRT3_PC3 EQU 0x4000501b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC4 +CYREG_PRT3_PC4 EQU 0x4000501c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC5 +CYREG_PRT3_PC5 EQU 0x4000501d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC6 +CYREG_PRT3_PC6 EQU 0x4000501e + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC7 +CYREG_PRT3_PC7 EQU 0x4000501f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE +CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE +CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC0 +CYREG_PRT4_PC0 EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC1 +CYREG_PRT4_PC1 EQU 0x40005021 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC2 +CYREG_PRT4_PC2 EQU 0x40005022 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC3 +CYREG_PRT4_PC3 EQU 0x40005023 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC4 +CYREG_PRT4_PC4 EQU 0x40005024 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC5 +CYREG_PRT4_PC5 EQU 0x40005025 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC6 +CYREG_PRT4_PC6 EQU 0x40005026 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC7 +CYREG_PRT4_PC7 EQU 0x40005027 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE +CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE +CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC0 +CYREG_PRT5_PC0 EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC1 +CYREG_PRT5_PC1 EQU 0x40005029 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC2 +CYREG_PRT5_PC2 EQU 0x4000502a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC3 +CYREG_PRT5_PC3 EQU 0x4000502b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC4 +CYREG_PRT5_PC4 EQU 0x4000502c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC5 +CYREG_PRT5_PC5 EQU 0x4000502d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC6 +CYREG_PRT5_PC6 EQU 0x4000502e + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC7 +CYREG_PRT5_PC7 EQU 0x4000502f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE +CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE +CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC0 +CYREG_PRT6_PC0 EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC1 +CYREG_PRT6_PC1 EQU 0x40005031 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC2 +CYREG_PRT6_PC2 EQU 0x40005032 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC3 +CYREG_PRT6_PC3 EQU 0x40005033 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC4 +CYREG_PRT6_PC4 EQU 0x40005034 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC5 +CYREG_PRT6_PC5 EQU 0x40005035 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC6 +CYREG_PRT6_PC6 EQU 0x40005036 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC7 +CYREG_PRT6_PC7 EQU 0x40005037 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE +CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE +CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC0 +CYREG_PRT12_PC0 EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC1 +CYREG_PRT12_PC1 EQU 0x40005061 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC2 +CYREG_PRT12_PC2 EQU 0x40005062 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC3 +CYREG_PRT12_PC3 EQU 0x40005063 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC4 +CYREG_PRT12_PC4 EQU 0x40005064 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC5 +CYREG_PRT12_PC5 EQU 0x40005065 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC6 +CYREG_PRT12_PC6 EQU 0x40005066 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC7 +CYREG_PRT12_PC7 EQU 0x40005067 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE +CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE +CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC0 +CYREG_IO_PC_PRT15_PC0 EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC1 +CYREG_IO_PC_PRT15_PC1 EQU 0x40005079 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC2 +CYREG_IO_PC_PRT15_PC2 EQU 0x4000507a + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC3 +CYREG_IO_PC_PRT15_PC3 EQU 0x4000507b + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC4 +CYREG_IO_PC_PRT15_PC4 EQU 0x4000507c + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC5 +CYREG_IO_PC_PRT15_PC5 EQU 0x4000507d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE +CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE +CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC0 +CYREG_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC1 +CYREG_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_BASE +CYDEV_IO_DR_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_SIZE +CYDEV_IO_DR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE +CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE +CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR_ALIAS +CYREG_PRT0_DR_ALIAS EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE +CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE +CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR_ALIAS +CYREG_PRT1_DR_ALIAS EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE +CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE +CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR_ALIAS +CYREG_PRT2_DR_ALIAS EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE +CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE +CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR_ALIAS +CYREG_PRT3_DR_ALIAS EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE +CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE +CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR_ALIAS +CYREG_PRT4_DR_ALIAS EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE +CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE +CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DR_ALIAS +CYREG_PRT5_DR_ALIAS EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE +CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE +CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DR_ALIAS +CYREG_PRT6_DR_ALIAS EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE +CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE +CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DR_ALIAS +CYREG_PRT12_DR_ALIAS EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE +CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE +CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DR_15_ALIAS +CYREG_PRT15_DR_15_ALIAS EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_BASE +CYDEV_IO_PS_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_SIZE +CYDEV_IO_PS_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE +CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE +CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS_ALIAS +CYREG_PRT0_PS_ALIAS EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE +CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE +CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS_ALIAS +CYREG_PRT1_PS_ALIAS EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE +CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE +CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS_ALIAS +CYREG_PRT2_PS_ALIAS EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE +CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE +CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS_ALIAS +CYREG_PRT3_PS_ALIAS EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE +CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE +CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS_ALIAS +CYREG_PRT4_PS_ALIAS EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE +CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE +CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PS_ALIAS +CYREG_PRT5_PS_ALIAS EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE +CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE +CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PS_ALIAS +CYREG_PRT6_PS_ALIAS EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE +CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE +CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PS_ALIAS +CYREG_PRT12_PS_ALIAS EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE +CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE +CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PS15_ALIAS +CYREG_PRT15_PS15_ALIAS EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_BASE +CYDEV_IO_PRT_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_SIZE +CYDEV_IO_PRT_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE +CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE +CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR +CYREG_PRT0_DR EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS +CYREG_PRT0_PS EQU 0x40005101 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM0 +CYREG_PRT0_DM0 EQU 0x40005102 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM1 +CYREG_PRT0_DM1 EQU 0x40005103 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM2 +CYREG_PRT0_DM2 EQU 0x40005104 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_SLW +CYREG_PRT0_SLW EQU 0x40005105 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BYP +CYREG_PRT0_BYP EQU 0x40005106 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BIE +CYREG_PRT0_BIE EQU 0x40005107 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_INP_DIS +CYREG_PRT0_INP_DIS EQU 0x40005108 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_CTL +CYREG_PRT0_CTL EQU 0x40005109 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PRT +CYREG_PRT0_PRT EQU 0x4000510a + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BIT_MASK +CYREG_PRT0_BIT_MASK EQU 0x4000510b + ENDIF + IF :LNOT::DEF:CYREG_PRT0_AMUX +CYREG_PRT0_AMUX EQU 0x4000510c + ENDIF + IF :LNOT::DEF:CYREG_PRT0_AG +CYREG_PRT0_AG EQU 0x4000510d + ENDIF + IF :LNOT::DEF:CYREG_PRT0_LCD_COM_SEG +CYREG_PRT0_LCD_COM_SEG EQU 0x4000510e + ENDIF + IF :LNOT::DEF:CYREG_PRT0_LCD_EN +CYREG_PRT0_LCD_EN EQU 0x4000510f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE +CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE +CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR +CYREG_PRT1_DR EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS +CYREG_PRT1_PS EQU 0x40005111 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM0 +CYREG_PRT1_DM0 EQU 0x40005112 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM1 +CYREG_PRT1_DM1 EQU 0x40005113 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM2 +CYREG_PRT1_DM2 EQU 0x40005114 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_SLW +CYREG_PRT1_SLW EQU 0x40005115 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BYP +CYREG_PRT1_BYP EQU 0x40005116 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BIE +CYREG_PRT1_BIE EQU 0x40005117 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_INP_DIS +CYREG_PRT1_INP_DIS EQU 0x40005118 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_CTL +CYREG_PRT1_CTL EQU 0x40005119 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PRT +CYREG_PRT1_PRT EQU 0x4000511a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BIT_MASK +CYREG_PRT1_BIT_MASK EQU 0x4000511b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_AMUX +CYREG_PRT1_AMUX EQU 0x4000511c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_AG +CYREG_PRT1_AG EQU 0x4000511d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_LCD_COM_SEG +CYREG_PRT1_LCD_COM_SEG EQU 0x4000511e + ENDIF + IF :LNOT::DEF:CYREG_PRT1_LCD_EN +CYREG_PRT1_LCD_EN EQU 0x4000511f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE +CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE +CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR +CYREG_PRT2_DR EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS +CYREG_PRT2_PS EQU 0x40005121 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM0 +CYREG_PRT2_DM0 EQU 0x40005122 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM1 +CYREG_PRT2_DM1 EQU 0x40005123 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM2 +CYREG_PRT2_DM2 EQU 0x40005124 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_SLW +CYREG_PRT2_SLW EQU 0x40005125 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BYP +CYREG_PRT2_BYP EQU 0x40005126 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BIE +CYREG_PRT2_BIE EQU 0x40005127 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_INP_DIS +CYREG_PRT2_INP_DIS EQU 0x40005128 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_CTL +CYREG_PRT2_CTL EQU 0x40005129 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PRT +CYREG_PRT2_PRT EQU 0x4000512a + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BIT_MASK +CYREG_PRT2_BIT_MASK EQU 0x4000512b + ENDIF + IF :LNOT::DEF:CYREG_PRT2_AMUX +CYREG_PRT2_AMUX EQU 0x4000512c + ENDIF + IF :LNOT::DEF:CYREG_PRT2_AG +CYREG_PRT2_AG EQU 0x4000512d + ENDIF + IF :LNOT::DEF:CYREG_PRT2_LCD_COM_SEG +CYREG_PRT2_LCD_COM_SEG EQU 0x4000512e + ENDIF + IF :LNOT::DEF:CYREG_PRT2_LCD_EN +CYREG_PRT2_LCD_EN EQU 0x4000512f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE +CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE +CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR +CYREG_PRT3_DR EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS +CYREG_PRT3_PS EQU 0x40005131 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM0 +CYREG_PRT3_DM0 EQU 0x40005132 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM1 +CYREG_PRT3_DM1 EQU 0x40005133 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM2 +CYREG_PRT3_DM2 EQU 0x40005134 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_SLW +CYREG_PRT3_SLW EQU 0x40005135 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BYP +CYREG_PRT3_BYP EQU 0x40005136 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BIE +CYREG_PRT3_BIE EQU 0x40005137 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_INP_DIS +CYREG_PRT3_INP_DIS EQU 0x40005138 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_CTL +CYREG_PRT3_CTL EQU 0x40005139 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PRT +CYREG_PRT3_PRT EQU 0x4000513a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BIT_MASK +CYREG_PRT3_BIT_MASK EQU 0x4000513b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_AMUX +CYREG_PRT3_AMUX EQU 0x4000513c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_AG +CYREG_PRT3_AG EQU 0x4000513d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_LCD_COM_SEG +CYREG_PRT3_LCD_COM_SEG EQU 0x4000513e + ENDIF + IF :LNOT::DEF:CYREG_PRT3_LCD_EN +CYREG_PRT3_LCD_EN EQU 0x4000513f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE +CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE +CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR +CYREG_PRT4_DR EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS +CYREG_PRT4_PS EQU 0x40005141 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM0 +CYREG_PRT4_DM0 EQU 0x40005142 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM1 +CYREG_PRT4_DM1 EQU 0x40005143 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM2 +CYREG_PRT4_DM2 EQU 0x40005144 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_SLW +CYREG_PRT4_SLW EQU 0x40005145 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BYP +CYREG_PRT4_BYP EQU 0x40005146 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BIE +CYREG_PRT4_BIE EQU 0x40005147 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_INP_DIS +CYREG_PRT4_INP_DIS EQU 0x40005148 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_CTL +CYREG_PRT4_CTL EQU 0x40005149 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PRT +CYREG_PRT4_PRT EQU 0x4000514a + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BIT_MASK +CYREG_PRT4_BIT_MASK EQU 0x4000514b + ENDIF + IF :LNOT::DEF:CYREG_PRT4_AMUX +CYREG_PRT4_AMUX EQU 0x4000514c + ENDIF + IF :LNOT::DEF:CYREG_PRT4_AG +CYREG_PRT4_AG EQU 0x4000514d + ENDIF + IF :LNOT::DEF:CYREG_PRT4_LCD_COM_SEG +CYREG_PRT4_LCD_COM_SEG EQU 0x4000514e + ENDIF + IF :LNOT::DEF:CYREG_PRT4_LCD_EN +CYREG_PRT4_LCD_EN EQU 0x4000514f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE +CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE +CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DR +CYREG_PRT5_DR EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PS +CYREG_PRT5_PS EQU 0x40005151 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM0 +CYREG_PRT5_DM0 EQU 0x40005152 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM1 +CYREG_PRT5_DM1 EQU 0x40005153 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM2 +CYREG_PRT5_DM2 EQU 0x40005154 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_SLW +CYREG_PRT5_SLW EQU 0x40005155 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BYP +CYREG_PRT5_BYP EQU 0x40005156 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BIE +CYREG_PRT5_BIE EQU 0x40005157 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_INP_DIS +CYREG_PRT5_INP_DIS EQU 0x40005158 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_CTL +CYREG_PRT5_CTL EQU 0x40005159 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PRT +CYREG_PRT5_PRT EQU 0x4000515a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BIT_MASK +CYREG_PRT5_BIT_MASK EQU 0x4000515b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_AMUX +CYREG_PRT5_AMUX EQU 0x4000515c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_AG +CYREG_PRT5_AG EQU 0x4000515d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_LCD_COM_SEG +CYREG_PRT5_LCD_COM_SEG EQU 0x4000515e + ENDIF + IF :LNOT::DEF:CYREG_PRT5_LCD_EN +CYREG_PRT5_LCD_EN EQU 0x4000515f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE +CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE +CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DR +CYREG_PRT6_DR EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PS +CYREG_PRT6_PS EQU 0x40005161 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM0 +CYREG_PRT6_DM0 EQU 0x40005162 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM1 +CYREG_PRT6_DM1 EQU 0x40005163 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM2 +CYREG_PRT6_DM2 EQU 0x40005164 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_SLW +CYREG_PRT6_SLW EQU 0x40005165 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BYP +CYREG_PRT6_BYP EQU 0x40005166 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BIE +CYREG_PRT6_BIE EQU 0x40005167 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_INP_DIS +CYREG_PRT6_INP_DIS EQU 0x40005168 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_CTL +CYREG_PRT6_CTL EQU 0x40005169 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PRT +CYREG_PRT6_PRT EQU 0x4000516a + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BIT_MASK +CYREG_PRT6_BIT_MASK EQU 0x4000516b + ENDIF + IF :LNOT::DEF:CYREG_PRT6_AMUX +CYREG_PRT6_AMUX EQU 0x4000516c + ENDIF + IF :LNOT::DEF:CYREG_PRT6_AG +CYREG_PRT6_AG EQU 0x4000516d + ENDIF + IF :LNOT::DEF:CYREG_PRT6_LCD_COM_SEG +CYREG_PRT6_LCD_COM_SEG EQU 0x4000516e + ENDIF + IF :LNOT::DEF:CYREG_PRT6_LCD_EN +CYREG_PRT6_LCD_EN EQU 0x4000516f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE +CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE +CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DR +CYREG_PRT12_DR EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PS +CYREG_PRT12_PS EQU 0x400051c1 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM0 +CYREG_PRT12_DM0 EQU 0x400051c2 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM1 +CYREG_PRT12_DM1 EQU 0x400051c3 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM2 +CYREG_PRT12_DM2 EQU 0x400051c4 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SLW +CYREG_PRT12_SLW EQU 0x400051c5 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BYP +CYREG_PRT12_BYP EQU 0x400051c6 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BIE +CYREG_PRT12_BIE EQU 0x400051c7 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_INP_DIS +CYREG_PRT12_INP_DIS EQU 0x400051c8 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_HYST_EN +CYREG_PRT12_SIO_HYST_EN EQU 0x400051c9 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PRT +CYREG_PRT12_PRT EQU 0x400051ca + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BIT_MASK +CYREG_PRT12_BIT_MASK EQU 0x400051cb + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_REG_HIFREQ +CYREG_PRT12_SIO_REG_HIFREQ EQU 0x400051cc + ENDIF + IF :LNOT::DEF:CYREG_PRT12_AG +CYREG_PRT12_AG EQU 0x400051cd + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_CFG +CYREG_PRT12_SIO_CFG EQU 0x400051ce + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_DIFF +CYREG_PRT12_SIO_DIFF EQU 0x400051cf + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE +CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE +CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DR +CYREG_PRT15_DR EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PS +CYREG_PRT15_PS EQU 0x400051f1 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM0 +CYREG_PRT15_DM0 EQU 0x400051f2 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM1 +CYREG_PRT15_DM1 EQU 0x400051f3 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM2 +CYREG_PRT15_DM2 EQU 0x400051f4 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_SLW +CYREG_PRT15_SLW EQU 0x400051f5 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BYP +CYREG_PRT15_BYP EQU 0x400051f6 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BIE +CYREG_PRT15_BIE EQU 0x400051f7 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_INP_DIS +CYREG_PRT15_INP_DIS EQU 0x400051f8 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_CTL +CYREG_PRT15_CTL EQU 0x400051f9 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PRT +CYREG_PRT15_PRT EQU 0x400051fa + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BIT_MASK +CYREG_PRT15_BIT_MASK EQU 0x400051fb + ENDIF + IF :LNOT::DEF:CYREG_PRT15_AMUX +CYREG_PRT15_AMUX EQU 0x400051fc + ENDIF + IF :LNOT::DEF:CYREG_PRT15_AG +CYREG_PRT15_AG EQU 0x400051fd + ENDIF + IF :LNOT::DEF:CYREG_PRT15_LCD_COM_SEG +CYREG_PRT15_LCD_COM_SEG EQU 0x400051fe + ENDIF + IF :LNOT::DEF:CYREG_PRT15_LCD_EN +CYREG_PRT15_LCD_EN EQU 0x400051ff + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_BASE +CYDEV_PRTDSI_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_SIZE +CYDEV_PRTDSI_SIZE EQU 0x0000007f + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE +CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE +CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OUT_SEL0 +CYREG_PRT0_OUT_SEL0 EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OUT_SEL1 +CYREG_PRT0_OUT_SEL1 EQU 0x40005201 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OE_SEL0 +CYREG_PRT0_OE_SEL0 EQU 0x40005202 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OE_SEL1 +CYREG_PRT0_OE_SEL1 EQU 0x40005203 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DBL_SYNC_IN +CYREG_PRT0_DBL_SYNC_IN EQU 0x40005204 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_SYNC_OUT +CYREG_PRT0_SYNC_OUT EQU 0x40005205 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_CAPS_SEL +CYREG_PRT0_CAPS_SEL EQU 0x40005206 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE +CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE +CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OUT_SEL0 +CYREG_PRT1_OUT_SEL0 EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OUT_SEL1 +CYREG_PRT1_OUT_SEL1 EQU 0x40005209 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OE_SEL0 +CYREG_PRT1_OE_SEL0 EQU 0x4000520a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OE_SEL1 +CYREG_PRT1_OE_SEL1 EQU 0x4000520b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DBL_SYNC_IN +CYREG_PRT1_DBL_SYNC_IN EQU 0x4000520c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_SYNC_OUT +CYREG_PRT1_SYNC_OUT EQU 0x4000520d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_CAPS_SEL +CYREG_PRT1_CAPS_SEL EQU 0x4000520e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE +CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE +CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OUT_SEL0 +CYREG_PRT2_OUT_SEL0 EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OUT_SEL1 +CYREG_PRT2_OUT_SEL1 EQU 0x40005211 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OE_SEL0 +CYREG_PRT2_OE_SEL0 EQU 0x40005212 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OE_SEL1 +CYREG_PRT2_OE_SEL1 EQU 0x40005213 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DBL_SYNC_IN +CYREG_PRT2_DBL_SYNC_IN EQU 0x40005214 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_SYNC_OUT +CYREG_PRT2_SYNC_OUT EQU 0x40005215 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_CAPS_SEL +CYREG_PRT2_CAPS_SEL EQU 0x40005216 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE +CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE +CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OUT_SEL0 +CYREG_PRT3_OUT_SEL0 EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OUT_SEL1 +CYREG_PRT3_OUT_SEL1 EQU 0x40005219 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OE_SEL0 +CYREG_PRT3_OE_SEL0 EQU 0x4000521a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OE_SEL1 +CYREG_PRT3_OE_SEL1 EQU 0x4000521b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DBL_SYNC_IN +CYREG_PRT3_DBL_SYNC_IN EQU 0x4000521c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_SYNC_OUT +CYREG_PRT3_SYNC_OUT EQU 0x4000521d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_CAPS_SEL +CYREG_PRT3_CAPS_SEL EQU 0x4000521e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE +CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE +CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OUT_SEL0 +CYREG_PRT4_OUT_SEL0 EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OUT_SEL1 +CYREG_PRT4_OUT_SEL1 EQU 0x40005221 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OE_SEL0 +CYREG_PRT4_OE_SEL0 EQU 0x40005222 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OE_SEL1 +CYREG_PRT4_OE_SEL1 EQU 0x40005223 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DBL_SYNC_IN +CYREG_PRT4_DBL_SYNC_IN EQU 0x40005224 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_SYNC_OUT +CYREG_PRT4_SYNC_OUT EQU 0x40005225 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_CAPS_SEL +CYREG_PRT4_CAPS_SEL EQU 0x40005226 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE +CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE +CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OUT_SEL0 +CYREG_PRT5_OUT_SEL0 EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OUT_SEL1 +CYREG_PRT5_OUT_SEL1 EQU 0x40005229 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OE_SEL0 +CYREG_PRT5_OE_SEL0 EQU 0x4000522a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OE_SEL1 +CYREG_PRT5_OE_SEL1 EQU 0x4000522b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DBL_SYNC_IN +CYREG_PRT5_DBL_SYNC_IN EQU 0x4000522c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_SYNC_OUT +CYREG_PRT5_SYNC_OUT EQU 0x4000522d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_CAPS_SEL +CYREG_PRT5_CAPS_SEL EQU 0x4000522e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE +CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE +CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OUT_SEL0 +CYREG_PRT6_OUT_SEL0 EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OUT_SEL1 +CYREG_PRT6_OUT_SEL1 EQU 0x40005231 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OE_SEL0 +CYREG_PRT6_OE_SEL0 EQU 0x40005232 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OE_SEL1 +CYREG_PRT6_OE_SEL1 EQU 0x40005233 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DBL_SYNC_IN +CYREG_PRT6_DBL_SYNC_IN EQU 0x40005234 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_SYNC_OUT +CYREG_PRT6_SYNC_OUT EQU 0x40005235 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_CAPS_SEL +CYREG_PRT6_CAPS_SEL EQU 0x40005236 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE +CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE +CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OUT_SEL0 +CYREG_PRT12_OUT_SEL0 EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OUT_SEL1 +CYREG_PRT12_OUT_SEL1 EQU 0x40005261 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OE_SEL0 +CYREG_PRT12_OE_SEL0 EQU 0x40005262 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OE_SEL1 +CYREG_PRT12_OE_SEL1 EQU 0x40005263 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DBL_SYNC_IN +CYREG_PRT12_DBL_SYNC_IN EQU 0x40005264 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SYNC_OUT +CYREG_PRT12_SYNC_OUT EQU 0x40005265 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE +CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE +CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OUT_SEL0 +CYREG_PRT15_OUT_SEL0 EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OUT_SEL1 +CYREG_PRT15_OUT_SEL1 EQU 0x40005279 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OE_SEL0 +CYREG_PRT15_OE_SEL0 EQU 0x4000527a + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OE_SEL1 +CYREG_PRT15_OE_SEL1 EQU 0x4000527b + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DBL_SYNC_IN +CYREG_PRT15_DBL_SYNC_IN EQU 0x4000527c + ENDIF + IF :LNOT::DEF:CYREG_PRT15_SYNC_OUT +CYREG_PRT15_SYNC_OUT EQU 0x4000527d + ENDIF + IF :LNOT::DEF:CYREG_PRT15_CAPS_SEL +CYREG_PRT15_CAPS_SEL EQU 0x4000527e + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_BASE +CYDEV_EMIF_BASE EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_SIZE +CYDEV_EMIF_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_NO_UDB +CYREG_EMIF_NO_UDB EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_RP_WAIT_STATES +CYREG_EMIF_RP_WAIT_STATES EQU 0x40005401 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_MEM_DWN +CYREG_EMIF_MEM_DWN EQU 0x40005402 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_MEMCLK_DIV +CYREG_EMIF_MEMCLK_DIV EQU 0x40005403 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_CLOCK_EN +CYREG_EMIF_CLOCK_EN EQU 0x40005404 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_EM_TYPE +CYREG_EMIF_EM_TYPE EQU 0x40005405 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_WP_WAIT_STATES +CYREG_EMIF_WP_WAIT_STATES EQU 0x40005406 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_BASE +CYDEV_ANAIF_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_SIZE +CYDEV_ANAIF_SIZE EQU 0x000003a9 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE +CYDEV_ANAIF_CFG_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE +CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE +CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE +CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR0 +CYREG_SC0_CR0 EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR1 +CYREG_SC0_CR1 EQU 0x40005801 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR2 +CYREG_SC0_CR2 EQU 0x40005802 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE +CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE +CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR0 +CYREG_SC1_CR0 EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR1 +CYREG_SC1_CR1 EQU 0x40005805 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR2 +CYREG_SC1_CR2 EQU 0x40005806 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE +CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE +CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR0 +CYREG_SC2_CR0 EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR1 +CYREG_SC2_CR1 EQU 0x40005809 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR2 +CYREG_SC2_CR2 EQU 0x4000580a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE +CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE +CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR0 +CYREG_SC3_CR0 EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR1 +CYREG_SC3_CR1 EQU 0x4000580d + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR2 +CYREG_SC3_CR2 EQU 0x4000580e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE +CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE +CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_CR0 +CYREG_DAC0_CR0 EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_CR1 +CYREG_DAC0_CR1 EQU 0x40005821 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_TST +CYREG_DAC0_TST EQU 0x40005822 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE +CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE +CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_CR0 +CYREG_DAC1_CR0 EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_CR1 +CYREG_DAC1_CR1 EQU 0x40005825 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_TST +CYREG_DAC1_TST EQU 0x40005826 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE +CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE +CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_CR0 +CYREG_DAC2_CR0 EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_CR1 +CYREG_DAC2_CR1 EQU 0x40005829 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_TST +CYREG_DAC2_TST EQU 0x4000582a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE +CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE +CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_CR0 +CYREG_DAC3_CR0 EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYREG_DAC3_CR1 +CYREG_DAC3_CR1 EQU 0x4000582d + ENDIF + IF :LNOT::DEF:CYREG_DAC3_TST +CYREG_DAC3_TST EQU 0x4000582e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE +CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE +CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_CR +CYREG_CMP0_CR EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE +CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE +CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_CR +CYREG_CMP1_CR EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE +CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE +CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_CR +CYREG_CMP2_CR EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE +CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE +CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_CR +CYREG_CMP3_CR EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE +CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE +CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT0_CR +CYREG_LUT0_CR EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYREG_LUT0_MX +CYREG_LUT0_MX EQU 0x40005849 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE +CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE +CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT1_CR +CYREG_LUT1_CR EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYREG_LUT1_MX +CYREG_LUT1_MX EQU 0x4000584b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE +CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE +CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT2_CR +CYREG_LUT2_CR EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYREG_LUT2_MX +CYREG_LUT2_MX EQU 0x4000584d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE +CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE +CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT3_CR +CYREG_LUT3_CR EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYREG_LUT3_MX +CYREG_LUT3_MX EQU 0x4000584f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE +CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE +CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_CR +CYREG_OPAMP0_CR EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_RSVD +CYREG_OPAMP0_RSVD EQU 0x40005859 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE +CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE +CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_CR +CYREG_OPAMP1_CR EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_RSVD +CYREG_OPAMP1_RSVD EQU 0x4000585b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE +CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE +CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_CR +CYREG_OPAMP2_CR EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_RSVD +CYREG_OPAMP2_RSVD EQU 0x4000585d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE +CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE +CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_CR +CYREG_OPAMP3_CR EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_RSVD +CYREG_OPAMP3_RSVD EQU 0x4000585f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE +CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE +CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_CR0 +CYREG_LCDDAC_CR0 EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_CR1 +CYREG_LCDDAC_CR1 EQU 0x40005869 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE +CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE +CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCDDRV_CR +CYREG_LCDDRV_CR EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE +CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE +CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCDTMR_CFG +CYREG_LCDTMR_CFG EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE +CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE +CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_BG_CR0 +CYREG_BG_CR0 EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYREG_BG_RSVD +CYREG_BG_RSVD EQU 0x4000586d + ENDIF + IF :LNOT::DEF:CYREG_BG_DFT0 +CYREG_BG_DFT0 EQU 0x4000586e + ENDIF + IF :LNOT::DEF:CYREG_BG_DFT1 +CYREG_BG_DFT1 EQU 0x4000586f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE +CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE +CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CAPSL_CFG0 +CYREG_CAPSL_CFG0 EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYREG_CAPSL_CFG1 +CYREG_CAPSL_CFG1 EQU 0x40005871 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE +CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE +CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CAPSR_CFG0 +CYREG_CAPSR_CFG0 EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYREG_CAPSR_CFG1 +CYREG_CAPSR_CFG1 EQU 0x40005873 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE +CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE +CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PUMP_CR0 +CYREG_PUMP_CR0 EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYREG_PUMP_CR1 +CYREG_PUMP_CR1 EQU 0x40005877 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE +CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE +CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LPF0_CR0 +CYREG_LPF0_CR0 EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYREG_LPF0_RSVD +CYREG_LPF0_RSVD EQU 0x40005879 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE +CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE +CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LPF1_CR0 +CYREG_LPF1_CR0 EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYREG_LPF1_RSVD +CYREG_LPF1_RSVD EQU 0x4000587b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE +CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE +CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_ANAIF_CFG_MISC_CR0 +CYREG_ANAIF_CFG_MISC_CR0 EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE +CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE +CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR0 +CYREG_DSM0_CR0 EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR1 +CYREG_DSM0_CR1 EQU 0x40005881 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR2 +CYREG_DSM0_CR2 EQU 0x40005882 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR3 +CYREG_DSM0_CR3 EQU 0x40005883 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR4 +CYREG_DSM0_CR4 EQU 0x40005884 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR5 +CYREG_DSM0_CR5 EQU 0x40005885 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR6 +CYREG_DSM0_CR6 EQU 0x40005886 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR7 +CYREG_DSM0_CR7 EQU 0x40005887 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR8 +CYREG_DSM0_CR8 EQU 0x40005888 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR9 +CYREG_DSM0_CR9 EQU 0x40005889 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR10 +CYREG_DSM0_CR10 EQU 0x4000588a + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR11 +CYREG_DSM0_CR11 EQU 0x4000588b + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR12 +CYREG_DSM0_CR12 EQU 0x4000588c + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR13 +CYREG_DSM0_CR13 EQU 0x4000588d + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR14 +CYREG_DSM0_CR14 EQU 0x4000588e + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR15 +CYREG_DSM0_CR15 EQU 0x4000588f + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR16 +CYREG_DSM0_CR16 EQU 0x40005890 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR17 +CYREG_DSM0_CR17 EQU 0x40005891 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF0 +CYREG_DSM0_REF0 EQU 0x40005892 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF1 +CYREG_DSM0_REF1 EQU 0x40005893 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF2 +CYREG_DSM0_REF2 EQU 0x40005894 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF3 +CYREG_DSM0_REF3 EQU 0x40005895 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_DEM0 +CYREG_DSM0_DEM0 EQU 0x40005896 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_DEM1 +CYREG_DSM0_DEM1 EQU 0x40005897 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_TST0 +CYREG_DSM0_TST0 EQU 0x40005898 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_TST1 +CYREG_DSM0_TST1 EQU 0x40005899 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF0 +CYREG_DSM0_BUF0 EQU 0x4000589a + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF1 +CYREG_DSM0_BUF1 EQU 0x4000589b + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF2 +CYREG_DSM0_BUF2 EQU 0x4000589c + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF3 +CYREG_DSM0_BUF3 EQU 0x4000589d + ENDIF + IF :LNOT::DEF:CYREG_DSM0_MISC +CYREG_DSM0_MISC EQU 0x4000589e + ENDIF + IF :LNOT::DEF:CYREG_DSM0_RSVD1 +CYREG_DSM0_RSVD1 EQU 0x4000589f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE +CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE +CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR0 +CYREG_SAR0_CSR0 EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR1 +CYREG_SAR0_CSR1 EQU 0x40005901 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR2 +CYREG_SAR0_CSR2 EQU 0x40005902 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR3 +CYREG_SAR0_CSR3 EQU 0x40005903 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR4 +CYREG_SAR0_CSR4 EQU 0x40005904 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR5 +CYREG_SAR0_CSR5 EQU 0x40005905 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR6 +CYREG_SAR0_CSR6 EQU 0x40005906 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE +CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE +CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR0 +CYREG_SAR1_CSR0 EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR1 +CYREG_SAR1_CSR1 EQU 0x40005909 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR2 +CYREG_SAR1_CSR2 EQU 0x4000590a + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR3 +CYREG_SAR1_CSR3 EQU 0x4000590b + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR4 +CYREG_SAR1_CSR4 EQU 0x4000590c + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR5 +CYREG_SAR1_CSR5 EQU 0x4000590d + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR6 +CYREG_SAR1_CSR6 EQU 0x4000590e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE +CYDEV_ANAIF_RT_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE +CYDEV_ANAIF_RT_SIZE EQU 0x00000162 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE +CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE +CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW0 +CYREG_SC0_SW0 EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW2 +CYREG_SC0_SW2 EQU 0x40005a02 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW3 +CYREG_SC0_SW3 EQU 0x40005a03 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW4 +CYREG_SC0_SW4 EQU 0x40005a04 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW6 +CYREG_SC0_SW6 EQU 0x40005a06 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW7 +CYREG_SC0_SW7 EQU 0x40005a07 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW8 +CYREG_SC0_SW8 EQU 0x40005a08 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW10 +CYREG_SC0_SW10 EQU 0x40005a0a + ENDIF + IF :LNOT::DEF:CYREG_SC0_CLK +CYREG_SC0_CLK EQU 0x40005a0b + ENDIF + IF :LNOT::DEF:CYREG_SC0_BST +CYREG_SC0_BST EQU 0x40005a0c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE +CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE +CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW0 +CYREG_SC1_SW0 EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW2 +CYREG_SC1_SW2 EQU 0x40005a12 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW3 +CYREG_SC1_SW3 EQU 0x40005a13 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW4 +CYREG_SC1_SW4 EQU 0x40005a14 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW6 +CYREG_SC1_SW6 EQU 0x40005a16 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW7 +CYREG_SC1_SW7 EQU 0x40005a17 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW8 +CYREG_SC1_SW8 EQU 0x40005a18 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW10 +CYREG_SC1_SW10 EQU 0x40005a1a + ENDIF + IF :LNOT::DEF:CYREG_SC1_CLK +CYREG_SC1_CLK EQU 0x40005a1b + ENDIF + IF :LNOT::DEF:CYREG_SC1_BST +CYREG_SC1_BST EQU 0x40005a1c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE +CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE +CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW0 +CYREG_SC2_SW0 EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW2 +CYREG_SC2_SW2 EQU 0x40005a22 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW3 +CYREG_SC2_SW3 EQU 0x40005a23 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW4 +CYREG_SC2_SW4 EQU 0x40005a24 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW6 +CYREG_SC2_SW6 EQU 0x40005a26 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW7 +CYREG_SC2_SW7 EQU 0x40005a27 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW8 +CYREG_SC2_SW8 EQU 0x40005a28 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW10 +CYREG_SC2_SW10 EQU 0x40005a2a + ENDIF + IF :LNOT::DEF:CYREG_SC2_CLK +CYREG_SC2_CLK EQU 0x40005a2b + ENDIF + IF :LNOT::DEF:CYREG_SC2_BST +CYREG_SC2_BST EQU 0x40005a2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE +CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE +CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW0 +CYREG_SC3_SW0 EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW2 +CYREG_SC3_SW2 EQU 0x40005a32 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW3 +CYREG_SC3_SW3 EQU 0x40005a33 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW4 +CYREG_SC3_SW4 EQU 0x40005a34 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW6 +CYREG_SC3_SW6 EQU 0x40005a36 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW7 +CYREG_SC3_SW7 EQU 0x40005a37 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW8 +CYREG_SC3_SW8 EQU 0x40005a38 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW10 +CYREG_SC3_SW10 EQU 0x40005a3a + ENDIF + IF :LNOT::DEF:CYREG_SC3_CLK +CYREG_SC3_CLK EQU 0x40005a3b + ENDIF + IF :LNOT::DEF:CYREG_SC3_BST +CYREG_SC3_BST EQU 0x40005a3c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE +CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE +CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW0 +CYREG_DAC0_SW0 EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW2 +CYREG_DAC0_SW2 EQU 0x40005a82 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW3 +CYREG_DAC0_SW3 EQU 0x40005a83 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW4 +CYREG_DAC0_SW4 EQU 0x40005a84 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_STROBE +CYREG_DAC0_STROBE EQU 0x40005a87 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE +CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE +CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW0 +CYREG_DAC1_SW0 EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW2 +CYREG_DAC1_SW2 EQU 0x40005a8a + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW3 +CYREG_DAC1_SW3 EQU 0x40005a8b + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW4 +CYREG_DAC1_SW4 EQU 0x40005a8c + ENDIF + IF :LNOT::DEF:CYREG_DAC1_STROBE +CYREG_DAC1_STROBE EQU 0x40005a8f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE +CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE +CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW0 +CYREG_DAC2_SW0 EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW2 +CYREG_DAC2_SW2 EQU 0x40005a92 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW3 +CYREG_DAC2_SW3 EQU 0x40005a93 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW4 +CYREG_DAC2_SW4 EQU 0x40005a94 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_STROBE +CYREG_DAC2_STROBE EQU 0x40005a97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE +CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE +CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW0 +CYREG_DAC3_SW0 EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW2 +CYREG_DAC3_SW2 EQU 0x40005a9a + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW3 +CYREG_DAC3_SW3 EQU 0x40005a9b + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW4 +CYREG_DAC3_SW4 EQU 0x40005a9c + ENDIF + IF :LNOT::DEF:CYREG_DAC3_STROBE +CYREG_DAC3_STROBE EQU 0x40005a9f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE +CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE +CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW0 +CYREG_CMP0_SW0 EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW2 +CYREG_CMP0_SW2 EQU 0x40005ac2 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW3 +CYREG_CMP0_SW3 EQU 0x40005ac3 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW4 +CYREG_CMP0_SW4 EQU 0x40005ac4 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW6 +CYREG_CMP0_SW6 EQU 0x40005ac6 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_CLK +CYREG_CMP0_CLK EQU 0x40005ac7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE +CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE +CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW0 +CYREG_CMP1_SW0 EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW2 +CYREG_CMP1_SW2 EQU 0x40005aca + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW3 +CYREG_CMP1_SW3 EQU 0x40005acb + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW4 +CYREG_CMP1_SW4 EQU 0x40005acc + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW6 +CYREG_CMP1_SW6 EQU 0x40005ace + ENDIF + IF :LNOT::DEF:CYREG_CMP1_CLK +CYREG_CMP1_CLK EQU 0x40005acf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE +CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE +CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW0 +CYREG_CMP2_SW0 EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW2 +CYREG_CMP2_SW2 EQU 0x40005ad2 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW3 +CYREG_CMP2_SW3 EQU 0x40005ad3 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW4 +CYREG_CMP2_SW4 EQU 0x40005ad4 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW6 +CYREG_CMP2_SW6 EQU 0x40005ad6 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_CLK +CYREG_CMP2_CLK EQU 0x40005ad7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE +CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE +CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW0 +CYREG_CMP3_SW0 EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW2 +CYREG_CMP3_SW2 EQU 0x40005ada + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW3 +CYREG_CMP3_SW3 EQU 0x40005adb + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW4 +CYREG_CMP3_SW4 EQU 0x40005adc + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW6 +CYREG_CMP3_SW6 EQU 0x40005ade + ENDIF + IF :LNOT::DEF:CYREG_CMP3_CLK +CYREG_CMP3_CLK EQU 0x40005adf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE +CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE +CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW0 +CYREG_DSM0_SW0 EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW2 +CYREG_DSM0_SW2 EQU 0x40005b02 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW3 +CYREG_DSM0_SW3 EQU 0x40005b03 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW4 +CYREG_DSM0_SW4 EQU 0x40005b04 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW6 +CYREG_DSM0_SW6 EQU 0x40005b06 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CLK +CYREG_DSM0_CLK EQU 0x40005b07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE +CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE +CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW0 +CYREG_SAR0_SW0 EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW2 +CYREG_SAR0_SW2 EQU 0x40005b22 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW3 +CYREG_SAR0_SW3 EQU 0x40005b23 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW4 +CYREG_SAR0_SW4 EQU 0x40005b24 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW6 +CYREG_SAR0_SW6 EQU 0x40005b26 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CLK +CYREG_SAR0_CLK EQU 0x40005b27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE +CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE +CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW0 +CYREG_SAR1_SW0 EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW2 +CYREG_SAR1_SW2 EQU 0x40005b2a + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW3 +CYREG_SAR1_SW3 EQU 0x40005b2b + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW4 +CYREG_SAR1_SW4 EQU 0x40005b2c + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW6 +CYREG_SAR1_SW6 EQU 0x40005b2e + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CLK +CYREG_SAR1_CLK EQU 0x40005b2f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE +CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE +CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_MX +CYREG_OPAMP0_MX EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_SW +CYREG_OPAMP0_SW EQU 0x40005b41 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE +CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE +CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_MX +CYREG_OPAMP1_MX EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_SW +CYREG_OPAMP1_SW EQU 0x40005b43 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE +CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE +CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_MX +CYREG_OPAMP2_MX EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_SW +CYREG_OPAMP2_SW EQU 0x40005b45 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE +CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE +CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_MX +CYREG_OPAMP3_MX EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_SW +CYREG_OPAMP3_SW EQU 0x40005b47 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE +CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE +CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW0 +CYREG_LCDDAC_SW0 EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW1 +CYREG_LCDDAC_SW1 EQU 0x40005b51 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW2 +CYREG_LCDDAC_SW2 EQU 0x40005b52 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW3 +CYREG_LCDDAC_SW3 EQU 0x40005b53 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW4 +CYREG_LCDDAC_SW4 EQU 0x40005b54 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE +CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE +CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SC_MISC +CYREG_SC_MISC EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE +CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE +CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW0 +CYREG_BUS_SW0 EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW2 +CYREG_BUS_SW2 EQU 0x40005b5a + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW3 +CYREG_BUS_SW3 EQU 0x40005b5b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE +CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE +CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR0 +CYREG_DFT_CR0 EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR1 +CYREG_DFT_CR1 EQU 0x40005b5d + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR2 +CYREG_DFT_CR2 EQU 0x40005b5e + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR3 +CYREG_DFT_CR3 EQU 0x40005b5f + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR4 +CYREG_DFT_CR4 EQU 0x40005b60 + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR5 +CYREG_DFT_CR5 EQU 0x40005b61 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE +CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE +CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE +CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE +CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_D +CYREG_DAC0_D EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE +CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE +CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_D +CYREG_DAC1_D EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE +CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE +CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_D +CYREG_DAC2_D EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE +CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE +CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_D +CYREG_DAC3_D EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE +CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE +CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_OUT0 +CYREG_DSM0_OUT0 EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_OUT1 +CYREG_DSM0_OUT1 EQU 0x40005b89 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE +CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE +CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LUT_SR +CYREG_LUT_SR EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYREG_LUT_WRK1 +CYREG_LUT_WRK1 EQU 0x40005b91 + ENDIF + IF :LNOT::DEF:CYREG_LUT_MSK +CYREG_LUT_MSK EQU 0x40005b92 + ENDIF + IF :LNOT::DEF:CYREG_LUT_CLK +CYREG_LUT_CLK EQU 0x40005b93 + ENDIF + IF :LNOT::DEF:CYREG_LUT_CPTR +CYREG_LUT_CPTR EQU 0x40005b94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE +CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE +CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP_WRK +CYREG_CMP_WRK EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYREG_CMP_TST +CYREG_CMP_TST EQU 0x40005b97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE +CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE +CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_SC_SR +CYREG_SC_SR EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYREG_SC_WRK1 +CYREG_SC_WRK1 EQU 0x40005b99 + ENDIF + IF :LNOT::DEF:CYREG_SC_MSK +CYREG_SC_MSK EQU 0x40005b9a + ENDIF + IF :LNOT::DEF:CYREG_SC_CMPINV +CYREG_SC_CMPINV EQU 0x40005b9b + ENDIF + IF :LNOT::DEF:CYREG_SC_CPTR +CYREG_SC_CPTR EQU 0x40005b9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE +CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE +CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_WRK0 +CYREG_SAR0_WRK0 EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_WRK1 +CYREG_SAR0_WRK1 EQU 0x40005ba1 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE +CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE +CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_WRK0 +CYREG_SAR1_WRK0 EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_WRK1 +CYREG_SAR1_WRK1 EQU 0x40005ba3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE +CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE +CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_ANAIF_WRK_SARS_SOF +CYREG_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BASE +CYDEV_USB_BASE EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIZE +CYDEV_USB_SIZE EQU 0x00000300 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR0 +CYREG_USB_EP0_DR0 EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR1 +CYREG_USB_EP0_DR1 EQU 0x40006001 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR2 +CYREG_USB_EP0_DR2 EQU 0x40006002 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR3 +CYREG_USB_EP0_DR3 EQU 0x40006003 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR4 +CYREG_USB_EP0_DR4 EQU 0x40006004 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR5 +CYREG_USB_EP0_DR5 EQU 0x40006005 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR6 +CYREG_USB_EP0_DR6 EQU 0x40006006 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR7 +CYREG_USB_EP0_DR7 EQU 0x40006007 + ENDIF + IF :LNOT::DEF:CYREG_USB_CR0 +CYREG_USB_CR0 EQU 0x40006008 + ENDIF + IF :LNOT::DEF:CYREG_USB_CR1 +CYREG_USB_CR1 EQU 0x40006009 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_EN +CYREG_USB_SIE_EP_INT_EN EQU 0x4000600a + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_SR +CYREG_USB_SIE_EP_INT_SR EQU 0x4000600b + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE +CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE +CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT0 +CYREG_USB_SIE_EP1_CNT0 EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT1 +CYREG_USB_SIE_EP1_CNT1 EQU 0x4000600d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CR0 +CYREG_USB_SIE_EP1_CR0 EQU 0x4000600e + ENDIF + IF :LNOT::DEF:CYREG_USB_USBIO_CR0 +CYREG_USB_USBIO_CR0 EQU 0x40006010 + ENDIF + IF :LNOT::DEF:CYREG_USB_USBIO_CR1 +CYREG_USB_USBIO_CR1 EQU 0x40006012 + ENDIF + IF :LNOT::DEF:CYREG_USB_DYN_RECONFIG +CYREG_USB_DYN_RECONFIG EQU 0x40006014 + ENDIF + IF :LNOT::DEF:CYREG_USB_SOF0 +CYREG_USB_SOF0 EQU 0x40006018 + ENDIF + IF :LNOT::DEF:CYREG_USB_SOF1 +CYREG_USB_SOF1 EQU 0x40006019 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE +CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE +CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT0 +CYREG_USB_SIE_EP2_CNT0 EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT1 +CYREG_USB_SIE_EP2_CNT1 EQU 0x4000601d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CR0 +CYREG_USB_SIE_EP2_CR0 EQU 0x4000601e + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_CR +CYREG_USB_EP0_CR EQU 0x40006028 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_CNT +CYREG_USB_EP0_CNT EQU 0x40006029 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE +CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE +CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT0 +CYREG_USB_SIE_EP3_CNT0 EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT1 +CYREG_USB_SIE_EP3_CNT1 EQU 0x4000602d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CR0 +CYREG_USB_SIE_EP3_CR0 EQU 0x4000602e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE +CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE +CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT0 +CYREG_USB_SIE_EP4_CNT0 EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT1 +CYREG_USB_SIE_EP4_CNT1 EQU 0x4000603d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CR0 +CYREG_USB_SIE_EP4_CR0 EQU 0x4000603e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE +CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE +CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT0 +CYREG_USB_SIE_EP5_CNT0 EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT1 +CYREG_USB_SIE_EP5_CNT1 EQU 0x4000604d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CR0 +CYREG_USB_SIE_EP5_CR0 EQU 0x4000604e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE +CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE +CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT0 +CYREG_USB_SIE_EP6_CNT0 EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT1 +CYREG_USB_SIE_EP6_CNT1 EQU 0x4000605d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CR0 +CYREG_USB_SIE_EP6_CR0 EQU 0x4000605e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE +CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE +CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT0 +CYREG_USB_SIE_EP7_CNT0 EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT1 +CYREG_USB_SIE_EP7_CNT1 EQU 0x4000606d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CR0 +CYREG_USB_SIE_EP7_CR0 EQU 0x4000606e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE +CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE +CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT0 +CYREG_USB_SIE_EP8_CNT0 EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT1 +CYREG_USB_SIE_EP8_CNT1 EQU 0x4000607d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CR0 +CYREG_USB_SIE_EP8_CR0 EQU 0x4000607e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE +CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE +CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_CFG +CYREG_USB_ARB_EP1_CFG EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_INT_EN +CYREG_USB_ARB_EP1_INT_EN EQU 0x40006081 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_SR +CYREG_USB_ARB_EP1_SR EQU 0x40006082 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE +CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE +CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA +CYREG_USB_ARB_RW1_WA EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA_MSB +CYREG_USB_ARB_RW1_WA_MSB EQU 0x40006085 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA +CYREG_USB_ARB_RW1_RA EQU 0x40006086 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA_MSB +CYREG_USB_ARB_RW1_RA_MSB EQU 0x40006087 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_DR +CYREG_USB_ARB_RW1_DR EQU 0x40006088 + ENDIF + IF :LNOT::DEF:CYREG_USB_BUF_SIZE +CYREG_USB_BUF_SIZE EQU 0x4000608c + ENDIF + IF :LNOT::DEF:CYREG_USB_EP_ACTIVE +CYREG_USB_EP_ACTIVE EQU 0x4000608e + ENDIF + IF :LNOT::DEF:CYREG_USB_EP_TYPE +CYREG_USB_EP_TYPE EQU 0x4000608f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE +CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE +CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_CFG +CYREG_USB_ARB_EP2_CFG EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_INT_EN +CYREG_USB_ARB_EP2_INT_EN EQU 0x40006091 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_SR +CYREG_USB_ARB_EP2_SR EQU 0x40006092 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE +CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE +CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA +CYREG_USB_ARB_RW2_WA EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA_MSB +CYREG_USB_ARB_RW2_WA_MSB EQU 0x40006095 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA +CYREG_USB_ARB_RW2_RA EQU 0x40006096 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA_MSB +CYREG_USB_ARB_RW2_RA_MSB EQU 0x40006097 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_DR +CYREG_USB_ARB_RW2_DR EQU 0x40006098 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_CFG +CYREG_USB_ARB_CFG EQU 0x4000609c + ENDIF + IF :LNOT::DEF:CYREG_USB_USB_CLK_EN +CYREG_USB_USB_CLK_EN EQU 0x4000609d + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_INT_EN +CYREG_USB_ARB_INT_EN EQU 0x4000609e + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_INT_SR +CYREG_USB_ARB_INT_SR EQU 0x4000609f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE +CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE +CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_CFG +CYREG_USB_ARB_EP3_CFG EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_INT_EN +CYREG_USB_ARB_EP3_INT_EN EQU 0x400060a1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_SR +CYREG_USB_ARB_EP3_SR EQU 0x400060a2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE +CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE +CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA +CYREG_USB_ARB_RW3_WA EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA_MSB +CYREG_USB_ARB_RW3_WA_MSB EQU 0x400060a5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA +CYREG_USB_ARB_RW3_RA EQU 0x400060a6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA_MSB +CYREG_USB_ARB_RW3_RA_MSB EQU 0x400060a7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_DR +CYREG_USB_ARB_RW3_DR EQU 0x400060a8 + ENDIF + IF :LNOT::DEF:CYREG_USB_CWA +CYREG_USB_CWA EQU 0x400060ac + ENDIF + IF :LNOT::DEF:CYREG_USB_CWA_MSB +CYREG_USB_CWA_MSB EQU 0x400060ad + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE +CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE +CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_CFG +CYREG_USB_ARB_EP4_CFG EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_INT_EN +CYREG_USB_ARB_EP4_INT_EN EQU 0x400060b1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_SR +CYREG_USB_ARB_EP4_SR EQU 0x400060b2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE +CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE +CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA +CYREG_USB_ARB_RW4_WA EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA_MSB +CYREG_USB_ARB_RW4_WA_MSB EQU 0x400060b5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA +CYREG_USB_ARB_RW4_RA EQU 0x400060b6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA_MSB +CYREG_USB_ARB_RW4_RA_MSB EQU 0x400060b7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_DR +CYREG_USB_ARB_RW4_DR EQU 0x400060b8 + ENDIF + IF :LNOT::DEF:CYREG_USB_DMA_THRES +CYREG_USB_DMA_THRES EQU 0x400060bc + ENDIF + IF :LNOT::DEF:CYREG_USB_DMA_THRES_MSB +CYREG_USB_DMA_THRES_MSB EQU 0x400060bd + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE +CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE +CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_CFG +CYREG_USB_ARB_EP5_CFG EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_INT_EN +CYREG_USB_ARB_EP5_INT_EN EQU 0x400060c1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_SR +CYREG_USB_ARB_EP5_SR EQU 0x400060c2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE +CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE +CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA +CYREG_USB_ARB_RW5_WA EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA_MSB +CYREG_USB_ARB_RW5_WA_MSB EQU 0x400060c5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA +CYREG_USB_ARB_RW5_RA EQU 0x400060c6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA_MSB +CYREG_USB_ARB_RW5_RA_MSB EQU 0x400060c7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_DR +CYREG_USB_ARB_RW5_DR EQU 0x400060c8 + ENDIF + IF :LNOT::DEF:CYREG_USB_BUS_RST_CNT +CYREG_USB_BUS_RST_CNT EQU 0x400060cc + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE +CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE +CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_CFG +CYREG_USB_ARB_EP6_CFG EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_INT_EN +CYREG_USB_ARB_EP6_INT_EN EQU 0x400060d1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_SR +CYREG_USB_ARB_EP6_SR EQU 0x400060d2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE +CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE +CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA +CYREG_USB_ARB_RW6_WA EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA_MSB +CYREG_USB_ARB_RW6_WA_MSB EQU 0x400060d5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA +CYREG_USB_ARB_RW6_RA EQU 0x400060d6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA_MSB +CYREG_USB_ARB_RW6_RA_MSB EQU 0x400060d7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_DR +CYREG_USB_ARB_RW6_DR EQU 0x400060d8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE +CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE +CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_CFG +CYREG_USB_ARB_EP7_CFG EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_INT_EN +CYREG_USB_ARB_EP7_INT_EN EQU 0x400060e1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_SR +CYREG_USB_ARB_EP7_SR EQU 0x400060e2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE +CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE +CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA +CYREG_USB_ARB_RW7_WA EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA_MSB +CYREG_USB_ARB_RW7_WA_MSB EQU 0x400060e5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA +CYREG_USB_ARB_RW7_RA EQU 0x400060e6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA_MSB +CYREG_USB_ARB_RW7_RA_MSB EQU 0x400060e7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_DR +CYREG_USB_ARB_RW7_DR EQU 0x400060e8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE +CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE +CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_CFG +CYREG_USB_ARB_EP8_CFG EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_INT_EN +CYREG_USB_ARB_EP8_INT_EN EQU 0x400060f1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_SR +CYREG_USB_ARB_EP8_SR EQU 0x400060f2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE +CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE +CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA +CYREG_USB_ARB_RW8_WA EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA_MSB +CYREG_USB_ARB_RW8_WA_MSB EQU 0x400060f5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA +CYREG_USB_ARB_RW8_RA EQU 0x400060f6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA_MSB +CYREG_USB_ARB_RW8_RA_MSB EQU 0x400060f7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_DR +CYREG_USB_ARB_RW8_DR EQU 0x400060f8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_BASE +CYDEV_USB_MEM_BASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_SIZE +CYDEV_USB_MEM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_USB_MEM_DATA_MBASE +CYREG_USB_MEM_DATA_MBASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYREG_USB_MEM_DATA_MSIZE +CYREG_USB_MEM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_BASE +CYDEV_UWRK_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_SIZE +CYDEV_UWRK_SIZE EQU 0x00000b60 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE +CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE +CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE +CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE +CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A0 +CYREG_B0_UDB00_A0 EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A0 +CYREG_B0_UDB01_A0 EQU 0x40006401 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A0 +CYREG_B0_UDB02_A0 EQU 0x40006402 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A0 +CYREG_B0_UDB03_A0 EQU 0x40006403 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A0 +CYREG_B0_UDB04_A0 EQU 0x40006404 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A0 +CYREG_B0_UDB05_A0 EQU 0x40006405 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A0 +CYREG_B0_UDB06_A0 EQU 0x40006406 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A0 +CYREG_B0_UDB07_A0 EQU 0x40006407 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A0 +CYREG_B0_UDB08_A0 EQU 0x40006408 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A0 +CYREG_B0_UDB09_A0 EQU 0x40006409 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A0 +CYREG_B0_UDB10_A0 EQU 0x4000640a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A0 +CYREG_B0_UDB11_A0 EQU 0x4000640b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A0 +CYREG_B0_UDB12_A0 EQU 0x4000640c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A0 +CYREG_B0_UDB13_A0 EQU 0x4000640d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A0 +CYREG_B0_UDB14_A0 EQU 0x4000640e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A0 +CYREG_B0_UDB15_A0 EQU 0x4000640f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A1 +CYREG_B0_UDB00_A1 EQU 0x40006410 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A1 +CYREG_B0_UDB01_A1 EQU 0x40006411 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A1 +CYREG_B0_UDB02_A1 EQU 0x40006412 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A1 +CYREG_B0_UDB03_A1 EQU 0x40006413 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A1 +CYREG_B0_UDB04_A1 EQU 0x40006414 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A1 +CYREG_B0_UDB05_A1 EQU 0x40006415 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A1 +CYREG_B0_UDB06_A1 EQU 0x40006416 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A1 +CYREG_B0_UDB07_A1 EQU 0x40006417 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A1 +CYREG_B0_UDB08_A1 EQU 0x40006418 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A1 +CYREG_B0_UDB09_A1 EQU 0x40006419 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A1 +CYREG_B0_UDB10_A1 EQU 0x4000641a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A1 +CYREG_B0_UDB11_A1 EQU 0x4000641b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A1 +CYREG_B0_UDB12_A1 EQU 0x4000641c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A1 +CYREG_B0_UDB13_A1 EQU 0x4000641d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A1 +CYREG_B0_UDB14_A1 EQU 0x4000641e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A1 +CYREG_B0_UDB15_A1 EQU 0x4000641f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D0 +CYREG_B0_UDB00_D0 EQU 0x40006420 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D0 +CYREG_B0_UDB01_D0 EQU 0x40006421 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D0 +CYREG_B0_UDB02_D0 EQU 0x40006422 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D0 +CYREG_B0_UDB03_D0 EQU 0x40006423 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D0 +CYREG_B0_UDB04_D0 EQU 0x40006424 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D0 +CYREG_B0_UDB05_D0 EQU 0x40006425 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D0 +CYREG_B0_UDB06_D0 EQU 0x40006426 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D0 +CYREG_B0_UDB07_D0 EQU 0x40006427 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D0 +CYREG_B0_UDB08_D0 EQU 0x40006428 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D0 +CYREG_B0_UDB09_D0 EQU 0x40006429 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D0 +CYREG_B0_UDB10_D0 EQU 0x4000642a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D0 +CYREG_B0_UDB11_D0 EQU 0x4000642b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D0 +CYREG_B0_UDB12_D0 EQU 0x4000642c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D0 +CYREG_B0_UDB13_D0 EQU 0x4000642d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D0 +CYREG_B0_UDB14_D0 EQU 0x4000642e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D0 +CYREG_B0_UDB15_D0 EQU 0x4000642f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D1 +CYREG_B0_UDB00_D1 EQU 0x40006430 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D1 +CYREG_B0_UDB01_D1 EQU 0x40006431 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D1 +CYREG_B0_UDB02_D1 EQU 0x40006432 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D1 +CYREG_B0_UDB03_D1 EQU 0x40006433 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D1 +CYREG_B0_UDB04_D1 EQU 0x40006434 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D1 +CYREG_B0_UDB05_D1 EQU 0x40006435 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D1 +CYREG_B0_UDB06_D1 EQU 0x40006436 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D1 +CYREG_B0_UDB07_D1 EQU 0x40006437 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D1 +CYREG_B0_UDB08_D1 EQU 0x40006438 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D1 +CYREG_B0_UDB09_D1 EQU 0x40006439 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D1 +CYREG_B0_UDB10_D1 EQU 0x4000643a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D1 +CYREG_B0_UDB11_D1 EQU 0x4000643b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D1 +CYREG_B0_UDB12_D1 EQU 0x4000643c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D1 +CYREG_B0_UDB13_D1 EQU 0x4000643d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D1 +CYREG_B0_UDB14_D1 EQU 0x4000643e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D1 +CYREG_B0_UDB15_D1 EQU 0x4000643f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F0 +CYREG_B0_UDB00_F0 EQU 0x40006440 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F0 +CYREG_B0_UDB01_F0 EQU 0x40006441 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F0 +CYREG_B0_UDB02_F0 EQU 0x40006442 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F0 +CYREG_B0_UDB03_F0 EQU 0x40006443 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F0 +CYREG_B0_UDB04_F0 EQU 0x40006444 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F0 +CYREG_B0_UDB05_F0 EQU 0x40006445 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F0 +CYREG_B0_UDB06_F0 EQU 0x40006446 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F0 +CYREG_B0_UDB07_F0 EQU 0x40006447 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F0 +CYREG_B0_UDB08_F0 EQU 0x40006448 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F0 +CYREG_B0_UDB09_F0 EQU 0x40006449 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F0 +CYREG_B0_UDB10_F0 EQU 0x4000644a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F0 +CYREG_B0_UDB11_F0 EQU 0x4000644b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F0 +CYREG_B0_UDB12_F0 EQU 0x4000644c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F0 +CYREG_B0_UDB13_F0 EQU 0x4000644d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F0 +CYREG_B0_UDB14_F0 EQU 0x4000644e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F0 +CYREG_B0_UDB15_F0 EQU 0x4000644f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F1 +CYREG_B0_UDB00_F1 EQU 0x40006450 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F1 +CYREG_B0_UDB01_F1 EQU 0x40006451 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F1 +CYREG_B0_UDB02_F1 EQU 0x40006452 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F1 +CYREG_B0_UDB03_F1 EQU 0x40006453 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F1 +CYREG_B0_UDB04_F1 EQU 0x40006454 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F1 +CYREG_B0_UDB05_F1 EQU 0x40006455 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F1 +CYREG_B0_UDB06_F1 EQU 0x40006456 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F1 +CYREG_B0_UDB07_F1 EQU 0x40006457 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F1 +CYREG_B0_UDB08_F1 EQU 0x40006458 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F1 +CYREG_B0_UDB09_F1 EQU 0x40006459 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F1 +CYREG_B0_UDB10_F1 EQU 0x4000645a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F1 +CYREG_B0_UDB11_F1 EQU 0x4000645b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F1 +CYREG_B0_UDB12_F1 EQU 0x4000645c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F1 +CYREG_B0_UDB13_F1 EQU 0x4000645d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F1 +CYREG_B0_UDB14_F1 EQU 0x4000645e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F1 +CYREG_B0_UDB15_F1 EQU 0x4000645f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ST +CYREG_B0_UDB00_ST EQU 0x40006460 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ST +CYREG_B0_UDB01_ST EQU 0x40006461 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ST +CYREG_B0_UDB02_ST EQU 0x40006462 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ST +CYREG_B0_UDB03_ST EQU 0x40006463 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ST +CYREG_B0_UDB04_ST EQU 0x40006464 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ST +CYREG_B0_UDB05_ST EQU 0x40006465 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ST +CYREG_B0_UDB06_ST EQU 0x40006466 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ST +CYREG_B0_UDB07_ST EQU 0x40006467 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ST +CYREG_B0_UDB08_ST EQU 0x40006468 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ST +CYREG_B0_UDB09_ST EQU 0x40006469 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ST +CYREG_B0_UDB10_ST EQU 0x4000646a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ST +CYREG_B0_UDB11_ST EQU 0x4000646b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ST +CYREG_B0_UDB12_ST EQU 0x4000646c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ST +CYREG_B0_UDB13_ST EQU 0x4000646d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ST +CYREG_B0_UDB14_ST EQU 0x4000646e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ST +CYREG_B0_UDB15_ST EQU 0x4000646f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_CTL +CYREG_B0_UDB00_CTL EQU 0x40006470 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_CTL +CYREG_B0_UDB01_CTL EQU 0x40006471 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_CTL +CYREG_B0_UDB02_CTL EQU 0x40006472 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_CTL +CYREG_B0_UDB03_CTL EQU 0x40006473 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_CTL +CYREG_B0_UDB04_CTL EQU 0x40006474 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_CTL +CYREG_B0_UDB05_CTL EQU 0x40006475 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_CTL +CYREG_B0_UDB06_CTL EQU 0x40006476 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_CTL +CYREG_B0_UDB07_CTL EQU 0x40006477 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_CTL +CYREG_B0_UDB08_CTL EQU 0x40006478 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_CTL +CYREG_B0_UDB09_CTL EQU 0x40006479 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_CTL +CYREG_B0_UDB10_CTL EQU 0x4000647a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_CTL +CYREG_B0_UDB11_CTL EQU 0x4000647b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_CTL +CYREG_B0_UDB12_CTL EQU 0x4000647c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_CTL +CYREG_B0_UDB13_CTL EQU 0x4000647d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_CTL +CYREG_B0_UDB14_CTL EQU 0x4000647e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_CTL +CYREG_B0_UDB15_CTL EQU 0x4000647f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MSK +CYREG_B0_UDB00_MSK EQU 0x40006480 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MSK +CYREG_B0_UDB01_MSK EQU 0x40006481 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MSK +CYREG_B0_UDB02_MSK EQU 0x40006482 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MSK +CYREG_B0_UDB03_MSK EQU 0x40006483 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MSK +CYREG_B0_UDB04_MSK EQU 0x40006484 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MSK +CYREG_B0_UDB05_MSK EQU 0x40006485 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MSK +CYREG_B0_UDB06_MSK EQU 0x40006486 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MSK +CYREG_B0_UDB07_MSK EQU 0x40006487 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MSK +CYREG_B0_UDB08_MSK EQU 0x40006488 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MSK +CYREG_B0_UDB09_MSK EQU 0x40006489 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MSK +CYREG_B0_UDB10_MSK EQU 0x4000648a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MSK +CYREG_B0_UDB11_MSK EQU 0x4000648b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MSK +CYREG_B0_UDB12_MSK EQU 0x4000648c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MSK +CYREG_B0_UDB13_MSK EQU 0x4000648d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MSK +CYREG_B0_UDB14_MSK EQU 0x4000648e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MSK +CYREG_B0_UDB15_MSK EQU 0x4000648f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ACTL +CYREG_B0_UDB00_ACTL EQU 0x40006490 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ACTL +CYREG_B0_UDB01_ACTL EQU 0x40006491 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ACTL +CYREG_B0_UDB02_ACTL EQU 0x40006492 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ACTL +CYREG_B0_UDB03_ACTL EQU 0x40006493 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ACTL +CYREG_B0_UDB04_ACTL EQU 0x40006494 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ACTL +CYREG_B0_UDB05_ACTL EQU 0x40006495 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ACTL +CYREG_B0_UDB06_ACTL EQU 0x40006496 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ACTL +CYREG_B0_UDB07_ACTL EQU 0x40006497 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ACTL +CYREG_B0_UDB08_ACTL EQU 0x40006498 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ACTL +CYREG_B0_UDB09_ACTL EQU 0x40006499 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ACTL +CYREG_B0_UDB10_ACTL EQU 0x4000649a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ACTL +CYREG_B0_UDB11_ACTL EQU 0x4000649b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ACTL +CYREG_B0_UDB12_ACTL EQU 0x4000649c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ACTL +CYREG_B0_UDB13_ACTL EQU 0x4000649d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ACTL +CYREG_B0_UDB14_ACTL EQU 0x4000649e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ACTL +CYREG_B0_UDB15_ACTL EQU 0x4000649f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MC +CYREG_B0_UDB00_MC EQU 0x400064a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MC +CYREG_B0_UDB01_MC EQU 0x400064a1 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MC +CYREG_B0_UDB02_MC EQU 0x400064a2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MC +CYREG_B0_UDB03_MC EQU 0x400064a3 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MC +CYREG_B0_UDB04_MC EQU 0x400064a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MC +CYREG_B0_UDB05_MC EQU 0x400064a5 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MC +CYREG_B0_UDB06_MC EQU 0x400064a6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MC +CYREG_B0_UDB07_MC EQU 0x400064a7 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MC +CYREG_B0_UDB08_MC EQU 0x400064a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MC +CYREG_B0_UDB09_MC EQU 0x400064a9 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MC +CYREG_B0_UDB10_MC EQU 0x400064aa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MC +CYREG_B0_UDB11_MC EQU 0x400064ab + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MC +CYREG_B0_UDB12_MC EQU 0x400064ac + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MC +CYREG_B0_UDB13_MC EQU 0x400064ad + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MC +CYREG_B0_UDB14_MC EQU 0x400064ae + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MC +CYREG_B0_UDB15_MC EQU 0x400064af + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE +CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE +CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A0 +CYREG_B1_UDB04_A0 EQU 0x40006504 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A0 +CYREG_B1_UDB05_A0 EQU 0x40006505 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A0 +CYREG_B1_UDB06_A0 EQU 0x40006506 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A0 +CYREG_B1_UDB07_A0 EQU 0x40006507 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A0 +CYREG_B1_UDB08_A0 EQU 0x40006508 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A0 +CYREG_B1_UDB09_A0 EQU 0x40006509 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A0 +CYREG_B1_UDB10_A0 EQU 0x4000650a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A0 +CYREG_B1_UDB11_A0 EQU 0x4000650b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A1 +CYREG_B1_UDB04_A1 EQU 0x40006514 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A1 +CYREG_B1_UDB05_A1 EQU 0x40006515 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A1 +CYREG_B1_UDB06_A1 EQU 0x40006516 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A1 +CYREG_B1_UDB07_A1 EQU 0x40006517 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A1 +CYREG_B1_UDB08_A1 EQU 0x40006518 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A1 +CYREG_B1_UDB09_A1 EQU 0x40006519 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A1 +CYREG_B1_UDB10_A1 EQU 0x4000651a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A1 +CYREG_B1_UDB11_A1 EQU 0x4000651b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D0 +CYREG_B1_UDB04_D0 EQU 0x40006524 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D0 +CYREG_B1_UDB05_D0 EQU 0x40006525 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D0 +CYREG_B1_UDB06_D0 EQU 0x40006526 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D0 +CYREG_B1_UDB07_D0 EQU 0x40006527 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D0 +CYREG_B1_UDB08_D0 EQU 0x40006528 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D0 +CYREG_B1_UDB09_D0 EQU 0x40006529 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D0 +CYREG_B1_UDB10_D0 EQU 0x4000652a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D0 +CYREG_B1_UDB11_D0 EQU 0x4000652b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D1 +CYREG_B1_UDB04_D1 EQU 0x40006534 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D1 +CYREG_B1_UDB05_D1 EQU 0x40006535 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D1 +CYREG_B1_UDB06_D1 EQU 0x40006536 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D1 +CYREG_B1_UDB07_D1 EQU 0x40006537 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D1 +CYREG_B1_UDB08_D1 EQU 0x40006538 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D1 +CYREG_B1_UDB09_D1 EQU 0x40006539 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D1 +CYREG_B1_UDB10_D1 EQU 0x4000653a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D1 +CYREG_B1_UDB11_D1 EQU 0x4000653b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F0 +CYREG_B1_UDB04_F0 EQU 0x40006544 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F0 +CYREG_B1_UDB05_F0 EQU 0x40006545 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F0 +CYREG_B1_UDB06_F0 EQU 0x40006546 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F0 +CYREG_B1_UDB07_F0 EQU 0x40006547 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F0 +CYREG_B1_UDB08_F0 EQU 0x40006548 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F0 +CYREG_B1_UDB09_F0 EQU 0x40006549 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F0 +CYREG_B1_UDB10_F0 EQU 0x4000654a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F0 +CYREG_B1_UDB11_F0 EQU 0x4000654b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F1 +CYREG_B1_UDB04_F1 EQU 0x40006554 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F1 +CYREG_B1_UDB05_F1 EQU 0x40006555 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F1 +CYREG_B1_UDB06_F1 EQU 0x40006556 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F1 +CYREG_B1_UDB07_F1 EQU 0x40006557 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F1 +CYREG_B1_UDB08_F1 EQU 0x40006558 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F1 +CYREG_B1_UDB09_F1 EQU 0x40006559 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F1 +CYREG_B1_UDB10_F1 EQU 0x4000655a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F1 +CYREG_B1_UDB11_F1 EQU 0x4000655b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ST +CYREG_B1_UDB04_ST EQU 0x40006564 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ST +CYREG_B1_UDB05_ST EQU 0x40006565 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ST +CYREG_B1_UDB06_ST EQU 0x40006566 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ST +CYREG_B1_UDB07_ST EQU 0x40006567 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ST +CYREG_B1_UDB08_ST EQU 0x40006568 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ST +CYREG_B1_UDB09_ST EQU 0x40006569 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ST +CYREG_B1_UDB10_ST EQU 0x4000656a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ST +CYREG_B1_UDB11_ST EQU 0x4000656b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_CTL +CYREG_B1_UDB04_CTL EQU 0x40006574 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_CTL +CYREG_B1_UDB05_CTL EQU 0x40006575 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_CTL +CYREG_B1_UDB06_CTL EQU 0x40006576 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_CTL +CYREG_B1_UDB07_CTL EQU 0x40006577 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_CTL +CYREG_B1_UDB08_CTL EQU 0x40006578 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_CTL +CYREG_B1_UDB09_CTL EQU 0x40006579 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_CTL +CYREG_B1_UDB10_CTL EQU 0x4000657a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_CTL +CYREG_B1_UDB11_CTL EQU 0x4000657b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MSK +CYREG_B1_UDB04_MSK EQU 0x40006584 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MSK +CYREG_B1_UDB05_MSK EQU 0x40006585 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MSK +CYREG_B1_UDB06_MSK EQU 0x40006586 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MSK +CYREG_B1_UDB07_MSK EQU 0x40006587 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MSK +CYREG_B1_UDB08_MSK EQU 0x40006588 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MSK +CYREG_B1_UDB09_MSK EQU 0x40006589 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MSK +CYREG_B1_UDB10_MSK EQU 0x4000658a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MSK +CYREG_B1_UDB11_MSK EQU 0x4000658b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ACTL +CYREG_B1_UDB04_ACTL EQU 0x40006594 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ACTL +CYREG_B1_UDB05_ACTL EQU 0x40006595 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ACTL +CYREG_B1_UDB06_ACTL EQU 0x40006596 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ACTL +CYREG_B1_UDB07_ACTL EQU 0x40006597 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ACTL +CYREG_B1_UDB08_ACTL EQU 0x40006598 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ACTL +CYREG_B1_UDB09_ACTL EQU 0x40006599 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ACTL +CYREG_B1_UDB10_ACTL EQU 0x4000659a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ACTL +CYREG_B1_UDB11_ACTL EQU 0x4000659b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MC +CYREG_B1_UDB04_MC EQU 0x400065a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MC +CYREG_B1_UDB05_MC EQU 0x400065a5 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MC +CYREG_B1_UDB06_MC EQU 0x400065a6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MC +CYREG_B1_UDB07_MC EQU 0x400065a7 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MC +CYREG_B1_UDB08_MC EQU 0x400065a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MC +CYREG_B1_UDB09_MC EQU 0x400065a9 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MC +CYREG_B1_UDB10_MC EQU 0x400065aa + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MC +CYREG_B1_UDB11_MC EQU 0x400065ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE +CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE +CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE +CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE +CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE +CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE +CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A0_A1 +CYREG_B0_UDB00_A0_A1 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A0_A1 +CYREG_B0_UDB01_A0_A1 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A0_A1 +CYREG_B0_UDB02_A0_A1 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A0_A1 +CYREG_B0_UDB03_A0_A1 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A0_A1 +CYREG_B0_UDB04_A0_A1 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A0_A1 +CYREG_B0_UDB05_A0_A1 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A0_A1 +CYREG_B0_UDB06_A0_A1 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A0_A1 +CYREG_B0_UDB07_A0_A1 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A0_A1 +CYREG_B0_UDB08_A0_A1 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A0_A1 +CYREG_B0_UDB09_A0_A1 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A0_A1 +CYREG_B0_UDB10_A0_A1 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A0_A1 +CYREG_B0_UDB11_A0_A1 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A0_A1 +CYREG_B0_UDB12_A0_A1 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A0_A1 +CYREG_B0_UDB13_A0_A1 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A0_A1 +CYREG_B0_UDB14_A0_A1 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A0_A1 +CYREG_B0_UDB15_A0_A1 EQU 0x4000681e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D0_D1 +CYREG_B0_UDB00_D0_D1 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D0_D1 +CYREG_B0_UDB01_D0_D1 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D0_D1 +CYREG_B0_UDB02_D0_D1 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D0_D1 +CYREG_B0_UDB03_D0_D1 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D0_D1 +CYREG_B0_UDB04_D0_D1 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D0_D1 +CYREG_B0_UDB05_D0_D1 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D0_D1 +CYREG_B0_UDB06_D0_D1 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D0_D1 +CYREG_B0_UDB07_D0_D1 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D0_D1 +CYREG_B0_UDB08_D0_D1 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D0_D1 +CYREG_B0_UDB09_D0_D1 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D0_D1 +CYREG_B0_UDB10_D0_D1 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D0_D1 +CYREG_B0_UDB11_D0_D1 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D0_D1 +CYREG_B0_UDB12_D0_D1 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D0_D1 +CYREG_B0_UDB13_D0_D1 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D0_D1 +CYREG_B0_UDB14_D0_D1 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D0_D1 +CYREG_B0_UDB15_D0_D1 EQU 0x4000685e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F0_F1 +CYREG_B0_UDB00_F0_F1 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F0_F1 +CYREG_B0_UDB01_F0_F1 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F0_F1 +CYREG_B0_UDB02_F0_F1 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F0_F1 +CYREG_B0_UDB03_F0_F1 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F0_F1 +CYREG_B0_UDB04_F0_F1 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F0_F1 +CYREG_B0_UDB05_F0_F1 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F0_F1 +CYREG_B0_UDB06_F0_F1 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F0_F1 +CYREG_B0_UDB07_F0_F1 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F0_F1 +CYREG_B0_UDB08_F0_F1 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F0_F1 +CYREG_B0_UDB09_F0_F1 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F0_F1 +CYREG_B0_UDB10_F0_F1 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F0_F1 +CYREG_B0_UDB11_F0_F1 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F0_F1 +CYREG_B0_UDB12_F0_F1 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F0_F1 +CYREG_B0_UDB13_F0_F1 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F0_F1 +CYREG_B0_UDB14_F0_F1 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F0_F1 +CYREG_B0_UDB15_F0_F1 EQU 0x4000689e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ST_CTL +CYREG_B0_UDB00_ST_CTL EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ST_CTL +CYREG_B0_UDB01_ST_CTL EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ST_CTL +CYREG_B0_UDB02_ST_CTL EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ST_CTL +CYREG_B0_UDB03_ST_CTL EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ST_CTL +CYREG_B0_UDB04_ST_CTL EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ST_CTL +CYREG_B0_UDB05_ST_CTL EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ST_CTL +CYREG_B0_UDB06_ST_CTL EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ST_CTL +CYREG_B0_UDB07_ST_CTL EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ST_CTL +CYREG_B0_UDB08_ST_CTL EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ST_CTL +CYREG_B0_UDB09_ST_CTL EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ST_CTL +CYREG_B0_UDB10_ST_CTL EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ST_CTL +CYREG_B0_UDB11_ST_CTL EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ST_CTL +CYREG_B0_UDB12_ST_CTL EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ST_CTL +CYREG_B0_UDB13_ST_CTL EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ST_CTL +CYREG_B0_UDB14_ST_CTL EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ST_CTL +CYREG_B0_UDB15_ST_CTL EQU 0x400068de + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MSK_ACTL +CYREG_B0_UDB00_MSK_ACTL EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MSK_ACTL +CYREG_B0_UDB01_MSK_ACTL EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MSK_ACTL +CYREG_B0_UDB02_MSK_ACTL EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MSK_ACTL +CYREG_B0_UDB03_MSK_ACTL EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MSK_ACTL +CYREG_B0_UDB04_MSK_ACTL EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MSK_ACTL +CYREG_B0_UDB05_MSK_ACTL EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MSK_ACTL +CYREG_B0_UDB06_MSK_ACTL EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MSK_ACTL +CYREG_B0_UDB07_MSK_ACTL EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MSK_ACTL +CYREG_B0_UDB08_MSK_ACTL EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MSK_ACTL +CYREG_B0_UDB09_MSK_ACTL EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MSK_ACTL +CYREG_B0_UDB10_MSK_ACTL EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MSK_ACTL +CYREG_B0_UDB11_MSK_ACTL EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MSK_ACTL +CYREG_B0_UDB12_MSK_ACTL EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MSK_ACTL +CYREG_B0_UDB13_MSK_ACTL EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MSK_ACTL +CYREG_B0_UDB14_MSK_ACTL EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MSK_ACTL +CYREG_B0_UDB15_MSK_ACTL EQU 0x4000691e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MC_00 +CYREG_B0_UDB00_MC_00 EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MC_00 +CYREG_B0_UDB01_MC_00 EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MC_00 +CYREG_B0_UDB02_MC_00 EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MC_00 +CYREG_B0_UDB03_MC_00 EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MC_00 +CYREG_B0_UDB04_MC_00 EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MC_00 +CYREG_B0_UDB05_MC_00 EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MC_00 +CYREG_B0_UDB06_MC_00 EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MC_00 +CYREG_B0_UDB07_MC_00 EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MC_00 +CYREG_B0_UDB08_MC_00 EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MC_00 +CYREG_B0_UDB09_MC_00 EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MC_00 +CYREG_B0_UDB10_MC_00 EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MC_00 +CYREG_B0_UDB11_MC_00 EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MC_00 +CYREG_B0_UDB12_MC_00 EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MC_00 +CYREG_B0_UDB13_MC_00 EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MC_00 +CYREG_B0_UDB14_MC_00 EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MC_00 +CYREG_B0_UDB15_MC_00 EQU 0x4000695e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE +CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE +CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A0_A1 +CYREG_B1_UDB04_A0_A1 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A0_A1 +CYREG_B1_UDB05_A0_A1 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A0_A1 +CYREG_B1_UDB06_A0_A1 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A0_A1 +CYREG_B1_UDB07_A0_A1 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A0_A1 +CYREG_B1_UDB08_A0_A1 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A0_A1 +CYREG_B1_UDB09_A0_A1 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A0_A1 +CYREG_B1_UDB10_A0_A1 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A0_A1 +CYREG_B1_UDB11_A0_A1 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D0_D1 +CYREG_B1_UDB04_D0_D1 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D0_D1 +CYREG_B1_UDB05_D0_D1 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D0_D1 +CYREG_B1_UDB06_D0_D1 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D0_D1 +CYREG_B1_UDB07_D0_D1 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D0_D1 +CYREG_B1_UDB08_D0_D1 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D0_D1 +CYREG_B1_UDB09_D0_D1 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D0_D1 +CYREG_B1_UDB10_D0_D1 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D0_D1 +CYREG_B1_UDB11_D0_D1 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F0_F1 +CYREG_B1_UDB04_F0_F1 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F0_F1 +CYREG_B1_UDB05_F0_F1 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F0_F1 +CYREG_B1_UDB06_F0_F1 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F0_F1 +CYREG_B1_UDB07_F0_F1 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F0_F1 +CYREG_B1_UDB08_F0_F1 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F0_F1 +CYREG_B1_UDB09_F0_F1 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F0_F1 +CYREG_B1_UDB10_F0_F1 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F0_F1 +CYREG_B1_UDB11_F0_F1 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ST_CTL +CYREG_B1_UDB04_ST_CTL EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ST_CTL +CYREG_B1_UDB05_ST_CTL EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ST_CTL +CYREG_B1_UDB06_ST_CTL EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ST_CTL +CYREG_B1_UDB07_ST_CTL EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ST_CTL +CYREG_B1_UDB08_ST_CTL EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ST_CTL +CYREG_B1_UDB09_ST_CTL EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ST_CTL +CYREG_B1_UDB10_ST_CTL EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ST_CTL +CYREG_B1_UDB11_ST_CTL EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MSK_ACTL +CYREG_B1_UDB04_MSK_ACTL EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MSK_ACTL +CYREG_B1_UDB05_MSK_ACTL EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MSK_ACTL +CYREG_B1_UDB06_MSK_ACTL EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MSK_ACTL +CYREG_B1_UDB07_MSK_ACTL EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MSK_ACTL +CYREG_B1_UDB08_MSK_ACTL EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MSK_ACTL +CYREG_B1_UDB09_MSK_ACTL EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MSK_ACTL +CYREG_B1_UDB10_MSK_ACTL EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MSK_ACTL +CYREG_B1_UDB11_MSK_ACTL EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MC_00 +CYREG_B1_UDB04_MC_00 EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MC_00 +CYREG_B1_UDB05_MC_00 EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MC_00 +CYREG_B1_UDB06_MC_00 EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MC_00 +CYREG_B1_UDB07_MC_00 EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MC_00 +CYREG_B1_UDB08_MC_00 EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MC_00 +CYREG_B1_UDB09_MC_00 EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MC_00 +CYREG_B1_UDB10_MC_00 EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MC_00 +CYREG_B1_UDB11_MC_00 EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE +CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE +CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE +CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE +CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_A0 +CYREG_B0_UDB00_01_A0 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_A0 +CYREG_B0_UDB01_02_A0 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_A0 +CYREG_B0_UDB02_03_A0 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_A0 +CYREG_B0_UDB03_04_A0 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_A0 +CYREG_B0_UDB04_05_A0 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_A0 +CYREG_B0_UDB05_06_A0 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_A0 +CYREG_B0_UDB06_07_A0 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_A0 +CYREG_B0_UDB07_08_A0 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_A0 +CYREG_B0_UDB08_09_A0 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_A0 +CYREG_B0_UDB09_10_A0 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_A0 +CYREG_B0_UDB10_11_A0 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_A0 +CYREG_B0_UDB11_12_A0 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_A0 +CYREG_B0_UDB12_13_A0 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_A0 +CYREG_B0_UDB13_14_A0 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_A0 +CYREG_B0_UDB14_15_A0 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_A1 +CYREG_B0_UDB00_01_A1 EQU 0x40006820 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_A1 +CYREG_B0_UDB01_02_A1 EQU 0x40006822 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_A1 +CYREG_B0_UDB02_03_A1 EQU 0x40006824 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_A1 +CYREG_B0_UDB03_04_A1 EQU 0x40006826 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_A1 +CYREG_B0_UDB04_05_A1 EQU 0x40006828 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_A1 +CYREG_B0_UDB05_06_A1 EQU 0x4000682a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_A1 +CYREG_B0_UDB06_07_A1 EQU 0x4000682c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_A1 +CYREG_B0_UDB07_08_A1 EQU 0x4000682e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_A1 +CYREG_B0_UDB08_09_A1 EQU 0x40006830 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_A1 +CYREG_B0_UDB09_10_A1 EQU 0x40006832 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_A1 +CYREG_B0_UDB10_11_A1 EQU 0x40006834 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_A1 +CYREG_B0_UDB11_12_A1 EQU 0x40006836 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_A1 +CYREG_B0_UDB12_13_A1 EQU 0x40006838 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_A1 +CYREG_B0_UDB13_14_A1 EQU 0x4000683a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_A1 +CYREG_B0_UDB14_15_A1 EQU 0x4000683c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_D0 +CYREG_B0_UDB00_01_D0 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_D0 +CYREG_B0_UDB01_02_D0 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_D0 +CYREG_B0_UDB02_03_D0 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_D0 +CYREG_B0_UDB03_04_D0 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_D0 +CYREG_B0_UDB04_05_D0 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_D0 +CYREG_B0_UDB05_06_D0 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_D0 +CYREG_B0_UDB06_07_D0 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_D0 +CYREG_B0_UDB07_08_D0 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_D0 +CYREG_B0_UDB08_09_D0 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_D0 +CYREG_B0_UDB09_10_D0 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_D0 +CYREG_B0_UDB10_11_D0 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_D0 +CYREG_B0_UDB11_12_D0 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_D0 +CYREG_B0_UDB12_13_D0 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_D0 +CYREG_B0_UDB13_14_D0 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_D0 +CYREG_B0_UDB14_15_D0 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_D1 +CYREG_B0_UDB00_01_D1 EQU 0x40006860 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_D1 +CYREG_B0_UDB01_02_D1 EQU 0x40006862 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_D1 +CYREG_B0_UDB02_03_D1 EQU 0x40006864 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_D1 +CYREG_B0_UDB03_04_D1 EQU 0x40006866 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_D1 +CYREG_B0_UDB04_05_D1 EQU 0x40006868 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_D1 +CYREG_B0_UDB05_06_D1 EQU 0x4000686a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_D1 +CYREG_B0_UDB06_07_D1 EQU 0x4000686c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_D1 +CYREG_B0_UDB07_08_D1 EQU 0x4000686e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_D1 +CYREG_B0_UDB08_09_D1 EQU 0x40006870 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_D1 +CYREG_B0_UDB09_10_D1 EQU 0x40006872 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_D1 +CYREG_B0_UDB10_11_D1 EQU 0x40006874 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_D1 +CYREG_B0_UDB11_12_D1 EQU 0x40006876 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_D1 +CYREG_B0_UDB12_13_D1 EQU 0x40006878 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_D1 +CYREG_B0_UDB13_14_D1 EQU 0x4000687a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_D1 +CYREG_B0_UDB14_15_D1 EQU 0x4000687c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_F0 +CYREG_B0_UDB00_01_F0 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_F0 +CYREG_B0_UDB01_02_F0 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_F0 +CYREG_B0_UDB02_03_F0 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_F0 +CYREG_B0_UDB03_04_F0 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_F0 +CYREG_B0_UDB04_05_F0 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_F0 +CYREG_B0_UDB05_06_F0 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_F0 +CYREG_B0_UDB06_07_F0 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_F0 +CYREG_B0_UDB07_08_F0 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_F0 +CYREG_B0_UDB08_09_F0 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_F0 +CYREG_B0_UDB09_10_F0 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_F0 +CYREG_B0_UDB10_11_F0 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_F0 +CYREG_B0_UDB11_12_F0 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_F0 +CYREG_B0_UDB12_13_F0 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_F0 +CYREG_B0_UDB13_14_F0 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_F0 +CYREG_B0_UDB14_15_F0 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_F1 +CYREG_B0_UDB00_01_F1 EQU 0x400068a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_F1 +CYREG_B0_UDB01_02_F1 EQU 0x400068a2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_F1 +CYREG_B0_UDB02_03_F1 EQU 0x400068a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_F1 +CYREG_B0_UDB03_04_F1 EQU 0x400068a6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_F1 +CYREG_B0_UDB04_05_F1 EQU 0x400068a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_F1 +CYREG_B0_UDB05_06_F1 EQU 0x400068aa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_F1 +CYREG_B0_UDB06_07_F1 EQU 0x400068ac + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_F1 +CYREG_B0_UDB07_08_F1 EQU 0x400068ae + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_F1 +CYREG_B0_UDB08_09_F1 EQU 0x400068b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_F1 +CYREG_B0_UDB09_10_F1 EQU 0x400068b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_F1 +CYREG_B0_UDB10_11_F1 EQU 0x400068b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_F1 +CYREG_B0_UDB11_12_F1 EQU 0x400068b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_F1 +CYREG_B0_UDB12_13_F1 EQU 0x400068b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_F1 +CYREG_B0_UDB13_14_F1 EQU 0x400068ba + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_F1 +CYREG_B0_UDB14_15_F1 EQU 0x400068bc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_ST +CYREG_B0_UDB00_01_ST EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_ST +CYREG_B0_UDB01_02_ST EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_ST +CYREG_B0_UDB02_03_ST EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_ST +CYREG_B0_UDB03_04_ST EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_ST +CYREG_B0_UDB04_05_ST EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_ST +CYREG_B0_UDB05_06_ST EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_ST +CYREG_B0_UDB06_07_ST EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_ST +CYREG_B0_UDB07_08_ST EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_ST +CYREG_B0_UDB08_09_ST EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_ST +CYREG_B0_UDB09_10_ST EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_ST +CYREG_B0_UDB10_11_ST EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_ST +CYREG_B0_UDB11_12_ST EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_ST +CYREG_B0_UDB12_13_ST EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_ST +CYREG_B0_UDB13_14_ST EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_ST +CYREG_B0_UDB14_15_ST EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_CTL +CYREG_B0_UDB00_01_CTL EQU 0x400068e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_CTL +CYREG_B0_UDB01_02_CTL EQU 0x400068e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_CTL +CYREG_B0_UDB02_03_CTL EQU 0x400068e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_CTL +CYREG_B0_UDB03_04_CTL EQU 0x400068e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_CTL +CYREG_B0_UDB04_05_CTL EQU 0x400068e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_CTL +CYREG_B0_UDB05_06_CTL EQU 0x400068ea + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_CTL +CYREG_B0_UDB06_07_CTL EQU 0x400068ec + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_CTL +CYREG_B0_UDB07_08_CTL EQU 0x400068ee + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_CTL +CYREG_B0_UDB08_09_CTL EQU 0x400068f0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_CTL +CYREG_B0_UDB09_10_CTL EQU 0x400068f2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_CTL +CYREG_B0_UDB10_11_CTL EQU 0x400068f4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_CTL +CYREG_B0_UDB11_12_CTL EQU 0x400068f6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_CTL +CYREG_B0_UDB12_13_CTL EQU 0x400068f8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_CTL +CYREG_B0_UDB13_14_CTL EQU 0x400068fa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_CTL +CYREG_B0_UDB14_15_CTL EQU 0x400068fc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_MSK +CYREG_B0_UDB00_01_MSK EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_MSK +CYREG_B0_UDB01_02_MSK EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_MSK +CYREG_B0_UDB02_03_MSK EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_MSK +CYREG_B0_UDB03_04_MSK EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_MSK +CYREG_B0_UDB04_05_MSK EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_MSK +CYREG_B0_UDB05_06_MSK EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_MSK +CYREG_B0_UDB06_07_MSK EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_MSK +CYREG_B0_UDB07_08_MSK EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_MSK +CYREG_B0_UDB08_09_MSK EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_MSK +CYREG_B0_UDB09_10_MSK EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_MSK +CYREG_B0_UDB10_11_MSK EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_MSK +CYREG_B0_UDB11_12_MSK EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_MSK +CYREG_B0_UDB12_13_MSK EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_MSK +CYREG_B0_UDB13_14_MSK EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_MSK +CYREG_B0_UDB14_15_MSK EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_ACTL +CYREG_B0_UDB00_01_ACTL EQU 0x40006920 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_ACTL +CYREG_B0_UDB01_02_ACTL EQU 0x40006922 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_ACTL +CYREG_B0_UDB02_03_ACTL EQU 0x40006924 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_ACTL +CYREG_B0_UDB03_04_ACTL EQU 0x40006926 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_ACTL +CYREG_B0_UDB04_05_ACTL EQU 0x40006928 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_ACTL +CYREG_B0_UDB05_06_ACTL EQU 0x4000692a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_ACTL +CYREG_B0_UDB06_07_ACTL EQU 0x4000692c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_ACTL +CYREG_B0_UDB07_08_ACTL EQU 0x4000692e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_ACTL +CYREG_B0_UDB08_09_ACTL EQU 0x40006930 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_ACTL +CYREG_B0_UDB09_10_ACTL EQU 0x40006932 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_ACTL +CYREG_B0_UDB10_11_ACTL EQU 0x40006934 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_ACTL +CYREG_B0_UDB11_12_ACTL EQU 0x40006936 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_ACTL +CYREG_B0_UDB12_13_ACTL EQU 0x40006938 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_ACTL +CYREG_B0_UDB13_14_ACTL EQU 0x4000693a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_ACTL +CYREG_B0_UDB14_15_ACTL EQU 0x4000693c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_MC +CYREG_B0_UDB00_01_MC EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_MC +CYREG_B0_UDB01_02_MC EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_MC +CYREG_B0_UDB02_03_MC EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_MC +CYREG_B0_UDB03_04_MC EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_MC +CYREG_B0_UDB04_05_MC EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_MC +CYREG_B0_UDB05_06_MC EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_MC +CYREG_B0_UDB06_07_MC EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_MC +CYREG_B0_UDB07_08_MC EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_MC +CYREG_B0_UDB08_09_MC EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_MC +CYREG_B0_UDB09_10_MC EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_MC +CYREG_B0_UDB10_11_MC EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_MC +CYREG_B0_UDB11_12_MC EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_MC +CYREG_B0_UDB12_13_MC EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_MC +CYREG_B0_UDB13_14_MC EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_MC +CYREG_B0_UDB14_15_MC EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE +CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE +CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_A0 +CYREG_B1_UDB04_05_A0 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_A0 +CYREG_B1_UDB05_06_A0 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_A0 +CYREG_B1_UDB06_07_A0 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_A0 +CYREG_B1_UDB07_08_A0 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_A0 +CYREG_B1_UDB08_09_A0 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_A0 +CYREG_B1_UDB09_10_A0 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_A0 +CYREG_B1_UDB10_11_A0 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_A0 +CYREG_B1_UDB11_12_A0 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_A1 +CYREG_B1_UDB04_05_A1 EQU 0x40006a28 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_A1 +CYREG_B1_UDB05_06_A1 EQU 0x40006a2a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_A1 +CYREG_B1_UDB06_07_A1 EQU 0x40006a2c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_A1 +CYREG_B1_UDB07_08_A1 EQU 0x40006a2e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_A1 +CYREG_B1_UDB08_09_A1 EQU 0x40006a30 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_A1 +CYREG_B1_UDB09_10_A1 EQU 0x40006a32 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_A1 +CYREG_B1_UDB10_11_A1 EQU 0x40006a34 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_A1 +CYREG_B1_UDB11_12_A1 EQU 0x40006a36 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_D0 +CYREG_B1_UDB04_05_D0 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_D0 +CYREG_B1_UDB05_06_D0 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_D0 +CYREG_B1_UDB06_07_D0 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_D0 +CYREG_B1_UDB07_08_D0 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_D0 +CYREG_B1_UDB08_09_D0 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_D0 +CYREG_B1_UDB09_10_D0 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_D0 +CYREG_B1_UDB10_11_D0 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_D0 +CYREG_B1_UDB11_12_D0 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_D1 +CYREG_B1_UDB04_05_D1 EQU 0x40006a68 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_D1 +CYREG_B1_UDB05_06_D1 EQU 0x40006a6a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_D1 +CYREG_B1_UDB06_07_D1 EQU 0x40006a6c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_D1 +CYREG_B1_UDB07_08_D1 EQU 0x40006a6e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_D1 +CYREG_B1_UDB08_09_D1 EQU 0x40006a70 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_D1 +CYREG_B1_UDB09_10_D1 EQU 0x40006a72 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_D1 +CYREG_B1_UDB10_11_D1 EQU 0x40006a74 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_D1 +CYREG_B1_UDB11_12_D1 EQU 0x40006a76 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_F0 +CYREG_B1_UDB04_05_F0 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_F0 +CYREG_B1_UDB05_06_F0 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_F0 +CYREG_B1_UDB06_07_F0 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_F0 +CYREG_B1_UDB07_08_F0 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_F0 +CYREG_B1_UDB08_09_F0 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_F0 +CYREG_B1_UDB09_10_F0 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_F0 +CYREG_B1_UDB10_11_F0 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_F0 +CYREG_B1_UDB11_12_F0 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_F1 +CYREG_B1_UDB04_05_F1 EQU 0x40006aa8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_F1 +CYREG_B1_UDB05_06_F1 EQU 0x40006aaa + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_F1 +CYREG_B1_UDB06_07_F1 EQU 0x40006aac + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_F1 +CYREG_B1_UDB07_08_F1 EQU 0x40006aae + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_F1 +CYREG_B1_UDB08_09_F1 EQU 0x40006ab0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_F1 +CYREG_B1_UDB09_10_F1 EQU 0x40006ab2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_F1 +CYREG_B1_UDB10_11_F1 EQU 0x40006ab4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_F1 +CYREG_B1_UDB11_12_F1 EQU 0x40006ab6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_ST +CYREG_B1_UDB04_05_ST EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_ST +CYREG_B1_UDB05_06_ST EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_ST +CYREG_B1_UDB06_07_ST EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_ST +CYREG_B1_UDB07_08_ST EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_ST +CYREG_B1_UDB08_09_ST EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_ST +CYREG_B1_UDB09_10_ST EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_ST +CYREG_B1_UDB10_11_ST EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_ST +CYREG_B1_UDB11_12_ST EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_CTL +CYREG_B1_UDB04_05_CTL EQU 0x40006ae8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_CTL +CYREG_B1_UDB05_06_CTL EQU 0x40006aea + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_CTL +CYREG_B1_UDB06_07_CTL EQU 0x40006aec + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_CTL +CYREG_B1_UDB07_08_CTL EQU 0x40006aee + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_CTL +CYREG_B1_UDB08_09_CTL EQU 0x40006af0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_CTL +CYREG_B1_UDB09_10_CTL EQU 0x40006af2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_CTL +CYREG_B1_UDB10_11_CTL EQU 0x40006af4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_CTL +CYREG_B1_UDB11_12_CTL EQU 0x40006af6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_MSK +CYREG_B1_UDB04_05_MSK EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_MSK +CYREG_B1_UDB05_06_MSK EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_MSK +CYREG_B1_UDB06_07_MSK EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_MSK +CYREG_B1_UDB07_08_MSK EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_MSK +CYREG_B1_UDB08_09_MSK EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_MSK +CYREG_B1_UDB09_10_MSK EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_MSK +CYREG_B1_UDB10_11_MSK EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_MSK +CYREG_B1_UDB11_12_MSK EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_ACTL +CYREG_B1_UDB04_05_ACTL EQU 0x40006b28 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_ACTL +CYREG_B1_UDB05_06_ACTL EQU 0x40006b2a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_ACTL +CYREG_B1_UDB06_07_ACTL EQU 0x40006b2c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_ACTL +CYREG_B1_UDB07_08_ACTL EQU 0x40006b2e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_ACTL +CYREG_B1_UDB08_09_ACTL EQU 0x40006b30 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_ACTL +CYREG_B1_UDB09_10_ACTL EQU 0x40006b32 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_ACTL +CYREG_B1_UDB10_11_ACTL EQU 0x40006b34 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_ACTL +CYREG_B1_UDB11_12_ACTL EQU 0x40006b36 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_MC +CYREG_B1_UDB04_05_MC EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_MC +CYREG_B1_UDB05_06_MC EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_MC +CYREG_B1_UDB06_07_MC EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_MC +CYREG_B1_UDB07_08_MC EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_MC +CYREG_B1_UDB08_09_MC EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_MC +CYREG_B1_UDB09_10_MC EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_MC +CYREG_B1_UDB10_11_MC EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_MC +CYREG_B1_UDB11_12_MC EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_BASE +CYDEV_PHUB_BASE EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_SIZE +CYDEV_PHUB_SIZE EQU 0x00000c00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFG +CYREG_PHUB_CFG EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_ERR +CYREG_PHUB_ERR EQU 0x40007004 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_ERR_ADR +CYREG_PHUB_ERR_ADR EQU 0x40007008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE +CYDEV_PHUB_CH0_BASE EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE +CYDEV_PHUB_CH0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_CFG +CYREG_PHUB_CH0_BASIC_CFG EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_ACTION +CYREG_PHUB_CH0_ACTION EQU 0x40007014 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_STATUS +CYREG_PHUB_CH0_BASIC_STATUS EQU 0x40007018 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE +CYDEV_PHUB_CH1_BASE EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE +CYDEV_PHUB_CH1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_CFG +CYREG_PHUB_CH1_BASIC_CFG EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_ACTION +CYREG_PHUB_CH1_ACTION EQU 0x40007024 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_STATUS +CYREG_PHUB_CH1_BASIC_STATUS EQU 0x40007028 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE +CYDEV_PHUB_CH2_BASE EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE +CYDEV_PHUB_CH2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_CFG +CYREG_PHUB_CH2_BASIC_CFG EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_ACTION +CYREG_PHUB_CH2_ACTION EQU 0x40007034 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_STATUS +CYREG_PHUB_CH2_BASIC_STATUS EQU 0x40007038 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE +CYDEV_PHUB_CH3_BASE EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE +CYDEV_PHUB_CH3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_CFG +CYREG_PHUB_CH3_BASIC_CFG EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_ACTION +CYREG_PHUB_CH3_ACTION EQU 0x40007044 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_STATUS +CYREG_PHUB_CH3_BASIC_STATUS EQU 0x40007048 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE +CYDEV_PHUB_CH4_BASE EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE +CYDEV_PHUB_CH4_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_CFG +CYREG_PHUB_CH4_BASIC_CFG EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_ACTION +CYREG_PHUB_CH4_ACTION EQU 0x40007054 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_STATUS +CYREG_PHUB_CH4_BASIC_STATUS EQU 0x40007058 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE +CYDEV_PHUB_CH5_BASE EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE +CYDEV_PHUB_CH5_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_CFG +CYREG_PHUB_CH5_BASIC_CFG EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_ACTION +CYREG_PHUB_CH5_ACTION EQU 0x40007064 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_STATUS +CYREG_PHUB_CH5_BASIC_STATUS EQU 0x40007068 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE +CYDEV_PHUB_CH6_BASE EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE +CYDEV_PHUB_CH6_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_CFG +CYREG_PHUB_CH6_BASIC_CFG EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_ACTION +CYREG_PHUB_CH6_ACTION EQU 0x40007074 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_STATUS +CYREG_PHUB_CH6_BASIC_STATUS EQU 0x40007078 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE +CYDEV_PHUB_CH7_BASE EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE +CYDEV_PHUB_CH7_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_CFG +CYREG_PHUB_CH7_BASIC_CFG EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_ACTION +CYREG_PHUB_CH7_ACTION EQU 0x40007084 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_STATUS +CYREG_PHUB_CH7_BASIC_STATUS EQU 0x40007088 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE +CYDEV_PHUB_CH8_BASE EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE +CYDEV_PHUB_CH8_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_CFG +CYREG_PHUB_CH8_BASIC_CFG EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_ACTION +CYREG_PHUB_CH8_ACTION EQU 0x40007094 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_STATUS +CYREG_PHUB_CH8_BASIC_STATUS EQU 0x40007098 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE +CYDEV_PHUB_CH9_BASE EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE +CYDEV_PHUB_CH9_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_CFG +CYREG_PHUB_CH9_BASIC_CFG EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_ACTION +CYREG_PHUB_CH9_ACTION EQU 0x400070a4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_STATUS +CYREG_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE +CYDEV_PHUB_CH10_BASE EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE +CYDEV_PHUB_CH10_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_CFG +CYREG_PHUB_CH10_BASIC_CFG EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_ACTION +CYREG_PHUB_CH10_ACTION EQU 0x400070b4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_STATUS +CYREG_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE +CYDEV_PHUB_CH11_BASE EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE +CYDEV_PHUB_CH11_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_CFG +CYREG_PHUB_CH11_BASIC_CFG EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_ACTION +CYREG_PHUB_CH11_ACTION EQU 0x400070c4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_STATUS +CYREG_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE +CYDEV_PHUB_CH12_BASE EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE +CYDEV_PHUB_CH12_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_CFG +CYREG_PHUB_CH12_BASIC_CFG EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_ACTION +CYREG_PHUB_CH12_ACTION EQU 0x400070d4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_STATUS +CYREG_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE +CYDEV_PHUB_CH13_BASE EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE +CYDEV_PHUB_CH13_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_CFG +CYREG_PHUB_CH13_BASIC_CFG EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_ACTION +CYREG_PHUB_CH13_ACTION EQU 0x400070e4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_STATUS +CYREG_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE +CYDEV_PHUB_CH14_BASE EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE +CYDEV_PHUB_CH14_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_CFG +CYREG_PHUB_CH14_BASIC_CFG EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_ACTION +CYREG_PHUB_CH14_ACTION EQU 0x400070f4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_STATUS +CYREG_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE +CYDEV_PHUB_CH15_BASE EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE +CYDEV_PHUB_CH15_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_CFG +CYREG_PHUB_CH15_BASIC_CFG EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_ACTION +CYREG_PHUB_CH15_ACTION EQU 0x40007104 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_STATUS +CYREG_PHUB_CH15_BASIC_STATUS EQU 0x40007108 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE +CYDEV_PHUB_CH16_BASE EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE +CYDEV_PHUB_CH16_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_CFG +CYREG_PHUB_CH16_BASIC_CFG EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_ACTION +CYREG_PHUB_CH16_ACTION EQU 0x40007114 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_STATUS +CYREG_PHUB_CH16_BASIC_STATUS EQU 0x40007118 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE +CYDEV_PHUB_CH17_BASE EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE +CYDEV_PHUB_CH17_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_CFG +CYREG_PHUB_CH17_BASIC_CFG EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_ACTION +CYREG_PHUB_CH17_ACTION EQU 0x40007124 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_STATUS +CYREG_PHUB_CH17_BASIC_STATUS EQU 0x40007128 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE +CYDEV_PHUB_CH18_BASE EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE +CYDEV_PHUB_CH18_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_CFG +CYREG_PHUB_CH18_BASIC_CFG EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_ACTION +CYREG_PHUB_CH18_ACTION EQU 0x40007134 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_STATUS +CYREG_PHUB_CH18_BASIC_STATUS EQU 0x40007138 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE +CYDEV_PHUB_CH19_BASE EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE +CYDEV_PHUB_CH19_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_CFG +CYREG_PHUB_CH19_BASIC_CFG EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_ACTION +CYREG_PHUB_CH19_ACTION EQU 0x40007144 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_STATUS +CYREG_PHUB_CH19_BASIC_STATUS EQU 0x40007148 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE +CYDEV_PHUB_CH20_BASE EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE +CYDEV_PHUB_CH20_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_CFG +CYREG_PHUB_CH20_BASIC_CFG EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_ACTION +CYREG_PHUB_CH20_ACTION EQU 0x40007154 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_STATUS +CYREG_PHUB_CH20_BASIC_STATUS EQU 0x40007158 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE +CYDEV_PHUB_CH21_BASE EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE +CYDEV_PHUB_CH21_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_CFG +CYREG_PHUB_CH21_BASIC_CFG EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_ACTION +CYREG_PHUB_CH21_ACTION EQU 0x40007164 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_STATUS +CYREG_PHUB_CH21_BASIC_STATUS EQU 0x40007168 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE +CYDEV_PHUB_CH22_BASE EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE +CYDEV_PHUB_CH22_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_CFG +CYREG_PHUB_CH22_BASIC_CFG EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_ACTION +CYREG_PHUB_CH22_ACTION EQU 0x40007174 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_STATUS +CYREG_PHUB_CH22_BASIC_STATUS EQU 0x40007178 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE +CYDEV_PHUB_CH23_BASE EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE +CYDEV_PHUB_CH23_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_CFG +CYREG_PHUB_CH23_BASIC_CFG EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_ACTION +CYREG_PHUB_CH23_ACTION EQU 0x40007184 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_STATUS +CYREG_PHUB_CH23_BASIC_STATUS EQU 0x40007188 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE +CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE +CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG0 +CYREG_PHUB_CFGMEM0_CFG0 EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG1 +CYREG_PHUB_CFGMEM0_CFG1 EQU 0x40007604 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE +CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE +CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG0 +CYREG_PHUB_CFGMEM1_CFG0 EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG1 +CYREG_PHUB_CFGMEM1_CFG1 EQU 0x4000760c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE +CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE +CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG0 +CYREG_PHUB_CFGMEM2_CFG0 EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG1 +CYREG_PHUB_CFGMEM2_CFG1 EQU 0x40007614 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE +CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE +CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG0 +CYREG_PHUB_CFGMEM3_CFG0 EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG1 +CYREG_PHUB_CFGMEM3_CFG1 EQU 0x4000761c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE +CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE +CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG0 +CYREG_PHUB_CFGMEM4_CFG0 EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG1 +CYREG_PHUB_CFGMEM4_CFG1 EQU 0x40007624 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE +CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE +CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG0 +CYREG_PHUB_CFGMEM5_CFG0 EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG1 +CYREG_PHUB_CFGMEM5_CFG1 EQU 0x4000762c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE +CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE +CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG0 +CYREG_PHUB_CFGMEM6_CFG0 EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG1 +CYREG_PHUB_CFGMEM6_CFG1 EQU 0x40007634 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE +CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE +CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG0 +CYREG_PHUB_CFGMEM7_CFG0 EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG1 +CYREG_PHUB_CFGMEM7_CFG1 EQU 0x4000763c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE +CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE +CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG0 +CYREG_PHUB_CFGMEM8_CFG0 EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG1 +CYREG_PHUB_CFGMEM8_CFG1 EQU 0x40007644 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE +CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE +CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG0 +CYREG_PHUB_CFGMEM9_CFG0 EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG1 +CYREG_PHUB_CFGMEM9_CFG1 EQU 0x4000764c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE +CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE +CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG0 +CYREG_PHUB_CFGMEM10_CFG0 EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG1 +CYREG_PHUB_CFGMEM10_CFG1 EQU 0x40007654 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE +CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE +CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG0 +CYREG_PHUB_CFGMEM11_CFG0 EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG1 +CYREG_PHUB_CFGMEM11_CFG1 EQU 0x4000765c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE +CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE +CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG0 +CYREG_PHUB_CFGMEM12_CFG0 EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG1 +CYREG_PHUB_CFGMEM12_CFG1 EQU 0x40007664 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE +CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE +CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG0 +CYREG_PHUB_CFGMEM13_CFG0 EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG1 +CYREG_PHUB_CFGMEM13_CFG1 EQU 0x4000766c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE +CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE +CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG0 +CYREG_PHUB_CFGMEM14_CFG0 EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG1 +CYREG_PHUB_CFGMEM14_CFG1 EQU 0x40007674 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE +CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE +CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG0 +CYREG_PHUB_CFGMEM15_CFG0 EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG1 +CYREG_PHUB_CFGMEM15_CFG1 EQU 0x4000767c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE +CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE +CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG0 +CYREG_PHUB_CFGMEM16_CFG0 EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG1 +CYREG_PHUB_CFGMEM16_CFG1 EQU 0x40007684 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE +CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE +CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG0 +CYREG_PHUB_CFGMEM17_CFG0 EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG1 +CYREG_PHUB_CFGMEM17_CFG1 EQU 0x4000768c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE +CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE +CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG0 +CYREG_PHUB_CFGMEM18_CFG0 EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG1 +CYREG_PHUB_CFGMEM18_CFG1 EQU 0x40007694 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE +CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE +CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG0 +CYREG_PHUB_CFGMEM19_CFG0 EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG1 +CYREG_PHUB_CFGMEM19_CFG1 EQU 0x4000769c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE +CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE +CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG0 +CYREG_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG1 +CYREG_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE +CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE +CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG0 +CYREG_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG1 +CYREG_PHUB_CFGMEM21_CFG1 EQU 0x400076ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE +CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE +CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG0 +CYREG_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG1 +CYREG_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE +CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE +CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG0 +CYREG_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG1 +CYREG_PHUB_CFGMEM23_CFG1 EQU 0x400076bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE +CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE +CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD0 +CYREG_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD1 +CYREG_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE +CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE +CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD0 +CYREG_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD1 +CYREG_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE +CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE +CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD0 +CYREG_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD1 +CYREG_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE +CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE +CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD0 +CYREG_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD1 +CYREG_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE +CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE +CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD0 +CYREG_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD1 +CYREG_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE +CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE +CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD0 +CYREG_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD1 +CYREG_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE +CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE +CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD0 +CYREG_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD1 +CYREG_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE +CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE +CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD0 +CYREG_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD1 +CYREG_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE +CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE +CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD0 +CYREG_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD1 +CYREG_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE +CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE +CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD0 +CYREG_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD1 +CYREG_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE +CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE +CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD0 +CYREG_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD1 +CYREG_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE +CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE +CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD0 +CYREG_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD1 +CYREG_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE +CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE +CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD0 +CYREG_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD1 +CYREG_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE +CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE +CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD0 +CYREG_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD1 +CYREG_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE +CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE +CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD0 +CYREG_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD1 +CYREG_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE +CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE +CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD0 +CYREG_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD1 +CYREG_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE +CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE +CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD0 +CYREG_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD1 +CYREG_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE +CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE +CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD0 +CYREG_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD1 +CYREG_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE +CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE +CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD0 +CYREG_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD1 +CYREG_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE +CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE +CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD0 +CYREG_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD1 +CYREG_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE +CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE +CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD0 +CYREG_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD1 +CYREG_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE +CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE +CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD0 +CYREG_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD1 +CYREG_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE +CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE +CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD0 +CYREG_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD1 +CYREG_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE +CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE +CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD0 +CYREG_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD1 +CYREG_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE +CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE +CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD0 +CYREG_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD1 +CYREG_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE +CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE +CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD0 +CYREG_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD1 +CYREG_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE +CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE +CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD0 +CYREG_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD1 +CYREG_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE +CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE +CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD0 +CYREG_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD1 +CYREG_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE +CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE +CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD0 +CYREG_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD1 +CYREG_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE +CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE +CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD0 +CYREG_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD1 +CYREG_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE +CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE +CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD0 +CYREG_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD1 +CYREG_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE +CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE +CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD0 +CYREG_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD1 +CYREG_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE +CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE +CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD0 +CYREG_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD1 +CYREG_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE +CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE +CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD0 +CYREG_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD1 +CYREG_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE +CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE +CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD0 +CYREG_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD1 +CYREG_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE +CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE +CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD0 +CYREG_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD1 +CYREG_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE +CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE +CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD0 +CYREG_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD1 +CYREG_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE +CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE +CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD0 +CYREG_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD1 +CYREG_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE +CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE +CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD0 +CYREG_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD1 +CYREG_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE +CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE +CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD0 +CYREG_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD1 +CYREG_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE +CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE +CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD0 +CYREG_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD1 +CYREG_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE +CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE +CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD0 +CYREG_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD1 +CYREG_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE +CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE +CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD0 +CYREG_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD1 +CYREG_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE +CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE +CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD0 +CYREG_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD1 +CYREG_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE +CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE +CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD0 +CYREG_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD1 +CYREG_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE +CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE +CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD0 +CYREG_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD1 +CYREG_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE +CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE +CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD0 +CYREG_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD1 +CYREG_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE +CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE +CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD0 +CYREG_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD1 +CYREG_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE +CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE +CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD0 +CYREG_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD1 +CYREG_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE +CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE +CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD0 +CYREG_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD1 +CYREG_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE +CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE +CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD0 +CYREG_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD1 +CYREG_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE +CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE +CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD0 +CYREG_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD1 +CYREG_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE +CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE +CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD0 +CYREG_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD1 +CYREG_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE +CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE +CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD0 +CYREG_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD1 +CYREG_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE +CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE +CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD0 +CYREG_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD1 +CYREG_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE +CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE +CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD0 +CYREG_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD1 +CYREG_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE +CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE +CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD0 +CYREG_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD1 +CYREG_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE +CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE +CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD0 +CYREG_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD1 +CYREG_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE +CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE +CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD0 +CYREG_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD1 +CYREG_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE +CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE +CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD0 +CYREG_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD1 +CYREG_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE +CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE +CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD0 +CYREG_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD1 +CYREG_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE +CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE +CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD0 +CYREG_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD1 +CYREG_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE +CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE +CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD0 +CYREG_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD1 +CYREG_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE +CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE +CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD0 +CYREG_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD1 +CYREG_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE +CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE +CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD0 +CYREG_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD1 +CYREG_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE +CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE +CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD0 +CYREG_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD1 +CYREG_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE +CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE +CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD0 +CYREG_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD1 +CYREG_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE +CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE +CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD0 +CYREG_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD1 +CYREG_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE +CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE +CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD0 +CYREG_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD1 +CYREG_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE +CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE +CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD0 +CYREG_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD1 +CYREG_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE +CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE +CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD0 +CYREG_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD1 +CYREG_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE +CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE +CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD0 +CYREG_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD1 +CYREG_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE +CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE +CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD0 +CYREG_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD1 +CYREG_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE +CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE +CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD0 +CYREG_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD1 +CYREG_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE +CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE +CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD0 +CYREG_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD1 +CYREG_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE +CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE +CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD0 +CYREG_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD1 +CYREG_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE +CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE +CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD0 +CYREG_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD1 +CYREG_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE +CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE +CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD0 +CYREG_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD1 +CYREG_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE +CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE +CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD0 +CYREG_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD1 +CYREG_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE +CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE +CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD0 +CYREG_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD1 +CYREG_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE +CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE +CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD0 +CYREG_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD1 +CYREG_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE +CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE +CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD0 +CYREG_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD1 +CYREG_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE +CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE +CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD0 +CYREG_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD1 +CYREG_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE +CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE +CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD0 +CYREG_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD1 +CYREG_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE +CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE +CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD0 +CYREG_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD1 +CYREG_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE +CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE +CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD0 +CYREG_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD1 +CYREG_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE +CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE +CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD0 +CYREG_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD1 +CYREG_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE +CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE +CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD0 +CYREG_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD1 +CYREG_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE +CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE +CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD0 +CYREG_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD1 +CYREG_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE +CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE +CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD0 +CYREG_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD1 +CYREG_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE +CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE +CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD0 +CYREG_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD1 +CYREG_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE +CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE +CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD0 +CYREG_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD1 +CYREG_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE +CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE +CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD0 +CYREG_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD1 +CYREG_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE +CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE +CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD0 +CYREG_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD1 +CYREG_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE +CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE +CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD0 +CYREG_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD1 +CYREG_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE +CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE +CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD0 +CYREG_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD1 +CYREG_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE +CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE +CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD0 +CYREG_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD1 +CYREG_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE +CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE +CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD0 +CYREG_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD1 +CYREG_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE +CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE +CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD0 +CYREG_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD1 +CYREG_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE +CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE +CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD0 +CYREG_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD1 +CYREG_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE +CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE +CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD0 +CYREG_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD1 +CYREG_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE +CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE +CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD0 +CYREG_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD1 +CYREG_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE +CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE +CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD0 +CYREG_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD1 +CYREG_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE +CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE +CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD0 +CYREG_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD1 +CYREG_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE +CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE +CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD0 +CYREG_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD1 +CYREG_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE +CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE +CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD0 +CYREG_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD1 +CYREG_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE +CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE +CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD0 +CYREG_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD1 +CYREG_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE +CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE +CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD0 +CYREG_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD1 +CYREG_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE +CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE +CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD0 +CYREG_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD1 +CYREG_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE +CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE +CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD0 +CYREG_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD1 +CYREG_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE +CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE +CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD0 +CYREG_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD1 +CYREG_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE +CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE +CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD0 +CYREG_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD1 +CYREG_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE +CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE +CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD0 +CYREG_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD1 +CYREG_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE +CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE +CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD0 +CYREG_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD1 +CYREG_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE +CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE +CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD0 +CYREG_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD1 +CYREG_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE +CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE +CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD0 +CYREG_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD1 +CYREG_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE +CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE +CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD0 +CYREG_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD1 +CYREG_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE +CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE +CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD0 +CYREG_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD1 +CYREG_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE +CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE +CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD0 +CYREG_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD1 +CYREG_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE +CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE +CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD0 +CYREG_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD1 +CYREG_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE +CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE +CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD0 +CYREG_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD1 +CYREG_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE +CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE +CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD0 +CYREG_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD1 +CYREG_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE +CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE +CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD0 +CYREG_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD1 +CYREG_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE +CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE +CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD0 +CYREG_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD1 +CYREG_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE +CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE +CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD0 +CYREG_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD1 +CYREG_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE +CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE +CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD0 +CYREG_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD1 +CYREG_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE +CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE +CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD0 +CYREG_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD1 +CYREG_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE +CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE +CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD0 +CYREG_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD1 +CYREG_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc + ENDIF + IF :LNOT::DEF:CYDEV_EE_BASE +CYDEV_EE_BASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_SIZE +CYDEV_EE_SIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYREG_EE_DATA_MBASE +CYREG_EE_DATA_MBASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYREG_EE_DATA_MSIZE +CYREG_EE_DATA_MSIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_BASE +CYDEV_CAN0_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_SIZE +CYDEV_CAN0_SIZE EQU 0x000002a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE +CYDEV_CAN0_CSR_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE +CYDEV_CAN0_CSR_SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_INT_SR +CYREG_CAN0_CSR_INT_SR EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_INT_EN +CYREG_CAN0_CSR_INT_EN EQU 0x4000a004 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_BUF_SR +CYREG_CAN0_CSR_BUF_SR EQU 0x4000a008 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_ERR_SR +CYREG_CAN0_CSR_ERR_SR EQU 0x4000a00c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_CMD +CYREG_CAN0_CSR_CMD EQU 0x4000a010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_CFG +CYREG_CAN0_CSR_CFG EQU 0x4000a014 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE +CYDEV_CAN0_TX0_BASE EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE +CYDEV_CAN0_TX0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_CMD +CYREG_CAN0_TX0_CMD EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_ID +CYREG_CAN0_TX0_ID EQU 0x4000a024 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_DH +CYREG_CAN0_TX0_DH EQU 0x4000a028 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_DL +CYREG_CAN0_TX0_DL EQU 0x4000a02c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE +CYDEV_CAN0_TX1_BASE EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE +CYDEV_CAN0_TX1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_CMD +CYREG_CAN0_TX1_CMD EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_ID +CYREG_CAN0_TX1_ID EQU 0x4000a034 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_DH +CYREG_CAN0_TX1_DH EQU 0x4000a038 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_DL +CYREG_CAN0_TX1_DL EQU 0x4000a03c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE +CYDEV_CAN0_TX2_BASE EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE +CYDEV_CAN0_TX2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_CMD +CYREG_CAN0_TX2_CMD EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_ID +CYREG_CAN0_TX2_ID EQU 0x4000a044 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_DH +CYREG_CAN0_TX2_DH EQU 0x4000a048 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_DL +CYREG_CAN0_TX2_DL EQU 0x4000a04c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE +CYDEV_CAN0_TX3_BASE EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE +CYDEV_CAN0_TX3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_CMD +CYREG_CAN0_TX3_CMD EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_ID +CYREG_CAN0_TX3_ID EQU 0x4000a054 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_DH +CYREG_CAN0_TX3_DH EQU 0x4000a058 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_DL +CYREG_CAN0_TX3_DL EQU 0x4000a05c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE +CYDEV_CAN0_TX4_BASE EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE +CYDEV_CAN0_TX4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_CMD +CYREG_CAN0_TX4_CMD EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_ID +CYREG_CAN0_TX4_ID EQU 0x4000a064 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_DH +CYREG_CAN0_TX4_DH EQU 0x4000a068 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_DL +CYREG_CAN0_TX4_DL EQU 0x4000a06c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE +CYDEV_CAN0_TX5_BASE EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE +CYDEV_CAN0_TX5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_CMD +CYREG_CAN0_TX5_CMD EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_ID +CYREG_CAN0_TX5_ID EQU 0x4000a074 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_DH +CYREG_CAN0_TX5_DH EQU 0x4000a078 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_DL +CYREG_CAN0_TX5_DL EQU 0x4000a07c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE +CYDEV_CAN0_TX6_BASE EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE +CYDEV_CAN0_TX6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_CMD +CYREG_CAN0_TX6_CMD EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_ID +CYREG_CAN0_TX6_ID EQU 0x4000a084 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_DH +CYREG_CAN0_TX6_DH EQU 0x4000a088 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_DL +CYREG_CAN0_TX6_DL EQU 0x4000a08c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE +CYDEV_CAN0_TX7_BASE EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE +CYDEV_CAN0_TX7_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_CMD +CYREG_CAN0_TX7_CMD EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_ID +CYREG_CAN0_TX7_ID EQU 0x4000a094 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_DH +CYREG_CAN0_TX7_DH EQU 0x4000a098 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_DL +CYREG_CAN0_TX7_DL EQU 0x4000a09c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE +CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE +CYDEV_CAN0_RX0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_CMD +CYREG_CAN0_RX0_CMD EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ID +CYREG_CAN0_RX0_ID EQU 0x4000a0a4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_DH +CYREG_CAN0_RX0_DH EQU 0x4000a0a8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_DL +CYREG_CAN0_RX0_DL EQU 0x4000a0ac + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_AMR +CYREG_CAN0_RX0_AMR EQU 0x4000a0b0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ACR +CYREG_CAN0_RX0_ACR EQU 0x4000a0b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_AMRD +CYREG_CAN0_RX0_AMRD EQU 0x4000a0b8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ACRD +CYREG_CAN0_RX0_ACRD EQU 0x4000a0bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE +CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE +CYDEV_CAN0_RX1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_CMD +CYREG_CAN0_RX1_CMD EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ID +CYREG_CAN0_RX1_ID EQU 0x4000a0c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_DH +CYREG_CAN0_RX1_DH EQU 0x4000a0c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_DL +CYREG_CAN0_RX1_DL EQU 0x4000a0cc + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_AMR +CYREG_CAN0_RX1_AMR EQU 0x4000a0d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ACR +CYREG_CAN0_RX1_ACR EQU 0x4000a0d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_AMRD +CYREG_CAN0_RX1_AMRD EQU 0x4000a0d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ACRD +CYREG_CAN0_RX1_ACRD EQU 0x4000a0dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE +CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE +CYDEV_CAN0_RX2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_CMD +CYREG_CAN0_RX2_CMD EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ID +CYREG_CAN0_RX2_ID EQU 0x4000a0e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_DH +CYREG_CAN0_RX2_DH EQU 0x4000a0e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_DL +CYREG_CAN0_RX2_DL EQU 0x4000a0ec + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_AMR +CYREG_CAN0_RX2_AMR EQU 0x4000a0f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ACR +CYREG_CAN0_RX2_ACR EQU 0x4000a0f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_AMRD +CYREG_CAN0_RX2_AMRD EQU 0x4000a0f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ACRD +CYREG_CAN0_RX2_ACRD EQU 0x4000a0fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE +CYDEV_CAN0_RX3_BASE EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE +CYDEV_CAN0_RX3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_CMD +CYREG_CAN0_RX3_CMD EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ID +CYREG_CAN0_RX3_ID EQU 0x4000a104 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_DH +CYREG_CAN0_RX3_DH EQU 0x4000a108 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_DL +CYREG_CAN0_RX3_DL EQU 0x4000a10c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_AMR +CYREG_CAN0_RX3_AMR EQU 0x4000a110 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ACR +CYREG_CAN0_RX3_ACR EQU 0x4000a114 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_AMRD +CYREG_CAN0_RX3_AMRD EQU 0x4000a118 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ACRD +CYREG_CAN0_RX3_ACRD EQU 0x4000a11c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE +CYDEV_CAN0_RX4_BASE EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE +CYDEV_CAN0_RX4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_CMD +CYREG_CAN0_RX4_CMD EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ID +CYREG_CAN0_RX4_ID EQU 0x4000a124 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_DH +CYREG_CAN0_RX4_DH EQU 0x4000a128 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_DL +CYREG_CAN0_RX4_DL EQU 0x4000a12c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_AMR +CYREG_CAN0_RX4_AMR EQU 0x4000a130 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ACR +CYREG_CAN0_RX4_ACR EQU 0x4000a134 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_AMRD +CYREG_CAN0_RX4_AMRD EQU 0x4000a138 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ACRD +CYREG_CAN0_RX4_ACRD EQU 0x4000a13c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE +CYDEV_CAN0_RX5_BASE EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE +CYDEV_CAN0_RX5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_CMD +CYREG_CAN0_RX5_CMD EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ID +CYREG_CAN0_RX5_ID EQU 0x4000a144 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_DH +CYREG_CAN0_RX5_DH EQU 0x4000a148 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_DL +CYREG_CAN0_RX5_DL EQU 0x4000a14c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_AMR +CYREG_CAN0_RX5_AMR EQU 0x4000a150 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ACR +CYREG_CAN0_RX5_ACR EQU 0x4000a154 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_AMRD +CYREG_CAN0_RX5_AMRD EQU 0x4000a158 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ACRD +CYREG_CAN0_RX5_ACRD EQU 0x4000a15c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE +CYDEV_CAN0_RX6_BASE EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE +CYDEV_CAN0_RX6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_CMD +CYREG_CAN0_RX6_CMD EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ID +CYREG_CAN0_RX6_ID EQU 0x4000a164 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_DH +CYREG_CAN0_RX6_DH EQU 0x4000a168 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_DL +CYREG_CAN0_RX6_DL EQU 0x4000a16c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_AMR +CYREG_CAN0_RX6_AMR EQU 0x4000a170 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ACR +CYREG_CAN0_RX6_ACR EQU 0x4000a174 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_AMRD +CYREG_CAN0_RX6_AMRD EQU 0x4000a178 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ACRD +CYREG_CAN0_RX6_ACRD EQU 0x4000a17c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE +CYDEV_CAN0_RX7_BASE EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE +CYDEV_CAN0_RX7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_CMD +CYREG_CAN0_RX7_CMD EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ID +CYREG_CAN0_RX7_ID EQU 0x4000a184 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_DH +CYREG_CAN0_RX7_DH EQU 0x4000a188 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_DL +CYREG_CAN0_RX7_DL EQU 0x4000a18c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_AMR +CYREG_CAN0_RX7_AMR EQU 0x4000a190 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ACR +CYREG_CAN0_RX7_ACR EQU 0x4000a194 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_AMRD +CYREG_CAN0_RX7_AMRD EQU 0x4000a198 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ACRD +CYREG_CAN0_RX7_ACRD EQU 0x4000a19c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE +CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE +CYDEV_CAN0_RX8_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_CMD +CYREG_CAN0_RX8_CMD EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ID +CYREG_CAN0_RX8_ID EQU 0x4000a1a4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_DH +CYREG_CAN0_RX8_DH EQU 0x4000a1a8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_DL +CYREG_CAN0_RX8_DL EQU 0x4000a1ac + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_AMR +CYREG_CAN0_RX8_AMR EQU 0x4000a1b0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ACR +CYREG_CAN0_RX8_ACR EQU 0x4000a1b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_AMRD +CYREG_CAN0_RX8_AMRD EQU 0x4000a1b8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ACRD +CYREG_CAN0_RX8_ACRD EQU 0x4000a1bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE +CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE +CYDEV_CAN0_RX9_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_CMD +CYREG_CAN0_RX9_CMD EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ID +CYREG_CAN0_RX9_ID EQU 0x4000a1c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_DH +CYREG_CAN0_RX9_DH EQU 0x4000a1c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_DL +CYREG_CAN0_RX9_DL EQU 0x4000a1cc + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_AMR +CYREG_CAN0_RX9_AMR EQU 0x4000a1d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ACR +CYREG_CAN0_RX9_ACR EQU 0x4000a1d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_AMRD +CYREG_CAN0_RX9_AMRD EQU 0x4000a1d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ACRD +CYREG_CAN0_RX9_ACRD EQU 0x4000a1dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE +CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE +CYDEV_CAN0_RX10_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_CMD +CYREG_CAN0_RX10_CMD EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ID +CYREG_CAN0_RX10_ID EQU 0x4000a1e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_DH +CYREG_CAN0_RX10_DH EQU 0x4000a1e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_DL +CYREG_CAN0_RX10_DL EQU 0x4000a1ec + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_AMR +CYREG_CAN0_RX10_AMR EQU 0x4000a1f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ACR +CYREG_CAN0_RX10_ACR EQU 0x4000a1f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_AMRD +CYREG_CAN0_RX10_AMRD EQU 0x4000a1f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ACRD +CYREG_CAN0_RX10_ACRD EQU 0x4000a1fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE +CYDEV_CAN0_RX11_BASE EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE +CYDEV_CAN0_RX11_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_CMD +CYREG_CAN0_RX11_CMD EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ID +CYREG_CAN0_RX11_ID EQU 0x4000a204 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_DH +CYREG_CAN0_RX11_DH EQU 0x4000a208 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_DL +CYREG_CAN0_RX11_DL EQU 0x4000a20c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_AMR +CYREG_CAN0_RX11_AMR EQU 0x4000a210 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ACR +CYREG_CAN0_RX11_ACR EQU 0x4000a214 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_AMRD +CYREG_CAN0_RX11_AMRD EQU 0x4000a218 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ACRD +CYREG_CAN0_RX11_ACRD EQU 0x4000a21c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE +CYDEV_CAN0_RX12_BASE EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE +CYDEV_CAN0_RX12_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_CMD +CYREG_CAN0_RX12_CMD EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ID +CYREG_CAN0_RX12_ID EQU 0x4000a224 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_DH +CYREG_CAN0_RX12_DH EQU 0x4000a228 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_DL +CYREG_CAN0_RX12_DL EQU 0x4000a22c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_AMR +CYREG_CAN0_RX12_AMR EQU 0x4000a230 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ACR +CYREG_CAN0_RX12_ACR EQU 0x4000a234 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_AMRD +CYREG_CAN0_RX12_AMRD EQU 0x4000a238 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ACRD +CYREG_CAN0_RX12_ACRD EQU 0x4000a23c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE +CYDEV_CAN0_RX13_BASE EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE +CYDEV_CAN0_RX13_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_CMD +CYREG_CAN0_RX13_CMD EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ID +CYREG_CAN0_RX13_ID EQU 0x4000a244 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_DH +CYREG_CAN0_RX13_DH EQU 0x4000a248 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_DL +CYREG_CAN0_RX13_DL EQU 0x4000a24c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_AMR +CYREG_CAN0_RX13_AMR EQU 0x4000a250 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ACR +CYREG_CAN0_RX13_ACR EQU 0x4000a254 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_AMRD +CYREG_CAN0_RX13_AMRD EQU 0x4000a258 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ACRD +CYREG_CAN0_RX13_ACRD EQU 0x4000a25c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE +CYDEV_CAN0_RX14_BASE EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE +CYDEV_CAN0_RX14_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_CMD +CYREG_CAN0_RX14_CMD EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ID +CYREG_CAN0_RX14_ID EQU 0x4000a264 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_DH +CYREG_CAN0_RX14_DH EQU 0x4000a268 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_DL +CYREG_CAN0_RX14_DL EQU 0x4000a26c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_AMR +CYREG_CAN0_RX14_AMR EQU 0x4000a270 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ACR +CYREG_CAN0_RX14_ACR EQU 0x4000a274 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_AMRD +CYREG_CAN0_RX14_AMRD EQU 0x4000a278 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ACRD +CYREG_CAN0_RX14_ACRD EQU 0x4000a27c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE +CYDEV_CAN0_RX15_BASE EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE +CYDEV_CAN0_RX15_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_CMD +CYREG_CAN0_RX15_CMD EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ID +CYREG_CAN0_RX15_ID EQU 0x4000a284 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_DH +CYREG_CAN0_RX15_DH EQU 0x4000a288 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_DL +CYREG_CAN0_RX15_DL EQU 0x4000a28c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_AMR +CYREG_CAN0_RX15_AMR EQU 0x4000a290 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ACR +CYREG_CAN0_RX15_ACR EQU 0x4000a294 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_AMRD +CYREG_CAN0_RX15_AMRD EQU 0x4000a298 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ACRD +CYREG_CAN0_RX15_ACRD EQU 0x4000a29c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_BASE +CYDEV_DFB0_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SIZE +CYDEV_DFB0_SIZE EQU 0x000007b5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE +CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE +CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MBASE +CYREG_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MSIZE +CYREG_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE +CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE +CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MBASE +CYREG_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MSIZE +CYREG_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE +CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE +CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MBASE +CYREG_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MSIZE +CYREG_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE +CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE +CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MBASE +CYREG_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MSIZE +CYREG_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE +CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE +CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MBASE +CYREG_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MSIZE +CYREG_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE +CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE +CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MBASE +CYREG_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MSIZE +CYREG_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CR +CYREG_DFB0_CR EQU 0x4000c780 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_SR +CYREG_DFB0_SR EQU 0x4000c784 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_RAM_EN +CYREG_DFB0_RAM_EN EQU 0x4000c788 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_RAM_DIR +CYREG_DFB0_RAM_DIR EQU 0x4000c78c + ENDIF + IF :LNOT::DEF:CYREG_DFB0_SEMA +CYREG_DFB0_SEMA EQU 0x4000c790 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DSI_CTRL +CYREG_DFB0_DSI_CTRL EQU 0x4000c794 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_INT_CTRL +CYREG_DFB0_INT_CTRL EQU 0x4000c798 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DMA_CTRL +CYREG_DFB0_DMA_CTRL EQU 0x4000c79c + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEA +CYREG_DFB0_STAGEA EQU 0x4000c7a0 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEAM +CYREG_DFB0_STAGEAM EQU 0x4000c7a1 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEAH +CYREG_DFB0_STAGEAH EQU 0x4000c7a2 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEB +CYREG_DFB0_STAGEB EQU 0x4000c7a4 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEBM +CYREG_DFB0_STAGEBM EQU 0x4000c7a5 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEBH +CYREG_DFB0_STAGEBH EQU 0x4000c7a6 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDA +CYREG_DFB0_HOLDA EQU 0x4000c7a8 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAM +CYREG_DFB0_HOLDAM EQU 0x4000c7a9 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAH +CYREG_DFB0_HOLDAH EQU 0x4000c7aa + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAS +CYREG_DFB0_HOLDAS EQU 0x4000c7ab + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDB +CYREG_DFB0_HOLDB EQU 0x4000c7ac + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBM +CYREG_DFB0_HOLDBM EQU 0x4000c7ad + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBH +CYREG_DFB0_HOLDBH EQU 0x4000c7ae + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBS +CYREG_DFB0_HOLDBS EQU 0x4000c7af + ENDIF + IF :LNOT::DEF:CYREG_DFB0_COHER +CYREG_DFB0_COHER EQU 0x4000c7b0 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DALIGN +CYREG_DFB0_DALIGN EQU 0x4000c7b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BASE +CYDEV_UCFG_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_SIZE +CYDEV_UCFG_SIZE EQU 0x00005040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_BASE +CYDEV_UCFG_B0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE +CYDEV_UCFG_B0_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE +CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE +CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE +CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE +CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT0 +CYREG_B0_P0_U0_PLD_IT0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT1 +CYREG_B0_P0_U0_PLD_IT1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT2 +CYREG_B0_P0_U0_PLD_IT2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT3 +CYREG_B0_P0_U0_PLD_IT3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT4 +CYREG_B0_P0_U0_PLD_IT4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT5 +CYREG_B0_P0_U0_PLD_IT5 EQU 0x40010014 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT6 +CYREG_B0_P0_U0_PLD_IT6 EQU 0x40010018 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT7 +CYREG_B0_P0_U0_PLD_IT7 EQU 0x4001001c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT8 +CYREG_B0_P0_U0_PLD_IT8 EQU 0x40010020 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT9 +CYREG_B0_P0_U0_PLD_IT9 EQU 0x40010024 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT10 +CYREG_B0_P0_U0_PLD_IT10 EQU 0x40010028 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT11 +CYREG_B0_P0_U0_PLD_IT11 EQU 0x4001002c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT0 +CYREG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT1 +CYREG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT2 +CYREG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT3 +CYREG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_CEN_CONST +CYREG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_XORFB +CYREG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_SET_RESET +CYREG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_BYPASS +CYREG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG0 +CYREG_B0_P0_U0_CFG0 EQU 0x40010040 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG1 +CYREG_B0_P0_U0_CFG1 EQU 0x40010041 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG2 +CYREG_B0_P0_U0_CFG2 EQU 0x40010042 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG3 +CYREG_B0_P0_U0_CFG3 EQU 0x40010043 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG4 +CYREG_B0_P0_U0_CFG4 EQU 0x40010044 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG5 +CYREG_B0_P0_U0_CFG5 EQU 0x40010045 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG6 +CYREG_B0_P0_U0_CFG6 EQU 0x40010046 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG7 +CYREG_B0_P0_U0_CFG7 EQU 0x40010047 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG8 +CYREG_B0_P0_U0_CFG8 EQU 0x40010048 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG9 +CYREG_B0_P0_U0_CFG9 EQU 0x40010049 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG10 +CYREG_B0_P0_U0_CFG10 EQU 0x4001004a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG11 +CYREG_B0_P0_U0_CFG11 EQU 0x4001004b + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG12 +CYREG_B0_P0_U0_CFG12 EQU 0x4001004c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG13 +CYREG_B0_P0_U0_CFG13 EQU 0x4001004d + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG14 +CYREG_B0_P0_U0_CFG14 EQU 0x4001004e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG15 +CYREG_B0_P0_U0_CFG15 EQU 0x4001004f + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG16 +CYREG_B0_P0_U0_CFG16 EQU 0x40010050 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG17 +CYREG_B0_P0_U0_CFG17 EQU 0x40010051 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG18 +CYREG_B0_P0_U0_CFG18 EQU 0x40010052 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG19 +CYREG_B0_P0_U0_CFG19 EQU 0x40010053 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG20 +CYREG_B0_P0_U0_CFG20 EQU 0x40010054 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG21 +CYREG_B0_P0_U0_CFG21 EQU 0x40010055 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG22 +CYREG_B0_P0_U0_CFG22 EQU 0x40010056 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG23 +CYREG_B0_P0_U0_CFG23 EQU 0x40010057 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG24 +CYREG_B0_P0_U0_CFG24 EQU 0x40010058 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG25 +CYREG_B0_P0_U0_CFG25 EQU 0x40010059 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG26 +CYREG_B0_P0_U0_CFG26 EQU 0x4001005a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG27 +CYREG_B0_P0_U0_CFG27 EQU 0x4001005b + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG28 +CYREG_B0_P0_U0_CFG28 EQU 0x4001005c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG29 +CYREG_B0_P0_U0_CFG29 EQU 0x4001005d + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG30 +CYREG_B0_P0_U0_CFG30 EQU 0x4001005e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG31 +CYREG_B0_P0_U0_CFG31 EQU 0x4001005f + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG0 +CYREG_B0_P0_U0_DCFG0 EQU 0x40010060 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG1 +CYREG_B0_P0_U0_DCFG1 EQU 0x40010062 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG2 +CYREG_B0_P0_U0_DCFG2 EQU 0x40010064 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG3 +CYREG_B0_P0_U0_DCFG3 EQU 0x40010066 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG4 +CYREG_B0_P0_U0_DCFG4 EQU 0x40010068 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG5 +CYREG_B0_P0_U0_DCFG5 EQU 0x4001006a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG6 +CYREG_B0_P0_U0_DCFG6 EQU 0x4001006c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG7 +CYREG_B0_P0_U0_DCFG7 EQU 0x4001006e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE +CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE +CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT0 +CYREG_B0_P0_U1_PLD_IT0 EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT1 +CYREG_B0_P0_U1_PLD_IT1 EQU 0x40010084 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT2 +CYREG_B0_P0_U1_PLD_IT2 EQU 0x40010088 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT3 +CYREG_B0_P0_U1_PLD_IT3 EQU 0x4001008c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT4 +CYREG_B0_P0_U1_PLD_IT4 EQU 0x40010090 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT5 +CYREG_B0_P0_U1_PLD_IT5 EQU 0x40010094 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT6 +CYREG_B0_P0_U1_PLD_IT6 EQU 0x40010098 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT7 +CYREG_B0_P0_U1_PLD_IT7 EQU 0x4001009c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT8 +CYREG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT9 +CYREG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT10 +CYREG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT11 +CYREG_B0_P0_U1_PLD_IT11 EQU 0x400100ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT0 +CYREG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT1 +CYREG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT2 +CYREG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT3 +CYREG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_CEN_CONST +CYREG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_XORFB +CYREG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_SET_RESET +CYREG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_BYPASS +CYREG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG0 +CYREG_B0_P0_U1_CFG0 EQU 0x400100c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG1 +CYREG_B0_P0_U1_CFG1 EQU 0x400100c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG2 +CYREG_B0_P0_U1_CFG2 EQU 0x400100c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG3 +CYREG_B0_P0_U1_CFG3 EQU 0x400100c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG4 +CYREG_B0_P0_U1_CFG4 EQU 0x400100c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG5 +CYREG_B0_P0_U1_CFG5 EQU 0x400100c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG6 +CYREG_B0_P0_U1_CFG6 EQU 0x400100c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG7 +CYREG_B0_P0_U1_CFG7 EQU 0x400100c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG8 +CYREG_B0_P0_U1_CFG8 EQU 0x400100c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG9 +CYREG_B0_P0_U1_CFG9 EQU 0x400100c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG10 +CYREG_B0_P0_U1_CFG10 EQU 0x400100ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG11 +CYREG_B0_P0_U1_CFG11 EQU 0x400100cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG12 +CYREG_B0_P0_U1_CFG12 EQU 0x400100cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG13 +CYREG_B0_P0_U1_CFG13 EQU 0x400100cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG14 +CYREG_B0_P0_U1_CFG14 EQU 0x400100ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG15 +CYREG_B0_P0_U1_CFG15 EQU 0x400100cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG16 +CYREG_B0_P0_U1_CFG16 EQU 0x400100d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG17 +CYREG_B0_P0_U1_CFG17 EQU 0x400100d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG18 +CYREG_B0_P0_U1_CFG18 EQU 0x400100d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG19 +CYREG_B0_P0_U1_CFG19 EQU 0x400100d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG20 +CYREG_B0_P0_U1_CFG20 EQU 0x400100d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG21 +CYREG_B0_P0_U1_CFG21 EQU 0x400100d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG22 +CYREG_B0_P0_U1_CFG22 EQU 0x400100d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG23 +CYREG_B0_P0_U1_CFG23 EQU 0x400100d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG24 +CYREG_B0_P0_U1_CFG24 EQU 0x400100d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG25 +CYREG_B0_P0_U1_CFG25 EQU 0x400100d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG26 +CYREG_B0_P0_U1_CFG26 EQU 0x400100da + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG27 +CYREG_B0_P0_U1_CFG27 EQU 0x400100db + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG28 +CYREG_B0_P0_U1_CFG28 EQU 0x400100dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG29 +CYREG_B0_P0_U1_CFG29 EQU 0x400100dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG30 +CYREG_B0_P0_U1_CFG30 EQU 0x400100de + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG31 +CYREG_B0_P0_U1_CFG31 EQU 0x400100df + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG0 +CYREG_B0_P0_U1_DCFG0 EQU 0x400100e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG1 +CYREG_B0_P0_U1_DCFG1 EQU 0x400100e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG2 +CYREG_B0_P0_U1_DCFG2 EQU 0x400100e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG3 +CYREG_B0_P0_U1_DCFG3 EQU 0x400100e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG4 +CYREG_B0_P0_U1_DCFG4 EQU 0x400100e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG5 +CYREG_B0_P0_U1_DCFG5 EQU 0x400100ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG6 +CYREG_B0_P0_U1_DCFG6 EQU 0x400100ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG7 +CYREG_B0_P0_U1_DCFG7 EQU 0x400100ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE +CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE +CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE +CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE +CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE +CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE +CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT0 +CYREG_B0_P1_U0_PLD_IT0 EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT1 +CYREG_B0_P1_U0_PLD_IT1 EQU 0x40010204 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT2 +CYREG_B0_P1_U0_PLD_IT2 EQU 0x40010208 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT3 +CYREG_B0_P1_U0_PLD_IT3 EQU 0x4001020c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT4 +CYREG_B0_P1_U0_PLD_IT4 EQU 0x40010210 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT5 +CYREG_B0_P1_U0_PLD_IT5 EQU 0x40010214 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT6 +CYREG_B0_P1_U0_PLD_IT6 EQU 0x40010218 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT7 +CYREG_B0_P1_U0_PLD_IT7 EQU 0x4001021c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT8 +CYREG_B0_P1_U0_PLD_IT8 EQU 0x40010220 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT9 +CYREG_B0_P1_U0_PLD_IT9 EQU 0x40010224 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT10 +CYREG_B0_P1_U0_PLD_IT10 EQU 0x40010228 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT11 +CYREG_B0_P1_U0_PLD_IT11 EQU 0x4001022c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT0 +CYREG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT1 +CYREG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT2 +CYREG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT3 +CYREG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_CEN_CONST +CYREG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_XORFB +CYREG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_SET_RESET +CYREG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_BYPASS +CYREG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG0 +CYREG_B0_P1_U0_CFG0 EQU 0x40010240 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG1 +CYREG_B0_P1_U0_CFG1 EQU 0x40010241 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG2 +CYREG_B0_P1_U0_CFG2 EQU 0x40010242 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG3 +CYREG_B0_P1_U0_CFG3 EQU 0x40010243 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG4 +CYREG_B0_P1_U0_CFG4 EQU 0x40010244 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG5 +CYREG_B0_P1_U0_CFG5 EQU 0x40010245 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG6 +CYREG_B0_P1_U0_CFG6 EQU 0x40010246 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG7 +CYREG_B0_P1_U0_CFG7 EQU 0x40010247 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG8 +CYREG_B0_P1_U0_CFG8 EQU 0x40010248 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG9 +CYREG_B0_P1_U0_CFG9 EQU 0x40010249 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG10 +CYREG_B0_P1_U0_CFG10 EQU 0x4001024a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG11 +CYREG_B0_P1_U0_CFG11 EQU 0x4001024b + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG12 +CYREG_B0_P1_U0_CFG12 EQU 0x4001024c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG13 +CYREG_B0_P1_U0_CFG13 EQU 0x4001024d + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG14 +CYREG_B0_P1_U0_CFG14 EQU 0x4001024e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG15 +CYREG_B0_P1_U0_CFG15 EQU 0x4001024f + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG16 +CYREG_B0_P1_U0_CFG16 EQU 0x40010250 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG17 +CYREG_B0_P1_U0_CFG17 EQU 0x40010251 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG18 +CYREG_B0_P1_U0_CFG18 EQU 0x40010252 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG19 +CYREG_B0_P1_U0_CFG19 EQU 0x40010253 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG20 +CYREG_B0_P1_U0_CFG20 EQU 0x40010254 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG21 +CYREG_B0_P1_U0_CFG21 EQU 0x40010255 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG22 +CYREG_B0_P1_U0_CFG22 EQU 0x40010256 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG23 +CYREG_B0_P1_U0_CFG23 EQU 0x40010257 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG24 +CYREG_B0_P1_U0_CFG24 EQU 0x40010258 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG25 +CYREG_B0_P1_U0_CFG25 EQU 0x40010259 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG26 +CYREG_B0_P1_U0_CFG26 EQU 0x4001025a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG27 +CYREG_B0_P1_U0_CFG27 EQU 0x4001025b + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG28 +CYREG_B0_P1_U0_CFG28 EQU 0x4001025c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG29 +CYREG_B0_P1_U0_CFG29 EQU 0x4001025d + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG30 +CYREG_B0_P1_U0_CFG30 EQU 0x4001025e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG31 +CYREG_B0_P1_U0_CFG31 EQU 0x4001025f + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG0 +CYREG_B0_P1_U0_DCFG0 EQU 0x40010260 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG1 +CYREG_B0_P1_U0_DCFG1 EQU 0x40010262 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG2 +CYREG_B0_P1_U0_DCFG2 EQU 0x40010264 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG3 +CYREG_B0_P1_U0_DCFG3 EQU 0x40010266 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG4 +CYREG_B0_P1_U0_DCFG4 EQU 0x40010268 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG5 +CYREG_B0_P1_U0_DCFG5 EQU 0x4001026a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG6 +CYREG_B0_P1_U0_DCFG6 EQU 0x4001026c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG7 +CYREG_B0_P1_U0_DCFG7 EQU 0x4001026e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE +CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE +CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT0 +CYREG_B0_P1_U1_PLD_IT0 EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT1 +CYREG_B0_P1_U1_PLD_IT1 EQU 0x40010284 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT2 +CYREG_B0_P1_U1_PLD_IT2 EQU 0x40010288 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT3 +CYREG_B0_P1_U1_PLD_IT3 EQU 0x4001028c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT4 +CYREG_B0_P1_U1_PLD_IT4 EQU 0x40010290 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT5 +CYREG_B0_P1_U1_PLD_IT5 EQU 0x40010294 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT6 +CYREG_B0_P1_U1_PLD_IT6 EQU 0x40010298 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT7 +CYREG_B0_P1_U1_PLD_IT7 EQU 0x4001029c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT8 +CYREG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT9 +CYREG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT10 +CYREG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT11 +CYREG_B0_P1_U1_PLD_IT11 EQU 0x400102ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT0 +CYREG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT1 +CYREG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT2 +CYREG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT3 +CYREG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_CEN_CONST +CYREG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_XORFB +CYREG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_SET_RESET +CYREG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_BYPASS +CYREG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG0 +CYREG_B0_P1_U1_CFG0 EQU 0x400102c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG1 +CYREG_B0_P1_U1_CFG1 EQU 0x400102c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG2 +CYREG_B0_P1_U1_CFG2 EQU 0x400102c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG3 +CYREG_B0_P1_U1_CFG3 EQU 0x400102c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG4 +CYREG_B0_P1_U1_CFG4 EQU 0x400102c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG5 +CYREG_B0_P1_U1_CFG5 EQU 0x400102c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG6 +CYREG_B0_P1_U1_CFG6 EQU 0x400102c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG7 +CYREG_B0_P1_U1_CFG7 EQU 0x400102c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG8 +CYREG_B0_P1_U1_CFG8 EQU 0x400102c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG9 +CYREG_B0_P1_U1_CFG9 EQU 0x400102c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG10 +CYREG_B0_P1_U1_CFG10 EQU 0x400102ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG11 +CYREG_B0_P1_U1_CFG11 EQU 0x400102cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG12 +CYREG_B0_P1_U1_CFG12 EQU 0x400102cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG13 +CYREG_B0_P1_U1_CFG13 EQU 0x400102cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG14 +CYREG_B0_P1_U1_CFG14 EQU 0x400102ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG15 +CYREG_B0_P1_U1_CFG15 EQU 0x400102cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG16 +CYREG_B0_P1_U1_CFG16 EQU 0x400102d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG17 +CYREG_B0_P1_U1_CFG17 EQU 0x400102d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG18 +CYREG_B0_P1_U1_CFG18 EQU 0x400102d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG19 +CYREG_B0_P1_U1_CFG19 EQU 0x400102d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG20 +CYREG_B0_P1_U1_CFG20 EQU 0x400102d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG21 +CYREG_B0_P1_U1_CFG21 EQU 0x400102d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG22 +CYREG_B0_P1_U1_CFG22 EQU 0x400102d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG23 +CYREG_B0_P1_U1_CFG23 EQU 0x400102d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG24 +CYREG_B0_P1_U1_CFG24 EQU 0x400102d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG25 +CYREG_B0_P1_U1_CFG25 EQU 0x400102d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG26 +CYREG_B0_P1_U1_CFG26 EQU 0x400102da + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG27 +CYREG_B0_P1_U1_CFG27 EQU 0x400102db + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG28 +CYREG_B0_P1_U1_CFG28 EQU 0x400102dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG29 +CYREG_B0_P1_U1_CFG29 EQU 0x400102dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG30 +CYREG_B0_P1_U1_CFG30 EQU 0x400102de + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG31 +CYREG_B0_P1_U1_CFG31 EQU 0x400102df + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG0 +CYREG_B0_P1_U1_DCFG0 EQU 0x400102e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG1 +CYREG_B0_P1_U1_DCFG1 EQU 0x400102e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG2 +CYREG_B0_P1_U1_DCFG2 EQU 0x400102e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG3 +CYREG_B0_P1_U1_DCFG3 EQU 0x400102e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG4 +CYREG_B0_P1_U1_DCFG4 EQU 0x400102e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG5 +CYREG_B0_P1_U1_DCFG5 EQU 0x400102ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG6 +CYREG_B0_P1_U1_DCFG6 EQU 0x400102ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG7 +CYREG_B0_P1_U1_DCFG7 EQU 0x400102ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE +CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE +CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE +CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE +CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE +CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE +CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT0 +CYREG_B0_P2_U0_PLD_IT0 EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT1 +CYREG_B0_P2_U0_PLD_IT1 EQU 0x40010404 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT2 +CYREG_B0_P2_U0_PLD_IT2 EQU 0x40010408 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT3 +CYREG_B0_P2_U0_PLD_IT3 EQU 0x4001040c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT4 +CYREG_B0_P2_U0_PLD_IT4 EQU 0x40010410 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT5 +CYREG_B0_P2_U0_PLD_IT5 EQU 0x40010414 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT6 +CYREG_B0_P2_U0_PLD_IT6 EQU 0x40010418 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT7 +CYREG_B0_P2_U0_PLD_IT7 EQU 0x4001041c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT8 +CYREG_B0_P2_U0_PLD_IT8 EQU 0x40010420 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT9 +CYREG_B0_P2_U0_PLD_IT9 EQU 0x40010424 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT10 +CYREG_B0_P2_U0_PLD_IT10 EQU 0x40010428 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT11 +CYREG_B0_P2_U0_PLD_IT11 EQU 0x4001042c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT0 +CYREG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT1 +CYREG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT2 +CYREG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT3 +CYREG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_CEN_CONST +CYREG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_XORFB +CYREG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_SET_RESET +CYREG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_BYPASS +CYREG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG0 +CYREG_B0_P2_U0_CFG0 EQU 0x40010440 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG1 +CYREG_B0_P2_U0_CFG1 EQU 0x40010441 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG2 +CYREG_B0_P2_U0_CFG2 EQU 0x40010442 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG3 +CYREG_B0_P2_U0_CFG3 EQU 0x40010443 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG4 +CYREG_B0_P2_U0_CFG4 EQU 0x40010444 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG5 +CYREG_B0_P2_U0_CFG5 EQU 0x40010445 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG6 +CYREG_B0_P2_U0_CFG6 EQU 0x40010446 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG7 +CYREG_B0_P2_U0_CFG7 EQU 0x40010447 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG8 +CYREG_B0_P2_U0_CFG8 EQU 0x40010448 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG9 +CYREG_B0_P2_U0_CFG9 EQU 0x40010449 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG10 +CYREG_B0_P2_U0_CFG10 EQU 0x4001044a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG11 +CYREG_B0_P2_U0_CFG11 EQU 0x4001044b + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG12 +CYREG_B0_P2_U0_CFG12 EQU 0x4001044c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG13 +CYREG_B0_P2_U0_CFG13 EQU 0x4001044d + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG14 +CYREG_B0_P2_U0_CFG14 EQU 0x4001044e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG15 +CYREG_B0_P2_U0_CFG15 EQU 0x4001044f + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG16 +CYREG_B0_P2_U0_CFG16 EQU 0x40010450 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG17 +CYREG_B0_P2_U0_CFG17 EQU 0x40010451 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG18 +CYREG_B0_P2_U0_CFG18 EQU 0x40010452 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG19 +CYREG_B0_P2_U0_CFG19 EQU 0x40010453 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG20 +CYREG_B0_P2_U0_CFG20 EQU 0x40010454 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG21 +CYREG_B0_P2_U0_CFG21 EQU 0x40010455 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG22 +CYREG_B0_P2_U0_CFG22 EQU 0x40010456 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG23 +CYREG_B0_P2_U0_CFG23 EQU 0x40010457 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG24 +CYREG_B0_P2_U0_CFG24 EQU 0x40010458 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG25 +CYREG_B0_P2_U0_CFG25 EQU 0x40010459 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG26 +CYREG_B0_P2_U0_CFG26 EQU 0x4001045a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG27 +CYREG_B0_P2_U0_CFG27 EQU 0x4001045b + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG28 +CYREG_B0_P2_U0_CFG28 EQU 0x4001045c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG29 +CYREG_B0_P2_U0_CFG29 EQU 0x4001045d + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG30 +CYREG_B0_P2_U0_CFG30 EQU 0x4001045e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG31 +CYREG_B0_P2_U0_CFG31 EQU 0x4001045f + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG0 +CYREG_B0_P2_U0_DCFG0 EQU 0x40010460 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG1 +CYREG_B0_P2_U0_DCFG1 EQU 0x40010462 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG2 +CYREG_B0_P2_U0_DCFG2 EQU 0x40010464 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG3 +CYREG_B0_P2_U0_DCFG3 EQU 0x40010466 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG4 +CYREG_B0_P2_U0_DCFG4 EQU 0x40010468 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG5 +CYREG_B0_P2_U0_DCFG5 EQU 0x4001046a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG6 +CYREG_B0_P2_U0_DCFG6 EQU 0x4001046c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG7 +CYREG_B0_P2_U0_DCFG7 EQU 0x4001046e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE +CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE +CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT0 +CYREG_B0_P2_U1_PLD_IT0 EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT1 +CYREG_B0_P2_U1_PLD_IT1 EQU 0x40010484 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT2 +CYREG_B0_P2_U1_PLD_IT2 EQU 0x40010488 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT3 +CYREG_B0_P2_U1_PLD_IT3 EQU 0x4001048c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT4 +CYREG_B0_P2_U1_PLD_IT4 EQU 0x40010490 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT5 +CYREG_B0_P2_U1_PLD_IT5 EQU 0x40010494 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT6 +CYREG_B0_P2_U1_PLD_IT6 EQU 0x40010498 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT7 +CYREG_B0_P2_U1_PLD_IT7 EQU 0x4001049c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT8 +CYREG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT9 +CYREG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT10 +CYREG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT11 +CYREG_B0_P2_U1_PLD_IT11 EQU 0x400104ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT0 +CYREG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT1 +CYREG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT2 +CYREG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT3 +CYREG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_CEN_CONST +CYREG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_XORFB +CYREG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_SET_RESET +CYREG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_BYPASS +CYREG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG0 +CYREG_B0_P2_U1_CFG0 EQU 0x400104c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG1 +CYREG_B0_P2_U1_CFG1 EQU 0x400104c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG2 +CYREG_B0_P2_U1_CFG2 EQU 0x400104c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG3 +CYREG_B0_P2_U1_CFG3 EQU 0x400104c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG4 +CYREG_B0_P2_U1_CFG4 EQU 0x400104c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG5 +CYREG_B0_P2_U1_CFG5 EQU 0x400104c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG6 +CYREG_B0_P2_U1_CFG6 EQU 0x400104c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG7 +CYREG_B0_P2_U1_CFG7 EQU 0x400104c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG8 +CYREG_B0_P2_U1_CFG8 EQU 0x400104c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG9 +CYREG_B0_P2_U1_CFG9 EQU 0x400104c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG10 +CYREG_B0_P2_U1_CFG10 EQU 0x400104ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG11 +CYREG_B0_P2_U1_CFG11 EQU 0x400104cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG12 +CYREG_B0_P2_U1_CFG12 EQU 0x400104cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG13 +CYREG_B0_P2_U1_CFG13 EQU 0x400104cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG14 +CYREG_B0_P2_U1_CFG14 EQU 0x400104ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG15 +CYREG_B0_P2_U1_CFG15 EQU 0x400104cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG16 +CYREG_B0_P2_U1_CFG16 EQU 0x400104d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG17 +CYREG_B0_P2_U1_CFG17 EQU 0x400104d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG18 +CYREG_B0_P2_U1_CFG18 EQU 0x400104d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG19 +CYREG_B0_P2_U1_CFG19 EQU 0x400104d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG20 +CYREG_B0_P2_U1_CFG20 EQU 0x400104d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG21 +CYREG_B0_P2_U1_CFG21 EQU 0x400104d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG22 +CYREG_B0_P2_U1_CFG22 EQU 0x400104d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG23 +CYREG_B0_P2_U1_CFG23 EQU 0x400104d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG24 +CYREG_B0_P2_U1_CFG24 EQU 0x400104d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG25 +CYREG_B0_P2_U1_CFG25 EQU 0x400104d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG26 +CYREG_B0_P2_U1_CFG26 EQU 0x400104da + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG27 +CYREG_B0_P2_U1_CFG27 EQU 0x400104db + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG28 +CYREG_B0_P2_U1_CFG28 EQU 0x400104dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG29 +CYREG_B0_P2_U1_CFG29 EQU 0x400104dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG30 +CYREG_B0_P2_U1_CFG30 EQU 0x400104de + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG31 +CYREG_B0_P2_U1_CFG31 EQU 0x400104df + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG0 +CYREG_B0_P2_U1_DCFG0 EQU 0x400104e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG1 +CYREG_B0_P2_U1_DCFG1 EQU 0x400104e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG2 +CYREG_B0_P2_U1_DCFG2 EQU 0x400104e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG3 +CYREG_B0_P2_U1_DCFG3 EQU 0x400104e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG4 +CYREG_B0_P2_U1_DCFG4 EQU 0x400104e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG5 +CYREG_B0_P2_U1_DCFG5 EQU 0x400104ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG6 +CYREG_B0_P2_U1_DCFG6 EQU 0x400104ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG7 +CYREG_B0_P2_U1_DCFG7 EQU 0x400104ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE +CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE +CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE +CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE +CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE +CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE +CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT0 +CYREG_B0_P3_U0_PLD_IT0 EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT1 +CYREG_B0_P3_U0_PLD_IT1 EQU 0x40010604 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT2 +CYREG_B0_P3_U0_PLD_IT2 EQU 0x40010608 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT3 +CYREG_B0_P3_U0_PLD_IT3 EQU 0x4001060c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT4 +CYREG_B0_P3_U0_PLD_IT4 EQU 0x40010610 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT5 +CYREG_B0_P3_U0_PLD_IT5 EQU 0x40010614 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT6 +CYREG_B0_P3_U0_PLD_IT6 EQU 0x40010618 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT7 +CYREG_B0_P3_U0_PLD_IT7 EQU 0x4001061c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT8 +CYREG_B0_P3_U0_PLD_IT8 EQU 0x40010620 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT9 +CYREG_B0_P3_U0_PLD_IT9 EQU 0x40010624 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT10 +CYREG_B0_P3_U0_PLD_IT10 EQU 0x40010628 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT11 +CYREG_B0_P3_U0_PLD_IT11 EQU 0x4001062c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT0 +CYREG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT1 +CYREG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT2 +CYREG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT3 +CYREG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_CEN_CONST +CYREG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_XORFB +CYREG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_SET_RESET +CYREG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_BYPASS +CYREG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG0 +CYREG_B0_P3_U0_CFG0 EQU 0x40010640 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG1 +CYREG_B0_P3_U0_CFG1 EQU 0x40010641 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG2 +CYREG_B0_P3_U0_CFG2 EQU 0x40010642 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG3 +CYREG_B0_P3_U0_CFG3 EQU 0x40010643 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG4 +CYREG_B0_P3_U0_CFG4 EQU 0x40010644 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG5 +CYREG_B0_P3_U0_CFG5 EQU 0x40010645 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG6 +CYREG_B0_P3_U0_CFG6 EQU 0x40010646 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG7 +CYREG_B0_P3_U0_CFG7 EQU 0x40010647 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG8 +CYREG_B0_P3_U0_CFG8 EQU 0x40010648 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG9 +CYREG_B0_P3_U0_CFG9 EQU 0x40010649 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG10 +CYREG_B0_P3_U0_CFG10 EQU 0x4001064a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG11 +CYREG_B0_P3_U0_CFG11 EQU 0x4001064b + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG12 +CYREG_B0_P3_U0_CFG12 EQU 0x4001064c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG13 +CYREG_B0_P3_U0_CFG13 EQU 0x4001064d + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG14 +CYREG_B0_P3_U0_CFG14 EQU 0x4001064e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG15 +CYREG_B0_P3_U0_CFG15 EQU 0x4001064f + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG16 +CYREG_B0_P3_U0_CFG16 EQU 0x40010650 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG17 +CYREG_B0_P3_U0_CFG17 EQU 0x40010651 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG18 +CYREG_B0_P3_U0_CFG18 EQU 0x40010652 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG19 +CYREG_B0_P3_U0_CFG19 EQU 0x40010653 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG20 +CYREG_B0_P3_U0_CFG20 EQU 0x40010654 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG21 +CYREG_B0_P3_U0_CFG21 EQU 0x40010655 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG22 +CYREG_B0_P3_U0_CFG22 EQU 0x40010656 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG23 +CYREG_B0_P3_U0_CFG23 EQU 0x40010657 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG24 +CYREG_B0_P3_U0_CFG24 EQU 0x40010658 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG25 +CYREG_B0_P3_U0_CFG25 EQU 0x40010659 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG26 +CYREG_B0_P3_U0_CFG26 EQU 0x4001065a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG27 +CYREG_B0_P3_U0_CFG27 EQU 0x4001065b + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG28 +CYREG_B0_P3_U0_CFG28 EQU 0x4001065c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG29 +CYREG_B0_P3_U0_CFG29 EQU 0x4001065d + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG30 +CYREG_B0_P3_U0_CFG30 EQU 0x4001065e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG31 +CYREG_B0_P3_U0_CFG31 EQU 0x4001065f + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG0 +CYREG_B0_P3_U0_DCFG0 EQU 0x40010660 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG1 +CYREG_B0_P3_U0_DCFG1 EQU 0x40010662 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG2 +CYREG_B0_P3_U0_DCFG2 EQU 0x40010664 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG3 +CYREG_B0_P3_U0_DCFG3 EQU 0x40010666 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG4 +CYREG_B0_P3_U0_DCFG4 EQU 0x40010668 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG5 +CYREG_B0_P3_U0_DCFG5 EQU 0x4001066a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG6 +CYREG_B0_P3_U0_DCFG6 EQU 0x4001066c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG7 +CYREG_B0_P3_U0_DCFG7 EQU 0x4001066e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE +CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE +CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT0 +CYREG_B0_P3_U1_PLD_IT0 EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT1 +CYREG_B0_P3_U1_PLD_IT1 EQU 0x40010684 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT2 +CYREG_B0_P3_U1_PLD_IT2 EQU 0x40010688 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT3 +CYREG_B0_P3_U1_PLD_IT3 EQU 0x4001068c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT4 +CYREG_B0_P3_U1_PLD_IT4 EQU 0x40010690 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT5 +CYREG_B0_P3_U1_PLD_IT5 EQU 0x40010694 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT6 +CYREG_B0_P3_U1_PLD_IT6 EQU 0x40010698 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT7 +CYREG_B0_P3_U1_PLD_IT7 EQU 0x4001069c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT8 +CYREG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT9 +CYREG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT10 +CYREG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT11 +CYREG_B0_P3_U1_PLD_IT11 EQU 0x400106ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT0 +CYREG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT1 +CYREG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT2 +CYREG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT3 +CYREG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_CEN_CONST +CYREG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_XORFB +CYREG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_SET_RESET +CYREG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_BYPASS +CYREG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG0 +CYREG_B0_P3_U1_CFG0 EQU 0x400106c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG1 +CYREG_B0_P3_U1_CFG1 EQU 0x400106c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG2 +CYREG_B0_P3_U1_CFG2 EQU 0x400106c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG3 +CYREG_B0_P3_U1_CFG3 EQU 0x400106c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG4 +CYREG_B0_P3_U1_CFG4 EQU 0x400106c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG5 +CYREG_B0_P3_U1_CFG5 EQU 0x400106c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG6 +CYREG_B0_P3_U1_CFG6 EQU 0x400106c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG7 +CYREG_B0_P3_U1_CFG7 EQU 0x400106c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG8 +CYREG_B0_P3_U1_CFG8 EQU 0x400106c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG9 +CYREG_B0_P3_U1_CFG9 EQU 0x400106c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG10 +CYREG_B0_P3_U1_CFG10 EQU 0x400106ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG11 +CYREG_B0_P3_U1_CFG11 EQU 0x400106cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG12 +CYREG_B0_P3_U1_CFG12 EQU 0x400106cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG13 +CYREG_B0_P3_U1_CFG13 EQU 0x400106cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG14 +CYREG_B0_P3_U1_CFG14 EQU 0x400106ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG15 +CYREG_B0_P3_U1_CFG15 EQU 0x400106cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG16 +CYREG_B0_P3_U1_CFG16 EQU 0x400106d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG17 +CYREG_B0_P3_U1_CFG17 EQU 0x400106d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG18 +CYREG_B0_P3_U1_CFG18 EQU 0x400106d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG19 +CYREG_B0_P3_U1_CFG19 EQU 0x400106d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG20 +CYREG_B0_P3_U1_CFG20 EQU 0x400106d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG21 +CYREG_B0_P3_U1_CFG21 EQU 0x400106d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG22 +CYREG_B0_P3_U1_CFG22 EQU 0x400106d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG23 +CYREG_B0_P3_U1_CFG23 EQU 0x400106d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG24 +CYREG_B0_P3_U1_CFG24 EQU 0x400106d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG25 +CYREG_B0_P3_U1_CFG25 EQU 0x400106d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG26 +CYREG_B0_P3_U1_CFG26 EQU 0x400106da + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG27 +CYREG_B0_P3_U1_CFG27 EQU 0x400106db + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG28 +CYREG_B0_P3_U1_CFG28 EQU 0x400106dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG29 +CYREG_B0_P3_U1_CFG29 EQU 0x400106dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG30 +CYREG_B0_P3_U1_CFG30 EQU 0x400106de + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG31 +CYREG_B0_P3_U1_CFG31 EQU 0x400106df + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG0 +CYREG_B0_P3_U1_DCFG0 EQU 0x400106e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG1 +CYREG_B0_P3_U1_DCFG1 EQU 0x400106e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG2 +CYREG_B0_P3_U1_DCFG2 EQU 0x400106e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG3 +CYREG_B0_P3_U1_DCFG3 EQU 0x400106e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG4 +CYREG_B0_P3_U1_DCFG4 EQU 0x400106e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG5 +CYREG_B0_P3_U1_DCFG5 EQU 0x400106ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG6 +CYREG_B0_P3_U1_DCFG6 EQU 0x400106ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG7 +CYREG_B0_P3_U1_DCFG7 EQU 0x400106ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE +CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE +CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE +CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE +CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE +CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE +CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT0 +CYREG_B0_P4_U0_PLD_IT0 EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT1 +CYREG_B0_P4_U0_PLD_IT1 EQU 0x40010804 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT2 +CYREG_B0_P4_U0_PLD_IT2 EQU 0x40010808 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT3 +CYREG_B0_P4_U0_PLD_IT3 EQU 0x4001080c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT4 +CYREG_B0_P4_U0_PLD_IT4 EQU 0x40010810 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT5 +CYREG_B0_P4_U0_PLD_IT5 EQU 0x40010814 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT6 +CYREG_B0_P4_U0_PLD_IT6 EQU 0x40010818 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT7 +CYREG_B0_P4_U0_PLD_IT7 EQU 0x4001081c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT8 +CYREG_B0_P4_U0_PLD_IT8 EQU 0x40010820 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT9 +CYREG_B0_P4_U0_PLD_IT9 EQU 0x40010824 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT10 +CYREG_B0_P4_U0_PLD_IT10 EQU 0x40010828 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT11 +CYREG_B0_P4_U0_PLD_IT11 EQU 0x4001082c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT0 +CYREG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT1 +CYREG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT2 +CYREG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT3 +CYREG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_CEN_CONST +CYREG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_XORFB +CYREG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_SET_RESET +CYREG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_BYPASS +CYREG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG0 +CYREG_B0_P4_U0_CFG0 EQU 0x40010840 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG1 +CYREG_B0_P4_U0_CFG1 EQU 0x40010841 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG2 +CYREG_B0_P4_U0_CFG2 EQU 0x40010842 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG3 +CYREG_B0_P4_U0_CFG3 EQU 0x40010843 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG4 +CYREG_B0_P4_U0_CFG4 EQU 0x40010844 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG5 +CYREG_B0_P4_U0_CFG5 EQU 0x40010845 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG6 +CYREG_B0_P4_U0_CFG6 EQU 0x40010846 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG7 +CYREG_B0_P4_U0_CFG7 EQU 0x40010847 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG8 +CYREG_B0_P4_U0_CFG8 EQU 0x40010848 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG9 +CYREG_B0_P4_U0_CFG9 EQU 0x40010849 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG10 +CYREG_B0_P4_U0_CFG10 EQU 0x4001084a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG11 +CYREG_B0_P4_U0_CFG11 EQU 0x4001084b + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG12 +CYREG_B0_P4_U0_CFG12 EQU 0x4001084c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG13 +CYREG_B0_P4_U0_CFG13 EQU 0x4001084d + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG14 +CYREG_B0_P4_U0_CFG14 EQU 0x4001084e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG15 +CYREG_B0_P4_U0_CFG15 EQU 0x4001084f + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG16 +CYREG_B0_P4_U0_CFG16 EQU 0x40010850 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG17 +CYREG_B0_P4_U0_CFG17 EQU 0x40010851 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG18 +CYREG_B0_P4_U0_CFG18 EQU 0x40010852 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG19 +CYREG_B0_P4_U0_CFG19 EQU 0x40010853 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG20 +CYREG_B0_P4_U0_CFG20 EQU 0x40010854 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG21 +CYREG_B0_P4_U0_CFG21 EQU 0x40010855 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG22 +CYREG_B0_P4_U0_CFG22 EQU 0x40010856 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG23 +CYREG_B0_P4_U0_CFG23 EQU 0x40010857 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG24 +CYREG_B0_P4_U0_CFG24 EQU 0x40010858 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG25 +CYREG_B0_P4_U0_CFG25 EQU 0x40010859 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG26 +CYREG_B0_P4_U0_CFG26 EQU 0x4001085a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG27 +CYREG_B0_P4_U0_CFG27 EQU 0x4001085b + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG28 +CYREG_B0_P4_U0_CFG28 EQU 0x4001085c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG29 +CYREG_B0_P4_U0_CFG29 EQU 0x4001085d + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG30 +CYREG_B0_P4_U0_CFG30 EQU 0x4001085e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG31 +CYREG_B0_P4_U0_CFG31 EQU 0x4001085f + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG0 +CYREG_B0_P4_U0_DCFG0 EQU 0x40010860 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG1 +CYREG_B0_P4_U0_DCFG1 EQU 0x40010862 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG2 +CYREG_B0_P4_U0_DCFG2 EQU 0x40010864 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG3 +CYREG_B0_P4_U0_DCFG3 EQU 0x40010866 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG4 +CYREG_B0_P4_U0_DCFG4 EQU 0x40010868 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG5 +CYREG_B0_P4_U0_DCFG5 EQU 0x4001086a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG6 +CYREG_B0_P4_U0_DCFG6 EQU 0x4001086c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG7 +CYREG_B0_P4_U0_DCFG7 EQU 0x4001086e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE +CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE +CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT0 +CYREG_B0_P4_U1_PLD_IT0 EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT1 +CYREG_B0_P4_U1_PLD_IT1 EQU 0x40010884 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT2 +CYREG_B0_P4_U1_PLD_IT2 EQU 0x40010888 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT3 +CYREG_B0_P4_U1_PLD_IT3 EQU 0x4001088c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT4 +CYREG_B0_P4_U1_PLD_IT4 EQU 0x40010890 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT5 +CYREG_B0_P4_U1_PLD_IT5 EQU 0x40010894 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT6 +CYREG_B0_P4_U1_PLD_IT6 EQU 0x40010898 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT7 +CYREG_B0_P4_U1_PLD_IT7 EQU 0x4001089c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT8 +CYREG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT9 +CYREG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT10 +CYREG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT11 +CYREG_B0_P4_U1_PLD_IT11 EQU 0x400108ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT0 +CYREG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT1 +CYREG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT2 +CYREG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT3 +CYREG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_CEN_CONST +CYREG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_XORFB +CYREG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_SET_RESET +CYREG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_BYPASS +CYREG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG0 +CYREG_B0_P4_U1_CFG0 EQU 0x400108c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG1 +CYREG_B0_P4_U1_CFG1 EQU 0x400108c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG2 +CYREG_B0_P4_U1_CFG2 EQU 0x400108c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG3 +CYREG_B0_P4_U1_CFG3 EQU 0x400108c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG4 +CYREG_B0_P4_U1_CFG4 EQU 0x400108c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG5 +CYREG_B0_P4_U1_CFG5 EQU 0x400108c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG6 +CYREG_B0_P4_U1_CFG6 EQU 0x400108c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG7 +CYREG_B0_P4_U1_CFG7 EQU 0x400108c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG8 +CYREG_B0_P4_U1_CFG8 EQU 0x400108c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG9 +CYREG_B0_P4_U1_CFG9 EQU 0x400108c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG10 +CYREG_B0_P4_U1_CFG10 EQU 0x400108ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG11 +CYREG_B0_P4_U1_CFG11 EQU 0x400108cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG12 +CYREG_B0_P4_U1_CFG12 EQU 0x400108cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG13 +CYREG_B0_P4_U1_CFG13 EQU 0x400108cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG14 +CYREG_B0_P4_U1_CFG14 EQU 0x400108ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG15 +CYREG_B0_P4_U1_CFG15 EQU 0x400108cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG16 +CYREG_B0_P4_U1_CFG16 EQU 0x400108d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG17 +CYREG_B0_P4_U1_CFG17 EQU 0x400108d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG18 +CYREG_B0_P4_U1_CFG18 EQU 0x400108d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG19 +CYREG_B0_P4_U1_CFG19 EQU 0x400108d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG20 +CYREG_B0_P4_U1_CFG20 EQU 0x400108d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG21 +CYREG_B0_P4_U1_CFG21 EQU 0x400108d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG22 +CYREG_B0_P4_U1_CFG22 EQU 0x400108d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG23 +CYREG_B0_P4_U1_CFG23 EQU 0x400108d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG24 +CYREG_B0_P4_U1_CFG24 EQU 0x400108d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG25 +CYREG_B0_P4_U1_CFG25 EQU 0x400108d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG26 +CYREG_B0_P4_U1_CFG26 EQU 0x400108da + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG27 +CYREG_B0_P4_U1_CFG27 EQU 0x400108db + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG28 +CYREG_B0_P4_U1_CFG28 EQU 0x400108dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG29 +CYREG_B0_P4_U1_CFG29 EQU 0x400108dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG30 +CYREG_B0_P4_U1_CFG30 EQU 0x400108de + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG31 +CYREG_B0_P4_U1_CFG31 EQU 0x400108df + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG0 +CYREG_B0_P4_U1_DCFG0 EQU 0x400108e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG1 +CYREG_B0_P4_U1_DCFG1 EQU 0x400108e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG2 +CYREG_B0_P4_U1_DCFG2 EQU 0x400108e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG3 +CYREG_B0_P4_U1_DCFG3 EQU 0x400108e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG4 +CYREG_B0_P4_U1_DCFG4 EQU 0x400108e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG5 +CYREG_B0_P4_U1_DCFG5 EQU 0x400108ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG6 +CYREG_B0_P4_U1_DCFG6 EQU 0x400108ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG7 +CYREG_B0_P4_U1_DCFG7 EQU 0x400108ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE +CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE +CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE +CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE +CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE +CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE +CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT0 +CYREG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT1 +CYREG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT2 +CYREG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT3 +CYREG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT4 +CYREG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT5 +CYREG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT6 +CYREG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT7 +CYREG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT8 +CYREG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT9 +CYREG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT10 +CYREG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT11 +CYREG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT0 +CYREG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT1 +CYREG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT2 +CYREG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT3 +CYREG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_CEN_CONST +CYREG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_XORFB +CYREG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_SET_RESET +CYREG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_BYPASS +CYREG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG0 +CYREG_B0_P5_U0_CFG0 EQU 0x40010a40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG1 +CYREG_B0_P5_U0_CFG1 EQU 0x40010a41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG2 +CYREG_B0_P5_U0_CFG2 EQU 0x40010a42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG3 +CYREG_B0_P5_U0_CFG3 EQU 0x40010a43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG4 +CYREG_B0_P5_U0_CFG4 EQU 0x40010a44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG5 +CYREG_B0_P5_U0_CFG5 EQU 0x40010a45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG6 +CYREG_B0_P5_U0_CFG6 EQU 0x40010a46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG7 +CYREG_B0_P5_U0_CFG7 EQU 0x40010a47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG8 +CYREG_B0_P5_U0_CFG8 EQU 0x40010a48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG9 +CYREG_B0_P5_U0_CFG9 EQU 0x40010a49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG10 +CYREG_B0_P5_U0_CFG10 EQU 0x40010a4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG11 +CYREG_B0_P5_U0_CFG11 EQU 0x40010a4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG12 +CYREG_B0_P5_U0_CFG12 EQU 0x40010a4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG13 +CYREG_B0_P5_U0_CFG13 EQU 0x40010a4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG14 +CYREG_B0_P5_U0_CFG14 EQU 0x40010a4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG15 +CYREG_B0_P5_U0_CFG15 EQU 0x40010a4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG16 +CYREG_B0_P5_U0_CFG16 EQU 0x40010a50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG17 +CYREG_B0_P5_U0_CFG17 EQU 0x40010a51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG18 +CYREG_B0_P5_U0_CFG18 EQU 0x40010a52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG19 +CYREG_B0_P5_U0_CFG19 EQU 0x40010a53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG20 +CYREG_B0_P5_U0_CFG20 EQU 0x40010a54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG21 +CYREG_B0_P5_U0_CFG21 EQU 0x40010a55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG22 +CYREG_B0_P5_U0_CFG22 EQU 0x40010a56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG23 +CYREG_B0_P5_U0_CFG23 EQU 0x40010a57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG24 +CYREG_B0_P5_U0_CFG24 EQU 0x40010a58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG25 +CYREG_B0_P5_U0_CFG25 EQU 0x40010a59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG26 +CYREG_B0_P5_U0_CFG26 EQU 0x40010a5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG27 +CYREG_B0_P5_U0_CFG27 EQU 0x40010a5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG28 +CYREG_B0_P5_U0_CFG28 EQU 0x40010a5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG29 +CYREG_B0_P5_U0_CFG29 EQU 0x40010a5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG30 +CYREG_B0_P5_U0_CFG30 EQU 0x40010a5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG31 +CYREG_B0_P5_U0_CFG31 EQU 0x40010a5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG0 +CYREG_B0_P5_U0_DCFG0 EQU 0x40010a60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG1 +CYREG_B0_P5_U0_DCFG1 EQU 0x40010a62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG2 +CYREG_B0_P5_U0_DCFG2 EQU 0x40010a64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG3 +CYREG_B0_P5_U0_DCFG3 EQU 0x40010a66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG4 +CYREG_B0_P5_U0_DCFG4 EQU 0x40010a68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG5 +CYREG_B0_P5_U0_DCFG5 EQU 0x40010a6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG6 +CYREG_B0_P5_U0_DCFG6 EQU 0x40010a6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG7 +CYREG_B0_P5_U0_DCFG7 EQU 0x40010a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE +CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE +CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT0 +CYREG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT1 +CYREG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT2 +CYREG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT3 +CYREG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT4 +CYREG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT5 +CYREG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT6 +CYREG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT7 +CYREG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT8 +CYREG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT9 +CYREG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT10 +CYREG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT11 +CYREG_B0_P5_U1_PLD_IT11 EQU 0x40010aac + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT0 +CYREG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT1 +CYREG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT2 +CYREG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT3 +CYREG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_CEN_CONST +CYREG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_XORFB +CYREG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_SET_RESET +CYREG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_BYPASS +CYREG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG0 +CYREG_B0_P5_U1_CFG0 EQU 0x40010ac0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG1 +CYREG_B0_P5_U1_CFG1 EQU 0x40010ac1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG2 +CYREG_B0_P5_U1_CFG2 EQU 0x40010ac2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG3 +CYREG_B0_P5_U1_CFG3 EQU 0x40010ac3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG4 +CYREG_B0_P5_U1_CFG4 EQU 0x40010ac4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG5 +CYREG_B0_P5_U1_CFG5 EQU 0x40010ac5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG6 +CYREG_B0_P5_U1_CFG6 EQU 0x40010ac6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG7 +CYREG_B0_P5_U1_CFG7 EQU 0x40010ac7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG8 +CYREG_B0_P5_U1_CFG8 EQU 0x40010ac8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG9 +CYREG_B0_P5_U1_CFG9 EQU 0x40010ac9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG10 +CYREG_B0_P5_U1_CFG10 EQU 0x40010aca + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG11 +CYREG_B0_P5_U1_CFG11 EQU 0x40010acb + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG12 +CYREG_B0_P5_U1_CFG12 EQU 0x40010acc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG13 +CYREG_B0_P5_U1_CFG13 EQU 0x40010acd + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG14 +CYREG_B0_P5_U1_CFG14 EQU 0x40010ace + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG15 +CYREG_B0_P5_U1_CFG15 EQU 0x40010acf + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG16 +CYREG_B0_P5_U1_CFG16 EQU 0x40010ad0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG17 +CYREG_B0_P5_U1_CFG17 EQU 0x40010ad1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG18 +CYREG_B0_P5_U1_CFG18 EQU 0x40010ad2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG19 +CYREG_B0_P5_U1_CFG19 EQU 0x40010ad3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG20 +CYREG_B0_P5_U1_CFG20 EQU 0x40010ad4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG21 +CYREG_B0_P5_U1_CFG21 EQU 0x40010ad5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG22 +CYREG_B0_P5_U1_CFG22 EQU 0x40010ad6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG23 +CYREG_B0_P5_U1_CFG23 EQU 0x40010ad7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG24 +CYREG_B0_P5_U1_CFG24 EQU 0x40010ad8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG25 +CYREG_B0_P5_U1_CFG25 EQU 0x40010ad9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG26 +CYREG_B0_P5_U1_CFG26 EQU 0x40010ada + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG27 +CYREG_B0_P5_U1_CFG27 EQU 0x40010adb + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG28 +CYREG_B0_P5_U1_CFG28 EQU 0x40010adc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG29 +CYREG_B0_P5_U1_CFG29 EQU 0x40010add + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG30 +CYREG_B0_P5_U1_CFG30 EQU 0x40010ade + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG31 +CYREG_B0_P5_U1_CFG31 EQU 0x40010adf + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG0 +CYREG_B0_P5_U1_DCFG0 EQU 0x40010ae0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG1 +CYREG_B0_P5_U1_DCFG1 EQU 0x40010ae2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG2 +CYREG_B0_P5_U1_DCFG2 EQU 0x40010ae4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG3 +CYREG_B0_P5_U1_DCFG3 EQU 0x40010ae6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG4 +CYREG_B0_P5_U1_DCFG4 EQU 0x40010ae8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG5 +CYREG_B0_P5_U1_DCFG5 EQU 0x40010aea + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG6 +CYREG_B0_P5_U1_DCFG6 EQU 0x40010aec + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG7 +CYREG_B0_P5_U1_DCFG7 EQU 0x40010aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE +CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE +CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE +CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE +CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE +CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE +CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT0 +CYREG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT1 +CYREG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT2 +CYREG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT3 +CYREG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT4 +CYREG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT5 +CYREG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT6 +CYREG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT7 +CYREG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT8 +CYREG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT9 +CYREG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT10 +CYREG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT11 +CYREG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT0 +CYREG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT1 +CYREG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT2 +CYREG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT3 +CYREG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_CEN_CONST +CYREG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_XORFB +CYREG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_SET_RESET +CYREG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_BYPASS +CYREG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG0 +CYREG_B0_P6_U0_CFG0 EQU 0x40010c40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG1 +CYREG_B0_P6_U0_CFG1 EQU 0x40010c41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG2 +CYREG_B0_P6_U0_CFG2 EQU 0x40010c42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG3 +CYREG_B0_P6_U0_CFG3 EQU 0x40010c43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG4 +CYREG_B0_P6_U0_CFG4 EQU 0x40010c44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG5 +CYREG_B0_P6_U0_CFG5 EQU 0x40010c45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG6 +CYREG_B0_P6_U0_CFG6 EQU 0x40010c46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG7 +CYREG_B0_P6_U0_CFG7 EQU 0x40010c47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG8 +CYREG_B0_P6_U0_CFG8 EQU 0x40010c48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG9 +CYREG_B0_P6_U0_CFG9 EQU 0x40010c49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG10 +CYREG_B0_P6_U0_CFG10 EQU 0x40010c4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG11 +CYREG_B0_P6_U0_CFG11 EQU 0x40010c4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG12 +CYREG_B0_P6_U0_CFG12 EQU 0x40010c4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG13 +CYREG_B0_P6_U0_CFG13 EQU 0x40010c4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG14 +CYREG_B0_P6_U0_CFG14 EQU 0x40010c4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG15 +CYREG_B0_P6_U0_CFG15 EQU 0x40010c4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG16 +CYREG_B0_P6_U0_CFG16 EQU 0x40010c50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG17 +CYREG_B0_P6_U0_CFG17 EQU 0x40010c51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG18 +CYREG_B0_P6_U0_CFG18 EQU 0x40010c52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG19 +CYREG_B0_P6_U0_CFG19 EQU 0x40010c53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG20 +CYREG_B0_P6_U0_CFG20 EQU 0x40010c54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG21 +CYREG_B0_P6_U0_CFG21 EQU 0x40010c55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG22 +CYREG_B0_P6_U0_CFG22 EQU 0x40010c56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG23 +CYREG_B0_P6_U0_CFG23 EQU 0x40010c57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG24 +CYREG_B0_P6_U0_CFG24 EQU 0x40010c58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG25 +CYREG_B0_P6_U0_CFG25 EQU 0x40010c59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG26 +CYREG_B0_P6_U0_CFG26 EQU 0x40010c5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG27 +CYREG_B0_P6_U0_CFG27 EQU 0x40010c5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG28 +CYREG_B0_P6_U0_CFG28 EQU 0x40010c5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG29 +CYREG_B0_P6_U0_CFG29 EQU 0x40010c5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG30 +CYREG_B0_P6_U0_CFG30 EQU 0x40010c5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG31 +CYREG_B0_P6_U0_CFG31 EQU 0x40010c5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG0 +CYREG_B0_P6_U0_DCFG0 EQU 0x40010c60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG1 +CYREG_B0_P6_U0_DCFG1 EQU 0x40010c62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG2 +CYREG_B0_P6_U0_DCFG2 EQU 0x40010c64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG3 +CYREG_B0_P6_U0_DCFG3 EQU 0x40010c66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG4 +CYREG_B0_P6_U0_DCFG4 EQU 0x40010c68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG5 +CYREG_B0_P6_U0_DCFG5 EQU 0x40010c6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG6 +CYREG_B0_P6_U0_DCFG6 EQU 0x40010c6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG7 +CYREG_B0_P6_U0_DCFG7 EQU 0x40010c6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE +CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE +CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT0 +CYREG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT1 +CYREG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT2 +CYREG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT3 +CYREG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT4 +CYREG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT5 +CYREG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT6 +CYREG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT7 +CYREG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT8 +CYREG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT9 +CYREG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT10 +CYREG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT11 +CYREG_B0_P6_U1_PLD_IT11 EQU 0x40010cac + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT0 +CYREG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT1 +CYREG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT2 +CYREG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT3 +CYREG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_CEN_CONST +CYREG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_XORFB +CYREG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_SET_RESET +CYREG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_BYPASS +CYREG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG0 +CYREG_B0_P6_U1_CFG0 EQU 0x40010cc0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG1 +CYREG_B0_P6_U1_CFG1 EQU 0x40010cc1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG2 +CYREG_B0_P6_U1_CFG2 EQU 0x40010cc2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG3 +CYREG_B0_P6_U1_CFG3 EQU 0x40010cc3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG4 +CYREG_B0_P6_U1_CFG4 EQU 0x40010cc4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG5 +CYREG_B0_P6_U1_CFG5 EQU 0x40010cc5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG6 +CYREG_B0_P6_U1_CFG6 EQU 0x40010cc6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG7 +CYREG_B0_P6_U1_CFG7 EQU 0x40010cc7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG8 +CYREG_B0_P6_U1_CFG8 EQU 0x40010cc8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG9 +CYREG_B0_P6_U1_CFG9 EQU 0x40010cc9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG10 +CYREG_B0_P6_U1_CFG10 EQU 0x40010cca + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG11 +CYREG_B0_P6_U1_CFG11 EQU 0x40010ccb + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG12 +CYREG_B0_P6_U1_CFG12 EQU 0x40010ccc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG13 +CYREG_B0_P6_U1_CFG13 EQU 0x40010ccd + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG14 +CYREG_B0_P6_U1_CFG14 EQU 0x40010cce + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG15 +CYREG_B0_P6_U1_CFG15 EQU 0x40010ccf + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG16 +CYREG_B0_P6_U1_CFG16 EQU 0x40010cd0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG17 +CYREG_B0_P6_U1_CFG17 EQU 0x40010cd1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG18 +CYREG_B0_P6_U1_CFG18 EQU 0x40010cd2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG19 +CYREG_B0_P6_U1_CFG19 EQU 0x40010cd3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG20 +CYREG_B0_P6_U1_CFG20 EQU 0x40010cd4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG21 +CYREG_B0_P6_U1_CFG21 EQU 0x40010cd5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG22 +CYREG_B0_P6_U1_CFG22 EQU 0x40010cd6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG23 +CYREG_B0_P6_U1_CFG23 EQU 0x40010cd7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG24 +CYREG_B0_P6_U1_CFG24 EQU 0x40010cd8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG25 +CYREG_B0_P6_U1_CFG25 EQU 0x40010cd9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG26 +CYREG_B0_P6_U1_CFG26 EQU 0x40010cda + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG27 +CYREG_B0_P6_U1_CFG27 EQU 0x40010cdb + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG28 +CYREG_B0_P6_U1_CFG28 EQU 0x40010cdc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG29 +CYREG_B0_P6_U1_CFG29 EQU 0x40010cdd + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG30 +CYREG_B0_P6_U1_CFG30 EQU 0x40010cde + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG31 +CYREG_B0_P6_U1_CFG31 EQU 0x40010cdf + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG0 +CYREG_B0_P6_U1_DCFG0 EQU 0x40010ce0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG1 +CYREG_B0_P6_U1_DCFG1 EQU 0x40010ce2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG2 +CYREG_B0_P6_U1_DCFG2 EQU 0x40010ce4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG3 +CYREG_B0_P6_U1_DCFG3 EQU 0x40010ce6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG4 +CYREG_B0_P6_U1_DCFG4 EQU 0x40010ce8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG5 +CYREG_B0_P6_U1_DCFG5 EQU 0x40010cea + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG6 +CYREG_B0_P6_U1_DCFG6 EQU 0x40010cec + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG7 +CYREG_B0_P6_U1_DCFG7 EQU 0x40010cee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE +CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE +CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE +CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE +CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE +CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE +CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT0 +CYREG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT1 +CYREG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT2 +CYREG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT3 +CYREG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT4 +CYREG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT5 +CYREG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT6 +CYREG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT7 +CYREG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT8 +CYREG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT9 +CYREG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT10 +CYREG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT11 +CYREG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT0 +CYREG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT1 +CYREG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT2 +CYREG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT3 +CYREG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_CEN_CONST +CYREG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_XORFB +CYREG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_SET_RESET +CYREG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_BYPASS +CYREG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG0 +CYREG_B0_P7_U0_CFG0 EQU 0x40010e40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG1 +CYREG_B0_P7_U0_CFG1 EQU 0x40010e41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG2 +CYREG_B0_P7_U0_CFG2 EQU 0x40010e42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG3 +CYREG_B0_P7_U0_CFG3 EQU 0x40010e43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG4 +CYREG_B0_P7_U0_CFG4 EQU 0x40010e44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG5 +CYREG_B0_P7_U0_CFG5 EQU 0x40010e45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG6 +CYREG_B0_P7_U0_CFG6 EQU 0x40010e46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG7 +CYREG_B0_P7_U0_CFG7 EQU 0x40010e47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG8 +CYREG_B0_P7_U0_CFG8 EQU 0x40010e48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG9 +CYREG_B0_P7_U0_CFG9 EQU 0x40010e49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG10 +CYREG_B0_P7_U0_CFG10 EQU 0x40010e4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG11 +CYREG_B0_P7_U0_CFG11 EQU 0x40010e4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG12 +CYREG_B0_P7_U0_CFG12 EQU 0x40010e4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG13 +CYREG_B0_P7_U0_CFG13 EQU 0x40010e4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG14 +CYREG_B0_P7_U0_CFG14 EQU 0x40010e4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG15 +CYREG_B0_P7_U0_CFG15 EQU 0x40010e4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG16 +CYREG_B0_P7_U0_CFG16 EQU 0x40010e50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG17 +CYREG_B0_P7_U0_CFG17 EQU 0x40010e51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG18 +CYREG_B0_P7_U0_CFG18 EQU 0x40010e52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG19 +CYREG_B0_P7_U0_CFG19 EQU 0x40010e53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG20 +CYREG_B0_P7_U0_CFG20 EQU 0x40010e54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG21 +CYREG_B0_P7_U0_CFG21 EQU 0x40010e55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG22 +CYREG_B0_P7_U0_CFG22 EQU 0x40010e56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG23 +CYREG_B0_P7_U0_CFG23 EQU 0x40010e57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG24 +CYREG_B0_P7_U0_CFG24 EQU 0x40010e58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG25 +CYREG_B0_P7_U0_CFG25 EQU 0x40010e59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG26 +CYREG_B0_P7_U0_CFG26 EQU 0x40010e5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG27 +CYREG_B0_P7_U0_CFG27 EQU 0x40010e5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG28 +CYREG_B0_P7_U0_CFG28 EQU 0x40010e5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG29 +CYREG_B0_P7_U0_CFG29 EQU 0x40010e5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG30 +CYREG_B0_P7_U0_CFG30 EQU 0x40010e5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG31 +CYREG_B0_P7_U0_CFG31 EQU 0x40010e5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG0 +CYREG_B0_P7_U0_DCFG0 EQU 0x40010e60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG1 +CYREG_B0_P7_U0_DCFG1 EQU 0x40010e62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG2 +CYREG_B0_P7_U0_DCFG2 EQU 0x40010e64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG3 +CYREG_B0_P7_U0_DCFG3 EQU 0x40010e66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG4 +CYREG_B0_P7_U0_DCFG4 EQU 0x40010e68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG5 +CYREG_B0_P7_U0_DCFG5 EQU 0x40010e6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG6 +CYREG_B0_P7_U0_DCFG6 EQU 0x40010e6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG7 +CYREG_B0_P7_U0_DCFG7 EQU 0x40010e6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE +CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE +CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT0 +CYREG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT1 +CYREG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT2 +CYREG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT3 +CYREG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT4 +CYREG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT5 +CYREG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT6 +CYREG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT7 +CYREG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT8 +CYREG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT9 +CYREG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT10 +CYREG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT11 +CYREG_B0_P7_U1_PLD_IT11 EQU 0x40010eac + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT0 +CYREG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT1 +CYREG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT2 +CYREG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT3 +CYREG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_CEN_CONST +CYREG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_XORFB +CYREG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_SET_RESET +CYREG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_BYPASS +CYREG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG0 +CYREG_B0_P7_U1_CFG0 EQU 0x40010ec0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG1 +CYREG_B0_P7_U1_CFG1 EQU 0x40010ec1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG2 +CYREG_B0_P7_U1_CFG2 EQU 0x40010ec2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG3 +CYREG_B0_P7_U1_CFG3 EQU 0x40010ec3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG4 +CYREG_B0_P7_U1_CFG4 EQU 0x40010ec4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG5 +CYREG_B0_P7_U1_CFG5 EQU 0x40010ec5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG6 +CYREG_B0_P7_U1_CFG6 EQU 0x40010ec6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG7 +CYREG_B0_P7_U1_CFG7 EQU 0x40010ec7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG8 +CYREG_B0_P7_U1_CFG8 EQU 0x40010ec8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG9 +CYREG_B0_P7_U1_CFG9 EQU 0x40010ec9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG10 +CYREG_B0_P7_U1_CFG10 EQU 0x40010eca + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG11 +CYREG_B0_P7_U1_CFG11 EQU 0x40010ecb + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG12 +CYREG_B0_P7_U1_CFG12 EQU 0x40010ecc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG13 +CYREG_B0_P7_U1_CFG13 EQU 0x40010ecd + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG14 +CYREG_B0_P7_U1_CFG14 EQU 0x40010ece + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG15 +CYREG_B0_P7_U1_CFG15 EQU 0x40010ecf + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG16 +CYREG_B0_P7_U1_CFG16 EQU 0x40010ed0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG17 +CYREG_B0_P7_U1_CFG17 EQU 0x40010ed1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG18 +CYREG_B0_P7_U1_CFG18 EQU 0x40010ed2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG19 +CYREG_B0_P7_U1_CFG19 EQU 0x40010ed3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG20 +CYREG_B0_P7_U1_CFG20 EQU 0x40010ed4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG21 +CYREG_B0_P7_U1_CFG21 EQU 0x40010ed5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG22 +CYREG_B0_P7_U1_CFG22 EQU 0x40010ed6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG23 +CYREG_B0_P7_U1_CFG23 EQU 0x40010ed7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG24 +CYREG_B0_P7_U1_CFG24 EQU 0x40010ed8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG25 +CYREG_B0_P7_U1_CFG25 EQU 0x40010ed9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG26 +CYREG_B0_P7_U1_CFG26 EQU 0x40010eda + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG27 +CYREG_B0_P7_U1_CFG27 EQU 0x40010edb + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG28 +CYREG_B0_P7_U1_CFG28 EQU 0x40010edc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG29 +CYREG_B0_P7_U1_CFG29 EQU 0x40010edd + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG30 +CYREG_B0_P7_U1_CFG30 EQU 0x40010ede + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG31 +CYREG_B0_P7_U1_CFG31 EQU 0x40010edf + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG0 +CYREG_B0_P7_U1_DCFG0 EQU 0x40010ee0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG1 +CYREG_B0_P7_U1_DCFG1 EQU 0x40010ee2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG2 +CYREG_B0_P7_U1_DCFG2 EQU 0x40010ee4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG3 +CYREG_B0_P7_U1_DCFG3 EQU 0x40010ee6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG4 +CYREG_B0_P7_U1_DCFG4 EQU 0x40010ee8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG5 +CYREG_B0_P7_U1_DCFG5 EQU 0x40010eea + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG6 +CYREG_B0_P7_U1_DCFG6 EQU 0x40010eec + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG7 +CYREG_B0_P7_U1_DCFG7 EQU 0x40010eee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE +CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE +CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_BASE +CYDEV_UCFG_B1_BASE EQU 0x40011000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE +CYDEV_UCFG_B1_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE +CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE +CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE +CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE +CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT0 +CYREG_B1_P2_U0_PLD_IT0 EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT1 +CYREG_B1_P2_U0_PLD_IT1 EQU 0x40011404 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT2 +CYREG_B1_P2_U0_PLD_IT2 EQU 0x40011408 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT3 +CYREG_B1_P2_U0_PLD_IT3 EQU 0x4001140c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT4 +CYREG_B1_P2_U0_PLD_IT4 EQU 0x40011410 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT5 +CYREG_B1_P2_U0_PLD_IT5 EQU 0x40011414 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT6 +CYREG_B1_P2_U0_PLD_IT6 EQU 0x40011418 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT7 +CYREG_B1_P2_U0_PLD_IT7 EQU 0x4001141c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT8 +CYREG_B1_P2_U0_PLD_IT8 EQU 0x40011420 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT9 +CYREG_B1_P2_U0_PLD_IT9 EQU 0x40011424 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT10 +CYREG_B1_P2_U0_PLD_IT10 EQU 0x40011428 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT11 +CYREG_B1_P2_U0_PLD_IT11 EQU 0x4001142c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT0 +CYREG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT1 +CYREG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT2 +CYREG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT3 +CYREG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_CEN_CONST +CYREG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_XORFB +CYREG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_SET_RESET +CYREG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_BYPASS +CYREG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG0 +CYREG_B1_P2_U0_CFG0 EQU 0x40011440 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG1 +CYREG_B1_P2_U0_CFG1 EQU 0x40011441 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG2 +CYREG_B1_P2_U0_CFG2 EQU 0x40011442 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG3 +CYREG_B1_P2_U0_CFG3 EQU 0x40011443 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG4 +CYREG_B1_P2_U0_CFG4 EQU 0x40011444 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG5 +CYREG_B1_P2_U0_CFG5 EQU 0x40011445 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG6 +CYREG_B1_P2_U0_CFG6 EQU 0x40011446 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG7 +CYREG_B1_P2_U0_CFG7 EQU 0x40011447 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG8 +CYREG_B1_P2_U0_CFG8 EQU 0x40011448 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG9 +CYREG_B1_P2_U0_CFG9 EQU 0x40011449 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG10 +CYREG_B1_P2_U0_CFG10 EQU 0x4001144a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG11 +CYREG_B1_P2_U0_CFG11 EQU 0x4001144b + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG12 +CYREG_B1_P2_U0_CFG12 EQU 0x4001144c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG13 +CYREG_B1_P2_U0_CFG13 EQU 0x4001144d + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG14 +CYREG_B1_P2_U0_CFG14 EQU 0x4001144e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG15 +CYREG_B1_P2_U0_CFG15 EQU 0x4001144f + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG16 +CYREG_B1_P2_U0_CFG16 EQU 0x40011450 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG17 +CYREG_B1_P2_U0_CFG17 EQU 0x40011451 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG18 +CYREG_B1_P2_U0_CFG18 EQU 0x40011452 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG19 +CYREG_B1_P2_U0_CFG19 EQU 0x40011453 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG20 +CYREG_B1_P2_U0_CFG20 EQU 0x40011454 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG21 +CYREG_B1_P2_U0_CFG21 EQU 0x40011455 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG22 +CYREG_B1_P2_U0_CFG22 EQU 0x40011456 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG23 +CYREG_B1_P2_U0_CFG23 EQU 0x40011457 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG24 +CYREG_B1_P2_U0_CFG24 EQU 0x40011458 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG25 +CYREG_B1_P2_U0_CFG25 EQU 0x40011459 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG26 +CYREG_B1_P2_U0_CFG26 EQU 0x4001145a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG27 +CYREG_B1_P2_U0_CFG27 EQU 0x4001145b + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG28 +CYREG_B1_P2_U0_CFG28 EQU 0x4001145c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG29 +CYREG_B1_P2_U0_CFG29 EQU 0x4001145d + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG30 +CYREG_B1_P2_U0_CFG30 EQU 0x4001145e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG31 +CYREG_B1_P2_U0_CFG31 EQU 0x4001145f + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG0 +CYREG_B1_P2_U0_DCFG0 EQU 0x40011460 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG1 +CYREG_B1_P2_U0_DCFG1 EQU 0x40011462 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG2 +CYREG_B1_P2_U0_DCFG2 EQU 0x40011464 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG3 +CYREG_B1_P2_U0_DCFG3 EQU 0x40011466 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG4 +CYREG_B1_P2_U0_DCFG4 EQU 0x40011468 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG5 +CYREG_B1_P2_U0_DCFG5 EQU 0x4001146a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG6 +CYREG_B1_P2_U0_DCFG6 EQU 0x4001146c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG7 +CYREG_B1_P2_U0_DCFG7 EQU 0x4001146e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE +CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE +CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT0 +CYREG_B1_P2_U1_PLD_IT0 EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT1 +CYREG_B1_P2_U1_PLD_IT1 EQU 0x40011484 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT2 +CYREG_B1_P2_U1_PLD_IT2 EQU 0x40011488 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT3 +CYREG_B1_P2_U1_PLD_IT3 EQU 0x4001148c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT4 +CYREG_B1_P2_U1_PLD_IT4 EQU 0x40011490 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT5 +CYREG_B1_P2_U1_PLD_IT5 EQU 0x40011494 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT6 +CYREG_B1_P2_U1_PLD_IT6 EQU 0x40011498 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT7 +CYREG_B1_P2_U1_PLD_IT7 EQU 0x4001149c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT8 +CYREG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT9 +CYREG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT10 +CYREG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT11 +CYREG_B1_P2_U1_PLD_IT11 EQU 0x400114ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT0 +CYREG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT1 +CYREG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT2 +CYREG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT3 +CYREG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_CEN_CONST +CYREG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_XORFB +CYREG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_SET_RESET +CYREG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_BYPASS +CYREG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG0 +CYREG_B1_P2_U1_CFG0 EQU 0x400114c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG1 +CYREG_B1_P2_U1_CFG1 EQU 0x400114c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG2 +CYREG_B1_P2_U1_CFG2 EQU 0x400114c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG3 +CYREG_B1_P2_U1_CFG3 EQU 0x400114c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG4 +CYREG_B1_P2_U1_CFG4 EQU 0x400114c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG5 +CYREG_B1_P2_U1_CFG5 EQU 0x400114c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG6 +CYREG_B1_P2_U1_CFG6 EQU 0x400114c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG7 +CYREG_B1_P2_U1_CFG7 EQU 0x400114c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG8 +CYREG_B1_P2_U1_CFG8 EQU 0x400114c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG9 +CYREG_B1_P2_U1_CFG9 EQU 0x400114c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG10 +CYREG_B1_P2_U1_CFG10 EQU 0x400114ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG11 +CYREG_B1_P2_U1_CFG11 EQU 0x400114cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG12 +CYREG_B1_P2_U1_CFG12 EQU 0x400114cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG13 +CYREG_B1_P2_U1_CFG13 EQU 0x400114cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG14 +CYREG_B1_P2_U1_CFG14 EQU 0x400114ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG15 +CYREG_B1_P2_U1_CFG15 EQU 0x400114cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG16 +CYREG_B1_P2_U1_CFG16 EQU 0x400114d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG17 +CYREG_B1_P2_U1_CFG17 EQU 0x400114d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG18 +CYREG_B1_P2_U1_CFG18 EQU 0x400114d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG19 +CYREG_B1_P2_U1_CFG19 EQU 0x400114d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG20 +CYREG_B1_P2_U1_CFG20 EQU 0x400114d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG21 +CYREG_B1_P2_U1_CFG21 EQU 0x400114d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG22 +CYREG_B1_P2_U1_CFG22 EQU 0x400114d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG23 +CYREG_B1_P2_U1_CFG23 EQU 0x400114d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG24 +CYREG_B1_P2_U1_CFG24 EQU 0x400114d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG25 +CYREG_B1_P2_U1_CFG25 EQU 0x400114d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG26 +CYREG_B1_P2_U1_CFG26 EQU 0x400114da + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG27 +CYREG_B1_P2_U1_CFG27 EQU 0x400114db + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG28 +CYREG_B1_P2_U1_CFG28 EQU 0x400114dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG29 +CYREG_B1_P2_U1_CFG29 EQU 0x400114dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG30 +CYREG_B1_P2_U1_CFG30 EQU 0x400114de + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG31 +CYREG_B1_P2_U1_CFG31 EQU 0x400114df + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG0 +CYREG_B1_P2_U1_DCFG0 EQU 0x400114e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG1 +CYREG_B1_P2_U1_DCFG1 EQU 0x400114e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG2 +CYREG_B1_P2_U1_DCFG2 EQU 0x400114e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG3 +CYREG_B1_P2_U1_DCFG3 EQU 0x400114e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG4 +CYREG_B1_P2_U1_DCFG4 EQU 0x400114e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG5 +CYREG_B1_P2_U1_DCFG5 EQU 0x400114ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG6 +CYREG_B1_P2_U1_DCFG6 EQU 0x400114ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG7 +CYREG_B1_P2_U1_DCFG7 EQU 0x400114ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE +CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE +CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE +CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE +CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE +CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE +CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT0 +CYREG_B1_P3_U0_PLD_IT0 EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT1 +CYREG_B1_P3_U0_PLD_IT1 EQU 0x40011604 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT2 +CYREG_B1_P3_U0_PLD_IT2 EQU 0x40011608 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT3 +CYREG_B1_P3_U0_PLD_IT3 EQU 0x4001160c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT4 +CYREG_B1_P3_U0_PLD_IT4 EQU 0x40011610 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT5 +CYREG_B1_P3_U0_PLD_IT5 EQU 0x40011614 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT6 +CYREG_B1_P3_U0_PLD_IT6 EQU 0x40011618 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT7 +CYREG_B1_P3_U0_PLD_IT7 EQU 0x4001161c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT8 +CYREG_B1_P3_U0_PLD_IT8 EQU 0x40011620 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT9 +CYREG_B1_P3_U0_PLD_IT9 EQU 0x40011624 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT10 +CYREG_B1_P3_U0_PLD_IT10 EQU 0x40011628 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT11 +CYREG_B1_P3_U0_PLD_IT11 EQU 0x4001162c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT0 +CYREG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT1 +CYREG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT2 +CYREG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT3 +CYREG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_CEN_CONST +CYREG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_XORFB +CYREG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_SET_RESET +CYREG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_BYPASS +CYREG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG0 +CYREG_B1_P3_U0_CFG0 EQU 0x40011640 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG1 +CYREG_B1_P3_U0_CFG1 EQU 0x40011641 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG2 +CYREG_B1_P3_U0_CFG2 EQU 0x40011642 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG3 +CYREG_B1_P3_U0_CFG3 EQU 0x40011643 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG4 +CYREG_B1_P3_U0_CFG4 EQU 0x40011644 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG5 +CYREG_B1_P3_U0_CFG5 EQU 0x40011645 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG6 +CYREG_B1_P3_U0_CFG6 EQU 0x40011646 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG7 +CYREG_B1_P3_U0_CFG7 EQU 0x40011647 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG8 +CYREG_B1_P3_U0_CFG8 EQU 0x40011648 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG9 +CYREG_B1_P3_U0_CFG9 EQU 0x40011649 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG10 +CYREG_B1_P3_U0_CFG10 EQU 0x4001164a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG11 +CYREG_B1_P3_U0_CFG11 EQU 0x4001164b + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG12 +CYREG_B1_P3_U0_CFG12 EQU 0x4001164c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG13 +CYREG_B1_P3_U0_CFG13 EQU 0x4001164d + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG14 +CYREG_B1_P3_U0_CFG14 EQU 0x4001164e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG15 +CYREG_B1_P3_U0_CFG15 EQU 0x4001164f + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG16 +CYREG_B1_P3_U0_CFG16 EQU 0x40011650 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG17 +CYREG_B1_P3_U0_CFG17 EQU 0x40011651 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG18 +CYREG_B1_P3_U0_CFG18 EQU 0x40011652 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG19 +CYREG_B1_P3_U0_CFG19 EQU 0x40011653 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG20 +CYREG_B1_P3_U0_CFG20 EQU 0x40011654 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG21 +CYREG_B1_P3_U0_CFG21 EQU 0x40011655 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG22 +CYREG_B1_P3_U0_CFG22 EQU 0x40011656 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG23 +CYREG_B1_P3_U0_CFG23 EQU 0x40011657 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG24 +CYREG_B1_P3_U0_CFG24 EQU 0x40011658 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG25 +CYREG_B1_P3_U0_CFG25 EQU 0x40011659 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG26 +CYREG_B1_P3_U0_CFG26 EQU 0x4001165a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG27 +CYREG_B1_P3_U0_CFG27 EQU 0x4001165b + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG28 +CYREG_B1_P3_U0_CFG28 EQU 0x4001165c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG29 +CYREG_B1_P3_U0_CFG29 EQU 0x4001165d + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG30 +CYREG_B1_P3_U0_CFG30 EQU 0x4001165e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG31 +CYREG_B1_P3_U0_CFG31 EQU 0x4001165f + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG0 +CYREG_B1_P3_U0_DCFG0 EQU 0x40011660 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG1 +CYREG_B1_P3_U0_DCFG1 EQU 0x40011662 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG2 +CYREG_B1_P3_U0_DCFG2 EQU 0x40011664 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG3 +CYREG_B1_P3_U0_DCFG3 EQU 0x40011666 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG4 +CYREG_B1_P3_U0_DCFG4 EQU 0x40011668 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG5 +CYREG_B1_P3_U0_DCFG5 EQU 0x4001166a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG6 +CYREG_B1_P3_U0_DCFG6 EQU 0x4001166c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG7 +CYREG_B1_P3_U0_DCFG7 EQU 0x4001166e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE +CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE +CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT0 +CYREG_B1_P3_U1_PLD_IT0 EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT1 +CYREG_B1_P3_U1_PLD_IT1 EQU 0x40011684 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT2 +CYREG_B1_P3_U1_PLD_IT2 EQU 0x40011688 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT3 +CYREG_B1_P3_U1_PLD_IT3 EQU 0x4001168c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT4 +CYREG_B1_P3_U1_PLD_IT4 EQU 0x40011690 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT5 +CYREG_B1_P3_U1_PLD_IT5 EQU 0x40011694 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT6 +CYREG_B1_P3_U1_PLD_IT6 EQU 0x40011698 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT7 +CYREG_B1_P3_U1_PLD_IT7 EQU 0x4001169c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT8 +CYREG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT9 +CYREG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT10 +CYREG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT11 +CYREG_B1_P3_U1_PLD_IT11 EQU 0x400116ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT0 +CYREG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT1 +CYREG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT2 +CYREG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT3 +CYREG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_CEN_CONST +CYREG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_XORFB +CYREG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_SET_RESET +CYREG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_BYPASS +CYREG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG0 +CYREG_B1_P3_U1_CFG0 EQU 0x400116c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG1 +CYREG_B1_P3_U1_CFG1 EQU 0x400116c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG2 +CYREG_B1_P3_U1_CFG2 EQU 0x400116c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG3 +CYREG_B1_P3_U1_CFG3 EQU 0x400116c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG4 +CYREG_B1_P3_U1_CFG4 EQU 0x400116c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG5 +CYREG_B1_P3_U1_CFG5 EQU 0x400116c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG6 +CYREG_B1_P3_U1_CFG6 EQU 0x400116c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG7 +CYREG_B1_P3_U1_CFG7 EQU 0x400116c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG8 +CYREG_B1_P3_U1_CFG8 EQU 0x400116c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG9 +CYREG_B1_P3_U1_CFG9 EQU 0x400116c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG10 +CYREG_B1_P3_U1_CFG10 EQU 0x400116ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG11 +CYREG_B1_P3_U1_CFG11 EQU 0x400116cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG12 +CYREG_B1_P3_U1_CFG12 EQU 0x400116cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG13 +CYREG_B1_P3_U1_CFG13 EQU 0x400116cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG14 +CYREG_B1_P3_U1_CFG14 EQU 0x400116ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG15 +CYREG_B1_P3_U1_CFG15 EQU 0x400116cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG16 +CYREG_B1_P3_U1_CFG16 EQU 0x400116d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG17 +CYREG_B1_P3_U1_CFG17 EQU 0x400116d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG18 +CYREG_B1_P3_U1_CFG18 EQU 0x400116d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG19 +CYREG_B1_P3_U1_CFG19 EQU 0x400116d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG20 +CYREG_B1_P3_U1_CFG20 EQU 0x400116d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG21 +CYREG_B1_P3_U1_CFG21 EQU 0x400116d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG22 +CYREG_B1_P3_U1_CFG22 EQU 0x400116d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG23 +CYREG_B1_P3_U1_CFG23 EQU 0x400116d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG24 +CYREG_B1_P3_U1_CFG24 EQU 0x400116d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG25 +CYREG_B1_P3_U1_CFG25 EQU 0x400116d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG26 +CYREG_B1_P3_U1_CFG26 EQU 0x400116da + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG27 +CYREG_B1_P3_U1_CFG27 EQU 0x400116db + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG28 +CYREG_B1_P3_U1_CFG28 EQU 0x400116dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG29 +CYREG_B1_P3_U1_CFG29 EQU 0x400116dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG30 +CYREG_B1_P3_U1_CFG30 EQU 0x400116de + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG31 +CYREG_B1_P3_U1_CFG31 EQU 0x400116df + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG0 +CYREG_B1_P3_U1_DCFG0 EQU 0x400116e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG1 +CYREG_B1_P3_U1_DCFG1 EQU 0x400116e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG2 +CYREG_B1_P3_U1_DCFG2 EQU 0x400116e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG3 +CYREG_B1_P3_U1_DCFG3 EQU 0x400116e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG4 +CYREG_B1_P3_U1_DCFG4 EQU 0x400116e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG5 +CYREG_B1_P3_U1_DCFG5 EQU 0x400116ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG6 +CYREG_B1_P3_U1_DCFG6 EQU 0x400116ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG7 +CYREG_B1_P3_U1_DCFG7 EQU 0x400116ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE +CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE +CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE +CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE +CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE +CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE +CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT0 +CYREG_B1_P4_U0_PLD_IT0 EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT1 +CYREG_B1_P4_U0_PLD_IT1 EQU 0x40011804 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT2 +CYREG_B1_P4_U0_PLD_IT2 EQU 0x40011808 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT3 +CYREG_B1_P4_U0_PLD_IT3 EQU 0x4001180c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT4 +CYREG_B1_P4_U0_PLD_IT4 EQU 0x40011810 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT5 +CYREG_B1_P4_U0_PLD_IT5 EQU 0x40011814 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT6 +CYREG_B1_P4_U0_PLD_IT6 EQU 0x40011818 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT7 +CYREG_B1_P4_U0_PLD_IT7 EQU 0x4001181c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT8 +CYREG_B1_P4_U0_PLD_IT8 EQU 0x40011820 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT9 +CYREG_B1_P4_U0_PLD_IT9 EQU 0x40011824 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT10 +CYREG_B1_P4_U0_PLD_IT10 EQU 0x40011828 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT11 +CYREG_B1_P4_U0_PLD_IT11 EQU 0x4001182c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT0 +CYREG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT1 +CYREG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT2 +CYREG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT3 +CYREG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_CEN_CONST +CYREG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_XORFB +CYREG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_SET_RESET +CYREG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_BYPASS +CYREG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG0 +CYREG_B1_P4_U0_CFG0 EQU 0x40011840 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG1 +CYREG_B1_P4_U0_CFG1 EQU 0x40011841 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG2 +CYREG_B1_P4_U0_CFG2 EQU 0x40011842 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG3 +CYREG_B1_P4_U0_CFG3 EQU 0x40011843 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG4 +CYREG_B1_P4_U0_CFG4 EQU 0x40011844 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG5 +CYREG_B1_P4_U0_CFG5 EQU 0x40011845 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG6 +CYREG_B1_P4_U0_CFG6 EQU 0x40011846 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG7 +CYREG_B1_P4_U0_CFG7 EQU 0x40011847 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG8 +CYREG_B1_P4_U0_CFG8 EQU 0x40011848 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG9 +CYREG_B1_P4_U0_CFG9 EQU 0x40011849 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG10 +CYREG_B1_P4_U0_CFG10 EQU 0x4001184a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG11 +CYREG_B1_P4_U0_CFG11 EQU 0x4001184b + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG12 +CYREG_B1_P4_U0_CFG12 EQU 0x4001184c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG13 +CYREG_B1_P4_U0_CFG13 EQU 0x4001184d + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG14 +CYREG_B1_P4_U0_CFG14 EQU 0x4001184e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG15 +CYREG_B1_P4_U0_CFG15 EQU 0x4001184f + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG16 +CYREG_B1_P4_U0_CFG16 EQU 0x40011850 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG17 +CYREG_B1_P4_U0_CFG17 EQU 0x40011851 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG18 +CYREG_B1_P4_U0_CFG18 EQU 0x40011852 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG19 +CYREG_B1_P4_U0_CFG19 EQU 0x40011853 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG20 +CYREG_B1_P4_U0_CFG20 EQU 0x40011854 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG21 +CYREG_B1_P4_U0_CFG21 EQU 0x40011855 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG22 +CYREG_B1_P4_U0_CFG22 EQU 0x40011856 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG23 +CYREG_B1_P4_U0_CFG23 EQU 0x40011857 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG24 +CYREG_B1_P4_U0_CFG24 EQU 0x40011858 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG25 +CYREG_B1_P4_U0_CFG25 EQU 0x40011859 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG26 +CYREG_B1_P4_U0_CFG26 EQU 0x4001185a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG27 +CYREG_B1_P4_U0_CFG27 EQU 0x4001185b + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG28 +CYREG_B1_P4_U0_CFG28 EQU 0x4001185c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG29 +CYREG_B1_P4_U0_CFG29 EQU 0x4001185d + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG30 +CYREG_B1_P4_U0_CFG30 EQU 0x4001185e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG31 +CYREG_B1_P4_U0_CFG31 EQU 0x4001185f + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG0 +CYREG_B1_P4_U0_DCFG0 EQU 0x40011860 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG1 +CYREG_B1_P4_U0_DCFG1 EQU 0x40011862 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG2 +CYREG_B1_P4_U0_DCFG2 EQU 0x40011864 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG3 +CYREG_B1_P4_U0_DCFG3 EQU 0x40011866 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG4 +CYREG_B1_P4_U0_DCFG4 EQU 0x40011868 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG5 +CYREG_B1_P4_U0_DCFG5 EQU 0x4001186a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG6 +CYREG_B1_P4_U0_DCFG6 EQU 0x4001186c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG7 +CYREG_B1_P4_U0_DCFG7 EQU 0x4001186e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE +CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE +CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT0 +CYREG_B1_P4_U1_PLD_IT0 EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT1 +CYREG_B1_P4_U1_PLD_IT1 EQU 0x40011884 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT2 +CYREG_B1_P4_U1_PLD_IT2 EQU 0x40011888 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT3 +CYREG_B1_P4_U1_PLD_IT3 EQU 0x4001188c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT4 +CYREG_B1_P4_U1_PLD_IT4 EQU 0x40011890 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT5 +CYREG_B1_P4_U1_PLD_IT5 EQU 0x40011894 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT6 +CYREG_B1_P4_U1_PLD_IT6 EQU 0x40011898 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT7 +CYREG_B1_P4_U1_PLD_IT7 EQU 0x4001189c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT8 +CYREG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT9 +CYREG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT10 +CYREG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT11 +CYREG_B1_P4_U1_PLD_IT11 EQU 0x400118ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT0 +CYREG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT1 +CYREG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT2 +CYREG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT3 +CYREG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_CEN_CONST +CYREG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_XORFB +CYREG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_SET_RESET +CYREG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_BYPASS +CYREG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG0 +CYREG_B1_P4_U1_CFG0 EQU 0x400118c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG1 +CYREG_B1_P4_U1_CFG1 EQU 0x400118c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG2 +CYREG_B1_P4_U1_CFG2 EQU 0x400118c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG3 +CYREG_B1_P4_U1_CFG3 EQU 0x400118c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG4 +CYREG_B1_P4_U1_CFG4 EQU 0x400118c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG5 +CYREG_B1_P4_U1_CFG5 EQU 0x400118c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG6 +CYREG_B1_P4_U1_CFG6 EQU 0x400118c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG7 +CYREG_B1_P4_U1_CFG7 EQU 0x400118c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG8 +CYREG_B1_P4_U1_CFG8 EQU 0x400118c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG9 +CYREG_B1_P4_U1_CFG9 EQU 0x400118c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG10 +CYREG_B1_P4_U1_CFG10 EQU 0x400118ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG11 +CYREG_B1_P4_U1_CFG11 EQU 0x400118cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG12 +CYREG_B1_P4_U1_CFG12 EQU 0x400118cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG13 +CYREG_B1_P4_U1_CFG13 EQU 0x400118cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG14 +CYREG_B1_P4_U1_CFG14 EQU 0x400118ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG15 +CYREG_B1_P4_U1_CFG15 EQU 0x400118cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG16 +CYREG_B1_P4_U1_CFG16 EQU 0x400118d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG17 +CYREG_B1_P4_U1_CFG17 EQU 0x400118d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG18 +CYREG_B1_P4_U1_CFG18 EQU 0x400118d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG19 +CYREG_B1_P4_U1_CFG19 EQU 0x400118d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG20 +CYREG_B1_P4_U1_CFG20 EQU 0x400118d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG21 +CYREG_B1_P4_U1_CFG21 EQU 0x400118d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG22 +CYREG_B1_P4_U1_CFG22 EQU 0x400118d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG23 +CYREG_B1_P4_U1_CFG23 EQU 0x400118d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG24 +CYREG_B1_P4_U1_CFG24 EQU 0x400118d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG25 +CYREG_B1_P4_U1_CFG25 EQU 0x400118d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG26 +CYREG_B1_P4_U1_CFG26 EQU 0x400118da + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG27 +CYREG_B1_P4_U1_CFG27 EQU 0x400118db + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG28 +CYREG_B1_P4_U1_CFG28 EQU 0x400118dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG29 +CYREG_B1_P4_U1_CFG29 EQU 0x400118dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG30 +CYREG_B1_P4_U1_CFG30 EQU 0x400118de + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG31 +CYREG_B1_P4_U1_CFG31 EQU 0x400118df + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG0 +CYREG_B1_P4_U1_DCFG0 EQU 0x400118e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG1 +CYREG_B1_P4_U1_DCFG1 EQU 0x400118e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG2 +CYREG_B1_P4_U1_DCFG2 EQU 0x400118e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG3 +CYREG_B1_P4_U1_DCFG3 EQU 0x400118e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG4 +CYREG_B1_P4_U1_DCFG4 EQU 0x400118e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG5 +CYREG_B1_P4_U1_DCFG5 EQU 0x400118ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG6 +CYREG_B1_P4_U1_DCFG6 EQU 0x400118ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG7 +CYREG_B1_P4_U1_DCFG7 EQU 0x400118ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE +CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE +CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE +CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE +CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE +CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE +CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT0 +CYREG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT1 +CYREG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT2 +CYREG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT3 +CYREG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT4 +CYREG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT5 +CYREG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT6 +CYREG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT7 +CYREG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT8 +CYREG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT9 +CYREG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT10 +CYREG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT11 +CYREG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT0 +CYREG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT1 +CYREG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT2 +CYREG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT3 +CYREG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_CEN_CONST +CYREG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_XORFB +CYREG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_SET_RESET +CYREG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_BYPASS +CYREG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG0 +CYREG_B1_P5_U0_CFG0 EQU 0x40011a40 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG1 +CYREG_B1_P5_U0_CFG1 EQU 0x40011a41 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG2 +CYREG_B1_P5_U0_CFG2 EQU 0x40011a42 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG3 +CYREG_B1_P5_U0_CFG3 EQU 0x40011a43 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG4 +CYREG_B1_P5_U0_CFG4 EQU 0x40011a44 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG5 +CYREG_B1_P5_U0_CFG5 EQU 0x40011a45 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG6 +CYREG_B1_P5_U0_CFG6 EQU 0x40011a46 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG7 +CYREG_B1_P5_U0_CFG7 EQU 0x40011a47 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG8 +CYREG_B1_P5_U0_CFG8 EQU 0x40011a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG9 +CYREG_B1_P5_U0_CFG9 EQU 0x40011a49 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG10 +CYREG_B1_P5_U0_CFG10 EQU 0x40011a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG11 +CYREG_B1_P5_U0_CFG11 EQU 0x40011a4b + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG12 +CYREG_B1_P5_U0_CFG12 EQU 0x40011a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG13 +CYREG_B1_P5_U0_CFG13 EQU 0x40011a4d + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG14 +CYREG_B1_P5_U0_CFG14 EQU 0x40011a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG15 +CYREG_B1_P5_U0_CFG15 EQU 0x40011a4f + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG16 +CYREG_B1_P5_U0_CFG16 EQU 0x40011a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG17 +CYREG_B1_P5_U0_CFG17 EQU 0x40011a51 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG18 +CYREG_B1_P5_U0_CFG18 EQU 0x40011a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG19 +CYREG_B1_P5_U0_CFG19 EQU 0x40011a53 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG20 +CYREG_B1_P5_U0_CFG20 EQU 0x40011a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG21 +CYREG_B1_P5_U0_CFG21 EQU 0x40011a55 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG22 +CYREG_B1_P5_U0_CFG22 EQU 0x40011a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG23 +CYREG_B1_P5_U0_CFG23 EQU 0x40011a57 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG24 +CYREG_B1_P5_U0_CFG24 EQU 0x40011a58 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG25 +CYREG_B1_P5_U0_CFG25 EQU 0x40011a59 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG26 +CYREG_B1_P5_U0_CFG26 EQU 0x40011a5a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG27 +CYREG_B1_P5_U0_CFG27 EQU 0x40011a5b + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG28 +CYREG_B1_P5_U0_CFG28 EQU 0x40011a5c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG29 +CYREG_B1_P5_U0_CFG29 EQU 0x40011a5d + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG30 +CYREG_B1_P5_U0_CFG30 EQU 0x40011a5e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG31 +CYREG_B1_P5_U0_CFG31 EQU 0x40011a5f + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG0 +CYREG_B1_P5_U0_DCFG0 EQU 0x40011a60 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG1 +CYREG_B1_P5_U0_DCFG1 EQU 0x40011a62 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG2 +CYREG_B1_P5_U0_DCFG2 EQU 0x40011a64 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG3 +CYREG_B1_P5_U0_DCFG3 EQU 0x40011a66 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG4 +CYREG_B1_P5_U0_DCFG4 EQU 0x40011a68 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG5 +CYREG_B1_P5_U0_DCFG5 EQU 0x40011a6a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG6 +CYREG_B1_P5_U0_DCFG6 EQU 0x40011a6c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG7 +CYREG_B1_P5_U0_DCFG7 EQU 0x40011a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE +CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE +CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT0 +CYREG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT1 +CYREG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT2 +CYREG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT3 +CYREG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT4 +CYREG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT5 +CYREG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT6 +CYREG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT7 +CYREG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT8 +CYREG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT9 +CYREG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT10 +CYREG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT11 +CYREG_B1_P5_U1_PLD_IT11 EQU 0x40011aac + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT0 +CYREG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT1 +CYREG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT2 +CYREG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT3 +CYREG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_CEN_CONST +CYREG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_XORFB +CYREG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_SET_RESET +CYREG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_BYPASS +CYREG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG0 +CYREG_B1_P5_U1_CFG0 EQU 0x40011ac0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG1 +CYREG_B1_P5_U1_CFG1 EQU 0x40011ac1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG2 +CYREG_B1_P5_U1_CFG2 EQU 0x40011ac2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG3 +CYREG_B1_P5_U1_CFG3 EQU 0x40011ac3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG4 +CYREG_B1_P5_U1_CFG4 EQU 0x40011ac4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG5 +CYREG_B1_P5_U1_CFG5 EQU 0x40011ac5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG6 +CYREG_B1_P5_U1_CFG6 EQU 0x40011ac6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG7 +CYREG_B1_P5_U1_CFG7 EQU 0x40011ac7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG8 +CYREG_B1_P5_U1_CFG8 EQU 0x40011ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG9 +CYREG_B1_P5_U1_CFG9 EQU 0x40011ac9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG10 +CYREG_B1_P5_U1_CFG10 EQU 0x40011aca + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG11 +CYREG_B1_P5_U1_CFG11 EQU 0x40011acb + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG12 +CYREG_B1_P5_U1_CFG12 EQU 0x40011acc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG13 +CYREG_B1_P5_U1_CFG13 EQU 0x40011acd + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG14 +CYREG_B1_P5_U1_CFG14 EQU 0x40011ace + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG15 +CYREG_B1_P5_U1_CFG15 EQU 0x40011acf + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG16 +CYREG_B1_P5_U1_CFG16 EQU 0x40011ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG17 +CYREG_B1_P5_U1_CFG17 EQU 0x40011ad1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG18 +CYREG_B1_P5_U1_CFG18 EQU 0x40011ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG19 +CYREG_B1_P5_U1_CFG19 EQU 0x40011ad3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG20 +CYREG_B1_P5_U1_CFG20 EQU 0x40011ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG21 +CYREG_B1_P5_U1_CFG21 EQU 0x40011ad5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG22 +CYREG_B1_P5_U1_CFG22 EQU 0x40011ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG23 +CYREG_B1_P5_U1_CFG23 EQU 0x40011ad7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG24 +CYREG_B1_P5_U1_CFG24 EQU 0x40011ad8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG25 +CYREG_B1_P5_U1_CFG25 EQU 0x40011ad9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG26 +CYREG_B1_P5_U1_CFG26 EQU 0x40011ada + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG27 +CYREG_B1_P5_U1_CFG27 EQU 0x40011adb + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG28 +CYREG_B1_P5_U1_CFG28 EQU 0x40011adc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG29 +CYREG_B1_P5_U1_CFG29 EQU 0x40011add + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG30 +CYREG_B1_P5_U1_CFG30 EQU 0x40011ade + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG31 +CYREG_B1_P5_U1_CFG31 EQU 0x40011adf + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG0 +CYREG_B1_P5_U1_DCFG0 EQU 0x40011ae0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG1 +CYREG_B1_P5_U1_DCFG1 EQU 0x40011ae2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG2 +CYREG_B1_P5_U1_DCFG2 EQU 0x40011ae4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG3 +CYREG_B1_P5_U1_DCFG3 EQU 0x40011ae6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG4 +CYREG_B1_P5_U1_DCFG4 EQU 0x40011ae8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG5 +CYREG_B1_P5_U1_DCFG5 EQU 0x40011aea + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG6 +CYREG_B1_P5_U1_DCFG6 EQU 0x40011aec + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG7 +CYREG_B1_P5_U1_DCFG7 EQU 0x40011aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE +CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE +CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE +CYDEV_UCFG_DSI0_BASE EQU 0x40014000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE +CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE +CYDEV_UCFG_DSI1_BASE EQU 0x40014100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE +CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE +CYDEV_UCFG_DSI2_BASE EQU 0x40014200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE +CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE +CYDEV_UCFG_DSI3_BASE EQU 0x40014300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE +CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE +CYDEV_UCFG_DSI4_BASE EQU 0x40014400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE +CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE +CYDEV_UCFG_DSI5_BASE EQU 0x40014500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE +CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE +CYDEV_UCFG_DSI6_BASE EQU 0x40014600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE +CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE +CYDEV_UCFG_DSI7_BASE EQU 0x40014700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE +CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE +CYDEV_UCFG_DSI8_BASE EQU 0x40014800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE +CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE +CYDEV_UCFG_DSI9_BASE EQU 0x40014900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE +CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE +CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE +CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE +CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE +CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE +CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE +CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_MDCLK_EN +CYREG_BCTL0_MDCLK_EN EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_MBCLK_EN +CYREG_BCTL0_MBCLK_EN EQU 0x40015001 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_WAIT_CFG +CYREG_BCTL0_WAIT_CFG EQU 0x40015002 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BANK_CTL +CYREG_BCTL0_BANK_CTL EQU 0x40015003 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_UDB_TEST_3 +CYREG_BCTL0_UDB_TEST_3 EQU 0x40015007 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN0 +CYREG_BCTL0_DCLK_EN0 EQU 0x40015008 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN0 +CYREG_BCTL0_BCLK_EN0 EQU 0x40015009 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN1 +CYREG_BCTL0_DCLK_EN1 EQU 0x4001500a + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN1 +CYREG_BCTL0_BCLK_EN1 EQU 0x4001500b + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN2 +CYREG_BCTL0_DCLK_EN2 EQU 0x4001500c + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN2 +CYREG_BCTL0_BCLK_EN2 EQU 0x4001500d + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN3 +CYREG_BCTL0_DCLK_EN3 EQU 0x4001500e + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN3 +CYREG_BCTL0_BCLK_EN3 EQU 0x4001500f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE +CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE +CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_MDCLK_EN +CYREG_BCTL1_MDCLK_EN EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_MBCLK_EN +CYREG_BCTL1_MBCLK_EN EQU 0x40015011 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_WAIT_CFG +CYREG_BCTL1_WAIT_CFG EQU 0x40015012 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BANK_CTL +CYREG_BCTL1_BANK_CTL EQU 0x40015013 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_UDB_TEST_3 +CYREG_BCTL1_UDB_TEST_3 EQU 0x40015017 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN0 +CYREG_BCTL1_DCLK_EN0 EQU 0x40015018 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN0 +CYREG_BCTL1_BCLK_EN0 EQU 0x40015019 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN1 +CYREG_BCTL1_DCLK_EN1 EQU 0x4001501a + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN1 +CYREG_BCTL1_BCLK_EN1 EQU 0x4001501b + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN2 +CYREG_BCTL1_DCLK_EN2 EQU 0x4001501c + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN2 +CYREG_BCTL1_BCLK_EN2 EQU 0x4001501d + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN3 +CYREG_BCTL1_DCLK_EN3 EQU 0x4001501e + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN3 +CYREG_BCTL1_BCLK_EN3 EQU 0x4001501f + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_BASE +CYDEV_IDMUX_BASE EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_SIZE +CYDEV_IDMUX_SIZE EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL0 +CYREG_IDMUX_IRQ_CTL0 EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL1 +CYREG_IDMUX_IRQ_CTL1 EQU 0x40015101 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL2 +CYREG_IDMUX_IRQ_CTL2 EQU 0x40015102 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL3 +CYREG_IDMUX_IRQ_CTL3 EQU 0x40015103 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL4 +CYREG_IDMUX_IRQ_CTL4 EQU 0x40015104 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL5 +CYREG_IDMUX_IRQ_CTL5 EQU 0x40015105 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL6 +CYREG_IDMUX_IRQ_CTL6 EQU 0x40015106 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL7 +CYREG_IDMUX_IRQ_CTL7 EQU 0x40015107 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL0 +CYREG_IDMUX_DRQ_CTL0 EQU 0x40015110 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL1 +CYREG_IDMUX_DRQ_CTL1 EQU 0x40015111 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL2 +CYREG_IDMUX_DRQ_CTL2 EQU 0x40015112 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL3 +CYREG_IDMUX_DRQ_CTL3 EQU 0x40015113 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL4 +CYREG_IDMUX_DRQ_CTL4 EQU 0x40015114 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL5 +CYREG_IDMUX_DRQ_CTL5 EQU 0x40015115 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_BASE +CYDEV_CACHERAM_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_SIZE +CYDEV_CACHERAM_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYREG_CACHERAM_DATA_MBASE +CYREG_CACHERAM_DATA_MBASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYREG_CACHERAM_DATA_MSIZE +CYREG_CACHERAM_DATA_MSIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_BASE +CYDEV_SFR_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_SIZE +CYDEV_SFR_SIZE EQU 0x000000fb + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO0 +CYREG_SFR_GPIO0 EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD0 +CYREG_SFR_GPIRD0 EQU 0x40050189 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO0_SEL +CYREG_SFR_GPIO0_SEL EQU 0x4005018a + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO1 +CYREG_SFR_GPIO1 EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD1 +CYREG_SFR_GPIRD1 EQU 0x40050191 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO2 +CYREG_SFR_GPIO2 EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD2 +CYREG_SFR_GPIRD2 EQU 0x40050199 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO2_SEL +CYREG_SFR_GPIO2_SEL EQU 0x4005019a + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO1_SEL +CYREG_SFR_GPIO1_SEL EQU 0x400501a2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO3 +CYREG_SFR_GPIO3 EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD3 +CYREG_SFR_GPIRD3 EQU 0x400501b1 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO3_SEL +CYREG_SFR_GPIO3_SEL EQU 0x400501b2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO4 +CYREG_SFR_GPIO4 EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD4 +CYREG_SFR_GPIRD4 EQU 0x400501c1 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO4_SEL +CYREG_SFR_GPIO4_SEL EQU 0x400501c2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO5 +CYREG_SFR_GPIO5 EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD5 +CYREG_SFR_GPIRD5 EQU 0x400501c9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO5_SEL +CYREG_SFR_GPIO5_SEL EQU 0x400501ca + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO6 +CYREG_SFR_GPIO6 EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD6 +CYREG_SFR_GPIRD6 EQU 0x400501d9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO6_SEL +CYREG_SFR_GPIO6_SEL EQU 0x400501da + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO12 +CYREG_SFR_GPIO12 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD12 +CYREG_SFR_GPIRD12 EQU 0x400501e9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO12_SEL +CYREG_SFR_GPIO12_SEL EQU 0x400501f2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO15 +CYREG_SFR_GPIO15 EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD15 +CYREG_SFR_GPIRD15 EQU 0x400501f9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO15_SEL +CYREG_SFR_GPIO15_SEL EQU 0x400501fa + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BASE +CYDEV_P3BA_BASE EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SIZE +CYDEV_P3BA_SIZE EQU 0x0000002b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_Y_START +CYREG_P3BA_Y_START EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_YROLL +CYREG_P3BA_YROLL EQU 0x40050301 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_YCFG +CYREG_P3BA_YCFG EQU 0x40050302 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_START1 +CYREG_P3BA_X_START1 EQU 0x40050303 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_START2 +CYREG_P3BA_X_START2 EQU 0x40050304 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XROLL1 +CYREG_P3BA_XROLL1 EQU 0x40050305 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XROLL2 +CYREG_P3BA_XROLL2 EQU 0x40050306 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XINC +CYREG_P3BA_XINC EQU 0x40050307 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XCFG +CYREG_P3BA_XCFG EQU 0x40050308 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR1 +CYREG_P3BA_OFFSETADDR1 EQU 0x40050309 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR2 +CYREG_P3BA_OFFSETADDR2 EQU 0x4005030a + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR3 +CYREG_P3BA_OFFSETADDR3 EQU 0x4005030b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR1 +CYREG_P3BA_ABSADDR1 EQU 0x4005030c + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR2 +CYREG_P3BA_ABSADDR2 EQU 0x4005030d + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR3 +CYREG_P3BA_ABSADDR3 EQU 0x4005030e + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR4 +CYREG_P3BA_ABSADDR4 EQU 0x4005030f + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATCFG1 +CYREG_P3BA_DATCFG1 EQU 0x40050310 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATCFG2 +CYREG_P3BA_DATCFG2 EQU 0x40050311 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT1 +CYREG_P3BA_CMP_RSLT1 EQU 0x40050314 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT2 +CYREG_P3BA_CMP_RSLT2 EQU 0x40050315 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT3 +CYREG_P3BA_CMP_RSLT3 EQU 0x40050316 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT4 +CYREG_P3BA_CMP_RSLT4 EQU 0x40050317 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG1 +CYREG_P3BA_DATA_REG1 EQU 0x40050318 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG2 +CYREG_P3BA_DATA_REG2 EQU 0x40050319 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG3 +CYREG_P3BA_DATA_REG3 EQU 0x4005031a + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG4 +CYREG_P3BA_DATA_REG4 EQU 0x4005031b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA1 +CYREG_P3BA_EXP_DATA1 EQU 0x4005031c + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA2 +CYREG_P3BA_EXP_DATA2 EQU 0x4005031d + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA3 +CYREG_P3BA_EXP_DATA3 EQU 0x4005031e + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA4 +CYREG_P3BA_EXP_DATA4 EQU 0x4005031f + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA1 +CYREG_P3BA_MSTR_HRDATA1 EQU 0x40050320 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA2 +CYREG_P3BA_MSTR_HRDATA2 EQU 0x40050321 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA3 +CYREG_P3BA_MSTR_HRDATA3 EQU 0x40050322 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA4 +CYREG_P3BA_MSTR_HRDATA4 EQU 0x40050323 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_BIST_EN +CYREG_P3BA_BIST_EN EQU 0x40050324 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_PHUB_MASTER_SSR +CYREG_P3BA_PHUB_MASTER_SSR EQU 0x40050325 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_SEQCFG1 +CYREG_P3BA_SEQCFG1 EQU 0x40050326 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_SEQCFG2 +CYREG_P3BA_SEQCFG2 EQU 0x40050327 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_Y_CURR +CYREG_P3BA_Y_CURR EQU 0x40050328 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_CURR1 +CYREG_P3BA_X_CURR1 EQU 0x40050329 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_CURR2 +CYREG_P3BA_X_CURR2 EQU 0x4005032a + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_BASE +CYDEV_PANTHER_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_SIZE +CYDEV_PANTHER_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_STCALIB_CFG +CYREG_PANTHER_STCALIB_CFG EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_WAITPIPE +CYREG_PANTHER_WAITPIPE EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_TRACE_CFG +CYREG_PANTHER_TRACE_CFG EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_DBG_CFG +CYREG_PANTHER_DBG_CFG EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_CM3_LCKRST_STAT +CYREG_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_DEVICE_ID +CYREG_PANTHER_DEVICE_ID EQU 0x4008001c + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_BASE +CYDEV_FLSECC_BASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_SIZE +CYDEV_FLSECC_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_FLSECC_DATA_MBASE +CYREG_FLSECC_DATA_MBASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYREG_FLSECC_DATA_MSIZE +CYREG_FLSECC_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_BASE +CYDEV_FLSHID_BASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_SIZE +CYDEV_FLSHID_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_RSVD_MBASE +CYREG_FLSHID_RSVD_MBASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_RSVD_MSIZE +CYREG_FLSHID_RSVD_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MBASE +CYREG_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MSIZE +CYREG_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE +CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE +CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_Y_LOC +CYREG_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_X_LOC +CYREG_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WAFER_NUM +CYREG_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_LSB +CYREG_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_MSB +CYREG_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WRK_WK +CYREG_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_FAB_YR +CYREG_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_MINOR +CYREG_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_3MHZ +CYREG_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_6MHZ +CYREG_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_12MHZ +CYREG_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_24MHZ +CYREG_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_67MHZ +CYREG_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_80MHZ +CYREG_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_92MHZ +CYREG_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_USB +CYREG_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M1 +CYREG_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M2 +CYREG_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M3 +CYREG_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M4 +CYREG_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M5 +CYREG_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M6 +CYREG_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M7 +CYREG_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M8 +CYREG_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M1 +CYREG_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M2 +CYREG_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M3 +CYREG_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M4 +CYREG_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M5 +CYREG_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M6 +CYREG_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M7 +CYREG_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M8 +CYREG_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M1 +CYREG_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M2 +CYREG_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M3 +CYREG_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M4 +CYREG_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M5 +CYREG_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M6 +CYREG_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M7 +CYREG_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M8 +CYREG_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M1 +CYREG_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M2 +CYREG_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M3 +CYREG_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M4 +CYREG_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M5 +CYREG_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M6 +CYREG_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M7 +CYREG_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M8 +CYREG_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M1 +CYREG_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M2 +CYREG_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M3 +CYREG_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M4 +CYREG_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M5 +CYREG_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M6 +CYREG_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M7 +CYREG_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M8 +CYREG_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE +CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE +CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_IMO_TR1 +CYREG_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR0 +CYREG_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR0 +CYREG_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR0 +CYREG_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR0 +CYREG_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR1 +CYREG_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR1 +CYREG_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR1 +CYREG_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR1 +CYREG_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM +CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_BASE +CYDEV_EXTMEM_BASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_SIZE +CYDEV_EXTMEM_SIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYREG_EXTMEM_DATA_MBASE +CYREG_EXTMEM_DATA_MBASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYREG_EXTMEM_DATA_MSIZE +CYREG_EXTMEM_DATA_MSIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_BASE +CYDEV_ITM_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_SIZE +CYDEV_ITM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_EN +CYREG_ITM_TRACE_EN EQU 0xe0000e00 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_PRIVILEGE +CYREG_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_CTRL +CYREG_ITM_TRACE_CTRL EQU 0xe0000e80 + ENDIF + IF :LNOT::DEF:CYREG_ITM_LOCK_ACCESS +CYREG_ITM_LOCK_ACCESS EQU 0xe0000fb0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_LOCK_STATUS +CYREG_ITM_LOCK_STATUS EQU 0xe0000fb4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID4 +CYREG_ITM_PID4 EQU 0xe0000fd0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID5 +CYREG_ITM_PID5 EQU 0xe0000fd4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID6 +CYREG_ITM_PID6 EQU 0xe0000fd8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID7 +CYREG_ITM_PID7 EQU 0xe0000fdc + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID0 +CYREG_ITM_PID0 EQU 0xe0000fe0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID1 +CYREG_ITM_PID1 EQU 0xe0000fe4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID2 +CYREG_ITM_PID2 EQU 0xe0000fe8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID3 +CYREG_ITM_PID3 EQU 0xe0000fec + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID0 +CYREG_ITM_CID0 EQU 0xe0000ff0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID1 +CYREG_ITM_CID1 EQU 0xe0000ff4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID2 +CYREG_ITM_CID2 EQU 0xe0000ff8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID3 +CYREG_ITM_CID3 EQU 0xe0000ffc + ENDIF + IF :LNOT::DEF:CYDEV_DWT_BASE +CYDEV_DWT_BASE EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SIZE +CYDEV_DWT_SIZE EQU 0x0000005c + ENDIF + IF :LNOT::DEF:CYREG_DWT_CTRL +CYREG_DWT_CTRL EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYREG_DWT_CYCLE_COUNT +CYREG_DWT_CYCLE_COUNT EQU 0xe0001004 + ENDIF + IF :LNOT::DEF:CYREG_DWT_CPI_COUNT +CYREG_DWT_CPI_COUNT EQU 0xe0001008 + ENDIF + IF :LNOT::DEF:CYREG_DWT_EXC_OVHD_COUNT +CYREG_DWT_EXC_OVHD_COUNT EQU 0xe000100c + ENDIF + IF :LNOT::DEF:CYREG_DWT_SLEEP_COUNT +CYREG_DWT_SLEEP_COUNT EQU 0xe0001010 + ENDIF + IF :LNOT::DEF:CYREG_DWT_LSU_COUNT +CYREG_DWT_LSU_COUNT EQU 0xe0001014 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FOLD_COUNT +CYREG_DWT_FOLD_COUNT EQU 0xe0001018 + ENDIF + IF :LNOT::DEF:CYREG_DWT_PC_SAMPLE +CYREG_DWT_PC_SAMPLE EQU 0xe000101c + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_0 +CYREG_DWT_COMP_0 EQU 0xe0001020 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_0 +CYREG_DWT_MASK_0 EQU 0xe0001024 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_0 +CYREG_DWT_FUNCTION_0 EQU 0xe0001028 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_1 +CYREG_DWT_COMP_1 EQU 0xe0001030 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_1 +CYREG_DWT_MASK_1 EQU 0xe0001034 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_1 +CYREG_DWT_FUNCTION_1 EQU 0xe0001038 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_2 +CYREG_DWT_COMP_2 EQU 0xe0001040 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_2 +CYREG_DWT_MASK_2 EQU 0xe0001044 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_2 +CYREG_DWT_FUNCTION_2 EQU 0xe0001048 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_3 +CYREG_DWT_COMP_3 EQU 0xe0001050 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_3 +CYREG_DWT_MASK_3 EQU 0xe0001054 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_3 +CYREG_DWT_FUNCTION_3 EQU 0xe0001058 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_BASE +CYDEV_FPB_BASE EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_SIZE +CYDEV_FPB_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CTRL +CYREG_FPB_CTRL EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYREG_FPB_REMAP +CYREG_FPB_REMAP EQU 0xe0002004 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_0 +CYREG_FPB_FP_COMP_0 EQU 0xe0002008 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_1 +CYREG_FPB_FP_COMP_1 EQU 0xe000200c + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_2 +CYREG_FPB_FP_COMP_2 EQU 0xe0002010 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_3 +CYREG_FPB_FP_COMP_3 EQU 0xe0002014 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_4 +CYREG_FPB_FP_COMP_4 EQU 0xe0002018 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_5 +CYREG_FPB_FP_COMP_5 EQU 0xe000201c + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_6 +CYREG_FPB_FP_COMP_6 EQU 0xe0002020 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_7 +CYREG_FPB_FP_COMP_7 EQU 0xe0002024 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID4 +CYREG_FPB_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID5 +CYREG_FPB_PID5 EQU 0xe0002fd4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID6 +CYREG_FPB_PID6 EQU 0xe0002fd8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID7 +CYREG_FPB_PID7 EQU 0xe0002fdc + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID0 +CYREG_FPB_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID1 +CYREG_FPB_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID2 +CYREG_FPB_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID3 +CYREG_FPB_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID0 +CYREG_FPB_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID1 +CYREG_FPB_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID2 +CYREG_FPB_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID3 +CYREG_FPB_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BASE +CYDEV_NVIC_BASE EQU 0xe000e000 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SIZE +CYDEV_NVIC_SIZE EQU 0x00000d3c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_INT_CTL_TYPE +CYREG_NVIC_INT_CTL_TYPE EQU 0xe000e004 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CTL +CYREG_NVIC_SYSTICK_CTL EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_RELOAD +CYREG_NVIC_SYSTICK_RELOAD EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CURRENT +CYREG_NVIC_SYSTICK_CURRENT EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CAL +CYREG_NVIC_SYSTICK_CAL EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SETENA0 +CYREG_NVIC_SETENA0 EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CLRENA0 +CYREG_NVIC_CLRENA0 EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SETPEND0 +CYREG_NVIC_SETPEND0 EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CLRPEND0 +CYREG_NVIC_CLRPEND0 EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_ACTIVE0 +CYREG_NVIC_ACTIVE0 EQU 0xe000e300 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_0 +CYREG_NVIC_PRI_0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_1 +CYREG_NVIC_PRI_1 EQU 0xe000e401 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_2 +CYREG_NVIC_PRI_2 EQU 0xe000e402 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_3 +CYREG_NVIC_PRI_3 EQU 0xe000e403 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_4 +CYREG_NVIC_PRI_4 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_5 +CYREG_NVIC_PRI_5 EQU 0xe000e405 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_6 +CYREG_NVIC_PRI_6 EQU 0xe000e406 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_7 +CYREG_NVIC_PRI_7 EQU 0xe000e407 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_8 +CYREG_NVIC_PRI_8 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_9 +CYREG_NVIC_PRI_9 EQU 0xe000e409 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_10 +CYREG_NVIC_PRI_10 EQU 0xe000e40a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_11 +CYREG_NVIC_PRI_11 EQU 0xe000e40b + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_12 +CYREG_NVIC_PRI_12 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_13 +CYREG_NVIC_PRI_13 EQU 0xe000e40d + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_14 +CYREG_NVIC_PRI_14 EQU 0xe000e40e + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_15 +CYREG_NVIC_PRI_15 EQU 0xe000e40f + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_16 +CYREG_NVIC_PRI_16 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_17 +CYREG_NVIC_PRI_17 EQU 0xe000e411 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_18 +CYREG_NVIC_PRI_18 EQU 0xe000e412 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_19 +CYREG_NVIC_PRI_19 EQU 0xe000e413 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_20 +CYREG_NVIC_PRI_20 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_21 +CYREG_NVIC_PRI_21 EQU 0xe000e415 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_22 +CYREG_NVIC_PRI_22 EQU 0xe000e416 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_23 +CYREG_NVIC_PRI_23 EQU 0xe000e417 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_24 +CYREG_NVIC_PRI_24 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_25 +CYREG_NVIC_PRI_25 EQU 0xe000e419 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_26 +CYREG_NVIC_PRI_26 EQU 0xe000e41a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_27 +CYREG_NVIC_PRI_27 EQU 0xe000e41b + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_28 +CYREG_NVIC_PRI_28 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_29 +CYREG_NVIC_PRI_29 EQU 0xe000e41d + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_30 +CYREG_NVIC_PRI_30 EQU 0xe000e41e + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_31 +CYREG_NVIC_PRI_31 EQU 0xe000e41f + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CPUID_BASE +CYREG_NVIC_CPUID_BASE EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_INTR_CTRL_STATE +CYREG_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_VECT_OFFSET +CYREG_NVIC_VECT_OFFSET EQU 0xe000ed08 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_APPLN_INTR +CYREG_NVIC_APPLN_INTR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTEM_CONTROL +CYREG_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CFG_CONTROL +CYREG_NVIC_CFG_CONTROL EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_4_7 +CYREG_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_8_11 +CYREG_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_12_15 +CYREG_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_HANDLER_CSR +CYREG_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_STATUS +CYREG_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_STATUS +CYREG_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_USAGE_FAULT_STATUS +CYREG_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_HARD_FAULT_STATUS +CYREG_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_DEBUG_FAULT_STATUS +CYREG_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_ADD +CYREG_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_ADD +CYREG_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_BASE +CYDEV_CORE_DBG_BASE EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE +CYDEV_CORE_DBG_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_HLT_CS +CYREG_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_SEL +CYREG_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_DATA +CYREG_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_EXC_MON_CTL +CYREG_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_BASE +CYDEV_TPIU_BASE EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SIZE +CYDEV_TPIU_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ +CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CURRENT_SYNC_PRT_SZ +CYREG_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ASYNC_CLK_PRESCALER +CYREG_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PROTOCOL +CYREG_TPIU_PROTOCOL EQU 0xe00400f0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_STAT +CYREG_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_CTRL +CYREG_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_TRIGGER +CYREG_TPIU_TRIGGER EQU 0xe0040ee8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITETMDATA +CYREG_TPIU_ITETMDATA EQU 0xe0040eec + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITATBCTR2 +CYREG_TPIU_ITATBCTR2 EQU 0xe0040ef0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITATBCTR0 +CYREG_TPIU_ITATBCTR0 EQU 0xe0040ef8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITITMDATA +CYREG_TPIU_ITITMDATA EQU 0xe0040efc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITCTRL +CYREG_TPIU_ITCTRL EQU 0xe0040f00 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_DEVID +CYREG_TPIU_DEVID EQU 0xe0040fc8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_DEVTYPE +CYREG_TPIU_DEVTYPE EQU 0xe0040fcc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID4 +CYREG_TPIU_PID4 EQU 0xe0040fd0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID5 +CYREG_TPIU_PID5 EQU 0xe0040fd4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID6 +CYREG_TPIU_PID6 EQU 0xe0040fd8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID7 +CYREG_TPIU_PID7 EQU 0xe0040fdc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID0 +CYREG_TPIU_PID0 EQU 0xe0040fe0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID1 +CYREG_TPIU_PID1 EQU 0xe0040fe4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID2 +CYREG_TPIU_PID2 EQU 0xe0040fe8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID3 +CYREG_TPIU_PID3 EQU 0xe0040fec + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID0 +CYREG_TPIU_CID0 EQU 0xe0040ff0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID1 +CYREG_TPIU_CID1 EQU 0xe0040ff4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID2 +CYREG_TPIU_CID2 EQU 0xe0040ff8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID3 +CYREG_TPIU_CID3 EQU 0xe0040ffc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_BASE +CYDEV_ETM_BASE EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SIZE +CYDEV_ETM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CTL +CYREG_ETM_CTL EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CFG_CODE +CYREG_ETM_CFG_CODE EQU 0xe0041004 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRIG_EVENT +CYREG_ETM_TRIG_EVENT EQU 0xe0041008 + ENDIF + IF :LNOT::DEF:CYREG_ETM_STATUS +CYREG_ETM_STATUS EQU 0xe0041010 + ENDIF + IF :LNOT::DEF:CYREG_ETM_SYS_CFG +CYREG_ETM_SYS_CFG EQU 0xe0041014 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRACE_ENB_EVENT +CYREG_ETM_TRACE_ENB_EVENT EQU 0xe0041020 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRACE_EN_CTRL1 +CYREG_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 + ENDIF + IF :LNOT::DEF:CYREG_ETM_FIFOFULL_LEVEL +CYREG_ETM_FIFOFULL_LEVEL EQU 0xe004102c + ENDIF + IF :LNOT::DEF:CYREG_ETM_SYNC_FREQ +CYREG_ETM_SYNC_FREQ EQU 0xe00411e0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ETM_ID +CYREG_ETM_ETM_ID EQU 0xe00411e4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CFG_CODE_EXT +CYREG_ETM_CFG_CODE_EXT EQU 0xe00411e8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TR_SS_EMBICE_CTRL +CYREG_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CS_TRACE_ID +CYREG_ETM_CS_TRACE_ID EQU 0xe0041200 + ENDIF + IF :LNOT::DEF:CYREG_ETM_OS_LOCK_ACCESS +CYREG_ETM_OS_LOCK_ACCESS EQU 0xe0041300 + ENDIF + IF :LNOT::DEF:CYREG_ETM_OS_LOCK_STATUS +CYREG_ETM_OS_LOCK_STATUS EQU 0xe0041304 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PDSR +CYREG_ETM_PDSR EQU 0xe0041314 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITMISCIN +CYREG_ETM_ITMISCIN EQU 0xe0041ee0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITTRIGOUT +CYREG_ETM_ITTRIGOUT EQU 0xe0041ee8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITATBCTR2 +CYREG_ETM_ITATBCTR2 EQU 0xe0041ef0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITATBCTR0 +CYREG_ETM_ITATBCTR0 EQU 0xe0041ef8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_INT_MODE_CTRL +CYREG_ETM_INT_MODE_CTRL EQU 0xe0041f00 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CLM_TAG_SET +CYREG_ETM_CLM_TAG_SET EQU 0xe0041fa0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CLM_TAG_CLR +CYREG_ETM_CLM_TAG_CLR EQU 0xe0041fa4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_LOCK_ACCESS +CYREG_ETM_LOCK_ACCESS EQU 0xe0041fb0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_LOCK_STATUS +CYREG_ETM_LOCK_STATUS EQU 0xe0041fb4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_AUTH_STATUS +CYREG_ETM_AUTH_STATUS EQU 0xe0041fb8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_DEV_TYPE +CYREG_ETM_DEV_TYPE EQU 0xe0041fcc + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID4 +CYREG_ETM_PID4 EQU 0xe0041fd0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID5 +CYREG_ETM_PID5 EQU 0xe0041fd4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID6 +CYREG_ETM_PID6 EQU 0xe0041fd8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID7 +CYREG_ETM_PID7 EQU 0xe0041fdc + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID0 +CYREG_ETM_PID0 EQU 0xe0041fe0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID1 +CYREG_ETM_PID1 EQU 0xe0041fe4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID2 +CYREG_ETM_PID2 EQU 0xe0041fe8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID3 +CYREG_ETM_PID3 EQU 0xe0041fec + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID0 +CYREG_ETM_CID0 EQU 0xe0041ff0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID1 +CYREG_ETM_CID1 EQU 0xe0041ff4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID2 +CYREG_ETM_CID2 EQU 0xe0041ff8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID3 +CYREG_ETM_CID3 EQU 0xe0041ffc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE +CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE +CYDEV_ROM_TABLE_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_NVIC +CYREG_ROM_TABLE_NVIC EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_DWT +CYREG_ROM_TABLE_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_FPB +CYREG_ROM_TABLE_FPB EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_ITM +CYREG_ROM_TABLE_ITM EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_TPIU +CYREG_ROM_TABLE_TPIU EQU 0xe00ff010 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_ETM +CYREG_ROM_TABLE_ETM EQU 0xe00ff014 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_END +CYREG_ROM_TABLE_END EQU 0xe00ff018 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_MEMTYPE +CYREG_ROM_TABLE_MEMTYPE EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID4 +CYREG_ROM_TABLE_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID5 +CYREG_ROM_TABLE_PID5 EQU 0xe00fffd4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID6 +CYREG_ROM_TABLE_PID6 EQU 0xe00fffd8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID7 +CYREG_ROM_TABLE_PID7 EQU 0xe00fffdc + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID0 +CYREG_ROM_TABLE_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID1 +CYREG_ROM_TABLE_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID2 +CYREG_ROM_TABLE_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID3 +CYREG_ROM_TABLE_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID0 +CYREG_ROM_TABLE_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID1 +CYREG_ROM_TABLE_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID2 +CYREG_ROM_TABLE_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID3 +CYREG_ROM_TABLE_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SIZE +CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE + ENDIF + IF :LNOT::DEF:CYDEV_ECC_BASE +CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE +CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE +CYDEV_ECC_ROW_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE +CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE +CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PERIPH_BASE +CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE + ENDIF + IF :LNOT::DEF:CYCLK_LD_DISABLE +CYCLK_LD_DISABLE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYCLK_LD_SYNC_EN +CYCLK_LD_SYNC_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYCLK_LD_LOAD +CYCLK_LD_LOAD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYCLK_PIPE +CYCLK_PIPE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYCLK_SSS +CYCLK_SSS EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYCLK_EARLY +CYCLK_EARLY EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYCLK_DUTY +CYCLK_DUTY EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYCLK_SYNC +CYCLK_SYNC EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D +CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG +CYCLK_SRC_SEL_SYNC_DIG EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_IMO +CYCLK_SRC_SEL_IMO EQU 1 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ +CYCLK_SRC_SEL_XTAL_MHZ EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM +CYCLK_SRC_SEL_XTALM EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_ILO +CYCLK_SRC_SEL_ILO EQU 3 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_PLL +CYCLK_SRC_SEL_PLL EQU 4 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ +CYCLK_SRC_SEL_XTAL_KHZ EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK +CYCLK_SRC_SEL_XTALK EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G +CYCLK_SRC_SEL_DSI_G EQU 6 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D +CYCLK_SRC_SEL_DSI_D EQU 7 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A +CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A +CYCLK_SRC_SEL_DSI_A EQU 7 + ENDIF + END diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h new file mode 100644 index 0000000..2dec2e0 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -0,0 +1,1875 @@ +#ifndef INCLUDED_CYFITTER_H +#define INCLUDED_CYFITTER_H +#include +#include + +/* SDCard_RxInternalInterrupt */ +#define SDCard_RxInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SDCard_RxInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SDCard_RxInternalInterrupt__INTC_MASK 0x01u +#define SDCard_RxInternalInterrupt__INTC_NUMBER 0u +#define SDCard_RxInternalInterrupt__INTC_PRIOR_NUM 7u +#define SDCard_RxInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define SDCard_RxInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SDCard_RxInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SDCard_TxInternalInterrupt */ +#define SDCard_TxInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SDCard_TxInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SDCard_TxInternalInterrupt__INTC_MASK 0x02u +#define SDCard_TxInternalInterrupt__INTC_NUMBER 1u +#define SDCard_TxInternalInterrupt__INTC_PRIOR_NUM 7u +#define SDCard_TxInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define SDCard_TxInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SDCard_TxInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_Out_DBx */ +#define SCSI_Out_DBx__0__MASK 0x01u +#define SCSI_Out_DBx__0__PC CYREG_PRT0_PC0 +#define SCSI_Out_DBx__0__PORT 0u +#define SCSI_Out_DBx__0__SHIFT 0 +#define SCSI_Out_DBx__1__MASK 0x02u +#define SCSI_Out_DBx__1__PC CYREG_PRT0_PC1 +#define SCSI_Out_DBx__1__PORT 0u +#define SCSI_Out_DBx__1__SHIFT 1 +#define SCSI_Out_DBx__2__MASK 0x04u +#define SCSI_Out_DBx__2__PC CYREG_PRT0_PC2 +#define SCSI_Out_DBx__2__PORT 0u +#define SCSI_Out_DBx__2__SHIFT 2 +#define SCSI_Out_DBx__3__MASK 0x08u +#define SCSI_Out_DBx__3__PC CYREG_PRT0_PC3 +#define SCSI_Out_DBx__3__PORT 0u +#define SCSI_Out_DBx__3__SHIFT 3 +#define SCSI_Out_DBx__4__MASK 0x10u +#define SCSI_Out_DBx__4__PC CYREG_PRT0_PC4 +#define SCSI_Out_DBx__4__PORT 0u +#define SCSI_Out_DBx__4__SHIFT 4 +#define SCSI_Out_DBx__5__MASK 0x20u +#define SCSI_Out_DBx__5__PC CYREG_PRT0_PC5 +#define SCSI_Out_DBx__5__PORT 0u +#define SCSI_Out_DBx__5__SHIFT 5 +#define SCSI_Out_DBx__6__MASK 0x40u +#define SCSI_Out_DBx__6__PC CYREG_PRT0_PC6 +#define SCSI_Out_DBx__6__PORT 0u +#define SCSI_Out_DBx__6__SHIFT 6 +#define SCSI_Out_DBx__7__MASK 0x80u +#define SCSI_Out_DBx__7__PC CYREG_PRT0_PC7 +#define SCSI_Out_DBx__7__PORT 0u +#define SCSI_Out_DBx__7__SHIFT 7 +#define SCSI_Out_DBx__AG CYREG_PRT0_AG +#define SCSI_Out_DBx__AMUX CYREG_PRT0_AMUX +#define SCSI_Out_DBx__BIE CYREG_PRT0_BIE +#define SCSI_Out_DBx__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out_DBx__BYP CYREG_PRT0_BYP +#define SCSI_Out_DBx__CTL CYREG_PRT0_CTL +#define SCSI_Out_DBx__DM0 CYREG_PRT0_DM0 +#define SCSI_Out_DBx__DM1 CYREG_PRT0_DM1 +#define SCSI_Out_DBx__DM2 CYREG_PRT0_DM2 +#define SCSI_Out_DBx__DR CYREG_PRT0_DR +#define SCSI_Out_DBx__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out_DBx__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out_DBx__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out_DBx__MASK 0xFFu +#define SCSI_Out_DBx__PORT 0u +#define SCSI_Out_DBx__PRT CYREG_PRT0_PRT +#define SCSI_Out_DBx__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out_DBx__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out_DBx__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out_DBx__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out_DBx__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out_DBx__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out_DBx__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out_DBx__PS CYREG_PRT0_PS +#define SCSI_Out_DBx__SCSI_Out_DB0__MASK 0x01u +#define SCSI_Out_DBx__SCSI_Out_DB0__PC CYREG_PRT0_PC0 +#define SCSI_Out_DBx__SCSI_Out_DB0__PORT 0u +#define SCSI_Out_DBx__SCSI_Out_DB0__SHIFT 0 +#define SCSI_Out_DBx__SCSI_Out_DB1__MASK 0x02u +#define SCSI_Out_DBx__SCSI_Out_DB1__PC CYREG_PRT0_PC1 +#define SCSI_Out_DBx__SCSI_Out_DB1__PORT 0u +#define SCSI_Out_DBx__SCSI_Out_DB1__SHIFT 1 +#define SCSI_Out_DBx__SCSI_Out_DB2__MASK 0x04u +#define SCSI_Out_DBx__SCSI_Out_DB2__PC CYREG_PRT0_PC2 +#define SCSI_Out_DBx__SCSI_Out_DB2__PORT 0u +#define SCSI_Out_DBx__SCSI_Out_DB2__SHIFT 2 +#define SCSI_Out_DBx__SCSI_Out_DB3__MASK 0x08u +#define SCSI_Out_DBx__SCSI_Out_DB3__PC CYREG_PRT0_PC3 +#define SCSI_Out_DBx__SCSI_Out_DB3__PORT 0u +#define SCSI_Out_DBx__SCSI_Out_DB3__SHIFT 3 +#define SCSI_Out_DBx__SCSI_Out_DB4__MASK 0x10u +#define SCSI_Out_DBx__SCSI_Out_DB4__PC CYREG_PRT0_PC4 +#define SCSI_Out_DBx__SCSI_Out_DB4__PORT 0u +#define SCSI_Out_DBx__SCSI_Out_DB4__SHIFT 4 +#define SCSI_Out_DBx__SCSI_Out_DB5__MASK 0x20u +#define SCSI_Out_DBx__SCSI_Out_DB5__PC CYREG_PRT0_PC5 +#define SCSI_Out_DBx__SCSI_Out_DB5__PORT 0u +#define SCSI_Out_DBx__SCSI_Out_DB5__SHIFT 5 +#define SCSI_Out_DBx__SCSI_Out_DB6__MASK 0x40u +#define SCSI_Out_DBx__SCSI_Out_DB6__PC CYREG_PRT0_PC6 +#define SCSI_Out_DBx__SCSI_Out_DB6__PORT 0u +#define SCSI_Out_DBx__SCSI_Out_DB6__SHIFT 6 +#define SCSI_Out_DBx__SCSI_Out_DB7__MASK 0x80u +#define SCSI_Out_DBx__SCSI_Out_DB7__PC CYREG_PRT0_PC7 +#define SCSI_Out_DBx__SCSI_Out_DB7__PORT 0u +#define SCSI_Out_DBx__SCSI_Out_DB7__SHIFT 7 +#define SCSI_Out_DBx__SHIFT 0 +#define SCSI_Out_DBx__SLW CYREG_PRT0_SLW + +/* SDCard_BSPIM */ +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_RxStsReg__4__POS 4 +#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u +#define SDCard_BSPIM_RxStsReg__5__POS 5 +#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u +#define SDCard_BSPIM_RxStsReg__6__POS 6 +#define SDCard_BSPIM_RxStsReg__MASK 0x70u +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST +#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u +#define SDCard_BSPIM_TxStsReg__0__POS 0 +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST +#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u +#define SDCard_BSPIM_TxStsReg__1__POS 1 +#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u +#define SDCard_BSPIM_TxStsReg__2__POS 2 +#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u +#define SDCard_BSPIM_TxStsReg__3__POS 3 +#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_TxStsReg__4__POS 4 +#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB07_08_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB07_08_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB07_08_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB07_08_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB07_08_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB07_08_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB07_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB07_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB07_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB07_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB07_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB07_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB07_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB07_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB07_F1 +#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL + +/* SCSI_In_DBx */ +#define SCSI_In_DBx__0__MASK 0x01u +#define SCSI_In_DBx__0__PC CYREG_PRT2_PC0 +#define SCSI_In_DBx__0__PORT 2u +#define SCSI_In_DBx__0__SHIFT 0 +#define SCSI_In_DBx__1__MASK 0x02u +#define SCSI_In_DBx__1__PC CYREG_PRT2_PC1 +#define SCSI_In_DBx__1__PORT 2u +#define SCSI_In_DBx__1__SHIFT 1 +#define SCSI_In_DBx__2__MASK 0x04u +#define SCSI_In_DBx__2__PC CYREG_PRT2_PC2 +#define SCSI_In_DBx__2__PORT 2u +#define SCSI_In_DBx__2__SHIFT 2 +#define SCSI_In_DBx__3__MASK 0x08u +#define SCSI_In_DBx__3__PC CYREG_PRT2_PC3 +#define SCSI_In_DBx__3__PORT 2u +#define SCSI_In_DBx__3__SHIFT 3 +#define SCSI_In_DBx__4__MASK 0x10u +#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4 +#define SCSI_In_DBx__4__PORT 2u +#define SCSI_In_DBx__4__SHIFT 4 +#define SCSI_In_DBx__5__MASK 0x20u +#define SCSI_In_DBx__5__PC CYREG_PRT2_PC5 +#define SCSI_In_DBx__5__PORT 2u +#define SCSI_In_DBx__5__SHIFT 5 +#define SCSI_In_DBx__6__MASK 0x40u +#define SCSI_In_DBx__6__PC CYREG_PRT2_PC6 +#define SCSI_In_DBx__6__PORT 2u +#define SCSI_In_DBx__6__SHIFT 6 +#define SCSI_In_DBx__7__MASK 0x80u +#define SCSI_In_DBx__7__PC CYREG_PRT2_PC7 +#define SCSI_In_DBx__7__PORT 2u +#define SCSI_In_DBx__7__SHIFT 7 +#define SCSI_In_DBx__AG CYREG_PRT2_AG +#define SCSI_In_DBx__AMUX CYREG_PRT2_AMUX +#define SCSI_In_DBx__BIE CYREG_PRT2_BIE +#define SCSI_In_DBx__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In_DBx__BYP CYREG_PRT2_BYP +#define SCSI_In_DBx__CTL CYREG_PRT2_CTL +#define SCSI_In_DBx__DM0 CYREG_PRT2_DM0 +#define SCSI_In_DBx__DM1 CYREG_PRT2_DM1 +#define SCSI_In_DBx__DM2 CYREG_PRT2_DM2 +#define SCSI_In_DBx__DR CYREG_PRT2_DR +#define SCSI_In_DBx__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In_DBx__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In_DBx__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In_DBx__MASK 0xFFu +#define SCSI_In_DBx__PORT 2u +#define SCSI_In_DBx__PRT CYREG_PRT2_PRT +#define SCSI_In_DBx__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In_DBx__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In_DBx__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In_DBx__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In_DBx__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In_DBx__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In_DBx__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In_DBx__PS CYREG_PRT2_PS +#define SCSI_In_DBx__SCSI_Out_DB0__MASK 0x01u +#define SCSI_In_DBx__SCSI_Out_DB0__PC CYREG_PRT2_PC0 +#define SCSI_In_DBx__SCSI_Out_DB0__PORT 2u +#define SCSI_In_DBx__SCSI_Out_DB0__SHIFT 0 +#define SCSI_In_DBx__SCSI_Out_DB1__MASK 0x02u +#define SCSI_In_DBx__SCSI_Out_DB1__PC CYREG_PRT2_PC1 +#define SCSI_In_DBx__SCSI_Out_DB1__PORT 2u +#define SCSI_In_DBx__SCSI_Out_DB1__SHIFT 1 +#define SCSI_In_DBx__SCSI_Out_DB2__MASK 0x04u +#define SCSI_In_DBx__SCSI_Out_DB2__PC CYREG_PRT2_PC2 +#define SCSI_In_DBx__SCSI_Out_DB2__PORT 2u +#define SCSI_In_DBx__SCSI_Out_DB2__SHIFT 2 +#define SCSI_In_DBx__SCSI_Out_DB3__MASK 0x08u +#define SCSI_In_DBx__SCSI_Out_DB3__PC CYREG_PRT2_PC3 +#define SCSI_In_DBx__SCSI_Out_DB3__PORT 2u +#define SCSI_In_DBx__SCSI_Out_DB3__SHIFT 3 +#define SCSI_In_DBx__SCSI_Out_DB4__MASK 0x10u +#define SCSI_In_DBx__SCSI_Out_DB4__PC CYREG_PRT2_PC4 +#define SCSI_In_DBx__SCSI_Out_DB4__PORT 2u +#define SCSI_In_DBx__SCSI_Out_DB4__SHIFT 4 +#define SCSI_In_DBx__SCSI_Out_DB5__MASK 0x20u +#define SCSI_In_DBx__SCSI_Out_DB5__PC CYREG_PRT2_PC5 +#define SCSI_In_DBx__SCSI_Out_DB5__PORT 2u +#define SCSI_In_DBx__SCSI_Out_DB5__SHIFT 5 +#define SCSI_In_DBx__SCSI_Out_DB6__MASK 0x40u +#define SCSI_In_DBx__SCSI_Out_DB6__PC CYREG_PRT2_PC6 +#define SCSI_In_DBx__SCSI_Out_DB6__PORT 2u +#define SCSI_In_DBx__SCSI_Out_DB6__SHIFT 6 +#define SCSI_In_DBx__SCSI_Out_DB7__MASK 0x80u +#define SCSI_In_DBx__SCSI_Out_DB7__PC CYREG_PRT2_PC7 +#define SCSI_In_DBx__SCSI_Out_DB7__PORT 2u +#define SCSI_In_DBx__SCSI_Out_DB7__SHIFT 7 +#define SCSI_In_DBx__SHIFT 0 +#define SCSI_In_DBx__SLW CYREG_PRT2_SLW + +/* SD_Data_Clk */ +#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 +#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 +#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 +#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u +#define SD_Data_Clk__INDEX 0x00u +#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SD_Data_Clk__PM_ACT_MSK 0x01u +#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SD_Data_Clk__PM_STBY_MSK 0x01u + +/* SD_Init_Clk */ +#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG1_CFG0 +#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG1_CFG1 +#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG1_CFG2 +#define SD_Init_Clk__CFG2_SRC_SEL_MASK 0x07u +#define SD_Init_Clk__INDEX 0x01u +#define SD_Init_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SD_Init_Clk__PM_ACT_MSK 0x02u +#define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SD_Init_Clk__PM_STBY_MSK 0x02u + +/* SD_Clk_Ctl */ +#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u +#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0 +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB05_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB05_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u +#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB05_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL + +/* PARITY_EN */ +#define PARITY_EN__0__MASK 0x10u +#define PARITY_EN__0__PC CYREG_PRT5_PC4 +#define PARITY_EN__0__PORT 5u +#define PARITY_EN__0__SHIFT 4 +#define PARITY_EN__AG CYREG_PRT5_AG +#define PARITY_EN__AMUX CYREG_PRT5_AMUX +#define PARITY_EN__BIE CYREG_PRT5_BIE +#define PARITY_EN__BIT_MASK CYREG_PRT5_BIT_MASK +#define PARITY_EN__BYP CYREG_PRT5_BYP +#define PARITY_EN__CTL CYREG_PRT5_CTL +#define PARITY_EN__DM0 CYREG_PRT5_DM0 +#define PARITY_EN__DM1 CYREG_PRT5_DM1 +#define PARITY_EN__DM2 CYREG_PRT5_DM2 +#define PARITY_EN__DR CYREG_PRT5_DR +#define PARITY_EN__INP_DIS CYREG_PRT5_INP_DIS +#define PARITY_EN__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define PARITY_EN__LCD_EN CYREG_PRT5_LCD_EN +#define PARITY_EN__MASK 0x10u +#define PARITY_EN__PORT 5u +#define PARITY_EN__PRT CYREG_PRT5_PRT +#define PARITY_EN__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define PARITY_EN__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define PARITY_EN__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define PARITY_EN__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define PARITY_EN__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define PARITY_EN__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define PARITY_EN__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define PARITY_EN__PS CYREG_PRT5_PS +#define PARITY_EN__SHIFT 4 +#define PARITY_EN__SLW CYREG_PRT5_SLW + +/* SCSI_Out */ +#define SCSI_Out__0__AG CYREG_PRT4_AG +#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__0__BIE CYREG_PRT4_BIE +#define SCSI_Out__0__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__0__BYP CYREG_PRT4_BYP +#define SCSI_Out__0__CTL CYREG_PRT4_CTL +#define SCSI_Out__0__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__0__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__0__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__0__DR CYREG_PRT4_DR +#define SCSI_Out__0__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__0__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__0__MASK 0x04u +#define SCSI_Out__0__PC CYREG_PRT4_PC2 +#define SCSI_Out__0__PORT 4u +#define SCSI_Out__0__PRT CYREG_PRT4_PRT +#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__0__PS CYREG_PRT4_PS +#define SCSI_Out__0__SHIFT 2 +#define SCSI_Out__0__SLW CYREG_PRT4_SLW +#define SCSI_Out__1__AG CYREG_PRT4_AG +#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__1__BIE CYREG_PRT4_BIE +#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__1__BYP CYREG_PRT4_BYP +#define SCSI_Out__1__CTL CYREG_PRT4_CTL +#define SCSI_Out__1__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__1__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__1__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__1__DR CYREG_PRT4_DR +#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__1__MASK 0x08u +#define SCSI_Out__1__PC CYREG_PRT4_PC3 +#define SCSI_Out__1__PORT 4u +#define SCSI_Out__1__PRT CYREG_PRT4_PRT +#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__1__PS CYREG_PRT4_PS +#define SCSI_Out__1__SHIFT 3 +#define SCSI_Out__1__SLW CYREG_PRT4_SLW +#define SCSI_Out__2__AG CYREG_PRT4_AG +#define SCSI_Out__2__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__2__BIE CYREG_PRT4_BIE +#define SCSI_Out__2__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__2__BYP CYREG_PRT4_BYP +#define SCSI_Out__2__CTL CYREG_PRT4_CTL +#define SCSI_Out__2__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__2__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__2__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__2__DR CYREG_PRT4_DR +#define SCSI_Out__2__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__2__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__2__MASK 0x10u +#define SCSI_Out__2__PC CYREG_PRT4_PC4 +#define SCSI_Out__2__PORT 4u +#define SCSI_Out__2__PRT CYREG_PRT4_PRT +#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__2__PS CYREG_PRT4_PS +#define SCSI_Out__2__SHIFT 4 +#define SCSI_Out__2__SLW CYREG_PRT4_SLW +#define SCSI_Out__3__AG CYREG_PRT4_AG +#define SCSI_Out__3__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__3__BIE CYREG_PRT4_BIE +#define SCSI_Out__3__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__3__BYP CYREG_PRT4_BYP +#define SCSI_Out__3__CTL CYREG_PRT4_CTL +#define SCSI_Out__3__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__3__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__3__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__3__DR CYREG_PRT4_DR +#define SCSI_Out__3__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__3__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__3__MASK 0x20u +#define SCSI_Out__3__PC CYREG_PRT4_PC5 +#define SCSI_Out__3__PORT 4u +#define SCSI_Out__3__PRT CYREG_PRT4_PRT +#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__3__PS CYREG_PRT4_PS +#define SCSI_Out__3__SHIFT 5 +#define SCSI_Out__3__SLW CYREG_PRT4_SLW +#define SCSI_Out__4__AG CYREG_PRT4_AG +#define SCSI_Out__4__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__4__BIE CYREG_PRT4_BIE +#define SCSI_Out__4__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__4__BYP CYREG_PRT4_BYP +#define SCSI_Out__4__CTL CYREG_PRT4_CTL +#define SCSI_Out__4__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__4__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__4__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__4__DR CYREG_PRT4_DR +#define SCSI_Out__4__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__4__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__4__MASK 0x40u +#define SCSI_Out__4__PC CYREG_PRT4_PC6 +#define SCSI_Out__4__PORT 4u +#define SCSI_Out__4__PRT CYREG_PRT4_PRT +#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__4__PS CYREG_PRT4_PS +#define SCSI_Out__4__SHIFT 6 +#define SCSI_Out__4__SLW CYREG_PRT4_SLW +#define SCSI_Out__5__AG CYREG_PRT4_AG +#define SCSI_Out__5__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__5__BIE CYREG_PRT4_BIE +#define SCSI_Out__5__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__5__BYP CYREG_PRT4_BYP +#define SCSI_Out__5__CTL CYREG_PRT4_CTL +#define SCSI_Out__5__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__5__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__5__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__5__DR CYREG_PRT4_DR +#define SCSI_Out__5__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__5__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__5__MASK 0x80u +#define SCSI_Out__5__PC CYREG_PRT4_PC7 +#define SCSI_Out__5__PORT 4u +#define SCSI_Out__5__PRT CYREG_PRT4_PRT +#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__5__PS CYREG_PRT4_PS +#define SCSI_Out__5__SHIFT 7 +#define SCSI_Out__5__SLW CYREG_PRT4_SLW +#define SCSI_Out__6__AG CYREG_PRT6_AG +#define SCSI_Out__6__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__6__BIE CYREG_PRT6_BIE +#define SCSI_Out__6__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__6__BYP CYREG_PRT6_BYP +#define SCSI_Out__6__CTL CYREG_PRT6_CTL +#define SCSI_Out__6__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__6__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__6__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__6__DR CYREG_PRT6_DR +#define SCSI_Out__6__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__6__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__6__MASK 0x01u +#define SCSI_Out__6__PC CYREG_PRT6_PC0 +#define SCSI_Out__6__PORT 6u +#define SCSI_Out__6__PRT CYREG_PRT6_PRT +#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__6__PS CYREG_PRT6_PS +#define SCSI_Out__6__SHIFT 0 +#define SCSI_Out__6__SLW CYREG_PRT6_SLW +#define SCSI_Out__7__AG CYREG_PRT6_AG +#define SCSI_Out__7__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__7__BIE CYREG_PRT6_BIE +#define SCSI_Out__7__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__7__BYP CYREG_PRT6_BYP +#define SCSI_Out__7__CTL CYREG_PRT6_CTL +#define SCSI_Out__7__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__7__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__7__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__7__DR CYREG_PRT6_DR +#define SCSI_Out__7__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__7__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__7__MASK 0x02u +#define SCSI_Out__7__PC CYREG_PRT6_PC1 +#define SCSI_Out__7__PORT 6u +#define SCSI_Out__7__PRT CYREG_PRT6_PRT +#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__7__PS CYREG_PRT6_PS +#define SCSI_Out__7__SHIFT 1 +#define SCSI_Out__7__SLW CYREG_PRT6_SLW +#define SCSI_Out__8__AG CYREG_PRT6_AG +#define SCSI_Out__8__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__8__BIE CYREG_PRT6_BIE +#define SCSI_Out__8__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__8__BYP CYREG_PRT6_BYP +#define SCSI_Out__8__CTL CYREG_PRT6_CTL +#define SCSI_Out__8__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__8__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__8__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__8__DR CYREG_PRT6_DR +#define SCSI_Out__8__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__8__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__8__MASK 0x04u +#define SCSI_Out__8__PC CYREG_PRT6_PC2 +#define SCSI_Out__8__PORT 6u +#define SCSI_Out__8__PRT CYREG_PRT6_PRT +#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__8__PS CYREG_PRT6_PS +#define SCSI_Out__8__SHIFT 2 +#define SCSI_Out__8__SLW CYREG_PRT6_SLW +#define SCSI_Out__9__AG CYREG_PRT6_AG +#define SCSI_Out__9__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__9__BIE CYREG_PRT6_BIE +#define SCSI_Out__9__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__9__BYP CYREG_PRT6_BYP +#define SCSI_Out__9__CTL CYREG_PRT6_CTL +#define SCSI_Out__9__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__9__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__9__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__9__DR CYREG_PRT6_DR +#define SCSI_Out__9__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__9__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__9__MASK 0x08u +#define SCSI_Out__9__PC CYREG_PRT6_PC3 +#define SCSI_Out__9__PORT 6u +#define SCSI_Out__9__PRT CYREG_PRT6_PRT +#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__9__PS CYREG_PRT6_PS +#define SCSI_Out__9__SHIFT 3 +#define SCSI_Out__9__SLW CYREG_PRT6_SLW +#define SCSI_Out__ACK__AG CYREG_PRT4_AG +#define SCSI_Out__ACK__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__ACK__BIE CYREG_PRT4_BIE +#define SCSI_Out__ACK__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__ACK__BYP CYREG_PRT4_BYP +#define SCSI_Out__ACK__CTL CYREG_PRT4_CTL +#define SCSI_Out__ACK__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__ACK__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__ACK__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__ACK__DR CYREG_PRT4_DR +#define SCSI_Out__ACK__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__ACK__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__ACK__MASK 0x20u +#define SCSI_Out__ACK__PC CYREG_PRT4_PC5 +#define SCSI_Out__ACK__PORT 4u +#define SCSI_Out__ACK__PRT CYREG_PRT4_PRT +#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__ACK__PS CYREG_PRT4_PS +#define SCSI_Out__ACK__SHIFT 5 +#define SCSI_Out__ACK__SLW CYREG_PRT4_SLW +#define SCSI_Out__ATN__AG CYREG_PRT4_AG +#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__ATN__BIE CYREG_PRT4_BIE +#define SCSI_Out__ATN__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__ATN__BYP CYREG_PRT4_BYP +#define SCSI_Out__ATN__CTL CYREG_PRT4_CTL +#define SCSI_Out__ATN__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__ATN__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__ATN__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__ATN__DR CYREG_PRT4_DR +#define SCSI_Out__ATN__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__ATN__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__ATN__MASK 0x08u +#define SCSI_Out__ATN__PC CYREG_PRT4_PC3 +#define SCSI_Out__ATN__PORT 4u +#define SCSI_Out__ATN__PRT CYREG_PRT4_PRT +#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__ATN__PS CYREG_PRT4_PS +#define SCSI_Out__ATN__SHIFT 3 +#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW +#define SCSI_Out__BSY__AG CYREG_PRT4_AG +#define SCSI_Out__BSY__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__BSY__BIE CYREG_PRT4_BIE +#define SCSI_Out__BSY__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__BSY__BYP CYREG_PRT4_BYP +#define SCSI_Out__BSY__CTL CYREG_PRT4_CTL +#define SCSI_Out__BSY__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__BSY__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__BSY__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__BSY__DR CYREG_PRT4_DR +#define SCSI_Out__BSY__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__BSY__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__BSY__MASK 0x10u +#define SCSI_Out__BSY__PC CYREG_PRT4_PC4 +#define SCSI_Out__BSY__PORT 4u +#define SCSI_Out__BSY__PRT CYREG_PRT4_PRT +#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__BSY__PS CYREG_PRT4_PS +#define SCSI_Out__BSY__SHIFT 4 +#define SCSI_Out__BSY__SLW CYREG_PRT4_SLW +#define SCSI_Out__CD__AG CYREG_PRT6_AG +#define SCSI_Out__CD__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__CD__BIE CYREG_PRT6_BIE +#define SCSI_Out__CD__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__CD__BYP CYREG_PRT6_BYP +#define SCSI_Out__CD__CTL CYREG_PRT6_CTL +#define SCSI_Out__CD__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__CD__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__CD__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__CD__DR CYREG_PRT6_DR +#define SCSI_Out__CD__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__CD__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__CD__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__CD__MASK 0x02u +#define SCSI_Out__CD__PC CYREG_PRT6_PC1 +#define SCSI_Out__CD__PORT 6u +#define SCSI_Out__CD__PRT CYREG_PRT6_PRT +#define SCSI_Out__CD__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__CD__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__CD__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__CD__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__CD__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__CD__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__CD__PS CYREG_PRT6_PS +#define SCSI_Out__CD__SHIFT 1 +#define SCSI_Out__CD__SLW CYREG_PRT6_SLW +#define SCSI_Out__DBP__AG CYREG_PRT4_AG +#define SCSI_Out__DBP__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__DBP__BIE CYREG_PRT4_BIE +#define SCSI_Out__DBP__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__DBP__BYP CYREG_PRT4_BYP +#define SCSI_Out__DBP__CTL CYREG_PRT4_CTL +#define SCSI_Out__DBP__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__DBP__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__DBP__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__DBP__DR CYREG_PRT4_DR +#define SCSI_Out__DBP__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__DBP__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__DBP__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__DBP__MASK 0x04u +#define SCSI_Out__DBP__PC CYREG_PRT4_PC2 +#define SCSI_Out__DBP__PORT 4u +#define SCSI_Out__DBP__PRT CYREG_PRT4_PRT +#define SCSI_Out__DBP__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__DBP__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__DBP__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__DBP__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__DBP__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__DBP__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__DBP__PS CYREG_PRT4_PS +#define SCSI_Out__DBP__SHIFT 2 +#define SCSI_Out__DBP__SLW CYREG_PRT4_SLW +#define SCSI_Out__IO__AG CYREG_PRT6_AG +#define SCSI_Out__IO__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__IO__BIE CYREG_PRT6_BIE +#define SCSI_Out__IO__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__IO__BYP CYREG_PRT6_BYP +#define SCSI_Out__IO__CTL CYREG_PRT6_CTL +#define SCSI_Out__IO__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__IO__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__IO__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__IO__DR CYREG_PRT6_DR +#define SCSI_Out__IO__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__IO__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__IO__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__IO__MASK 0x08u +#define SCSI_Out__IO__PC CYREG_PRT6_PC3 +#define SCSI_Out__IO__PORT 6u +#define SCSI_Out__IO__PRT CYREG_PRT6_PRT +#define SCSI_Out__IO__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__IO__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__IO__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__IO__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__IO__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__IO__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__IO__PS CYREG_PRT6_PS +#define SCSI_Out__IO__SHIFT 3 +#define SCSI_Out__IO__SLW CYREG_PRT6_SLW +#define SCSI_Out__MSG__AG CYREG_PRT4_AG +#define SCSI_Out__MSG__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__MSG__BIE CYREG_PRT4_BIE +#define SCSI_Out__MSG__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__MSG__BYP CYREG_PRT4_BYP +#define SCSI_Out__MSG__CTL CYREG_PRT4_CTL +#define SCSI_Out__MSG__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__MSG__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__MSG__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__MSG__DR CYREG_PRT4_DR +#define SCSI_Out__MSG__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__MSG__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__MSG__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__MSG__MASK 0x80u +#define SCSI_Out__MSG__PC CYREG_PRT4_PC7 +#define SCSI_Out__MSG__PORT 4u +#define SCSI_Out__MSG__PRT CYREG_PRT4_PRT +#define SCSI_Out__MSG__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__MSG__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__MSG__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__MSG__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__MSG__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__MSG__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__MSG__PS CYREG_PRT4_PS +#define SCSI_Out__MSG__SHIFT 7 +#define SCSI_Out__MSG__SLW CYREG_PRT4_SLW +#define SCSI_Out__REQ__AG CYREG_PRT6_AG +#define SCSI_Out__REQ__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__REQ__BIE CYREG_PRT6_BIE +#define SCSI_Out__REQ__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__REQ__BYP CYREG_PRT6_BYP +#define SCSI_Out__REQ__CTL CYREG_PRT6_CTL +#define SCSI_Out__REQ__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__REQ__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__REQ__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__REQ__DR CYREG_PRT6_DR +#define SCSI_Out__REQ__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__REQ__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__REQ__MASK 0x04u +#define SCSI_Out__REQ__PC CYREG_PRT6_PC2 +#define SCSI_Out__REQ__PORT 6u +#define SCSI_Out__REQ__PRT CYREG_PRT6_PRT +#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__REQ__PS CYREG_PRT6_PS +#define SCSI_Out__REQ__SHIFT 2 +#define SCSI_Out__REQ__SLW CYREG_PRT6_SLW +#define SCSI_Out__RST__AG CYREG_PRT4_AG +#define SCSI_Out__RST__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__RST__BIE CYREG_PRT4_BIE +#define SCSI_Out__RST__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__RST__BYP CYREG_PRT4_BYP +#define SCSI_Out__RST__CTL CYREG_PRT4_CTL +#define SCSI_Out__RST__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__RST__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__RST__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__RST__DR CYREG_PRT4_DR +#define SCSI_Out__RST__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__RST__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__RST__MASK 0x40u +#define SCSI_Out__RST__PC CYREG_PRT4_PC6 +#define SCSI_Out__RST__PORT 4u +#define SCSI_Out__RST__PRT CYREG_PRT4_PRT +#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__RST__PS CYREG_PRT4_PS +#define SCSI_Out__RST__SHIFT 6 +#define SCSI_Out__RST__SLW CYREG_PRT4_SLW +#define SCSI_Out__SEL__AG CYREG_PRT6_AG +#define SCSI_Out__SEL__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__SEL__BIE CYREG_PRT6_BIE +#define SCSI_Out__SEL__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__SEL__BYP CYREG_PRT6_BYP +#define SCSI_Out__SEL__CTL CYREG_PRT6_CTL +#define SCSI_Out__SEL__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__SEL__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__SEL__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__SEL__DR CYREG_PRT6_DR +#define SCSI_Out__SEL__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__SEL__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__SEL__MASK 0x01u +#define SCSI_Out__SEL__PC CYREG_PRT6_PC0 +#define SCSI_Out__SEL__PORT 6u +#define SCSI_Out__SEL__PRT CYREG_PRT6_PRT +#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__SEL__PS CYREG_PRT6_PS +#define SCSI_Out__SEL__SHIFT 0 +#define SCSI_Out__SEL__SLW CYREG_PRT6_SLW + +/* SCSI_ID */ +#define SCSI_ID__0__MASK 0x80u +#define SCSI_ID__0__PC CYREG_PRT5_PC7 +#define SCSI_ID__0__PORT 5u +#define SCSI_ID__0__SHIFT 7 +#define SCSI_ID__1__MASK 0x40u +#define SCSI_ID__1__PC CYREG_PRT5_PC6 +#define SCSI_ID__1__PORT 5u +#define SCSI_ID__1__SHIFT 6 +#define SCSI_ID__2__MASK 0x20u +#define SCSI_ID__2__PC CYREG_PRT5_PC5 +#define SCSI_ID__2__PORT 5u +#define SCSI_ID__2__SHIFT 5 +#define SCSI_ID__AG CYREG_PRT5_AG +#define SCSI_ID__AMUX CYREG_PRT5_AMUX +#define SCSI_ID__BIE CYREG_PRT5_BIE +#define SCSI_ID__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_ID__BYP CYREG_PRT5_BYP +#define SCSI_ID__CTL CYREG_PRT5_CTL +#define SCSI_ID__DM0 CYREG_PRT5_DM0 +#define SCSI_ID__DM1 CYREG_PRT5_DM1 +#define SCSI_ID__DM2 CYREG_PRT5_DM2 +#define SCSI_ID__DR CYREG_PRT5_DR +#define SCSI_ID__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_ID__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_ID__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_ID__PORT 5u +#define SCSI_ID__PRT CYREG_PRT5_PRT +#define SCSI_ID__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_ID__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_ID__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_ID__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_ID__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_ID__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_ID__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_ID__PS CYREG_PRT5_PS +#define SCSI_ID__SLW CYREG_PRT5_SLW + +/* SCSI_In */ +#define SCSI_In__0__AG CYREG_PRT12_AG +#define SCSI_In__0__BIE CYREG_PRT12_BIE +#define SCSI_In__0__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_In__0__BYP CYREG_PRT12_BYP +#define SCSI_In__0__DM0 CYREG_PRT12_DM0 +#define SCSI_In__0__DM1 CYREG_PRT12_DM1 +#define SCSI_In__0__DM2 CYREG_PRT12_DM2 +#define SCSI_In__0__DR CYREG_PRT12_DR +#define SCSI_In__0__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_In__0__MASK 0x10u +#define SCSI_In__0__PC CYREG_PRT12_PC4 +#define SCSI_In__0__PORT 12u +#define SCSI_In__0__PRT CYREG_PRT12_PRT +#define SCSI_In__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_In__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_In__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_In__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_In__0__PS CYREG_PRT12_PS +#define SCSI_In__0__SHIFT 4 +#define SCSI_In__0__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_In__0__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_In__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_In__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_In__0__SLW CYREG_PRT12_SLW +#define SCSI_In__1__AG CYREG_PRT12_AG +#define SCSI_In__1__BIE CYREG_PRT12_BIE +#define SCSI_In__1__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_In__1__BYP CYREG_PRT12_BYP +#define SCSI_In__1__DM0 CYREG_PRT12_DM0 +#define SCSI_In__1__DM1 CYREG_PRT12_DM1 +#define SCSI_In__1__DM2 CYREG_PRT12_DM2 +#define SCSI_In__1__DR CYREG_PRT12_DR +#define SCSI_In__1__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_In__1__MASK 0x20u +#define SCSI_In__1__PC CYREG_PRT12_PC5 +#define SCSI_In__1__PORT 12u +#define SCSI_In__1__PRT CYREG_PRT12_PRT +#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_In__1__PS CYREG_PRT12_PS +#define SCSI_In__1__SHIFT 5 +#define SCSI_In__1__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_In__1__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_In__1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_In__1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_In__1__SLW CYREG_PRT12_SLW +#define SCSI_In__2__AG CYREG_PRT6_AG +#define SCSI_In__2__AMUX CYREG_PRT6_AMUX +#define SCSI_In__2__BIE CYREG_PRT6_BIE +#define SCSI_In__2__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In__2__BYP CYREG_PRT6_BYP +#define SCSI_In__2__CTL CYREG_PRT6_CTL +#define SCSI_In__2__DM0 CYREG_PRT6_DM0 +#define SCSI_In__2__DM1 CYREG_PRT6_DM1 +#define SCSI_In__2__DM2 CYREG_PRT6_DM2 +#define SCSI_In__2__DR CYREG_PRT6_DR +#define SCSI_In__2__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In__2__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__2__MASK 0x10u +#define SCSI_In__2__PC CYREG_PRT6_PC4 +#define SCSI_In__2__PORT 6u +#define SCSI_In__2__PRT CYREG_PRT6_PRT +#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In__2__PS CYREG_PRT6_PS +#define SCSI_In__2__SHIFT 4 +#define SCSI_In__2__SLW CYREG_PRT6_SLW +#define SCSI_In__3__AG CYREG_PRT6_AG +#define SCSI_In__3__AMUX CYREG_PRT6_AMUX +#define SCSI_In__3__BIE CYREG_PRT6_BIE +#define SCSI_In__3__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In__3__BYP CYREG_PRT6_BYP +#define SCSI_In__3__CTL CYREG_PRT6_CTL +#define SCSI_In__3__DM0 CYREG_PRT6_DM0 +#define SCSI_In__3__DM1 CYREG_PRT6_DM1 +#define SCSI_In__3__DM2 CYREG_PRT6_DM2 +#define SCSI_In__3__DR CYREG_PRT6_DR +#define SCSI_In__3__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In__3__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__3__MASK 0x20u +#define SCSI_In__3__PC CYREG_PRT6_PC5 +#define SCSI_In__3__PORT 6u +#define SCSI_In__3__PRT CYREG_PRT6_PRT +#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In__3__PS CYREG_PRT6_PS +#define SCSI_In__3__SHIFT 5 +#define SCSI_In__3__SLW CYREG_PRT6_SLW +#define SCSI_In__4__AG CYREG_PRT6_AG +#define SCSI_In__4__AMUX CYREG_PRT6_AMUX +#define SCSI_In__4__BIE CYREG_PRT6_BIE +#define SCSI_In__4__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In__4__BYP CYREG_PRT6_BYP +#define SCSI_In__4__CTL CYREG_PRT6_CTL +#define SCSI_In__4__DM0 CYREG_PRT6_DM0 +#define SCSI_In__4__DM1 CYREG_PRT6_DM1 +#define SCSI_In__4__DM2 CYREG_PRT6_DM2 +#define SCSI_In__4__DR CYREG_PRT6_DR +#define SCSI_In__4__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In__4__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__4__MASK 0x40u +#define SCSI_In__4__PC CYREG_PRT6_PC6 +#define SCSI_In__4__PORT 6u +#define SCSI_In__4__PRT CYREG_PRT6_PRT +#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In__4__PS CYREG_PRT6_PS +#define SCSI_In__4__SHIFT 6 +#define SCSI_In__4__SLW CYREG_PRT6_SLW +#define SCSI_In__5__AG CYREG_PRT6_AG +#define SCSI_In__5__AMUX CYREG_PRT6_AMUX +#define SCSI_In__5__BIE CYREG_PRT6_BIE +#define SCSI_In__5__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In__5__BYP CYREG_PRT6_BYP +#define SCSI_In__5__CTL CYREG_PRT6_CTL +#define SCSI_In__5__DM0 CYREG_PRT6_DM0 +#define SCSI_In__5__DM1 CYREG_PRT6_DM1 +#define SCSI_In__5__DM2 CYREG_PRT6_DM2 +#define SCSI_In__5__DR CYREG_PRT6_DR +#define SCSI_In__5__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In__5__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In__5__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__5__MASK 0x80u +#define SCSI_In__5__PC CYREG_PRT6_PC7 +#define SCSI_In__5__PORT 6u +#define SCSI_In__5__PRT CYREG_PRT6_PRT +#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In__5__PS CYREG_PRT6_PS +#define SCSI_In__5__SHIFT 7 +#define SCSI_In__5__SLW CYREG_PRT6_SLW +#define SCSI_In__6__AG CYREG_PRT5_AG +#define SCSI_In__6__AMUX CYREG_PRT5_AMUX +#define SCSI_In__6__BIE CYREG_PRT5_BIE +#define SCSI_In__6__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In__6__BYP CYREG_PRT5_BYP +#define SCSI_In__6__CTL CYREG_PRT5_CTL +#define SCSI_In__6__DM0 CYREG_PRT5_DM0 +#define SCSI_In__6__DM1 CYREG_PRT5_DM1 +#define SCSI_In__6__DM2 CYREG_PRT5_DM2 +#define SCSI_In__6__DR CYREG_PRT5_DR +#define SCSI_In__6__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In__6__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In__6__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In__6__MASK 0x01u +#define SCSI_In__6__PC CYREG_PRT5_PC0 +#define SCSI_In__6__PORT 5u +#define SCSI_In__6__PRT CYREG_PRT5_PRT +#define SCSI_In__6__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In__6__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In__6__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In__6__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In__6__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In__6__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In__6__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In__6__PS CYREG_PRT5_PS +#define SCSI_In__6__SHIFT 0 +#define SCSI_In__6__SLW CYREG_PRT5_SLW +#define SCSI_In__7__AG CYREG_PRT5_AG +#define SCSI_In__7__AMUX CYREG_PRT5_AMUX +#define SCSI_In__7__BIE CYREG_PRT5_BIE +#define SCSI_In__7__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In__7__BYP CYREG_PRT5_BYP +#define SCSI_In__7__CTL CYREG_PRT5_CTL +#define SCSI_In__7__DM0 CYREG_PRT5_DM0 +#define SCSI_In__7__DM1 CYREG_PRT5_DM1 +#define SCSI_In__7__DM2 CYREG_PRT5_DM2 +#define SCSI_In__7__DR CYREG_PRT5_DR +#define SCSI_In__7__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In__7__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In__7__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In__7__MASK 0x02u +#define SCSI_In__7__PC CYREG_PRT5_PC1 +#define SCSI_In__7__PORT 5u +#define SCSI_In__7__PRT CYREG_PRT5_PRT +#define SCSI_In__7__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In__7__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In__7__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In__7__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In__7__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In__7__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In__7__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In__7__PS CYREG_PRT5_PS +#define SCSI_In__7__SHIFT 1 +#define SCSI_In__7__SLW CYREG_PRT5_SLW +#define SCSI_In__8__AG CYREG_PRT5_AG +#define SCSI_In__8__AMUX CYREG_PRT5_AMUX +#define SCSI_In__8__BIE CYREG_PRT5_BIE +#define SCSI_In__8__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In__8__BYP CYREG_PRT5_BYP +#define SCSI_In__8__CTL CYREG_PRT5_CTL +#define SCSI_In__8__DM0 CYREG_PRT5_DM0 +#define SCSI_In__8__DM1 CYREG_PRT5_DM1 +#define SCSI_In__8__DM2 CYREG_PRT5_DM2 +#define SCSI_In__8__DR CYREG_PRT5_DR +#define SCSI_In__8__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In__8__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In__8__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In__8__MASK 0x04u +#define SCSI_In__8__PC CYREG_PRT5_PC2 +#define SCSI_In__8__PORT 5u +#define SCSI_In__8__PRT CYREG_PRT5_PRT +#define SCSI_In__8__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In__8__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In__8__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In__8__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In__8__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In__8__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In__8__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In__8__PS CYREG_PRT5_PS +#define SCSI_In__8__SHIFT 2 +#define SCSI_In__8__SLW CYREG_PRT5_SLW +#define SCSI_In__9__AG CYREG_PRT5_AG +#define SCSI_In__9__AMUX CYREG_PRT5_AMUX +#define SCSI_In__9__BIE CYREG_PRT5_BIE +#define SCSI_In__9__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In__9__BYP CYREG_PRT5_BYP +#define SCSI_In__9__CTL CYREG_PRT5_CTL +#define SCSI_In__9__DM0 CYREG_PRT5_DM0 +#define SCSI_In__9__DM1 CYREG_PRT5_DM1 +#define SCSI_In__9__DM2 CYREG_PRT5_DM2 +#define SCSI_In__9__DR CYREG_PRT5_DR +#define SCSI_In__9__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In__9__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In__9__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In__9__MASK 0x08u +#define SCSI_In__9__PC CYREG_PRT5_PC3 +#define SCSI_In__9__PORT 5u +#define SCSI_In__9__PRT CYREG_PRT5_PRT +#define SCSI_In__9__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In__9__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In__9__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In__9__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In__9__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In__9__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In__9__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In__9__PS CYREG_PRT5_PS +#define SCSI_In__9__SHIFT 3 +#define SCSI_In__9__SLW CYREG_PRT5_SLW +#define SCSI_In__ACK__AG CYREG_PRT6_AG +#define SCSI_In__ACK__AMUX CYREG_PRT6_AMUX +#define SCSI_In__ACK__BIE CYREG_PRT6_BIE +#define SCSI_In__ACK__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In__ACK__BYP CYREG_PRT6_BYP +#define SCSI_In__ACK__CTL CYREG_PRT6_CTL +#define SCSI_In__ACK__DM0 CYREG_PRT6_DM0 +#define SCSI_In__ACK__DM1 CYREG_PRT6_DM1 +#define SCSI_In__ACK__DM2 CYREG_PRT6_DM2 +#define SCSI_In__ACK__DR CYREG_PRT6_DR +#define SCSI_In__ACK__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In__ACK__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__ACK__MASK 0x20u +#define SCSI_In__ACK__PC CYREG_PRT6_PC5 +#define SCSI_In__ACK__PORT 6u +#define SCSI_In__ACK__PRT CYREG_PRT6_PRT +#define SCSI_In__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In__ACK__PS CYREG_PRT6_PS +#define SCSI_In__ACK__SHIFT 5 +#define SCSI_In__ACK__SLW CYREG_PRT6_SLW +#define SCSI_In__ATN__AG CYREG_PRT12_AG +#define SCSI_In__ATN__BIE CYREG_PRT12_BIE +#define SCSI_In__ATN__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_In__ATN__BYP CYREG_PRT12_BYP +#define SCSI_In__ATN__DM0 CYREG_PRT12_DM0 +#define SCSI_In__ATN__DM1 CYREG_PRT12_DM1 +#define SCSI_In__ATN__DM2 CYREG_PRT12_DM2 +#define SCSI_In__ATN__DR CYREG_PRT12_DR +#define SCSI_In__ATN__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_In__ATN__MASK 0x20u +#define SCSI_In__ATN__PC CYREG_PRT12_PC5 +#define SCSI_In__ATN__PORT 12u +#define SCSI_In__ATN__PRT CYREG_PRT12_PRT +#define SCSI_In__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_In__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_In__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_In__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_In__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_In__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_In__ATN__PS CYREG_PRT12_PS +#define SCSI_In__ATN__SHIFT 5 +#define SCSI_In__ATN__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_In__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_In__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_In__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_In__ATN__SLW CYREG_PRT12_SLW +#define SCSI_In__BSY__AG CYREG_PRT6_AG +#define SCSI_In__BSY__AMUX CYREG_PRT6_AMUX +#define SCSI_In__BSY__BIE CYREG_PRT6_BIE +#define SCSI_In__BSY__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In__BSY__BYP CYREG_PRT6_BYP +#define SCSI_In__BSY__CTL CYREG_PRT6_CTL +#define SCSI_In__BSY__DM0 CYREG_PRT6_DM0 +#define SCSI_In__BSY__DM1 CYREG_PRT6_DM1 +#define SCSI_In__BSY__DM2 CYREG_PRT6_DM2 +#define SCSI_In__BSY__DR CYREG_PRT6_DR +#define SCSI_In__BSY__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In__BSY__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__BSY__MASK 0x10u +#define SCSI_In__BSY__PC CYREG_PRT6_PC4 +#define SCSI_In__BSY__PORT 6u +#define SCSI_In__BSY__PRT CYREG_PRT6_PRT +#define SCSI_In__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In__BSY__PS CYREG_PRT6_PS +#define SCSI_In__BSY__SHIFT 4 +#define SCSI_In__BSY__SLW CYREG_PRT6_SLW +#define SCSI_In__CD__AG CYREG_PRT5_AG +#define SCSI_In__CD__AMUX CYREG_PRT5_AMUX +#define SCSI_In__CD__BIE CYREG_PRT5_BIE +#define SCSI_In__CD__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In__CD__BYP CYREG_PRT5_BYP +#define SCSI_In__CD__CTL CYREG_PRT5_CTL +#define SCSI_In__CD__DM0 CYREG_PRT5_DM0 +#define SCSI_In__CD__DM1 CYREG_PRT5_DM1 +#define SCSI_In__CD__DM2 CYREG_PRT5_DM2 +#define SCSI_In__CD__DR CYREG_PRT5_DR +#define SCSI_In__CD__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In__CD__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In__CD__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In__CD__MASK 0x02u +#define SCSI_In__CD__PC CYREG_PRT5_PC1 +#define SCSI_In__CD__PORT 5u +#define SCSI_In__CD__PRT CYREG_PRT5_PRT +#define SCSI_In__CD__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In__CD__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In__CD__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In__CD__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In__CD__PS CYREG_PRT5_PS +#define SCSI_In__CD__SHIFT 1 +#define SCSI_In__CD__SLW CYREG_PRT5_SLW +#define SCSI_In__DBP__AG CYREG_PRT12_AG +#define SCSI_In__DBP__BIE CYREG_PRT12_BIE +#define SCSI_In__DBP__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_In__DBP__BYP CYREG_PRT12_BYP +#define SCSI_In__DBP__DM0 CYREG_PRT12_DM0 +#define SCSI_In__DBP__DM1 CYREG_PRT12_DM1 +#define SCSI_In__DBP__DM2 CYREG_PRT12_DM2 +#define SCSI_In__DBP__DR CYREG_PRT12_DR +#define SCSI_In__DBP__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_In__DBP__MASK 0x10u +#define SCSI_In__DBP__PC CYREG_PRT12_PC4 +#define SCSI_In__DBP__PORT 12u +#define SCSI_In__DBP__PRT CYREG_PRT12_PRT +#define SCSI_In__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_In__DBP__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_In__DBP__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_In__DBP__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_In__DBP__PS CYREG_PRT12_PS +#define SCSI_In__DBP__SHIFT 4 +#define SCSI_In__DBP__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_In__DBP__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_In__DBP__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_In__DBP__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_In__DBP__SLW CYREG_PRT12_SLW +#define SCSI_In__IO__AG CYREG_PRT5_AG +#define SCSI_In__IO__AMUX CYREG_PRT5_AMUX +#define SCSI_In__IO__BIE CYREG_PRT5_BIE +#define SCSI_In__IO__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In__IO__BYP CYREG_PRT5_BYP +#define SCSI_In__IO__CTL CYREG_PRT5_CTL +#define SCSI_In__IO__DM0 CYREG_PRT5_DM0 +#define SCSI_In__IO__DM1 CYREG_PRT5_DM1 +#define SCSI_In__IO__DM2 CYREG_PRT5_DM2 +#define SCSI_In__IO__DR CYREG_PRT5_DR +#define SCSI_In__IO__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In__IO__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In__IO__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In__IO__MASK 0x08u +#define SCSI_In__IO__PC CYREG_PRT5_PC3 +#define SCSI_In__IO__PORT 5u +#define SCSI_In__IO__PRT CYREG_PRT5_PRT +#define SCSI_In__IO__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In__IO__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In__IO__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In__IO__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In__IO__PS CYREG_PRT5_PS +#define SCSI_In__IO__SHIFT 3 +#define SCSI_In__IO__SLW CYREG_PRT5_SLW +#define SCSI_In__MSG__AG CYREG_PRT6_AG +#define SCSI_In__MSG__AMUX CYREG_PRT6_AMUX +#define SCSI_In__MSG__BIE CYREG_PRT6_BIE +#define SCSI_In__MSG__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In__MSG__BYP CYREG_PRT6_BYP +#define SCSI_In__MSG__CTL CYREG_PRT6_CTL +#define SCSI_In__MSG__DM0 CYREG_PRT6_DM0 +#define SCSI_In__MSG__DM1 CYREG_PRT6_DM1 +#define SCSI_In__MSG__DM2 CYREG_PRT6_DM2 +#define SCSI_In__MSG__DR CYREG_PRT6_DR +#define SCSI_In__MSG__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In__MSG__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In__MSG__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__MSG__MASK 0x80u +#define SCSI_In__MSG__PC CYREG_PRT6_PC7 +#define SCSI_In__MSG__PORT 6u +#define SCSI_In__MSG__PRT CYREG_PRT6_PRT +#define SCSI_In__MSG__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In__MSG__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In__MSG__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In__MSG__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In__MSG__PS CYREG_PRT6_PS +#define SCSI_In__MSG__SHIFT 7 +#define SCSI_In__MSG__SLW CYREG_PRT6_SLW +#define SCSI_In__REQ__AG CYREG_PRT5_AG +#define SCSI_In__REQ__AMUX CYREG_PRT5_AMUX +#define SCSI_In__REQ__BIE CYREG_PRT5_BIE +#define SCSI_In__REQ__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In__REQ__BYP CYREG_PRT5_BYP +#define SCSI_In__REQ__CTL CYREG_PRT5_CTL +#define SCSI_In__REQ__DM0 CYREG_PRT5_DM0 +#define SCSI_In__REQ__DM1 CYREG_PRT5_DM1 +#define SCSI_In__REQ__DM2 CYREG_PRT5_DM2 +#define SCSI_In__REQ__DR CYREG_PRT5_DR +#define SCSI_In__REQ__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In__REQ__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In__REQ__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In__REQ__MASK 0x04u +#define SCSI_In__REQ__PC CYREG_PRT5_PC2 +#define SCSI_In__REQ__PORT 5u +#define SCSI_In__REQ__PRT CYREG_PRT5_PRT +#define SCSI_In__REQ__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In__REQ__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In__REQ__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In__REQ__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In__REQ__PS CYREG_PRT5_PS +#define SCSI_In__REQ__SHIFT 2 +#define SCSI_In__REQ__SLW CYREG_PRT5_SLW +#define SCSI_In__RST__AG CYREG_PRT6_AG +#define SCSI_In__RST__AMUX CYREG_PRT6_AMUX +#define SCSI_In__RST__BIE CYREG_PRT6_BIE +#define SCSI_In__RST__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In__RST__BYP CYREG_PRT6_BYP +#define SCSI_In__RST__CTL CYREG_PRT6_CTL +#define SCSI_In__RST__DM0 CYREG_PRT6_DM0 +#define SCSI_In__RST__DM1 CYREG_PRT6_DM1 +#define SCSI_In__RST__DM2 CYREG_PRT6_DM2 +#define SCSI_In__RST__DR CYREG_PRT6_DR +#define SCSI_In__RST__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In__RST__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__RST__MASK 0x40u +#define SCSI_In__RST__PC CYREG_PRT6_PC6 +#define SCSI_In__RST__PORT 6u +#define SCSI_In__RST__PRT CYREG_PRT6_PRT +#define SCSI_In__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In__RST__PS CYREG_PRT6_PS +#define SCSI_In__RST__SHIFT 6 +#define SCSI_In__RST__SLW CYREG_PRT6_SLW +#define SCSI_In__SEL__AG CYREG_PRT5_AG +#define SCSI_In__SEL__AMUX CYREG_PRT5_AMUX +#define SCSI_In__SEL__BIE CYREG_PRT5_BIE +#define SCSI_In__SEL__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In__SEL__BYP CYREG_PRT5_BYP +#define SCSI_In__SEL__CTL CYREG_PRT5_CTL +#define SCSI_In__SEL__DM0 CYREG_PRT5_DM0 +#define SCSI_In__SEL__DM1 CYREG_PRT5_DM1 +#define SCSI_In__SEL__DM2 CYREG_PRT5_DM2 +#define SCSI_In__SEL__DR CYREG_PRT5_DR +#define SCSI_In__SEL__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In__SEL__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In__SEL__MASK 0x01u +#define SCSI_In__SEL__PC CYREG_PRT5_PC0 +#define SCSI_In__SEL__PORT 5u +#define SCSI_In__SEL__PRT CYREG_PRT5_PRT +#define SCSI_In__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In__SEL__PS CYREG_PRT5_PS +#define SCSI_In__SEL__SHIFT 0 +#define SCSI_In__SEL__SLW CYREG_PRT5_SLW + +/* SD_DAT1 */ +#define SD_DAT1__0__MASK 0x20u +#define SD_DAT1__0__PC CYREG_PRT3_PC5 +#define SD_DAT1__0__PORT 3u +#define SD_DAT1__0__SHIFT 5 +#define SD_DAT1__AG CYREG_PRT3_AG +#define SD_DAT1__AMUX CYREG_PRT3_AMUX +#define SD_DAT1__BIE CYREG_PRT3_BIE +#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_DAT1__BYP CYREG_PRT3_BYP +#define SD_DAT1__CTL CYREG_PRT3_CTL +#define SD_DAT1__DM0 CYREG_PRT3_DM0 +#define SD_DAT1__DM1 CYREG_PRT3_DM1 +#define SD_DAT1__DM2 CYREG_PRT3_DM2 +#define SD_DAT1__DR CYREG_PRT3_DR +#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS +#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN +#define SD_DAT1__MASK 0x20u +#define SD_DAT1__PORT 3u +#define SD_DAT1__PRT CYREG_PRT3_PRT +#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_DAT1__PS CYREG_PRT3_PS +#define SD_DAT1__SHIFT 5 +#define SD_DAT1__SLW CYREG_PRT3_SLW + +/* SD_DAT2 */ +#define SD_DAT2__0__MASK 0x01u +#define SD_DAT2__0__PC CYREG_PRT3_PC0 +#define SD_DAT2__0__PORT 3u +#define SD_DAT2__0__SHIFT 0 +#define SD_DAT2__AG CYREG_PRT3_AG +#define SD_DAT2__AMUX CYREG_PRT3_AMUX +#define SD_DAT2__BIE CYREG_PRT3_BIE +#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_DAT2__BYP CYREG_PRT3_BYP +#define SD_DAT2__CTL CYREG_PRT3_CTL +#define SD_DAT2__DM0 CYREG_PRT3_DM0 +#define SD_DAT2__DM1 CYREG_PRT3_DM1 +#define SD_DAT2__DM2 CYREG_PRT3_DM2 +#define SD_DAT2__DR CYREG_PRT3_DR +#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS +#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN +#define SD_DAT2__MASK 0x01u +#define SD_DAT2__PORT 3u +#define SD_DAT2__PRT CYREG_PRT3_PRT +#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_DAT2__PS CYREG_PRT3_PS +#define SD_DAT2__SHIFT 0 +#define SD_DAT2__SLW CYREG_PRT3_SLW + +/* SD_MISO */ +#define SD_MISO__0__MASK 0x10u +#define SD_MISO__0__PC CYREG_PRT3_PC4 +#define SD_MISO__0__PORT 3u +#define SD_MISO__0__SHIFT 4 +#define SD_MISO__AG CYREG_PRT3_AG +#define SD_MISO__AMUX CYREG_PRT3_AMUX +#define SD_MISO__BIE CYREG_PRT3_BIE +#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MISO__BYP CYREG_PRT3_BYP +#define SD_MISO__CTL CYREG_PRT3_CTL +#define SD_MISO__DM0 CYREG_PRT3_DM0 +#define SD_MISO__DM1 CYREG_PRT3_DM1 +#define SD_MISO__DM2 CYREG_PRT3_DM2 +#define SD_MISO__DR CYREG_PRT3_DR +#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MISO__MASK 0x10u +#define SD_MISO__PORT 3u +#define SD_MISO__PRT CYREG_PRT3_PRT +#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MISO__PS CYREG_PRT3_PS +#define SD_MISO__SHIFT 4 +#define SD_MISO__SLW CYREG_PRT3_SLW + +/* SD_MOSI */ +#define SD_MOSI__0__MASK 0x04u +#define SD_MOSI__0__PC CYREG_PRT3_PC2 +#define SD_MOSI__0__PORT 3u +#define SD_MOSI__0__SHIFT 2 +#define SD_MOSI__AG CYREG_PRT3_AG +#define SD_MOSI__AMUX CYREG_PRT3_AMUX +#define SD_MOSI__BIE CYREG_PRT3_BIE +#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MOSI__BYP CYREG_PRT3_BYP +#define SD_MOSI__CTL CYREG_PRT3_CTL +#define SD_MOSI__DM0 CYREG_PRT3_DM0 +#define SD_MOSI__DM1 CYREG_PRT3_DM1 +#define SD_MOSI__DM2 CYREG_PRT3_DM2 +#define SD_MOSI__DR CYREG_PRT3_DR +#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MOSI__MASK 0x04u +#define SD_MOSI__PORT 3u +#define SD_MOSI__PRT CYREG_PRT3_PRT +#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MOSI__PS CYREG_PRT3_PS +#define SD_MOSI__SHIFT 2 +#define SD_MOSI__SLW CYREG_PRT3_SLW + +/* SD_SCK */ +#define SD_SCK__0__MASK 0x08u +#define SD_SCK__0__PC CYREG_PRT3_PC3 +#define SD_SCK__0__PORT 3u +#define SD_SCK__0__SHIFT 3 +#define SD_SCK__AG CYREG_PRT3_AG +#define SD_SCK__AMUX CYREG_PRT3_AMUX +#define SD_SCK__BIE CYREG_PRT3_BIE +#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_SCK__BYP CYREG_PRT3_BYP +#define SD_SCK__CTL CYREG_PRT3_CTL +#define SD_SCK__DM0 CYREG_PRT3_DM0 +#define SD_SCK__DM1 CYREG_PRT3_DM1 +#define SD_SCK__DM2 CYREG_PRT3_DM2 +#define SD_SCK__DR CYREG_PRT3_DR +#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS +#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN +#define SD_SCK__MASK 0x08u +#define SD_SCK__PORT 3u +#define SD_SCK__PRT CYREG_PRT3_PRT +#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_SCK__PS CYREG_PRT3_PS +#define SD_SCK__SHIFT 3 +#define SD_SCK__SLW CYREG_PRT3_SLW + +/* SD_CD */ +#define SD_CD__0__MASK 0x40u +#define SD_CD__0__PC CYREG_PRT3_PC6 +#define SD_CD__0__PORT 3u +#define SD_CD__0__SHIFT 6 +#define SD_CD__AG CYREG_PRT3_AG +#define SD_CD__AMUX CYREG_PRT3_AMUX +#define SD_CD__BIE CYREG_PRT3_BIE +#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CD__BYP CYREG_PRT3_BYP +#define SD_CD__CTL CYREG_PRT3_CTL +#define SD_CD__DM0 CYREG_PRT3_DM0 +#define SD_CD__DM1 CYREG_PRT3_DM1 +#define SD_CD__DM2 CYREG_PRT3_DM2 +#define SD_CD__DR CYREG_PRT3_DR +#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CD__MASK 0x40u +#define SD_CD__PORT 3u +#define SD_CD__PRT CYREG_PRT3_PRT +#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CD__PS CYREG_PRT3_PS +#define SD_CD__SHIFT 6 +#define SD_CD__SLW CYREG_PRT3_SLW + +/* SD_CS */ +#define SD_CS__0__MASK 0x02u +#define SD_CS__0__PC CYREG_PRT3_PC1 +#define SD_CS__0__PORT 3u +#define SD_CS__0__SHIFT 1 +#define SD_CS__AG CYREG_PRT3_AG +#define SD_CS__AMUX CYREG_PRT3_AMUX +#define SD_CS__BIE CYREG_PRT3_BIE +#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CS__BYP CYREG_PRT3_BYP +#define SD_CS__CTL CYREG_PRT3_CTL +#define SD_CS__DM0 CYREG_PRT3_DM0 +#define SD_CS__DM1 CYREG_PRT3_DM1 +#define SD_CS__DM2 CYREG_PRT3_DM2 +#define SD_CS__DR CYREG_PRT3_DR +#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CS__MASK 0x02u +#define SD_CS__PORT 3u +#define SD_CS__PRT CYREG_PRT3_PRT +#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CS__PS CYREG_PRT3_PS +#define SD_CS__SHIFT 1 +#define SD_CS__SLW CYREG_PRT3_SLW + +/* SD_WP */ +#define SD_WP__0__MASK 0x80u +#define SD_WP__0__PC CYREG_PRT3_PC7 +#define SD_WP__0__PORT 3u +#define SD_WP__0__SHIFT 7 +#define SD_WP__AG CYREG_PRT3_AG +#define SD_WP__AMUX CYREG_PRT3_AMUX +#define SD_WP__BIE CYREG_PRT3_BIE +#define SD_WP__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_WP__BYP CYREG_PRT3_BYP +#define SD_WP__CTL CYREG_PRT3_CTL +#define SD_WP__DM0 CYREG_PRT3_DM0 +#define SD_WP__DM1 CYREG_PRT3_DM1 +#define SD_WP__DM2 CYREG_PRT3_DM2 +#define SD_WP__DR CYREG_PRT3_DR +#define SD_WP__INP_DIS CYREG_PRT3_INP_DIS +#define SD_WP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_WP__LCD_EN CYREG_PRT3_LCD_EN +#define SD_WP__MASK 0x80u +#define SD_WP__PORT 3u +#define SD_WP__PRT CYREG_PRT3_PRT +#define SD_WP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_WP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_WP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_WP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_WP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_WP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_WP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_WP__PS CYREG_PRT3_PS +#define SD_WP__SHIFT 7 +#define SD_WP__SLW CYREG_PRT3_SLW + +/* LED1 */ +#define LED1__0__MASK 0x08u +#define LED1__0__PC CYREG_PRT12_PC3 +#define LED1__0__PORT 12u +#define LED1__0__SHIFT 3 +#define LED1__AG CYREG_PRT12_AG +#define LED1__BIE CYREG_PRT12_BIE +#define LED1__BIT_MASK CYREG_PRT12_BIT_MASK +#define LED1__BYP CYREG_PRT12_BYP +#define LED1__DM0 CYREG_PRT12_DM0 +#define LED1__DM1 CYREG_PRT12_DM1 +#define LED1__DM2 CYREG_PRT12_DM2 +#define LED1__DR CYREG_PRT12_DR +#define LED1__INP_DIS CYREG_PRT12_INP_DIS +#define LED1__MASK 0x08u +#define LED1__PORT 12u +#define LED1__PRT CYREG_PRT12_PRT +#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define LED1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define LED1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define LED1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define LED1__PS CYREG_PRT12_PS +#define LED1__SHIFT 3 +#define LED1__SIO_CFG CYREG_PRT12_SIO_CFG +#define LED1__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define LED1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define LED1__SLW CYREG_PRT12_SLW + +/* Miscellaneous */ +/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ +#define CYDEV_DEBUGGING_DPS_SWD_SWV 6 +#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0 +#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0 +#define CYDEV_CONFIG_FASTBOOT_ENABLED 1 +#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u +#define CYDEV_CHIP_MEMBER_5B 4u +#define CYDEV_CHIP_FAMILY_PSOC5 3u +#define CYDEV_CHIP_DIE_PSOC5LP 4u +#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP +#define BCLK__BUS_CLK__HZ 64000000U +#define BCLK__BUS_CLK__KHZ 64000U +#define BCLK__BUS_CLK__MHZ 64U +#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT +#define CYDEV_CHIP_DIE_LEOPARD 1u +#define CYDEV_CHIP_DIE_PANTHER 3u +#define CYDEV_CHIP_DIE_PSOC4A 2u +#define CYDEV_CHIP_DIE_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_PSOC3 1u +#define CYDEV_CHIP_FAMILY_PSOC4 2u +#define CYDEV_CHIP_FAMILY_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 +#define CYDEV_CHIP_JTAG_ID 0x2E12F069u +#define CYDEV_CHIP_MEMBER_3A 1u +#define CYDEV_CHIP_MEMBER_4A 2u +#define CYDEV_CHIP_MEMBER_5A 3u +#define CYDEV_CHIP_MEMBER_UNKNOWN 0u +#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B +#define CYDEV_CHIP_REVISION_3A_ES1 0u +#define CYDEV_CHIP_REVISION_3A_ES2 1u +#define CYDEV_CHIP_REVISION_3A_ES3 3u +#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u +#define CYDEV_CHIP_REVISION_4A_ES0 17u +#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_5A_ES0 0u +#define CYDEV_CHIP_REVISION_5A_ES1 1u +#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u +#define CYDEV_CHIP_REVISION_5B_ES0 0u +#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION +#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION +#define CYDEV_CHIP_REV_LEOPARD_ES1 0u +#define CYDEV_CHIP_REV_LEOPARD_ES2 1u +#define CYDEV_CHIP_REV_LEOPARD_ES3 3u +#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u +#define CYDEV_CHIP_REV_PANTHER_ES0 0u +#define CYDEV_CHIP_REV_PANTHER_ES1 1u +#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u +#define CYDEV_CHIP_REV_PSOC4A_ES0 17u +#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u +#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u +#define CYDEV_CONFIGURATION_COMPRESSED 1 +#define CYDEV_CONFIGURATION_DMA 0 +#define CYDEV_CONFIGURATION_ECC 1 +#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED +#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED +#define CYDEV_CONFIGURATION_MODE_DMA 2 +#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1 +#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn +#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1 +#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2 +#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV +#define CYDEV_DEBUGGING_DPS_Disable 3 +#define CYDEV_DEBUGGING_DPS_JTAG_4 1 +#define CYDEV_DEBUGGING_DPS_JTAG_5 0 +#define CYDEV_DEBUGGING_DPS_SWD 2 +#define CYDEV_DEBUGGING_ENABLE 1 +#define CYDEV_DEBUGGING_REQXRES 1 +#define CYDEV_DEBUGGING_XRES 0 +#define CYDEV_DEBUG_ENABLE_MASK 0x20u +#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG +#define CYDEV_DMA_CHANNELS_AVAILABLE 24u +#define CYDEV_ECC_ENABLE 0 +#define CYDEV_HEAP_SIZE 0x1000 +#define CYDEV_INSTRUCT_CACHE_ENABLED 1 +#define CYDEV_INTR_RISING 0x00000003u +#define CYDEV_PROJ_TYPE 0 +#define CYDEV_PROJ_TYPE_BOOTLOADER 1 +#define CYDEV_PROJ_TYPE_LOADABLE 2 +#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3 +#define CYDEV_PROJ_TYPE_STANDARD 0 +#define CYDEV_PROTECTION_ENABLE 0 +#define CYDEV_STACK_SIZE 0x4000 +#define CYDEV_USE_BUNDLED_CMSIS 1 +#define CYDEV_VARIABLE_VDDA 0 +#define CYDEV_VDDA 5.0 +#define CYDEV_VDDA_MV 5000 +#define CYDEV_VDDD 5.0 +#define CYDEV_VDDD_MV 5000 +#define CYDEV_VDDIO0 5.0 +#define CYDEV_VDDIO0_MV 5000 +#define CYDEV_VDDIO1 5.0 +#define CYDEV_VDDIO1_MV 5000 +#define CYDEV_VDDIO2 5.0 +#define CYDEV_VDDIO2_MV 5000 +#define CYDEV_VDDIO3 3.3 +#define CYDEV_VDDIO3_MV 3300 +#define CYDEV_VIO0 5 +#define CYDEV_VIO0_MV 5000 +#define CYDEV_VIO1 5 +#define CYDEV_VIO1_MV 5000 +#define CYDEV_VIO2 5 +#define CYDEV_VIO2_MV 5000 +#define CYDEV_VIO3 3.3 +#define CYDEV_VIO3_MV 3300 +#define DMA_CHANNELS_USED__MASK0 0x00000000u +#define CYDEV_BOOTLOADER_ENABLE 0 + +#endif /* INCLUDED_CYFITTER_H */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c new file mode 100644 index 0000000..200ebad --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -0,0 +1,412 @@ +/******************************************************************************* +* FILENAME: cyfitter_cfg.c +* PSoC Creator 2.2 Component Pack 6 +* +* Description: +* This file is automatically generated by PSoC Creator with device +* initialization code. Except for the user defined sections in +* CyClockStartupError(), this file should not be modified. +* +******************************************************************************** +* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include +#include +#include +#include +#include +#include + +/* Clock startup error codes */ +#define CYCLOCKSTART_NO_ERROR 0u +#define CYCLOCKSTART_XTAL_ERROR 1u +#define CYCLOCKSTART_32KHZ_ERROR 2u +#define CYCLOCKSTART_PLL_ERROR 3u + +#ifdef CY_NEED_CYCLOCKSTARTUPERROR +/******************************************************************************* +* Function Name: CyClockStartupError +******************************************************************************** +* Summary: +* If an error is encountered during clock configuration (crystal startup error, +* PLL lock error, etc.), the system will end up here. Unless reimplemented by +* the customer, this function will stop in an infinite loop. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((unused)) +#endif +static void CyClockStartupError(uint8 errorCode); +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((unused)) +#endif +static void CyClockStartupError(uint8 errorCode) +{ + /* To remove the compiler warning if errorCode not used. */ + errorCode = errorCode; + + /* `#START CyClockStartupError` */ + + /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + /* we will end up here to allow the customer to implement something to */ + /* deal with the clock condition. */ + + /* `#END` */ + + /* If nothing else, stop here since the clocks have not started */ + /* correctly. */ + while(1) {} +} +#endif + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) + #define CYPACKED __attribute__ ((packed)) + #define CYALIGNED __attribute__ ((aligned)) + + #if defined(__ARMCC_VERSION) + #define CY_CFG_MEMORY_BARRIER() __memory_changed() + #else + #define CY_CFG_MEMORY_BARRIER() __sync_synchronize() + #endif + + + __attribute__ ((unused)) + static void CYMEMZERO(void *s, size_t n); + __attribute__ ((unused)) + static void CYMEMZERO(void *s, size_t n) + { + (void)memset(s, 0, n); + } + __attribute__ ((unused)) + static void CYCONFIGCPY(void *dest, const void *src, size_t n); + __attribute__ ((unused)) + static void CYCONFIGCPY(void *dest, const void *src, size_t n) + { + (void)memcpy(dest, src, n); + } + __attribute__ ((unused)) + static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); + __attribute__ ((unused)) + static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) + { + (void)memcpy(dest, src, n); + } +#else + #error Unsupported toolchain +#endif + +#define CY_CFG_BASE_ADDR_COUNT 16u +typedef struct +{ + uint8 offset; + uint8 value; +} CYPACKED cy_cfg_addrvalue_t; + +#define cy_cfg_addr_table ((const uint32 CYFAR *)0x48000000u) +#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000040u) + +/* UDB_1_1_0_CONFIG Address: CYDEV_UCFG_B1_P3_U1_BASE Size (bytes): 128 */ +#define BS_UDB_1_1_0_CONFIG_VAL ((const uint8 CYFAR *)0x480002CCu) + +/* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */ +#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x4800034Cu) + +/* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */ +#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x48000354u) + +/* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */ +#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x48000360u) + +/* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */ +#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x48000368u) + +/* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */ +#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x48000370u) + +/* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ +#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x4800037Cu) + +/* IOPINS0_5 Address: CYREG_PRT5_DR Size (bytes): 10 */ +#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x48000384u) + +/* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */ +#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x48000390u) + + +/******************************************************************************* +* Function Name: cfg_write_bytes32 +******************************************************************************** +* Summary: +* This function is used for setting up the chip configuration areas that +* contain relatively sparse data. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) +{ + /* For 32-bit little-endian architectures */ + uint32 i, j = 0u; + for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) + { + uint32 baseAddr = addr_table[i]; + uint8 count = (uint8)baseAddr; + baseAddr &= 0xFFFFFF00u; + while (count != 0u) + { + CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value); + j++; + count--; + } + } +} + +/******************************************************************************* +* Function Name: ClockSetup +******************************************************************************** +* +* Summary: +* Performs the initialization of all of the clocks in the device based on the +* settings in the Clock tab of the DWR. This includes enabling the requested +* clocks and setting the necessary dividers to produce the desired frequency. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void ClockSetup(void); +static void ClockSetup(void) +{ + uint32 timeout; + uint8 pllLock; + + + /* Configure Digital Clocks based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0001u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x18u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x001Du); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x19u); + + /* Configure ILO based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x02u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_CR), 0x08u); + + /* Configure IMO based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x02u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_24MHZ))); + + /* Configure PLL based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1051u); + /* Wait up to 250us for the PLL to lock */ + pllLock = 0u; + for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) { + pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0)); + CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */ + } + + /* Configure Bus/Master Clock based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); + + CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x02u))); +} + + +/* Analog API Functions */ + + +/******************************************************************************* +* Function Name: AnalogSetDefault +******************************************************************************** +* +* Summary: +* Sets up the analog portions of the chip to default values based on chip +* configuration options from the project. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void AnalogSetDefault(void); +static void AnalogSetDefault(void) +{ + uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u)); + CY_SET_XTND_REG8((void CYFAR *)CYREG_BG_DFT0, bg_xover_inl_trim & 0x07u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_BG_DFT1, ((uint8)((uint8)bg_xover_inl_trim >> 4)) & 0x0Fu); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u); +} + + +/******************************************************************************* +* Function Name: SetAnalogRoutingPumps +******************************************************************************** +* +* Summary: +* Enables or disables the analog pumps feeding analog routing switches. +* Intended to be called at startup, based on the Vdda system configuration; +* may be called during operation when the user informs us that the Vdda voltage +* crossed the pump threshold. +* +* Parameters: +* enabled - 1 to enable the pumps, 0 to disable the pumps +* +* Return: +* void +* +*******************************************************************************/ +void SetAnalogRoutingPumps(uint8 enabled) +{ + uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0); + if (enabled != 0u) + { + regValue |= 0x00u; + } + else + { + regValue &= (uint8)~0x00u; + } + CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue); +} + +#define CY_AMUX_UNUSED CYREG_BOOST_SR + + +/******************************************************************************* +* Function Name: cyfitter_cfg +******************************************************************************** +* Summary: +* This function is called by the start-up code for the selected device. It +* performs all of the necessary device configuration based on the design +* settings. This includes settings from the Design Wide Resources (DWR) such +* as Clocks and Pins as well as any component configuration that is necessary. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ + +void cyfitter_cfg(void) +{ +#ifdef CYGlobalIntDisable + /* Disable interrupts by default. Let user enable if/when they want. */ + CYGlobalIntDisable +#endif + + + /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u)); + /* Setup clocks based on selections from Clock DWR */ + ClockSetup(); + /* Enable/Disable Debug functionality based on settings from System DWR */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u)); + + { + + typedef struct { + void CYFAR *address; + uint16 size; + } CYPACKED cfg_memset_t; + + + typedef struct { + void CYFAR *dest; + const void CYFAR *src; + uint16 size; + } CYPACKED cfg_memcpy_t; + + static const cfg_memset_t CYCODE cfg_memset_list [] = { + /* address, size */ + {(void CYFAR *)(CYREG_PRT1_DR), 16u}, + {(void CYFAR *)(CYREG_PRT15_DR), 16u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 640u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P3_ROUTE_BASE), 1280u}, + {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, + {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, + {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, + }; + + static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { + /* dest, src, size */ + {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), BS_UDB_1_1_0_CONFIG_VAL, 128u}, + }; + + uint8 CYDATA i; + + /* Zero out critical memory blocks before beginning configuration */ + for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + { + const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; + CYMEMZERO(ms->address, (uint32)(ms->size)); + } + + /* Copy device configuration data into registers */ + for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) + { + const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; + void * CYDATA destPtr = mc->dest; + const void * CYDATA srcPtr = mc->src; + uint16 CYDATA numBytes = mc->size; + CYCONFIGCPY(destPtr, srcPtr, numBytes); + } + + cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); + + /* Enable digital routing */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u); + + /* Enable UDB array */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u); + } + + /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ + CYCONFIGCPY((void CYFAR *)(CYREG_PRT0_DM0), (const void CYFAR *)(BS_IOPINS0_0_VAL), 8u); + CYCONFIGCPY((void CYFAR *)(CYREG_PRT12_DR), (const void CYFAR *)(BS_IOPINS0_7_VAL), 10u); + CYCONFIGCPY((void CYFAR *)(CYREG_PRT12_DR + 0x0000000Bu), (const void CYFAR *)(BS_IOPINS1_7_VAL), 5u); + CYCONFIGCPY((void CYFAR *)(CYREG_PRT2_DM0), (const void CYFAR *)(BS_IOPINS0_2_VAL), 8u); + CYCONFIGCPY((void CYFAR *)(CYREG_PRT3_DR), (const void CYFAR *)(BS_IOPINS0_3_VAL), 10u); + CYCONFIGCPY((void CYFAR *)(CYREG_PRT4_DM0), (const void CYFAR *)(BS_IOPINS0_4_VAL), 8u); + CYCONFIGCPY((void CYFAR *)(CYREG_PRT5_DR), (const void CYFAR *)(BS_IOPINS0_5_VAL), 10u); + CYCONFIGCPY((void CYFAR *)(CYREG_PRT6_DM0), (const void CYFAR *)(BS_IOPINS0_6_VAL), 8u); + + /* Switch Boost to the precision bandgap reference from its internal reference */ + CY_SET_REG8((void CYXDATA *)CYDEV_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYDEV_BOOST_CR2) | 0x08u)); + + /* Perform basic analog initialization to defaults */ + AnalogSetDefault(); + + /* Configure alternate active mode */ + CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u); +} diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h new file mode 100644 index 0000000..2a831c5 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -0,0 +1,28 @@ +/******************************************************************************* +* FILENAME: cyfitter_cfg.h +* PSoC Creator 2.2 Component Pack 6 +* +* Description: +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef CYFITTER_CFG_H +#define CYFITTER_CFG_H + +#include + +extern void cyfitter_cfg(void); + +/* Analog Set/Unset methods */ +extern void SetAnalogRoutingPumps(uint8 enabled); + + +#endif /* CYFITTER_CFG_H */ + +/*[]*/ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc new file mode 100644 index 0000000..629bee4 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -0,0 +1,1867 @@ +.ifndef INCLUDED_CYFITTERGNU_INC +.set INCLUDED_CYFITTERGNU_INC, 1 +.include "cydevicegnu.inc" +.include "cydevicegnu_trm.inc" + +/* SDCard_RxInternalInterrupt */ +.set SDCard_RxInternalInterrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SDCard_RxInternalInterrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SDCard_RxInternalInterrupt__INTC_MASK, 0x01 +.set SDCard_RxInternalInterrupt__INTC_NUMBER, 0 +.set SDCard_RxInternalInterrupt__INTC_PRIOR_NUM, 7 +.set SDCard_RxInternalInterrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set SDCard_RxInternalInterrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SDCard_RxInternalInterrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SDCard_TxInternalInterrupt */ +.set SDCard_TxInternalInterrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SDCard_TxInternalInterrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SDCard_TxInternalInterrupt__INTC_MASK, 0x02 +.set SDCard_TxInternalInterrupt__INTC_NUMBER, 1 +.set SDCard_TxInternalInterrupt__INTC_PRIOR_NUM, 7 +.set SDCard_TxInternalInterrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set SDCard_TxInternalInterrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SDCard_TxInternalInterrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_Out_DBx */ +.set SCSI_Out_DBx__0__MASK, 0x01 +.set SCSI_Out_DBx__0__PC, CYREG_PRT0_PC0 +.set SCSI_Out_DBx__0__PORT, 0 +.set SCSI_Out_DBx__0__SHIFT, 0 +.set SCSI_Out_DBx__1__MASK, 0x02 +.set SCSI_Out_DBx__1__PC, CYREG_PRT0_PC1 +.set SCSI_Out_DBx__1__PORT, 0 +.set SCSI_Out_DBx__1__SHIFT, 1 +.set SCSI_Out_DBx__2__MASK, 0x04 +.set SCSI_Out_DBx__2__PC, CYREG_PRT0_PC2 +.set SCSI_Out_DBx__2__PORT, 0 +.set SCSI_Out_DBx__2__SHIFT, 2 +.set SCSI_Out_DBx__3__MASK, 0x08 +.set SCSI_Out_DBx__3__PC, CYREG_PRT0_PC3 +.set SCSI_Out_DBx__3__PORT, 0 +.set SCSI_Out_DBx__3__SHIFT, 3 +.set SCSI_Out_DBx__4__MASK, 0x10 +.set SCSI_Out_DBx__4__PC, CYREG_PRT0_PC4 +.set SCSI_Out_DBx__4__PORT, 0 +.set SCSI_Out_DBx__4__SHIFT, 4 +.set SCSI_Out_DBx__5__MASK, 0x20 +.set SCSI_Out_DBx__5__PC, CYREG_PRT0_PC5 +.set SCSI_Out_DBx__5__PORT, 0 +.set SCSI_Out_DBx__5__SHIFT, 5 +.set SCSI_Out_DBx__6__MASK, 0x40 +.set SCSI_Out_DBx__6__PC, CYREG_PRT0_PC6 +.set SCSI_Out_DBx__6__PORT, 0 +.set SCSI_Out_DBx__6__SHIFT, 6 +.set SCSI_Out_DBx__7__MASK, 0x80 +.set SCSI_Out_DBx__7__PC, CYREG_PRT0_PC7 +.set SCSI_Out_DBx__7__PORT, 0 +.set SCSI_Out_DBx__7__SHIFT, 7 +.set SCSI_Out_DBx__AG, CYREG_PRT0_AG +.set SCSI_Out_DBx__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out_DBx__BIE, CYREG_PRT0_BIE +.set SCSI_Out_DBx__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out_DBx__BYP, CYREG_PRT0_BYP +.set SCSI_Out_DBx__CTL, CYREG_PRT0_CTL +.set SCSI_Out_DBx__DM0, CYREG_PRT0_DM0 +.set SCSI_Out_DBx__DM1, CYREG_PRT0_DM1 +.set SCSI_Out_DBx__DM2, CYREG_PRT0_DM2 +.set SCSI_Out_DBx__DR, CYREG_PRT0_DR +.set SCSI_Out_DBx__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out_DBx__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out_DBx__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out_DBx__MASK, 0xFF +.set SCSI_Out_DBx__PORT, 0 +.set SCSI_Out_DBx__PRT, CYREG_PRT0_PRT +.set SCSI_Out_DBx__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out_DBx__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out_DBx__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out_DBx__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out_DBx__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out_DBx__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out_DBx__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out_DBx__PS, CYREG_PRT0_PS +.set SCSI_Out_DBx__SCSI_Out_DB0__MASK, 0x01 +.set SCSI_Out_DBx__SCSI_Out_DB0__PC, CYREG_PRT0_PC0 +.set SCSI_Out_DBx__SCSI_Out_DB0__PORT, 0 +.set SCSI_Out_DBx__SCSI_Out_DB0__SHIFT, 0 +.set SCSI_Out_DBx__SCSI_Out_DB1__MASK, 0x02 +.set SCSI_Out_DBx__SCSI_Out_DB1__PC, CYREG_PRT0_PC1 +.set SCSI_Out_DBx__SCSI_Out_DB1__PORT, 0 +.set SCSI_Out_DBx__SCSI_Out_DB1__SHIFT, 1 +.set SCSI_Out_DBx__SCSI_Out_DB2__MASK, 0x04 +.set SCSI_Out_DBx__SCSI_Out_DB2__PC, CYREG_PRT0_PC2 +.set SCSI_Out_DBx__SCSI_Out_DB2__PORT, 0 +.set SCSI_Out_DBx__SCSI_Out_DB2__SHIFT, 2 +.set SCSI_Out_DBx__SCSI_Out_DB3__MASK, 0x08 +.set SCSI_Out_DBx__SCSI_Out_DB3__PC, CYREG_PRT0_PC3 +.set SCSI_Out_DBx__SCSI_Out_DB3__PORT, 0 +.set SCSI_Out_DBx__SCSI_Out_DB3__SHIFT, 3 +.set SCSI_Out_DBx__SCSI_Out_DB4__MASK, 0x10 +.set SCSI_Out_DBx__SCSI_Out_DB4__PC, CYREG_PRT0_PC4 +.set SCSI_Out_DBx__SCSI_Out_DB4__PORT, 0 +.set SCSI_Out_DBx__SCSI_Out_DB4__SHIFT, 4 +.set SCSI_Out_DBx__SCSI_Out_DB5__MASK, 0x20 +.set SCSI_Out_DBx__SCSI_Out_DB5__PC, CYREG_PRT0_PC5 +.set SCSI_Out_DBx__SCSI_Out_DB5__PORT, 0 +.set SCSI_Out_DBx__SCSI_Out_DB5__SHIFT, 5 +.set SCSI_Out_DBx__SCSI_Out_DB6__MASK, 0x40 +.set SCSI_Out_DBx__SCSI_Out_DB6__PC, CYREG_PRT0_PC6 +.set SCSI_Out_DBx__SCSI_Out_DB6__PORT, 0 +.set SCSI_Out_DBx__SCSI_Out_DB6__SHIFT, 6 +.set SCSI_Out_DBx__SCSI_Out_DB7__MASK, 0x80 +.set SCSI_Out_DBx__SCSI_Out_DB7__PC, CYREG_PRT0_PC7 +.set SCSI_Out_DBx__SCSI_Out_DB7__PORT, 0 +.set SCSI_Out_DBx__SCSI_Out_DB7__SHIFT, 7 +.set SCSI_Out_DBx__SHIFT, 0 +.set SCSI_Out_DBx__SLW, CYREG_PRT0_SLW + +/* SDCard_BSPIM */ +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_RxStsReg__4__POS, 4 +.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 +.set SDCard_BSPIM_RxStsReg__5__POS, 5 +.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 +.set SDCard_BSPIM_RxStsReg__6__POS, 6 +.set SDCard_BSPIM_RxStsReg__MASK, 0x70 +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST +.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 +.set SDCard_BSPIM_TxStsReg__0__POS, 0 +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST +.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 +.set SDCard_BSPIM_TxStsReg__1__POS, 1 +.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 +.set SDCard_BSPIM_TxStsReg__2__POS, 2 +.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 +.set SDCard_BSPIM_TxStsReg__3__POS, 3 +.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_TxStsReg__4__POS, 4 +.set SDCard_BSPIM_TxStsReg__MASK, 0x1F +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB07_08_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB07_08_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB07_08_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB07_08_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB07_08_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB07_08_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB07_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB07_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB07_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB07_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB07_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB07_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB07_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB07_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB07_F1 +.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL + +/* SCSI_In_DBx */ +.set SCSI_In_DBx__0__MASK, 0x01 +.set SCSI_In_DBx__0__PC, CYREG_PRT2_PC0 +.set SCSI_In_DBx__0__PORT, 2 +.set SCSI_In_DBx__0__SHIFT, 0 +.set SCSI_In_DBx__1__MASK, 0x02 +.set SCSI_In_DBx__1__PC, CYREG_PRT2_PC1 +.set SCSI_In_DBx__1__PORT, 2 +.set SCSI_In_DBx__1__SHIFT, 1 +.set SCSI_In_DBx__2__MASK, 0x04 +.set SCSI_In_DBx__2__PC, CYREG_PRT2_PC2 +.set SCSI_In_DBx__2__PORT, 2 +.set SCSI_In_DBx__2__SHIFT, 2 +.set SCSI_In_DBx__3__MASK, 0x08 +.set SCSI_In_DBx__3__PC, CYREG_PRT2_PC3 +.set SCSI_In_DBx__3__PORT, 2 +.set SCSI_In_DBx__3__SHIFT, 3 +.set SCSI_In_DBx__4__MASK, 0x10 +.set SCSI_In_DBx__4__PC, CYREG_PRT2_PC4 +.set SCSI_In_DBx__4__PORT, 2 +.set SCSI_In_DBx__4__SHIFT, 4 +.set SCSI_In_DBx__5__MASK, 0x20 +.set SCSI_In_DBx__5__PC, CYREG_PRT2_PC5 +.set SCSI_In_DBx__5__PORT, 2 +.set SCSI_In_DBx__5__SHIFT, 5 +.set SCSI_In_DBx__6__MASK, 0x40 +.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC6 +.set SCSI_In_DBx__6__PORT, 2 +.set SCSI_In_DBx__6__SHIFT, 6 +.set SCSI_In_DBx__7__MASK, 0x80 +.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC7 +.set SCSI_In_DBx__7__PORT, 2 +.set SCSI_In_DBx__7__SHIFT, 7 +.set SCSI_In_DBx__AG, CYREG_PRT2_AG +.set SCSI_In_DBx__AMUX, CYREG_PRT2_AMUX +.set SCSI_In_DBx__BIE, CYREG_PRT2_BIE +.set SCSI_In_DBx__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In_DBx__BYP, CYREG_PRT2_BYP +.set SCSI_In_DBx__CTL, CYREG_PRT2_CTL +.set SCSI_In_DBx__DM0, CYREG_PRT2_DM0 +.set SCSI_In_DBx__DM1, CYREG_PRT2_DM1 +.set SCSI_In_DBx__DM2, CYREG_PRT2_DM2 +.set SCSI_In_DBx__DR, CYREG_PRT2_DR +.set SCSI_In_DBx__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In_DBx__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In_DBx__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In_DBx__MASK, 0xFF +.set SCSI_In_DBx__PORT, 2 +.set SCSI_In_DBx__PRT, CYREG_PRT2_PRT +.set SCSI_In_DBx__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In_DBx__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In_DBx__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In_DBx__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In_DBx__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In_DBx__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In_DBx__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In_DBx__PS, CYREG_PRT2_PS +.set SCSI_In_DBx__SCSI_Out_DB0__MASK, 0x01 +.set SCSI_In_DBx__SCSI_Out_DB0__PC, CYREG_PRT2_PC0 +.set SCSI_In_DBx__SCSI_Out_DB0__PORT, 2 +.set SCSI_In_DBx__SCSI_Out_DB0__SHIFT, 0 +.set SCSI_In_DBx__SCSI_Out_DB1__MASK, 0x02 +.set SCSI_In_DBx__SCSI_Out_DB1__PC, CYREG_PRT2_PC1 +.set SCSI_In_DBx__SCSI_Out_DB1__PORT, 2 +.set SCSI_In_DBx__SCSI_Out_DB1__SHIFT, 1 +.set SCSI_In_DBx__SCSI_Out_DB2__MASK, 0x04 +.set SCSI_In_DBx__SCSI_Out_DB2__PC, CYREG_PRT2_PC2 +.set SCSI_In_DBx__SCSI_Out_DB2__PORT, 2 +.set SCSI_In_DBx__SCSI_Out_DB2__SHIFT, 2 +.set SCSI_In_DBx__SCSI_Out_DB3__MASK, 0x08 +.set SCSI_In_DBx__SCSI_Out_DB3__PC, CYREG_PRT2_PC3 +.set SCSI_In_DBx__SCSI_Out_DB3__PORT, 2 +.set SCSI_In_DBx__SCSI_Out_DB3__SHIFT, 3 +.set SCSI_In_DBx__SCSI_Out_DB4__MASK, 0x10 +.set SCSI_In_DBx__SCSI_Out_DB4__PC, CYREG_PRT2_PC4 +.set SCSI_In_DBx__SCSI_Out_DB4__PORT, 2 +.set SCSI_In_DBx__SCSI_Out_DB4__SHIFT, 4 +.set SCSI_In_DBx__SCSI_Out_DB5__MASK, 0x20 +.set SCSI_In_DBx__SCSI_Out_DB5__PC, CYREG_PRT2_PC5 +.set SCSI_In_DBx__SCSI_Out_DB5__PORT, 2 +.set SCSI_In_DBx__SCSI_Out_DB5__SHIFT, 5 +.set SCSI_In_DBx__SCSI_Out_DB6__MASK, 0x40 +.set SCSI_In_DBx__SCSI_Out_DB6__PC, CYREG_PRT2_PC6 +.set SCSI_In_DBx__SCSI_Out_DB6__PORT, 2 +.set SCSI_In_DBx__SCSI_Out_DB6__SHIFT, 6 +.set SCSI_In_DBx__SCSI_Out_DB7__MASK, 0x80 +.set SCSI_In_DBx__SCSI_Out_DB7__PC, CYREG_PRT2_PC7 +.set SCSI_In_DBx__SCSI_Out_DB7__PORT, 2 +.set SCSI_In_DBx__SCSI_Out_DB7__SHIFT, 7 +.set SCSI_In_DBx__SHIFT, 0 +.set SCSI_In_DBx__SLW, CYREG_PRT2_SLW + +/* SD_Data_Clk */ +.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 +.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 +.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 +.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 +.set SD_Data_Clk__INDEX, 0x00 +.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SD_Data_Clk__PM_ACT_MSK, 0x01 +.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SD_Data_Clk__PM_STBY_MSK, 0x01 + +/* SD_Init_Clk */ +.set SD_Init_Clk__CFG0, CYREG_CLKDIST_DCFG1_CFG0 +.set SD_Init_Clk__CFG1, CYREG_CLKDIST_DCFG1_CFG1 +.set SD_Init_Clk__CFG2, CYREG_CLKDIST_DCFG1_CFG2 +.set SD_Init_Clk__CFG2_SRC_SEL_MASK, 0x07 +.set SD_Init_Clk__INDEX, 0x01 +.set SD_Init_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SD_Init_Clk__PM_ACT_MSK, 0x02 +.set SD_Init_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SD_Init_Clk__PM_STBY_MSK, 0x02 + +/* SD_Clk_Ctl */ +.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01 +.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0 +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB05_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB05_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01 +.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB05_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL + +/* PARITY_EN */ +.set PARITY_EN__0__MASK, 0x10 +.set PARITY_EN__0__PC, CYREG_PRT5_PC4 +.set PARITY_EN__0__PORT, 5 +.set PARITY_EN__0__SHIFT, 4 +.set PARITY_EN__AG, CYREG_PRT5_AG +.set PARITY_EN__AMUX, CYREG_PRT5_AMUX +.set PARITY_EN__BIE, CYREG_PRT5_BIE +.set PARITY_EN__BIT_MASK, CYREG_PRT5_BIT_MASK +.set PARITY_EN__BYP, CYREG_PRT5_BYP +.set PARITY_EN__CTL, CYREG_PRT5_CTL +.set PARITY_EN__DM0, CYREG_PRT5_DM0 +.set PARITY_EN__DM1, CYREG_PRT5_DM1 +.set PARITY_EN__DM2, CYREG_PRT5_DM2 +.set PARITY_EN__DR, CYREG_PRT5_DR +.set PARITY_EN__INP_DIS, CYREG_PRT5_INP_DIS +.set PARITY_EN__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set PARITY_EN__LCD_EN, CYREG_PRT5_LCD_EN +.set PARITY_EN__MASK, 0x10 +.set PARITY_EN__PORT, 5 +.set PARITY_EN__PRT, CYREG_PRT5_PRT +.set PARITY_EN__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set PARITY_EN__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set PARITY_EN__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set PARITY_EN__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set PARITY_EN__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set PARITY_EN__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set PARITY_EN__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set PARITY_EN__PS, CYREG_PRT5_PS +.set PARITY_EN__SHIFT, 4 +.set PARITY_EN__SLW, CYREG_PRT5_SLW + +/* SCSI_Out */ +.set SCSI_Out__0__AG, CYREG_PRT4_AG +.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__0__BIE, CYREG_PRT4_BIE +.set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__0__BYP, CYREG_PRT4_BYP +.set SCSI_Out__0__CTL, CYREG_PRT4_CTL +.set SCSI_Out__0__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__0__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__0__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__0__DR, CYREG_PRT4_DR +.set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__0__MASK, 0x04 +.set SCSI_Out__0__PC, CYREG_PRT4_PC2 +.set SCSI_Out__0__PORT, 4 +.set SCSI_Out__0__PRT, CYREG_PRT4_PRT +.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__0__PS, CYREG_PRT4_PS +.set SCSI_Out__0__SHIFT, 2 +.set SCSI_Out__0__SLW, CYREG_PRT4_SLW +.set SCSI_Out__1__AG, CYREG_PRT4_AG +.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__1__BIE, CYREG_PRT4_BIE +.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__1__BYP, CYREG_PRT4_BYP +.set SCSI_Out__1__CTL, CYREG_PRT4_CTL +.set SCSI_Out__1__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__1__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__1__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__1__DR, CYREG_PRT4_DR +.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__1__MASK, 0x08 +.set SCSI_Out__1__PC, CYREG_PRT4_PC3 +.set SCSI_Out__1__PORT, 4 +.set SCSI_Out__1__PRT, CYREG_PRT4_PRT +.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__1__PS, CYREG_PRT4_PS +.set SCSI_Out__1__SHIFT, 3 +.set SCSI_Out__1__SLW, CYREG_PRT4_SLW +.set SCSI_Out__2__AG, CYREG_PRT4_AG +.set SCSI_Out__2__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__2__BIE, CYREG_PRT4_BIE +.set SCSI_Out__2__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__2__BYP, CYREG_PRT4_BYP +.set SCSI_Out__2__CTL, CYREG_PRT4_CTL +.set SCSI_Out__2__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__2__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__2__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__2__DR, CYREG_PRT4_DR +.set SCSI_Out__2__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__2__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__2__MASK, 0x10 +.set SCSI_Out__2__PC, CYREG_PRT4_PC4 +.set SCSI_Out__2__PORT, 4 +.set SCSI_Out__2__PRT, CYREG_PRT4_PRT +.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__2__PS, CYREG_PRT4_PS +.set SCSI_Out__2__SHIFT, 4 +.set SCSI_Out__2__SLW, CYREG_PRT4_SLW +.set SCSI_Out__3__AG, CYREG_PRT4_AG +.set SCSI_Out__3__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__3__BIE, CYREG_PRT4_BIE +.set SCSI_Out__3__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__3__BYP, CYREG_PRT4_BYP +.set SCSI_Out__3__CTL, CYREG_PRT4_CTL +.set SCSI_Out__3__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__3__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__3__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__3__DR, CYREG_PRT4_DR +.set SCSI_Out__3__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__3__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__3__MASK, 0x20 +.set SCSI_Out__3__PC, CYREG_PRT4_PC5 +.set SCSI_Out__3__PORT, 4 +.set SCSI_Out__3__PRT, CYREG_PRT4_PRT +.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__3__PS, CYREG_PRT4_PS +.set SCSI_Out__3__SHIFT, 5 +.set SCSI_Out__3__SLW, CYREG_PRT4_SLW +.set SCSI_Out__4__AG, CYREG_PRT4_AG +.set SCSI_Out__4__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__4__BIE, CYREG_PRT4_BIE +.set SCSI_Out__4__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__4__BYP, CYREG_PRT4_BYP +.set SCSI_Out__4__CTL, CYREG_PRT4_CTL +.set SCSI_Out__4__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__4__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__4__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__4__DR, CYREG_PRT4_DR +.set SCSI_Out__4__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__4__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__4__MASK, 0x40 +.set SCSI_Out__4__PC, CYREG_PRT4_PC6 +.set SCSI_Out__4__PORT, 4 +.set SCSI_Out__4__PRT, CYREG_PRT4_PRT +.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__4__PS, CYREG_PRT4_PS +.set SCSI_Out__4__SHIFT, 6 +.set SCSI_Out__4__SLW, CYREG_PRT4_SLW +.set SCSI_Out__5__AG, CYREG_PRT4_AG +.set SCSI_Out__5__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__5__BIE, CYREG_PRT4_BIE +.set SCSI_Out__5__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__5__BYP, CYREG_PRT4_BYP +.set SCSI_Out__5__CTL, CYREG_PRT4_CTL +.set SCSI_Out__5__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__5__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__5__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__5__DR, CYREG_PRT4_DR +.set SCSI_Out__5__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__5__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__5__MASK, 0x80 +.set SCSI_Out__5__PC, CYREG_PRT4_PC7 +.set SCSI_Out__5__PORT, 4 +.set SCSI_Out__5__PRT, CYREG_PRT4_PRT +.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__5__PS, CYREG_PRT4_PS +.set SCSI_Out__5__SHIFT, 7 +.set SCSI_Out__5__SLW, CYREG_PRT4_SLW +.set SCSI_Out__6__AG, CYREG_PRT6_AG +.set SCSI_Out__6__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__6__BIE, CYREG_PRT6_BIE +.set SCSI_Out__6__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__6__BYP, CYREG_PRT6_BYP +.set SCSI_Out__6__CTL, CYREG_PRT6_CTL +.set SCSI_Out__6__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__6__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__6__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__6__DR, CYREG_PRT6_DR +.set SCSI_Out__6__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__6__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__6__MASK, 0x01 +.set SCSI_Out__6__PC, CYREG_PRT6_PC0 +.set SCSI_Out__6__PORT, 6 +.set SCSI_Out__6__PRT, CYREG_PRT6_PRT +.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__6__PS, CYREG_PRT6_PS +.set SCSI_Out__6__SHIFT, 0 +.set SCSI_Out__6__SLW, CYREG_PRT6_SLW +.set SCSI_Out__7__AG, CYREG_PRT6_AG +.set SCSI_Out__7__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__7__BIE, CYREG_PRT6_BIE +.set SCSI_Out__7__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__7__BYP, CYREG_PRT6_BYP +.set SCSI_Out__7__CTL, CYREG_PRT6_CTL +.set SCSI_Out__7__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__7__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__7__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__7__DR, CYREG_PRT6_DR +.set SCSI_Out__7__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__7__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__7__MASK, 0x02 +.set SCSI_Out__7__PC, CYREG_PRT6_PC1 +.set SCSI_Out__7__PORT, 6 +.set SCSI_Out__7__PRT, CYREG_PRT6_PRT +.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__7__PS, CYREG_PRT6_PS +.set SCSI_Out__7__SHIFT, 1 +.set SCSI_Out__7__SLW, CYREG_PRT6_SLW +.set SCSI_Out__8__AG, CYREG_PRT6_AG +.set SCSI_Out__8__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__8__BIE, CYREG_PRT6_BIE +.set SCSI_Out__8__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__8__BYP, CYREG_PRT6_BYP +.set SCSI_Out__8__CTL, CYREG_PRT6_CTL +.set SCSI_Out__8__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__8__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__8__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__8__DR, CYREG_PRT6_DR +.set SCSI_Out__8__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__8__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__8__MASK, 0x04 +.set SCSI_Out__8__PC, CYREG_PRT6_PC2 +.set SCSI_Out__8__PORT, 6 +.set SCSI_Out__8__PRT, CYREG_PRT6_PRT +.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__8__PS, CYREG_PRT6_PS +.set SCSI_Out__8__SHIFT, 2 +.set SCSI_Out__8__SLW, CYREG_PRT6_SLW +.set SCSI_Out__9__AG, CYREG_PRT6_AG +.set SCSI_Out__9__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__9__BIE, CYREG_PRT6_BIE +.set SCSI_Out__9__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__9__BYP, CYREG_PRT6_BYP +.set SCSI_Out__9__CTL, CYREG_PRT6_CTL +.set SCSI_Out__9__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__9__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__9__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__9__DR, CYREG_PRT6_DR +.set SCSI_Out__9__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__9__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__9__MASK, 0x08 +.set SCSI_Out__9__PC, CYREG_PRT6_PC3 +.set SCSI_Out__9__PORT, 6 +.set SCSI_Out__9__PRT, CYREG_PRT6_PRT +.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__9__PS, CYREG_PRT6_PS +.set SCSI_Out__9__SHIFT, 3 +.set SCSI_Out__9__SLW, CYREG_PRT6_SLW +.set SCSI_Out__ACK__AG, CYREG_PRT4_AG +.set SCSI_Out__ACK__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__ACK__BIE, CYREG_PRT4_BIE +.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__ACK__BYP, CYREG_PRT4_BYP +.set SCSI_Out__ACK__CTL, CYREG_PRT4_CTL +.set SCSI_Out__ACK__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__ACK__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__ACK__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__ACK__DR, CYREG_PRT4_DR +.set SCSI_Out__ACK__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__ACK__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__ACK__MASK, 0x20 +.set SCSI_Out__ACK__PC, CYREG_PRT4_PC5 +.set SCSI_Out__ACK__PORT, 4 +.set SCSI_Out__ACK__PRT, CYREG_PRT4_PRT +.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__ACK__PS, CYREG_PRT4_PS +.set SCSI_Out__ACK__SHIFT, 5 +.set SCSI_Out__ACK__SLW, CYREG_PRT4_SLW +.set SCSI_Out__ATN__AG, CYREG_PRT4_AG +.set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE +.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP +.set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL +.set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__ATN__DR, CYREG_PRT4_DR +.set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__ATN__MASK, 0x08 +.set SCSI_Out__ATN__PC, CYREG_PRT4_PC3 +.set SCSI_Out__ATN__PORT, 4 +.set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT +.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__ATN__PS, CYREG_PRT4_PS +.set SCSI_Out__ATN__SHIFT, 3 +.set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW +.set SCSI_Out__BSY__AG, CYREG_PRT4_AG +.set SCSI_Out__BSY__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__BSY__BIE, CYREG_PRT4_BIE +.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__BSY__BYP, CYREG_PRT4_BYP +.set SCSI_Out__BSY__CTL, CYREG_PRT4_CTL +.set SCSI_Out__BSY__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__BSY__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__BSY__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__BSY__DR, CYREG_PRT4_DR +.set SCSI_Out__BSY__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__BSY__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__BSY__MASK, 0x10 +.set SCSI_Out__BSY__PC, CYREG_PRT4_PC4 +.set SCSI_Out__BSY__PORT, 4 +.set SCSI_Out__BSY__PRT, CYREG_PRT4_PRT +.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__BSY__PS, CYREG_PRT4_PS +.set SCSI_Out__BSY__SHIFT, 4 +.set SCSI_Out__BSY__SLW, CYREG_PRT4_SLW +.set SCSI_Out__CD__AG, CYREG_PRT6_AG +.set SCSI_Out__CD__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__CD__BIE, CYREG_PRT6_BIE +.set SCSI_Out__CD__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__CD__BYP, CYREG_PRT6_BYP +.set SCSI_Out__CD__CTL, CYREG_PRT6_CTL +.set SCSI_Out__CD__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__CD__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__CD__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__CD__DR, CYREG_PRT6_DR +.set SCSI_Out__CD__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__CD__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__CD__MASK, 0x02 +.set SCSI_Out__CD__PC, CYREG_PRT6_PC1 +.set SCSI_Out__CD__PORT, 6 +.set SCSI_Out__CD__PRT, CYREG_PRT6_PRT +.set SCSI_Out__CD__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__CD__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__CD__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__CD__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__CD__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__CD__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__CD__PS, CYREG_PRT6_PS +.set SCSI_Out__CD__SHIFT, 1 +.set SCSI_Out__CD__SLW, CYREG_PRT6_SLW +.set SCSI_Out__DBP__AG, CYREG_PRT4_AG +.set SCSI_Out__DBP__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__DBP__BIE, CYREG_PRT4_BIE +.set SCSI_Out__DBP__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__DBP__BYP, CYREG_PRT4_BYP +.set SCSI_Out__DBP__CTL, CYREG_PRT4_CTL +.set SCSI_Out__DBP__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__DBP__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__DBP__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__DBP__DR, CYREG_PRT4_DR +.set SCSI_Out__DBP__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__DBP__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__DBP__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__DBP__MASK, 0x04 +.set SCSI_Out__DBP__PC, CYREG_PRT4_PC2 +.set SCSI_Out__DBP__PORT, 4 +.set SCSI_Out__DBP__PRT, CYREG_PRT4_PRT +.set SCSI_Out__DBP__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__DBP__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__DBP__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__DBP__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__DBP__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__DBP__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__DBP__PS, CYREG_PRT4_PS +.set SCSI_Out__DBP__SHIFT, 2 +.set SCSI_Out__DBP__SLW, CYREG_PRT4_SLW +.set SCSI_Out__IO__AG, CYREG_PRT6_AG +.set SCSI_Out__IO__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__IO__BIE, CYREG_PRT6_BIE +.set SCSI_Out__IO__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__IO__BYP, CYREG_PRT6_BYP +.set SCSI_Out__IO__CTL, CYREG_PRT6_CTL +.set SCSI_Out__IO__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__IO__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__IO__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__IO__DR, CYREG_PRT6_DR +.set SCSI_Out__IO__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__IO__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__IO__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__IO__MASK, 0x08 +.set SCSI_Out__IO__PC, CYREG_PRT6_PC3 +.set SCSI_Out__IO__PORT, 6 +.set SCSI_Out__IO__PRT, CYREG_PRT6_PRT +.set SCSI_Out__IO__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__IO__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__IO__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__IO__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__IO__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__IO__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__IO__PS, CYREG_PRT6_PS +.set SCSI_Out__IO__SHIFT, 3 +.set SCSI_Out__IO__SLW, CYREG_PRT6_SLW +.set SCSI_Out__MSG__AG, CYREG_PRT4_AG +.set SCSI_Out__MSG__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__MSG__BIE, CYREG_PRT4_BIE +.set SCSI_Out__MSG__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__MSG__BYP, CYREG_PRT4_BYP +.set SCSI_Out__MSG__CTL, CYREG_PRT4_CTL +.set SCSI_Out__MSG__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__MSG__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__MSG__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__MSG__DR, CYREG_PRT4_DR +.set SCSI_Out__MSG__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__MSG__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__MSG__MASK, 0x80 +.set SCSI_Out__MSG__PC, CYREG_PRT4_PC7 +.set SCSI_Out__MSG__PORT, 4 +.set SCSI_Out__MSG__PRT, CYREG_PRT4_PRT +.set SCSI_Out__MSG__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__MSG__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__MSG__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__MSG__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__MSG__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__MSG__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__MSG__PS, CYREG_PRT4_PS +.set SCSI_Out__MSG__SHIFT, 7 +.set SCSI_Out__MSG__SLW, CYREG_PRT4_SLW +.set SCSI_Out__REQ__AG, CYREG_PRT6_AG +.set SCSI_Out__REQ__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__REQ__BIE, CYREG_PRT6_BIE +.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__REQ__BYP, CYREG_PRT6_BYP +.set SCSI_Out__REQ__CTL, CYREG_PRT6_CTL +.set SCSI_Out__REQ__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__REQ__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__REQ__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__REQ__DR, CYREG_PRT6_DR +.set SCSI_Out__REQ__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__REQ__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__REQ__MASK, 0x04 +.set SCSI_Out__REQ__PC, CYREG_PRT6_PC2 +.set SCSI_Out__REQ__PORT, 6 +.set SCSI_Out__REQ__PRT, CYREG_PRT6_PRT +.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__REQ__PS, CYREG_PRT6_PS +.set SCSI_Out__REQ__SHIFT, 2 +.set SCSI_Out__REQ__SLW, CYREG_PRT6_SLW +.set SCSI_Out__RST__AG, CYREG_PRT4_AG +.set SCSI_Out__RST__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__RST__BIE, CYREG_PRT4_BIE +.set SCSI_Out__RST__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__RST__BYP, CYREG_PRT4_BYP +.set SCSI_Out__RST__CTL, CYREG_PRT4_CTL +.set SCSI_Out__RST__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__RST__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__RST__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__RST__DR, CYREG_PRT4_DR +.set SCSI_Out__RST__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__RST__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__RST__MASK, 0x40 +.set SCSI_Out__RST__PC, CYREG_PRT4_PC6 +.set SCSI_Out__RST__PORT, 4 +.set SCSI_Out__RST__PRT, CYREG_PRT4_PRT +.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__RST__PS, CYREG_PRT4_PS +.set SCSI_Out__RST__SHIFT, 6 +.set SCSI_Out__RST__SLW, CYREG_PRT4_SLW +.set SCSI_Out__SEL__AG, CYREG_PRT6_AG +.set SCSI_Out__SEL__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__SEL__BIE, CYREG_PRT6_BIE +.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__SEL__BYP, CYREG_PRT6_BYP +.set SCSI_Out__SEL__CTL, CYREG_PRT6_CTL +.set SCSI_Out__SEL__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__SEL__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__SEL__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__SEL__DR, CYREG_PRT6_DR +.set SCSI_Out__SEL__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__SEL__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__SEL__MASK, 0x01 +.set SCSI_Out__SEL__PC, CYREG_PRT6_PC0 +.set SCSI_Out__SEL__PORT, 6 +.set SCSI_Out__SEL__PRT, CYREG_PRT6_PRT +.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__SEL__PS, CYREG_PRT6_PS +.set SCSI_Out__SEL__SHIFT, 0 +.set SCSI_Out__SEL__SLW, CYREG_PRT6_SLW + +/* SCSI_ID */ +.set SCSI_ID__0__MASK, 0x80 +.set SCSI_ID__0__PC, CYREG_PRT5_PC7 +.set SCSI_ID__0__PORT, 5 +.set SCSI_ID__0__SHIFT, 7 +.set SCSI_ID__1__MASK, 0x40 +.set SCSI_ID__1__PC, CYREG_PRT5_PC6 +.set SCSI_ID__1__PORT, 5 +.set SCSI_ID__1__SHIFT, 6 +.set SCSI_ID__2__MASK, 0x20 +.set SCSI_ID__2__PC, CYREG_PRT5_PC5 +.set SCSI_ID__2__PORT, 5 +.set SCSI_ID__2__SHIFT, 5 +.set SCSI_ID__AG, CYREG_PRT5_AG +.set SCSI_ID__AMUX, CYREG_PRT5_AMUX +.set SCSI_ID__BIE, CYREG_PRT5_BIE +.set SCSI_ID__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_ID__BYP, CYREG_PRT5_BYP +.set SCSI_ID__CTL, CYREG_PRT5_CTL +.set SCSI_ID__DM0, CYREG_PRT5_DM0 +.set SCSI_ID__DM1, CYREG_PRT5_DM1 +.set SCSI_ID__DM2, CYREG_PRT5_DM2 +.set SCSI_ID__DR, CYREG_PRT5_DR +.set SCSI_ID__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_ID__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_ID__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_ID__PORT, 5 +.set SCSI_ID__PRT, CYREG_PRT5_PRT +.set SCSI_ID__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_ID__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_ID__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_ID__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_ID__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_ID__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_ID__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_ID__PS, CYREG_PRT5_PS +.set SCSI_ID__SLW, CYREG_PRT5_SLW + +/* SCSI_In */ +.set SCSI_In__0__AG, CYREG_PRT12_AG +.set SCSI_In__0__BIE, CYREG_PRT12_BIE +.set SCSI_In__0__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_In__0__BYP, CYREG_PRT12_BYP +.set SCSI_In__0__DM0, CYREG_PRT12_DM0 +.set SCSI_In__0__DM1, CYREG_PRT12_DM1 +.set SCSI_In__0__DM2, CYREG_PRT12_DM2 +.set SCSI_In__0__DR, CYREG_PRT12_DR +.set SCSI_In__0__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_In__0__MASK, 0x10 +.set SCSI_In__0__PC, CYREG_PRT12_PC4 +.set SCSI_In__0__PORT, 12 +.set SCSI_In__0__PRT, CYREG_PRT12_PRT +.set SCSI_In__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_In__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_In__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_In__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_In__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_In__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_In__0__PS, CYREG_PRT12_PS +.set SCSI_In__0__SHIFT, 4 +.set SCSI_In__0__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_In__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_In__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_In__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_In__0__SLW, CYREG_PRT12_SLW +.set SCSI_In__1__AG, CYREG_PRT12_AG +.set SCSI_In__1__BIE, CYREG_PRT12_BIE +.set SCSI_In__1__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_In__1__BYP, CYREG_PRT12_BYP +.set SCSI_In__1__DM0, CYREG_PRT12_DM0 +.set SCSI_In__1__DM1, CYREG_PRT12_DM1 +.set SCSI_In__1__DM2, CYREG_PRT12_DM2 +.set SCSI_In__1__DR, CYREG_PRT12_DR +.set SCSI_In__1__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_In__1__MASK, 0x20 +.set SCSI_In__1__PC, CYREG_PRT12_PC5 +.set SCSI_In__1__PORT, 12 +.set SCSI_In__1__PRT, CYREG_PRT12_PRT +.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_In__1__PS, CYREG_PRT12_PS +.set SCSI_In__1__SHIFT, 5 +.set SCSI_In__1__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_In__1__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_In__1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_In__1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_In__1__SLW, CYREG_PRT12_SLW +.set SCSI_In__2__AG, CYREG_PRT6_AG +.set SCSI_In__2__AMUX, CYREG_PRT6_AMUX +.set SCSI_In__2__BIE, CYREG_PRT6_BIE +.set SCSI_In__2__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In__2__BYP, CYREG_PRT6_BYP +.set SCSI_In__2__CTL, CYREG_PRT6_CTL +.set SCSI_In__2__DM0, CYREG_PRT6_DM0 +.set SCSI_In__2__DM1, CYREG_PRT6_DM1 +.set SCSI_In__2__DM2, CYREG_PRT6_DM2 +.set SCSI_In__2__DR, CYREG_PRT6_DR +.set SCSI_In__2__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In__2__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__2__MASK, 0x10 +.set SCSI_In__2__PC, CYREG_PRT6_PC4 +.set SCSI_In__2__PORT, 6 +.set SCSI_In__2__PRT, CYREG_PRT6_PRT +.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In__2__PS, CYREG_PRT6_PS +.set SCSI_In__2__SHIFT, 4 +.set SCSI_In__2__SLW, CYREG_PRT6_SLW +.set SCSI_In__3__AG, CYREG_PRT6_AG +.set SCSI_In__3__AMUX, CYREG_PRT6_AMUX +.set SCSI_In__3__BIE, CYREG_PRT6_BIE +.set SCSI_In__3__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In__3__BYP, CYREG_PRT6_BYP +.set SCSI_In__3__CTL, CYREG_PRT6_CTL +.set SCSI_In__3__DM0, CYREG_PRT6_DM0 +.set SCSI_In__3__DM1, CYREG_PRT6_DM1 +.set SCSI_In__3__DM2, CYREG_PRT6_DM2 +.set SCSI_In__3__DR, CYREG_PRT6_DR +.set SCSI_In__3__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In__3__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__3__MASK, 0x20 +.set SCSI_In__3__PC, CYREG_PRT6_PC5 +.set SCSI_In__3__PORT, 6 +.set SCSI_In__3__PRT, CYREG_PRT6_PRT +.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In__3__PS, CYREG_PRT6_PS +.set SCSI_In__3__SHIFT, 5 +.set SCSI_In__3__SLW, CYREG_PRT6_SLW +.set SCSI_In__4__AG, CYREG_PRT6_AG +.set SCSI_In__4__AMUX, CYREG_PRT6_AMUX +.set SCSI_In__4__BIE, CYREG_PRT6_BIE +.set SCSI_In__4__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In__4__BYP, CYREG_PRT6_BYP +.set SCSI_In__4__CTL, CYREG_PRT6_CTL +.set SCSI_In__4__DM0, CYREG_PRT6_DM0 +.set SCSI_In__4__DM1, CYREG_PRT6_DM1 +.set SCSI_In__4__DM2, CYREG_PRT6_DM2 +.set SCSI_In__4__DR, CYREG_PRT6_DR +.set SCSI_In__4__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In__4__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__4__MASK, 0x40 +.set SCSI_In__4__PC, CYREG_PRT6_PC6 +.set SCSI_In__4__PORT, 6 +.set SCSI_In__4__PRT, CYREG_PRT6_PRT +.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In__4__PS, CYREG_PRT6_PS +.set SCSI_In__4__SHIFT, 6 +.set SCSI_In__4__SLW, CYREG_PRT6_SLW +.set SCSI_In__5__AG, CYREG_PRT6_AG +.set SCSI_In__5__AMUX, CYREG_PRT6_AMUX +.set SCSI_In__5__BIE, CYREG_PRT6_BIE +.set SCSI_In__5__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In__5__BYP, CYREG_PRT6_BYP +.set SCSI_In__5__CTL, CYREG_PRT6_CTL +.set SCSI_In__5__DM0, CYREG_PRT6_DM0 +.set SCSI_In__5__DM1, CYREG_PRT6_DM1 +.set SCSI_In__5__DM2, CYREG_PRT6_DM2 +.set SCSI_In__5__DR, CYREG_PRT6_DR +.set SCSI_In__5__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In__5__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In__5__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__5__MASK, 0x80 +.set SCSI_In__5__PC, CYREG_PRT6_PC7 +.set SCSI_In__5__PORT, 6 +.set SCSI_In__5__PRT, CYREG_PRT6_PRT +.set SCSI_In__5__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In__5__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In__5__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In__5__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In__5__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In__5__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In__5__PS, CYREG_PRT6_PS +.set SCSI_In__5__SHIFT, 7 +.set SCSI_In__5__SLW, CYREG_PRT6_SLW +.set SCSI_In__6__AG, CYREG_PRT5_AG +.set SCSI_In__6__AMUX, CYREG_PRT5_AMUX +.set SCSI_In__6__BIE, CYREG_PRT5_BIE +.set SCSI_In__6__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In__6__BYP, CYREG_PRT5_BYP +.set SCSI_In__6__CTL, CYREG_PRT5_CTL +.set SCSI_In__6__DM0, CYREG_PRT5_DM0 +.set SCSI_In__6__DM1, CYREG_PRT5_DM1 +.set SCSI_In__6__DM2, CYREG_PRT5_DM2 +.set SCSI_In__6__DR, CYREG_PRT5_DR +.set SCSI_In__6__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In__6__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In__6__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In__6__MASK, 0x01 +.set SCSI_In__6__PC, CYREG_PRT5_PC0 +.set SCSI_In__6__PORT, 5 +.set SCSI_In__6__PRT, CYREG_PRT5_PRT +.set SCSI_In__6__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In__6__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In__6__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In__6__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In__6__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In__6__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In__6__PS, CYREG_PRT5_PS +.set SCSI_In__6__SHIFT, 0 +.set SCSI_In__6__SLW, CYREG_PRT5_SLW +.set SCSI_In__7__AG, CYREG_PRT5_AG +.set SCSI_In__7__AMUX, CYREG_PRT5_AMUX +.set SCSI_In__7__BIE, CYREG_PRT5_BIE +.set SCSI_In__7__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In__7__BYP, CYREG_PRT5_BYP +.set SCSI_In__7__CTL, CYREG_PRT5_CTL +.set SCSI_In__7__DM0, CYREG_PRT5_DM0 +.set SCSI_In__7__DM1, CYREG_PRT5_DM1 +.set SCSI_In__7__DM2, CYREG_PRT5_DM2 +.set SCSI_In__7__DR, CYREG_PRT5_DR +.set SCSI_In__7__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In__7__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In__7__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In__7__MASK, 0x02 +.set SCSI_In__7__PC, CYREG_PRT5_PC1 +.set SCSI_In__7__PORT, 5 +.set SCSI_In__7__PRT, CYREG_PRT5_PRT +.set SCSI_In__7__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In__7__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In__7__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In__7__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In__7__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In__7__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In__7__PS, CYREG_PRT5_PS +.set SCSI_In__7__SHIFT, 1 +.set SCSI_In__7__SLW, CYREG_PRT5_SLW +.set SCSI_In__8__AG, CYREG_PRT5_AG +.set SCSI_In__8__AMUX, CYREG_PRT5_AMUX +.set SCSI_In__8__BIE, CYREG_PRT5_BIE +.set SCSI_In__8__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In__8__BYP, CYREG_PRT5_BYP +.set SCSI_In__8__CTL, CYREG_PRT5_CTL +.set SCSI_In__8__DM0, CYREG_PRT5_DM0 +.set SCSI_In__8__DM1, CYREG_PRT5_DM1 +.set SCSI_In__8__DM2, CYREG_PRT5_DM2 +.set SCSI_In__8__DR, CYREG_PRT5_DR +.set SCSI_In__8__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In__8__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In__8__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In__8__MASK, 0x04 +.set SCSI_In__8__PC, CYREG_PRT5_PC2 +.set SCSI_In__8__PORT, 5 +.set SCSI_In__8__PRT, CYREG_PRT5_PRT +.set SCSI_In__8__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In__8__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In__8__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In__8__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In__8__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In__8__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In__8__PS, CYREG_PRT5_PS +.set SCSI_In__8__SHIFT, 2 +.set SCSI_In__8__SLW, CYREG_PRT5_SLW +.set SCSI_In__9__AG, CYREG_PRT5_AG +.set SCSI_In__9__AMUX, CYREG_PRT5_AMUX +.set SCSI_In__9__BIE, CYREG_PRT5_BIE +.set SCSI_In__9__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In__9__BYP, CYREG_PRT5_BYP +.set SCSI_In__9__CTL, CYREG_PRT5_CTL +.set SCSI_In__9__DM0, CYREG_PRT5_DM0 +.set SCSI_In__9__DM1, CYREG_PRT5_DM1 +.set SCSI_In__9__DM2, CYREG_PRT5_DM2 +.set SCSI_In__9__DR, CYREG_PRT5_DR +.set SCSI_In__9__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In__9__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In__9__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In__9__MASK, 0x08 +.set SCSI_In__9__PC, CYREG_PRT5_PC3 +.set SCSI_In__9__PORT, 5 +.set SCSI_In__9__PRT, CYREG_PRT5_PRT +.set SCSI_In__9__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In__9__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In__9__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In__9__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In__9__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In__9__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In__9__PS, CYREG_PRT5_PS +.set SCSI_In__9__SHIFT, 3 +.set SCSI_In__9__SLW, CYREG_PRT5_SLW +.set SCSI_In__ACK__AG, CYREG_PRT6_AG +.set SCSI_In__ACK__AMUX, CYREG_PRT6_AMUX +.set SCSI_In__ACK__BIE, CYREG_PRT6_BIE +.set SCSI_In__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In__ACK__BYP, CYREG_PRT6_BYP +.set SCSI_In__ACK__CTL, CYREG_PRT6_CTL +.set SCSI_In__ACK__DM0, CYREG_PRT6_DM0 +.set SCSI_In__ACK__DM1, CYREG_PRT6_DM1 +.set SCSI_In__ACK__DM2, CYREG_PRT6_DM2 +.set SCSI_In__ACK__DR, CYREG_PRT6_DR +.set SCSI_In__ACK__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In__ACK__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__ACK__MASK, 0x20 +.set SCSI_In__ACK__PC, CYREG_PRT6_PC5 +.set SCSI_In__ACK__PORT, 6 +.set SCSI_In__ACK__PRT, CYREG_PRT6_PRT +.set SCSI_In__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In__ACK__PS, CYREG_PRT6_PS +.set SCSI_In__ACK__SHIFT, 5 +.set SCSI_In__ACK__SLW, CYREG_PRT6_SLW +.set SCSI_In__ATN__AG, CYREG_PRT12_AG +.set SCSI_In__ATN__BIE, CYREG_PRT12_BIE +.set SCSI_In__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_In__ATN__BYP, CYREG_PRT12_BYP +.set SCSI_In__ATN__DM0, CYREG_PRT12_DM0 +.set SCSI_In__ATN__DM1, CYREG_PRT12_DM1 +.set SCSI_In__ATN__DM2, CYREG_PRT12_DM2 +.set SCSI_In__ATN__DR, CYREG_PRT12_DR +.set SCSI_In__ATN__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_In__ATN__MASK, 0x20 +.set SCSI_In__ATN__PC, CYREG_PRT12_PC5 +.set SCSI_In__ATN__PORT, 12 +.set SCSI_In__ATN__PRT, CYREG_PRT12_PRT +.set SCSI_In__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_In__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_In__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_In__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_In__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_In__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_In__ATN__PS, CYREG_PRT12_PS +.set SCSI_In__ATN__SHIFT, 5 +.set SCSI_In__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_In__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_In__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_In__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_In__ATN__SLW, CYREG_PRT12_SLW +.set SCSI_In__BSY__AG, CYREG_PRT6_AG +.set SCSI_In__BSY__AMUX, CYREG_PRT6_AMUX +.set SCSI_In__BSY__BIE, CYREG_PRT6_BIE +.set SCSI_In__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In__BSY__BYP, CYREG_PRT6_BYP +.set SCSI_In__BSY__CTL, CYREG_PRT6_CTL +.set SCSI_In__BSY__DM0, CYREG_PRT6_DM0 +.set SCSI_In__BSY__DM1, CYREG_PRT6_DM1 +.set SCSI_In__BSY__DM2, CYREG_PRT6_DM2 +.set SCSI_In__BSY__DR, CYREG_PRT6_DR +.set SCSI_In__BSY__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In__BSY__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__BSY__MASK, 0x10 +.set SCSI_In__BSY__PC, CYREG_PRT6_PC4 +.set SCSI_In__BSY__PORT, 6 +.set SCSI_In__BSY__PRT, CYREG_PRT6_PRT +.set SCSI_In__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In__BSY__PS, CYREG_PRT6_PS +.set SCSI_In__BSY__SHIFT, 4 +.set SCSI_In__BSY__SLW, CYREG_PRT6_SLW +.set SCSI_In__CD__AG, CYREG_PRT5_AG +.set SCSI_In__CD__AMUX, CYREG_PRT5_AMUX +.set SCSI_In__CD__BIE, CYREG_PRT5_BIE +.set SCSI_In__CD__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In__CD__BYP, CYREG_PRT5_BYP +.set SCSI_In__CD__CTL, CYREG_PRT5_CTL +.set SCSI_In__CD__DM0, CYREG_PRT5_DM0 +.set SCSI_In__CD__DM1, CYREG_PRT5_DM1 +.set SCSI_In__CD__DM2, CYREG_PRT5_DM2 +.set SCSI_In__CD__DR, CYREG_PRT5_DR +.set SCSI_In__CD__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In__CD__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In__CD__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In__CD__MASK, 0x02 +.set SCSI_In__CD__PC, CYREG_PRT5_PC1 +.set SCSI_In__CD__PORT, 5 +.set SCSI_In__CD__PRT, CYREG_PRT5_PRT +.set SCSI_In__CD__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In__CD__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In__CD__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In__CD__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In__CD__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In__CD__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In__CD__PS, CYREG_PRT5_PS +.set SCSI_In__CD__SHIFT, 1 +.set SCSI_In__CD__SLW, CYREG_PRT5_SLW +.set SCSI_In__DBP__AG, CYREG_PRT12_AG +.set SCSI_In__DBP__BIE, CYREG_PRT12_BIE +.set SCSI_In__DBP__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_In__DBP__BYP, CYREG_PRT12_BYP +.set SCSI_In__DBP__DM0, CYREG_PRT12_DM0 +.set SCSI_In__DBP__DM1, CYREG_PRT12_DM1 +.set SCSI_In__DBP__DM2, CYREG_PRT12_DM2 +.set SCSI_In__DBP__DR, CYREG_PRT12_DR +.set SCSI_In__DBP__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_In__DBP__MASK, 0x10 +.set SCSI_In__DBP__PC, CYREG_PRT12_PC4 +.set SCSI_In__DBP__PORT, 12 +.set SCSI_In__DBP__PRT, CYREG_PRT12_PRT +.set SCSI_In__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_In__DBP__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_In__DBP__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_In__DBP__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_In__DBP__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_In__DBP__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_In__DBP__PS, CYREG_PRT12_PS +.set SCSI_In__DBP__SHIFT, 4 +.set SCSI_In__DBP__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_In__DBP__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_In__DBP__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_In__DBP__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_In__DBP__SLW, CYREG_PRT12_SLW +.set SCSI_In__IO__AG, CYREG_PRT5_AG +.set SCSI_In__IO__AMUX, CYREG_PRT5_AMUX +.set SCSI_In__IO__BIE, CYREG_PRT5_BIE +.set SCSI_In__IO__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In__IO__BYP, CYREG_PRT5_BYP +.set SCSI_In__IO__CTL, CYREG_PRT5_CTL +.set SCSI_In__IO__DM0, CYREG_PRT5_DM0 +.set SCSI_In__IO__DM1, CYREG_PRT5_DM1 +.set SCSI_In__IO__DM2, CYREG_PRT5_DM2 +.set SCSI_In__IO__DR, CYREG_PRT5_DR +.set SCSI_In__IO__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In__IO__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In__IO__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In__IO__MASK, 0x08 +.set SCSI_In__IO__PC, CYREG_PRT5_PC3 +.set SCSI_In__IO__PORT, 5 +.set SCSI_In__IO__PRT, CYREG_PRT5_PRT +.set SCSI_In__IO__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In__IO__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In__IO__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In__IO__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In__IO__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In__IO__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In__IO__PS, CYREG_PRT5_PS +.set SCSI_In__IO__SHIFT, 3 +.set SCSI_In__IO__SLW, CYREG_PRT5_SLW +.set SCSI_In__MSG__AG, CYREG_PRT6_AG +.set SCSI_In__MSG__AMUX, CYREG_PRT6_AMUX +.set SCSI_In__MSG__BIE, CYREG_PRT6_BIE +.set SCSI_In__MSG__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In__MSG__BYP, CYREG_PRT6_BYP +.set SCSI_In__MSG__CTL, CYREG_PRT6_CTL +.set SCSI_In__MSG__DM0, CYREG_PRT6_DM0 +.set SCSI_In__MSG__DM1, CYREG_PRT6_DM1 +.set SCSI_In__MSG__DM2, CYREG_PRT6_DM2 +.set SCSI_In__MSG__DR, CYREG_PRT6_DR +.set SCSI_In__MSG__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In__MSG__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In__MSG__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__MSG__MASK, 0x80 +.set SCSI_In__MSG__PC, CYREG_PRT6_PC7 +.set SCSI_In__MSG__PORT, 6 +.set SCSI_In__MSG__PRT, CYREG_PRT6_PRT +.set SCSI_In__MSG__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In__MSG__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In__MSG__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In__MSG__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In__MSG__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In__MSG__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In__MSG__PS, CYREG_PRT6_PS +.set SCSI_In__MSG__SHIFT, 7 +.set SCSI_In__MSG__SLW, CYREG_PRT6_SLW +.set SCSI_In__REQ__AG, CYREG_PRT5_AG +.set SCSI_In__REQ__AMUX, CYREG_PRT5_AMUX +.set SCSI_In__REQ__BIE, CYREG_PRT5_BIE +.set SCSI_In__REQ__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In__REQ__BYP, CYREG_PRT5_BYP +.set SCSI_In__REQ__CTL, CYREG_PRT5_CTL +.set SCSI_In__REQ__DM0, CYREG_PRT5_DM0 +.set SCSI_In__REQ__DM1, CYREG_PRT5_DM1 +.set SCSI_In__REQ__DM2, CYREG_PRT5_DM2 +.set SCSI_In__REQ__DR, CYREG_PRT5_DR +.set SCSI_In__REQ__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In__REQ__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In__REQ__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In__REQ__MASK, 0x04 +.set SCSI_In__REQ__PC, CYREG_PRT5_PC2 +.set SCSI_In__REQ__PORT, 5 +.set SCSI_In__REQ__PRT, CYREG_PRT5_PRT +.set SCSI_In__REQ__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In__REQ__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In__REQ__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In__REQ__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In__REQ__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In__REQ__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In__REQ__PS, CYREG_PRT5_PS +.set SCSI_In__REQ__SHIFT, 2 +.set SCSI_In__REQ__SLW, CYREG_PRT5_SLW +.set SCSI_In__RST__AG, CYREG_PRT6_AG +.set SCSI_In__RST__AMUX, CYREG_PRT6_AMUX +.set SCSI_In__RST__BIE, CYREG_PRT6_BIE +.set SCSI_In__RST__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In__RST__BYP, CYREG_PRT6_BYP +.set SCSI_In__RST__CTL, CYREG_PRT6_CTL +.set SCSI_In__RST__DM0, CYREG_PRT6_DM0 +.set SCSI_In__RST__DM1, CYREG_PRT6_DM1 +.set SCSI_In__RST__DM2, CYREG_PRT6_DM2 +.set SCSI_In__RST__DR, CYREG_PRT6_DR +.set SCSI_In__RST__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In__RST__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__RST__MASK, 0x40 +.set SCSI_In__RST__PC, CYREG_PRT6_PC6 +.set SCSI_In__RST__PORT, 6 +.set SCSI_In__RST__PRT, CYREG_PRT6_PRT +.set SCSI_In__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In__RST__PS, CYREG_PRT6_PS +.set SCSI_In__RST__SHIFT, 6 +.set SCSI_In__RST__SLW, CYREG_PRT6_SLW +.set SCSI_In__SEL__AG, CYREG_PRT5_AG +.set SCSI_In__SEL__AMUX, CYREG_PRT5_AMUX +.set SCSI_In__SEL__BIE, CYREG_PRT5_BIE +.set SCSI_In__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In__SEL__BYP, CYREG_PRT5_BYP +.set SCSI_In__SEL__CTL, CYREG_PRT5_CTL +.set SCSI_In__SEL__DM0, CYREG_PRT5_DM0 +.set SCSI_In__SEL__DM1, CYREG_PRT5_DM1 +.set SCSI_In__SEL__DM2, CYREG_PRT5_DM2 +.set SCSI_In__SEL__DR, CYREG_PRT5_DR +.set SCSI_In__SEL__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In__SEL__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In__SEL__MASK, 0x01 +.set SCSI_In__SEL__PC, CYREG_PRT5_PC0 +.set SCSI_In__SEL__PORT, 5 +.set SCSI_In__SEL__PRT, CYREG_PRT5_PRT +.set SCSI_In__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In__SEL__PS, CYREG_PRT5_PS +.set SCSI_In__SEL__SHIFT, 0 +.set SCSI_In__SEL__SLW, CYREG_PRT5_SLW + +/* SD_DAT1 */ +.set SD_DAT1__0__MASK, 0x20 +.set SD_DAT1__0__PC, CYREG_PRT3_PC5 +.set SD_DAT1__0__PORT, 3 +.set SD_DAT1__0__SHIFT, 5 +.set SD_DAT1__AG, CYREG_PRT3_AG +.set SD_DAT1__AMUX, CYREG_PRT3_AMUX +.set SD_DAT1__BIE, CYREG_PRT3_BIE +.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_DAT1__BYP, CYREG_PRT3_BYP +.set SD_DAT1__CTL, CYREG_PRT3_CTL +.set SD_DAT1__DM0, CYREG_PRT3_DM0 +.set SD_DAT1__DM1, CYREG_PRT3_DM1 +.set SD_DAT1__DM2, CYREG_PRT3_DM2 +.set SD_DAT1__DR, CYREG_PRT3_DR +.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_DAT1__MASK, 0x20 +.set SD_DAT1__PORT, 3 +.set SD_DAT1__PRT, CYREG_PRT3_PRT +.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_DAT1__PS, CYREG_PRT3_PS +.set SD_DAT1__SHIFT, 5 +.set SD_DAT1__SLW, CYREG_PRT3_SLW + +/* SD_DAT2 */ +.set SD_DAT2__0__MASK, 0x01 +.set SD_DAT2__0__PC, CYREG_PRT3_PC0 +.set SD_DAT2__0__PORT, 3 +.set SD_DAT2__0__SHIFT, 0 +.set SD_DAT2__AG, CYREG_PRT3_AG +.set SD_DAT2__AMUX, CYREG_PRT3_AMUX +.set SD_DAT2__BIE, CYREG_PRT3_BIE +.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_DAT2__BYP, CYREG_PRT3_BYP +.set SD_DAT2__CTL, CYREG_PRT3_CTL +.set SD_DAT2__DM0, CYREG_PRT3_DM0 +.set SD_DAT2__DM1, CYREG_PRT3_DM1 +.set SD_DAT2__DM2, CYREG_PRT3_DM2 +.set SD_DAT2__DR, CYREG_PRT3_DR +.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_DAT2__MASK, 0x01 +.set SD_DAT2__PORT, 3 +.set SD_DAT2__PRT, CYREG_PRT3_PRT +.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_DAT2__PS, CYREG_PRT3_PS +.set SD_DAT2__SHIFT, 0 +.set SD_DAT2__SLW, CYREG_PRT3_SLW + +/* SD_MISO */ +.set SD_MISO__0__MASK, 0x10 +.set SD_MISO__0__PC, CYREG_PRT3_PC4 +.set SD_MISO__0__PORT, 3 +.set SD_MISO__0__SHIFT, 4 +.set SD_MISO__AG, CYREG_PRT3_AG +.set SD_MISO__AMUX, CYREG_PRT3_AMUX +.set SD_MISO__BIE, CYREG_PRT3_BIE +.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MISO__BYP, CYREG_PRT3_BYP +.set SD_MISO__CTL, CYREG_PRT3_CTL +.set SD_MISO__DM0, CYREG_PRT3_DM0 +.set SD_MISO__DM1, CYREG_PRT3_DM1 +.set SD_MISO__DM2, CYREG_PRT3_DM2 +.set SD_MISO__DR, CYREG_PRT3_DR +.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MISO__MASK, 0x10 +.set SD_MISO__PORT, 3 +.set SD_MISO__PRT, CYREG_PRT3_PRT +.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MISO__PS, CYREG_PRT3_PS +.set SD_MISO__SHIFT, 4 +.set SD_MISO__SLW, CYREG_PRT3_SLW + +/* SD_MOSI */ +.set SD_MOSI__0__MASK, 0x04 +.set SD_MOSI__0__PC, CYREG_PRT3_PC2 +.set SD_MOSI__0__PORT, 3 +.set SD_MOSI__0__SHIFT, 2 +.set SD_MOSI__AG, CYREG_PRT3_AG +.set SD_MOSI__AMUX, CYREG_PRT3_AMUX +.set SD_MOSI__BIE, CYREG_PRT3_BIE +.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MOSI__BYP, CYREG_PRT3_BYP +.set SD_MOSI__CTL, CYREG_PRT3_CTL +.set SD_MOSI__DM0, CYREG_PRT3_DM0 +.set SD_MOSI__DM1, CYREG_PRT3_DM1 +.set SD_MOSI__DM2, CYREG_PRT3_DM2 +.set SD_MOSI__DR, CYREG_PRT3_DR +.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MOSI__MASK, 0x04 +.set SD_MOSI__PORT, 3 +.set SD_MOSI__PRT, CYREG_PRT3_PRT +.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MOSI__PS, CYREG_PRT3_PS +.set SD_MOSI__SHIFT, 2 +.set SD_MOSI__SLW, CYREG_PRT3_SLW + +/* SD_SCK */ +.set SD_SCK__0__MASK, 0x08 +.set SD_SCK__0__PC, CYREG_PRT3_PC3 +.set SD_SCK__0__PORT, 3 +.set SD_SCK__0__SHIFT, 3 +.set SD_SCK__AG, CYREG_PRT3_AG +.set SD_SCK__AMUX, CYREG_PRT3_AMUX +.set SD_SCK__BIE, CYREG_PRT3_BIE +.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_SCK__BYP, CYREG_PRT3_BYP +.set SD_SCK__CTL, CYREG_PRT3_CTL +.set SD_SCK__DM0, CYREG_PRT3_DM0 +.set SD_SCK__DM1, CYREG_PRT3_DM1 +.set SD_SCK__DM2, CYREG_PRT3_DM2 +.set SD_SCK__DR, CYREG_PRT3_DR +.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_SCK__MASK, 0x08 +.set SD_SCK__PORT, 3 +.set SD_SCK__PRT, CYREG_PRT3_PRT +.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_SCK__PS, CYREG_PRT3_PS +.set SD_SCK__SHIFT, 3 +.set SD_SCK__SLW, CYREG_PRT3_SLW + +/* SD_CD */ +.set SD_CD__0__MASK, 0x40 +.set SD_CD__0__PC, CYREG_PRT3_PC6 +.set SD_CD__0__PORT, 3 +.set SD_CD__0__SHIFT, 6 +.set SD_CD__AG, CYREG_PRT3_AG +.set SD_CD__AMUX, CYREG_PRT3_AMUX +.set SD_CD__BIE, CYREG_PRT3_BIE +.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CD__BYP, CYREG_PRT3_BYP +.set SD_CD__CTL, CYREG_PRT3_CTL +.set SD_CD__DM0, CYREG_PRT3_DM0 +.set SD_CD__DM1, CYREG_PRT3_DM1 +.set SD_CD__DM2, CYREG_PRT3_DM2 +.set SD_CD__DR, CYREG_PRT3_DR +.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CD__MASK, 0x40 +.set SD_CD__PORT, 3 +.set SD_CD__PRT, CYREG_PRT3_PRT +.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CD__PS, CYREG_PRT3_PS +.set SD_CD__SHIFT, 6 +.set SD_CD__SLW, CYREG_PRT3_SLW + +/* SD_CS */ +.set SD_CS__0__MASK, 0x02 +.set SD_CS__0__PC, CYREG_PRT3_PC1 +.set SD_CS__0__PORT, 3 +.set SD_CS__0__SHIFT, 1 +.set SD_CS__AG, CYREG_PRT3_AG +.set SD_CS__AMUX, CYREG_PRT3_AMUX +.set SD_CS__BIE, CYREG_PRT3_BIE +.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CS__BYP, CYREG_PRT3_BYP +.set SD_CS__CTL, CYREG_PRT3_CTL +.set SD_CS__DM0, CYREG_PRT3_DM0 +.set SD_CS__DM1, CYREG_PRT3_DM1 +.set SD_CS__DM2, CYREG_PRT3_DM2 +.set SD_CS__DR, CYREG_PRT3_DR +.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CS__MASK, 0x02 +.set SD_CS__PORT, 3 +.set SD_CS__PRT, CYREG_PRT3_PRT +.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CS__PS, CYREG_PRT3_PS +.set SD_CS__SHIFT, 1 +.set SD_CS__SLW, CYREG_PRT3_SLW + +/* SD_WP */ +.set SD_WP__0__MASK, 0x80 +.set SD_WP__0__PC, CYREG_PRT3_PC7 +.set SD_WP__0__PORT, 3 +.set SD_WP__0__SHIFT, 7 +.set SD_WP__AG, CYREG_PRT3_AG +.set SD_WP__AMUX, CYREG_PRT3_AMUX +.set SD_WP__BIE, CYREG_PRT3_BIE +.set SD_WP__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_WP__BYP, CYREG_PRT3_BYP +.set SD_WP__CTL, CYREG_PRT3_CTL +.set SD_WP__DM0, CYREG_PRT3_DM0 +.set SD_WP__DM1, CYREG_PRT3_DM1 +.set SD_WP__DM2, CYREG_PRT3_DM2 +.set SD_WP__DR, CYREG_PRT3_DR +.set SD_WP__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_WP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_WP__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_WP__MASK, 0x80 +.set SD_WP__PORT, 3 +.set SD_WP__PRT, CYREG_PRT3_PRT +.set SD_WP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_WP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_WP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_WP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_WP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_WP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_WP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_WP__PS, CYREG_PRT3_PS +.set SD_WP__SHIFT, 7 +.set SD_WP__SLW, CYREG_PRT3_SLW + +/* LED1 */ +.set LED1__0__MASK, 0x08 +.set LED1__0__PC, CYREG_PRT12_PC3 +.set LED1__0__PORT, 12 +.set LED1__0__SHIFT, 3 +.set LED1__AG, CYREG_PRT12_AG +.set LED1__BIE, CYREG_PRT12_BIE +.set LED1__BIT_MASK, CYREG_PRT12_BIT_MASK +.set LED1__BYP, CYREG_PRT12_BYP +.set LED1__DM0, CYREG_PRT12_DM0 +.set LED1__DM1, CYREG_PRT12_DM1 +.set LED1__DM2, CYREG_PRT12_DM2 +.set LED1__DR, CYREG_PRT12_DR +.set LED1__INP_DIS, CYREG_PRT12_INP_DIS +.set LED1__MASK, 0x08 +.set LED1__PORT, 12 +.set LED1__PRT, CYREG_PRT12_PRT +.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set LED1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set LED1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set LED1__PS, CYREG_PRT12_PS +.set LED1__SHIFT, 3 +.set LED1__SIO_CFG, CYREG_PRT12_SIO_CFG +.set LED1__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set LED1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set LED1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set LED1__SLW, CYREG_PRT12_SLW + +/* Miscellaneous */ +/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ +.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6 +.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 +.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0 +.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1 +.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 +.set CYDEV_CHIP_MEMBER_5B, 4 +.set CYDEV_CHIP_FAMILY_PSOC5, 3 +.set CYDEV_CHIP_DIE_PSOC5LP, 4 +.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP +.set BCLK__BUS_CLK__HZ, 64000000 +.set BCLK__BUS_CLK__KHZ, 64000 +.set BCLK__BUS_CLK__MHZ, 64 +.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT +.set CYDEV_CHIP_DIE_LEOPARD, 1 +.set CYDEV_CHIP_DIE_PANTHER, 3 +.set CYDEV_CHIP_DIE_PSOC4A, 2 +.set CYDEV_CHIP_DIE_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_PSOC3, 1 +.set CYDEV_CHIP_FAMILY_PSOC4, 2 +.set CYDEV_CHIP_FAMILY_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 +.set CYDEV_CHIP_JTAG_ID, 0x2E12F069 +.set CYDEV_CHIP_MEMBER_3A, 1 +.set CYDEV_CHIP_MEMBER_4A, 2 +.set CYDEV_CHIP_MEMBER_5A, 3 +.set CYDEV_CHIP_MEMBER_UNKNOWN, 0 +.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B +.set CYDEV_CHIP_REVISION_3A_ES1, 0 +.set CYDEV_CHIP_REVISION_3A_ES2, 1 +.set CYDEV_CHIP_REVISION_3A_ES3, 3 +.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 +.set CYDEV_CHIP_REVISION_4A_ES0, 17 +.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_5A_ES0, 0 +.set CYDEV_CHIP_REVISION_5A_ES1, 1 +.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 +.set CYDEV_CHIP_REVISION_5B_ES0, 0 +.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION +.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION +.set CYDEV_CHIP_REV_LEOPARD_ES1, 0 +.set CYDEV_CHIP_REV_LEOPARD_ES2, 1 +.set CYDEV_CHIP_REV_LEOPARD_ES3, 3 +.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 +.set CYDEV_CHIP_REV_PANTHER_ES0, 0 +.set CYDEV_CHIP_REV_PANTHER_ES1, 1 +.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1 +.set CYDEV_CHIP_REV_PSOC4A_ES0, 17 +.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 +.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 +.set CYDEV_CONFIGURATION_COMPRESSED, 1 +.set CYDEV_CONFIGURATION_DMA, 0 +.set CYDEV_CONFIGURATION_ECC, 1 +.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED +.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED +.set CYDEV_CONFIGURATION_MODE_DMA, 2 +.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1 +.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn +.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1 +.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2 +.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV +.set CYDEV_DEBUGGING_DPS_Disable, 3 +.set CYDEV_DEBUGGING_DPS_JTAG_4, 1 +.set CYDEV_DEBUGGING_DPS_JTAG_5, 0 +.set CYDEV_DEBUGGING_DPS_SWD, 2 +.set CYDEV_DEBUGGING_ENABLE, 1 +.set CYDEV_DEBUGGING_REQXRES, 1 +.set CYDEV_DEBUGGING_XRES, 0 +.set CYDEV_DEBUG_ENABLE_MASK, 0x20 +.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG +.set CYDEV_DMA_CHANNELS_AVAILABLE, 24 +.set CYDEV_ECC_ENABLE, 0 +.set CYDEV_HEAP_SIZE, 0x1000 +.set CYDEV_INSTRUCT_CACHE_ENABLED, 1 +.set CYDEV_INTR_RISING, 0x00000003 +.set CYDEV_PROJ_TYPE, 0 +.set CYDEV_PROJ_TYPE_BOOTLOADER, 1 +.set CYDEV_PROJ_TYPE_LOADABLE, 2 +.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3 +.set CYDEV_PROJ_TYPE_STANDARD, 0 +.set CYDEV_PROTECTION_ENABLE, 0 +.set CYDEV_STACK_SIZE, 0x4000 +.set CYDEV_USE_BUNDLED_CMSIS, 1 +.set CYDEV_VARIABLE_VDDA, 0 +.set CYDEV_VDDA_MV, 5000 +.set CYDEV_VDDD_MV, 5000 +.set CYDEV_VDDIO0_MV, 5000 +.set CYDEV_VDDIO1_MV, 5000 +.set CYDEV_VDDIO2_MV, 5000 +.set CYDEV_VDDIO3_MV, 3300 +.set CYDEV_VIO0, 5 +.set CYDEV_VIO0_MV, 5000 +.set CYDEV_VIO1, 5 +.set CYDEV_VIO1_MV, 5000 +.set CYDEV_VIO2, 5 +.set CYDEV_VIO2_MV, 5000 +.set CYDEV_VIO3_MV, 3300 +.set DMA_CHANNELS_USED__MASK0, 0x00000000 +.set CYDEV_BOOTLOADER_ENABLE, 0 +.endif diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc new file mode 100644 index 0000000..3699982 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -0,0 +1,1868 @@ + IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC +INCLUDED_CYFITTERRV_INC EQU 1 + GET cydevicerv.inc + GET cydevicerv_trm.inc + +; SDCard_RxInternalInterrupt +SDCard_RxInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SDCard_RxInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SDCard_RxInternalInterrupt__INTC_MASK EQU 0x01 +SDCard_RxInternalInterrupt__INTC_NUMBER EQU 0 +SDCard_RxInternalInterrupt__INTC_PRIOR_NUM EQU 7 +SDCard_RxInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +SDCard_RxInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SDCard_RxInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SDCard_TxInternalInterrupt +SDCard_TxInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SDCard_TxInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SDCard_TxInternalInterrupt__INTC_MASK EQU 0x02 +SDCard_TxInternalInterrupt__INTC_NUMBER EQU 1 +SDCard_TxInternalInterrupt__INTC_PRIOR_NUM EQU 7 +SDCard_TxInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SDCard_TxInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SDCard_TxInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_Out_DBx +SCSI_Out_DBx__0__MASK EQU 0x01 +SCSI_Out_DBx__0__PC EQU CYREG_PRT0_PC0 +SCSI_Out_DBx__0__PORT EQU 0 +SCSI_Out_DBx__0__SHIFT EQU 0 +SCSI_Out_DBx__1__MASK EQU 0x02 +SCSI_Out_DBx__1__PC EQU CYREG_PRT0_PC1 +SCSI_Out_DBx__1__PORT EQU 0 +SCSI_Out_DBx__1__SHIFT EQU 1 +SCSI_Out_DBx__2__MASK EQU 0x04 +SCSI_Out_DBx__2__PC EQU CYREG_PRT0_PC2 +SCSI_Out_DBx__2__PORT EQU 0 +SCSI_Out_DBx__2__SHIFT EQU 2 +SCSI_Out_DBx__3__MASK EQU 0x08 +SCSI_Out_DBx__3__PC EQU CYREG_PRT0_PC3 +SCSI_Out_DBx__3__PORT EQU 0 +SCSI_Out_DBx__3__SHIFT EQU 3 +SCSI_Out_DBx__4__MASK EQU 0x10 +SCSI_Out_DBx__4__PC EQU CYREG_PRT0_PC4 +SCSI_Out_DBx__4__PORT EQU 0 +SCSI_Out_DBx__4__SHIFT EQU 4 +SCSI_Out_DBx__5__MASK EQU 0x20 +SCSI_Out_DBx__5__PC EQU CYREG_PRT0_PC5 +SCSI_Out_DBx__5__PORT EQU 0 +SCSI_Out_DBx__5__SHIFT EQU 5 +SCSI_Out_DBx__6__MASK EQU 0x40 +SCSI_Out_DBx__6__PC EQU CYREG_PRT0_PC6 +SCSI_Out_DBx__6__PORT EQU 0 +SCSI_Out_DBx__6__SHIFT EQU 6 +SCSI_Out_DBx__7__MASK EQU 0x80 +SCSI_Out_DBx__7__PC EQU CYREG_PRT0_PC7 +SCSI_Out_DBx__7__PORT EQU 0 +SCSI_Out_DBx__7__SHIFT EQU 7 +SCSI_Out_DBx__AG EQU CYREG_PRT0_AG +SCSI_Out_DBx__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out_DBx__BIE EQU CYREG_PRT0_BIE +SCSI_Out_DBx__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out_DBx__BYP EQU CYREG_PRT0_BYP +SCSI_Out_DBx__CTL EQU CYREG_PRT0_CTL +SCSI_Out_DBx__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out_DBx__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out_DBx__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out_DBx__DR EQU CYREG_PRT0_DR +SCSI_Out_DBx__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out_DBx__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out_DBx__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out_DBx__MASK EQU 0xFF +SCSI_Out_DBx__PORT EQU 0 +SCSI_Out_DBx__PRT EQU CYREG_PRT0_PRT +SCSI_Out_DBx__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out_DBx__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out_DBx__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out_DBx__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out_DBx__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out_DBx__PS EQU CYREG_PRT0_PS +SCSI_Out_DBx__SCSI_Out_DB0__MASK EQU 0x01 +SCSI_Out_DBx__SCSI_Out_DB0__PC EQU CYREG_PRT0_PC0 +SCSI_Out_DBx__SCSI_Out_DB0__PORT EQU 0 +SCSI_Out_DBx__SCSI_Out_DB0__SHIFT EQU 0 +SCSI_Out_DBx__SCSI_Out_DB1__MASK EQU 0x02 +SCSI_Out_DBx__SCSI_Out_DB1__PC EQU CYREG_PRT0_PC1 +SCSI_Out_DBx__SCSI_Out_DB1__PORT EQU 0 +SCSI_Out_DBx__SCSI_Out_DB1__SHIFT EQU 1 +SCSI_Out_DBx__SCSI_Out_DB2__MASK EQU 0x04 +SCSI_Out_DBx__SCSI_Out_DB2__PC EQU CYREG_PRT0_PC2 +SCSI_Out_DBx__SCSI_Out_DB2__PORT EQU 0 +SCSI_Out_DBx__SCSI_Out_DB2__SHIFT EQU 2 +SCSI_Out_DBx__SCSI_Out_DB3__MASK EQU 0x08 +SCSI_Out_DBx__SCSI_Out_DB3__PC EQU CYREG_PRT0_PC3 +SCSI_Out_DBx__SCSI_Out_DB3__PORT EQU 0 +SCSI_Out_DBx__SCSI_Out_DB3__SHIFT EQU 3 +SCSI_Out_DBx__SCSI_Out_DB4__MASK EQU 0x10 +SCSI_Out_DBx__SCSI_Out_DB4__PC EQU CYREG_PRT0_PC4 +SCSI_Out_DBx__SCSI_Out_DB4__PORT EQU 0 +SCSI_Out_DBx__SCSI_Out_DB4__SHIFT EQU 4 +SCSI_Out_DBx__SCSI_Out_DB5__MASK EQU 0x20 +SCSI_Out_DBx__SCSI_Out_DB5__PC EQU CYREG_PRT0_PC5 +SCSI_Out_DBx__SCSI_Out_DB5__PORT EQU 0 +SCSI_Out_DBx__SCSI_Out_DB5__SHIFT EQU 5 +SCSI_Out_DBx__SCSI_Out_DB6__MASK EQU 0x40 +SCSI_Out_DBx__SCSI_Out_DB6__PC EQU CYREG_PRT0_PC6 +SCSI_Out_DBx__SCSI_Out_DB6__PORT EQU 0 +SCSI_Out_DBx__SCSI_Out_DB6__SHIFT EQU 6 +SCSI_Out_DBx__SCSI_Out_DB7__MASK EQU 0x80 +SCSI_Out_DBx__SCSI_Out_DB7__PC EQU CYREG_PRT0_PC7 +SCSI_Out_DBx__SCSI_Out_DB7__PORT EQU 0 +SCSI_Out_DBx__SCSI_Out_DB7__SHIFT EQU 7 +SCSI_Out_DBx__SHIFT EQU 0 +SCSI_Out_DBx__SLW EQU CYREG_PRT0_SLW + +; SDCard_BSPIM +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB07_08_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB07_08_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB07_08_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB07_08_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB07_08_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB07_08_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB07_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB07_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB07_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB07_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB07_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB07_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB07_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB07_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB07_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL + +; SCSI_In_DBx +SCSI_In_DBx__0__MASK EQU 0x01 +SCSI_In_DBx__0__PC EQU CYREG_PRT2_PC0 +SCSI_In_DBx__0__PORT EQU 2 +SCSI_In_DBx__0__SHIFT EQU 0 +SCSI_In_DBx__1__MASK EQU 0x02 +SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC1 +SCSI_In_DBx__1__PORT EQU 2 +SCSI_In_DBx__1__SHIFT EQU 1 +SCSI_In_DBx__2__MASK EQU 0x04 +SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC2 +SCSI_In_DBx__2__PORT EQU 2 +SCSI_In_DBx__2__SHIFT EQU 2 +SCSI_In_DBx__3__MASK EQU 0x08 +SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC3 +SCSI_In_DBx__3__PORT EQU 2 +SCSI_In_DBx__3__SHIFT EQU 3 +SCSI_In_DBx__4__MASK EQU 0x10 +SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4 +SCSI_In_DBx__4__PORT EQU 2 +SCSI_In_DBx__4__SHIFT EQU 4 +SCSI_In_DBx__5__MASK EQU 0x20 +SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC5 +SCSI_In_DBx__5__PORT EQU 2 +SCSI_In_DBx__5__SHIFT EQU 5 +SCSI_In_DBx__6__MASK EQU 0x40 +SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC6 +SCSI_In_DBx__6__PORT EQU 2 +SCSI_In_DBx__6__SHIFT EQU 6 +SCSI_In_DBx__7__MASK EQU 0x80 +SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC7 +SCSI_In_DBx__7__PORT EQU 2 +SCSI_In_DBx__7__SHIFT EQU 7 +SCSI_In_DBx__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__MASK EQU 0xFF +SCSI_In_DBx__PORT EQU 2 +SCSI_In_DBx__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__SCSI_Out_DB0__MASK EQU 0x01 +SCSI_In_DBx__SCSI_Out_DB0__PC EQU CYREG_PRT2_PC0 +SCSI_In_DBx__SCSI_Out_DB0__PORT EQU 2 +SCSI_In_DBx__SCSI_Out_DB0__SHIFT EQU 0 +SCSI_In_DBx__SCSI_Out_DB1__MASK EQU 0x02 +SCSI_In_DBx__SCSI_Out_DB1__PC EQU CYREG_PRT2_PC1 +SCSI_In_DBx__SCSI_Out_DB1__PORT EQU 2 +SCSI_In_DBx__SCSI_Out_DB1__SHIFT EQU 1 +SCSI_In_DBx__SCSI_Out_DB2__MASK EQU 0x04 +SCSI_In_DBx__SCSI_Out_DB2__PC EQU CYREG_PRT2_PC2 +SCSI_In_DBx__SCSI_Out_DB2__PORT EQU 2 +SCSI_In_DBx__SCSI_Out_DB2__SHIFT EQU 2 +SCSI_In_DBx__SCSI_Out_DB3__MASK EQU 0x08 +SCSI_In_DBx__SCSI_Out_DB3__PC EQU CYREG_PRT2_PC3 +SCSI_In_DBx__SCSI_Out_DB3__PORT EQU 2 +SCSI_In_DBx__SCSI_Out_DB3__SHIFT EQU 3 +SCSI_In_DBx__SCSI_Out_DB4__MASK EQU 0x10 +SCSI_In_DBx__SCSI_Out_DB4__PC EQU CYREG_PRT2_PC4 +SCSI_In_DBx__SCSI_Out_DB4__PORT EQU 2 +SCSI_In_DBx__SCSI_Out_DB4__SHIFT EQU 4 +SCSI_In_DBx__SCSI_Out_DB5__MASK EQU 0x20 +SCSI_In_DBx__SCSI_Out_DB5__PC EQU CYREG_PRT2_PC5 +SCSI_In_DBx__SCSI_Out_DB5__PORT EQU 2 +SCSI_In_DBx__SCSI_Out_DB5__SHIFT EQU 5 +SCSI_In_DBx__SCSI_Out_DB6__MASK EQU 0x40 +SCSI_In_DBx__SCSI_Out_DB6__PC EQU CYREG_PRT2_PC6 +SCSI_In_DBx__SCSI_Out_DB6__PORT EQU 2 +SCSI_In_DBx__SCSI_Out_DB6__SHIFT EQU 6 +SCSI_In_DBx__SCSI_Out_DB7__MASK EQU 0x80 +SCSI_In_DBx__SCSI_Out_DB7__PC EQU CYREG_PRT2_PC7 +SCSI_In_DBx__SCSI_Out_DB7__PORT EQU 2 +SCSI_In_DBx__SCSI_Out_DB7__SHIFT EQU 7 +SCSI_In_DBx__SHIFT EQU 0 +SCSI_In_DBx__SLW EQU CYREG_PRT2_SLW + +; SD_Data_Clk +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 + +; SD_Init_Clk +SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Init_Clk__INDEX EQU 0x01 +SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Init_Clk__PM_ACT_MSK EQU 0x02 +SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Init_Clk__PM_STBY_MSK EQU 0x02 + +; SD_Clk_Ctl +SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB05_MSK +SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL + +; PARITY_EN +PARITY_EN__0__MASK EQU 0x10 +PARITY_EN__0__PC EQU CYREG_PRT5_PC4 +PARITY_EN__0__PORT EQU 5 +PARITY_EN__0__SHIFT EQU 4 +PARITY_EN__AG EQU CYREG_PRT5_AG +PARITY_EN__AMUX EQU CYREG_PRT5_AMUX +PARITY_EN__BIE EQU CYREG_PRT5_BIE +PARITY_EN__BIT_MASK EQU CYREG_PRT5_BIT_MASK +PARITY_EN__BYP EQU CYREG_PRT5_BYP +PARITY_EN__CTL EQU CYREG_PRT5_CTL +PARITY_EN__DM0 EQU CYREG_PRT5_DM0 +PARITY_EN__DM1 EQU CYREG_PRT5_DM1 +PARITY_EN__DM2 EQU CYREG_PRT5_DM2 +PARITY_EN__DR EQU CYREG_PRT5_DR +PARITY_EN__INP_DIS EQU CYREG_PRT5_INP_DIS +PARITY_EN__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +PARITY_EN__LCD_EN EQU CYREG_PRT5_LCD_EN +PARITY_EN__MASK EQU 0x10 +PARITY_EN__PORT EQU 5 +PARITY_EN__PRT EQU CYREG_PRT5_PRT +PARITY_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +PARITY_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +PARITY_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +PARITY_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +PARITY_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +PARITY_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +PARITY_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +PARITY_EN__PS EQU CYREG_PRT5_PS +PARITY_EN__SHIFT EQU 4 +PARITY_EN__SLW EQU CYREG_PRT5_SLW + +; SCSI_Out +SCSI_Out__0__AG EQU CYREG_PRT4_AG +SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__0__BIE EQU CYREG_PRT4_BIE +SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__0__BYP EQU CYREG_PRT4_BYP +SCSI_Out__0__CTL EQU CYREG_PRT4_CTL +SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__0__DR EQU CYREG_PRT4_DR +SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__0__MASK EQU 0x04 +SCSI_Out__0__PC EQU CYREG_PRT4_PC2 +SCSI_Out__0__PORT EQU 4 +SCSI_Out__0__PRT EQU CYREG_PRT4_PRT +SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__0__PS EQU CYREG_PRT4_PS +SCSI_Out__0__SHIFT EQU 2 +SCSI_Out__0__SLW EQU CYREG_PRT4_SLW +SCSI_Out__1__AG EQU CYREG_PRT4_AG +SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__1__BIE EQU CYREG_PRT4_BIE +SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__1__BYP EQU CYREG_PRT4_BYP +SCSI_Out__1__CTL EQU CYREG_PRT4_CTL +SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__1__DR EQU CYREG_PRT4_DR +SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__1__MASK EQU 0x08 +SCSI_Out__1__PC EQU CYREG_PRT4_PC3 +SCSI_Out__1__PORT EQU 4 +SCSI_Out__1__PRT EQU CYREG_PRT4_PRT +SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__1__PS EQU CYREG_PRT4_PS +SCSI_Out__1__SHIFT EQU 3 +SCSI_Out__1__SLW EQU CYREG_PRT4_SLW +SCSI_Out__2__AG EQU CYREG_PRT4_AG +SCSI_Out__2__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__2__BIE EQU CYREG_PRT4_BIE +SCSI_Out__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__2__BYP EQU CYREG_PRT4_BYP +SCSI_Out__2__CTL EQU CYREG_PRT4_CTL +SCSI_Out__2__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__2__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__2__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__2__DR EQU CYREG_PRT4_DR +SCSI_Out__2__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__2__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__2__MASK EQU 0x10 +SCSI_Out__2__PC EQU CYREG_PRT4_PC4 +SCSI_Out__2__PORT EQU 4 +SCSI_Out__2__PRT EQU CYREG_PRT4_PRT +SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__2__PS EQU CYREG_PRT4_PS +SCSI_Out__2__SHIFT EQU 4 +SCSI_Out__2__SLW EQU CYREG_PRT4_SLW +SCSI_Out__3__AG EQU CYREG_PRT4_AG +SCSI_Out__3__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__3__BIE EQU CYREG_PRT4_BIE +SCSI_Out__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__3__BYP EQU CYREG_PRT4_BYP +SCSI_Out__3__CTL EQU CYREG_PRT4_CTL +SCSI_Out__3__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__3__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__3__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__3__DR EQU CYREG_PRT4_DR +SCSI_Out__3__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__3__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__3__MASK EQU 0x20 +SCSI_Out__3__PC EQU CYREG_PRT4_PC5 +SCSI_Out__3__PORT EQU 4 +SCSI_Out__3__PRT EQU CYREG_PRT4_PRT +SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__3__PS EQU CYREG_PRT4_PS +SCSI_Out__3__SHIFT EQU 5 +SCSI_Out__3__SLW EQU CYREG_PRT4_SLW +SCSI_Out__4__AG EQU CYREG_PRT4_AG +SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__4__BIE EQU CYREG_PRT4_BIE +SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__4__BYP EQU CYREG_PRT4_BYP +SCSI_Out__4__CTL EQU CYREG_PRT4_CTL +SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__4__DR EQU CYREG_PRT4_DR +SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__4__MASK EQU 0x40 +SCSI_Out__4__PC EQU CYREG_PRT4_PC6 +SCSI_Out__4__PORT EQU 4 +SCSI_Out__4__PRT EQU CYREG_PRT4_PRT +SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__4__PS EQU CYREG_PRT4_PS +SCSI_Out__4__SHIFT EQU 6 +SCSI_Out__4__SLW EQU CYREG_PRT4_SLW +SCSI_Out__5__AG EQU CYREG_PRT4_AG +SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__5__BIE EQU CYREG_PRT4_BIE +SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__5__BYP EQU CYREG_PRT4_BYP +SCSI_Out__5__CTL EQU CYREG_PRT4_CTL +SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__5__DR EQU CYREG_PRT4_DR +SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__5__MASK EQU 0x80 +SCSI_Out__5__PC EQU CYREG_PRT4_PC7 +SCSI_Out__5__PORT EQU 4 +SCSI_Out__5__PRT EQU CYREG_PRT4_PRT +SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__5__PS EQU CYREG_PRT4_PS +SCSI_Out__5__SHIFT EQU 7 +SCSI_Out__5__SLW EQU CYREG_PRT4_SLW +SCSI_Out__6__AG EQU CYREG_PRT6_AG +SCSI_Out__6__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__6__BIE EQU CYREG_PRT6_BIE +SCSI_Out__6__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__6__BYP EQU CYREG_PRT6_BYP +SCSI_Out__6__CTL EQU CYREG_PRT6_CTL +SCSI_Out__6__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__6__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__6__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__6__DR EQU CYREG_PRT6_DR +SCSI_Out__6__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__6__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__6__MASK EQU 0x01 +SCSI_Out__6__PC EQU CYREG_PRT6_PC0 +SCSI_Out__6__PORT EQU 6 +SCSI_Out__6__PRT EQU CYREG_PRT6_PRT +SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__6__PS EQU CYREG_PRT6_PS +SCSI_Out__6__SHIFT EQU 0 +SCSI_Out__6__SLW EQU CYREG_PRT6_SLW +SCSI_Out__7__AG EQU CYREG_PRT6_AG +SCSI_Out__7__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__7__BIE EQU CYREG_PRT6_BIE +SCSI_Out__7__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__7__BYP EQU CYREG_PRT6_BYP +SCSI_Out__7__CTL EQU CYREG_PRT6_CTL +SCSI_Out__7__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__7__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__7__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__7__DR EQU CYREG_PRT6_DR +SCSI_Out__7__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__7__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__7__MASK EQU 0x02 +SCSI_Out__7__PC EQU CYREG_PRT6_PC1 +SCSI_Out__7__PORT EQU 6 +SCSI_Out__7__PRT EQU CYREG_PRT6_PRT +SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__7__PS EQU CYREG_PRT6_PS +SCSI_Out__7__SHIFT EQU 1 +SCSI_Out__7__SLW EQU CYREG_PRT6_SLW +SCSI_Out__8__AG EQU CYREG_PRT6_AG +SCSI_Out__8__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__8__BIE EQU CYREG_PRT6_BIE +SCSI_Out__8__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__8__BYP EQU CYREG_PRT6_BYP +SCSI_Out__8__CTL EQU CYREG_PRT6_CTL +SCSI_Out__8__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__8__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__8__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__8__DR EQU CYREG_PRT6_DR +SCSI_Out__8__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__8__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__8__MASK EQU 0x04 +SCSI_Out__8__PC EQU CYREG_PRT6_PC2 +SCSI_Out__8__PORT EQU 6 +SCSI_Out__8__PRT EQU CYREG_PRT6_PRT +SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__8__PS EQU CYREG_PRT6_PS +SCSI_Out__8__SHIFT EQU 2 +SCSI_Out__8__SLW EQU CYREG_PRT6_SLW +SCSI_Out__9__AG EQU CYREG_PRT6_AG +SCSI_Out__9__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__9__BIE EQU CYREG_PRT6_BIE +SCSI_Out__9__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__9__BYP EQU CYREG_PRT6_BYP +SCSI_Out__9__CTL EQU CYREG_PRT6_CTL +SCSI_Out__9__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__9__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__9__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__9__DR EQU CYREG_PRT6_DR +SCSI_Out__9__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__9__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__9__MASK EQU 0x08 +SCSI_Out__9__PC EQU CYREG_PRT6_PC3 +SCSI_Out__9__PORT EQU 6 +SCSI_Out__9__PRT EQU CYREG_PRT6_PRT +SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__9__PS EQU CYREG_PRT6_PS +SCSI_Out__9__SHIFT EQU 3 +SCSI_Out__9__SLW EQU CYREG_PRT6_SLW +SCSI_Out__ACK__AG EQU CYREG_PRT4_AG +SCSI_Out__ACK__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__ACK__BIE EQU CYREG_PRT4_BIE +SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__ACK__BYP EQU CYREG_PRT4_BYP +SCSI_Out__ACK__CTL EQU CYREG_PRT4_CTL +SCSI_Out__ACK__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__ACK__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__ACK__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__ACK__DR EQU CYREG_PRT4_DR +SCSI_Out__ACK__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__ACK__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__ACK__MASK EQU 0x20 +SCSI_Out__ACK__PC EQU CYREG_PRT4_PC5 +SCSI_Out__ACK__PORT EQU 4 +SCSI_Out__ACK__PRT EQU CYREG_PRT4_PRT +SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__ACK__PS EQU CYREG_PRT4_PS +SCSI_Out__ACK__SHIFT EQU 5 +SCSI_Out__ACK__SLW EQU CYREG_PRT4_SLW +SCSI_Out__ATN__AG EQU CYREG_PRT4_AG +SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE +SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP +SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL +SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__ATN__DR EQU CYREG_PRT4_DR +SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__ATN__MASK EQU 0x08 +SCSI_Out__ATN__PC EQU CYREG_PRT4_PC3 +SCSI_Out__ATN__PORT EQU 4 +SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT +SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__ATN__PS EQU CYREG_PRT4_PS +SCSI_Out__ATN__SHIFT EQU 3 +SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW +SCSI_Out__BSY__AG EQU CYREG_PRT4_AG +SCSI_Out__BSY__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__BSY__BIE EQU CYREG_PRT4_BIE +SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__BSY__BYP EQU CYREG_PRT4_BYP +SCSI_Out__BSY__CTL EQU CYREG_PRT4_CTL +SCSI_Out__BSY__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__BSY__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__BSY__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__BSY__DR EQU CYREG_PRT4_DR +SCSI_Out__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__BSY__MASK EQU 0x10 +SCSI_Out__BSY__PC EQU CYREG_PRT4_PC4 +SCSI_Out__BSY__PORT EQU 4 +SCSI_Out__BSY__PRT EQU CYREG_PRT4_PRT +SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__BSY__PS EQU CYREG_PRT4_PS +SCSI_Out__BSY__SHIFT EQU 4 +SCSI_Out__BSY__SLW EQU CYREG_PRT4_SLW +SCSI_Out__CD__AG EQU CYREG_PRT6_AG +SCSI_Out__CD__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__CD__BIE EQU CYREG_PRT6_BIE +SCSI_Out__CD__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__CD__BYP EQU CYREG_PRT6_BYP +SCSI_Out__CD__CTL EQU CYREG_PRT6_CTL +SCSI_Out__CD__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__CD__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__CD__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__CD__DR EQU CYREG_PRT6_DR +SCSI_Out__CD__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__CD__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__CD__MASK EQU 0x02 +SCSI_Out__CD__PC EQU CYREG_PRT6_PC1 +SCSI_Out__CD__PORT EQU 6 +SCSI_Out__CD__PRT EQU CYREG_PRT6_PRT +SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__CD__PS EQU CYREG_PRT6_PS +SCSI_Out__CD__SHIFT EQU 1 +SCSI_Out__CD__SLW EQU CYREG_PRT6_SLW +SCSI_Out__DBP__AG EQU CYREG_PRT4_AG +SCSI_Out__DBP__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__DBP__BIE EQU CYREG_PRT4_BIE +SCSI_Out__DBP__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__DBP__BYP EQU CYREG_PRT4_BYP +SCSI_Out__DBP__CTL EQU CYREG_PRT4_CTL +SCSI_Out__DBP__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__DBP__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__DBP__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__DBP__DR EQU CYREG_PRT4_DR +SCSI_Out__DBP__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__DBP__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__DBP__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__DBP__MASK EQU 0x04 +SCSI_Out__DBP__PC EQU CYREG_PRT4_PC2 +SCSI_Out__DBP__PORT EQU 4 +SCSI_Out__DBP__PRT EQU CYREG_PRT4_PRT +SCSI_Out__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__DBP__PS EQU CYREG_PRT4_PS +SCSI_Out__DBP__SHIFT EQU 2 +SCSI_Out__DBP__SLW EQU CYREG_PRT4_SLW +SCSI_Out__IO__AG EQU CYREG_PRT6_AG +SCSI_Out__IO__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__IO__BIE EQU CYREG_PRT6_BIE +SCSI_Out__IO__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__IO__BYP EQU CYREG_PRT6_BYP +SCSI_Out__IO__CTL EQU CYREG_PRT6_CTL +SCSI_Out__IO__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__IO__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__IO__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__IO__DR EQU CYREG_PRT6_DR +SCSI_Out__IO__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__IO__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__IO__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__IO__MASK EQU 0x08 +SCSI_Out__IO__PC EQU CYREG_PRT6_PC3 +SCSI_Out__IO__PORT EQU 6 +SCSI_Out__IO__PRT EQU CYREG_PRT6_PRT +SCSI_Out__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__IO__PS EQU CYREG_PRT6_PS +SCSI_Out__IO__SHIFT EQU 3 +SCSI_Out__IO__SLW EQU CYREG_PRT6_SLW +SCSI_Out__MSG__AG EQU CYREG_PRT4_AG +SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE +SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__MSG__BYP EQU CYREG_PRT4_BYP +SCSI_Out__MSG__CTL EQU CYREG_PRT4_CTL +SCSI_Out__MSG__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__MSG__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__MSG__DR EQU CYREG_PRT4_DR +SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__MSG__MASK EQU 0x80 +SCSI_Out__MSG__PC EQU CYREG_PRT4_PC7 +SCSI_Out__MSG__PORT EQU 4 +SCSI_Out__MSG__PRT EQU CYREG_PRT4_PRT +SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__MSG__PS EQU CYREG_PRT4_PS +SCSI_Out__MSG__SHIFT EQU 7 +SCSI_Out__MSG__SLW EQU CYREG_PRT4_SLW +SCSI_Out__REQ__AG EQU CYREG_PRT6_AG +SCSI_Out__REQ__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__REQ__BIE EQU CYREG_PRT6_BIE +SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__REQ__BYP EQU CYREG_PRT6_BYP +SCSI_Out__REQ__CTL EQU CYREG_PRT6_CTL +SCSI_Out__REQ__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__REQ__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__REQ__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__REQ__DR EQU CYREG_PRT6_DR +SCSI_Out__REQ__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__REQ__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__REQ__MASK EQU 0x04 +SCSI_Out__REQ__PC EQU CYREG_PRT6_PC2 +SCSI_Out__REQ__PORT EQU 6 +SCSI_Out__REQ__PRT EQU CYREG_PRT6_PRT +SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__REQ__PS EQU CYREG_PRT6_PS +SCSI_Out__REQ__SHIFT EQU 2 +SCSI_Out__REQ__SLW EQU CYREG_PRT6_SLW +SCSI_Out__RST__AG EQU CYREG_PRT4_AG +SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE +SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP +SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL +SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__RST__DR EQU CYREG_PRT4_DR +SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__RST__MASK EQU 0x40 +SCSI_Out__RST__PC EQU CYREG_PRT4_PC6 +SCSI_Out__RST__PORT EQU 4 +SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT +SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__RST__PS EQU CYREG_PRT4_PS +SCSI_Out__RST__SHIFT EQU 6 +SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW +SCSI_Out__SEL__AG EQU CYREG_PRT6_AG +SCSI_Out__SEL__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__SEL__BIE EQU CYREG_PRT6_BIE +SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__SEL__BYP EQU CYREG_PRT6_BYP +SCSI_Out__SEL__CTL EQU CYREG_PRT6_CTL +SCSI_Out__SEL__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__SEL__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__SEL__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__SEL__DR EQU CYREG_PRT6_DR +SCSI_Out__SEL__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__SEL__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__SEL__MASK EQU 0x01 +SCSI_Out__SEL__PC EQU CYREG_PRT6_PC0 +SCSI_Out__SEL__PORT EQU 6 +SCSI_Out__SEL__PRT EQU CYREG_PRT6_PRT +SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__SEL__PS EQU CYREG_PRT6_PS +SCSI_Out__SEL__SHIFT EQU 0 +SCSI_Out__SEL__SLW EQU CYREG_PRT6_SLW + +; SCSI_ID +SCSI_ID__0__MASK EQU 0x80 +SCSI_ID__0__PC EQU CYREG_PRT5_PC7 +SCSI_ID__0__PORT EQU 5 +SCSI_ID__0__SHIFT EQU 7 +SCSI_ID__1__MASK EQU 0x40 +SCSI_ID__1__PC EQU CYREG_PRT5_PC6 +SCSI_ID__1__PORT EQU 5 +SCSI_ID__1__SHIFT EQU 6 +SCSI_ID__2__MASK EQU 0x20 +SCSI_ID__2__PC EQU CYREG_PRT5_PC5 +SCSI_ID__2__PORT EQU 5 +SCSI_ID__2__SHIFT EQU 5 +SCSI_ID__AG EQU CYREG_PRT5_AG +SCSI_ID__AMUX EQU CYREG_PRT5_AMUX +SCSI_ID__BIE EQU CYREG_PRT5_BIE +SCSI_ID__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_ID__BYP EQU CYREG_PRT5_BYP +SCSI_ID__CTL EQU CYREG_PRT5_CTL +SCSI_ID__DM0 EQU CYREG_PRT5_DM0 +SCSI_ID__DM1 EQU CYREG_PRT5_DM1 +SCSI_ID__DM2 EQU CYREG_PRT5_DM2 +SCSI_ID__DR EQU CYREG_PRT5_DR +SCSI_ID__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_ID__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_ID__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_ID__PORT EQU 5 +SCSI_ID__PRT EQU CYREG_PRT5_PRT +SCSI_ID__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_ID__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_ID__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_ID__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_ID__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_ID__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_ID__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_ID__PS EQU CYREG_PRT5_PS +SCSI_ID__SLW EQU CYREG_PRT5_SLW + +; SCSI_In +SCSI_In__0__AG EQU CYREG_PRT12_AG +SCSI_In__0__BIE EQU CYREG_PRT12_BIE +SCSI_In__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In__0__BYP EQU CYREG_PRT12_BYP +SCSI_In__0__DM0 EQU CYREG_PRT12_DM0 +SCSI_In__0__DM1 EQU CYREG_PRT12_DM1 +SCSI_In__0__DM2 EQU CYREG_PRT12_DM2 +SCSI_In__0__DR EQU CYREG_PRT12_DR +SCSI_In__0__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In__0__MASK EQU 0x10 +SCSI_In__0__PC EQU CYREG_PRT12_PC4 +SCSI_In__0__PORT EQU 12 +SCSI_In__0__PRT EQU CYREG_PRT12_PRT +SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In__0__PS EQU CYREG_PRT12_PS +SCSI_In__0__SHIFT EQU 4 +SCSI_In__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In__0__SLW EQU CYREG_PRT12_SLW +SCSI_In__1__AG EQU CYREG_PRT12_AG +SCSI_In__1__BIE EQU CYREG_PRT12_BIE +SCSI_In__1__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In__1__BYP EQU CYREG_PRT12_BYP +SCSI_In__1__DM0 EQU CYREG_PRT12_DM0 +SCSI_In__1__DM1 EQU CYREG_PRT12_DM1 +SCSI_In__1__DM2 EQU CYREG_PRT12_DM2 +SCSI_In__1__DR EQU CYREG_PRT12_DR +SCSI_In__1__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In__1__MASK EQU 0x20 +SCSI_In__1__PC EQU CYREG_PRT12_PC5 +SCSI_In__1__PORT EQU 12 +SCSI_In__1__PRT EQU CYREG_PRT12_PRT +SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In__1__PS EQU CYREG_PRT12_PS +SCSI_In__1__SHIFT EQU 5 +SCSI_In__1__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In__1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In__1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In__1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In__1__SLW EQU CYREG_PRT12_SLW +SCSI_In__2__AG EQU CYREG_PRT6_AG +SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__2__BIE EQU CYREG_PRT6_BIE +SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__2__BYP EQU CYREG_PRT6_BYP +SCSI_In__2__CTL EQU CYREG_PRT6_CTL +SCSI_In__2__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__2__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__2__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__2__DR EQU CYREG_PRT6_DR +SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__2__MASK EQU 0x10 +SCSI_In__2__PC EQU CYREG_PRT6_PC4 +SCSI_In__2__PORT EQU 6 +SCSI_In__2__PRT EQU CYREG_PRT6_PRT +SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__2__PS EQU CYREG_PRT6_PS +SCSI_In__2__SHIFT EQU 4 +SCSI_In__2__SLW EQU CYREG_PRT6_SLW +SCSI_In__3__AG EQU CYREG_PRT6_AG +SCSI_In__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__3__BIE EQU CYREG_PRT6_BIE +SCSI_In__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__3__BYP EQU CYREG_PRT6_BYP +SCSI_In__3__CTL EQU CYREG_PRT6_CTL +SCSI_In__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__3__DR EQU CYREG_PRT6_DR +SCSI_In__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__3__MASK EQU 0x20 +SCSI_In__3__PC EQU CYREG_PRT6_PC5 +SCSI_In__3__PORT EQU 6 +SCSI_In__3__PRT EQU CYREG_PRT6_PRT +SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__3__PS EQU CYREG_PRT6_PS +SCSI_In__3__SHIFT EQU 5 +SCSI_In__3__SLW EQU CYREG_PRT6_SLW +SCSI_In__4__AG EQU CYREG_PRT6_AG +SCSI_In__4__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__4__BIE EQU CYREG_PRT6_BIE +SCSI_In__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__4__BYP EQU CYREG_PRT6_BYP +SCSI_In__4__CTL EQU CYREG_PRT6_CTL +SCSI_In__4__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__4__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__4__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__4__DR EQU CYREG_PRT6_DR +SCSI_In__4__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__4__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__4__MASK EQU 0x40 +SCSI_In__4__PC EQU CYREG_PRT6_PC6 +SCSI_In__4__PORT EQU 6 +SCSI_In__4__PRT EQU CYREG_PRT6_PRT +SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__4__PS EQU CYREG_PRT6_PS +SCSI_In__4__SHIFT EQU 6 +SCSI_In__4__SLW EQU CYREG_PRT6_SLW +SCSI_In__5__AG EQU CYREG_PRT6_AG +SCSI_In__5__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__5__BIE EQU CYREG_PRT6_BIE +SCSI_In__5__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__5__BYP EQU CYREG_PRT6_BYP +SCSI_In__5__CTL EQU CYREG_PRT6_CTL +SCSI_In__5__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__5__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__5__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__5__DR EQU CYREG_PRT6_DR +SCSI_In__5__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__5__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__5__MASK EQU 0x80 +SCSI_In__5__PC EQU CYREG_PRT6_PC7 +SCSI_In__5__PORT EQU 6 +SCSI_In__5__PRT EQU CYREG_PRT6_PRT +SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__5__PS EQU CYREG_PRT6_PS +SCSI_In__5__SHIFT EQU 7 +SCSI_In__5__SLW EQU CYREG_PRT6_SLW +SCSI_In__6__AG EQU CYREG_PRT5_AG +SCSI_In__6__AMUX EQU CYREG_PRT5_AMUX +SCSI_In__6__BIE EQU CYREG_PRT5_BIE +SCSI_In__6__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In__6__BYP EQU CYREG_PRT5_BYP +SCSI_In__6__CTL EQU CYREG_PRT5_CTL +SCSI_In__6__DM0 EQU CYREG_PRT5_DM0 +SCSI_In__6__DM1 EQU CYREG_PRT5_DM1 +SCSI_In__6__DM2 EQU CYREG_PRT5_DM2 +SCSI_In__6__DR EQU CYREG_PRT5_DR +SCSI_In__6__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In__6__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In__6__MASK EQU 0x01 +SCSI_In__6__PC EQU CYREG_PRT5_PC0 +SCSI_In__6__PORT EQU 5 +SCSI_In__6__PRT EQU CYREG_PRT5_PRT +SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In__6__PS EQU CYREG_PRT5_PS +SCSI_In__6__SHIFT EQU 0 +SCSI_In__6__SLW EQU CYREG_PRT5_SLW +SCSI_In__7__AG EQU CYREG_PRT5_AG +SCSI_In__7__AMUX EQU CYREG_PRT5_AMUX +SCSI_In__7__BIE EQU CYREG_PRT5_BIE +SCSI_In__7__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In__7__BYP EQU CYREG_PRT5_BYP +SCSI_In__7__CTL EQU CYREG_PRT5_CTL +SCSI_In__7__DM0 EQU CYREG_PRT5_DM0 +SCSI_In__7__DM1 EQU CYREG_PRT5_DM1 +SCSI_In__7__DM2 EQU CYREG_PRT5_DM2 +SCSI_In__7__DR EQU CYREG_PRT5_DR +SCSI_In__7__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In__7__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In__7__MASK EQU 0x02 +SCSI_In__7__PC EQU CYREG_PRT5_PC1 +SCSI_In__7__PORT EQU 5 +SCSI_In__7__PRT EQU CYREG_PRT5_PRT +SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In__7__PS EQU CYREG_PRT5_PS +SCSI_In__7__SHIFT EQU 1 +SCSI_In__7__SLW EQU CYREG_PRT5_SLW +SCSI_In__8__AG EQU CYREG_PRT5_AG +SCSI_In__8__AMUX EQU CYREG_PRT5_AMUX +SCSI_In__8__BIE EQU CYREG_PRT5_BIE +SCSI_In__8__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In__8__BYP EQU CYREG_PRT5_BYP +SCSI_In__8__CTL EQU CYREG_PRT5_CTL +SCSI_In__8__DM0 EQU CYREG_PRT5_DM0 +SCSI_In__8__DM1 EQU CYREG_PRT5_DM1 +SCSI_In__8__DM2 EQU CYREG_PRT5_DM2 +SCSI_In__8__DR EQU CYREG_PRT5_DR +SCSI_In__8__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In__8__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In__8__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In__8__MASK EQU 0x04 +SCSI_In__8__PC EQU CYREG_PRT5_PC2 +SCSI_In__8__PORT EQU 5 +SCSI_In__8__PRT EQU CYREG_PRT5_PRT +SCSI_In__8__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In__8__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In__8__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In__8__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In__8__PS EQU CYREG_PRT5_PS +SCSI_In__8__SHIFT EQU 2 +SCSI_In__8__SLW EQU CYREG_PRT5_SLW +SCSI_In__9__AG EQU CYREG_PRT5_AG +SCSI_In__9__AMUX EQU CYREG_PRT5_AMUX +SCSI_In__9__BIE EQU CYREG_PRT5_BIE +SCSI_In__9__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In__9__BYP EQU CYREG_PRT5_BYP +SCSI_In__9__CTL EQU CYREG_PRT5_CTL +SCSI_In__9__DM0 EQU CYREG_PRT5_DM0 +SCSI_In__9__DM1 EQU CYREG_PRT5_DM1 +SCSI_In__9__DM2 EQU CYREG_PRT5_DM2 +SCSI_In__9__DR EQU CYREG_PRT5_DR +SCSI_In__9__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In__9__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In__9__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In__9__MASK EQU 0x08 +SCSI_In__9__PC EQU CYREG_PRT5_PC3 +SCSI_In__9__PORT EQU 5 +SCSI_In__9__PRT EQU CYREG_PRT5_PRT +SCSI_In__9__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In__9__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In__9__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In__9__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In__9__PS EQU CYREG_PRT5_PS +SCSI_In__9__SHIFT EQU 3 +SCSI_In__9__SLW EQU CYREG_PRT5_SLW +SCSI_In__ACK__AG EQU CYREG_PRT6_AG +SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__ACK__DR EQU CYREG_PRT6_DR +SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__ACK__MASK EQU 0x20 +SCSI_In__ACK__PC EQU CYREG_PRT6_PC5 +SCSI_In__ACK__PORT EQU 6 +SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__ACK__PS EQU CYREG_PRT6_PS +SCSI_In__ACK__SHIFT EQU 5 +SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_In__ATN__AG EQU CYREG_PRT12_AG +SCSI_In__ATN__BIE EQU CYREG_PRT12_BIE +SCSI_In__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In__ATN__BYP EQU CYREG_PRT12_BYP +SCSI_In__ATN__DM0 EQU CYREG_PRT12_DM0 +SCSI_In__ATN__DM1 EQU CYREG_PRT12_DM1 +SCSI_In__ATN__DM2 EQU CYREG_PRT12_DM2 +SCSI_In__ATN__DR EQU CYREG_PRT12_DR +SCSI_In__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In__ATN__MASK EQU 0x20 +SCSI_In__ATN__PC EQU CYREG_PRT12_PC5 +SCSI_In__ATN__PORT EQU 12 +SCSI_In__ATN__PRT EQU CYREG_PRT12_PRT +SCSI_In__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In__ATN__PS EQU CYREG_PRT12_PS +SCSI_In__ATN__SHIFT EQU 5 +SCSI_In__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In__ATN__SLW EQU CYREG_PRT12_SLW +SCSI_In__BSY__AG EQU CYREG_PRT6_AG +SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__BSY__DR EQU CYREG_PRT6_DR +SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__BSY__MASK EQU 0x10 +SCSI_In__BSY__PC EQU CYREG_PRT6_PC4 +SCSI_In__BSY__PORT EQU 6 +SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__BSY__PS EQU CYREG_PRT6_PS +SCSI_In__BSY__SHIFT EQU 4 +SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_In__CD__AG EQU CYREG_PRT5_AG +SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX +SCSI_In__CD__BIE EQU CYREG_PRT5_BIE +SCSI_In__CD__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In__CD__BYP EQU CYREG_PRT5_BYP +SCSI_In__CD__CTL EQU CYREG_PRT5_CTL +SCSI_In__CD__DM0 EQU CYREG_PRT5_DM0 +SCSI_In__CD__DM1 EQU CYREG_PRT5_DM1 +SCSI_In__CD__DM2 EQU CYREG_PRT5_DM2 +SCSI_In__CD__DR EQU CYREG_PRT5_DR +SCSI_In__CD__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In__CD__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In__CD__MASK EQU 0x02 +SCSI_In__CD__PC EQU CYREG_PRT5_PC1 +SCSI_In__CD__PORT EQU 5 +SCSI_In__CD__PRT EQU CYREG_PRT5_PRT +SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In__CD__PS EQU CYREG_PRT5_PS +SCSI_In__CD__SHIFT EQU 1 +SCSI_In__CD__SLW EQU CYREG_PRT5_SLW +SCSI_In__DBP__AG EQU CYREG_PRT12_AG +SCSI_In__DBP__BIE EQU CYREG_PRT12_BIE +SCSI_In__DBP__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In__DBP__BYP EQU CYREG_PRT12_BYP +SCSI_In__DBP__DM0 EQU CYREG_PRT12_DM0 +SCSI_In__DBP__DM1 EQU CYREG_PRT12_DM1 +SCSI_In__DBP__DM2 EQU CYREG_PRT12_DM2 +SCSI_In__DBP__DR EQU CYREG_PRT12_DR +SCSI_In__DBP__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In__DBP__MASK EQU 0x10 +SCSI_In__DBP__PC EQU CYREG_PRT12_PC4 +SCSI_In__DBP__PORT EQU 12 +SCSI_In__DBP__PRT EQU CYREG_PRT12_PRT +SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In__DBP__PS EQU CYREG_PRT12_PS +SCSI_In__DBP__SHIFT EQU 4 +SCSI_In__DBP__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In__DBP__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In__DBP__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In__DBP__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In__DBP__SLW EQU CYREG_PRT12_SLW +SCSI_In__IO__AG EQU CYREG_PRT5_AG +SCSI_In__IO__AMUX EQU CYREG_PRT5_AMUX +SCSI_In__IO__BIE EQU CYREG_PRT5_BIE +SCSI_In__IO__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In__IO__BYP EQU CYREG_PRT5_BYP +SCSI_In__IO__CTL EQU CYREG_PRT5_CTL +SCSI_In__IO__DM0 EQU CYREG_PRT5_DM0 +SCSI_In__IO__DM1 EQU CYREG_PRT5_DM1 +SCSI_In__IO__DM2 EQU CYREG_PRT5_DM2 +SCSI_In__IO__DR EQU CYREG_PRT5_DR +SCSI_In__IO__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In__IO__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In__IO__MASK EQU 0x08 +SCSI_In__IO__PC EQU CYREG_PRT5_PC3 +SCSI_In__IO__PORT EQU 5 +SCSI_In__IO__PRT EQU CYREG_PRT5_PRT +SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In__IO__PS EQU CYREG_PRT5_PS +SCSI_In__IO__SHIFT EQU 3 +SCSI_In__IO__SLW EQU CYREG_PRT5_SLW +SCSI_In__MSG__AG EQU CYREG_PRT6_AG +SCSI_In__MSG__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__MSG__BIE EQU CYREG_PRT6_BIE +SCSI_In__MSG__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__MSG__BYP EQU CYREG_PRT6_BYP +SCSI_In__MSG__CTL EQU CYREG_PRT6_CTL +SCSI_In__MSG__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__MSG__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__MSG__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__MSG__DR EQU CYREG_PRT6_DR +SCSI_In__MSG__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__MSG__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__MSG__MASK EQU 0x80 +SCSI_In__MSG__PC EQU CYREG_PRT6_PC7 +SCSI_In__MSG__PORT EQU 6 +SCSI_In__MSG__PRT EQU CYREG_PRT6_PRT +SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__MSG__PS EQU CYREG_PRT6_PS +SCSI_In__MSG__SHIFT EQU 7 +SCSI_In__MSG__SLW EQU CYREG_PRT6_SLW +SCSI_In__REQ__AG EQU CYREG_PRT5_AG +SCSI_In__REQ__AMUX EQU CYREG_PRT5_AMUX +SCSI_In__REQ__BIE EQU CYREG_PRT5_BIE +SCSI_In__REQ__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In__REQ__BYP EQU CYREG_PRT5_BYP +SCSI_In__REQ__CTL EQU CYREG_PRT5_CTL +SCSI_In__REQ__DM0 EQU CYREG_PRT5_DM0 +SCSI_In__REQ__DM1 EQU CYREG_PRT5_DM1 +SCSI_In__REQ__DM2 EQU CYREG_PRT5_DM2 +SCSI_In__REQ__DR EQU CYREG_PRT5_DR +SCSI_In__REQ__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In__REQ__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In__REQ__MASK EQU 0x04 +SCSI_In__REQ__PC EQU CYREG_PRT5_PC2 +SCSI_In__REQ__PORT EQU 5 +SCSI_In__REQ__PRT EQU CYREG_PRT5_PRT +SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In__REQ__PS EQU CYREG_PRT5_PS +SCSI_In__REQ__SHIFT EQU 2 +SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW +SCSI_In__RST__AG EQU CYREG_PRT6_AG +SCSI_In__RST__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__RST__BIE EQU CYREG_PRT6_BIE +SCSI_In__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__RST__BYP EQU CYREG_PRT6_BYP +SCSI_In__RST__CTL EQU CYREG_PRT6_CTL +SCSI_In__RST__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__RST__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__RST__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__RST__DR EQU CYREG_PRT6_DR +SCSI_In__RST__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__RST__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__RST__MASK EQU 0x40 +SCSI_In__RST__PC EQU CYREG_PRT6_PC6 +SCSI_In__RST__PORT EQU 6 +SCSI_In__RST__PRT EQU CYREG_PRT6_PRT +SCSI_In__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__RST__PS EQU CYREG_PRT6_PS +SCSI_In__RST__SHIFT EQU 6 +SCSI_In__RST__SLW EQU CYREG_PRT6_SLW +SCSI_In__SEL__AG EQU CYREG_PRT5_AG +SCSI_In__SEL__AMUX EQU CYREG_PRT5_AMUX +SCSI_In__SEL__BIE EQU CYREG_PRT5_BIE +SCSI_In__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In__SEL__BYP EQU CYREG_PRT5_BYP +SCSI_In__SEL__CTL EQU CYREG_PRT5_CTL +SCSI_In__SEL__DM0 EQU CYREG_PRT5_DM0 +SCSI_In__SEL__DM1 EQU CYREG_PRT5_DM1 +SCSI_In__SEL__DM2 EQU CYREG_PRT5_DM2 +SCSI_In__SEL__DR EQU CYREG_PRT5_DR +SCSI_In__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In__SEL__MASK EQU 0x01 +SCSI_In__SEL__PC EQU CYREG_PRT5_PC0 +SCSI_In__SEL__PORT EQU 5 +SCSI_In__SEL__PRT EQU CYREG_PRT5_PRT +SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In__SEL__PS EQU CYREG_PRT5_PS +SCSI_In__SEL__SHIFT EQU 0 +SCSI_In__SEL__SLW EQU CYREG_PRT5_SLW + +; SD_DAT1 +SD_DAT1__0__MASK EQU 0x20 +SD_DAT1__0__PC EQU CYREG_PRT3_PC5 +SD_DAT1__0__PORT EQU 3 +SD_DAT1__0__SHIFT EQU 5 +SD_DAT1__AG EQU CYREG_PRT3_AG +SD_DAT1__AMUX EQU CYREG_PRT3_AMUX +SD_DAT1__BIE EQU CYREG_PRT3_BIE +SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_DAT1__BYP EQU CYREG_PRT3_BYP +SD_DAT1__CTL EQU CYREG_PRT3_CTL +SD_DAT1__DM0 EQU CYREG_PRT3_DM0 +SD_DAT1__DM1 EQU CYREG_PRT3_DM1 +SD_DAT1__DM2 EQU CYREG_PRT3_DM2 +SD_DAT1__DR EQU CYREG_PRT3_DR +SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_DAT1__MASK EQU 0x20 +SD_DAT1__PORT EQU 3 +SD_DAT1__PRT EQU CYREG_PRT3_PRT +SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_DAT1__PS EQU CYREG_PRT3_PS +SD_DAT1__SHIFT EQU 5 +SD_DAT1__SLW EQU CYREG_PRT3_SLW + +; SD_DAT2 +SD_DAT2__0__MASK EQU 0x01 +SD_DAT2__0__PC EQU CYREG_PRT3_PC0 +SD_DAT2__0__PORT EQU 3 +SD_DAT2__0__SHIFT EQU 0 +SD_DAT2__AG EQU CYREG_PRT3_AG +SD_DAT2__AMUX EQU CYREG_PRT3_AMUX +SD_DAT2__BIE EQU CYREG_PRT3_BIE +SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_DAT2__BYP EQU CYREG_PRT3_BYP +SD_DAT2__CTL EQU CYREG_PRT3_CTL +SD_DAT2__DM0 EQU CYREG_PRT3_DM0 +SD_DAT2__DM1 EQU CYREG_PRT3_DM1 +SD_DAT2__DM2 EQU CYREG_PRT3_DM2 +SD_DAT2__DR EQU CYREG_PRT3_DR +SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_DAT2__MASK EQU 0x01 +SD_DAT2__PORT EQU 3 +SD_DAT2__PRT EQU CYREG_PRT3_PRT +SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_DAT2__PS EQU CYREG_PRT3_PS +SD_DAT2__SHIFT EQU 0 +SD_DAT2__SLW EQU CYREG_PRT3_SLW + +; SD_MISO +SD_MISO__0__MASK EQU 0x10 +SD_MISO__0__PC EQU CYREG_PRT3_PC4 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 4 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x10 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 4 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +; SD_MOSI +SD_MOSI__0__MASK EQU 0x04 +SD_MOSI__0__PC EQU CYREG_PRT3_PC2 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 2 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x04 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 2 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + +; SD_SCK +SD_SCK__0__MASK EQU 0x08 +SD_SCK__0__PC EQU CYREG_PRT3_PC3 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 3 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x08 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 3 +SD_SCK__SLW EQU CYREG_PRT3_SLW + +; SD_CD +SD_CD__0__MASK EQU 0x40 +SD_CD__0__PC EQU CYREG_PRT3_PC6 +SD_CD__0__PORT EQU 3 +SD_CD__0__SHIFT EQU 6 +SD_CD__AG EQU CYREG_PRT3_AG +SD_CD__AMUX EQU CYREG_PRT3_AMUX +SD_CD__BIE EQU CYREG_PRT3_BIE +SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CD__BYP EQU CYREG_PRT3_BYP +SD_CD__CTL EQU CYREG_PRT3_CTL +SD_CD__DM0 EQU CYREG_PRT3_DM0 +SD_CD__DM1 EQU CYREG_PRT3_DM1 +SD_CD__DM2 EQU CYREG_PRT3_DM2 +SD_CD__DR EQU CYREG_PRT3_DR +SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CD__MASK EQU 0x40 +SD_CD__PORT EQU 3 +SD_CD__PRT EQU CYREG_PRT3_PRT +SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CD__PS EQU CYREG_PRT3_PS +SD_CD__SHIFT EQU 6 +SD_CD__SLW EQU CYREG_PRT3_SLW + +; SD_CS +SD_CS__0__MASK EQU 0x02 +SD_CS__0__PC EQU CYREG_PRT3_PC1 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 1 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x02 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 1 +SD_CS__SLW EQU CYREG_PRT3_SLW + +; SD_WP +SD_WP__0__MASK EQU 0x80 +SD_WP__0__PC EQU CYREG_PRT3_PC7 +SD_WP__0__PORT EQU 3 +SD_WP__0__SHIFT EQU 7 +SD_WP__AG EQU CYREG_PRT3_AG +SD_WP__AMUX EQU CYREG_PRT3_AMUX +SD_WP__BIE EQU CYREG_PRT3_BIE +SD_WP__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_WP__BYP EQU CYREG_PRT3_BYP +SD_WP__CTL EQU CYREG_PRT3_CTL +SD_WP__DM0 EQU CYREG_PRT3_DM0 +SD_WP__DM1 EQU CYREG_PRT3_DM1 +SD_WP__DM2 EQU CYREG_PRT3_DM2 +SD_WP__DR EQU CYREG_PRT3_DR +SD_WP__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_WP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_WP__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_WP__MASK EQU 0x80 +SD_WP__PORT EQU 3 +SD_WP__PRT EQU CYREG_PRT3_PRT +SD_WP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_WP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_WP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_WP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_WP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_WP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_WP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_WP__PS EQU CYREG_PRT3_PS +SD_WP__SHIFT EQU 7 +SD_WP__SLW EQU CYREG_PRT3_SLW + +; LED1 +LED1__0__MASK EQU 0x08 +LED1__0__PC EQU CYREG_PRT12_PC3 +LED1__0__PORT EQU 12 +LED1__0__SHIFT EQU 3 +LED1__AG EQU CYREG_PRT12_AG +LED1__BIE EQU CYREG_PRT12_BIE +LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK +LED1__BYP EQU CYREG_PRT12_BYP +LED1__DM0 EQU CYREG_PRT12_DM0 +LED1__DM1 EQU CYREG_PRT12_DM1 +LED1__DM2 EQU CYREG_PRT12_DM2 +LED1__DR EQU CYREG_PRT12_DR +LED1__INP_DIS EQU CYREG_PRT12_INP_DIS +LED1__MASK EQU 0x08 +LED1__PORT EQU 12 +LED1__PRT EQU CYREG_PRT12_PRT +LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +LED1__PS EQU CYREG_PRT12_PS +LED1__SHIFT EQU 3 +LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG +LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +LED1__SLW EQU CYREG_PRT12_SLW + +; Miscellaneous +; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release +CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_MEMBER_5B EQU 4 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_DIE_PSOC5LP EQU 4 +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP +BCLK__BUS_CLK__HZ EQU 64000000 +BCLK__BUS_CLK__KHZ EQU 64000 +BCLK__BUS_CLK__MHZ EQU 64 +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PANTHER EQU 3 +CYDEV_CHIP_DIE_PSOC4A EQU 2 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 +CYDEV_CHIP_JTAG_ID EQU 0x2E12F069 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 2 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PANTHER_ES0 EQU 0 +CYDEV_CHIP_REV_PANTHER_ES1 EQU 1 +CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_DMA EQU 0 +CYDEV_CONFIGURATION_ECC EQU 1 +CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1 +CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0 +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DEBUGGING_REQXRES EQU 1 +CYDEV_DEBUGGING_XRES EQU 0 +CYDEV_DEBUG_ENABLE_MASK EQU 0x20 +CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG +CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 +CYDEV_ECC_ENABLE EQU 0 +CYDEV_HEAP_SIZE EQU 0x1000 +CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 +CYDEV_INTR_RISING EQU 0x00000003 +CYDEV_PROJ_TYPE EQU 0 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_PROTECTION_ENABLE EQU 0 +CYDEV_STACK_SIZE EQU 0x4000 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD_MV EQU 5000 +CYDEV_VDDIO0_MV EQU 5000 +CYDEV_VDDIO1_MV EQU 5000 +CYDEV_VDDIO2_MV EQU 5000 +CYDEV_VDDIO3_MV EQU 3300 +CYDEV_VIO0 EQU 5 +CYDEV_VIO0_MV EQU 5000 +CYDEV_VIO1 EQU 5 +CYDEV_VIO1_MV EQU 5000 +CYDEV_VIO2 EQU 5 +CYDEV_VIO2_MV EQU 5000 +CYDEV_VIO3_MV EQU 3300 +DMA_CHANNELS_USED__MASK0 EQU 0x00000000 +CYDEV_BOOTLOADER_ENABLE EQU 0 + ENDIF + END diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h new file mode 100644 index 0000000..21f9573 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h @@ -0,0 +1,295 @@ +/******************************************************************************* +* File Name: cypins.h +* Version 3.40 +* +* Description: +* This file contains the function prototypes and constants used for port/pin +* in access and control. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPINS_H) +#define CY_BOOT_CYPINS_H + +#include "cyfitter.h" +#include "cytypes.h" + + +/************************************** +* API Parameter Constants +**************************************/ + +#define CY_PINS_PC_DRIVE_MODE_SHIFT (0x01u) +#define CY_PINS_PC_DRIVE_MODE_MASK ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_0 ((uint8)(0x00u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_1 ((uint8)(0x01u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_2 ((uint8)(0x02u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_3 ((uint8)(0x03u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_4 ((uint8)(0x04u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_5 ((uint8)(0x05u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_6 ((uint8)(0x06u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_7 ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) + + +/* SetPinDriveMode */ +#define CY_PINS_DM_ALG_HIZ (CY_PINS_PC_DRIVE_MODE_0) +#define CY_PINS_DM_DIG_HIZ (CY_PINS_PC_DRIVE_MODE_1) +#define CY_PINS_DM_RES_UP (CY_PINS_PC_DRIVE_MODE_2) +#define CY_PINS_DM_RES_DWN (CY_PINS_PC_DRIVE_MODE_3) +#define CY_PINS_DM_OD_LO (CY_PINS_PC_DRIVE_MODE_4) +#define CY_PINS_DM_OD_HI (CY_PINS_PC_DRIVE_MODE_5) +#define CY_PINS_DM_STRONG (CY_PINS_PC_DRIVE_MODE_6) +#define CY_PINS_DM_RES_UPDWN (CY_PINS_PC_DRIVE_MODE_7) + + +/************************************** +* Register Constants +**************************************/ + +/* Port Pin Configuration Register */ +#define CY_PINS_PC_DATAOUT (0x01u) +#define CY_PINS_PC_PIN_FASTSLEW (0xBFu) +#define CY_PINS_PC_PIN_SLOWSLEW (0x40u) +#define CY_PINS_PC_PIN_STATE (0x10u) +#define CY_PINS_PC_BIDIR_EN (0x20u) +#define CY_PINS_PC_SLEW (0x40u) +#define CY_PINS_PC_BYPASS (0x80u) + + +/************************************** +* Pin API Macros +**************************************/ + +/******************************************************************************* +* Macro Name: CyPins_ReadPin +******************************************************************************** +* +* Summary: +* Reads the current value on the pin (pin state, PS). +* +* Parameters: +* pinPC: Port pin configuration register (uint16). +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* Pin state +* 0: Logic low value +* Non-0: Logic high value +* +*******************************************************************************/ +#define CyPins_ReadPin(pinPC) ( *(reg8 *)(pinPC) & CY_PINS_PC_PIN_STATE ) + + +/******************************************************************************* +* Macro Name: CyPins_SetPin +******************************************************************************** +* +* Summary: +* Set the output value for the pin (data register, DR) to a logic high. +* +* Note that this only has an effect for pins configured as software pins that +* are not driven by hardware. +* +* Parameters: +* pinPC: Port pin configuration register (uint16). +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_SetPin(pinPC) ( *(reg8 *)(pinPC) |= CY_PINS_PC_DATAOUT) + + +/******************************************************************************* +* Macro Name: CyPins_ClearPin +******************************************************************************** +* +* Summary: +* This macro sets the state of the specified pin to 0 +* +* Parameters: +* pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_ClearPin(pinPC) ( *(reg8 *)(pinPC) &= ((uint8)(~CY_PINS_PC_DATAOUT))) + + +/******************************************************************************* +* Macro Name: CyPins_SetPinDriveMode +******************************************************************************** +* +* Summary: +* Sets the drive mode for the pin (DM). +* +* Parameters: +* pinPC: Port pin configuration register (uint16) +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* mode: Desired drive mode +* +* Define Source +* PIN_DM_ALG_HIZ Analog HiZ +* PIN_DM_DIG_HIZ Digital HiZ +* PIN_DM_RES_UP Resistive pull up +* PIN_DM_RES_DWN Resistive pull down +* PIN_DM_OD_LO Open drain - drive low +* PIN_DM_OD_HI Open drain - drive high +* PIN_DM_STRONG Strong CMOS Output +* PIN_DM_RES_UPDWN Resistive pull up/down +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_SetPinDriveMode(pinPC, mode) \ + ( *(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & ((uint8)(~CY_PINS_PC_DRIVE_MODE_MASK))) | \ + ((mode) & CY_PINS_PC_DRIVE_MODE_MASK)) + + +/******************************************************************************* +* Macro Name: CyPins_ReadPinDriveMode +******************************************************************************** +* +* Summary: +* Reads the drive mode for the pin (DM). +* +* Parameters: +* pinPC: Port pin configuration register (uint16) +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* +* Return: +* mode: Current drive mode for the pin +* +* Define Source +* PIN_DM_ALG_HIZ Analog HiZ +* PIN_DM_DIG_HIZ Digital HiZ +* PIN_DM_RES_UP Resistive pull up +* PIN_DM_RES_DWN Resistive pull down +* PIN_DM_OD_LO Open drain - drive low +* PIN_DM_OD_HI Open drain - drive high +* PIN_DM_STRONG Strong CMOS Output +* PIN_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CyPins_ReadPinDriveMode(pinPC) (*(reg8 *)(pinPC) & CY_PINS_PC_DRIVE_MODE_MASK) + + +/******************************************************************************* +* Macro Name: CyPins_FastSlew +******************************************************************************** +* +* Summary: +* Set the slew rate for the pin to fast edge rate. +* Note that this only applies for pins in strong output drive modes, +* not to resistive drive modes. +* +* Parameters: +* pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_FastSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & CY_PINS_PC_PIN_FASTSLEW)) + + +/******************************************************************************* +* Macro Name: CyPins_SlowSlew +******************************************************************************** +* +* Summary: +* Set the slew rate for the pin to slow edge rate. +* Note that this only applies for pins in strong output drive modes, +* not to resistive drive modes. +* +* Parameters: +* pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_SlowSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) | CY_PINS_PC_PIN_SLOWSLEW)) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 +*******************************************************************************/ +#define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT) +#define PC_DRIVE_MODE_MASK (CY_PINS_PC_DRIVE_MODE_MASK) +#define PC_DRIVE_MODE_0 (CY_PINS_PC_DRIVE_MODE_0) +#define PC_DRIVE_MODE_1 (CY_PINS_PC_DRIVE_MODE_1) +#define PC_DRIVE_MODE_2 (CY_PINS_PC_DRIVE_MODE_2) +#define PC_DRIVE_MODE_3 (CY_PINS_PC_DRIVE_MODE_3) +#define PC_DRIVE_MODE_4 (CY_PINS_PC_DRIVE_MODE_4) +#define PC_DRIVE_MODE_5 (CY_PINS_PC_DRIVE_MODE_5) +#define PC_DRIVE_MODE_6 (CY_PINS_PC_DRIVE_MODE_6) +#define PC_DRIVE_MODE_7 (CY_PINS_PC_DRIVE_MODE_7) + +#define PIN_DM_ALG_HIZ (CY_PINS_DM_ALG_HIZ) +#define PIN_DM_DIG_HIZ (CY_PINS_DM_DIG_HIZ) +#define PIN_DM_RES_UP (CY_PINS_DM_RES_UP) +#define PIN_DM_RES_DWN (CY_PINS_DM_RES_DWN) +#define PIN_DM_OD_LO (CY_PINS_DM_OD_LO) +#define PIN_DM_OD_HI (CY_PINS_DM_OD_HI) +#define PIN_DM_STRONG (CY_PINS_DM_STRONG) +#define PIN_DM_RES_UPDWN (CY_PINS_DM_RES_UPDWN) + +#define PC_DATAOUT (CY_PINS_PC_DATAOUT) +#define PC_PIN_FASTSLEW (CY_PINS_PC_PIN_FASTSLEW) +#define PC_PIN_SLOWSLEW (CY_PINS_PC_PIN_SLOWSLEW) +#define PC_PIN_STATE (CY_PINS_PC_PIN_STATE) +#define PC_BIDIR_EN (CY_PINS_PC_BIDIR_EN) +#define PC_SLEW (CY_PINS_PC_SLEW) +#define PC_BYPASS (CY_PINS_PC_BYPASS) + +#endif /* (CY_BOOT_CYPINS_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h new file mode 100644 index 0000000..dda1034 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h @@ -0,0 +1,411 @@ +/******************************************************************************* +* FILENAME: cytypes.h +* Version 3.40 +* +* Description: +* CyTypes provides register access macros and approved types for use in +* firmware. +* +* Note: +* Due to endiannesses of the hardware and some compilers, the register +* access macros for big endian compilers use some library calls to arrange +* data the correct way. +* +* Register Access macros and functions perform their operations on an +* input of type pointer to void. The arguments passed to it should be +* pointers to the type associated with the register size. +* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYTYPES_H) +#define CY_BOOT_CYTYPES_H + +#if defined(__C51__) + #include +#endif /* (__C51__) */ + +/* ARM and C99 or later */ +#if defined(__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) + #include +#endif /* (__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) */ + +#include "cyfitter.h" + + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + + +/******************************************************************************* +* FAMILY encodes the overall architectural family +*******************************************************************************/ +#define CY_PSOC3 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) +#define CY_PSOC4 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) +#define CY_PSOC5 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5) + + +/******************************************************************************* +* MEMBER encodes both the family and the detailed architecture +*******************************************************************************/ +#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#ifdef CYDEV_CHIP_MEMBER_5B + #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B) +#else + #define CY_PSOC5LP 0 +#endif + + +/******************************************************************************* +* UDB revisions +*******************************************************************************/ +#define CY_UDB_V0 (CY_PSOC5A) +#define CY_UDB_V1 (!CY_UDB_V0) + + +/******************************************************************************* +* Base Types. Acceptable types from MISRA-C specifying signedness and size. +*******************************************************************************/ +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +typedef signed char int8; +typedef signed short int16; +typedef signed long int32; +typedef float float32; + +#if(!CY_PSOC3) + + typedef double float64; + typedef long long int64; + typedef unsigned long long uint64; + +#endif /* (!CY_PSOC3) */ + +/* Signed or unsigned depending on the compiler selection */ +typedef char char8; + + +/******************************************************************************* +* Memory address functions prototypes +*******************************************************************************/ +#if(CY_PSOC3) + + /*************************************************************************** + * Prototypes for absolute memory address functions (cymem.a51) with built-in + * endian conversion. These functions should be called through the + * CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros. + ***************************************************************************/ + extern uint8 cyread8 (volatile void far *addr); + extern void cywrite8 (volatile void far *addr, uint8 value); + + extern uint16 cyread16 (volatile void far *addr); + extern uint16 cyread16_nodpx(volatile void far *addr); + + extern void cywrite16 (volatile void far *addr, uint16 value); + extern void cywrite16_nodpx(volatile void far *addr, uint16 value); + + extern uint32 cyread24 (volatile void far *addr); + extern uint32 cyread24_nodpx(volatile void far *addr); + + extern void cywrite24 (volatile void far *addr, uint32 value); + extern void cywrite24_nodpx(volatile void far *addr, uint32 value); + + extern uint32 cyread32 (volatile void far *addr); + extern uint32 cyread32_nodpx(volatile void far *addr); + + extern void cywrite32 (volatile void far *addr, uint32 value); + extern void cywrite32_nodpx(volatile void far *addr, uint32 value); + + + /*************************************************************************** + * Memory access routines from cymem.a51 for the generated device + * configuration code. These functions may be subject to change in future + * revisions of the cy_boot component and they are not available for all + * devices. Most code should use memset or memcpy instead. + ***************************************************************************/ + void cymemzero(void far *addr, uint16 size); + void cyconfigcpy(uint16 size, const void far *src, void far *dest) large; + void cyconfigcpycode(uint16 size, const void code *src, void far *dest); + + #define CYCONFIGCPY_DECLARED (1) + +#else + + /* Prototype for function to set a 24-bit register. Located at cyutils.c */ + extern void CySetReg24(uint32 volatile * addr, uint32 value); + + #if(CY_PSOC4) + + extern uint32 CyGetReg24(uint32 volatile * addr); + + #endif /*(CY_PSOC4)*/ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Memory model definitions. To allow code to be 8051-ARM agnostic. +*******************************************************************************/ +#if(CY_PSOC3) + + #define CYBDATA bdata + #define CYBIT bit + #define CYCODE code + #define CYCOMPACT compact + #define CYDATA data + #define CYFAR far + #define CYIDATA idata + #define CYLARGE large + #define CYPDATA pdata + #define CYREENTRANT reentrant + #define CYSMALL small + #define CYXDATA xdata + #define XDATA xdata + + #define CY_NOINIT + +#else + + #define CYBDATA + #define CYBIT uint8 + #define CYCODE + #define CYCOMPACT + #define CYDATA + #define CYFAR + #define CYIDATA + #define CYLARGE + #define CYPDATA + #define CYREENTRANT + #define CYSMALL + #define CYXDATA + #define XDATA + + #if defined(__ARMCC_VERSION) + #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) + #elif defined (__GNUC__) + #define CY_NOINIT __attribute__ ((section(".noinit"))) + #endif /* (__ARMCC_VERSION) */ + + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC3) + + /* 8051 naturally returns an 8 bit value. */ + typedef unsigned char cystatus; + +#else + + /* ARM naturally returns a 32 bit value. */ + typedef unsigned long cystatus; + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Hardware Register Types. +*******************************************************************************/ +typedef volatile uint8 CYXDATA reg8; +typedef volatile uint16 CYXDATA reg16; +typedef volatile uint32 CYXDATA reg32; + + +/******************************************************************************* +* Interrupt Types and Macros +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_ISR(FuncName) void FuncName (void) interrupt 0 + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (CYCODE * cyisraddress)(void); + +#else + + #define CY_ISR(FuncName) void FuncName (void) + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (* cyisraddress)(void); + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Register Access +*******************************************************************************/ +#if(CY_PSOC3) + + + /******************************************************************************* + * KEIL for the 8051 is a big endian compiler This causes problems as the on chip + * registers are little endian. Byte swapping for two and four byte registers is + * implemented in the functions below. This will require conditional compilation + * of function prototypes in code. + *******************************************************************************/ + + /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */ + + #define CY_GET_REG8(addr) (*((reg8 *)(addr))) + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + #define CY_GET_REG16(addr) cyread16_nodpx ((volatile void far *)(reg16 *)(addr)) + #define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value) + + #define CY_GET_REG24(addr) cyread24_nodpx ((volatile void far *)(reg32 *)(addr)) + #define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value) + + #define CY_GET_REG32(addr) cyread32_nodpx ((volatile void far *)(reg32 *)(addr)) + #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value) + + /* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */ + #define CY_GET_XTND_REG8(addr) cyread8((volatile void far *)(addr)) + #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value) + + #define CY_GET_XTND_REG16(addr) cyread16((volatile void far *)(addr)) + #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value) + + #define CY_GET_XTND_REG24(addr) cyread24((volatile void far *)(addr)) + #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value) + + #define CY_GET_XTND_REG32(addr) cyread32((volatile void far *)(addr)) + #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value) + +#else + + /* 8, 16, 24 and 32-bit register access macros */ + #define CY_GET_REG8(addr) (*((reg8 *)(addr))) + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + #define CY_GET_REG16(addr) (*((reg16 *)(addr))) + #define CY_SET_REG16(addr, value) (*((reg16 *)(addr)) = (uint16)(value)) + + + #define CY_SET_REG24(addr, value) CySetReg24((reg32 *) (addr), (value)) + #if(CY_PSOC4) + #define CY_GET_REG24(addr) CyGetReg24((reg32 *) (addr)) + #else + #define CY_GET_REG24(addr) (*((reg32 *)(addr)) & 0x00FFFFFFu) + #endif /* (CY_PSOC4) */ + + + #define CY_GET_REG32(addr) (*((reg32 *)(addr))) + #define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value)) + + + /* To allow code to be 8051-ARM agnostic. */ + #define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr) + #define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value) + + #define CY_GET_XTND_REG16(addr) CY_GET_REG16(addr) + #define CY_SET_XTND_REG16(addr, value) CY_SET_REG16(addr, value) + + #define CY_GET_XTND_REG24(addr) CY_GET_REG24(addr) + #define CY_SET_XTND_REG24(addr, value) CY_SET_REG24(addr, value) + + #define CY_GET_XTND_REG32(addr) CY_GET_REG32(addr) + #define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value) + +#endif /* (CY_PSOC3) */ + + + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/* Get 8 bits of a 16 bit value. */ +#define LO8(x) ((uint8) (x)) +#define HI8(x) ((uint8) ((x) >> 8)) + +/* Get 16 bits of a 32 bit value. */ +#define LO16(x) ((uint16) (x)) +#define HI16(x) ((uint16) ((uint32)(x) >> 16)) + +/* Swap the byte ordering of a 32 bit value */ +#define CYSWAP_ENDIAN32(x) \ + ((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24))) + +/* Swap the byte ordering of a 16 bit value */ +#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | ((x) >> 8))) + + +/******************************************************************************* +* Defines the standard return values used PSoC content. A function is +* not limited to these return values but can use them when returning standard +* error values. Return values can be overloaded if documented in the function +* header. On the 8051 a function can use a larger return type but still use the +* defined return codes. +* +* Zero is successful, all other values indicate some form of failure. 1 - 0x7F - +* standard defined values; 0x80 - ... - user or content defined values. +*******************************************************************************/ +#define CYRET_SUCCESS (0x00u) /* Successful */ +#define CYRET_BAD_PARAM (0x01u) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02u) /* Invalid object specified */ +#define CYRET_MEMORY (0x03u) /* Memory related failure */ +#define CYRET_LOCKED (0x04u) /* Resource lock failure */ +#define CYRET_EMPTY (0x05u) /* No more objects available */ +#define CYRET_BAD_DATA (0x06u) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07u) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08u) /* Operation completed */ +#define CYRET_CANCELED (0x09u) /* Operation canceled */ +#define CYRET_TIMEOUT (0x10u) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11u) /* Operation not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFu) /* Unknown failure */ + + +/******************************************************************************* +* Intrinsic Defines: Processor NOP instruction +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_NOP _nop_() + +#else + + #if defined(__ARMCC_VERSION) + + /* RealView */ + #define CY_NOP __nop() + + #else + + /* GCC */ + #define CY_NOP __asm("NOP\n") + + #endif /* defined(__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.10 +*******************************************************************************/ + +/* Device is PSoC 3 and the revision is ES2 or earlier */ +#define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2)) + +/* Device is PSoC 3 and the revision is ES3 or later */ +#define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3)) + +/* Device is PSoC 5 and the revision is ES1 or earlier */ +#define CY_PSOC5_ES1 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1)) + +/* Device is PSoC 5 and the revision is ES2 or later */ +#define CY_PSOC5_ES2 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1)) + +#endif /* CY_BOOT_CYTYPES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c new file mode 100644 index 0000000..15256d7 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c @@ -0,0 +1,87 @@ +/******************************************************************************* +* FILENAME: cyutils.c +* Version 3.40 +* +* Description: +* CyUtils provides function to handle 24-bit value writes. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" + +#if (!CY_PSOC3) + + /*************************************************************************** + * Function Name: CySetReg24 + **************************************************************************** + * + * Summary: + * Writes the 24-bit value to the specified register. + * + * Parameters: + * addr : adress where data must be written + * value: data that must be written + * + * Return: + * None + * + * Reentrant: + * No + * + ***************************************************************************/ + void CySetReg24(uint32 volatile * addr, uint32 value) + { + uint8 volatile *tmpAddr; + + tmpAddr = (uint8 volatile *) addr; + + tmpAddr[0u] = (uint8) value; + tmpAddr[1u] = (uint8) (value >> 8u); + tmpAddr[2u] = (uint8) (value >> 16u); + } + + + #if(CY_PSOC4) + + /*************************************************************************** + * Function Name: CyGetReg24 + **************************************************************************** + * + * Summary: + * Reads the 24-bit value from the specified register. + * + * Parameters: + * addr : adress where data must be read + * + * Return: + * None + * + * Reentrant: + * No + * + ***************************************************************************/ + uint32 CyGetReg24(uint32 volatile * addr) + { + uint8 volatile *tmpAddr; + uint32 value; + + tmpAddr = (uint8 volatile *) addr; + + value = (uint32) tmpAddr[0u]; + value |= ((uint32) tmpAddr[1u] << 8u ); + value |= ((uint32) tmpAddr[2u] << 16u); + + return(value); + } + + #endif /*(CY_PSOC4)*/ + +#endif /* (!CY_PSOC3) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/post_link.bat b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/post_link.bat new file mode 100755 index 0000000..d6f7bdc --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/post_link.bat @@ -0,0 +1,19 @@ +@REM This script allows a 3rd party IDE to use CyHexTool to perform +@REM any post processing that is necessary to convert the raw flash +@REM image into a complete hex file to use in programming the PSoC. +@REM USAGE: post_link.bat +@REM arg1: Persistant path back to the directory containing the app project. +@REM arg2: Path (relative to arg1) of the directory where the hex files go. +@REM arg3: Name of the project. +@REM NOTE: This script is auto generated. Do not modify. + +"C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\bin\cyvalidateide.exe" -dev CY8C5268AXI-LP047 -ide "%~1\%~3" -flsAddr 0x0 -flsSize 0x40000 -sramAddr 0x1FFF8000 -sramSize 0x10000 +@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% +move "%~1\%~2\%~n3.hex" "%~1\%~2\%~n3.ihx" +@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% +"C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\bin\cyhextool" -o "%~1\%~2\%~n3.hex" -f "%~1\%~2\%~n3.ihx" -prot "%~dp0protect.hex" -id 2E12F069 -a EEPROM=90200000:800,PROGRAM=00000000:40000,CONFIG=80000000:8000,PROTECT=90400000:100 -meta 0001 -cunv 00004005 -wonv BC90ACAF -ecc "%~dp0config.hex" +@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% +CD /D "C:\Keil\UV4" +@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% +IF NOT EXIST "Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\SCSI2SD.svd" rem "Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\SCSI2SD.sfr" +@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h new file mode 100644 index 0000000..c93bf75 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -0,0 +1,64 @@ +/******************************************************************************* + * File Name: project.h + * PSoC Creator 2.2 Component Pack 6 + * + * Description: + * This file is automatically generated by PSoC Creator and should not + * be edited by hand. + * + * + ******************************************************************************** + * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. + * You may use this file only in accordance with the license, terms, conditions, + * disclaimers, and limitations in the end user license agreement accompanying + * the software package with which this file was provided. + ********************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*[]*/ + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/protect.hex b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/protect.hex new file mode 100644 index 0000000..34bea6f --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/protect.hex @@ -0,0 +1,5 @@ +:4000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C0 +:400040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080 +:400080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040 +:4000C0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +:00000001FF diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx new file mode 100644 index 0000000..880f831 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -0,0 +1,33 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git 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0.1 + CY8C52LP + 8 + 32 + + + SD_Clk_Ctl + No description available + 0x40006575 + + 0 + 0x1 + registers + + + + SD_Clk_Ctl_CONTROL_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + + + \ No newline at end of file diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD_PSoC5lib.uvopt b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD_PSoC5lib.uvopt new file mode 100644 index 0000000..0972a90 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD_PSoC5lib.uvopt @@ -0,0 +1,280 @@ + + + + 1.0 + +

### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + Debug + 0x3 + ARM-GNU + + + CY8C5268AXI-LP047 + Cypress + "IRAM(0x1FFF8000-0x20007FFF)IROM(0x0-0x3FFFF)CLOCK(67000000)CPUTYPE( "Cortex-M3") ESEL ELITTLE" + + + "C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\export\ide\uVision\4.x\driver\cyuvdriver_arm.dll"("Cypress MiniProg3/FX2LP v2.2") + + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\ARM-GNU\Debug\ + SCSI2SD_PSoC5lib + 0 + 1 + 0 + 1 + 0 + .\ARM-GNU\Debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DLM.DLL + -pEMBER + SARMCM3.DLL + + TLM.DLL + -pEMBER + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + + + + + + + + + "C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\export\ide\uVision\4.x\driver\cyuvdriver_arm.dll"("Cypress MiniProg3/FX2LP v2.2") + + + + + 1 + 0 + 0 + 0 + 1 + 8191 + + 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5 + .\Generated_Source\PSoC5\cydevicegnu.inc + + + cydevicerv.inc + 5 + .\Generated_Source\PSoC5\cydevicerv.inc + + + cydevice_trm.h + 5 + .\Generated_Source\PSoC5\cydevice_trm.h + + + cydevicegnu_trm.inc + 5 + .\Generated_Source\PSoC5\cydevicegnu_trm.inc + + + cydevicerv_trm.inc + 5 + .\Generated_Source\PSoC5\cydevicerv_trm.inc + + + cyfittergnu.inc + 5 + .\Generated_Source\PSoC5\cyfittergnu.inc + + + cyfitterrv.inc + 5 + .\Generated_Source\PSoC5\cyfitterrv.inc + + + cyfitter.h + 5 + .\Generated_Source\PSoC5\cyfitter.h + + + SCSI_In_DBx_aliases.h + 5 + .\Generated_Source\PSoC5\SCSI_In_DBx_aliases.h + + + SCSI_In_DBx.c + 1 + .\Generated_Source\PSoC5\SCSI_In_DBx.c + + + SCSI_In_DBx.h + 5 + .\Generated_Source\PSoC5\SCSI_In_DBx.h + + + SCSI_Out_DBx_aliases.h + 5 + .\Generated_Source\PSoC5\SCSI_Out_DBx_aliases.h + + + SCSI_Out_DBx.c + 1 + .\Generated_Source\PSoC5\SCSI_Out_DBx.c + + + SCSI_Out_DBx.h + 5 + .\Generated_Source\PSoC5\SCSI_Out_DBx.h + + + SD_MISO_aliases.h + 5 + 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.\Generated_Source\PSoC5\cyutils.c + + + project.h + 5 + .\Generated_Source\PSoC5\project.h + + + SCSI_In_aliases.h + 5 + .\Generated_Source\PSoC5\SCSI_In_aliases.h + + + SCSI_Out_aliases.h + 5 + .\Generated_Source\PSoC5\SCSI_Out_aliases.h + + + SD_Init_Clk.c + 1 + .\Generated_Source\PSoC5\SD_Init_Clk.c + + + SD_Init_Clk.h + 5 + .\Generated_Source\PSoC5\SD_Init_Clk.h + + + SD_Data_Clk.c + 1 + .\Generated_Source\PSoC5\SD_Data_Clk.c + + + SD_Data_Clk.h + 5 + .\Generated_Source\PSoC5\SD_Data_Clk.h + + + SD_Clk_Ctl.c + 1 + .\Generated_Source\PSoC5\SD_Clk_Ctl.c + + + SD_Clk_Ctl.h + 5 + .\Generated_Source\PSoC5\SD_Clk_Ctl.h + + + SDCard.c + 1 + .\Generated_Source\PSoC5\SDCard.c + + + SDCard.h + 5 + .\Generated_Source\PSoC5\SDCard.h + + + SDCard_PM.c + 1 + .\Generated_Source\PSoC5\SDCard_PM.c + + + SDCard_INT.c + 1 + .\Generated_Source\PSoC5\SDCard_INT.c + + + SDCard_PVT.h + 5 + .\Generated_Source\PSoC5\SDCard_PVT.h + + + + + + + Release + 0x3 + ARM-GNU + + + CY8C5268AXI-LP047 + Cypress + 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z=K^OEO2d#$SZ+cf{#=O4X~8skYJ5CE59RDJy4@y}8{Mi4=c;L2+>jM*VfCG{wbJeu z$YKGj5Yl5Y6U=u^cs!s^+MH`hi9^bED5JzkwQw!4T8TOaI|?xBid}``bBZ|cDvexE-{crKl=@$19Mm1XH`ou$8Z zmbI<3tZSWRed{b6T4%XR(g(62G@Y%V3F1rw1AUWDWaQH1P(FR=n4AEBJ6)osZc4EE zsP}LaSTK8&aQ!!qxIY{;2HrSgxY-~QDr`+*_luXHZB>E%&8Y)Q2`)k7v3#d(kYUhe z7;@jzk}I>m^j*B{_G?OQ=Q74dx0w@*6<)=4HSm-pGS|OUW{w_F_%Y!JHRPy!zDl_W zy=qsQUMw!Q+I`mOFY)NONu@`%5ZQOiiTLBXS&gu{Y=ha#9&$N$>Y1yoxU&33dV9=m zcW>0MBQC#>3{0=<(_oV6s;&#w`Ys}-OR4@}aTvDgMSd7AQA$u5k4=Zc2GZ(jHVl8S zie@(q#oOGAi|PCt7BG?4GXJhepoJ5N-!)uHXW81x(qLJ-_3^Q^U5)sVL^g{ z+s`lLgTEZ|i|7FPk4`@2J3S4%H|V`?XP4j`#ZS@i0R22hF+9^>K(95kbUU;)YSsLi zxTUV;$X8<-!a<^%`ZVdqBkh0gDtNa57q>QZdUmY}XOEh1mMLCc@n5)#|FKcUtz4-n zUS09WUBy3bRB +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#include "bits.h" + +const uint8 Lookup_OddParity[] = +{ +1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, +0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, +0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, +1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, +0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, +1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, +1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, +0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, +0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, +1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, +1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, +0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, +1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, +0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, +0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, +1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1 +}; + +uint8 countBits(uint8 value) +{ + int i; + for (i = 0; value; value >>= 1) + { + i += value & 1; + } + return i; +} diff --git a/software/SCSI2SD/SCSI2SD.cydsn/bits.h b/software/SCSI2SD/SCSI2SD.cydsn/bits.h new file mode 100755 index 0000000..7369ce6 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/bits.h @@ -0,0 +1,27 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#ifndef BITS_H +#define BITS_H + +#include "device.h" + +// Contains the odd-parity flag for a given 8-bit value. +extern const uint8 Lookup_OddParity[256]; + +uint8 countBits(uint8 value); + +#endif \ No newline at end of file diff --git a/software/SCSI2SD/SCSI2SD.cydsn/blinky.c b/software/SCSI2SD/SCSI2SD.cydsn/blinky.c new file mode 100755 index 0000000..676ec5d --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/blinky.c @@ -0,0 +1,31 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#include "blinky.h" +#include "device.h" + +void scsi2sd_test_blink(void) +{ + // Toggle LED. + while (1) + { + LED1_Write(0); + CyDelay(1000); // ms + LED1_Write(1); + CyDelay(250); // ms + } +} \ No newline at end of file diff --git a/software/SCSI2SD/SCSI2SD.cydsn/blinky.h b/software/SCSI2SD/SCSI2SD.cydsn/blinky.h new file mode 100755 index 0000000..a8fde4b --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/blinky.h @@ -0,0 +1,25 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#ifndef SCSI2SD_BLINKY_H +#define SCSI2SD_BLINKY_H + +// Helloworld LED blink test. +void scsi2sd_test_blink(void); + + +#endif // SCSI2SD_POST_H diff --git a/software/SCSI2SD/SCSI2SD.cydsn/device.h b/software/SCSI2SD/SCSI2SD.cydsn/device.h new file mode 100644 index 0000000..6280779 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/device.h @@ -0,0 +1,18 @@ +/******************************************************************************* +* This file is automatically generated by PSoC Creator +* and should not be edited by hand. +* +* This file is necessary for your project to build. +* Please do not delete it. +******************************************************************************** +* Copyright 2008-2011, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifndef DEVICE_H +#define DEVICE_H +#include + +#endif +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/diagnostic.c b/software/SCSI2SD/SCSI2SD.cydsn/diagnostic.c new file mode 100755 index 0000000..3f27b83 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/diagnostic.c @@ -0,0 +1,132 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#include "device.h" +#include "scsi.h" +#include "diagnostic.h" + +#include + +static const uint8 SupportedDiagnosticPages[] = +{ +0x00, // Page Code +0x00, // Reserved +0x02, // Page length +0x00, // Support "Supported diagnostic page" +0x40 // Support "Translate address page" +}; + +void scsiSendDiagnostic() +{ + // SEND DIAGNOSTIC + // Pretend to do self-test. Actual data is returned via the + // RECEIVE DIAGNOSTIC RESULTS command. + int selfTest = scsiDev.cdb[1] & 0x04; + uint32 paramLength = + (((uint32) scsiDev.cdb[3]) << 8) + + scsiDev.cdb[4]; + + if (!selfTest) + { + // Initiator sends us page data. + scsiDev.dataLen = paramLength; + scsiDev.phase = DATA_OUT; + + if (scsiDev.dataLen > sizeof (scsiDev.data)) + { + // Nowhere to store this data! + // Shouldn't happen - our buffer should be many magnitudes larger + // than the required size for diagnostic parameters. + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.status = CHECK_CONDITION; + scsiDev.phase = STATUS; + } + } + else + { + // Default command result will be a status of GOOD anyway. + } +} + +void scsiReceiveDiagnostic() +{ + // RECEIVE DIAGNOSTIC RESULTS + // We assume scsiDev.data contains the contents of a previous + // SEND DIAGNOSTICS command. We only care about the page-code part + // of the parameter list. + uint8 pageCode = scsiDev.data[0]; + + int allocLength = + (((uint16) scsiDev.cdb[3]) << 8) + + scsiDev.cdb[4]; + + + if (pageCode == 0x00) + { + memcpy( + scsiDev.data, + SupportedDiagnosticPages, + sizeof(SupportedDiagnosticPages)); + scsiDev.dataLen = sizeof(SupportedDiagnosticPages); + scsiDev.phase = DATA_IN; + } + else if (pageCode == 0x40) + { + // Translate between logical block address, physical sector address, or + // physical bytes. + uint8 suppliedFmt = scsiDev.data[4] & 0x7; + uint8 translateFmt = scsiDev.data[5] & 0x7; + + // Convert each supplied address back to a simple + // 64bit linear address, then convert back again. + uint64 fromByteAddr = + scsiByteAddress(suppliedFmt, &scsiDev.data[6]); + + scsiSaveByteAddress(translateFmt, fromByteAddr, &scsiDev.data[6]); + + // Fill out the rest of the response. + // (Clear out any optional bits). + scsiDev.data[4] = suppliedFmt; + scsiDev.data[5] = translateFmt; + + scsiDev.dataLen = 14; + scsiDev.phase = DATA_IN; + } + else + { + // error. + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.phase = STATUS; + } + + if (scsiDev.phase == DATA_IN && scsiDev.dataLen > allocLength) + { + // simply truncate the response. + scsiDev.dataLen = allocLength; + } + + uint8 lun = scsiDev.cdb[1] >> 5; + // Set the first byte to indicate LUN presence. + if (lun) // We only support lun 0 + { + scsiDev.data[0] = 0x7F; + } +} + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/diagnostic.h b/software/SCSI2SD/SCSI2SD.cydsn/diagnostic.h new file mode 100755 index 0000000..cec3f42 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/diagnostic.h @@ -0,0 +1,23 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#ifndef DIAGNOSTIC_H +#define DIAGNOSTIC_H + +void scsiSendDiagnostic(); +void scsiReceiveDiagnostic(); + +#endif \ No newline at end of file diff --git a/software/SCSI2SD/SCSI2SD.cydsn/disk.c b/software/SCSI2SD/SCSI2SD.cydsn/disk.c new file mode 100755 index 0000000..ad0fac5 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/disk.c @@ -0,0 +1,697 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#include "device.h" +#include "scsi.h" +#include "disk.h" + +#include + +// Global +BlockDevice blockDev; +Transfer transfer; + +static void startRead(int nextBlock); +static int sdInit(); + +static void doFormatUnit() +{ + // Low-level formatting is not required. + // Nothing left to do. +} + +static void doReadCapacity() +{ + uint32 lba = (((uint32) scsiDev.cdb[2]) << 24) + + (((uint32) scsiDev.cdb[3]) << 16) + + (((uint32) scsiDev.cdb[4]) << 8) + + scsiDev.cdb[5]; + int pmi = scsiDev.cdb[8] & 1; + + if (!pmi && lba) + { + // error. + // We don't do anything with the "partial medium indicator", and + // assume that delays are constant across each block. But the spec + // says we must return this error if pmi is specified incorrectly. + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.phase = STATUS; + } + else if (blockDev.capacity > 0) + { + uint32 highestBlock = blockDev.capacity - 1; + + scsiDev.data[0] = highestBlock >> 24; + scsiDev.data[1] = highestBlock >> 16; + scsiDev.data[2] = highestBlock >> 8; + scsiDev.data[3] = highestBlock; + + scsiDev.data[4] = blockDev.bs >> 24; + scsiDev.data[5] = blockDev.bs >> 16; + scsiDev.data[6] = blockDev.bs >> 8; + scsiDev.data[7] = blockDev.bs; + scsiDev.dataLen = 8; + scsiDev.phase = DATA_IN; + } + else + { + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = NOT_READY; + scsiDev.sense.asc = MEDIUM_NOT_PRESENT; + scsiDev.phase = STATUS; + } +} + +static void doWrite(uint32 lba, uint32 blocks) +{ + if (blockDev.state & DISK_WP) + { + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = WRITE_PROTECTED; + scsiDev.phase = STATUS; + } + else if (((uint64) lba) + blocks > blockDev.capacity) + { + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + scsiDev.phase = STATUS; + } + else + { + transfer.dir = TRANSFER_WRITE; + transfer.lba = lba; + transfer.blocks = blocks; + transfer.currentBlock = 0; + scsiDev.phase = DATA_OUT; + scsiDev.dataLen = SCSI_BLOCK_SIZE; + } +} + + +static void doRead(uint32 lba, uint32 blocks) +{ + if (((uint64) lba) + blocks > blockDev.capacity) + { + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + scsiDev.phase = STATUS; + } + else + { + transfer.dir = TRANSFER_READ; + transfer.lba = lba; + transfer.blocks = blocks; + transfer.currentBlock = 0; + scsiDev.phase = DATA_IN; + scsiDev.dataLen = 0; // No data yet + startRead(0); + } +} + +static void doSeek(uint32 lba) +{ + if (lba >= blockDev.capacity) + { + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + scsiDev.phase = STATUS; + } +} + +static int doTestUnitReady() +{ + int ready = 1; + if (!(blockDev.state & DISK_STARTED)) + { + ready = 0; + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = NOT_READY; + scsiDev.sense.asc = LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED; + scsiDev.phase = STATUS; + } + else if (!(blockDev.state & DISK_PRESENT)) + { + ready = 0; + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = NOT_READY; + scsiDev.sense.asc = MEDIUM_NOT_PRESENT; + scsiDev.phase = STATUS; + } + else if (!(blockDev.state & DISK_INITIALISED)) + { + ready = 0; + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = NOT_READY; + scsiDev.sense.asc = LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE; + scsiDev.phase = STATUS; + } + return ready; +} + +// Handle direct-access scsi device commands +int scsiDiskCommand() +{ + int commandHandled = 1; + + uint8 command = scsiDev.cdb[0]; + if (command == 0x1B) + { + // START STOP UNIT + // Enable or disable media access operations. + // Ignore load/eject requests. We can't do that. + //int immed = scsiDev.cdb[1] & 1; + int start = scsiDev.cdb[4] & 1; + + if (start) + { + blockDev.state = blockDev.state | DISK_STARTED; + if (!(blockDev.state & DISK_INITIALISED)) + { + if (sdInit()) + { + blockDev.state = blockDev.state | DISK_INITIALISED; + } + } + } + else + { + blockDev.state = blockDev.state & (-1 ^ DISK_STARTED); + } + } + else if (command == 0x00) + { + // TEST UNIT READY + doTestUnitReady(); + } + else if (!doTestUnitReady()) + { + // Status and sense codes already set by doTestUnitReady + } + else if (command == 0x04) + { + // FORMAT UNIT + doFormatUnit(); + } + else if (command == 0x08) + { + // READ(6) + uint32 lba = + (((uint32) scsiDev.cdb[1] & 0x1F) << 16) + + (((uint32) scsiDev.cdb[2]) << 8) + + scsiDev.cdb[3]; + uint32 blocks = scsiDev.cdb[4]; + if (blocks == 0) blocks = 256; + doRead(lba, blocks); + } + + else if (command == 0x28) + { + // READ(10) + // Ignore all cache control bits - we don't support a memory cache. + + uint32 lba = + (((uint32) scsiDev.cdb[2]) << 24) + + (((uint32) scsiDev.cdb[3]) << 16) + + (((uint32) scsiDev.cdb[4]) << 8) + + scsiDev.cdb[5]; + uint32 blocks = + (((uint32) scsiDev.cdb[7]) << 8) + + scsiDev.cdb[8]; + + doRead(lba, blocks); + } + + else if (command == 0x25) + { + // READ CAPACITY + doReadCapacity(); + } + + else if (command == 0x0B) + { + // SEEK(6) + uint32 lba = + (((uint32) scsiDev.cdb[1] & 0x1F) << 16) + + (((uint32) scsiDev.cdb[2]) << 8) + + scsiDev.cdb[3]; + + doSeek(lba); + } + + else if (command == 0x2B) + { + // SEEK(10) + uint32 lba = + (((uint32) scsiDev.cdb[2]) << 24) + + (((uint32) scsiDev.cdb[3]) << 16) + + (((uint32) scsiDev.cdb[4]) << 8) + + scsiDev.cdb[5]; + + doSeek(lba); + } + else if (command == 0x0A) + { + // WRITE(6) + uint32 lba = + (((uint32) scsiDev.cdb[1] & 0x1F) << 16) + + (((uint32) scsiDev.cdb[2]) << 8) + + scsiDev.cdb[3]; + uint32 blocks = scsiDev.cdb[4]; + if (blocks == 0) blocks = 256; + doWrite(lba, blocks); + } + + else if (command == 0x2A) + { + // WRITE(10) + // Ignore all cache control bits - we don't support a memory cache. + + uint32 lba = + (((uint32) scsiDev.cdb[2]) << 24) + + (((uint32) scsiDev.cdb[3]) << 16) + + (((uint32) scsiDev.cdb[4]) << 8) + + scsiDev.cdb[5]; + uint32 blocks = + (((uint32) scsiDev.cdb[7]) << 8) + + scsiDev.cdb[8]; + + doWrite(lba, blocks); + } + else if (command == 0x36) + { + // LOCK UNLOCK CACHE + // We don't have a cache to lock data into. do nothing. + } + else if (command == 0x34) + { + // PRE-FETCH. + // We don't have a cache to pre-fetch into. do nothing. + } + else if (command == 0x1E) + { + // PREVENT ALLOW MEDIUM REMOVAL + // Not much we can do to prevent the user removing the SD card. + // do nothing. + } + else if (command == 0x01) + { + // REZERO UNIT + // Set the lun to a vendor-specific state. Ignore. + } + else if (command == 0x35) + { + // SYNCHRONIZE CACHE + // We don't have a cache. do nothing. + } + else + { + commandHandled = 0; + } + + return commandHandled; +} + + +static uint8 sdCrc7(uint8* chr, uint8 cnt, uint8 crc) +{ + uint8 a; + for(a = 0; a < cnt; a++) + { + uint8 Data = chr[a]; + uint8 i; + for(i = 0; i < 8; i++) + { + crc <<= 1; + if( (Data & 0x80) ^ (crc & 0x80) ) {crc ^= 0x09;} + Data <<= 1; + } + } + return crc & 0x7F; +} + +// Read and write 1 byte. +static uint8 sdSpiByte(uint8 value) +{ + SDCard_WriteTxData(value); + while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE)) + {} + while (!SDCard_GetRxBufferSize()) {} + return SDCard_ReadRxData(); +} + +static void sdSendCommand(uint8 cmd, uint32 param) +{ + uint8 send[6]; + + send[0] = cmd | 0x40; + send[1] = param >> 24; + send[2] = param >> 16; + send[3] = param >> 8; + send[4] = param; + send[5] = (sdCrc7(send, 5, 0) << 1) | 1; + + for(cmd = 0; cmd < sizeof(send); cmd++) + { + sdSpiByte(send[cmd]); + } +} + +static uint8 sdReadResp() +{ + uint8 v; + uint8 i = 128; + do + { + v = sdSpiByte(0xFF); + } while(i-- && (v == 0xFF)); + return v; +} + +static uint8 sdWaitResp() +{ + uint8 v; + uint8 i = 255; + do + { + v = sdSpiByte(0xFF); + } while(i-- && (v != 0xFE)); + return v; +} + + +static uint8 sdCommandAndResponse(uint8 cmd, uint32 param) +{ + SDCard_ClearRxBuffer(); + sdSpiByte(0xFF); + sdSendCommand(cmd, param); + return sdReadResp(); +} + + +static int sdInit() +{ + int result = 0; + SD_CS_Write(1); // Set CS inactive (active low) + SD_Init_Clk_Start(); // Turn on the slow 400KHz clock + SD_Clk_Ctl_Write(0); // Select the 400KHz clock source. + SDCard_Start(); // Enable SPI hardware + + // Power on sequence. 74 clock cycles of a "1" while CS unasserted. + int i; + for (i = 0; i < 10; ++i) + { + sdSpiByte(0xFF); + } + + SD_CS_Write(0); // Set CS active (active low) + CyDelayUs(1); + + uint8 v = sdCommandAndResponse(0, 0); + if(v != 1){goto bad;} + + // TODO CMD8 + valid CC for ver2 + cards. arg 0x00..01AA + + + // TODO SDv2 support: ACMD41, fallback to CMD1 + + v = sdCommandAndResponse(1, 0); + for(i=0;v != 0 && i<50;++i){ + CyDelay(50); + v = sdCommandAndResponse(1, 0); + } + if(v){goto bad;} + + v = sdCommandAndResponse(16, SCSI_BLOCK_SIZE); //Force sector size + if(v){goto bad;} + v = sdCommandAndResponse(59, 0); //crc off + if(v){goto bad;} + + // now set the sd card up for full speed + SD_Data_Clk_Start(); // Turn on the fast clock + SD_Clk_Ctl_Write(1); // Select the fast clock source. + SD_Init_Clk_Stop(); // Stop the slow clock. + + v = sdCommandAndResponse(0x9, 0); + if(v){goto bad;} + v = sdWaitResp(); + if (v != 0xFE) { goto bad; } + uint8 buf[16]; + for (i = 0; i < 16; ++i) + { + buf[i] = sdSpiByte(0xFF); + } + sdSpiByte(0xFF); // CRC + sdSpiByte(0xFF); // CRC + uint32 c_size = (((((uint32)buf[6]) & 0x3) << 16) | (((uint32)buf[7]) << 8) | buf[8]) >> 6; + uint32 c_mult = (((((uint32)buf[9]) & 0x3) << 8) | ((uint32)buf[0xa])) >> 7; + uint32 sectorSize = buf[5] & 0x0F; + blockDev.capacity = ((c_size+1) * ((uint64)1 << (c_mult+2)) * ((uint64)1 << sectorSize)) / SCSI_BLOCK_SIZE; + result = 1; + goto out; + +bad: + blockDev.capacity = 0; + +out: + return result; + +} + +static void startRead(int nextBlock) +{ +// TODO 4Gb limit +// NOTE: CMD17 is NOT in hex. decimal 17. + uint8 v = sdCommandAndResponse(17, ((uint32)SCSI_BLOCK_SIZE) * (transfer.lba + transfer.currentBlock + nextBlock)); + if (v) + { + scsiDiskReset(); + + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = HARDWARE_ERROR; + scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; + scsiDev.phase = STATUS; + } +} + +static int readReady() +{ + uint8 v = sdWaitResp(); + if (v == 0xFF) + { + return 0; + } + else if (v == 0xFE) + { + return 1; + } + else + { + scsiDiskReset(); + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = HARDWARE_ERROR; + scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; + scsiDev.phase = STATUS; + return 0; + } +} +static void readSector() +{ +// TODO this is slow. Really slow. +// Even if we don't use DMA, we still want to read/write multiple bytes +// at a time. +/* + int i; + for (i = 0; i < SCSI_BLOCK_SIZE; ++i) + { + scsiDev.data[i] = sdSpiByte(0xFF); + } +*/ + + // We have a spi FIFO of 4 bytes. use it. + // This is much better, byut after 4 bytes we're still + // blocking a bit. + int i; + for (i = 0; i < SCSI_BLOCK_SIZE; i+=4) + { + SDCard_WriteTxData(0xFF); + SDCard_WriteTxData(0xFF); + SDCard_WriteTxData(0xFF); + SDCard_WriteTxData(0xFF); + + while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE)) + {} + scsiDev.data[i] = SDCard_ReadRxData(); + scsiDev.data[i+1] = SDCard_ReadRxData(); + scsiDev.data[i+2] = SDCard_ReadRxData(); + scsiDev.data[i+3] = SDCard_ReadRxData(); + + } + + + sdSpiByte(0xFF); // CRC + sdSpiByte(0xFF); // CRC + scsiDev.dataLen = SCSI_BLOCK_SIZE; + scsiDev.dataPtr = 0; +} + +static void writeSector() +{ + uint8 v = sdCommandAndResponse(24, ((uint32)SCSI_BLOCK_SIZE) * (transfer.lba + transfer.currentBlock)); + if (v) + { + scsiDiskReset(); + + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = HARDWARE_ERROR; + scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; + scsiDev.phase = STATUS; + } + else + { + SDCard_WriteTxData(0xFE); + int i; + for (i = 0; i < SCSI_BLOCK_SIZE; ++i) + { + SDCard_WriteTxData(scsiDev.data[i]); + } + while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE)) + {} + sdSpiByte(0x00); // CRC + sdSpiByte(0x00); // CRC + SDCard_ClearRxBuffer(); + v = sdSpiByte(0x00); // Response + if (((v & 0x1F) >> 1) != 0x2) // Accepted. + { + scsiDiskReset(); + + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = HARDWARE_ERROR; + scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; + scsiDev.phase = STATUS; + } + else + { + // Wait for the card to come out of busy. + v = sdSpiByte(0xFF); + while (v == 0) + { + v = sdSpiByte(0xFF); + } + uint8 r1 = sdCommandAndResponse(13, 0); // send status + uint8 r2 = sdSpiByte(0xFF); + if (r1 || r2) + { + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = HARDWARE_ERROR; + scsiDev.sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED; + scsiDev.phase = STATUS; + } + } + } +} + +void scsiDiskPoll() +{ + if (scsiDev.phase == DATA_IN && + transfer.currentBlock != transfer.blocks) + { + if (scsiDev.dataLen == 0) + { + if (readReady()) + { + readSector(); + if ((transfer.currentBlock + 1) < transfer.blocks) + { + startRead(1); // Tell SD card to grab data while we send + // buffer to SCSI. + } + } + } + else if (scsiDev.dataPtr == scsiDev.dataLen) + { + scsiDev.dataLen = 0; + scsiDev.dataPtr = 0; + transfer.currentBlock++; + if (transfer.currentBlock >= transfer.blocks) + { + scsiDev.phase = STATUS; + scsiDiskReset(); + } + } + } + else if (scsiDev.phase == DATA_OUT && + transfer.currentBlock != transfer.blocks) + { + if (scsiDev.dataPtr == SCSI_BLOCK_SIZE) + { + writeSector(); + scsiDev.dataPtr = 0; + transfer.currentBlock++; + if (transfer.currentBlock >= transfer.blocks) + { + scsiDev.dataLen = 0; + scsiDev.phase = STATUS; + scsiDiskReset(); + } + } + } +} + +void scsiDiskReset() +{ + // todo if SPI command in progress, cancel it. + scsiDev.dataPtr = 0; + scsiDev.savedDataPtr = 0; + scsiDev.dataLen = 0; + transfer.lba = 0; + transfer.blocks = 0; + transfer.currentBlock = 0; +} + +void scsiDiskInit() +{ + blockDev.bs = SCSI_BLOCK_SIZE; + blockDev.capacity = 0; + scsiDiskReset(); + + // Don't require the host to send us a START STOP UNIT command + blockDev.state = DISK_STARTED; + if (SD_WP_Read()) + { + blockDev.state = blockDev.state | DISK_WP; + } + + if (SD_CD_Read() == 0) + { + blockDev.state = blockDev.state | DISK_PRESENT; + +// todo IF FAILS, TRY AGAIN LATER. +// 5000 works well with the Mac. + CyDelay(5000); // allow the card to wake up. + if (sdInit()) + { + blockDev.state = blockDev.state | DISK_INITIALISED; + } + } +} + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/disk.h b/software/SCSI2SD/SCSI2SD.cydsn/disk.h new file mode 100755 index 0000000..5d2d04d --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/disk.h @@ -0,0 +1,59 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#ifndef DISK_H +#define DISK_H + +typedef enum +{ + DISK_STARTED = 1, // Controlled via START STOP UNIT + DISK_PRESENT = 2, // SD card is physically present + DISK_INITIALISED = 4, // SD card responded to init sequence + DISK_WP = 8 // Write-protect. +} DISK_STATE; + +typedef enum +{ + TRANSFER_READ, + TRANSFER_WRITE +} TRANSFER_DIR; + +typedef struct +{ + uint32 bs; // Block size. + uint32 capacity; // In blocks. + + int state; +} BlockDevice; + +typedef struct +{ + int dir; + uint32 lba; + uint32 blocks; + + uint32 currentBlock; +} Transfer; + +extern BlockDevice blockDev; +extern Transfer transfer; + +void scsiDiskInit(); +void scsiDiskReset(); +void scsiDiskPoll(); +int scsiDiskCommand(); + +#endif diff --git a/software/SCSI2SD/SCSI2SD.cydsn/geometry.c b/software/SCSI2SD/SCSI2SD.cydsn/geometry.c new file mode 100755 index 0000000..5665ae5 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/geometry.c @@ -0,0 +1,168 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#include "geometry.h" +#include "scsi.h" + +#include + +// Standard mapping according to ECMA-107 and ISO/IEC 9293:1994 +// Sector always starts at 1. There is no 0 sector. +uint64 CHS2LBA(uint32 c, uint8 h, uint32 s) +{ + return ( + (((uint64)c) * SCSI_HEADS_PER_CYLINDER + h) * + (uint64) SCSI_SECTORS_PER_TRACK + ) + (s - 1); +} + + +void LBA2CHS(uint32 lba, uint32* c, uint8* h, uint32* s) +{ + *c = lba / (SCSI_SECTORS_PER_TRACK * SCSI_HEADS_PER_CYLINDER); + *h = (lba / SCSI_SECTORS_PER_TRACK) % SCSI_HEADS_PER_CYLINDER; + *s = (lba % SCSI_SECTORS_PER_TRACK) + 1; +} + +uint64 scsiByteAddress(int format, const uint8* addr) +{ + uint64 result; + switch (format) + { + case ADDRESS_BLOCK: + { + uint32 lba = + (((uint32) addr[0]) << 24) + + (((uint32) addr[1]) << 16) + + (((uint32) addr[2]) << 8) + + addr[3]; + + result = (uint64) SCSI_BLOCK_SIZE * lba; + } break; + + case ADDRESS_PHYSICAL_BYTE: + { + uint32 cyl = + (((uint32) addr[0]) << 16) + + (((uint32) addr[1]) << 8) + + addr[2]; + + uint8 head = addr[3]; + + uint32 bytes = + (((uint32) addr[4]) << 24) + + (((uint32) addr[5]) << 16) + + (((uint32) addr[6]) << 8) + + addr[7]; + + result = CHS2LBA(cyl, head, 1) * (uint64) SCSI_SECTOR_SIZE + bytes; + } break; + + case ADDRESS_PHYSICAL_SECTOR: + { + uint32 cyl = + (((uint32) addr[0]) << 16) + + (((uint32) addr[1]) << 8) + + addr[2]; + + uint8 head = scsiDev.data[3]; + + uint32 sector = + (((uint32) addr[4]) << 24) + + (((uint32) addr[5]) << 16) + + (((uint32) addr[6]) << 8) + + addr[7]; + + result = CHS2LBA(cyl, head, sector) * (uint64) SCSI_SECTOR_SIZE; + } break; + + default: + result = -1; + } + + return result; +} + + +void scsiSaveByteAddress(int format, uint64 byteAddr, uint8* buf) +{ + uint32 lba = byteAddr / SCSI_BLOCK_SIZE; + uint32 byteOffset = byteAddr % SCSI_BLOCK_SIZE; + + switch (format) + { + case ADDRESS_BLOCK: + { + buf[0] = lba >> 24; + buf[1] = lba >> 16; + buf[2] = lba >> 8; + buf[3] = lba; + + buf[4] = 0; + buf[5] = 0; + buf[6] = 0; + buf[7] = 0; + } break; + + case ADDRESS_PHYSICAL_BYTE: + { + uint32 cyl; + uint8 head; + uint32 sector; + + LBA2CHS(lba, &cyl, &head, §or); + + uint32 bytes = sector * SCSI_SECTOR_SIZE + byteOffset; + + buf[0] = cyl >> 16; + buf[1] = cyl >> 8; + buf[2] = cyl; + + buf[3] = head; + + buf[4] = bytes >> 24; + buf[5] = bytes >> 16; + buf[6] = bytes >> 8; + buf[7] = bytes; + } break; + + case ADDRESS_PHYSICAL_SECTOR: + { + uint32 cyl; + uint8 head; + uint32 sector; + + LBA2CHS(lba, &cyl, &head, §or); + + buf[0] = cyl >> 16; + buf[1] = cyl >> 8; + buf[2] = cyl; + + buf[3] = head; + + buf[4] = sector >> 24; + buf[5] = sector >> 16; + buf[6] = sector >> 8; + buf[7] = sector; + } break; + + default: + memset(buf, 0, 8); + } + +} + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/geometry.h b/software/SCSI2SD/SCSI2SD.cydsn/geometry.h new file mode 100755 index 0000000..daf0fdd --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/geometry.h @@ -0,0 +1,51 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#ifndef GEOMETRY_H +#define GEOMETRY_H + +#include "device.h" + +// We make some assumptions that the block size and sector size +// are always equal. +#define SCSI_BLOCK_SIZE 512 +#define SCSI_SECTOR_SIZE 512 + +// Max allowed by legacy IBM-PC Bios (6 bits) +#define SCSI_SECTORS_PER_TRACK 63 + +// MS-DOS up to 7.10 will crash on 256 heads. +#define SCSI_HEADS_PER_CYLINDER 255 + +typedef enum +{ + ADDRESS_BLOCK = 0, + ADDRESS_PHYSICAL_BYTE = 4, + ADDRESS_PHYSICAL_SECTOR = 5 +} SCSI_ADDRESS_FORMAT; + + +uint64 CHS2LBA(uint32 c, uint8 h, uint32 s); +void LBA2CHS(uint32 lba, uint32* c, uint8* h, uint32* s); + +// Convert an address in the given SCSI_ADDRESS_FORMAT to +// a linear byte address. +// addr must be >= 8 bytes. +uint64 scsiByteAddress(int format, const uint8* addr); +void scsiSaveByteAddress(int format, uint64 byteAddr, uint8* buf); + + +#endif diff --git a/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c b/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c new file mode 100755 index 0000000..75fac44 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c @@ -0,0 +1,160 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#include "device.h" +#include "scsi.h" +#include "inquiry.h" + +#include + +static const uint8 StandardResponse[] = +{ +0x00, // "Direct-access device". AKA standard hard disk +0x00, // device type qualifier +0x02, // Complies with ANSI SCSI-2. +0x02, // SCSI-2 Inquiry response +31, // standard length +0, 0, //Reserved +0, // We don't support anything at all +'c','o','d','e','s','r','c',' ', +'S','C','S','I','2','S','D',' ',' ',' ',' ',' ',' ',' ',' ',' ', +'2','.','0','a' +}; + +static const uint8 SupportedVitalPages[] = +{ +0x00, // "Direct-access device". AKA standard hard disk +0x00, // Page Code +0x00, // Reserved +0x04, // Page length +0x00, // Support "Supported vital product data pages" +0x80, // Support "Unit serial number page" +0x81, // Support "Implemented operating definition page" +0x82 // Support "ASCII Implemented operating definition page" +}; + +static const uint8 UnitSerialNumber[] = +{ +0x00, // "Direct-access device". AKA standard hard disk +0x80, // Page Code +0x00, // Reserved +0x10, // Page length +'c','o','d','e','s','r','c','-','1','2','3','4','5','6','7','8' +}; + +static const uint8 ImpOperatingDefinition[] = +{ +0x00, // "Direct-access device". AKA standard hard disk +0x81, // Page Code +0x00, // Reserved +0x03, // Page length +0x03, // Current: SCSI-2 operating definition +0x03, // Default: SCSI-2 operating definition +0x03 // Supported (list): SCSI-2 operating definition. +}; + +static const uint8 AscImpOperatingDefinition[] = +{ +0x00, // "Direct-access device". AKA standard hard disk +0x82, // Page Code +0x00, // Reserved +0x07, // Page length +0x06, // Ascii length +'S','C','S','I','-','2' +}; + +void scsiInquiry() +{ + uint8 evpd = scsiDev.cdb[1] & 1; // enable vital product data. + uint8 pageCode = scsiDev.cdb[2]; + uint8 lun = scsiDev.cdb[1] >> 5; + uint32 allocationLength = scsiDev.cdb[4]; + if (allocationLength == 0) allocationLength = 256; + + if (!evpd) + { + if (pageCode) + { + // error. + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.phase = STATUS; + } + else + { + memcpy(scsiDev.data, StandardResponse, sizeof(StandardResponse)); + scsiDev.dataLen = sizeof(StandardResponse); + scsiDev.phase = DATA_IN; + + if (!lun) scsiDev.unitAttention = 0; + } + } + else if (pageCode == 0x00) + { + memcpy(scsiDev.data, SupportedVitalPages, sizeof(SupportedVitalPages)); + scsiDev.dataLen = sizeof(SupportedVitalPages); + scsiDev.phase = DATA_IN; + } + else if (pageCode == 0x80) + { + memcpy(scsiDev.data, UnitSerialNumber, sizeof(UnitSerialNumber)); + scsiDev.dataLen = sizeof(UnitSerialNumber); + scsiDev.phase = DATA_IN; + } + else if (pageCode == 0x81) + { + memcpy( + scsiDev.data, + ImpOperatingDefinition, + sizeof(ImpOperatingDefinition)); + scsiDev.dataLen = sizeof(ImpOperatingDefinition); + scsiDev.phase = DATA_IN; + } + else if (pageCode == 0x82) + { + memcpy( + scsiDev.data, + AscImpOperatingDefinition, + sizeof(AscImpOperatingDefinition)); + scsiDev.dataLen = sizeof(AscImpOperatingDefinition); + scsiDev.phase = DATA_IN; + } + else + { + // error. + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.phase = STATUS; + } + + + if (scsiDev.phase == DATA_IN && scsiDev.dataLen > allocationLength) + { + // Spec 8.2.5 requires us to simply truncate the response. + scsiDev.dataLen = allocationLength; + } + + + // Set the first byte to indicate LUN presence. + if (lun) // We only support lun 0 + { + scsiDev.data[0] = 0x7F; + } +} + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/inquiry.h b/software/SCSI2SD/SCSI2SD.cydsn/inquiry.h new file mode 100755 index 0000000..d068796 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/inquiry.h @@ -0,0 +1,22 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#ifndef INQUIRY_H +#define INQUIRY_H + +void scsiInquiry(); + +#endif diff --git a/software/SCSI2SD/SCSI2SD.cydsn/led.h b/software/SCSI2SD/SCSI2SD.cydsn/led.h new file mode 100755 index 0000000..48e1b83 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/led.h @@ -0,0 +1,25 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#ifndef LED_H +#define LED_H + +#include "device.h" + +#define ledOn() LED1_Write(0) +#define ledOff() LED1_Write(1) + +#endif \ No newline at end of file diff --git a/software/SCSI2SD/SCSI2SD.cydsn/loopback.c b/software/SCSI2SD/SCSI2SD.cydsn/loopback.c new file mode 100755 index 0000000..411899a --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/loopback.c @@ -0,0 +1,122 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#include "loopback.h" +#include "device.h" + +// Return true if all inputs are un-asserted (1) +// Note that CyPins returns non-zero if pin is active. It does NOT +// necessarily return 1. +static int test_initial_inputs(void) +{ + uint8 dbx = SCSI_In_DBx_Read(); + int result = + (dbx == 0xFF) && + CyPins_ReadPin(SCSI_In_DBP) && + CyPins_ReadPin(SCSI_In_ATN) && + CyPins_ReadPin(SCSI_In_BSY) && + CyPins_ReadPin(SCSI_In_ACK) && + CyPins_ReadPin(SCSI_In_RST) && + CyPins_ReadPin(SCSI_In_MSG) && + CyPins_ReadPin(SCSI_In_SEL) && + CyPins_ReadPin(SCSI_In_CD) && + CyPins_ReadPin(SCSI_In_REQ) && + CyPins_ReadPin(SCSI_In_IO); + + return result; +} + +static int test_data_lines(void) +{ + int result = 1; + int i; + for (i = 0; i < 8; ++i) + { + // We write using Active High + SCSI_Out_DBx_Write(1 << i); + CyDelay(1); // ms + + // And expect an Active Low response. + uint8 dbx = SCSI_In_DBx_Read(); + result = result && (dbx == (0xFF ^ (1 << i))); + } + SCSI_Out_DBx_Write(0); + return result; +} + +static int test_data_10MHz(void) +{ + // 10MHz = 100ns period. + // We'll try and go high -> low -> high in 100ns. + // At 66MHz, 50ns ~= 3 cycles. + + int result = 1; + int i; + for (i = 0; i < 100; ++i) + { + // We write using Active High + SCSI_Out_DBx_Write(0xFF); + CyDelayCycles(3); + // And expect an Active Low response. + uint8 dbx = SCSI_In_DBx_Read(); + result = result && (dbx == 0); + + // We write using Active High + SCSI_Out_DBx_Write(0); + CyDelayCycles(3); + // And expect an Active Low response. + dbx = SCSI_In_DBx_Read(); + result = result && (dbx == 0xFF); + } + SCSI_Out_DBx_Write(0); + return result; +} + +static void test_error(void) +{ + // Toggle LED. + while (1) + { + LED1_Write(0); + CyDelay(250); // ms + LED1_Write(1); + CyDelay(250); // ms + } +} + +static void test_success(void) +{ + // Toggle LED. + while (1) + { + LED1_Write(0); + CyDelay(1000); // ms + LED1_Write(1); + CyDelay(1000); // ms + } +} +void scsi2sd_test_loopback(void) +{ + if (!test_initial_inputs() || !test_data_lines() || !test_data_10MHz()) + { + test_error(); + } + else + { + test_success(); + } +} \ No newline at end of file diff --git a/software/SCSI2SD/SCSI2SD.cydsn/loopback.h b/software/SCSI2SD/SCSI2SD.cydsn/loopback.h new file mode 100755 index 0000000..1d1b7bf --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/loopback.h @@ -0,0 +1,30 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#ifndef SCSI2SD_LOOPBACK_H +#define SCSI2SD_LOOPBACK_H + +// Loopback test +// Ensure we can read-back whatever we write to the SCSI bus. +// This testing should be performed in isolation, with the +// terminator jumper and terminator power jumper installed. +// ie. do not connect a SCSI cable and plug us in to another +// device. +void scsi2sd_test_loopback(void); + + +#endif // SCSI2SD_POST_H diff --git a/software/SCSI2SD/SCSI2SD.cydsn/main.c b/software/SCSI2SD/SCSI2SD.cydsn/main.c new file mode 100755 index 0000000..e6f18e4 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/main.c @@ -0,0 +1,53 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#include "device.h" +// #include "blinky.h" +// #include "loopback.h" +#include "scsi.h" +#include "disk.h" +#include "led.h" + +const char* Notice = "Copyright (C) 2013 Michael McMaster "; + +void main() +{ + // scsi2sd_test_blinky(); // Initial test. Will not return. + // scsi2sd_test_loopback(); // Second test. Will not return. + ledOff(); + + /* Uncomment this line to enable global interrupts. */ + // MM: Try to avoid interrupts completely, as it will screw with our + // timing. + CyGlobalIntEnable; + + // TODO insert any initialisation code here. + scsiInit(0, 1); // ID 0 is mac boot disk + scsiDiskInit(); + + // Reading jumpers + // Is SD card detect asserted ? + + // TODO POST ? + + while (1) + { + scsiPoll(); + scsiDiskPoll(); + } +} + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/mode.c b/software/SCSI2SD/SCSI2SD.cydsn/mode.c new file mode 100755 index 0000000..89639cc --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/mode.c @@ -0,0 +1,322 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#include "device.h" +#include "scsi.h" +#include "mode.h" +#include "disk.h" + +#include + +static const uint8 DisconnectReconnectPage[] = +{ +0x02, // Page code +0x0E, // Page length +0, // Buffer full ratio +0, // Buffer empty ratio +0x00, 10, // Bus inactivity limit, 100us increments. Allow 1ms. +0x00, 0x00, // Disconnect time limit +0x00, 0x00, // Connect time limit +0x00, 0x00, // Maximum burst size +0x00 ,// DTDC. Not used. +0x00, 0x00, 0x00 // Reserved +}; + +static const uint8 FormatDevicePage[] = +{ +x03, // Page code +0x16, // Page length +0x00, 0x00, // Single zone +0x00, 0x00, // No alternate sectors +0x00, 0x00, // No alternate tracks +0x00, 0x00, // No alternate tracks per lun +0x00, SCSI_SECTORS_PER_TRACK, // Sectors per track +SCSI_SECTOR_SIZE >> 8, SCSI_SECTOR_SIZE & 0xFF, // Data bytes per physical sector +0x00, 0x01, // Interleave +0x00, 0x00, // Track skew factor +0x00, 0x00, // Cylinder skew factor +0xC0, // SSEC(set) HSEC(set) RMB SURF +0x00, 0x00, 0x00 // Reserved +}; + +static const uint8 RigidDiskDriveGeometry[] = +{ +0x04, // Page code +0x16, // Page length +0xFF, 0xFF, 0xFF, // Number of cylinders +SCSI_HEADS_PER_CYLINDER, // Number of heads +0xFF, 0xFF, 0xFF, // Starting cylinder-write precompensation +0xFF, 0xFF, 0xFF, // Starting cylinder-reduced write current +0x00, 0x1, // Drive step rate (units of 100ns) +0x00, 0x00, 0x00, // Landing zone cylinder +0x00, // RPL +0x00, // Rotational offset +0x00, // Reserved +5400 >> 8, 5400 & 0xFF, // Medium rotation rate (RPM) +0x00, 0x00 // Reserved +}; + +static const uint8 CachingPage[] = +{ +0x08, // Page Code +0x0A, // Page length +0x01, // Read cache disable +0x00, // No useful rention policy. +0x00, 0x00, // Pre-fetch always disabled +0x00, 0x00, // Minimum pre-fetch +0x00, 0x00, // Maximum pre-fetch +0x00, 0x00, // Maximum pre-fetch ceiling +}; + +static const uint8 ControlModePage[] = +{ +0x0A, // Page code +0x06, // Page length +0x00, // No logging +0x01, // Disable tagged queuing +0x00, // No async event notifications +0x00, // Reserved +0x00, 0x00 // AEN holdoff period. +}; + +static void pageIn(int pc, int dataIdx, const uint8* pageData, int pageLen) +{ + memcpy(&scsiDev.data[dataIdx], pageData, pageLen); + + if (pc == 0x01) // Mask out (un)changable values + { + memset(&scsiDev.data[dataIdx+2], 0, pageLen - 2); + } +} + +static void doModeSense( + int sixByteCmd, int dbd, int pc, int pageCode, int allocLength) +{ + // TODO Apple HD SC Drive Setup requests Page 3 (FormatDevicePage) with an + // allocLength of 0x20. We need 0x24 if we include a block descriptor, and + // thus return CHECK CONDITION. A block descriptor is optional, so we + // chose to ignore it. + // TODO make configurable + dbd = 1; + + if (pc == 0x03) // Saved Values not supported. + { + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = SAVING_PARAMETERS_NOT_SUPPORTED; + scsiDev.phase = STATUS; + } + else + { + ////////////// Mode Parameter Header + //////////////////////////////////// + + // Skip the Mode Data Length, we set that last. + int idx = 1; + if (!sixByteCmd) ++idx; + + scsiDev.data[idx++] = 0; // Medium type. 0 = default + + // Device-specific parameter. Contains cache bits (0) and + // a Write-Protect bit. + scsiDev.data[idx++] = (blockDev.state & DISK_WP) ? 0x80 : 0; + + if (sixByteCmd) + { + if (dbd) + { + scsiDev.data[idx++] = 0; // No block descriptor + } + else + { + // One block descriptor of length 8 bytes. + scsiDev.data[idx++] = 8; + } + } + else + { + scsiDev.data[idx++] = 0; // Reserved + scsiDev.data[idx++] = 0; // Reserved + if (dbd) + { + scsiDev.data[idx++] = 0; // No block descriptor + scsiDev.data[idx++] = 0; // No block descriptor + } + else + { + // One block descriptor of length 8 bytes. + scsiDev.data[idx++] = 0; + scsiDev.data[idx++] = 8; + } + } + + ////////////// Block Descriptor + //////////////////////////////////// + if (!dbd) + { + scsiDev.data[idx++] = 0; // Density code. Reserved for direct-access + // Number of blocks + // Zero == all remaining blocks shall have the medium + // characteristics specified. + scsiDev.data[idx++] = 0; + scsiDev.data[idx++] = 0; + scsiDev.data[idx++] = 0; + + scsiDev.data[idx++] = 0; // reserved + + // Block length + scsiDev.data[idx++] = SCSI_BLOCK_SIZE >> 16; + scsiDev.data[idx++] = SCSI_BLOCK_SIZE >> 8; + scsiDev.data[idx++] = SCSI_BLOCK_SIZE & 0xFF; + } + + int pageFound = 1; + + switch (pageCode) + { + case 0x3F: + // EVERYTHING + + case 0x02: + pageIn(pc, idx, DisconnectReconnectPage, sizeof(DisconnectReconnectPage)); + idx += sizeof(DisconnectReconnectPage); + if (pageCode != 0x3f) break; + + case 0x03: + pageIn(pc, idx, FormatDevicePage, sizeof(FormatDevicePage)); + idx += sizeof(FormatDevicePage); + if (pageCode != 0x3f) break; + + case 0x04: + { + pageIn(pc, idx, RigidDiskDriveGeometry, sizeof(RigidDiskDriveGeometry)); + + if (pc != 0x01) + { + // Need to fill out the number of cylinders. + uint32 cyl; + uint8 head; + uint32 sector; + LBA2CHS(blockDev.capacity, &cyl, &head, §or); + + scsiDev.data[idx+2] = cyl >> 16; + scsiDev.data[idx+3] = cyl >> 8; + scsiDev.data[idx+4] = cyl; + + memcpy(&scsiDev.data[idx+6], &scsiDev.data[idx+2], 3); + memcpy(&scsiDev.data[idx+9], &scsiDev.data[idx+2], 3); + } + + idx += sizeof(RigidDiskDriveGeometry); + if (pageCode != 0x3f) break; + } + + case 0x08: + pageIn(pc, idx, CachingPage, sizeof(CachingPage)); + idx += sizeof(CachingPage); + if (pageCode != 0x3f) break; + + case 0x0A: + pageIn(pc, idx, ControlModePage, sizeof(ControlModePage)); + idx += sizeof(ControlModePage); + break; + + default: + // Unknown Page Code + pageFound = 0; + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.phase = STATUS; + } + + + if (idx > allocLength) + { + // Initiator may not have space to receive results. + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.phase = STATUS; + } + else if (pageFound) + { + // Go back and fill out the mode data length + if (sixByteCmd) + { + // Cannot currently exceed limits. yay + scsiDev.data[0] = idx - 1; + } + else + { + scsiDev.data[0] = ((idx - 2) >> 8); + scsiDev.data[1] = (idx - 2); + } + + scsiDev.dataLen = idx; + scsiDev.phase = DATA_IN; + } + else + { + // Initiator may not have space to receive results. + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.phase = STATUS; + } + } +} + +int scsiModeCommand() +{ + int commandHandled = 1; + + uint8 command = scsiDev.cdb[0]; + + // We don't currently support the setting of any parameters. + // (ie. no MODE SELECT(6) or MODE SELECT(10) commands) + + if (command == 0x1A) + { + // MODE SENSE(6) + int dbd = scsiDev.cdb[1] & 0x08; // Disable block descriptors + int pc = scsiDev.cdb[2] >> 6; // Page Control + int pageCode = scsiDev.cdb[2] & 0x3F; + int allocLength = scsiDev.cdb[4]; + if (allocLength == 0) allocLength = 256; + doModeSense(1, dbd, pc, pageCode, allocLength); + } + else if (command == 0x5A) + { + // MODE SENSE(10) + int dbd = scsiDev.cdb[1] & 0x08; // Disable block descriptors + int pc = scsiDev.cdb[2] >> 6; // Page Control + int pageCode = scsiDev.cdb[2] & 0x3F; + int allocLength = + (((uint16) scsiDev.cdb[7]) << 8) + + scsiDev.cdb[8]; + doModeSense(0, dbd, pc, pageCode, allocLength); + } + else + { + commandHandled = 0; + } + + return commandHandled; +} + + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/mode.h b/software/SCSI2SD/SCSI2SD.cydsn/mode.h new file mode 100755 index 0000000..c097807 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/mode.h @@ -0,0 +1,22 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#ifndef MODE_H +#define MODE_H + +int scsiModeCommand(); + +#endif diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsi.c b/software/SCSI2SD/SCSI2SD.cydsn/scsi.c new file mode 100755 index 0000000..a5db1f9 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsi.c @@ -0,0 +1,683 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#include "device.h" +#include "scsi.h" +#include "scsiPhy.h" +#include "bits.h" +#include "diagnostic.h" +#include "disk.h" +#include "inquiry.h" +#include "led.h" +#include "mode.h" +#include "disk.h" + +#include + +// Global SCSI device state. +ScsiDevice scsiDev; + +static void enter_SelectionPhase(); +static void process_SelectionPhase(); +static void enter_BusFree(); +static void enter_MessageIn(uint8 message); +static void process_MessageIn(); +static void enter_Status(uint8 status); +static void process_Status(); +static void enter_DataIn(int len); +static void process_DataIn(); +static void process_DataOut(); +static void process_Command(); + +static void doReserveRelease(); + +static void enter_BusFree() +{ + scsiEnterPhase(BUS_FREE); + + ledOff(); + + scsiDev.phase = BUS_FREE; + SCSI_ClearPin(SCSI_Out_BSY); +} + +static void enter_MessageIn(uint8 message) +{ + scsiDev.msgIn = message; + scsiDev.phase = MESSAGE_IN; +} + +static void process_MessageIn() +{ + scsiEnterPhase(MESSAGE_IN); + scsiWrite(scsiDev.msgIn); + + scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN); + + + if (scsiDev.atnFlag) + { + // If there was a parity error, we go + // back to MESSAGE_OUT first, get out parity error message, then come + // back here. + } + else if (scsiDev.msgIn == MSG_COMMAND_COMPLETE) + { + enter_BusFree(); + } + else + { + // MESSAGE_REJECT. Go back to command phase + scsiDev.phase = COMMAND; + } +} + +static void enter_Status(uint8 status) +{ + scsiDev.status = status; + scsiDev.phase = STATUS; +} + +static void process_Status() +{ + scsiEnterPhase(STATUS); + scsiWrite(scsiDev.status); + + // Command Complete occurs AFTER a valid status has been + // sent. then we go bus-free. + enter_MessageIn(MSG_COMMAND_COMPLETE); +} + +static void enter_DataIn(int len) +{ + scsiDev.dataLen = len; + scsiDev.phase = DATA_IN; +} + +static void process_DataIn() +{ + if (scsiDev.dataLen > sizeof(scsiDev.data)) + { + scsiDev.dataLen = sizeof(scsiDev.data); + } + + scsiEnterPhase(DATA_IN); + while ((scsiDev.dataPtr < scsiDev.dataLen) && + !scsiDev.resetFlag && + !scsiDev.atnFlag) + { + scsiWrite(scsiDev.data[scsiDev.dataPtr]); + ++scsiDev.dataPtr; + + // scsiWrite will update resetFlag. + scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN); + } + + if ((scsiDev.dataPtr >= scsiDev.dataLen) && + (transfer.currentBlock == transfer.blocks)) + { + enter_Status(GOOD); + } +} + +static void process_DataOut() +{ + if (scsiDev.dataLen > sizeof(scsiDev.data)) + { + scsiDev.dataLen = sizeof(scsiDev.data); + } + + scsiEnterPhase(DATA_OUT); + while ((scsiDev.dataPtr < scsiDev.dataLen) && + !scsiDev.resetFlag && + !scsiDev.atnFlag) + { + scsiDev.parityError = 0; + scsiDev.data[scsiDev.dataPtr] = scsiRead(); + + if (scsiDev.parityError) + { + scsiDev.sense.code = ABORTED_COMMAND; + scsiDev.sense.asc = SCSI_PARITY_ERROR; + enter_Status(CHECK_CONDITION); + break; + } + ++scsiDev.dataPtr; + + // scsiRead will update resetFlag. + scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN); + } + + if ((scsiDev.dataPtr >= scsiDev.dataLen) && + (transfer.currentBlock == transfer.blocks)) + { + enter_Status(GOOD); + } +} + +static const uint8 CmdGroupBytes[8] = {6, 10, 10, 6, 6, 12, 6, 6}; +static void process_Command() +{ + scsiEnterPhase(COMMAND); + scsiDev.parityError = 0; + + memset(scsiDev.cdb, 0, sizeof(scsiDev.cdb)); + scsiDev.cdb[0] = scsiRead(); + + int group = scsiDev.cdb[0] >> 5; + int cmdSize = CmdGroupBytes[group]; + int i; + for (i = 1; i < cmdSize; ++i) + { + scsiDev.cdb[i] = scsiRead(); + } + + uint8 command = scsiDev.cdb[0]; + uint8 lun = scsiDev.cdb[1] >> 5; + + if (scsiDev.parityError) + { + scsiDev.sense.code = ABORTED_COMMAND; + scsiDev.sense.asc = SCSI_PARITY_ERROR; + enter_Status(CHECK_CONDITION); + } + else if (command == 0x12) + { + scsiInquiry(); + } + else if (command == 0x03) + { + // REQUEST SENSE + uint32 allocLength = scsiDev.cdb[4]; + if (allocLength == 0) allocLength = 256; + memset(scsiDev.data, 0, 18); + scsiDev.data[0] = 0xF0; + scsiDev.data[2] = scsiDev.sense.code & 0x0F; + + // TODO populate "information" field with requested LBA. + // TODO support more detailed sense data ? + + scsiDev.data[12] = scsiDev.sense.asc >> 8; + scsiDev.data[13] = scsiDev.sense.asc; + + // Silently truncate results. SCSI-2 spec 8.2.14. + enter_DataIn(allocLength < 18 ? allocLength : 18); + + // This is a good time to clear out old sense information. + scsiDev.sense.code = NO_SENSE; + scsiDev.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION; + } + // Some old SCSI drivers do NOT properly support + // unitAttention. OTOH, Linux seems to require it + // TODO MAKE CONFIGURABLE. + /* confirmed LCIII with unknown scsi driver fials here. + else if (scsiDev.unitAttention) + { + scsiDev.sense.code = UNIT_ATTENTION; + scsiDev.sense.asc = scsiDev.unitAttention; + enter_Status(CHECK_CONDITION); + }*/ + else if (lun) + { + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = LOGICAL_UNIT_NOT_SUPPORTED; + enter_Status(CHECK_CONDITION); + } + else if (command == 0x17 || command == 0x16) + { + doReserveRelease(); + } + else if ((scsiDev.reservedId >= 0) && + (scsiDev.reservedId != scsiDev.initiatorId)) + { + enter_Status(CONFLICT); + } + else if (command == 0x1C) + { + scsiReceiveDiagnostic(); + } + else if (command == 0x1D) + { + scsiSendDiagnostic(); + } + else if ( + !scsiModeCommand() && + !scsiDiskCommand()) + { + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = INVALID_COMMAND_OPERATION_CODE; + enter_Status(CHECK_CONDITION); + } + + // Successful + if (scsiDev.phase == COMMAND) // No status set, and not in DATA_IN + { + enter_Status(GOOD); + } + + scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN); +} + +static void doReserveRelease() +{ + int extentReservation = scsiDev.cdb[1] & 1; + int thirdPty = scsiDev.cdb[1] & 0x10; + int thirdPtyId = (scsiDev.cdb[1] >> 1) & 0x7; + uint8 command = scsiDev.cdb[0]; + + int canRelease = + (!thirdPty && (scsiDev.initiatorId == scsiDev.reservedId)) || + (thirdPty && + (scsiDev.reserverId == scsiDev.initiatorId) && + (scsiDev.reservedId == thirdPtyId) + ); + + if (extentReservation) + { + // Not supported. + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = INVALID_FIELD_IN_CDB; + enter_Status(CHECK_CONDITION); + } + else if (command == 0x17) // release + { + if ((scsiDev.reservedId < 0) || canRelease) + { + scsiDev.reservedId = -1; + scsiDev.reserverId = -1; + } + else + { + enter_Status(CONFLICT); + } + } + else // assume reserve. + { + if ((scsiDev.reservedId < 0) || canRelease) + { + scsiDev.reserverId = scsiDev.initiatorId; + if (thirdPty) + { + scsiDev.reservedId = thirdPtyId; + } + else + { + scsiDev.reservedId = scsiDev.initiatorId; + } + } + else + { + // Already reserved by someone else! + enter_Status(CONFLICT); + } + } +} + +static void scsiReset() +{ + ledOff(); + SCSI_Out_DBx_Write(0); + SCSI_ClearPin(SCSI_Out_DBP); + SCSI_ClearPin(SCSI_Out_ATN); + SCSI_ClearPin(SCSI_Out_BSY); + SCSI_ClearPin(SCSI_Out_ACK); + SCSI_ClearPin(SCSI_Out_RST); + SCSI_ClearPin(SCSI_Out_SEL); + SCSI_ClearPin(SCSI_Out_REQ); + SCSI_ClearPin(SCSI_Out_MSG); + SCSI_ClearPin(SCSI_Out_CD); + SCSI_ClearPin(SCSI_Out_IO); + + scsiDev.resetFlag = 0; + scsiDev.atnFlag = 0; + scsiDev.parityError = 0; + scsiDev.phase = BUS_FREE; + + if (scsiDev.unitAttention != POWER_ON_RESET) + { + scsiDev.unitAttention = SCSI_BUS_RESET; + } + scsiDev.reservedId = -1; + scsiDev.reserverId = -1; + scsiDev.sense.code = NO_SENSE; + scsiDev.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION; + scsiDiskReset(); + + // Sleep to allow the bus to settle down a bit. + // We must be ready again within the "Reset to selection time" of + // 250ms. + // There is no guarantee that the RST line will be negated by then. + int reset; + do + { + CyDelay(10); // 10ms. + reset = SCSI_ReadPin(SCSI_In_RST); + } while (reset); +} + +static void enter_SelectionPhase() +{ + + scsiDev.atnFlag = 0; + scsiDev.parityError = 0; + scsiDev.dataPtr = 0; + scsiDev.savedDataPtr = 0; + scsiDev.status = GOOD; + scsiDev.phase = SELECTION; +} + +static void process_SelectionPhase() +{ + uint8 mask = ~SCSI_In_DBx_Read(); + int goodParity = (Lookup_OddParity[mask] == SCSI_ReadPin(SCSI_In_DBP)); + + scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN); + int sel = SCSI_ReadPin(SCSI_In_SEL); + int bsy = SCSI_ReadPin(SCSI_In_BSY); + if (!bsy && sel && + (mask & scsiDev.scsiIdMask) && + goodParity && (countBits(mask) == 2)) + { + // We've been selected! + // Assert BSY - Selection success! + // must happen within 200us (Selection abort time) of seeing our + // ID + SEL. + // (Note: the initiator will be waiting the "Selection time-out delay" + // for our BSY response, which is actually a very generous 250ms) + SCSI_SetPin(SCSI_Out_BSY); + ledOn(); + + // Wait until the end of the selection phase. + // Keep checking the ATN flag, as the initiator may assert it at any + // time before releasing SEL. + while (!scsiDev.resetFlag) + { + scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN); + if (!SCSI_ReadPin(SCSI_In_SEL)) + { + break; + } + scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST); + } + + // Save our initiator now that we're no longer in a time-critical + // section. + uint8 initiatorMask = mask ^ scsiDev.scsiIdMask; + scsiDev.initiatorId = 0; + int i; + for (i = 0; i < 8; ++i) + { + if (initiatorMask & (1 << i)) + { + scsiDev.initiatorId = i; + break; + } + } + + scsiDev.phase = COMMAND; + } + else if (!sel) + { + scsiDev.phase = BUS_BUSY; + } + + scsiDev.resetFlag = scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST); +} + +static void process_MessageOut() +{ + scsiDev.atnFlag = 0; + scsiEnterPhase(MESSAGE_OUT); + + scsiDev.parityError = 0; + scsiDev.msgOut = scsiRead(); + + if (scsiDev.parityError) + { + // Skip the remaining message bytes, and then start the MESSAGE_OUT + // phase again from the start. The initiator will re-send the + // same set of messages. + while (SCSI_ReadPin(SCSI_In_ATN) && !scsiDev.resetFlag) + { + scsiRead(); + scsiDev.resetFlag = scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST); + } + + // Go-back and try the message again. + scsiDev.atnFlag = 1; + scsiDev.parityError = 0; + } + else if (scsiDev.msgOut == 0x00) + { + // COMMAND COMPLETE. but why would the target be receiving this ? nfi. + enter_BusFree(); + } + else if (scsiDev.msgOut == 0x06) + { + // ABORT + scsiDiskReset(); + enter_BusFree(); + } + else if (scsiDev.msgOut == 0x0C) + { + // BUS DEVICE RESET + + scsiDiskReset(); + + scsiDev.unitAttention = SCSI_BUS_RESET; + + // ANY initiator can reset the reservation state via this message. + scsiDev.reservedId = -1; + scsiDev.reserverId = -1; + enter_BusFree(); + } + else if (scsiDev.msgOut == 0x05) + { + // Initiate Detected Error + // Ignore for now + } + else if (scsiDev.msgOut == 0x0F) + { + // INITIATE RECOVERY + // Ignore for now + } + else if (scsiDev.msgOut == 0x10) + { + // RELEASE RECOVERY + // Ignore for now + enter_BusFree(); + } + else if (scsiDev.msgOut == MSG_REJECT) + { + // Message Reject + // Oh well. + scsiDev.resetFlag = 1; + } + else if (scsiDev.msgOut == 0x08) + { + // NOP + } + else if (scsiDev.msgOut == 0x09) + { + // Message Parity Error + // Go back and re-send the last message. + scsiDev.phase = MESSAGE_IN; + } + else if (scsiDev.msgOut & 0x80) // 0x80 -> 0xFF + { + // IDENTIFY + // We don't disconnect, so ignore disconnect privilege. + if ((scsiDev.msgOut & 0x18) || // Reserved bits set. + (scsiDev.msgOut & 0x20) || // We don't have any target routines! + (scsiDev.msgOut & 0x7) // We only support LUN 0! + ) + { + enter_MessageIn(MSG_REJECT); + } + } + else if (scsiDev.msgOut >= 0x20 && scsiDev.msgOut <= 0x2F) + { + // Two byte message. We don't support these. read and discard. + scsiRead(); + } + else if (scsiDev.msgOut == 0x01) + { + // Extended message. + int msgLen = scsiRead(); + if (msgLen == 0) msgLen = 256; + int i; + for (i = 0; i < msgLen && !scsiDev.resetFlag; ++i) + { + // Discard bytes. + scsiRead(); + } + + // We don't support ANY extended messages. + // Modify Data Pointer: We don't support reselection. + // Wide Data Transfer Request: No. 8bit only. + // Synchronous data transfer request. No, we can't do that. + // We don't support any 2-byte messages either. + // And we don't support any optional 1-byte messages. + // In each case, the correct response is MESSAGE REJECT. + enter_MessageIn(MSG_REJECT); + } + else + { + enter_MessageIn(MSG_REJECT); + } + + // atnFlag will be forced to 1 if there was a parity error. + scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN); +} + + +void scsiPoll(void) +{ + if (scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST)) + { + scsiReset(); + } + + switch (scsiDev.phase) + { + case BUS_FREE: + if (SCSI_ReadPin(SCSI_In_BSY)) + { + scsiDev.phase = BUS_BUSY; + } + break; + + case BUS_BUSY: + // Someone is using the bus. Perhaps they are trying to + // select us. + if (SCSI_ReadPin(SCSI_In_SEL)) + { + enter_SelectionPhase(); + } + else if (!SCSI_ReadPin(SCSI_In_BSY)) + { + scsiDev.phase = BUS_FREE; + } + break; + + case ARBITRATION: + // TODO Support reselection. + break; + + case SELECTION: + process_SelectionPhase(); + break; + + case RESELECTION: + // Not currently supported! + break; + + case COMMAND: + if (scsiDev.atnFlag) + { + process_MessageOut(); + } + else + { + process_Command(); + } + break; + + case DATA_IN: + if (scsiDev.atnFlag) + { + process_MessageOut(); + } + else + { + process_DataIn(); + } + break; + + case DATA_OUT: + if (scsiDev.atnFlag) + { + process_MessageOut(); + } + else + { + process_DataOut(); + } + break; + + case STATUS: + if (scsiDev.atnFlag) + { + process_MessageOut(); + } + else + { + process_Status(); + } + break; + + case MESSAGE_IN: + if (scsiDev.atnFlag) + { + process_MessageOut(); + } + else + { + process_MessageIn(); + } + + break; + + case MESSAGE_OUT: + process_MessageOut(); + break; + } +} + +void scsiInit(int scsiId, int enableParity) +{ + scsiDev.scsiIdMask = 1 << scsiId; + scsiDev.enableParity = enableParity; + + scsiDev.atnFlag = 0; + scsiDev.resetFlag = 1; + scsiDev.phase = BUS_FREE; + scsiDev.reservedId = -1; + scsiDev.reserverId = -1; + scsiDev.unitAttention = POWER_ON_RESET; +} + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsi.h b/software/SCSI2SD/SCSI2SD.cydsn/scsi.h new file mode 100755 index 0000000..86e8445 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsi.h @@ -0,0 +1,114 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#ifndef SCSI_H +#define SCSI_H + +// SCSI documentation goes here +// SCSI-2. +// Single LUN +// No tagged-queuing support - single command at a time. +// All read/write commands disconnect. State SD card latency. +// Fixed 512 byte sector size. +// 2TB limit, based on 32bit LBA (read16/write16 not supported) + +#include "geometry.h" +#include "sense.h" + +typedef enum +{ + // internal bits + __scsiphase_msg = 1, + __scsiphase_cd = 2, + __scsiphase_io = 4, + + BUS_FREE = -1, + BUS_BUSY = -2, + ARBITRATION = -3, + SELECTION = -4, + RESELECTION = -5, + STATUS = __scsiphase_cd | __scsiphase_io, + COMMAND = __scsiphase_cd, + DATA_IN = __scsiphase_io, + DATA_OUT = 0, + MESSAGE_IN = __scsiphase_msg | __scsiphase_cd | __scsiphase_io, + MESSAGE_OUT = __scsiphase_msg | __scsiphase_cd +} SCSI_PHASE; + +typedef enum +{ + GOOD = 0, + CHECK_CONDITION = 2, + BUSY = 0x8, + CONFLICT = 0x18 +} SCSI_STATUS; + +typedef enum +{ + MSG_COMMAND_COMPLETE = 0, + MSG_REJECT = 0x7 + +} SCSI_MESSAGE; + +typedef struct +{ + uint8_t scsiIdMask; + int enableParity; + + // Set to true (1) if the ATN flag was set, and we need to + // enter the MESSAGE_OUT phase. + int atnFlag; + + // Set to true (1) if the RST flag was set. + int resetFlag; + + // Set to true (1) if a parity error was observed. + int parityError; + + int phase; + + uint8 data[SCSI_BLOCK_SIZE]; + int dataPtr; // Index into data, reset on [re]selection to savedDataPtr + int savedDataPtr; // Index into data, initially 0. + int dataLen; + + uint8 cdb[12]; // command descriptor block + + // Only let the reserved initiator talk to us. + // A 3rd party may be sending the RESERVE/RELEASE commands + int initiatorId; // 0 -> 7. Set during the selection phase. + int reservedId;; // 0 -> 7 if reserved. -1 if not reserved. + int reserverId;; // 0 -> 7 if reserved. -1 if not reserved. + + // SCSI_STATUS value. + // Change to SCSI_STATUS_CHECK_CONDITION when setting a SENSE value + uint8 status; + + ScsiSense sense; + + uint16 unitAttention; // Set to the sense qualifier key to be returned. + + uint8 msgIn; + uint8 msgOut; +} ScsiDevice; + +extern ScsiDevice scsiDev; + +void scsiInit(int scsiId, int enableParity); +void scsiPoll(void); + + +#endif diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c b/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c new file mode 100755 index 0000000..5a0985f --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c @@ -0,0 +1,150 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#include "device.h" +#include "scsi.h" +#include "scsiPhy.h" +#include "bits.h" + +// Spins until the SCSI pin is true, or the reset flag is set. +static void waitForPinTrue(int pin) +{ + while (!scsiDev.resetFlag) + { + // TODO put some hardware gates in front of the RST pin, and store + // the state in a register. The minimum "Reset hold time" is 25us, which + // we can easily satisfy within this loop, but perhaps hard to satisfy + // if we don't call this function often. + scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST); + + if (SCSI_ReadPin(pin)) + { + break; + } + } +} + +// Spins until the SCSI pin is true, or the reset flag is set. +static void waitForPinFalse(int pin) +{ + while (!scsiDev.resetFlag) + { + // TODO put some hardware gates in front of the RST pin, and store + // the state in a register. The minimum "Reset hold time" is 25us, which + // we can easily satisfy within this loop, but perhaps hard to satisfy + // if we don't call this function often. + scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST); + + if (!SCSI_ReadPin(pin)) + { + break; + } + } +} + +static void deskewDelay(void) +{ + // Delay for deskew + cable skew. total 55 nanoseconds. + // Assumes 66MHz. + CyDelayCycles(4); +} + +uint8 scsiRead(void) +{ + SCSI_SetPin(SCSI_Out_REQ); + waitForPinTrue(SCSI_In_ACK); + deskewDelay(); + + uint8 value = ~SCSI_In_DBx_Read(); + scsiDev.parityError = scsiDev.parityError || + (Lookup_OddParity[value] != SCSI_ReadPin(SCSI_In_DBP)); + + SCSI_ClearPin(SCSI_Out_REQ); + waitForPinFalse(SCSI_In_ACK); + return value; +} + +void scsiWrite(uint8 value) +{ + SCSI_Out_DBx_Write(value); + if (Lookup_OddParity[value]) + { + SCSI_SetPin(SCSI_Out_DBP); + } + deskewDelay(); + + SCSI_SetPin(SCSI_Out_REQ); + + // Initiator reads data here. + + waitForPinTrue(SCSI_In_ACK); + + SCSI_ClearPin(SCSI_Out_DBP); + SCSI_Out_DBx_Write(0); + SCSI_ClearPin(SCSI_Out_REQ); + + // Wait for ACK to clear. + waitForPinFalse(SCSI_In_ACK); +} + +static void busSettleDelay(void) +{ + // Data Release time (switching IO) = 400ns + // + Bus Settle time (switching phase) = 400ns. + CyDelayUs(1); // Close enough. +} + +void scsiEnterPhase(int phase) +{ + if (phase > 0) + { + if (phase & __scsiphase_msg) + { + SCSI_SetPin(SCSI_Out_MSG); + } + else + { + SCSI_ClearPin(SCSI_Out_MSG); + } + + if (phase & __scsiphase_cd) + { + SCSI_SetPin(SCSI_Out_CD); + } + else + { + SCSI_ClearPin(SCSI_Out_CD); + } + + if (phase & __scsiphase_io) + { + SCSI_SetPin(SCSI_Out_IO); + } + else + { + SCSI_ClearPin(SCSI_Out_IO); + } + } + else + { + SCSI_ClearPin(SCSI_Out_MSG); + SCSI_ClearPin(SCSI_Out_CD); + SCSI_ClearPin(SCSI_Out_IO); + } + busSettleDelay(); +} + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h b/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h new file mode 100755 index 0000000..334d5cf --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h @@ -0,0 +1,41 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#ifndef SCSIPHY_H +#define SCSIPHY_H + +#define SCSI_SetPin(pin) \ + CyPins_SetPin((pin)); + +#define SCSI_ClearPin(pin) \ + CyPins_ClearPin((pin)); + +// Active low: we interpret a 0 as "true", and non-zero as "false" +#define SCSI_ReadPin(pin) \ + (CyPins_ReadPin((pin)) == 0) + +// Contains the odd-parity flag for a given 8-bit value. +extern const uint8 Lookup_OddParity[256]; + +uint8 scsiRead(void); +void scsiWrite(uint8 value); + +// Returns true if the ATN flag becomes set, indicating a parity error. +int scsiWriteMsg(uint8 msg); + +void scsiEnterPhase(int phase); + +#endif diff --git a/software/SCSI2SD/SCSI2SD.cydsn/sense.h b/software/SCSI2SD/SCSI2SD.cydsn/sense.h new file mode 100755 index 0000000..7852868 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/sense.h @@ -0,0 +1,176 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#ifndef SENSE_H +#define SENSE_H + +typedef enum +{ + NO_SENSE = 0, + RECOVERED_ERROR = 1, + NOT_READY = 2, + MEDIUM_ERROR = 3, + HARDWARE_ERROR = 4, + ILLEGAL_REQUEST = 5, + UNIT_ATTENTION = 6, + DATA_PROTECT = 7, + BLANK_CHECK = 8, + VENDOR_SPECIFIC = 9, + COPY_ABORTED = 0xA, + ABORTED_COMMAND = 0xB, + EQUAL = 0xC, + VOLUME_OVERFLOW = 0xD, + MISCOMPARE = 0xE, + RESERVED = 0xF +} SCSI_SENSE; + +// Top 8 bits = ASC. Lower 8 bits = ASCQ. +// Enum only contains definitions for direct-access related codes. +typedef enum +{ + ADDRESS_MARK_NOT_FOUND_FOR_DATA_FIELD = 0x1300, + ADDRESS_MARK_NOT_FOUND_FOR_ID_FIELD = 0x1200, + CANNOT_READ_MEDIUM_INCOMPATIBLE_FORMAT = 0x3002, + CANNOT_READ_MEDIUM_UNKNOWN_FORMAT = 0x3001, + CHANGED_OPERATING_DEFINITION = 0x3F02, + COMMAND_PHASE_ERROR = 0x4A00, + COMMAND_SEQUENCE_ERROR = 0x2C00, + COMMANDS_CLEARED_BY_ANOTHER_INITIATOR = 0x2F00, + COPY_CANNOT_EXECUTE_SINCE_HOST_CANNOT_DISCONNECT = 0x2B00, + DATA_PATH_FAILURE = 0x4100, + DATA_PHASE_ERROR = 0x4B00, + DATA_SYNCHRONIZATION_MARK_ERROR = 0x1600, + DEFECT_LIST_ERROR = 0x1900, + DEFECT_LIST_ERROR_IN_GROWN_LIST = 0x1903, + DEFECT_LIST_ERROR_IN_PRIMARY_LIST = 0x1902, + DEFECT_LIST_NOT_AVAILABLE = 0x1901, + DEFECT_LIST_NOT_FOUND = 0x1C00, + DEFECT_LIST_UPDATE_FAILURE = 0x3201, + ERROR_LOG_OVERFLOW = 0x0A00, + ERROR_TOO_LONG_TO_CORRECT = 0x1102, + FORMAT_COMMAND_FAILED = 0x3101, + GROWN_DEFECT_LIST_NOT_FOUND = 0x1C02, + IO_PROCESS_TERMINATED = 0x0006, + ID_CRC_OR_ECC_ERROR = 0x1000, + ILLEGAL_FUNCTION = 0x2200, + INCOMPATIBLE_MEDIUM_INSTALLED = 0x3000, + INITIATOR_DETECTED_ERROR_MESSAGE_RECEIVED = 0x4800, + INQUIRY_DATA_HAS_CHANGED = 0x3F03, + INTERNAL_TARGET_FAILURE = 0x4400, + INVALID_BITS_IN_IDENTIFY_MESSAGE = 0x3D00, + INVALID_COMMAND_OPERATION_CODE = 0x2000, + INVALID_FIELD_IN_CDB = 0x2400, + INVALID_FIELD_IN_PARAMETER_LIST = 0x2600, + INVALID_MESSAGE_ERROR = 0x4900, + LOG_COUNTER_AT_MAXIMUM = 0x5B02, + LOG_EXCEPTION = 0x5B00, + LOG_LIST_CODES_EXHAUSTED = 0x5B03, + LOG_PARAMETERS_CHANGED = 0x2A02, + LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE = 0x2100, + LOGICAL_UNIT_COMMUNICATION_FAILURE = 0x0800, + LOGICAL_UNIT_COMMUNICATION_PARITY_ERROR = 0x0802, + LOGICAL_UNIT_COMMUNICATION_TIMEOUT = 0x0801, + LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION = 0x0500, + LOGICAL_UNIT_FAILED_SELF_CONFIGURATION = 0x4C00, + LOGICAL_UNIT_HAS_NOT_SELF_CONFIGURED_YET = 0x3E00, + LOGICAL_UNIT_IS_IN_PROCESS_OF_BECOMING_READY = 0x0401, + LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE = 0x0400, + LOGICAL_UNIT_NOT_READY_FORMAT_IN_PROGRESS = 0x0404, + LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED = 0x0402, + LOGICAL_UNIT_NOT_READY_MANUAL_INTERVENTION_REQUIRED = 0x0403, + LOGICAL_UNIT_NOT_SUPPORTED = 0x2500, + MECHANICAL_POSITIONING_ERROR = 0x1501, + MEDIA_LOAD_OR_EJECT_FAILED = 0x5300, + MEDIUM_FORMAT_CORRUPTED = 0x3100, + MEDIUM_NOT_PRESENT = 0x3A00, + MEDIUM_REMOVAL_PREVENTED = 0x5302, + MESSAGE_ERROR = 0x4300, + MICROCODE_HAS_BEEN_CHANGED = 0x3F01, + MISCOMPARE_DURING_VERIFY_OPERATION = 0x1D00, + MISCORRECTED_ERROR = 0x110A, + MODE_PARAMETERS_CHANGED = 0x2A01, + MULTIPLE_PERIPHERAL_DEVICES_SELECTED = 0x0700, + MULTIPLE_READ_ERRORS = 0x1103, + NO_ADDITIONAL_SENSE_INFORMATION = 0x0000, + NO_DEFECT_SPARE_LOCATION_AVAILABLE = 0x3200, + NO_INDEX_SECTOR_SIGNAL = 0x0100, + NO_REFERENCE_POSITION_FOUND = 0x0600, + NO_SEEK_COMPLETE = 0x0200, + NOT_READY_TO_READY_TRANSITION_MEDIUM_MAY_HAVE_CHANGED = 0x2800, + OPERATOR_MEDIUM_REMOVAL_REQUEST = 0x5A01, + OPERATOR_REQUEST_OR_STATE_CHANGE_INPUT = 0x5A00, + OPERATOR_SELECTED_WRITE_PERMIT = 0x5A03, + OPERATOR_SELECTED_WRITE_PROTECT = 0x5A02, + OVERLAPPED_COMMANDS_ATTEMPTED = 0x4E00, + PARAMETER_LIST_LENGTH_ERROR = 0x1A00, + PARAMETER_NOT_SUPPORTED = 0x2601, + PARAMETER_VALUE_INVALID = 0x2602, + PARAMETERS_CHANGED = 0x2A00, + PERIPHERAL_DEVICE_WRITE_FAULT = 0x0300, + POSITIONING_ERROR_DETECTED_BY_READ_OF_MEDIUM = 0x1502, + POWER_ON_RESET_OR_BUS_DEVICE_RESET_OCCURRED = 0x2900, + POWER_ON_RESET = 0x2901, + POWER_ON_OR_SELF_TEST_FAILURE = 0x4200, + PRIMARY_DEFECT_LIST_NOT_FOUND = 0x1C01, + RAM_FAILURE = 0x4000, + RANDOM_POSITIONING_ERROR = 0x1500, + READ_RETRIES_EXHAUSTED = 0x1101, + RECORD_NOT_FOUND = 0x1401, + RECORDED_ENTITY_NOT_FOUND = 0x1400, + RECOVERED_DATA_DATA_AUTO_REALLOCATED = 0x1802, + RECOVERED_DATA_RECOMMEND_REASSIGNMENT = 0x1805, + RECOVERED_DATA_RECOMMEND_REWRITE = 0x1806, + RECOVERED_DATA_USING_PREVIOUS_SECTOR_ID = 0x1705, + RECOVERED_DATA_WITH_ERROR_CORRECTION_RETRIES_APPLIED = 0x1801, + RECOVERED_DATA_WITH_ERROR_CORRECTION_APPLIED = 0x1800, + RECOVERED_DATA_WITH_NEGATIVE_HEAD_OFFSET = 0x1703, + RECOVERED_DATA_WITH_NO_ERROR_CORRECTION_APPLIED = 0x1700, + RECOVERED_DATA_WITH_POSITIVE_HEAD_OFFSET = 0x1702, + RECOVERED_DATA_WITH_RETRIES = 0x1701, + RECOVERED_DATA_WITHOUT_ECC_DATA_AUTO_REALLOCATED = 0x1706, + RECOVERED_DATA_WITHOUT_ECC_RECOMMEND_REASSIGNMENT = 0x1707, + RECOVERED_DATA_WITHOUT_ECC_RECOMMEND_REWRITE = 0x1708, + RECOVERED_ID_WITH_ECC_CORRECTION = 0x1E00, + ROUNDED_PARAMETER = 0x3700, + RPL_STATUS_CHANGE = 0x5C00, + SAVING_PARAMETERS_NOT_SUPPORTED = 0x3900, + SCSI_BUS_RESET = 0x2902, + SCSI_PARITY_ERROR = 0x4700, + SELECT_OR_RESELECT_FAILURE = 0x4500, + SPINDLES_NOT_SYNCHRONIZED = 0x5C02, + SPINDLES_SYNCHRONIZED = 0x5C01, + SYNCHRONOUS_DATA_TRANSFER_ERROR = 0x1B00, + TARGET_OPERATING_CONDITIONS_HAVE_CHANGED = 0x3F00, + THRESHOLD_CONDITION_MET = 0x5B01, + THRESHOLD_PARAMETERS_NOT_SUPPORTED = 0x2603, + TRACK_FOLLOWING_ERROR = 0x0900, + UNRECOVERED_READ_ERROR = 0x1100, + UNRECOVERED_READ_ERROR_AUTO_REALLOCATE_FAILED = 0x1104, + UNRECOVERED_READ_ERROR_RECOMMEND_REASSIGNMENT = 0x110B, + UNRECOVERED_READ_ERROR_RECOMMEND_REWRITE_THE_DATA = 0x110C, + UNSUCCESSFUL_SOFT_RESET = 0x4600, + WRITE_ERROR_AUTO_REALLOCATION_FAILED = 0x0C02, + WRITE_ERROR_RECOVERED_WITH_AUTO_REALLOCATION = 0x0C01, + WRITE_PROTECTED = 0x2700 +} SCSI_ASC_ASCQ; + +typedef struct +{ + uint8 code; + uint16 asc; +} ScsiSense; + +#endif