diff --git a/CHANGELOG b/CHANGELOG index 5e6bc72..656e944 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,5 +1,9 @@ -201407XX 3.6 +201408XX 3.6 - Fix handling requests for LUNs other than 0 from SCSI-2 hosts. + - Handle glitches of the ACK line to improve stability and operate with + multiple devices on the SCSI bus. + - Re-add parity checking. This can be disabled using scsi2sd-config if + required. 20140718 3.5.2 - Fix blank SCSI ID in scsi2sd-config output. diff --git a/STATUS b/STATUS index 7074591..e1ad87f 100644 --- a/STATUS +++ b/STATUS @@ -1,2 +1,2 @@ -- Parity checking not implemented for the PSoC Datapath implementation +- Everything works. If it doesn't, please report the bug to michael@codesrc.com diff --git a/readme.txt b/readme.txt index 1e998a1..0188152 100644 --- a/readme.txt +++ b/readme.txt @@ -70,6 +70,7 @@ Compatibility Apple IIgs using Apple II High Speed SCSI controller card (from v3.3) Symbolics Lisp Machine XL1200, using 1280 byte sectors (from v3.4) PDP-11/73 running RSX11M+ V4.6 + Microvax 3100 Model 80 running VMS 7.3 (needs patch against v3.5.2 firmware) Amiga 500+ with GVP A530 Atari TT030 System V @@ -88,6 +89,7 @@ Samplers Casio FZ-20M Requires TERMPWR jumper. The manual shows the pin25 of the DB25 connector is "not connected". May require scsi2sd-config --apple flag + Yamaha EX5R Other diff --git a/software/SCSI2SD/src/disk.c b/software/SCSI2SD/src/disk.c index 1e656cd..d0f93ba 100755 --- a/software/SCSI2SD/src/disk.c +++ b/software/SCSI2SD/src/disk.c @@ -563,6 +563,12 @@ void scsiDiskPoll() if (scsiDev.phase == DATA_OUT) { + if (scsiDev.parityError) + { + scsiDev.sense.code = ABORTED_COMMAND; + scsiDev.sense.asc = SCSI_PARITY_ERROR; + scsiDev.status = CHECK_CONDITION;; + } scsiDev.phase = STATUS; } scsiDiskReset(); diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c index 5be5a84..74fe177 100755 --- a/software/SCSI2SD/src/scsi.c +++ b/software/SCSI2SD/src/scsi.c @@ -197,8 +197,7 @@ static void process_DataOut() scsiRead(scsiDev.data + scsiDev.dataPtr, len); scsiDev.dataPtr += len; - // TODO re-implement parity checking - if (0 && scsiDev.parityError && config->enableParity) + if (scsiDev.parityError && config->enableParity) { scsiDev.sense.code = ABORTED_COMMAND; scsiDev.sense.asc = SCSI_PARITY_ERROR; diff --git a/software/SCSI2SD/src/scsiPhy.c b/software/SCSI2SD/src/scsiPhy.c index 45362a7..46852fb 100755 --- a/software/SCSI2SD/src/scsiPhy.c +++ b/software/SCSI2SD/src/scsiPhy.c @@ -86,8 +86,9 @@ scsiReadByte(void) while (scsiPhyRxFifoEmpty() && !scsiDev.resetFlag) {} uint8_t val = scsiPhyRx(); + scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read(); - while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} + while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {} return val; } @@ -113,7 +114,8 @@ scsiReadPIO(uint8* data, uint32 count) ++i; } } - while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} + scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read(); + while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {} } static void @@ -182,7 +184,7 @@ scsiReadDMAPoll() if (dmaSentCount == dmaTotalCount) { dmaInProgress = 0; - while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} + scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read(); return 1; } else @@ -224,8 +226,6 @@ scsiWriteByte(uint8 value) while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {} scsiPhyRxFifoClear(); - - while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} } static void @@ -271,6 +271,7 @@ doTxSingleDMA(uint8* data, uint32 count) CyDmaClearPendingDrq(scsiDmaTxChan); txDMAComplete = 0; + rxDMAComplete = 1; CyDmaChEnable(scsiDmaTxChan, 1); } @@ -296,7 +297,6 @@ scsiWriteDMAPoll() { scsiPhyRxFifoClear(); dmaInProgress = 0; - while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} return 1; } else @@ -383,6 +383,8 @@ void scsiPhyReset() // Allow the FIFOs to fill up again. SCSI_ClearPin(SCSI_Out_RST); scsiTarget_AUX_CTL = scsiTarget_AUX_CTL & ~(0x03); + + SCSI_Parity_Error_Read(); // clear sticky bits } static void scsiPhyInitDMA() @@ -397,7 +399,7 @@ static void scsiPhyInitDMA() HI16(CYDEV_PERIPH_BASE), HI16(CYDEV_SRAM_BASE) ); - + scsiDmaTxChan = SCSI_TX_DMA_DmaInitialize( 1, // Bytes per burst @@ -411,7 +413,7 @@ static void scsiPhyInitDMA() scsiDmaRxTd[0] = CyDmaTdAllocate(); scsiDmaTxTd[0] = CyDmaTdAllocate(); - + SCSI_RX_DMA_COMPLETE_StartEx(scsiRxCompleteISR); SCSI_TX_DMA_COMPLETE_StartEx(scsiTxCompleteISR); } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c new file mode 100644 index 0000000..8d35a48 --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c @@ -0,0 +1,134 @@ +/******************************************************************************* +* File Name: SCSI_Parity_Error.c +* Version 1.80 +* +* Description: +* This file contains API to enable firmware to read the value of a Status +* Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Parity_Error.h" + +#if !defined(SCSI_Parity_Error_sts_sts_reg__REMOVED) /* Check for removal by optimization */ + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Status Register. +* +* Parameters: +* None. +* +* Return: +* The current value in the Status Register. +* +*******************************************************************************/ +uint8 SCSI_Parity_Error_Read(void) +{ + return SCSI_Parity_Error_Status; +} + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_InterruptEnable +******************************************************************************** +* +* Summary: +* Enables the Status Register interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Parity_Error_InterruptEnable(void) +{ + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + SCSI_Parity_Error_Status_Aux_Ctrl |= SCSI_Parity_Error_STATUS_INTR_ENBL; + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_InterruptDisable +******************************************************************************** +* +* Summary: +* Disables the Status Register interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Parity_Error_InterruptDisable(void) +{ + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + SCSI_Parity_Error_Status_Aux_Ctrl &= (uint8)(~SCSI_Parity_Error_STATUS_INTR_ENBL); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_WriteMask +******************************************************************************** +* +* Summary: +* Writes the current mask value assigned to the Status Register. +* +* Parameters: +* mask: Value to write into the mask register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Parity_Error_WriteMask(uint8 mask) +{ + #if(SCSI_Parity_Error_INPUTS < 8u) + mask &= (uint8)((((uint8)1u) << SCSI_Parity_Error_INPUTS) - 1u); + #endif /* End SCSI_Parity_Error_INPUTS < 8u */ + SCSI_Parity_Error_Status_Mask = mask; +} + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_ReadMask +******************************************************************************** +* +* Summary: +* Reads the current interrupt mask assigned to the Status Register. +* +* Parameters: +* None. +* +* Return: +* The value of the interrupt mask of the Status Register. +* +*******************************************************************************/ +uint8 SCSI_Parity_Error_ReadMask(void) +{ + return SCSI_Parity_Error_Status_Mask; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h new file mode 100644 index 0000000..d03aed7 --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h @@ -0,0 +1,63 @@ +/******************************************************************************* +* File Name: SCSI_Parity_Error.h +* Version 1.80 +* +* Description: +* This file containts Status Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */ +#define CY_STATUS_REG_SCSI_Parity_Error_H + +#include "cytypes.h" +#include "CyLib.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +uint8 SCSI_Parity_Error_Read(void) ; +void SCSI_Parity_Error_InterruptEnable(void) ; +void SCSI_Parity_Error_InterruptDisable(void) ; +void SCSI_Parity_Error_WriteMask(uint8 mask) ; +uint8 SCSI_Parity_Error_ReadMask(void) ; + + +/*************************************** +* API Constants +***************************************/ + +#define SCSI_Parity_Error_STATUS_INTR_ENBL 0x10u + + +/*************************************** +* Parameter Constants +***************************************/ + +/* Status Register Inputs */ +#define SCSI_Parity_Error_INPUTS 1 + + +/*************************************** +* Registers +***************************************/ + +/* Status Register */ +#define SCSI_Parity_Error_Status (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG ) +#define SCSI_Parity_Error_Status_PTR ( (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG ) +#define SCSI_Parity_Error_Status_Mask (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__MASK_REG ) +#define SCSI_Parity_Error_Status_Aux_Ctrl (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG ) + +#endif /* End CY_STATUS_REG_SCSI_Parity_Error_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 2ce57f8..1335c5f 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -71,6 +71,16 @@ #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* SCSI_Parity_Error */ +#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__0__POS 0 +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST + /* USBFS_bus_reset */ #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 @@ -84,41 +94,41 @@ /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL /* SCSI_Out_Bits */ #define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u @@ -133,15 +143,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL /* USBFS_arb_int */ #define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -166,24 +176,24 @@ /* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL /* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG @@ -656,8 +666,8 @@ #define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL #define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK #define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -665,17 +675,13 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK -#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB05_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB05_ST #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u @@ -685,28 +691,26 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB05_06_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB05_06_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB05_06_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB05_06_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB05_06_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB05_06_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB05_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB05_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB05_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB05_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB05_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB05_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB05_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB05_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB05_F1 -#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB06_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB06_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB06_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB06_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB06_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB06_F1 /* USBFS_dp_int */ #define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -1199,8 +1203,8 @@ /* scsiTarget */ #define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__POS 0 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 #define scsiTarget_StatusReg__2__MASK 0x04u @@ -1210,54 +1214,58 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB00_MSK -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB00_ST -#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST -#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK -#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST -#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL -#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK -#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL -#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL -#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK -#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0 -#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1 -#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0 -#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1 -#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0 -#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1 -#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1 -#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0 -#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1 -#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1 -#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0 -#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1 -#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1 -#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0 -#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1 -#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK +#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL +#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST +#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST +#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB04_MSK +#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL +#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL +#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB04_ST +#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL +#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK +#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB04_CTL +#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL +#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB04_CTL +#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL +#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB04_MSK +#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB04_05_A0 +#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB04_05_A1 +#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB04_05_D0 +#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB04_05_D1 +#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB04_05_F0 +#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB04_05_F1 +#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB04_A0_A1 +#define scsiTarget_datapath__A0_REG CYREG_B0_UDB04_A0 +#define scsiTarget_datapath__A1_REG CYREG_B0_UDB04_A1 +#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB04_D0_D1 +#define scsiTarget_datapath__D0_REG CYREG_B0_UDB04_D0 +#define scsiTarget_datapath__D1_REG CYREG_B0_UDB04_D1 +#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB04_F0_F1 +#define scsiTarget_datapath__F0_REG CYREG_B0_UDB04_F0 +#define scsiTarget_datapath__F1_REG CYREG_B0_UDB04_F1 +#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL /* USBFS_ep_0 */ #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 081c1e2..365ce1d 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 36u +#define CY_CFG_BASE_ADDR_COUNT 37u CYPACKED typedef struct { uint8 offset; @@ -380,39 +380,40 @@ void cyfitter_cfg(void) static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004502u, /* Base address: 0x40004500 Count: 2 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x4000520Au, /* Base address: 0x40005200 Count: 10 */ + 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */ 0x40006402u, /* Base address: 0x40006400 Count: 2 */ - 0x4001004Bu, /* Base address: 0x40010000 Count: 75 */ - 0x40010138u, /* Base address: 0x40010100 Count: 56 */ - 0x40010248u, /* Base address: 0x40010200 Count: 72 */ - 0x4001035Au, /* Base address: 0x40010300 Count: 90 */ - 0x40010462u, /* Base address: 0x40010400 Count: 98 */ - 0x40010551u, /* Base address: 0x40010500 Count: 81 */ - 0x40010657u, /* Base address: 0x40010600 Count: 87 */ - 0x40010752u, /* Base address: 0x40010700 Count: 82 */ - 0x4001090Au, /* Base address: 0x40010900 Count: 10 */ - 0x40010A04u, /* Base address: 0x40010A00 Count: 4 */ - 0x40010B1Au, /* Base address: 0x40010B00 Count: 26 */ - 0x40010C3Eu, /* Base address: 0x40010C00 Count: 62 */ - 0x40010D42u, /* Base address: 0x40010D00 Count: 66 */ - 0x40010F06u, /* Base address: 0x40010F00 Count: 6 */ - 0x40011506u, /* Base address: 0x40011500 Count: 6 */ - 0x40011652u, /* Base address: 0x40011600 Count: 82 */ - 0x4001174Eu, /* Base address: 0x40011700 Count: 78 */ - 0x40011907u, /* Base address: 0x40011900 Count: 7 */ - 0x40011B05u, /* Base address: 0x40011B00 Count: 5 */ - 0x40014017u, /* Base address: 0x40014000 Count: 23 */ - 0x40014116u, /* Base address: 0x40014100 Count: 22 */ - 0x40014210u, /* Base address: 0x40014200 Count: 16 */ - 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */ - 0x4001440Cu, /* Base address: 0x40014400 Count: 12 */ - 0x40014518u, /* Base address: 0x40014500 Count: 24 */ - 0x40014607u, /* Base address: 0x40014600 Count: 7 */ - 0x4001470Au, /* Base address: 0x40014700 Count: 10 */ - 0x40014807u, /* Base address: 0x40014800 Count: 7 */ - 0x40014909u, /* Base address: 0x40014900 Count: 9 */ - 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */ - 0x40015006u, /* Base address: 0x40015000 Count: 6 */ + 0x4001004Au, /* Base address: 0x40010000 Count: 74 */ + 0x40010137u, /* Base address: 0x40010100 Count: 55 */ + 0x4001024Au, /* Base address: 0x40010200 Count: 74 */ + 0x4001035Cu, /* Base address: 0x40010300 Count: 92 */ + 0x4001043Au, /* Base address: 0x40010400 Count: 58 */ + 0x4001055Cu, /* Base address: 0x40010500 Count: 92 */ + 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */ + 0x40010757u, /* Base address: 0x40010700 Count: 87 */ + 0x4001091Au, /* Base address: 0x40010900 Count: 26 */ + 0x40010A3Bu, /* Base address: 0x40010A00 Count: 59 */ + 0x40010B51u, /* Base address: 0x40010B00 Count: 81 */ + 0x40010D23u, /* Base address: 0x40010D00 Count: 35 */ + 0x40010E49u, /* Base address: 0x40010E00 Count: 73 */ + 0x40010F35u, /* Base address: 0x40010F00 Count: 53 */ + 0x4001145Bu, /* Base address: 0x40011400 Count: 91 */ + 0x40011543u, /* Base address: 0x40011500 Count: 67 */ + 0x4001161Eu, /* Base address: 0x40011600 Count: 30 */ + 0x40011750u, /* Base address: 0x40011700 Count: 80 */ + 0x4001190Du, /* Base address: 0x40011900 Count: 13 */ + 0x40011B03u, /* Base address: 0x40011B00 Count: 3 */ + 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */ + 0x40014119u, /* Base address: 0x40014100 Count: 25 */ + 0x4001420Cu, /* Base address: 0x40014200 Count: 12 */ + 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */ + 0x4001440Eu, /* Base address: 0x40014400 Count: 14 */ + 0x40014514u, /* Base address: 0x40014500 Count: 20 */ + 0x40014609u, /* Base address: 0x40014600 Count: 9 */ + 0x4001470Cu, /* Base address: 0x40014700 Count: 12 */ + 0x40014805u, /* Base address: 0x40014800 Count: 5 */ + 0x4001490Fu, /* Base address: 0x40014900 Count: 15 */ + 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */ + 0x40015002u, /* Base address: 0x40015000 Count: 2 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; @@ -420,1160 +421,1401 @@ void cyfitter_cfg(void) {0x36u, 0x02u}, {0x7Eu, 0x02u}, {0x01u, 0x20u}, - {0x0Au, 0x4Bu}, - {0x00u, 0x05u}, - {0x01u, 0x13u}, - {0x18u, 0x0Cu}, - {0x19u, 0x08u}, + {0x0Au, 0x27u}, + {0x00u, 0x04u}, + {0x01u, 0x11u}, + {0x18u, 0x04u}, {0x1Cu, 0x61u}, - {0x20u, 0x90u}, - {0x21u, 0x58u}, - {0x30u, 0x06u}, - {0x31u, 0x0Cu}, + {0x20u, 0x68u}, + {0x21u, 0xC0u}, + {0x2Cu, 0x0Fu}, + {0x30u, 0x09u}, + {0x31u, 0x0Au}, + {0x34u, 0x90u}, + {0x64u, 0x20u}, {0x7Cu, 0x40u}, - {0x23u, 0x02u}, + {0x24u, 0x02u}, {0x86u, 0x0Fu}, - {0x01u, 0x09u}, - {0x03u, 0x24u}, - {0x05u, 0x09u}, - {0x06u, 0x0Eu}, - {0x07u, 0x12u}, - {0x0Bu, 0x30u}, - {0x0Cu, 0x21u}, - {0x0Eu, 0x84u}, - {0x0Fu, 0x46u}, - {0x12u, 0x21u}, - {0x16u, 0xC0u}, - {0x18u, 0x21u}, - {0x1Au, 0x42u}, - {0x1Bu, 0x01u}, - {0x1Eu, 0x20u}, - {0x1Fu, 0x08u}, - {0x21u, 0x40u}, - {0x22u, 0x10u}, - {0x23u, 0x80u}, - {0x26u, 0x01u}, - {0x2Bu, 0x80u}, - {0x2Cu, 0x08u}, - {0x2Eu, 0x10u}, - {0x2Fu, 0x09u}, - {0x30u, 0x18u}, - {0x31u, 0x07u}, - {0x32u, 0xE0u}, - {0x33u, 0xC0u}, - {0x34u, 0x07u}, - {0x35u, 0x38u}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x04u}, + {0x03u, 0x80u}, + {0x06u, 0x80u}, + {0x07u, 0x07u}, + {0x09u, 0x44u}, + {0x0Bu, 0x88u}, + {0x0Eu, 0x07u}, + {0x10u, 0xAAu}, + {0x11u, 0xAAu}, + {0x12u, 0x55u}, + {0x13u, 0x55u}, + {0x14u, 0x99u}, + {0x15u, 0x99u}, + {0x16u, 0x22u}, + {0x17u, 0x22u}, + {0x1Au, 0x70u}, + {0x1Bu, 0x70u}, + {0x27u, 0x08u}, + {0x28u, 0x44u}, + {0x2Au, 0x88u}, + {0x2Eu, 0x08u}, + {0x30u, 0x0Fu}, + {0x33u, 0x0Fu}, + {0x34u, 0xF0u}, + {0x35u, 0xF0u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Cu, 0x11u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x30u}, - {0x81u, 0x01u}, - {0x82u, 0xC0u}, - {0x84u, 0x09u}, - {0x85u, 0x02u}, - {0x86u, 0x06u}, - {0x87u, 0x04u}, - {0x88u, 0xFFu}, - {0x8Bu, 0x02u}, - {0x8Cu, 0x50u}, - {0x8Du, 0x02u}, - {0x8Eu, 0xA0u}, - {0x8Fu, 0x08u}, - {0x91u, 0x01u}, - {0x94u, 0x03u}, - {0x96u, 0x0Cu}, - {0x97u, 0x0Cu}, - {0x98u, 0x90u}, - {0x9Au, 0x60u}, - {0x9Cu, 0xFFu}, - {0x9Fu, 0x02u}, - {0xA4u, 0x05u}, - {0xA5u, 0x01u}, - {0xA6u, 0x0Au}, - {0xA9u, 0x01u}, - {0xAAu, 0xFFu}, - {0xACu, 0x0Fu}, - {0xAEu, 0xF0u}, - {0xB5u, 0x0Eu}, - {0xB6u, 0xFFu}, - {0xB7u, 0x01u}, - {0xB9u, 0x80u}, + {0x82u, 0x20u}, + {0x84u, 0x02u}, + {0x85u, 0x08u}, + {0x86u, 0x0Du}, + {0x88u, 0x02u}, + {0x8Au, 0x04u}, + {0x8Bu, 0x19u}, + {0x8Cu, 0x0Du}, + {0x8Du, 0x33u}, + {0x8Fu, 0x4Cu}, + {0x90u, 0x10u}, + {0x91u, 0x18u}, + {0x92u, 0x20u}, + {0x93u, 0x60u}, + {0x94u, 0x0Du}, + {0x99u, 0x2Au}, + {0x9Au, 0x10u}, + {0x9Bu, 0x55u}, + {0x9Cu, 0x0Du}, + {0x9Du, 0x01u}, + {0x9Fu, 0x06u}, + {0xA0u, 0x02u}, + {0xA2u, 0x08u}, + {0xA3u, 0x10u}, + {0xA4u, 0x0Du}, + {0xA5u, 0x3Au}, + {0xA7u, 0x45u}, + {0xA8u, 0x01u}, + {0xAAu, 0x02u}, + {0xABu, 0x01u}, + {0xACu, 0x0Du}, + {0xB1u, 0x07u}, + {0xB2u, 0x0Fu}, + {0xB6u, 0x30u}, + {0xB7u, 0x78u}, + {0xBAu, 0x08u}, + {0xBBu, 0x82u}, {0xBEu, 0x40u}, - {0xBFu, 0x40u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, + {0xDBu, 0x04u}, {0xDCu, 0x10u}, {0xDFu, 0x01u}, - {0x00u, 0x88u}, - {0x03u, 0x20u}, - {0x05u, 0x20u}, - {0x06u, 0x42u}, - {0x07u, 0x60u}, - {0x08u, 0x01u}, - {0x0Au, 0x24u}, - {0x0Bu, 0x01u}, - {0x0Eu, 0x08u}, - {0x0Fu, 0x22u}, - {0x11u, 0x44u}, - {0x12u, 0x40u}, - {0x15u, 0xC0u}, - {0x16u, 0x01u}, - {0x17u, 0x18u}, - {0x19u, 0x02u}, - {0x1Au, 0x20u}, - {0x1Bu, 0x30u}, - {0x1Eu, 0x01u}, - {0x20u, 0x40u}, - {0x21u, 0x18u}, - {0x22u, 0x01u}, - {0x24u, 0x02u}, - {0x27u, 0x08u}, - {0x28u, 0x05u}, - {0x29u, 0x40u}, - {0x2Au, 0x11u}, - {0x2Du, 0x08u}, - {0x2Eu, 0x10u}, - {0x30u, 0xA0u}, - {0x35u, 0x40u}, - {0x36u, 0x02u}, - {0x37u, 0x08u}, - {0x38u, 0x44u}, - {0x39u, 0x22u}, - {0x3Cu, 0x80u}, - {0x3Du, 0x10u}, - {0x3Eu, 0x05u}, - {0x58u, 0x82u}, - {0x59u, 0x14u}, - {0x61u, 0x80u}, - {0x81u, 0x10u}, - {0x82u, 0x80u}, - {0x84u, 0x04u}, - {0x89u, 0x10u}, - {0x8Cu, 0x01u}, - {0xC0u, 0xF5u}, - {0xC2u, 0xEFu}, - {0xC4u, 0xEDu}, - {0xCAu, 0x6Du}, - {0xCCu, 0xDCu}, - {0xCEu, 0xFFu}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x08u}, - {0xE2u, 0x48u}, - {0xE6u, 0x02u}, - {0x06u, 0xFFu}, - {0x08u, 0xFFu}, - {0x0Cu, 0x50u}, - {0x0Du, 0x04u}, - {0x0Eu, 0xA0u}, - {0x0Fu, 0x03u}, - {0x11u, 0x01u}, - {0x12u, 0xFFu}, - {0x13u, 0x06u}, - {0x14u, 0x03u}, - {0x15u, 0x03u}, - {0x16u, 0x0Cu}, - {0x17u, 0x04u}, - {0x18u, 0x60u}, - {0x19u, 0x05u}, - {0x1Au, 0x90u}, - {0x1Bu, 0x02u}, - {0x1Cu, 0x0Fu}, - {0x1Eu, 0xF0u}, - {0x24u, 0x05u}, - {0x26u, 0x0Au}, - {0x28u, 0x06u}, - {0x2Au, 0x09u}, - {0x2Cu, 0x30u}, - {0x2Eu, 0xC0u}, - {0x32u, 0xFFu}, - {0x37u, 0x07u}, - {0x3Bu, 0x80u}, - {0x3Eu, 0x04u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Fu, 0x01u}, - {0x82u, 0x3Fu}, - {0x84u, 0x01u}, - {0x89u, 0x01u}, - {0x8Cu, 0x34u}, - {0x8Eu, 0x4Bu}, - {0x98u, 0x0Bu}, - {0x9Au, 0x64u}, - {0x9Cu, 0x08u}, - {0x9Eu, 0x52u}, - {0xA6u, 0x20u}, - {0xB2u, 0x40u}, - {0xB4u, 0x07u}, - {0xB6u, 0x38u}, - {0xB7u, 0x01u}, - {0xBEu, 0x04u}, - {0xBFu, 0x40u}, - {0xC0u, 0x54u}, - {0xC1u, 0x02u}, - {0xC2u, 0x30u}, - {0xC5u, 0xE2u}, - {0xC6u, 0xCFu}, - {0xC7u, 0x0Du}, - {0xC8u, 0x1Fu}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCFu, 0x2Cu}, - {0xD6u, 0x01u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDAu, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x01u}, - {0xDDu, 0x01u}, - {0xDFu, 0x01u}, - {0xE2u, 0xC0u}, - {0xE6u, 0x80u}, - {0xE8u, 0x40u}, - {0xE9u, 0x40u}, - {0xEEu, 0x08u}, - {0x00u, 0x80u}, - {0x02u, 0x40u}, - {0x03u, 0x10u}, - {0x05u, 0x20u}, - {0x06u, 0x02u}, - {0x07u, 0x10u}, - {0x0Au, 0x05u}, - {0x0Cu, 0x01u}, - {0x0Du, 0x40u}, - {0x0Eu, 0x08u}, - {0x0Fu, 0x20u}, - {0x13u, 0x04u}, - {0x14u, 0x08u}, - {0x16u, 0x01u}, - {0x17u, 0x68u}, - {0x18u, 0x14u}, - {0x19u, 0x40u}, - {0x1Au, 0x0Du}, - {0x1Bu, 0x80u}, - {0x1Eu, 0x10u}, - {0x22u, 0x40u}, - {0x25u, 0x40u}, - {0x28u, 0x01u}, - {0x29u, 0x04u}, - {0x2Bu, 0x21u}, - {0x35u, 0x11u}, - {0x36u, 0x08u}, - {0x3Au, 0x20u}, - {0x3Du, 0x80u}, - {0x3Eu, 0x80u}, - {0x40u, 0x14u}, - {0x41u, 0x01u}, - {0x49u, 0x40u}, - {0x4Au, 0x40u}, - {0x4Bu, 0x04u}, - {0x51u, 0x10u}, - {0x52u, 0x80u}, - {0x53u, 0x28u}, - {0x58u, 0x14u}, - {0x59u, 0x02u}, - {0x5Au, 0x80u}, - {0x60u, 0x02u}, - {0x62u, 0x04u}, - {0x63u, 0x88u}, - {0x68u, 0x80u}, - {0x69u, 0x54u}, - {0x70u, 0x20u}, - {0x73u, 0x51u}, - {0x83u, 0x04u}, - {0x84u, 0x80u}, - {0x86u, 0x42u}, - {0x88u, 0x02u}, - {0x89u, 0x02u}, - {0x8Cu, 0x04u}, - {0x8Du, 0x40u}, - {0x92u, 0x02u}, - {0x94u, 0x04u}, - {0x95u, 0x96u}, - {0x96u, 0x14u}, - {0x97u, 0x81u}, - {0x9Au, 0x30u}, - {0x9Bu, 0x08u}, - {0x9Cu, 0x80u}, - {0x9Du, 0x6Cu}, - {0x9Eu, 0x02u}, - {0x9Fu, 0x70u}, - {0xA0u, 0x04u}, - {0xA3u, 0x10u}, - {0xA4u, 0xE0u}, - {0xA5u, 0x80u}, - {0xA6u, 0x86u}, - {0xA7u, 0x09u}, - {0xAAu, 0x30u}, - {0xAFu, 0x40u}, - {0xB0u, 0x02u}, - {0xB1u, 0x0Au}, - {0xB3u, 0x08u}, - {0xC0u, 0xEDu}, - {0xC2u, 0xF3u}, - {0xC4u, 0xE4u}, - {0xCCu, 0xE0u}, - {0xCEu, 0x14u}, - {0xD0u, 0x07u}, - {0xD2u, 0x08u}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x0Fu}, - {0xE6u, 0x0Cu}, - {0xEAu, 0x04u}, - {0xECu, 0x04u}, - {0xEEu, 0x21u}, - {0x01u, 0x9Bu}, - {0x03u, 0x04u}, - {0x04u, 0x03u}, - {0x06u, 0x0Cu}, - {0x07u, 0x40u}, - {0x08u, 0x30u}, - {0x09u, 0x0Cu}, - {0x0Au, 0xC0u}, - {0x0Bu, 0x80u}, - {0x0Cu, 0x0Fu}, + {0x00u, 0x48u}, + {0x05u, 0x56u}, + {0x09u, 0x0Au}, + {0x0Au, 0x04u}, {0x0Du, 0x20u}, - {0x0Eu, 0xF0u}, + {0x0Eu, 0x11u}, {0x0Fu, 0x40u}, - {0x10u, 0x50u}, - {0x12u, 0xA0u}, - {0x15u, 0x98u}, - {0x17u, 0x04u}, + {0x11u, 0x50u}, + {0x15u, 0x24u}, + {0x16u, 0x02u}, + {0x17u, 0x01u}, + {0x18u, 0x40u}, + {0x1Au, 0x0Cu}, {0x1Bu, 0x01u}, - {0x1Cu, 0x06u}, - {0x1Du, 0x80u}, - {0x1Eu, 0x09u}, - {0x1Fu, 0x17u}, - {0x20u, 0x05u}, - {0x22u, 0x0Au}, - {0x23u, 0x20u}, - {0x24u, 0x60u}, - {0x25u, 0x03u}, - {0x26u, 0x90u}, - {0x27u, 0x0Cu}, - {0x29u, 0x02u}, - {0x2Fu, 0x1Fu}, - {0x31u, 0x1Fu}, - {0x34u, 0xFFu}, - {0x35u, 0x60u}, - {0x37u, 0x80u}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x50u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Cu, 0x10u}, - {0x5Fu, 0x01u}, - {0x81u, 0x35u}, - {0x89u, 0x39u}, - {0x8Bu, 0x42u}, - {0x8Fu, 0x04u}, - {0x91u, 0x20u}, - {0x95u, 0x4Au}, - {0x97u, 0x31u}, - {0x99u, 0x0Bu}, - {0x9Bu, 0x70u}, - {0x9Du, 0x12u}, - {0x9Fu, 0x01u}, - {0xA1u, 0x35u}, - {0xA5u, 0x15u}, - {0xA7u, 0x20u}, - {0xA9u, 0x05u}, - {0xABu, 0x30u}, - {0xADu, 0x30u}, - {0xAFu, 0x05u}, - {0xB3u, 0x78u}, - {0xB5u, 0x04u}, - {0xB7u, 0x03u}, - {0xB9u, 0x08u}, - {0xBBu, 0x80u}, - {0xBFu, 0x10u}, - {0xC0u, 0x62u}, - {0xC1u, 0x04u}, - {0xC2u, 0x10u}, - {0xC4u, 0x05u}, - {0xC5u, 0xCEu}, - {0xC6u, 0xFDu}, - {0xC7u, 0x0Bu}, - {0xC8u, 0x1Fu}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCCu, 0x22u}, - {0xCEu, 0xF0u}, - {0xCFu, 0x08u}, - {0xD0u, 0x04u}, - {0xD4u, 0x40u}, - {0xD6u, 0x04u}, - {0xD9u, 0x04u}, - {0xDAu, 0x04u}, - {0xDBu, 0x04u}, - {0xDFu, 0x01u}, - {0xE2u, 0xC0u}, - {0xE4u, 0x40u}, - {0xE5u, 0x01u}, - {0xE6u, 0x10u}, - {0xE7u, 0x11u}, - {0xE8u, 0xC0u}, - {0xE9u, 0x01u}, - {0xEBu, 0x11u}, - {0xECu, 0x40u}, - {0xEDu, 0x01u}, - {0xEEu, 0x40u}, - {0xEFu, 0x01u}, - {0x00u, 0x64u}, - {0x09u, 0x01u}, - {0x0Au, 0x02u}, - {0x10u, 0x40u}, - {0x12u, 0x10u}, - {0x19u, 0x20u}, - {0x20u, 0x80u}, - {0x21u, 0x81u}, - {0x22u, 0x10u}, - {0x24u, 0x02u}, - {0x26u, 0xACu}, - {0x28u, 0xC1u}, - {0x2Au, 0x48u}, - {0x2Bu, 0x08u}, - {0x2Du, 0x40u}, - {0x2Eu, 0x12u}, - {0x2Fu, 0x20u}, - {0x30u, 0x10u}, - {0x32u, 0x04u}, - {0x33u, 0x90u}, - {0x35u, 0x12u}, - {0x36u, 0x88u}, - {0x38u, 0x48u}, - {0x39u, 0xA2u}, - {0x3Du, 0x21u}, - {0x3Fu, 0x80u}, - {0x45u, 0x62u}, - {0x4Du, 0x82u}, - {0x4Eu, 0x08u}, - {0x4Fu, 0x05u}, - {0x55u, 0x04u}, - {0x56u, 0x24u}, - {0x57u, 0x40u}, - {0x64u, 0x02u}, - {0x66u, 0x20u}, - {0x67u, 0xA0u}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x14u}, - {0x78u, 0x02u}, - {0x7Bu, 0x40u}, - {0x7Eu, 0x20u}, - {0x7Fu, 0x10u}, - {0x82u, 0x40u}, - {0x88u, 0x40u}, - {0x8Eu, 0x19u}, - {0x91u, 0x20u}, - {0x92u, 0x0Eu}, - {0x93u, 0x50u}, - {0x95u, 0x82u}, - {0x97u, 0x80u}, - {0x9Au, 0x90u}, - {0x9Bu, 0x08u}, - {0x9Cu, 0x08u}, - {0x9Du, 0x39u}, - {0x9Eu, 0x41u}, - {0x9Fu, 0x14u}, - {0xA0u, 0x04u}, - {0xA3u, 0x88u}, - {0xA4u, 0x40u}, - {0xA5u, 0x80u}, - {0xA6u, 0x0Au}, - {0xAAu, 0x04u}, - {0xABu, 0x14u}, - {0xACu, 0x15u}, - {0xB1u, 0x40u}, - {0xB3u, 0x08u}, - {0xB5u, 0x40u}, - {0xB6u, 0x04u}, - {0xB7u, 0x40u}, - {0xC0u, 0x07u}, - {0xC2u, 0x09u}, - {0xC4u, 0x0Cu}, - {0xCAu, 0xFFu}, - {0xCCu, 0xFEu}, - {0xCEu, 0xBFu}, - {0xD0u, 0xB0u}, - {0xD2u, 0x30u}, - {0xD8u, 0xF0u}, - {0xE2u, 0x41u}, - {0xEAu, 0x0Au}, - {0xEEu, 0x06u}, - {0x00u, 0x24u}, - {0x01u, 0x01u}, - {0x04u, 0x6Cu}, - {0x05u, 0x10u}, - {0x0Au, 0x2Fu}, - {0x0Bu, 0x40u}, - {0x0Cu, 0x2Cu}, - {0x0Eu, 0x40u}, - {0x10u, 0x31u}, - {0x11u, 0x07u}, - {0x12u, 0x02u}, - {0x13u, 0xD8u}, - {0x14u, 0x40u}, - {0x15u, 0x08u}, - {0x16u, 0x2Cu}, - {0x17u, 0x61u}, - {0x18u, 0x11u}, - {0x19u, 0xA2u}, - {0x1Au, 0x0Eu}, - {0x1Bu, 0x08u}, - {0x1Cu, 0x08u}, - {0x1Du, 0x01u}, - {0x1Eu, 0x10u}, - {0x20u, 0x6Cu}, - {0x21u, 0x01u}, - {0x24u, 0x80u}, - {0x25u, 0x01u}, - {0x28u, 0x64u}, - {0x29u, 0x04u}, + {0x1Cu, 0x02u}, + {0x1Du, 0x04u}, + {0x21u, 0x24u}, + {0x27u, 0x42u}, {0x2Au, 0x08u}, - {0x2Cu, 0x80u}, - {0x2Du, 0x01u}, - {0x30u, 0x0Fu}, - {0x31u, 0x3Fu}, - {0x32u, 0x80u}, - {0x34u, 0x31u}, - {0x35u, 0xE0u}, - {0x36u, 0x40u}, - {0x37u, 0x08u}, - {0x38u, 0x08u}, - {0x39u, 0x02u}, - {0x3Au, 0x30u}, + {0x2Fu, 0x54u}, + {0x31u, 0x2Au}, + {0x36u, 0x10u}, + {0x37u, 0x42u}, + {0x38u, 0x02u}, + {0x39u, 0x18u}, + {0x3Bu, 0x24u}, + {0x3Du, 0x08u}, {0x3Eu, 0x40u}, - {0x3Fu, 0x41u}, - {0x56u, 0x02u}, - {0x57u, 0x20u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Fu, 0x01u}, - {0x81u, 0xC0u}, - {0x82u, 0x49u}, - {0x83u, 0x01u}, - {0x86u, 0x06u}, - {0x87u, 0x9Fu}, - {0x89u, 0xC0u}, - {0x8Bu, 0x08u}, - {0x8Cu, 0x09u}, - {0x8Du, 0xC0u}, - {0x8Eu, 0x24u}, - {0x8Fu, 0x02u}, - {0x91u, 0x90u}, - {0x93u, 0x40u}, - {0x97u, 0xFFu}, - {0x98u, 0x09u}, - {0x99u, 0xC0u}, - {0x9Au, 0x52u}, - {0x9Bu, 0x04u}, - {0x9Du, 0x80u}, - {0x9Eu, 0x30u}, - {0xA1u, 0x1Fu}, - {0xA3u, 0x20u}, - {0xA7u, 0x60u}, - {0xA9u, 0x7Fu}, - {0xAAu, 0x08u}, - {0xABu, 0x80u}, - {0xAEu, 0x01u}, - {0xB0u, 0x40u}, - {0xB3u, 0xFFu}, - {0xB4u, 0x07u}, - {0xB6u, 0x38u}, - {0xBEu, 0x01u}, - {0xBFu, 0x04u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDCu, 0x01u}, - {0xDFu, 0x01u}, - {0x00u, 0x84u}, - {0x03u, 0x80u}, - {0x04u, 0x02u}, - {0x05u, 0x10u}, - {0x06u, 0x20u}, - {0x07u, 0x01u}, - {0x08u, 0x80u}, - {0x0Au, 0x05u}, - {0x0Du, 0x02u}, - {0x0Eu, 0x18u}, - {0x0Fu, 0x01u}, - {0x13u, 0x50u}, - {0x15u, 0x09u}, - {0x17u, 0x50u}, - {0x18u, 0x04u}, - {0x1Au, 0x01u}, - {0x1Bu, 0x01u}, - {0x1Du, 0xB7u}, - {0x1Eu, 0x02u}, - {0x1Fu, 0x08u}, - {0x21u, 0x04u}, - {0x25u, 0x10u}, - {0x26u, 0x50u}, - {0x27u, 0x40u}, - {0x29u, 0x15u}, - {0x2Du, 0x40u}, - {0x2Eu, 0x02u}, - {0x2Fu, 0x28u}, - {0x32u, 0x88u}, - {0x33u, 0x11u}, - {0x35u, 0x11u}, - {0x36u, 0x88u}, - {0x38u, 0x80u}, - {0x39u, 0x10u}, - {0x3Au, 0x06u}, - {0x3Du, 0x29u}, - {0x45u, 0xC0u}, - {0x66u, 0x80u}, - {0x6Cu, 0x40u}, - {0x6Du, 0x51u}, - {0x6Eu, 0x10u}, - {0x6Fu, 0x31u}, - {0x75u, 0x80u}, - {0x76u, 0x02u}, - {0x81u, 0x80u}, - {0x82u, 0x20u}, - {0x8Bu, 0x01u}, - {0x90u, 0x02u}, - {0x92u, 0x04u}, - {0x93u, 0x55u}, - {0x94u, 0x04u}, - {0x95u, 0xC1u}, - {0x96u, 0x10u}, - {0x98u, 0x10u}, - {0x99u, 0x20u}, - {0x9Au, 0x85u}, - {0x9Bu, 0x08u}, - {0x9Cu, 0x88u}, - {0x9Du, 0x19u}, - {0x9Eu, 0x02u}, - {0xA0u, 0x44u}, - {0xA1u, 0x04u}, - {0xA2u, 0x8Cu}, - {0xA3u, 0x80u}, - {0xA5u, 0x62u}, - {0xA6u, 0x02u}, - {0xA7u, 0x20u}, - {0xA8u, 0x04u}, - {0xA9u, 0x93u}, - {0xACu, 0x10u}, - {0xB0u, 0x01u}, - {0xC0u, 0xFDu}, - {0xC2u, 0xF3u}, + {0x3Fu, 0x20u}, + {0x59u, 0x80u}, + {0x5Bu, 0x20u}, + {0x60u, 0x04u}, + {0x62u, 0x80u}, + {0x63u, 0x08u}, + {0x6Cu, 0x02u}, + {0x6Du, 0x08u}, + {0x6Fu, 0x18u}, + {0x83u, 0x18u}, + {0x84u, 0x50u}, + {0x88u, 0x01u}, + {0x89u, 0x04u}, + {0x8Au, 0x04u}, + {0x8Bu, 0x02u}, + {0x8Fu, 0x04u}, + {0xC0u, 0xF5u}, + {0xC2u, 0xFEu}, {0xC4u, 0xF3u}, - {0xCAu, 0xF7u}, - {0xCCu, 0xFFu}, - {0xCEu, 0xEFu}, - {0xD8u, 0x10u}, - {0xE2u, 0x89u}, - {0xE6u, 0x20u}, - {0xEAu, 0x08u}, - {0xEEu, 0x01u}, - {0x90u, 0x08u}, - {0x91u, 0x40u}, - {0x9Bu, 0x01u}, - {0x9Eu, 0x20u}, - {0xA2u, 0x10u}, - {0xA9u, 0x04u}, - {0xAEu, 0x40u}, - {0xE2u, 0x09u}, - {0xE6u, 0x20u}, - {0xEEu, 0x20u}, - {0xB9u, 0x08u}, - {0xBFu, 0x04u}, - {0xD9u, 0x04u}, - {0xDFu, 0x01u}, - {0x27u, 0x20u}, - {0x83u, 0x20u}, - {0x8Bu, 0x04u}, - {0x8Fu, 0x10u}, - {0x90u, 0x08u}, - {0x91u, 0x40u}, - {0x97u, 0x04u}, - {0x99u, 0x04u}, - {0x9Au, 0x40u}, - {0x9Bu, 0x11u}, - {0x9Eu, 0x20u}, - {0xA2u, 0x10u}, - {0xA9u, 0x54u}, - {0xADu, 0x05u}, - {0xAFu, 0x01u}, - {0xB1u, 0x02u}, - {0xB2u, 0x18u}, - {0xB4u, 0x40u}, - {0xB5u, 0x41u}, - {0xE2u, 0x10u}, - {0xE4u, 0x20u}, - {0xE6u, 0x40u}, - {0xE8u, 0xC4u}, - {0xEAu, 0x01u}, - {0xECu, 0x80u}, - {0xEEu, 0x50u}, - {0x02u, 0x04u}, - {0x06u, 0x20u}, - {0x08u, 0x21u}, - {0x0Au, 0x42u}, - {0x0Eu, 0x04u}, - {0x11u, 0x20u}, - {0x13u, 0x90u}, - {0x15u, 0x04u}, - {0x16u, 0x18u}, - {0x17u, 0x08u}, - {0x18u, 0x04u}, - {0x1Au, 0x10u}, - {0x1Bu, 0x01u}, - {0x1Eu, 0x02u}, - {0x21u, 0x10u}, - {0x22u, 0x40u}, - {0x23u, 0x20u}, - {0x24u, 0x04u}, - {0x25u, 0x08u}, + {0xCAu, 0xE2u}, + {0xCCu, 0xB7u}, + {0xCEu, 0x77u}, + {0xD6u, 0x0Cu}, + {0xD8u, 0x0Cu}, + {0xE0u, 0x04u}, + {0xE2u, 0xA0u}, + {0xE6u, 0x02u}, + {0x01u, 0x60u}, + {0x04u, 0x06u}, + {0x06u, 0x01u}, + {0x08u, 0x04u}, + {0x09u, 0x04u}, + {0x0Bu, 0x03u}, + {0x10u, 0x1Fu}, + {0x11u, 0x2Du}, + {0x13u, 0x12u}, + {0x16u, 0x1Eu}, + {0x18u, 0x01u}, + {0x19u, 0x1Bu}, + {0x1Au, 0x18u}, + {0x1Bu, 0x44u}, + {0x24u, 0x07u}, {0x26u, 0x08u}, - {0x27u, 0x44u}, - {0x29u, 0x4Du}, - {0x2Au, 0x01u}, - {0x2Bu, 0xB2u}, - {0x2Cu, 0x80u}, - {0x2Fu, 0x02u}, - {0x30u, 0x03u}, - {0x31u, 0xC0u}, - {0x32u, 0x1Cu}, - {0x33u, 0x03u}, - {0x34u, 0x80u}, - {0x36u, 0x60u}, - {0x37u, 0x3Cu}, - {0x3Eu, 0x51u}, - {0x3Fu, 0x45u}, + {0x29u, 0x19u}, + {0x2Au, 0x02u}, + {0x2Bu, 0x26u}, + {0x2Cu, 0x17u}, + {0x30u, 0x1Eu}, + {0x31u, 0x70u}, + {0x33u, 0x07u}, + {0x34u, 0x01u}, + {0x35u, 0x08u}, + {0x39u, 0x02u}, + {0x3Bu, 0x08u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x10u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Cu, 0x01u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x8Bu, 0x08u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x10u}, - {0x91u, 0x04u}, - {0x93u, 0x08u}, + {0x80u, 0x40u}, + {0x81u, 0x02u}, + {0x85u, 0x01u}, + {0x8Au, 0x07u}, + {0x8Du, 0x04u}, + {0x8Eu, 0x20u}, + {0x8Fu, 0x08u}, + {0x90u, 0x0Au}, + {0x92u, 0x05u}, + {0x94u, 0x09u}, + {0x96u, 0x02u}, {0x97u, 0x04u}, - {0x98u, 0x02u}, - {0xA5u, 0x01u}, - {0xA9u, 0x02u}, - {0xACu, 0x04u}, - {0xB0u, 0x02u}, + {0x98u, 0x04u}, + {0x99u, 0x02u}, + {0x9Au, 0x08u}, + {0xA1u, 0x02u}, + {0xA2u, 0x08u}, + {0xA6u, 0x10u}, + {0xABu, 0x08u}, + {0xACu, 0x10u}, + {0xADu, 0x02u}, + {0xAEu, 0x20u}, + {0xB0u, 0x30u}, {0xB1u, 0x02u}, - {0xB3u, 0x10u}, - {0xB4u, 0x01u}, - {0xB5u, 0x0Cu}, - {0xB6u, 0x04u}, - {0xB7u, 0x01u}, - {0xBEu, 0x51u}, - {0xBFu, 0x55u}, + {0xB2u, 0x0Fu}, + {0xB3u, 0x01u}, + {0xB4u, 0x40u}, + {0xB7u, 0x0Cu}, + {0xB9u, 0x02u}, + {0xBEu, 0x11u}, + {0xBFu, 0x45u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x01u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x03u, 0x02u}, - {0x04u, 0x40u}, - {0x05u, 0x02u}, - {0x06u, 0x24u}, - {0x09u, 0x10u}, - {0x0Cu, 0x80u}, - {0x0Eu, 0x20u}, - {0x0Fu, 0x04u}, - {0x10u, 0x01u}, - {0x14u, 0x08u}, - {0x16u, 0x40u}, - {0x17u, 0x48u}, - {0x19u, 0x61u}, - {0x1Du, 0x90u}, - {0x1Eu, 0xA0u}, - {0x21u, 0x45u}, - {0x22u, 0x10u}, + {0x00u, 0x20u}, + {0x02u, 0x82u}, + {0x03u, 0x08u}, + {0x04u, 0x20u}, + {0x05u, 0x08u}, + {0x09u, 0x0Au}, + {0x0Au, 0x04u}, + {0x0Eu, 0x44u}, + {0x0Fu, 0x20u}, + {0x11u, 0x01u}, + {0x13u, 0x44u}, + {0x14u, 0x21u}, + {0x17u, 0x10u}, + {0x19u, 0x20u}, + {0x1Au, 0x80u}, + {0x1Bu, 0x08u}, + {0x1Du, 0x02u}, + {0x1Eu, 0x40u}, + {0x1Fu, 0x20u}, + {0x20u, 0x12u}, + {0x22u, 0x01u}, {0x24u, 0x80u}, - {0x25u, 0x04u}, - {0x27u, 0x01u}, - {0x2Au, 0x18u}, - {0x2Cu, 0xA8u}, - {0x2Du, 0x40u}, - {0x31u, 0x02u}, - {0x32u, 0x08u}, - {0x34u, 0x08u}, - {0x36u, 0x11u}, - {0x39u, 0x10u}, - {0x3Au, 0x80u}, - {0x6Cu, 0x04u}, - {0x6Du, 0x50u}, - {0x6Eu, 0x02u}, - {0x6Fu, 0x10u}, - {0x74u, 0x90u}, - {0x75u, 0x04u}, - {0x76u, 0x40u}, - {0x81u, 0x10u}, - {0x83u, 0x40u}, + {0x25u, 0x01u}, + {0x27u, 0x28u}, + {0x28u, 0x04u}, + {0x29u, 0x01u}, + {0x2Bu, 0x02u}, + {0x2Eu, 0x20u}, + {0x32u, 0x28u}, + {0x35u, 0x10u}, + {0x37u, 0x01u}, + {0x38u, 0x04u}, + {0x39u, 0x22u}, + {0x3Au, 0x20u}, + {0x3Bu, 0x40u}, + {0x3Du, 0x02u}, + {0x3Fu, 0x10u}, + {0x45u, 0x40u}, + {0x46u, 0x02u}, + {0x58u, 0x98u}, + {0x5Cu, 0x40u}, + {0x5Fu, 0x30u}, + {0x60u, 0x02u}, + {0x62u, 0x14u}, + {0x66u, 0x80u}, + {0x80u, 0x02u}, + {0x81u, 0x02u}, + {0x82u, 0x40u}, {0x84u, 0x01u}, - {0x85u, 0x10u}, - {0x87u, 0x02u}, - {0x89u, 0x60u}, - {0x8Au, 0x80u}, - {0x8Cu, 0x08u}, - {0x8Du, 0x02u}, - {0x8Eu, 0x1Cu}, - {0x8Fu, 0x08u}, - {0x94u, 0x80u}, - {0x98u, 0x08u}, - {0xA0u, 0x20u}, - {0xA4u, 0x10u}, - {0xA5u, 0x80u}, - {0xA6u, 0x40u}, - {0xA8u, 0x08u}, - {0xA9u, 0x80u}, - {0xC0u, 0xF1u}, - {0xC2u, 0xE2u}, - {0xC4u, 0xF1u}, - {0xCAu, 0xF6u}, - {0xCCu, 0xE3u}, - {0xCEu, 0x0Cu}, - {0xE2u, 0xAAu}, - {0xE4u, 0x50u}, - {0xE6u, 0x01u}, - {0xE8u, 0x80u}, - {0xEAu, 0x04u}, - {0x80u, 0x40u}, - {0x84u, 0x10u}, - {0x86u, 0x40u}, - {0x88u, 0x20u}, + {0x85u, 0x80u}, + {0x88u, 0x04u}, + {0x8Au, 0x01u}, + {0x8Bu, 0x20u}, + {0x8Cu, 0x0Au}, + {0x90u, 0x04u}, + {0x92u, 0x08u}, + {0x93u, 0x04u}, + {0x94u, 0x02u}, + {0x95u, 0x64u}, + {0x96u, 0x51u}, + {0x97u, 0xE8u}, + {0x98u, 0x10u}, + {0x99u, 0x01u}, + {0x9Bu, 0x50u}, + {0x9Cu, 0x40u}, + {0x9Du, 0xD2u}, + {0x9Eu, 0x0Au}, + {0x9Fu, 0x01u}, + {0xA0u, 0x02u}, + {0xA1u, 0x04u}, + {0xA2u, 0x80u}, + {0xA3u, 0x11u}, + {0xA4u, 0x04u}, + {0xA5u, 0x0Au}, + {0xA6u, 0x10u}, + {0xABu, 0x10u}, + {0xAFu, 0x20u}, + {0xB1u, 0x20u}, + {0xB4u, 0x40u}, + {0xB5u, 0x01u}, + {0xC0u, 0x6Bu}, + {0xC2u, 0x7Eu}, + {0xC4u, 0xEDu}, + {0xCAu, 0x2Du}, + {0xCCu, 0xA6u}, + {0xCEu, 0xABu}, + {0xD6u, 0x1Eu}, + {0xD8u, 0x1Eu}, {0xE0u, 0x01u}, - {0xE4u, 0x20u}, - {0xABu, 0x21u}, - {0xAFu, 0x80u}, - {0xB0u, 0x08u}, - {0xB1u, 0x40u}, - {0xB2u, 0x10u}, - {0xB7u, 0x40u}, - {0x00u, 0x21u}, - {0x01u, 0x02u}, - {0x02u, 0x02u}, - {0x03u, 0x0Du}, - {0x04u, 0xE0u}, - {0x05u, 0x60u}, - {0x08u, 0x88u}, - {0x09u, 0x0Du}, - {0x0Au, 0x03u}, - {0x0Eu, 0x01u}, - {0x11u, 0x91u}, - {0x13u, 0x22u}, - {0x15u, 0x92u}, - {0x16u, 0xECu}, - {0x17u, 0x44u}, + {0xE2u, 0x28u}, + {0xEAu, 0x02u}, + {0xEEu, 0x01u}, + {0x00u, 0x02u}, + {0x09u, 0x01u}, + {0x14u, 0x01u}, + {0x28u, 0x04u}, + {0x2Du, 0x02u}, + {0x30u, 0x02u}, + {0x31u, 0x01u}, + {0x34u, 0x04u}, + {0x36u, 0x01u}, + {0x37u, 0x02u}, + {0x3Eu, 0x51u}, + {0x3Fu, 0x41u}, + {0x40u, 0x24u}, + {0x41u, 0x03u}, + {0x42u, 0x10u}, + {0x45u, 0xFCu}, + {0x46u, 0xD2u}, + {0x47u, 0x0Eu}, + {0x48u, 0x1Fu}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Fu, 0x2Cu}, + {0x56u, 0x01u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Au, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Du, 0x01u}, + {0x5Fu, 0x01u}, + {0x62u, 0xC0u}, + {0x66u, 0x80u}, + {0x68u, 0x40u}, + {0x69u, 0x40u}, + {0x6Eu, 0x08u}, + {0x84u, 0x0Bu}, + {0x86u, 0x14u}, + {0x8Du, 0x01u}, + {0x90u, 0x34u}, + {0x92u, 0x0Bu}, + {0x96u, 0x3Fu}, + {0x98u, 0x08u}, + {0x9Au, 0x22u}, + {0x9Eu, 0x10u}, + {0xA8u, 0x01u}, + {0xAFu, 0x02u}, + {0xB2u, 0x07u}, + {0xB3u, 0x02u}, + {0xB4u, 0x38u}, + {0xB5u, 0x01u}, + {0xBFu, 0x10u}, + {0xD4u, 0x09u}, + {0xD6u, 0x04u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x01u}, + {0xDFu, 0x01u}, + {0x02u, 0x40u}, + {0x05u, 0x04u}, + {0x08u, 0x08u}, + {0x0Du, 0x42u}, + {0x0Eu, 0x04u}, + {0x0Fu, 0x20u}, + {0x12u, 0x04u}, + {0x17u, 0x10u}, {0x18u, 0x04u}, - {0x19u, 0xA2u}, - {0x1Au, 0x43u}, - {0x1Bu, 0x18u}, - {0x1Du, 0x0Du}, - {0x21u, 0x0Du}, - {0x25u, 0x0Du}, - {0x2Au, 0x12u}, - {0x2Du, 0x0Du}, + {0x19u, 0x01u}, + {0x1Bu, 0x40u}, + {0x1Du, 0x0Cu}, + {0x1Eu, 0x24u}, + {0x1Fu, 0x30u}, + {0x23u, 0x81u}, + {0x27u, 0x24u}, + {0x28u, 0x06u}, + {0x2Au, 0x10u}, + {0x2Cu, 0x02u}, + {0x3Au, 0x10u}, + {0x3Eu, 0x80u}, + {0x41u, 0x0Au}, + {0x42u, 0x04u}, + {0x43u, 0x40u}, + {0x49u, 0x08u}, + {0x4Bu, 0x02u}, + {0x50u, 0x10u}, + {0x51u, 0x40u}, + {0x52u, 0x08u}, + {0x53u, 0x40u}, + {0x59u, 0x21u}, + {0x5Bu, 0x84u}, + {0x5Cu, 0x40u}, + {0x5Du, 0x10u}, + {0x5Eu, 0x02u}, + {0x5Fu, 0x04u}, + {0x60u, 0x14u}, + {0x63u, 0x81u}, + {0x64u, 0x40u}, + {0x65u, 0x80u}, + {0x68u, 0x04u}, + {0x69u, 0x49u}, + {0x70u, 0x09u}, + {0x72u, 0x0Au}, + {0x83u, 0x01u}, + {0x86u, 0x08u}, + {0x88u, 0x20u}, + {0x8Au, 0x04u}, + {0x8Bu, 0x04u}, + {0x8Cu, 0x98u}, + {0x90u, 0x90u}, + {0x92u, 0x08u}, + {0x93u, 0x10u}, + {0x94u, 0x22u}, + {0x95u, 0x67u}, + {0x96u, 0x15u}, + {0x97u, 0xE8u}, + {0x98u, 0x02u}, + {0x99u, 0x20u}, + {0x9Au, 0x94u}, + {0x9Bu, 0x58u}, + {0x9Cu, 0x60u}, + {0x9Du, 0x58u}, + {0x9Eu, 0x08u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x10u}, + {0xA1u, 0x06u}, + {0xA2u, 0x80u}, + {0xA3u, 0x11u}, + {0xA4u, 0x04u}, + {0xA5u, 0x48u}, + {0xA6u, 0x30u}, + {0xA7u, 0x02u}, + {0xA8u, 0x40u}, + {0xAAu, 0x02u}, + {0xACu, 0x01u}, + {0xADu, 0x0Au}, + {0xAEu, 0x08u}, + {0xB0u, 0x80u}, + {0xB6u, 0x04u}, + {0xC0u, 0x28u}, + {0xC2u, 0xF4u}, + {0xC4u, 0x42u}, + {0xCAu, 0x18u}, + {0xCEu, 0x14u}, + {0xD0u, 0x0Fu}, + {0xD6u, 0xFFu}, + {0xD8u, 0x9Fu}, + {0xE0u, 0x08u}, + {0xE4u, 0x04u}, + {0xEAu, 0x09u}, + {0xEEu, 0x0Cu}, + {0x08u, 0x14u}, + {0x0Au, 0x43u}, + {0x0Bu, 0xFFu}, + {0x0Cu, 0xE0u}, + {0x0Du, 0x69u}, + {0x0Fu, 0x96u}, + {0x11u, 0x0Fu}, + {0x12u, 0x02u}, + {0x13u, 0xF0u}, + {0x15u, 0x33u}, + {0x17u, 0xCCu}, + {0x18u, 0x21u}, + {0x1Au, 0x12u}, + {0x1Bu, 0xFFu}, + {0x1Du, 0x55u}, + {0x1Eu, 0xECu}, + {0x1Fu, 0xAAu}, + {0x20u, 0x88u}, + {0x21u, 0xFFu}, + {0x22u, 0x13u}, + {0x27u, 0xFFu}, + {0x2Au, 0x01u}, + {0x2Bu, 0xFFu}, {0x30u, 0x10u}, - {0x31u, 0x0Fu}, - {0x32u, 0x0Fu}, - {0x35u, 0x70u}, - {0x36u, 0xE0u}, - {0x37u, 0x80u}, - {0x39u, 0x20u}, + {0x31u, 0xFFu}, + {0x34u, 0xE0u}, + {0x36u, 0x0Fu}, {0x3Bu, 0x02u}, - {0x3Eu, 0x40u}, - {0x3Fu, 0x40u}, - {0x54u, 0x09u}, - {0x56u, 0x04u}, + {0x3Eu, 0x11u}, + {0x56u, 0x02u}, + {0x57u, 0x28u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, + {0x5Cu, 0x10u}, {0x5Fu, 0x01u}, - {0x80u, 0x50u}, - {0x81u, 0x30u}, - {0x82u, 0xA0u}, - {0x83u, 0xC0u}, - {0x84u, 0x03u}, - {0x85u, 0x06u}, - {0x86u, 0x0Cu}, - {0x87u, 0x09u}, + {0x84u, 0x40u}, + {0x85u, 0x03u}, + {0x86u, 0x1Fu}, + {0x87u, 0x0Cu}, + {0x89u, 0x50u}, + {0x8Au, 0x70u}, + {0x8Bu, 0xA0u}, + {0x8Cu, 0x03u}, + {0x8Du, 0x0Fu}, + {0x8Eu, 0x0Cu}, + {0x8Fu, 0xF0u}, + {0x90u, 0x20u}, + {0x92u, 0x4Fu}, + {0x94u, 0x10u}, + {0x95u, 0x05u}, + {0x96u, 0x2Fu}, + {0x97u, 0x0Au}, + {0x98u, 0x05u}, + {0x9Au, 0x0Au}, + {0x9Bu, 0xFFu}, + {0x9Fu, 0xFFu}, + {0xA1u, 0x60u}, + {0xA3u, 0x90u}, + {0xA4u, 0x0Fu}, + {0xA5u, 0xFFu}, + {0xA9u, 0x30u}, + {0xABu, 0xC0u}, + {0xACu, 0x06u}, + {0xADu, 0x06u}, + {0xAEu, 0x09u}, + {0xAFu, 0x09u}, + {0xB4u, 0x7Fu}, + {0xB5u, 0xFFu}, + {0xB9u, 0x80u}, + {0xBFu, 0x50u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x01u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x01u, 0x20u}, + {0x02u, 0x02u}, + {0x03u, 0x20u}, + {0x04u, 0x80u}, + {0x05u, 0x10u}, + {0x08u, 0x10u}, + {0x09u, 0x0Au}, + {0x0Bu, 0x80u}, + {0x0Cu, 0x02u}, + {0x0Du, 0x90u}, + {0x11u, 0x08u}, + {0x12u, 0x01u}, + {0x17u, 0x21u}, + {0x19u, 0x20u}, + {0x1Cu, 0x48u}, + {0x1Du, 0x80u}, + {0x21u, 0x40u}, + {0x22u, 0x20u}, + {0x26u, 0x02u}, + {0x28u, 0x40u}, + {0x29u, 0x02u}, + {0x2Au, 0x08u}, + {0x2Bu, 0x05u}, + {0x2Fu, 0x64u}, + {0x32u, 0x44u}, + {0x33u, 0x10u}, + {0x34u, 0x04u}, + {0x36u, 0x92u}, + {0x38u, 0x04u}, + {0x3Bu, 0x60u}, + {0x3Eu, 0x80u}, + {0x3Fu, 0x20u}, + {0x58u, 0xA0u}, + {0x60u, 0x08u}, + {0x62u, 0x40u}, + {0x67u, 0x10u}, + {0x6Du, 0xC4u}, + {0x6Eu, 0x15u}, + {0x75u, 0xC0u}, + {0x80u, 0x20u}, + {0x82u, 0x08u}, + {0x84u, 0x04u}, + {0x8Au, 0x40u}, + {0x8Bu, 0x40u}, + {0x8Cu, 0x08u}, + {0x8Du, 0x40u}, + {0x90u, 0x80u}, + {0x91u, 0x08u}, + {0x92u, 0x08u}, + {0x93u, 0x18u}, + {0x94u, 0x40u}, + {0x95u, 0x36u}, + {0x96u, 0x11u}, + {0x97u, 0x44u}, + {0x98u, 0x94u}, + {0x9Au, 0x83u}, + {0x9Bu, 0x30u}, + {0x9Cu, 0x08u}, + {0x9Du, 0x50u}, + {0x9Eu, 0x40u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x10u}, + {0xA1u, 0x0Eu}, + {0xA2u, 0x90u}, + {0xA3u, 0x31u}, + {0xA4u, 0x02u}, + {0xA5u, 0x40u}, + {0xA6u, 0x21u}, + {0xA7u, 0x02u}, + {0xA9u, 0x08u}, + {0xAAu, 0x01u}, + {0xADu, 0x80u}, + {0xAFu, 0x08u}, + {0xB0u, 0x10u}, + {0xB5u, 0x08u}, + {0xC0u, 0xC7u}, + {0xC2u, 0xDEu}, + {0xC4u, 0x55u}, + {0xCAu, 0xEFu}, + {0xCCu, 0xFEu}, + {0xCEu, 0x3Eu}, + {0xD6u, 0x0Cu}, + {0xD8u, 0x4Cu}, + {0xE2u, 0x02u}, + {0xE6u, 0x1Du}, + {0xEAu, 0x06u}, + {0xECu, 0x04u}, + {0x81u, 0x80u}, + {0x8Bu, 0x0Au}, + {0x8Fu, 0x80u}, + {0x90u, 0x02u}, + {0x92u, 0x01u}, + {0x9Bu, 0x02u}, + {0x9Fu, 0x48u}, + {0xA0u, 0x80u}, + {0xA1u, 0x80u}, + {0xA2u, 0x04u}, + {0xA3u, 0x08u}, + {0xA4u, 0x10u}, + {0xA6u, 0x20u}, + {0xA7u, 0x80u}, + {0xA8u, 0x08u}, + {0xABu, 0x10u}, + {0xADu, 0x21u}, + {0xB3u, 0x10u}, + {0xB4u, 0x08u}, + {0xB5u, 0x02u}, + {0xE0u, 0x40u}, + {0xE2u, 0x22u}, + {0xE4u, 0x80u}, + {0xE6u, 0x0Cu}, + {0xEAu, 0x22u}, + {0xECu, 0x10u}, + {0x00u, 0x06u}, + {0x0Bu, 0x02u}, + {0x0Cu, 0x04u}, + {0x0Eu, 0x03u}, + {0x11u, 0x02u}, + {0x13u, 0x04u}, + {0x14u, 0x06u}, + {0x18u, 0x02u}, + {0x1Au, 0x04u}, + {0x1Bu, 0x04u}, + {0x23u, 0x01u}, + {0x30u, 0x01u}, + {0x31u, 0x06u}, + {0x33u, 0x01u}, + {0x34u, 0x06u}, + {0x3Au, 0x20u}, + {0x3Fu, 0x01u}, + {0x54u, 0x01u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x10u}, + {0x5Fu, 0x01u}, + {0x82u, 0xFFu}, + {0x84u, 0x0Fu}, + {0x86u, 0xF0u}, + {0x87u, 0xFFu}, + {0x88u, 0x33u}, {0x89u, 0xFFu}, - {0x8Au, 0xFFu}, - {0x8Cu, 0x30u}, - {0x8Eu, 0xC0u}, - {0x90u, 0x0Fu}, - {0x92u, 0xF0u}, - {0x94u, 0x09u}, - {0x95u, 0x03u}, - {0x96u, 0x06u}, - {0x97u, 0x0Cu}, - {0x99u, 0x05u}, + {0x8Au, 0xCCu}, + {0x92u, 0xFFu}, + {0x93u, 0xFFu}, + {0x94u, 0x55u}, + {0x95u, 0x0Fu}, + {0x96u, 0xAAu}, + {0x97u, 0xF0u}, {0x9Au, 0xFFu}, - {0x9Bu, 0x0Au}, - {0x9Du, 0x0Fu}, - {0x9Eu, 0xFFu}, - {0x9Fu, 0xF0u}, - {0xA0u, 0x90u}, - {0xA1u, 0x50u}, - {0xA2u, 0x60u}, - {0xA3u, 0xA0u}, - {0xA4u, 0x05u}, - {0xA6u, 0x0Au}, + {0x9Cu, 0xFFu}, + {0x9Du, 0x33u}, + {0x9Fu, 0xCCu}, + {0xA1u, 0x96u}, + {0xA3u, 0x69u}, + {0xA4u, 0x69u}, + {0xA6u, 0x96u}, {0xA7u, 0xFFu}, {0xABu, 0xFFu}, - {0xADu, 0x60u}, - {0xAFu, 0x90u}, - {0xB1u, 0xFFu}, - {0xB2u, 0xFFu}, - {0xBEu, 0x04u}, - {0xBFu, 0x01u}, + {0xADu, 0x55u}, + {0xAEu, 0xFFu}, + {0xAFu, 0xAAu}, + {0xB3u, 0xFFu}, + {0xB4u, 0xFFu}, + {0xBAu, 0x20u}, + {0xBBu, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, + {0xDFu, 0x01u}, + {0x00u, 0x60u}, + {0x01u, 0x12u}, + {0x04u, 0x04u}, + {0x07u, 0x88u}, + {0x09u, 0x08u}, + {0x0Au, 0x08u}, + {0x0Du, 0x42u}, + {0x0Eu, 0x04u}, + {0x0Fu, 0x20u}, + {0x14u, 0x02u}, + {0x17u, 0x04u}, + {0x19u, 0x03u}, + {0x1Au, 0x0Cu}, + {0x1Cu, 0x04u}, + {0x1Fu, 0x10u}, + {0x21u, 0x08u}, + {0x23u, 0x40u}, + {0x26u, 0x08u}, + {0x27u, 0x10u}, + {0x29u, 0x01u}, + {0x2Cu, 0x08u}, + {0x2Eu, 0x04u}, + {0x2Fu, 0x81u}, + {0x30u, 0x20u}, + {0x32u, 0x01u}, + {0x34u, 0x02u}, + {0x36u, 0x88u}, + {0x39u, 0x10u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x04u}, + {0x5Au, 0x02u}, + {0x5Bu, 0x42u}, + {0x5Cu, 0x28u}, + {0x5Du, 0x81u}, + {0x65u, 0x40u}, + {0x6Cu, 0x21u}, + {0x6Eu, 0x89u}, + {0x6Fu, 0x08u}, + {0x74u, 0x81u}, + {0x76u, 0x24u}, + {0x80u, 0x20u}, + {0x85u, 0x80u}, + {0x8Au, 0x04u}, + {0x8Bu, 0x84u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x20u}, + {0x90u, 0x40u}, + {0x91u, 0x80u}, + {0x92u, 0x10u}, + {0x93u, 0x02u}, + {0x94u, 0x01u}, + {0x97u, 0x44u}, + {0x98u, 0x02u}, + {0x99u, 0x40u}, + {0x9Bu, 0x06u}, + {0x9Eu, 0x24u}, + {0xA1u, 0x80u}, + {0xA2u, 0x80u}, + {0xA3u, 0x10u}, + {0xA4u, 0x11u}, + {0xA5u, 0x02u}, + {0xA6u, 0x64u}, + {0xA7u, 0x08u}, + {0xAAu, 0x04u}, + {0xACu, 0x01u}, + {0xAEu, 0x03u}, + {0xB0u, 0x40u}, + {0xB7u, 0x04u}, + {0xC0u, 0x79u}, + {0xC2u, 0xF6u}, + {0xC4u, 0xA0u}, + {0xCAu, 0xF1u}, + {0xCCu, 0xD5u}, + {0xCEu, 0x64u}, + {0xD6u, 0xF8u}, + {0xD8u, 0x10u}, + {0xE2u, 0x90u}, + {0xE4u, 0x70u}, + {0xEAu, 0x20u}, + {0xECu, 0x10u}, + {0xEEu, 0x04u}, + {0x81u, 0x40u}, + {0x82u, 0x12u}, + {0x87u, 0x40u}, + {0x89u, 0x40u}, + {0x8Au, 0x20u}, + {0x8Fu, 0x10u}, + {0x90u, 0x40u}, + {0x92u, 0x01u}, + {0x93u, 0x02u}, + {0x94u, 0x01u}, + {0x97u, 0x04u}, + {0x98u, 0x02u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0x40u}, + {0x9Eu, 0x26u}, + {0xA1u, 0x80u}, + {0xA2u, 0x80u}, + {0xA4u, 0x10u}, + {0xA5u, 0x02u}, + {0xA6u, 0x66u}, + {0xA7u, 0x08u}, + {0xA8u, 0x02u}, + {0xAEu, 0x04u}, + {0xB2u, 0x04u}, + {0xB3u, 0x08u}, + {0xB4u, 0x90u}, + {0xB7u, 0x04u}, + {0xE0u, 0x90u}, + {0xE2u, 0x48u}, + {0xE4u, 0x02u}, + {0xE6u, 0x80u}, + {0xE8u, 0x40u}, + {0xEAu, 0x02u}, + {0xECu, 0x88u}, + {0xEEu, 0x40u}, + {0x02u, 0x08u}, + {0x05u, 0x01u}, + {0x06u, 0x10u}, + {0x0Cu, 0x0Au}, + {0x0Du, 0x02u}, + {0x0Eu, 0x05u}, + {0x0Fu, 0x04u}, + {0x10u, 0x09u}, + {0x12u, 0x02u}, + {0x17u, 0x04u}, + {0x18u, 0x04u}, + {0x1Au, 0x08u}, + {0x1Bu, 0x02u}, + {0x1Eu, 0x07u}, + {0x20u, 0x20u}, + {0x22u, 0x40u}, + {0x26u, 0x20u}, + {0x2Eu, 0x40u}, + {0x30u, 0x10u}, + {0x33u, 0x06u}, + {0x34u, 0x60u}, + {0x35u, 0x01u}, + {0x36u, 0x0Fu}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x04u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x84u, 0x50u}, + {0x85u, 0x09u}, + {0x86u, 0xA0u}, + {0x87u, 0x06u}, + {0x88u, 0x60u}, + {0x89u, 0x03u}, + {0x8Au, 0x90u}, + {0x8Bu, 0x0Cu}, + {0x8Cu, 0x0Fu}, + {0x8Eu, 0xF0u}, + {0x8Fu, 0xFFu}, + {0x91u, 0x0Fu}, + {0x93u, 0xF0u}, + {0x95u, 0x30u}, + {0x97u, 0xC0u}, + {0x9Bu, 0xFFu}, + {0x9Cu, 0x05u}, + {0x9Du, 0x90u}, + {0x9Eu, 0x0Au}, + {0x9Fu, 0x60u}, + {0xA3u, 0xFFu}, + {0xA4u, 0x03u}, + {0xA5u, 0x05u}, + {0xA6u, 0x0Cu}, + {0xA7u, 0x0Au}, + {0xA8u, 0x06u}, + {0xA9u, 0x50u}, + {0xAAu, 0x09u}, + {0xABu, 0xA0u}, + {0xACu, 0x30u}, + {0xAEu, 0xC0u}, + {0xB3u, 0xFFu}, + {0xB6u, 0xFFu}, + {0xBEu, 0x40u}, + {0xBFu, 0x04u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x09u}, + {0x02u, 0x02u}, + {0x06u, 0x24u}, + {0x07u, 0x02u}, + {0x09u, 0x02u}, + {0x0Au, 0x01u}, + {0x0Bu, 0x04u}, + {0x0Eu, 0x01u}, + {0x11u, 0x04u}, + {0x13u, 0x82u}, + {0x14u, 0x04u}, + {0x16u, 0x02u}, + {0x17u, 0x08u}, + {0x18u, 0x40u}, + {0x1Au, 0x05u}, + {0x1Du, 0x80u}, + {0x1Fu, 0x80u}, + {0x20u, 0x08u}, + {0x22u, 0x04u}, + {0x24u, 0x20u}, + {0x2Cu, 0x20u}, + {0x2Fu, 0x88u}, + {0x30u, 0x20u}, + {0x33u, 0x08u}, + {0x36u, 0x64u}, + {0x37u, 0x82u}, + {0x38u, 0x04u}, + {0x39u, 0x40u}, + {0x3Cu, 0x20u}, + {0x3Du, 0x04u}, + {0x3Fu, 0x88u}, + {0x58u, 0x40u}, + {0x5Bu, 0x10u}, + {0x5Cu, 0x80u}, + {0x60u, 0x04u}, + {0x62u, 0x80u}, + {0x64u, 0x02u}, + {0x69u, 0x40u}, + {0x6Bu, 0x02u}, + {0x83u, 0x40u}, + {0x88u, 0x24u}, + {0x8Fu, 0x11u}, + {0xC0u, 0xEDu}, + {0xC2u, 0x8Bu}, + {0xC4u, 0xEDu}, + {0xCAu, 0xE0u}, + {0xCCu, 0xF6u}, + {0xCEu, 0x7Au}, + {0xD6u, 0x1Cu}, + {0xD8u, 0x1Cu}, + {0xE0u, 0x40u}, + {0xE4u, 0xA0u}, + {0xE6u, 0x02u}, + {0x00u, 0x09u}, + {0x02u, 0x06u}, + {0x04u, 0x03u}, + {0x05u, 0x03u}, + {0x06u, 0x0Cu}, + {0x07u, 0x0Cu}, + {0x08u, 0x05u}, + {0x09u, 0x50u}, + {0x0Au, 0x0Au}, + {0x0Bu, 0xA0u}, + {0x0Du, 0x0Fu}, + {0x0Fu, 0xF0u}, + {0x10u, 0x0Fu}, + {0x12u, 0xF0u}, + {0x15u, 0x05u}, + {0x16u, 0xFFu}, + {0x17u, 0x0Au}, + {0x18u, 0xFFu}, + {0x1Bu, 0xFFu}, + {0x1Cu, 0x90u}, + {0x1Du, 0xFFu}, + {0x1Eu, 0x60u}, + {0x20u, 0xFFu}, + {0x21u, 0x60u}, + {0x23u, 0x90u}, + {0x24u, 0x50u}, + {0x26u, 0xA0u}, + {0x27u, 0xFFu}, + {0x28u, 0x30u}, + {0x29u, 0x30u}, + {0x2Au, 0xC0u}, + {0x2Bu, 0xC0u}, + {0x2Du, 0x06u}, + {0x2Fu, 0x09u}, + {0x30u, 0xFFu}, + {0x31u, 0xFFu}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x01u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Fu, 0x01u}, + {0x80u, 0x22u}, + {0x82u, 0x10u}, + {0x83u, 0x9Fu}, + {0x84u, 0x17u}, + {0x85u, 0xC0u}, + {0x86u, 0x28u}, + {0x87u, 0x04u}, + {0x88u, 0x29u}, + {0x89u, 0xC0u}, + {0x8Au, 0x16u}, + {0x8Bu, 0x08u}, + {0x8Cu, 0x16u}, + {0x8Du, 0x80u}, + {0x90u, 0x04u}, + {0x91u, 0x7Fu}, + {0x93u, 0x80u}, + {0x94u, 0x40u}, + {0x97u, 0x60u}, + {0x98u, 0x12u}, + {0x99u, 0x1Fu}, + {0x9Au, 0x04u}, + {0x9Bu, 0x20u}, + {0x9Cu, 0x16u}, + {0x9Du, 0xC0u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x31u}, + {0xA1u, 0xC0u}, + {0xA2u, 0x0Eu}, + {0xA3u, 0x02u}, + {0xA4u, 0x40u}, + {0xA7u, 0xFFu}, + {0xA8u, 0x10u}, + {0xAAu, 0x06u}, + {0xACu, 0x06u}, + {0xADu, 0x90u}, + {0xAEu, 0x10u}, + {0xAFu, 0x40u}, + {0xB0u, 0x30u}, + {0xB2u, 0x40u}, + {0xB4u, 0x0Fu}, + {0xB5u, 0xFFu}, + {0xB8u, 0x28u}, + {0xBAu, 0x02u}, + {0xBFu, 0x10u}, + {0xD4u, 0x40u}, + {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, - {0x00u, 0x08u}, - {0x01u, 0x22u}, - {0x02u, 0x01u}, - {0x03u, 0x40u}, - {0x04u, 0x44u}, - {0x05u, 0x11u}, - {0x08u, 0x18u}, - {0x09u, 0x40u}, - {0x0Au, 0x80u}, - {0x0Eu, 0x28u}, - {0x10u, 0x20u}, - {0x12u, 0xC0u}, - {0x13u, 0x08u}, - {0x16u, 0x04u}, - {0x19u, 0x08u}, - {0x1Cu, 0x40u}, - {0x1Eu, 0x20u}, - {0x1Fu, 0x80u}, - {0x22u, 0x02u}, - {0x24u, 0x04u}, - {0x25u, 0x01u}, - {0x27u, 0x01u}, - {0x28u, 0x10u}, - {0x29u, 0x22u}, - {0x2Au, 0x40u}, - {0x2Du, 0x41u}, + {0x00u, 0x04u}, + {0x02u, 0x48u}, + {0x05u, 0x91u}, + {0x07u, 0x20u}, + {0x08u, 0x50u}, + {0x0Au, 0x20u}, + {0x0Bu, 0x40u}, + {0x0Eu, 0x25u}, + {0x0Fu, 0x80u}, + {0x10u, 0x84u}, + {0x12u, 0x10u}, + {0x15u, 0x50u}, + {0x17u, 0x09u}, + {0x1Bu, 0x02u}, + {0x1Du, 0x15u}, + {0x1Eu, 0x40u}, + {0x1Fu, 0x20u}, + {0x21u, 0x01u}, + {0x27u, 0x08u}, + {0x28u, 0x54u}, + {0x2Au, 0x48u}, + {0x2Bu, 0x05u}, + {0x2Du, 0x40u}, + {0x2Eu, 0x01u}, {0x2Fu, 0x20u}, - {0x30u, 0x20u}, - {0x32u, 0x48u}, - {0x35u, 0x91u}, - {0x36u, 0x04u}, - {0x3Au, 0x11u}, - {0x3Bu, 0x08u}, - {0x3Cu, 0x04u}, - {0x3Du, 0x02u}, - {0x3Eu, 0x10u}, - {0x46u, 0x80u}, - {0x47u, 0x01u}, - {0x48u, 0x04u}, - {0x4Au, 0x08u}, - {0x5Eu, 0x82u}, - {0x5Fu, 0x24u}, - {0x64u, 0x08u}, - {0x66u, 0x82u}, - {0x67u, 0x08u}, - {0x69u, 0x80u}, - {0x6Au, 0x80u}, - {0x82u, 0x80u}, - {0x8Au, 0x02u}, - {0x91u, 0x41u}, - {0x92u, 0x10u}, - {0x93u, 0x05u}, - {0x95u, 0x80u}, - {0x98u, 0x10u}, - {0x99u, 0xB1u}, - {0x9Au, 0x05u}, - {0x9Bu, 0x08u}, - {0x9Cu, 0x08u}, - {0x9Du, 0x08u}, - {0xA0u, 0x04u}, - {0xA2u, 0x45u}, - {0xA3u, 0x20u}, - {0xA6u, 0x02u}, - {0xA8u, 0x04u}, - {0xB2u, 0x10u}, - {0xC0u, 0xFFu}, - {0xC2u, 0x6Fu}, - {0xC4u, 0x4Cu}, + {0x30u, 0x80u}, + {0x32u, 0x5Cu}, + {0x33u, 0x10u}, + {0x35u, 0x84u}, + {0x37u, 0x21u}, + {0x38u, 0x04u}, + {0x3Au, 0x10u}, + {0x3Bu, 0x60u}, + {0x3Du, 0x12u}, + {0x3Eu, 0x54u}, + {0x64u, 0xA0u}, + {0x66u, 0x20u}, + {0x67u, 0x01u}, + {0x84u, 0x80u}, + {0x8Eu, 0x04u}, + {0x90u, 0x04u}, + {0x91u, 0x40u}, + {0x92u, 0x9Du}, + {0x93u, 0x61u}, + {0x95u, 0x02u}, + {0x98u, 0x60u}, + {0x99u, 0x80u}, + {0x9Au, 0x28u}, + {0x9Bu, 0x31u}, + {0x9Du, 0x15u}, + {0xA1u, 0x01u}, + {0xA2u, 0x14u}, + {0xA3u, 0x45u}, + {0xA7u, 0x02u}, + {0xA8u, 0x05u}, + {0xAAu, 0x01u}, + {0xB1u, 0x30u}, + {0xB2u, 0x80u}, + {0xC0u, 0xFEu}, + {0xC2u, 0xFFu}, + {0xC4u, 0xFEu}, {0xCAu, 0xDFu}, {0xCCu, 0xFEu}, - {0xCEu, 0xE7u}, - {0xD6u, 0xF0u}, - {0xD8u, 0x90u}, - {0xE2u, 0x80u}, - {0xE6u, 0x04u}, - {0xE8u, 0x04u}, - {0xEAu, 0x80u}, + {0xCEu, 0xFEu}, + {0xD8u, 0xF0u}, + {0xE2u, 0x40u}, + {0xEAu, 0x04u}, + {0x80u, 0x08u}, + {0x82u, 0x84u}, + {0x87u, 0x80u}, + {0x88u, 0x02u}, + {0x8Au, 0x41u}, + {0x8Bu, 0x07u}, + {0x8Cu, 0x04u}, + {0x8Eu, 0x28u}, + {0x90u, 0x53u}, + {0x91u, 0xAAu}, + {0x92u, 0xACu}, + {0x93u, 0x55u}, + {0x94u, 0x01u}, + {0x95u, 0x99u}, + {0x96u, 0x12u}, + {0x97u, 0x22u}, + {0x9Bu, 0x70u}, + {0xA3u, 0x08u}, + {0xA5u, 0x44u}, + {0xA7u, 0x88u}, + {0xB0u, 0x0Fu}, + {0xB3u, 0x0Fu}, + {0xB4u, 0xC0u}, + {0xB5u, 0xF0u}, + {0xB6u, 0x30u}, + {0xBEu, 0x51u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDCu, 0x10u}, + {0xDFu, 0x01u}, + {0x00u, 0x20u}, + {0x01u, 0x01u}, + {0x02u, 0x01u}, + {0x05u, 0x95u}, + {0x07u, 0x08u}, + {0x08u, 0x20u}, + {0x09u, 0x10u}, + {0x0Bu, 0x50u}, + {0x0Cu, 0x02u}, + {0x0Eu, 0x09u}, + {0x15u, 0x64u}, + {0x17u, 0x21u}, + {0x18u, 0x02u}, + {0x19u, 0x20u}, + {0x1Au, 0x80u}, + {0x1Eu, 0x28u}, + {0x20u, 0x04u}, + {0x21u, 0x20u}, + {0x23u, 0x10u}, + {0x24u, 0x01u}, + {0x25u, 0x10u}, + {0x26u, 0x03u}, + {0x27u, 0x21u}, + {0x2Au, 0x02u}, + {0x2Bu, 0x20u}, + {0x2Eu, 0x85u}, + {0x31u, 0x2Au}, + {0x35u, 0x81u}, + {0x37u, 0x28u}, + {0x39u, 0x08u}, + {0x3Bu, 0x10u}, + {0x3Cu, 0x01u}, + {0x3Du, 0x48u}, + {0x3Eu, 0x10u}, + {0x47u, 0x29u}, + {0x4Cu, 0x04u}, + {0x4Eu, 0x02u}, + {0x4Fu, 0x05u}, + {0x54u, 0x02u}, + {0x55u, 0x05u}, + {0x56u, 0xA0u}, + {0x57u, 0x40u}, + {0x7Au, 0x80u}, + {0x7Bu, 0x40u}, + {0x89u, 0x20u}, + {0x8Eu, 0x40u}, + {0x91u, 0x4Du}, + {0x92u, 0x1Du}, + {0x93u, 0x60u}, + {0x94u, 0x04u}, + {0x95u, 0x32u}, + {0x96u, 0x80u}, + {0x97u, 0x04u}, + {0x98u, 0x40u}, + {0x99u, 0x80u}, + {0x9Au, 0x0Au}, + {0x9Bu, 0x10u}, + {0x9Du, 0x10u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x10u}, + {0xA1u, 0x0Au}, + {0xA3u, 0x25u}, + {0xA4u, 0x02u}, + {0xA6u, 0x01u}, + {0xA7u, 0x02u}, + {0xA9u, 0x02u}, + {0xADu, 0x01u}, + {0xB3u, 0x10u}, + {0xB5u, 0x20u}, + {0xB7u, 0x04u}, + {0xC0u, 0xFBu}, + {0xC2u, 0xDCu}, + {0xC4u, 0xF0u}, + {0xCAu, 0xD3u}, + {0xCCu, 0xF7u}, + {0xCEu, 0xF6u}, + {0xD0u, 0xE0u}, + {0xD2u, 0x30u}, + {0xEAu, 0x08u}, + {0xEEu, 0x06u}, + {0x8Eu, 0x20u}, + {0xA0u, 0x80u}, + {0xA4u, 0x10u}, + {0xA6u, 0x20u}, + {0xA8u, 0x01u}, + {0xAEu, 0x01u}, + {0xB3u, 0x08u}, + {0xB6u, 0x04u}, + {0xB7u, 0x40u}, + {0xE0u, 0x30u}, + {0xE8u, 0x10u}, + {0xEAu, 0x60u}, {0xEEu, 0x02u}, - {0x81u, 0x40u}, - {0x90u, 0x08u}, - {0x91u, 0x40u}, - {0x9Bu, 0x01u}, - {0xA2u, 0x10u}, - {0xAAu, 0x20u}, - {0xEEu, 0x02u}, - {0xB2u, 0x10u}, - {0xB3u, 0x01u}, - {0xB4u, 0x04u}, - {0xEAu, 0x90u}, - {0xEEu, 0x20u}, + {0xA8u, 0x80u}, + {0xB0u, 0x10u}, + {0xECu, 0x80u}, {0x12u, 0x08u}, {0x15u, 0x80u}, - {0x17u, 0x01u}, - {0x33u, 0x01u}, - {0x36u, 0x88u}, - {0x39u, 0x84u}, - {0x3Du, 0x41u}, - {0x40u, 0x08u}, - {0x59u, 0x12u}, - {0x5Fu, 0x02u}, - {0x61u, 0x02u}, + {0x17u, 0x04u}, + {0x33u, 0x04u}, + {0x36u, 0x28u}, + {0x39u, 0x88u}, + {0x3Du, 0x44u}, + {0x43u, 0x80u}, + {0x56u, 0x08u}, + {0x5Au, 0x08u}, + {0x5Cu, 0x08u}, + {0x61u, 0x10u}, {0x65u, 0x04u}, - {0x81u, 0x40u}, - {0x87u, 0x02u}, - {0x8Du, 0x10u}, + {0x81u, 0x80u}, + {0x83u, 0x10u}, + {0x87u, 0x80u}, + {0x89u, 0x80u}, + {0x8Au, 0x04u}, {0xC4u, 0xE0u}, {0xCCu, 0xE0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, - {0xD4u, 0x80u}, + {0xD4u, 0x40u}, {0xD6u, 0xC0u}, {0xD8u, 0xC0u}, - {0xE6u, 0x60u}, - {0x31u, 0x22u}, + {0xE2u, 0x20u}, + {0xE6u, 0x90u}, + {0x30u, 0x20u}, + {0x32u, 0x04u}, + {0x34u, 0x01u}, {0x36u, 0x40u}, - {0x37u, 0x04u}, - {0x54u, 0x02u}, - {0x56u, 0x80u}, - {0x59u, 0x40u}, - {0x63u, 0x80u}, - {0x85u, 0x04u}, - {0x95u, 0x04u}, + {0x51u, 0x80u}, + {0x57u, 0x10u}, + {0x59u, 0x80u}, + {0x62u, 0x08u}, + {0x81u, 0x04u}, + {0x82u, 0x08u}, + {0x84u, 0x08u}, + {0x8Au, 0x08u}, + {0x95u, 0x4Cu}, + {0x99u, 0x80u}, {0x9Cu, 0x08u}, - {0x9Du, 0x02u}, - {0xA6u, 0x80u}, - {0xA9u, 0x04u}, - {0xADu, 0x01u}, - {0xB1u, 0x02u}, + {0x9Du, 0x14u}, + {0x9Eu, 0x08u}, + {0xA1u, 0x80u}, + {0xA3u, 0x10u}, + {0xA6u, 0x20u}, {0xCCu, 0xF0u}, - {0xD4u, 0xC0u}, - {0xD6u, 0x20u}, + {0xD4u, 0xE0u}, {0xD8u, 0x40u}, - {0xE6u, 0x40u}, - {0xEAu, 0x10u}, - {0xEEu, 0x80u}, - {0x12u, 0x80u}, - {0x63u, 0x01u}, - {0x83u, 0x41u}, - {0x8Du, 0x02u}, - {0x9Cu, 0x08u}, - {0x9Du, 0x42u}, - {0x9Fu, 0x04u}, - {0xA5u, 0x22u}, - {0xA6u, 0xC0u}, - {0xA7u, 0x40u}, - {0xA8u, 0x02u}, - {0xAAu, 0x80u}, + {0xE2u, 0x20u}, + {0xE6u, 0x90u}, + {0x12u, 0x20u}, + {0x81u, 0x40u}, + {0x85u, 0x04u}, + {0x95u, 0x4Cu}, + {0x96u, 0x08u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x10u}, + {0xA4u, 0x20u}, + {0xA6u, 0x60u}, {0xC4u, 0x10u}, - {0xD6u, 0x40u}, - {0xE2u, 0xA0u}, - {0xEAu, 0xA0u}, - {0x83u, 0x04u}, - {0x85u, 0x20u}, - {0x89u, 0x42u}, - {0x9Cu, 0x08u}, - {0x9Du, 0x41u}, - {0x9Fu, 0x04u}, - {0xA5u, 0x22u}, + {0xE2u, 0x10u}, + {0xE6u, 0x20u}, + {0x73u, 0x01u}, + {0x84u, 0x20u}, + {0x86u, 0x24u}, + {0x8Fu, 0x01u}, + {0x95u, 0x04u}, + {0x96u, 0x08u}, + {0x9Du, 0x10u}, + {0xA4u, 0x20u}, {0xA6u, 0x40u}, - {0xA9u, 0x01u}, - {0xE2u, 0x90u}, - {0xE8u, 0x20u}, - {0x09u, 0x40u}, - {0x0Fu, 0x20u}, - {0x13u, 0x08u}, - {0x51u, 0x08u}, - {0x53u, 0x02u}, - {0x57u, 0x20u}, - {0x5Cu, 0x40u}, - {0x81u, 0x08u}, + {0xACu, 0x01u}, + {0xDCu, 0x20u}, + {0xE2u, 0x40u}, + {0xE6u, 0x50u}, + {0xEAu, 0x40u}, + {0x09u, 0x80u}, + {0x0Fu, 0x80u}, + {0x10u, 0x10u}, + {0x53u, 0x80u}, + {0x54u, 0x04u}, + {0x59u, 0x20u}, + {0x5Fu, 0x80u}, + {0x84u, 0x10u}, + {0x8Fu, 0x40u}, {0xC2u, 0x06u}, {0xC4u, 0x08u}, {0xD4u, 0x07u}, {0xD6u, 0x04u}, - {0x03u, 0x08u}, - {0x06u, 0x08u}, - {0x07u, 0x80u}, - {0x0Bu, 0x84u}, - {0x0Cu, 0x08u}, - {0x0Du, 0x10u}, - {0x82u, 0x08u}, - {0x84u, 0x08u}, - {0x87u, 0x40u}, - {0x8Bu, 0x04u}, + {0xE6u, 0x02u}, + {0x00u, 0x02u}, + {0x03u, 0x01u}, + {0x04u, 0x42u}, + {0x0Bu, 0x22u}, + {0x0Eu, 0x01u}, + {0x0Fu, 0x20u}, + {0x85u, 0x20u}, + {0x86u, 0x01u}, {0x8Cu, 0x40u}, - {0x8Fu, 0x08u}, - {0x94u, 0x40u}, - {0xA1u, 0x40u}, - {0xA3u, 0x10u}, - {0xA7u, 0x02u}, - {0xABu, 0x08u}, - {0xB3u, 0x20u}, - {0xC0u, 0x07u}, + {0x9Du, 0x20u}, + {0x9Fu, 0x01u}, + {0xA4u, 0x04u}, + {0xAFu, 0x81u}, + {0xB3u, 0x80u}, + {0xB5u, 0x80u}, + {0xC0u, 0x0Fu}, {0xC2u, 0x0Fu}, - {0xE0u, 0x02u}, - {0xE2u, 0x08u}, - {0xE6u, 0x04u}, - {0xE8u, 0x01u}, + {0xE2u, 0x02u}, + {0xEAu, 0x08u}, + {0xECu, 0x04u}, {0x8Fu, 0x10u}, - {0xA1u, 0x40u}, + {0x90u, 0x02u}, {0xA3u, 0x10u}, - {0xABu, 0x82u}, - {0xB1u, 0x10u}, + {0xA4u, 0x04u}, + {0xABu, 0x01u}, + {0xB0u, 0x01u}, + {0xB3u, 0x10u}, {0xE2u, 0x08u}, - {0xEEu, 0x04u}, - {0x09u, 0x40u}, - {0x0Bu, 0x80u}, - {0x0Fu, 0x41u}, - {0x83u, 0x01u}, - {0x87u, 0x40u}, - {0x89u, 0x40u}, - {0xB1u, 0x40u}, + {0xEAu, 0x05u}, + {0x09u, 0x02u}, + {0x0Bu, 0x08u}, + {0x0Eu, 0x04u}, + {0x0Fu, 0x40u}, + {0x80u, 0x01u}, + {0x85u, 0x02u}, + {0x87u, 0x04u}, + {0x90u, 0x02u}, + {0x96u, 0x04u}, + {0xA4u, 0x04u}, + {0xAEu, 0x04u}, {0xC2u, 0x0Fu}, - {0xE6u, 0x04u}, - {0xEEu, 0x04u}, - {0x88u, 0x08u}, - {0x9Cu, 0x08u}, - {0x9Du, 0x01u}, - {0xA3u, 0x20u}, + {0x95u, 0x04u}, + {0x9Du, 0x10u}, + {0xA2u, 0x20u}, {0xAEu, 0x40u}, - {0xB3u, 0x20u}, {0xEEu, 0x40u}, - {0x05u, 0x01u}, - {0x57u, 0x21u}, - {0x9Du, 0x01u}, - {0xA3u, 0x21u}, - {0xAFu, 0x01u}, + {0x07u, 0x40u}, + {0x52u, 0x20u}, + {0x57u, 0x80u}, + {0x85u, 0x04u}, + {0x8Fu, 0x80u}, + {0x95u, 0x04u}, + {0x9Fu, 0x40u}, + {0xA2u, 0x20u}, + {0xA9u, 0x10u}, + {0xABu, 0x40u}, {0xC0u, 0x20u}, - {0xD4u, 0x40u}, - {0xD6u, 0x20u}, - {0xEEu, 0x10u}, + {0xD4u, 0x60u}, + {0xE6u, 0x40u}, + {0xECu, 0x80u}, + {0xEEu, 0x20u}, + {0x88u, 0x04u}, + {0xA4u, 0x04u}, {0xAFu, 0x40u}, - {0x00u, 0x03u}, - {0x08u, 0x03u}, - {0x0Au, 0x03u}, - {0x0Eu, 0x02u}, - {0x10u, 0x01u}, - {0x1Au, 0x01u}, + {0xE0u, 0x04u}, + {0x10u, 0x03u}, + {0x1Au, 0x03u}, {0x00u, 0xFDu}, {0x01u, 0xABu}, {0x02u, 0x02u}, @@ -1587,15 +1829,44 @@ void cyfitter_cfg(void) uint16 size; } CYPACKED_ATTR cfg_memset_t; + + CYPACKED typedef struct { + void CYFAR *dest; + const void CYCODE *src; + uint16 size; + } CYPACKED_ATTR cfg_memcpy_t; + static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT1_DR), 16u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 512u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), 1408u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, - {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, + {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, + }; + + /* UDB_1_1_1_CONFIG Address: CYDEV_UCFG_B1_P3_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_1_1_CONFIG_VAL[] = { + 0x01u, 0x00u, 0x00u, 0x75u, 0x04u, 0x00u, 0x00u, 0x08u, 0x08u, 0x88u, 0x61u, 0x64u, 0x01u, 0x64u, 0x00u, 0x88u, + 0x10u, 0x24u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x70u, 0x00u, 0x07u, 0x40u, 0x10u, 0x01u, 0xECu, 0x00u, 0x00u, + 0xA2u, 0xECu, 0x08u, 0x00u, 0x01u, 0xACu, 0x00u, 0x40u, 0x07u, 0x00u, 0xD8u, 0x00u, 0x01u, 0x40u, 0x00u, 0x02u, + 0x00u, 0x80u, 0x3Fu, 0x71u, 0xE0u, 0x08u, 0x00u, 0x07u, 0x08u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x00u, 0x04u, 0x11u, + 0x34u, 0x02u, 0x50u, 0x00u, 0x06u, 0xDEu, 0xFCu, 0xBDu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, + 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ + static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { + 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x00u, 0x02u, 0x01u}; + + static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { + /* dest, src, size */ + {(void CYFAR *)(CYDEV_UCFG_B1_P3_U0_BASE), BS_UDB_1_1_1_CONFIG_VAL, 128u}, + {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; uint8 CYDATA i; @@ -1607,6 +1878,16 @@ void cyfitter_cfg(void) CYMEMZERO(ms->address, (uint32)(ms->size)); } + /* Copy device configuration data into registers */ + for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) + { + const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; + void * CYDATA destPtr = mc->dest; + const void CYCODE * CYDATA srcPtr = mc->src; + uint16 CYDATA numBytes = mc->size; + CYCONFIGCPYCODE(destPtr, srcPtr, numBytes); + } + cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 9362175..3842dd2 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -71,6 +71,16 @@ .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* SCSI_Parity_Error */ +.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB10_11_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB10_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB10_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB10_ST + /* USBFS_bus_reset */ .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 @@ -84,41 +94,41 @@ /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL /* SCSI_Out_Bits */ .set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 @@ -133,15 +143,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL /* USBFS_arb_int */ .set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -166,24 +176,24 @@ /* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL /* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG @@ -656,8 +666,8 @@ .set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL .set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK .set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -665,17 +675,13 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK -.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB05_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB05_ST .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 @@ -685,28 +691,26 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB05_06_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB05_06_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB05_06_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB05_06_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB05_06_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB05_06_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB05_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB05_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB05_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB05_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB05_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB05_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB05_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB05_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB05_F1 -.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB06_07_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB06_07_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB06_07_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB06_07_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB06_07_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB06_07_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB06_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB06_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB06_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB06_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB06_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB06_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB06_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB06_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB06_F1 /* USBFS_dp_int */ .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -1199,8 +1203,8 @@ /* scsiTarget */ .set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__POS, 0 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 .set scsiTarget_StatusReg__2__MASK, 0x04 @@ -1210,54 +1214,58 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB00_MSK -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB00_ST -.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST -.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK -.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST -.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK -.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL -.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL -.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK -.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0 -.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1 -.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0 -.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1 -.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0 -.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1 -.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1 -.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0 -.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1 -.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1 -.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0 -.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1 -.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1 -.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0 -.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1 -.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK +.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL +.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST +.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST +.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB04_MSK +.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL +.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL +.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB04_ST +.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK +.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB04_CTL +.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL +.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB04_CTL +.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL +.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB04_MSK +.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB04_05_A0 +.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB04_05_A1 +.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB04_05_D0 +.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB04_05_D1 +.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB04_05_F0 +.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB04_05_F1 +.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB04_A0_A1 +.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB04_A0 +.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB04_A1 +.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB04_D0_D1 +.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB04_D0 +.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB04_D1 +.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB04_F0_F1 +.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB04_F0 +.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB04_F1 +.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL /* USBFS_ep_0 */ .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index aefac3b..9ce179e 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -71,6 +71,16 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* SCSI_Parity_Error */ +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST + /* USBFS_bus_reset */ USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 @@ -84,41 +94,41 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL /* SCSI_Out_Bits */ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 @@ -133,15 +143,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL /* USBFS_arb_int */ USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -166,24 +176,24 @@ USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL /* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -656,8 +666,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -665,17 +675,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -685,28 +691,26 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB05_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB05_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB05_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB05_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB05_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB05_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1 /* USBFS_dp_int */ USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1199,8 +1203,8 @@ timer_clock__PM_STBY_MSK EQU 0x04 /* scsiTarget */ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1210,54 +1214,58 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL /* USBFS_ep_0 */ USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 2145cf3..52e34c0 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -71,6 +71,16 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; SCSI_Parity_Error +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST + ; USBFS_bus_reset USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 @@ -84,41 +94,41 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL ; SCSI_Out_Bits SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 @@ -133,15 +143,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL ; USBFS_arb_int USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -166,24 +176,24 @@ USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL ; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -656,8 +666,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -665,17 +675,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -685,28 +691,26 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB05_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB05_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB05_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB05_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB05_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB05_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1 ; USBFS_dp_int USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1199,8 +1203,8 @@ timer_clock__PM_STBY_MSK EQU 0x04 ; scsiTarget scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1210,54 +1214,58 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL ; USBFS_ep_0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c index 65a8d8b..27cf404 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used)) const uint8 cy_meta_loadable[] = { 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x52u, 0x03u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index d49b3af..542b2e7 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -70,6 +70,7 @@ #include #include #include +#include #include #include #include diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml new file mode 100755 index 0000000..94bc6b1 --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml @@ -0,0 +1,253 @@ + + + + + + + + + + + + + + + + + + + + + + SCSI2SD.svd + + + .\Generated_Source\PSoC5\cm3gcc.ld + .\Generated_Source\PSoC5\Cm3RealView.scat + .\Generated_Source\PSoC5\Cm3Iar.icf + + + + + ..\..\src\main.c + ..\..\src\diagnostic.c + ..\..\src\disk.c + ..\..\src\geometry.c + ..\..\src\inquiry.c + ..\..\src\mode.c + ..\..\src\scsi.c + ..\..\src\scsiPhy.c + ..\..\src\bits.c + ..\..\src\sd.c + ..\..\src\config.c + ..\..\src\led.c + ..\..\src\diagnostic.h + ..\..\src\disk.h + ..\..\src\geometry.h + ..\..\src\inquiry.h + ..\..\src\led.h + ..\..\src\mode.h + ..\..\src\scsi.h + ..\..\src\scsiPhy.h + ..\..\src\sense.h + ..\..\src\bits.h + ..\..\src\sd.h + ..\..\src\config.h + + + + + .\device.h + + + + + .\Generated_Source\PSoC5\cyfitter_cfg.h + .\Generated_Source\PSoC5\cyfitter_cfg.c + .\Generated_Source\PSoC5\cydevice.h + .\Generated_Source\PSoC5\cydevicegnu.inc + .\Generated_Source\PSoC5\cydevicerv.inc + .\Generated_Source\PSoC5\cydevice_trm.h + .\Generated_Source\PSoC5\cydevicegnu_trm.inc + .\Generated_Source\PSoC5\cydevicerv_trm.inc + .\Generated_Source\PSoC5\cyfittergnu.inc + .\Generated_Source\PSoC5\cyfitterrv.inc + .\Generated_Source\PSoC5\cyfitter.h + .\Generated_Source\PSoC5\SCSI_In_DBx_aliases.h + .\Generated_Source\PSoC5\SCSI_Out_DBx_aliases.h + .\Generated_Source\PSoC5\SD_MISO_aliases.h + .\Generated_Source\PSoC5\SD_MISO.c + .\Generated_Source\PSoC5\SD_MISO.h + .\Generated_Source\PSoC5\SD_MOSI_aliases.h + .\Generated_Source\PSoC5\SD_MOSI.c + .\Generated_Source\PSoC5\SD_MOSI.h + .\Generated_Source\PSoC5\SD_SCK_aliases.h + .\Generated_Source\PSoC5\SD_SCK.c + .\Generated_Source\PSoC5\SD_SCK.h + .\Generated_Source\PSoC5\SD_CS_aliases.h + .\Generated_Source\PSoC5\SD_CS.c + .\Generated_Source\PSoC5\SD_CS.h + .\Generated_Source\PSoC5\SD_DAT1_aliases.h + .\Generated_Source\PSoC5\SD_DAT1.c + .\Generated_Source\PSoC5\SD_DAT1.h + .\Generated_Source\PSoC5\SD_DAT2_aliases.h + .\Generated_Source\PSoC5\SD_DAT2.c + .\Generated_Source\PSoC5\SD_DAT2.h + .\Generated_Source\PSoC5\SD_CD_aliases.h + .\Generated_Source\PSoC5\SD_CD.c + .\Generated_Source\PSoC5\SD_CD.h + .\Generated_Source\PSoC5\SCSI_In_aliases.h + .\Generated_Source\PSoC5\SCSI_Out_aliases.h + .\Generated_Source\PSoC5\LED1_aliases.h + .\Generated_Source\PSoC5\LED1.c + .\Generated_Source\PSoC5\LED1.h + .\Generated_Source\PSoC5\Cm3Start.c + .\Generated_Source\PSoC5\core_cm3_psoc5.h + .\Generated_Source\PSoC5\core_cm3.h + .\Generated_Source\PSoC5\CyBootAsmGnu.s + .\Generated_Source\PSoC5\CyBootAsmRv.s + .\Generated_Source\PSoC5\CyDmac.c + .\Generated_Source\PSoC5\CyDmac.h + .\Generated_Source\PSoC5\CyFlash.c + .\Generated_Source\PSoC5\CyFlash.h + .\Generated_Source\PSoC5\CyLib.c + .\Generated_Source\PSoC5\CyLib.h + .\Generated_Source\PSoC5\cypins.h + .\Generated_Source\PSoC5\cyPm.c + .\Generated_Source\PSoC5\cyPm.h + .\Generated_Source\PSoC5\CySpc.c + .\Generated_Source\PSoC5\CySpc.h + .\Generated_Source\PSoC5\cytypes.h + .\Generated_Source\PSoC5\cyutils.c + .\Generated_Source\PSoC5\core_cmFunc.h + .\Generated_Source\PSoC5\core_cmInstr.h + .\Generated_Source\PSoC5\CyBootAsmIar.s + .\Generated_Source\PSoC5\project.h + .\Generated_Source\PSoC5\SD_Data_Clk.c + .\Generated_Source\PSoC5\SD_Data_Clk.h + .\Generated_Source\PSoC5\SDCard.c + .\Generated_Source\PSoC5\SDCard.h + .\Generated_Source\PSoC5\SDCard_PM.c + .\Generated_Source\PSoC5\SDCard_INT.c + .\Generated_Source\PSoC5\SDCard_PVT.h + .\Generated_Source\PSoC5\SCSI_RST_aliases.h + .\Generated_Source\PSoC5\SCSI_RST.c + .\Generated_Source\PSoC5\SCSI_RST.h + .\Generated_Source\PSoC5\SCSI_ATN_aliases.h + .\Generated_Source\PSoC5\SCSI_ATN.c + .\Generated_Source\PSoC5\SCSI_ATN.h + .\Generated_Source\PSoC5\SCSI_RST_ISR.c + .\Generated_Source\PSoC5\SCSI_RST_ISR.h + .\Generated_Source\PSoC5\cymetadata.c + .\Generated_Source\PSoC5\cydeviceiar.inc + .\Generated_Source\PSoC5\cydeviceiar_trm.inc + .\Generated_Source\PSoC5\cyfitteriar.inc + .\Generated_Source\PSoC5\cydisabledsheets.h + .\Generated_Source\PSoC5\CFG_EEPROM.c + .\Generated_Source\PSoC5\CFG_EEPROM.h + .\Generated_Source\PSoC5\cybootloader.c + .\Generated_Source\PSoC5\Bootloadable_1.c + .\Generated_Source\PSoC5\Bootloadable_1.h + .\Generated_Source\PSoC5\USBFS.c + .\Generated_Source\PSoC5\USBFS.h + .\Generated_Source\PSoC5\USBFS_audio.c + .\Generated_Source\PSoC5\USBFS_audio.h + .\Generated_Source\PSoC5\USBFS_boot.c + .\Generated_Source\PSoC5\USBFS_cdc.c + .\Generated_Source\PSoC5\USBFS_cdc.h + .\Generated_Source\PSoC5\USBFS_cls.c + .\Generated_Source\PSoC5\USBFS_descr.c + .\Generated_Source\PSoC5\USBFS_drv.c + .\Generated_Source\PSoC5\USBFS_episr.c + .\Generated_Source\PSoC5\USBFS_hid.c + .\Generated_Source\PSoC5\USBFS_hid.h + .\Generated_Source\PSoC5\USBFS_pm.c + .\Generated_Source\PSoC5\USBFS_std.c + .\Generated_Source\PSoC5\USBFS_vnd.c + .\Generated_Source\PSoC5\USBFS_midi.c + .\Generated_Source\PSoC5\USBFS_midi.h + .\Generated_Source\PSoC5\USBFS_pvt.h + .\Generated_Source\PSoC5\USBFS_Dm_aliases.h + .\Generated_Source\PSoC5\USBFS_Dm.c + .\Generated_Source\PSoC5\USBFS_Dm.h + .\Generated_Source\PSoC5\USBFS_Dp_aliases.h + .\Generated_Source\PSoC5\USBFS_Dp.c + .\Generated_Source\PSoC5\USBFS_Dp.h + .\Generated_Source\PSoC5\SCSI_CTL_PHASE.c + .\Generated_Source\PSoC5\SCSI_CTL_PHASE.h + .\Generated_Source\PSoC5\SCSI_CLK.c + .\Generated_Source\PSoC5\SCSI_CLK.h + .\Generated_Source\PSoC5\SCSI_Out_Bits.c + .\Generated_Source\PSoC5\SCSI_Out_Bits.h + .\Generated_Source\PSoC5\SCSI_Out_Ctl.c + .\Generated_Source\PSoC5\SCSI_Out_Ctl.h + .\Generated_Source\PSoC5\Debug_Timer.c + .\Generated_Source\PSoC5\Debug_Timer.h + .\Generated_Source\PSoC5\Debug_Timer_PM.c + .\Generated_Source\PSoC5\timer_clock.c + .\Generated_Source\PSoC5\timer_clock.h + .\Generated_Source\PSoC5\Debug_Timer_Interrupt.c + .\Generated_Source\PSoC5\Debug_Timer_Interrupt.h + .\Generated_Source\PSoC5\SCSI_TX_DMA_dma.c + .\Generated_Source\PSoC5\SCSI_TX_DMA_dma.h + .\Generated_Source\PSoC5\SCSI_TX_DMA_COMPLETE.c + .\Generated_Source\PSoC5\SCSI_TX_DMA_COMPLETE.h + .\Generated_Source\PSoC5\SD_RX_DMA_dma.c + .\Generated_Source\PSoC5\SD_RX_DMA_dma.h + .\Generated_Source\PSoC5\SD_TX_DMA_dma.c + .\Generated_Source\PSoC5\SD_TX_DMA_dma.h + .\Generated_Source\PSoC5\SD_RX_DMA_COMPLETE.c + .\Generated_Source\PSoC5\SD_RX_DMA_COMPLETE.h + .\Generated_Source\PSoC5\SD_TX_DMA_COMPLETE.c + .\Generated_Source\PSoC5\SD_TX_DMA_COMPLETE.h + .\Generated_Source\PSoC5\SCSI_RX_DMA_dma.c + .\Generated_Source\PSoC5\SCSI_RX_DMA_dma.h + .\Generated_Source\PSoC5\SCSI_RX_DMA_COMPLETE.c + .\Generated_Source\PSoC5\SCSI_RX_DMA_COMPLETE.h + .\Generated_Source\PSoC5\SCSI_Parity_Error.c + .\Generated_Source\PSoC5\SCSI_Parity_Error.h + .\Generated_Source\PSoC5\prebuild.bat + .\Generated_Source\PSoC5\postbuild.bat + .\Generated_Source\PSoC5\CyElfTool.exe + .\Generated_Source\PSoC5\libelf.dll + + + + + .\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a + + + + + .\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a + + + + + .\Generated_Source\PSoC5\IAR\CyComponentLibrary.a + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx index e13d32d..e399342 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,12 +1,11 @@ - + - + - @@ -64,7 +63,8 @@ - + + @@ -73,7 +73,6 @@ - @@ -154,36 +153,67 @@ - + + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - + - - + + - - + + - - + + - + + \ No newline at end of file diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit index 81519e1..515157a 100644 Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj index c7311f6..b8c108c 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -2943,6 +2943,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd index 55e6e85..d2edff0 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd @@ -9,7 +9,7 @@ SCSI_Out_Ctl No description available - 0x40006577 + 0x4000647E 0 0x1 @@ -30,7 +30,7 @@ SCSI_Out_Bits No description available - 0x4000647C + 0x4000647B 0 0x1 @@ -824,10 +824,165 @@ + + SCSI_Parity_Error + No description available + 0x4000646A + + 0 + 0x31 + registers + + + + SCSI_Parity_Error_STATUS_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + SCSI_Parity_Error_MASK_REG + No description available + 0x20 + 8 + read-write + 0 + 0 + + + SCSI_Parity_Error_STATUS_AUX_CTL_REG + No description available + 0x30 + 8 + read-write + 0 + 0 + + + FIFO0 + FIFO0 clear + 5 + 5 + read-write + + + ENABLED + Enable counter + 1 + + + DISABLED + Disable counter + 0 + + + + + INTRENBL + Enables or disables the Interrupt + 4 + 4 + read-write + + + ENABLED + Interrupt enabled + 1 + + + DISABLED + Interrupt disabled + 0 + + + + + FIFO1LEVEL + FIFO level + 3 + 3 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO0LEVEL + FIFO level + 2 + 2 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO1CLEAR + FIFO clear + 1 + 1 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + FIFO0CLEAR + FIFO clear + 0 + 0 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + + + SCSI_CTL_PHASE No description available - 0x40006475 + 0x40006471 0 0x1 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index f676ffa..70724a2 100755 Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.cysym b/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.cysym index 1eeb6a0..a0321ce 100755 Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.cysym and b/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.cysym differ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v b/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v index 5d46c5a..0298351 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v @@ -25,11 +25,13 @@ module scsiTarget ( output REQ, // Active High, connected to SCSI bus via inverter input nACK, // Active LOW, connected directly to SCSI bus. input [7:0] nDBx_in, // Active LOW, connected directly to SCSI bus. + input nDBP, // Active LOW, connected directly to SCSI bus input IO, // Active High, set by CPU via status register. input nRST, // Active LOW, connected directly to SCSI bus. input clk, output tx_intr, - output rx_intr + output rx_intr, + output parityErr ); @@ -55,6 +57,28 @@ cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync localparam IO_WRITE = 1'b1; localparam IO_READ = 1'b0; + +///////////////////////////////////////////////////////////////////////////// +// Input filter +///////////////////////////////////////////////////////////////////////////// +// Do not respond to glitches in the ACK signal. This will cause us to +// transfer rubbish data, or too many bytes, and generally leads to +// hanging the SCSI bus. Reflected signals can cause the ACK signal +// to be dirty. We don't care so much about the others as we don't +// respond to them on the rising edge. +// 4-stage shifter. Ass +reg safeACK; +reg[3:0] ackShift; +always @(posedge op_clk) begin + if (ackShift[3:1] == 0) begin + safeACK <= 0; + end + else if (ackShift[3:1] == 1) begin + safeACK <= 1; + end + ackShift <= {ackShift[2:0], ~nACK}; +end + ///////////////////////////////////////////////////////////////////////////// // STATE MACHINE ///////////////////////////////////////////////////////////////////////////// @@ -125,14 +149,22 @@ wire[7:0] pi; // Parallel output from the selected SRCA value (A0 or A1) to the ALU. wire[7:0] po; -// Set true to trigger storing A1 into F1. -wire fifoStore; +// Set true to trigger storing A1 into F1. Set while in STATE_RX +reg fifoStore; + +// Set to true on detecting a parity input while reading +reg parityErrReg; +// Temp values in parity calcs. We need to do it in 2 steps to avoid +// timing issues and running-out-of resources +reg[2:0] genParity; + +reg REQReg; // Set Output Pins -assign REQ = state[1] & state[2]; // STATE_READY & STATE_RX +assign REQ = REQReg; // STATE_READY & STATE_RX assign DBx_out[7:0] = data; assign pi[7:0] = ~nDBx_in[7:0]; // Invert active low scsi bus -assign fifoStore = (state == STATE_RX) ? 1'b1 : 1'b0; +assign parityErr = parityErrReg; ///////////////////////////////////////////////////////////////////////////// @@ -152,7 +184,7 @@ wire f0_bus_stat; // Tx FIFO not full wire f0_blk_stat; // Tx FIFO empty wire f1_bus_stat; // Rx FIFO not empty wire f1_blk_stat; // Rx FIFO full -wire txComplete = f0_blk_stat && (state == STATE_IDLE); +wire txComplete = f0_blk_stat && (state == STATE_IDLE) && ~safeACK; cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg ( /* input */ .clock(op_clk), @@ -174,18 +206,27 @@ always @(posedge op_clk) begin // and output FIFO is not full. // Note that output FIFO is unused in TX mode. if (!nRST) state <= STATE_IDLE; - else if (nACK & !f0_blk_stat) + else if (~safeACK & !f0_blk_stat && ((IO == IO_WRITE) || !f1_blk_stat)) state <= STATE_FIFOLOAD; else state <= STATE_IDLE; // Clear our output pins data <= 8'b0; + + REQReg <= 1'b0; + fifoStore <= 1'b0; + parityErrReg <= 1'b0; end STATE_FIFOLOAD: if (!nRST) state <= STATE_IDLE; - else state <= IO == IO_WRITE ? STATE_TX : STATE_READY; + else if (IO == IO_WRITE) + state <= STATE_TX; + else begin + state <= STATE_READY; + REQReg <= 1'b1; + end STATE_TX: begin @@ -200,21 +241,33 @@ always @(posedge op_clk) begin STATE_DESKEW: if (!nRST) state <= STATE_IDLE; - else if(deskewComplete) state <= STATE_READY; - else state <= STATE_DESKEW; + else if(deskewComplete) begin + state <= STATE_READY; + REQReg <= 1'b1; + end else state <= STATE_DESKEW; STATE_READY: if (!nRST) state <= STATE_IDLE; - else if (~nACK && ((IO == IO_WRITE) || !f1_blk_stat)) state <= STATE_RX; - else state <= STATE_READY; + else if (safeACK) begin + state <= STATE_RX; + fifoStore <= 1'b1; - STATE_RX: // same code here as for the IDLE state, as we make - // a quick run back to the next byte if possible. - if (!nRST) state <= STATE_IDLE; - else if (nACK & !f0_blk_stat) - state <= STATE_FIFOLOAD; - else - state <= STATE_IDLE; + genParity[0] <= (~nDBP) ^ 1'b1 ^ ~nDBx_in[7] ^ ~nDBx_in[6]; + genParity[1] <= ~nDBx_in[5] ^ ~nDBx_in[4] ^ ~nDBx_in[3]; + genParity[2] <= ~nDBx_in[2] ^ ~nDBx_in[1] ^ ~nDBx_in[0]; + end else state <= STATE_READY; + + STATE_RX: + begin + state <= STATE_IDLE; + REQReg <= 1'b0; + fifoStore <= 1'b0; + parityErrReg <= 1'b0; + data <= 8'b0; + if (IO == IO_READ) begin + parityErrReg <= ^genParity[2:0]; + end + end default: state <= STATE_IDLE; endcase diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml index 2530471..7f621fb 100755 --- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml +++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml @@ -18,7 +18,7 @@ - + USB_Bootloader.svd @@ -27,13 +27,13 @@ .\Generated_Source\PSoC5\Cm3Iar.icf - - + + .\main.c - - + + .\Generated_Source\PSoC5\cyfitter_cfg.h .\Generated_Source\PSoC5\cyfitter_cfg.c .\Generated_Source\PSoC5\cymetadata.c @@ -111,41 +111,41 @@ .\Generated_Source\PSoC5\libelf.dll - - + + .\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a - - + + .\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a - - + + .\Generated_Source\PSoC5\IAR\CyComponentLibrary.a - + - + - + - + - + - + - + diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyfit b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyfit index d405b9e..e16d539 100644 Binary files a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyfit and b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyfit differ diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 index 718dd0a..7fd05ff 100755 --- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 +++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 @@ -1081,6 +1081,7 @@ + @@ -1114,7 +1115,7 @@ - + @@ -1667,14 +1668,14 @@ C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif - + - + diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.rpt b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.rpt index 0408db3..d51d329 100644 --- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.rpt +++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.rpt @@ -1,13 +1,13 @@ -Loading plugins phase: Elapsed time ==> 0s.484ms -Initializing data phase: Elapsed time ==> 4s.047ms +Loading plugins phase: Elapsed time ==> 0s.529ms +Initializing data phase: Elapsed time ==> 4s.249ms -cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE +cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -Elaboration phase: Elapsed time ==> 7s.623ms +Elaboration phase: Elapsed time ==> 8s.312ms -HDL generation phase: Elapsed time ==> 0s.655ms +HDL generation phase: Elapsed time ==> 1s.015ms | | | | | | | @@ -25,23 +25,23 @@ HDL generation phase: Elapsed time ==> 0s.655ms ====================================================================== Compiling: USB_Bootloader.v Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog ====================================================================== ====================================================================== Compiling: USB_Bootloader.v Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog ====================================================================== ====================================================================== Compiling: USB_Bootloader.v Program : vlogfe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== vlogfe V6.3 IR 41: Verilog parser -Sun Jul 20 15:00:50 2014 +Thu Aug 28 22:24:58 2014 ====================================================================== @@ -51,7 +51,7 @@ Options : -yv2 -q10 USB_Bootloader.v ====================================================================== vpp V6.3 IR 41: Verilog Pre-Processor -Sun Jul 20 15:00:50 2014 +Thu Aug 28 22:24:59 2014 vpp: No errors. @@ -76,11 +76,11 @@ vlogfe: No errors. ====================================================================== Compiling: USB_Bootloader.v Program : tovif -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== tovif V6.3 IR 41: High-level synthesis -Sun Jul 20 15:00:51 2014 +Thu Aug 28 22:25:00 2014 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -91,8 +91,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\c Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. -Linking 'Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. +Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. +Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. tovif: No errors. @@ -100,11 +100,11 @@ tovif: No errors. ====================================================================== Compiling: USB_Bootloader.v Program : topld -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== topld V6.3 IR 41: Synthesis and optimization -Sun Jul 20 15:00:52 2014 +Thu Aug 28 22:25:02 2014 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -115,8 +115,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\c Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. -Linking 'Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. +Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. +Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. ---------------------------------------------------------- @@ -202,16 +202,16 @@ topld: No errors. CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog -Warp synthesis phase: Elapsed time ==> 8s.781ms +Warp synthesis phase: Elapsed time ==> 10s.236ms -cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Sunday, 20 July 2014 15:00:57 -Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog +cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Thursday, 28 August 2014 22:25:08 +Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog -Design parsing phase: Elapsed time ==> 0s.031ms +Design parsing phase: Elapsed time ==> 0s.344ms @@ -1315,7 +1315,7 @@ LPF Fixed Blocks : 0 : 2 : 2 : 0.00% SAR Fixed Blocks : 0 : 1 : 1 : 0.00% Technology Mapping: Elapsed time ==> 0s.406ms -Tech mapping phase: Elapsed time ==> 0s.687ms +Tech mapping phase: Elapsed time ==> 0s.702ms Initial Analog Placement Results: @@ -1345,7 +1345,7 @@ IO_5@[IOP=(3)][IoId=(5)] : SD_PULLUP(4) (fixed) IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed) IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed) USB[0]@[FFB(USB,0)] : \USBFS:USB\ -Analog Placement phase: Elapsed time ==> 0s.094ms +Analog Placement phase: Elapsed time ==> 0s.109ms Analog Routing phase: Elapsed time ==> 0s.000ms @@ -1363,12 +1363,12 @@ Dump of CyP35AnalogRoutingResultsDB IsVddaHalfUsedForComp = False IsVddaHalfUsedForSar0 = False IsVddaHalfUsedForSar1 = False -Analog Code Generation phase: Elapsed time ==> 1s.405ms +Analog Code Generation phase: Elapsed time ==> 1s.453ms I2659: No Constrained paths were found. The placer will run in non-timing driven mode. -I2076: Total run-time: 5.3 sec. +I2076: Total run-time: 4.1 sec. @@ -1382,10 +1382,10 @@ PLD Packing: Elapsed time ==> 0s.000ms Initial Partitioning Summary not displayed at this verbose level. Final Partitioning Summary not displayed at this verbose level. -Partitioning: Elapsed time ==> 0s.079ms +Partitioning: Elapsed time ==> 0s.063ms -Annealing: Elapsed time ==> 0s.000ms +Annealing: Elapsed time ==> 0s.014ms The seed used for moves was 114161200. Inital cost was 120, final cost is 120 (0.00% improvement). @@ -2664,32 +2664,32 @@ Port | Pin | Fixed | Type | Drive Mode | Name | Connection -Digital component placer commit/Report: Elapsed time ==> 0s.373ms -Digital Placement phase: Elapsed time ==> 9s.093ms +Digital component placer commit/Report: Elapsed time ==> 0s.359ms +Digital Placement phase: Elapsed time ==> 7s.578ms Routing successful. -Digital Routing phase: Elapsed time ==> 8s.703ms +Digital Routing phase: Elapsed time ==> 9s.796ms -Bitstream and API generation phase: Elapsed time ==> 25s.515ms +Bitstream and API generation phase: Elapsed time ==> 25s.390ms -Bitstream verification phase: Elapsed time ==> 0s.125ms +Bitstream verification phase: Elapsed time ==> 0s.158ms Timing report is in USB_Bootloader_timing.html. -Static timing analysis phase: Elapsed time ==> 3s.999ms +Static timing analysis phase: Elapsed time ==> 4s.278ms Data reporting phase: Elapsed time ==> 0s.000ms -Design database save phase: Elapsed time ==> 0s.734ms +Design database save phase: Elapsed time ==> 0s.656ms -cydsfit: Elapsed time ==> 50s.735ms +cydsfit: Elapsed time ==> 50s.921ms -Fitter phase: Elapsed time ==> 50s.829ms -API generation phase: Elapsed time ==> 23s.686ms +Fitter phase: Elapsed time ==> 50s.997ms +API generation phase: Elapsed time ==> 24s.640ms Dependency generation phase: Elapsed time ==> 0s.859ms -Cleanup phase: Elapsed time ==> 0s.609ms +Cleanup phase: Elapsed time ==> 0s.844ms diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader_timing.html b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader_timing.html index 8b6a5f5..d079f1a 100644 --- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader_timing.html +++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader_timing.html @@ -539,7 +539,7 @@ function getElementsByClass(rootNode, elemName, className) Project : USB_Bootloader Build Time : - 07/20/14 15:01:46 + 08/28/14 22:25:58 Device : CY8C5267AXI-LP051 Temperature : diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c new file mode 100644 index 0000000..16a0241 --- /dev/null +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c @@ -0,0 +1,521 @@ +/******************************************************************************* +* File Name: SCSI_CLK.c +* Version 2.10 +* +* Description: +* This file provides the source code to the API for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "SCSI_CLK.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SCSI_CLK_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_Start(void) +{ + /* Set the bit to enable the clock. */ + SCSI_CLK_CLKEN |= SCSI_CLK_CLKEN_MASK; + SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_Stop(void) +{ + /* Clear the bit to disable the clock. */ + SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK); + SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SCSI_CLK_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_StopBlock(void) +{ + if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(SCSI_CLK__CFG3) + CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SCSI_CLK__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(SCSI_CLK_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK); + SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(SCSI_CLK_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: SCSI_CLK_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_StandbyPower(uint8 state) +{ + if(state == 0u) + { + SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK); + } + else + { + SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = SCSI_CLK_GetSourceRegister(); + uint16 oldDivider = SCSI_CLK_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider); + SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + SCSI_CLK_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(SCSI_CLK__CFG3) + CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SCSI_CLK__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((SCSI_CLK_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider); + SCSI_CLK_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 SCSI_CLK_GetDividerRegister(void) +{ + return CY_GET_REG16(SCSI_CLK_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_SetModeRegister(uint8 modeBitMask) +{ + SCSI_CLK_MOD_SRC |= modeBitMask & (uint8)SCSI_CLK_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) +{ + SCSI_CLK_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SCSI_CLK_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 SCSI_CLK_GetModeRegister(void) +{ + return SCSI_CLK_MOD_SRC & (uint8)(SCSI_CLK_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = SCSI_CLK_GetDividerRegister(); + uint8 oldSrc = SCSI_CLK_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + SCSI_CLK_MOD_SRC |= CYCLK_SSS; + SCSI_CLK_MOD_SRC = + (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + SCSI_CLK_MOD_SRC = + (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource; + SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + SCSI_CLK_MOD_SRC = + (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 SCSI_CLK_GetSourceRegister(void) +{ + return SCSI_CLK_MOD_SRC & SCSI_CLK_SRC_SEL_MSK; +} + + +#if defined(SCSI_CLK__CFG3) + + +/******************************************************************************* +* Function Name: SCSI_CLK_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) +{ + SCSI_CLK_PHASE = clkPhase & SCSI_CLK_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 SCSI_CLK_GetPhaseRegister(void) +{ + return SCSI_CLK_PHASE & SCSI_CLK_PHASE_MASK; +} + +#endif /* SCSI_CLK__CFG3 */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h new file mode 100644 index 0000000..5c91503 --- /dev/null +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* File Name: SCSI_CLK.h +* Version 2.10 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_SCSI_CLK_H) +#define CY_CLOCK_SCSI_CLK_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_10 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_CLK_Start(void) ; +void SCSI_CLK_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void SCSI_CLK_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void SCSI_CLK_StandbyPower(uint8 state) ; +void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 SCSI_CLK_GetDividerRegister(void) ; +void SCSI_CLK_SetModeRegister(uint8 modeBitMask) ; +void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) ; +uint8 SCSI_CLK_GetModeRegister(void) ; +void SCSI_CLK_SetSourceRegister(uint8 clkSource) ; +uint8 SCSI_CLK_GetSourceRegister(void) ; +#if defined(SCSI_CLK__CFG3) +void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) ; +uint8 SCSI_CLK_GetPhaseRegister(void) ; +#endif /* defined(SCSI_CLK__CFG3) */ + +#define SCSI_CLK_Enable() SCSI_CLK_Start() +#define SCSI_CLK_Disable() SCSI_CLK_Stop() +#define SCSI_CLK_SetDivider(clkDivider) SCSI_CLK_SetDividerRegister(clkDivider, 1u) +#define SCSI_CLK_SetDividerValue(clkDivider) SCSI_CLK_SetDividerRegister((clkDivider) - 1u, 1u) +#define SCSI_CLK_SetMode(clkMode) SCSI_CLK_SetModeRegister(clkMode) +#define SCSI_CLK_SetSource(clkSource) SCSI_CLK_SetSourceRegister(clkSource) +#if defined(SCSI_CLK__CFG3) +#define SCSI_CLK_SetPhase(clkPhase) SCSI_CLK_SetPhaseRegister(clkPhase) +#define SCSI_CLK_SetPhaseValue(clkPhase) SCSI_CLK_SetPhaseRegister((clkPhase) + 1u) +#endif /* defined(SCSI_CLK__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define SCSI_CLK_CLKEN (* (reg8 *) SCSI_CLK__PM_ACT_CFG) +#define SCSI_CLK_CLKEN_PTR ((reg8 *) SCSI_CLK__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define SCSI_CLK_CLKSTBY (* (reg8 *) SCSI_CLK__PM_STBY_CFG) +#define SCSI_CLK_CLKSTBY_PTR ((reg8 *) SCSI_CLK__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define SCSI_CLK_DIV_LSB (* (reg8 *) SCSI_CLK__CFG0) +#define SCSI_CLK_DIV_LSB_PTR ((reg8 *) SCSI_CLK__CFG0) +#define SCSI_CLK_DIV_PTR ((reg16 *) SCSI_CLK__CFG0) + +/* Clock MSB divider configuration register. */ +#define SCSI_CLK_DIV_MSB (* (reg8 *) SCSI_CLK__CFG1) +#define SCSI_CLK_DIV_MSB_PTR ((reg8 *) SCSI_CLK__CFG1) + +/* Mode and source configuration register */ +#define SCSI_CLK_MOD_SRC (* (reg8 *) SCSI_CLK__CFG2) +#define SCSI_CLK_MOD_SRC_PTR ((reg8 *) SCSI_CLK__CFG2) + +#if defined(SCSI_CLK__CFG3) +/* Analog clock phase configuration register */ +#define SCSI_CLK_PHASE (* (reg8 *) SCSI_CLK__CFG3) +#define SCSI_CLK_PHASE_PTR ((reg8 *) SCSI_CLK__CFG3) +#endif /* defined(SCSI_CLK__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define SCSI_CLK_CLKEN_MASK SCSI_CLK__PM_ACT_MSK +#define SCSI_CLK_CLKSTBY_MASK SCSI_CLK__PM_STBY_MSK + +/* CFG2 field masks */ +#define SCSI_CLK_SRC_SEL_MSK SCSI_CLK__CFG2_SRC_SEL_MASK +#define SCSI_CLK_MODE_MASK (~(SCSI_CLK_SRC_SEL_MSK)) + +#if defined(SCSI_CLK__CFG3) +/* CFG3 phase mask */ +#define SCSI_CLK_PHASE_MASK SCSI_CLK__CFG3_PHASE_DLY_MASK +#endif /* defined(SCSI_CLK__CFG3) */ + +#endif /* CY_CLOCK_SCSI_CLK_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c new file mode 100644 index 0000000..8d35a48 --- /dev/null +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c @@ -0,0 +1,134 @@ +/******************************************************************************* +* File Name: SCSI_Parity_Error.c +* Version 1.80 +* +* Description: +* This file contains API to enable firmware to read the value of a Status +* Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Parity_Error.h" + +#if !defined(SCSI_Parity_Error_sts_sts_reg__REMOVED) /* Check for removal by optimization */ + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Status Register. +* +* Parameters: +* None. +* +* Return: +* The current value in the Status Register. +* +*******************************************************************************/ +uint8 SCSI_Parity_Error_Read(void) +{ + return SCSI_Parity_Error_Status; +} + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_InterruptEnable +******************************************************************************** +* +* Summary: +* Enables the Status Register interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Parity_Error_InterruptEnable(void) +{ + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + SCSI_Parity_Error_Status_Aux_Ctrl |= SCSI_Parity_Error_STATUS_INTR_ENBL; + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_InterruptDisable +******************************************************************************** +* +* Summary: +* Disables the Status Register interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Parity_Error_InterruptDisable(void) +{ + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + SCSI_Parity_Error_Status_Aux_Ctrl &= (uint8)(~SCSI_Parity_Error_STATUS_INTR_ENBL); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_WriteMask +******************************************************************************** +* +* Summary: +* Writes the current mask value assigned to the Status Register. +* +* Parameters: +* mask: Value to write into the mask register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Parity_Error_WriteMask(uint8 mask) +{ + #if(SCSI_Parity_Error_INPUTS < 8u) + mask &= (uint8)((((uint8)1u) << SCSI_Parity_Error_INPUTS) - 1u); + #endif /* End SCSI_Parity_Error_INPUTS < 8u */ + SCSI_Parity_Error_Status_Mask = mask; +} + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_ReadMask +******************************************************************************** +* +* Summary: +* Reads the current interrupt mask assigned to the Status Register. +* +* Parameters: +* None. +* +* Return: +* The value of the interrupt mask of the Status Register. +* +*******************************************************************************/ +uint8 SCSI_Parity_Error_ReadMask(void) +{ + return SCSI_Parity_Error_Status_Mask; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h new file mode 100644 index 0000000..d03aed7 --- /dev/null +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h @@ -0,0 +1,63 @@ +/******************************************************************************* +* File Name: SCSI_Parity_Error.h +* Version 1.80 +* +* Description: +* This file containts Status Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */ +#define CY_STATUS_REG_SCSI_Parity_Error_H + +#include "cytypes.h" +#include "CyLib.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +uint8 SCSI_Parity_Error_Read(void) ; +void SCSI_Parity_Error_InterruptEnable(void) ; +void SCSI_Parity_Error_InterruptDisable(void) ; +void SCSI_Parity_Error_WriteMask(uint8 mask) ; +uint8 SCSI_Parity_Error_ReadMask(void) ; + + +/*************************************** +* API Constants +***************************************/ + +#define SCSI_Parity_Error_STATUS_INTR_ENBL 0x10u + + +/*************************************** +* Parameter Constants +***************************************/ + +/* Status Register Inputs */ +#define SCSI_Parity_Error_INPUTS 1 + + +/*************************************** +* Registers +***************************************/ + +/* Status Register */ +#define SCSI_Parity_Error_Status (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG ) +#define SCSI_Parity_Error_Status_PTR ( (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG ) +#define SCSI_Parity_Error_Status_Mask (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__MASK_REG ) +#define SCSI_Parity_Error_Status_Aux_Ctrl (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG ) + +#endif /* End CY_STATUS_REG_SCSI_Parity_Error_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c index b4ea4da..1faf25b 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c @@ -1056,7 +1056,7 @@ const uint8 cy_bootloader[] = { 0x10u, 0xBDu, 0x82u, 0x18u, 0x03u, 0x46u, 0x93u, 0x42u, 0x02u, 0xD0u, 0x03u, 0xF8u, 0x01u, 0x1Bu, 0xFAu, 0xE7u, 0x70u, 0x47u, 0x00u, 0x00u, 0xA0u, 0x22u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x32u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x51u, 0x00u, 0x40u, 0x10u, 0x00u, 0xC0u, 0x51u, 0x00u, 0x40u, 0x10u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, 0x00u, 0x10u, 0x00u, 0x14u, 0x01u, 0x40u, 0x00u, 0x08u, @@ -1158,7 +1158,7 @@ __attribute__ ((__section__(".cymeta"), used)) #endif const uint8 cy_metadata[] = { 0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u, - 0x2Eu, 0x1Fu, 0x9Au, 0x39u}; + 0x2Eu, 0x1Fu, 0x9Au, 0x6Bu}; #if defined(__GNUC__) || defined(__ARMCC_VERSION) __attribute__ ((__section__(".cycustnvl"), used)) diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index a3ecd42..e79356b 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -71,6 +71,20 @@ #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* SCSI_Parity_Error */ +#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__0__POS 0 +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK +#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST + /* USBFS_bus_reset */ #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 @@ -84,41 +98,32 @@ /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL /* SCSI_Out_Bits */ #define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB10_11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB10_11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB10_11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB10_11_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB10_11_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB10_11_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB10_11_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u @@ -133,15 +138,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB10_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB10_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB10_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB10_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL /* USBFS_arb_int */ #define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -630,34 +635,34 @@ #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB08_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB08_ST -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB08_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB08_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB08_MSK -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB09_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB09_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB09_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB09_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB09_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB09_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB09_MSK +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -665,17 +670,11 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB11_MSK -#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB11_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB10_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB10_ST #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u @@ -685,28 +684,32 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB08_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB08_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB08_09_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB08_09_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB08_09_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB08_09_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB08_09_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB08_09_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB08_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB08_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB08_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB08_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB08_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB08_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB08_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB08_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB08_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB08_F1 -#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB11_MSK +#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B1_UDB11_ST_CTL +#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB11_ST_CTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB11_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB09_10_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB09_10_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB09_10_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB09_10_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB09_10_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB09_10_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB09_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB09_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB09_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB09_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB09_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB09_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB09_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB09_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB09_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB09_F1 +#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL /* USBFS_dp_int */ #define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -1184,21 +1187,21 @@ #define SD_Data_Clk__PM_STBY_MSK 0x01u /* timer_clock */ -#define timer_clock__CFG0 CYREG_CLKDIST_DCFG1_CFG0 -#define timer_clock__CFG1 CYREG_CLKDIST_DCFG1_CFG1 -#define timer_clock__CFG2 CYREG_CLKDIST_DCFG1_CFG2 +#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0 +#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1 +#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2 #define timer_clock__CFG2_SRC_SEL_MASK 0x07u -#define timer_clock__INDEX 0x01u +#define timer_clock__INDEX 0x02u #define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define timer_clock__PM_ACT_MSK 0x02u +#define timer_clock__PM_ACT_MSK 0x04u #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define timer_clock__PM_STBY_MSK 0x02u +#define timer_clock__PM_STBY_MSK 0x04u /* scsiTarget */ #define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__POS 0 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 #define scsiTarget_StatusReg__2__MASK 0x04u @@ -1208,54 +1211,54 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB13_MSK -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB13_ST -#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL -#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST -#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB14_MSK -#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL -#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL -#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL -#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB14_ST_CTL -#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB14_ST_CTL -#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB14_ST -#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL -#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK -#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK -#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL -#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB14_CTL -#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL -#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB14_CTL -#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL -#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL -#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB14_MSK -#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL -#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB14_15_A0 -#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB14_15_A1 -#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB14_15_D0 -#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB14_15_D1 -#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL -#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB14_15_F0 -#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB14_15_F1 -#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB14_A0_A1 -#define scsiTarget_datapath__A0_REG CYREG_B0_UDB14_A0 -#define scsiTarget_datapath__A1_REG CYREG_B0_UDB14_A1 -#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB14_D0_D1 -#define scsiTarget_datapath__D0_REG CYREG_B0_UDB14_D0 -#define scsiTarget_datapath__D1_REG CYREG_B0_UDB14_D1 -#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB14_ACTL -#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB14_F0_F1 -#define scsiTarget_datapath__F0_REG CYREG_B0_UDB14_F0 -#define scsiTarget_datapath__F1_REG CYREG_B0_UDB14_F1 -#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL -#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST +#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST +#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB11_MSK +#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL +#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL +#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB11_ST +#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL +#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK +#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB11_CTL +#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL +#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB11_CTL +#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL +#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB11_MSK +#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB11_12_A0 +#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB11_12_A1 +#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB11_12_D0 +#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB11_12_D1 +#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB11_12_F0 +#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB11_12_F1 +#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB11_A0_A1 +#define scsiTarget_datapath__A0_REG CYREG_B0_UDB11_A0 +#define scsiTarget_datapath__A1_REG CYREG_B0_UDB11_A1 +#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB11_D0_D1 +#define scsiTarget_datapath__D0_REG CYREG_B0_UDB11_D0 +#define scsiTarget_datapath__D1_REG CYREG_B0_UDB11_D1 +#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB11_F0_F1 +#define scsiTarget_datapath__F0_REG CYREG_B0_UDB11_F0 +#define scsiTarget_datapath__F1_REG CYREG_B0_UDB11_F1 +#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL /* USBFS_ep_0 */ #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -1493,6 +1496,17 @@ #define SCSI_ATN__SHIFT 0 #define SCSI_ATN__SLW CYREG_PRT2_SLW +/* SCSI_CLK */ +#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 +#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 +#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2 +#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u +#define SCSI_CLK__INDEX 0x01u +#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SCSI_CLK__PM_ACT_MSK 0x02u +#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SCSI_CLK__PM_STBY_MSK 0x02u + /* SCSI_Out */ #define SCSI_Out__0__AG CYREG_PRT15_AG #define SCSI_Out__0__AMUX CYREG_PRT15_AMUX diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index b64e051..4162415 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 37u +#define CY_CFG_BASE_ADDR_COUNT 38u CYPACKED typedef struct { uint8 offset; @@ -189,8 +189,10 @@ static void ClockSetup(void) /* Configure Digital Clocks based on settings from Clock DWR */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u); - CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0017u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x19u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0000u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u); /* Configure ILO based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); @@ -226,7 +228,7 @@ static void ClockSetup(void) CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x03u))); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x07u))); } @@ -378,1161 +380,1444 @@ void cyfitter_cfg(void) static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004502u, /* Base address: 0x40004500 Count: 2 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x4000520Eu, /* Base address: 0x40005200 Count: 14 */ + 0x40005210u, /* Base address: 0x40005200 Count: 16 */ 0x40006402u, /* Base address: 0x40006400 Count: 2 */ - 0x40010004u, /* Base address: 0x40010000 Count: 4 */ - 0x40010103u, /* Base address: 0x40010100 Count: 3 */ - 0x40010305u, /* Base address: 0x40010300 Count: 5 */ - 0x40010503u, /* Base address: 0x40010500 Count: 3 */ - 0x40010702u, /* Base address: 0x40010700 Count: 2 */ - 0x40010858u, /* Base address: 0x40010800 Count: 88 */ - 0x4001094Du, /* Base address: 0x40010900 Count: 77 */ + 0x40010104u, /* Base address: 0x40010100 Count: 4 */ + 0x4001023Du, /* Base address: 0x40010200 Count: 61 */ + 0x40010340u, /* Base address: 0x40010300 Count: 64 */ + 0x40010451u, /* Base address: 0x40010400 Count: 81 */ + 0x4001054Eu, /* Base address: 0x40010500 Count: 78 */ + 0x40010715u, /* Base address: 0x40010700 Count: 21 */ + 0x40010818u, /* Base address: 0x40010800 Count: 24 */ + 0x40010952u, /* Base address: 0x40010900 Count: 82 */ 0x40010A4Cu, /* Base address: 0x40010A00 Count: 76 */ - 0x40010B49u, /* Base address: 0x40010B00 Count: 73 */ - 0x40010C4Eu, /* Base address: 0x40010C00 Count: 78 */ - 0x40010D4Cu, /* Base address: 0x40010D00 Count: 76 */ - 0x40010E3Au, /* Base address: 0x40010E00 Count: 58 */ - 0x40010F38u, /* Base address: 0x40010F00 Count: 56 */ - 0x40011503u, /* Base address: 0x40011500 Count: 3 */ - 0x40011702u, /* Base address: 0x40011700 Count: 2 */ - 0x40011853u, /* Base address: 0x40011800 Count: 83 */ - 0x40011948u, /* Base address: 0x40011900 Count: 72 */ - 0x40011A4Fu, /* Base address: 0x40011A00 Count: 79 */ - 0x40011B4Au, /* Base address: 0x40011B00 Count: 74 */ - 0x40014015u, /* Base address: 0x40014000 Count: 21 */ + 0x40010B57u, /* Base address: 0x40010B00 Count: 87 */ + 0x40010C48u, /* Base address: 0x40010C00 Count: 72 */ + 0x40010D4Du, /* Base address: 0x40010D00 Count: 77 */ + 0x40010E53u, /* Base address: 0x40010E00 Count: 83 */ + 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */ + 0x4001150Bu, /* Base address: 0x40011500 Count: 11 */ + 0x4001170Fu, /* Base address: 0x40011700 Count: 15 */ + 0x4001184Eu, /* Base address: 0x40011800 Count: 78 */ + 0x40011947u, /* Base address: 0x40011900 Count: 71 */ + 0x40011A48u, /* Base address: 0x40011A00 Count: 72 */ + 0x40011B57u, /* Base address: 0x40011B00 Count: 87 */ + 0x40014016u, /* Base address: 0x40014000 Count: 22 */ 0x40014114u, /* Base address: 0x40014100 Count: 20 */ - 0x40014213u, /* Base address: 0x40014200 Count: 19 */ - 0x40014305u, /* Base address: 0x40014300 Count: 5 */ - 0x4001440Du, /* Base address: 0x40014400 Count: 13 */ - 0x40014515u, /* Base address: 0x40014500 Count: 21 */ + 0x40014211u, /* Base address: 0x40014200 Count: 17 */ + 0x40014306u, /* Base address: 0x40014300 Count: 6 */ + 0x40014411u, /* Base address: 0x40014400 Count: 17 */ + 0x40014513u, /* Base address: 0x40014500 Count: 19 */ 0x40014610u, /* Base address: 0x40014600 Count: 16 */ - 0x40014717u, /* Base address: 0x40014700 Count: 23 */ - 0x40014804u, /* Base address: 0x40014800 Count: 4 */ + 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */ + 0x40014806u, /* Base address: 0x40014800 Count: 6 */ 0x4001490Du, /* Base address: 0x40014900 Count: 13 */ - 0x40014C09u, /* Base address: 0x40014C00 Count: 9 */ - 0x40014D0Eu, /* Base address: 0x40014D00 Count: 14 */ - 0x40015007u, /* Base address: 0x40015000 Count: 7 */ + 0x40014C07u, /* Base address: 0x40014C00 Count: 7 */ + 0x40014D0Fu, /* Base address: 0x40014D00 Count: 15 */ + 0x40015004u, /* Base address: 0x40015000 Count: 4 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x27u, 0x02u}, {0x7Eu, 0x02u}, - {0x01u, 0x10u}, + {0x01u, 0x20u}, {0x0Au, 0x4Bu}, - {0x00u, 0x40u}, - {0x01u, 0x04u}, - {0x04u, 0x01u}, - {0x10u, 0x04u}, - {0x11u, 0x88u}, - {0x18u, 0x0Cu}, - {0x19u, 0x08u}, + {0x00u, 0x08u}, + {0x01u, 0x40u}, + {0x04u, 0x31u}, + {0x10u, 0x84u}, + {0x11u, 0x08u}, + {0x14u, 0x01u}, + {0x18u, 0x08u}, + {0x19u, 0x0Cu}, {0x1Cu, 0x20u}, {0x21u, 0x10u}, - {0x28u, 0x03u}, - {0x29u, 0x01u}, - {0x30u, 0x20u}, + {0x24u, 0x4Cu}, + {0x28u, 0x02u}, + {0x31u, 0x20u}, + {0x34u, 0x08u}, {0x78u, 0x20u}, {0x7Cu, 0x40u}, - {0x2Eu, 0x02u}, - {0x88u, 0x0Fu}, - {0xB8u, 0x80u}, - {0xBEu, 0x40u}, - {0xD8u, 0x04u}, - {0xDFu, 0x01u}, - {0x1Eu, 0x02u}, - {0xE0u, 0x40u}, - {0xE2u, 0x81u}, - {0x8Eu, 0x01u}, - {0xA2u, 0x01u}, - {0xE2u, 0x10u}, - {0xE6u, 0x04u}, - {0xEEu, 0x10u}, - {0xE2u, 0x18u}, - {0xE6u, 0x01u}, - {0xEEu, 0x04u}, - {0xEAu, 0x40u}, - {0xEEu, 0x08u}, - {0x01u, 0x01u}, - {0x04u, 0x04u}, - {0x06u, 0x03u}, - {0x08u, 0x85u}, - {0x09u, 0x01u}, - {0x0Au, 0x02u}, - {0x10u, 0x83u}, - {0x11u, 0x01u}, - {0x12u, 0x04u}, - {0x14u, 0x81u}, - {0x16u, 0x06u}, - {0x1Au, 0x08u}, - {0x1Cu, 0x28u}, - {0x1Du, 0x01u}, - {0x1Eu, 0x50u}, - {0x26u, 0x40u}, - {0x2Au, 0x10u}, - {0x2Eu, 0x20u}, - {0x30u, 0x80u}, - {0x31u, 0x01u}, - {0x32u, 0x07u}, - {0x34u, 0x18u}, - {0x36u, 0x60u}, - {0x39u, 0x02u}, - {0x3Au, 0x08u}, - {0x3Eu, 0x51u}, + {0x2Bu, 0x02u}, + {0x89u, 0x0Fu}, + {0x8Bu, 0x01u}, + {0x8Eu, 0x40u}, + {0xE4u, 0x04u}, + {0xE6u, 0x22u}, + {0x04u, 0x01u}, + {0x07u, 0x02u}, + {0x0Fu, 0x01u}, + {0x15u, 0x01u}, + {0x17u, 0x02u}, + {0x1Cu, 0x01u}, + {0x28u, 0x01u}, + {0x2Cu, 0x01u}, + {0x31u, 0x03u}, + {0x32u, 0x01u}, + {0x38u, 0x08u}, + {0x3Eu, 0x04u}, {0x3Fu, 0x01u}, - {0x40u, 0x43u}, - {0x41u, 0x02u}, - {0x42u, 0x10u}, - {0x44u, 0x05u}, - {0x45u, 0x0Eu}, - {0x46u, 0xBFu}, - {0x47u, 0xDCu}, - {0x48u, 0x3Du}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x22u}, - {0x4Eu, 0xF0u}, - {0x4Fu, 0x08u}, - {0x50u, 0x04u}, - {0x56u, 0x02u}, - {0x57u, 0x28u}, + {0x54u, 0x01u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Au, 0x04u}, {0x5Bu, 0x04u}, + {0x5Du, 0x10u}, {0x5Fu, 0x01u}, - {0x62u, 0xC0u}, - {0x64u, 0x40u}, - {0x65u, 0x01u}, - {0x66u, 0x10u}, - {0x67u, 0x11u}, - {0x68u, 0xC0u}, - {0x69u, 0x01u}, - {0x6Bu, 0x11u}, - {0x6Cu, 0x40u}, - {0x6Du, 0x01u}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x01u}, - {0x81u, 0x01u}, - {0x82u, 0x06u}, - {0x84u, 0x09u}, - {0x85u, 0x04u}, - {0x86u, 0x12u}, - {0x8Au, 0x09u}, - {0x8Eu, 0x08u}, - {0x90u, 0x09u}, - {0x92u, 0x24u}, - {0x9Au, 0x70u}, - {0x9Cu, 0x40u}, - {0x9Eu, 0x80u}, - {0xA1u, 0x02u}, - {0xA2u, 0x80u}, - {0xAEu, 0x01u}, - {0xB0u, 0x07u}, - {0xB3u, 0x02u}, - {0xB4u, 0x38u}, - {0xB5u, 0x01u}, - {0xB6u, 0xC0u}, - {0xB7u, 0x04u}, - {0xBEu, 0x40u}, - {0xBFu, 0x54u}, + {0x81u, 0x04u}, + {0x85u, 0x08u}, + {0x86u, 0x0Eu}, + {0x88u, 0x14u}, + {0x89u, 0x01u}, + {0x8Au, 0x0Au}, + {0x8Bu, 0x02u}, + {0x8Eu, 0x10u}, + {0x8Fu, 0x38u}, + {0x92u, 0x40u}, + {0x93u, 0x40u}, + {0x94u, 0x08u}, + {0x96u, 0x10u}, + {0x97u, 0x01u}, + {0x98u, 0x01u}, + {0x99u, 0x38u}, + {0x9Cu, 0x12u}, + {0x9Eu, 0x04u}, + {0x9Fu, 0x10u}, + {0xA0u, 0x01u}, + {0xA1u, 0x20u}, + {0xA4u, 0x20u}, + {0xA6u, 0x40u}, + {0xAAu, 0x20u}, + {0xABu, 0x02u}, + {0xACu, 0x01u}, + {0xB1u, 0x04u}, + {0xB2u, 0x1Eu}, + {0xB3u, 0x38u}, + {0xB4u, 0x60u}, + {0xB5u, 0x40u}, + {0xB6u, 0x01u}, + {0xB7u, 0x03u}, + {0xBEu, 0x50u}, + {0xBFu, 0x44u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDCu, 0x09u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x80u}, - {0x01u, 0x2Au}, - {0x04u, 0x20u}, - {0x05u, 0x04u}, - {0x08u, 0x44u}, - {0x09u, 0x08u}, - {0x0Au, 0x48u}, - {0x0Cu, 0x40u}, - {0x0Du, 0x42u}, - {0x0Eu, 0x20u}, - {0x0Fu, 0x04u}, - {0x11u, 0x01u}, - {0x13u, 0x40u}, + {0x01u, 0x28u}, + {0x02u, 0x02u}, + {0x04u, 0x04u}, + {0x08u, 0x40u}, + {0x09u, 0x04u}, + {0x0Au, 0x40u}, + {0x0Bu, 0x04u}, + {0x0Eu, 0x01u}, + {0x12u, 0x81u}, + {0x13u, 0x28u}, {0x14u, 0x01u}, - {0x15u, 0x18u}, - {0x16u, 0x01u}, - {0x17u, 0x08u}, - {0x19u, 0x02u}, - {0x1Au, 0x0Au}, - {0x1Du, 0x04u}, - {0x1Eu, 0x08u}, - {0x1Fu, 0x41u}, - {0x20u, 0x04u}, - {0x22u, 0x40u}, - {0x23u, 0x20u}, - {0x25u, 0x01u}, + {0x17u, 0x10u}, + {0x18u, 0x02u}, + {0x19u, 0x0Cu}, + {0x1Bu, 0x20u}, + {0x1Cu, 0x20u}, + {0x21u, 0x50u}, + {0x22u, 0x05u}, + {0x24u, 0x80u}, + {0x2Au, 0x11u}, {0x2Bu, 0x80u}, - {0x36u, 0x82u}, - {0x38u, 0x0Au}, - {0x3Cu, 0x22u}, - {0x44u, 0x02u}, - {0x45u, 0x16u}, - {0x4Du, 0x84u}, - {0x56u, 0x18u}, - {0x57u, 0x59u}, - {0x65u, 0x04u}, - {0x6Fu, 0x55u}, - {0x76u, 0x02u}, - {0x82u, 0x04u}, - {0x86u, 0x01u}, - {0x8Bu, 0xC0u}, - {0x90u, 0x40u}, - {0x92u, 0x40u}, - {0x93u, 0x4Cu}, - {0x94u, 0x24u}, - {0x95u, 0x90u}, - {0x96u, 0x80u}, - {0x98u, 0x1Au}, - {0x99u, 0x38u}, - {0x9Au, 0x01u}, - {0x9Cu, 0x64u}, - {0x9Du, 0x41u}, - {0x9Eu, 0x0Au}, - {0x9Fu, 0x7Du}, - {0xA0u, 0x41u}, - {0xA1u, 0x42u}, - {0xA2u, 0x81u}, - {0xA3u, 0x22u}, - {0xA5u, 0x35u}, - {0xA6u, 0x10u}, - {0xA7u, 0x41u}, - {0xB0u, 0x08u}, - {0xB5u, 0x41u}, - {0xB6u, 0x20u}, - {0xB7u, 0x40u}, - {0xC0u, 0x6Fu}, - {0xC2u, 0xFBu}, - {0xC4u, 0xE9u}, - {0xCAu, 0x01u}, - {0xCCu, 0x90u}, - {0xCEu, 0xA3u}, - {0xD0u, 0xF0u}, - {0xD2u, 0x10u}, - {0xD8u, 0x40u}, - {0xE4u, 0x06u}, - {0xEAu, 0x40u}, - {0xEEu, 0x08u}, - {0x04u, 0x09u}, - {0x05u, 0x04u}, - {0x06u, 0x12u}, - {0x0Au, 0x09u}, - {0x0Eu, 0x30u}, - {0x10u, 0x09u}, - {0x12u, 0x24u}, - {0x15u, 0x02u}, - {0x16u, 0x46u}, - {0x1Au, 0x80u}, - {0x1Eu, 0x08u}, - {0x20u, 0x40u}, - {0x21u, 0x01u}, - {0x22u, 0x80u}, - {0x26u, 0x01u}, - {0x30u, 0x38u}, - {0x31u, 0x02u}, - {0x32u, 0x07u}, - {0x33u, 0x04u}, - {0x34u, 0xC0u}, - {0x35u, 0x01u}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x15u}, + {0x31u, 0x14u}, + {0x32u, 0x81u}, + {0x33u, 0x40u}, + {0x37u, 0x08u}, + {0x38u, 0x40u}, + {0x3Au, 0x20u}, + {0x3Bu, 0x05u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x04u}, + {0x5Au, 0x80u}, + {0x5Fu, 0x80u}, + {0x63u, 0x01u}, + {0x6Cu, 0x20u}, + {0x6Fu, 0x09u}, + {0x80u, 0x40u}, + {0x85u, 0x10u}, + {0x87u, 0x80u}, + {0x88u, 0x20u}, + {0x8Bu, 0x20u}, + {0x8Du, 0x10u}, + {0x8Eu, 0x10u}, + {0x8Fu, 0x08u}, + {0x92u, 0x80u}, + {0x93u, 0x40u}, + {0x95u, 0x20u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x08u}, + {0xA8u, 0x08u}, + {0xADu, 0x10u}, + {0xB3u, 0x40u}, + {0xC0u, 0x27u}, + {0xC2u, 0x8Fu}, + {0xC4u, 0xCFu}, + {0xCAu, 0x05u}, + {0xCCu, 0x4Fu}, + {0xCEu, 0x5Fu}, + {0xD6u, 0x18u}, + {0xD8u, 0x08u}, + {0xE0u, 0x03u}, + {0xE2u, 0x18u}, + {0xE6u, 0x38u}, + {0xE8u, 0x02u}, + {0xEAu, 0x01u}, + {0x01u, 0x05u}, + {0x03u, 0x0Au}, + {0x04u, 0x05u}, + {0x06u, 0x0Au}, + {0x09u, 0xA0u}, + {0x0Bu, 0x4Fu}, + {0x0Du, 0x03u}, + {0x0Fu, 0x0Cu}, + {0x10u, 0x60u}, + {0x12u, 0x90u}, + {0x13u, 0x70u}, + {0x15u, 0x06u}, + {0x17u, 0x09u}, + {0x18u, 0x30u}, + {0x19u, 0x0Fu}, + {0x1Au, 0xC0u}, + {0x1Cu, 0x03u}, + {0x1Du, 0x90u}, + {0x1Eu, 0x0Cu}, + {0x1Fu, 0x2Fu}, + {0x21u, 0x80u}, + {0x24u, 0x50u}, + {0x26u, 0xA0u}, + {0x27u, 0x80u}, + {0x28u, 0x06u}, + {0x29u, 0xC0u}, + {0x2Au, 0x09u}, + {0x2Bu, 0x1Fu}, + {0x2Cu, 0x0Fu}, + {0x2Eu, 0xF0u}, + {0x30u, 0xFFu}, + {0x31u, 0x7Fu}, + {0x37u, 0x80u}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x40u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Cu, 0x09u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x10u}, {0x5Fu, 0x01u}, - {0x80u, 0xD6u}, + {0x81u, 0x03u}, + {0x83u, 0x0Cu}, + {0x85u, 0x09u}, + {0x87u, 0x06u}, + {0x89u, 0x50u}, + {0x8Au, 0xFFu}, + {0x8Bu, 0xA0u}, + {0x8Cu, 0xFFu}, + {0x8Du, 0x0Fu}, + {0x8Fu, 0xF0u}, + {0x90u, 0x05u}, + {0x92u, 0x0Au}, + {0x93u, 0xFFu}, + {0x94u, 0x50u}, + {0x95u, 0x90u}, + {0x96u, 0xA0u}, + {0x97u, 0x60u}, + {0x98u, 0x06u}, + {0x9Au, 0x09u}, + {0x9Bu, 0xFFu}, + {0x9Cu, 0x30u}, + {0x9Du, 0x05u}, + {0x9Eu, 0xC0u}, + {0x9Fu, 0x0Au}, + {0xA0u, 0x03u}, + {0xA1u, 0x30u}, + {0xA2u, 0x0Cu}, + {0xA3u, 0xC0u}, + {0xA6u, 0xFFu}, + {0xA7u, 0xFFu}, + {0xA8u, 0x60u}, + {0xAAu, 0x90u}, + {0xACu, 0x0Fu}, + {0xAEu, 0xF0u}, + {0xB3u, 0xFFu}, + {0xB6u, 0xFFu}, + {0xBEu, 0x40u}, + {0xBFu, 0x04u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDFu, 0x01u}, + {0x01u, 0x08u}, + {0x04u, 0x80u}, + {0x06u, 0x08u}, + {0x09u, 0x40u}, + {0x0Au, 0x44u}, + {0x0Cu, 0x80u}, + {0x0Eu, 0x80u}, + {0x0Fu, 0x14u}, + {0x11u, 0x40u}, + {0x12u, 0x10u}, + {0x13u, 0x20u}, + {0x14u, 0x14u}, + {0x15u, 0x41u}, + {0x18u, 0x80u}, + {0x19u, 0x02u}, + {0x1Eu, 0x01u}, + {0x21u, 0x02u}, + {0x22u, 0x80u}, + {0x23u, 0x80u}, + {0x27u, 0x10u}, + {0x29u, 0x04u}, + {0x2Au, 0x20u}, + {0x2Bu, 0x80u}, + {0x2Cu, 0x80u}, + {0x2Eu, 0x08u}, + {0x2Fu, 0x20u}, + {0x30u, 0x78u}, + {0x31u, 0x02u}, + {0x32u, 0x20u}, + {0x34u, 0x84u}, + {0x35u, 0x02u}, + {0x36u, 0x64u}, + {0x3Au, 0x01u}, + {0x3Bu, 0x60u}, + {0x3Du, 0x41u}, + {0x3Fu, 0x96u}, + {0x59u, 0x85u}, + {0x5Au, 0x10u}, + {0x62u, 0x80u}, + {0x80u, 0x80u}, + {0x83u, 0x40u}, + {0x84u, 0x40u}, + {0x86u, 0x02u}, + {0x8Eu, 0x01u}, + {0x8Fu, 0x80u}, + {0x92u, 0x10u}, + {0x93u, 0x40u}, + {0x94u, 0x44u}, + {0x96u, 0x45u}, + {0x99u, 0x08u}, + {0x9Bu, 0x20u}, + {0x9Cu, 0x41u}, + {0x9Du, 0x20u}, + {0x9Eu, 0x10u}, + {0x9Fu, 0xD0u}, + {0xA0u, 0x28u}, + {0xA3u, 0x40u}, + {0xA5u, 0x44u}, + {0xA6u, 0x02u}, + {0xA9u, 0x40u}, + {0xAEu, 0x04u}, + {0xAFu, 0x04u}, + {0xB0u, 0x10u}, + {0xB4u, 0x01u}, + {0xB6u, 0x20u}, + {0xB7u, 0x68u}, + {0xC0u, 0xC4u}, + {0xC2u, 0xFBu}, + {0xC4u, 0xF7u}, + {0xCAu, 0xC7u}, + {0xCCu, 0xFFu}, + {0xCEu, 0xFDu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x08u}, + {0xE2u, 0x0Eu}, + {0xE6u, 0x39u}, + {0xE8u, 0x01u}, + {0xEAu, 0x02u}, + {0x81u, 0x04u}, + {0x82u, 0x20u}, + {0x89u, 0x40u}, + {0x90u, 0x80u}, + {0x94u, 0x44u}, + {0x96u, 0x44u}, + {0x97u, 0x10u}, + {0x9Cu, 0x81u}, + {0x9Eu, 0x30u}, + {0xA5u, 0x44u}, + {0xA6u, 0x04u}, + {0xA7u, 0x20u}, + {0xA9u, 0x80u}, + {0xADu, 0x20u}, + {0xAFu, 0x10u}, + {0xB3u, 0x05u}, + {0xB5u, 0x05u}, + {0xE2u, 0x04u}, + {0xE4u, 0x80u}, + {0xEAu, 0x04u}, + {0xEEu, 0x82u}, + {0x03u, 0x08u}, + {0x13u, 0x07u}, + {0x15u, 0x19u}, + {0x17u, 0x22u}, + {0x19u, 0x14u}, + {0x1Bu, 0x48u}, + {0x1Du, 0x80u}, + {0x21u, 0x6Au}, + {0x23u, 0x15u}, + {0x24u, 0x02u}, + {0x27u, 0x20u}, + {0x28u, 0x01u}, + {0x2Fu, 0x70u}, + {0x32u, 0x02u}, + {0x33u, 0x70u}, + {0x34u, 0x01u}, + {0x35u, 0x80u}, + {0x37u, 0x0Fu}, + {0x3Eu, 0x14u}, + {0x3Fu, 0x10u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Cu, 0x10u}, + {0x5Fu, 0x01u}, + {0x00u, 0xA0u}, + {0x01u, 0x01u}, + {0x0Au, 0xAAu}, + {0x11u, 0x40u}, + {0x12u, 0x60u}, + {0x13u, 0x02u}, + {0x14u, 0x28u}, + {0x17u, 0x08u}, + {0x19u, 0x02u}, + {0x1Cu, 0x10u}, + {0x1Fu, 0x10u}, + {0x20u, 0x04u}, + {0x21u, 0x10u}, + {0x22u, 0x15u}, + {0x23u, 0x10u}, + {0x27u, 0x15u}, + {0x29u, 0x20u}, + {0x2Au, 0x40u}, + {0x2Bu, 0x08u}, + {0x2Cu, 0x40u}, + {0x2Du, 0x88u}, + {0x2Fu, 0x40u}, + {0x32u, 0x55u}, + {0x34u, 0x80u}, + {0x35u, 0x04u}, + {0x37u, 0x11u}, + {0x39u, 0x55u}, + {0x3Cu, 0x02u}, + {0x40u, 0x40u}, + {0x41u, 0x14u}, + {0x46u, 0x20u}, + {0x47u, 0x04u}, + {0x48u, 0x40u}, + {0x49u, 0x41u}, + {0x4Bu, 0x14u}, + {0x52u, 0x11u}, + {0x53u, 0x0Cu}, + {0x62u, 0x08u}, + {0x68u, 0x1Cu}, + {0x69u, 0x55u}, + {0x73u, 0x02u}, + {0x83u, 0x10u}, + {0x89u, 0x04u}, + {0x8Bu, 0x01u}, + {0x90u, 0x08u}, + {0x92u, 0x04u}, + {0x93u, 0x82u}, + {0x94u, 0x10u}, + {0x95u, 0x65u}, + {0x96u, 0xEAu}, + {0x97u, 0x20u}, + {0x98u, 0x12u}, + {0x99u, 0x8Cu}, + {0x9Au, 0x82u}, + {0x9Cu, 0x88u}, + {0x9Du, 0x02u}, + {0x9Eu, 0x20u}, + {0x9Fu, 0x1Au}, + {0xA0u, 0x81u}, + {0xA1u, 0x08u}, + {0xA2u, 0x30u}, + {0xA4u, 0x54u}, + {0xA5u, 0x04u}, + {0xA6u, 0x02u}, + {0xA7u, 0x01u}, + {0xA9u, 0x20u}, + {0xADu, 0x80u}, + {0xB2u, 0x15u}, + {0xB6u, 0x09u}, + {0xC0u, 0x0Bu}, + {0xC2u, 0x0Fu}, + {0xC4u, 0x6Du}, + {0xCAu, 0xDCu}, + {0xCCu, 0xFFu}, + {0xCEu, 0x8Fu}, + {0xD0u, 0x07u}, + {0xD2u, 0x0Cu}, + {0xD8u, 0x02u}, + {0xE4u, 0x80u}, + {0xE6u, 0x20u}, + {0xEAu, 0x90u}, + {0xEEu, 0xE0u}, + {0x00u, 0xC0u}, + {0x02u, 0x02u}, + {0x04u, 0xC0u}, + {0x06u, 0x08u}, + {0x08u, 0xC0u}, + {0x0Au, 0x04u}, + {0x0Eu, 0x9Fu}, + {0x11u, 0x01u}, + {0x12u, 0xFFu}, + {0x14u, 0x1Fu}, + {0x16u, 0x20u}, + {0x18u, 0x7Fu}, + {0x1Au, 0x80u}, + {0x1Cu, 0x80u}, + {0x20u, 0xC0u}, + {0x21u, 0x02u}, + {0x22u, 0x01u}, + {0x26u, 0x60u}, + {0x29u, 0x02u}, + {0x2Cu, 0x90u}, + {0x2Du, 0x04u}, + {0x2Eu, 0x40u}, + {0x31u, 0x01u}, + {0x34u, 0xFFu}, + {0x35u, 0x02u}, + {0x37u, 0x04u}, + {0x39u, 0x20u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x41u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Fu, 0x01u}, + {0x80u, 0x01u}, + {0x86u, 0x58u}, + {0x89u, 0x01u}, + {0x8Eu, 0xFEu}, + {0x94u, 0x76u}, + {0x96u, 0x80u}, + {0x98u, 0x06u}, + {0x9Au, 0x08u}, + {0x9Cu, 0x9Eu}, + {0x9Eu, 0x60u}, + {0xA0u, 0x20u}, + {0xA2u, 0x02u}, + {0xA8u, 0x06u}, + {0xACu, 0x04u}, + {0xB0u, 0x01u}, + {0xB2u, 0xE0u}, + {0xB5u, 0x01u}, + {0xB6u, 0x1Eu}, + {0xBEu, 0x01u}, + {0xBFu, 0x10u}, + {0xC0u, 0x21u}, + {0xC1u, 0x03u}, + {0xC2u, 0x60u}, + {0xC5u, 0xF2u}, + {0xC6u, 0xE0u}, + {0xC7u, 0xDCu}, + {0xC8u, 0x3Bu}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCFu, 0x2Cu}, + {0xD6u, 0x01u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDAu, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x01u}, + {0xDDu, 0x01u}, + {0xDFu, 0x01u}, + {0xE2u, 0xC0u}, + {0xE6u, 0x80u}, + {0xE8u, 0x40u}, + {0xE9u, 0x40u}, + {0xEEu, 0x08u}, + {0x00u, 0xA8u}, + {0x01u, 0x01u}, + {0x03u, 0x20u}, + {0x05u, 0x80u}, + {0x06u, 0x40u}, + {0x07u, 0x10u}, + {0x08u, 0x01u}, + {0x0Au, 0xAAu}, + {0x0Du, 0x08u}, + {0x0Eu, 0x0Au}, + {0x10u, 0x40u}, + {0x11u, 0x40u}, + {0x12u, 0x20u}, + {0x13u, 0x02u}, + {0x16u, 0x89u}, + {0x17u, 0x01u}, + {0x19u, 0x20u}, + {0x1Cu, 0x40u}, + {0x1Du, 0x8Cu}, + {0x1Eu, 0x02u}, + {0x1Fu, 0x4Cu}, + {0x22u, 0x20u}, + {0x23u, 0x41u}, + {0x24u, 0x04u}, + {0x29u, 0x62u}, + {0x31u, 0x01u}, + {0x3Fu, 0x10u}, + {0x45u, 0x88u}, + {0x47u, 0x10u}, + {0x4Cu, 0x40u}, + {0x4Du, 0x18u}, + {0x4Fu, 0x04u}, + {0x55u, 0x20u}, + {0x56u, 0x09u}, + {0x5Cu, 0x55u}, + {0x66u, 0x20u}, + {0x67u, 0x61u}, + {0x6Cu, 0x95u}, + {0x74u, 0x29u}, + {0x76u, 0x02u}, + {0x81u, 0x04u}, + {0x82u, 0x40u}, + {0x84u, 0x08u}, + {0x87u, 0x04u}, + {0x8Eu, 0x06u}, + {0x8Fu, 0x02u}, + {0x90u, 0x01u}, + {0x91u, 0x10u}, + {0x92u, 0x05u}, + {0x93u, 0x12u}, + {0x94u, 0xA2u}, + {0x95u, 0x65u}, + {0x96u, 0x48u}, + {0x97u, 0x84u}, + {0x98u, 0x12u}, + {0x99u, 0xC1u}, + {0x9Au, 0x40u}, + {0x9Bu, 0x01u}, + {0x9Cu, 0xC9u}, + {0x9Du, 0x04u}, + {0x9Fu, 0x18u}, + {0xA2u, 0x14u}, + {0xA3u, 0x02u}, + {0xA4u, 0x20u}, + {0xA5u, 0x2Cu}, + {0xA6u, 0x01u}, + {0xA7u, 0x29u}, + {0xADu, 0x10u}, + {0xB0u, 0x10u}, + {0xB4u, 0x02u}, + {0xB6u, 0x42u}, + {0xB7u, 0x01u}, + {0xC0u, 0xBFu}, + {0xC2u, 0xEFu}, + {0xC4u, 0xDDu}, + {0xCAu, 0x0Du}, + {0xCCu, 0x01u}, + {0xCEu, 0x20u}, + {0xD0u, 0x70u}, + {0xD2u, 0x20u}, + {0xD6u, 0xF0u}, + {0xD8u, 0xF0u}, + {0xE2u, 0x48u}, + {0xE6u, 0x70u}, + {0xE8u, 0x41u}, + {0xECu, 0x80u}, + {0xEEu, 0x50u}, + {0x02u, 0x08u}, + {0x04u, 0x99u}, + {0x05u, 0x20u}, + {0x06u, 0x22u}, + {0x0Au, 0x80u}, + {0x0Fu, 0x01u}, + {0x13u, 0x0Eu}, + {0x16u, 0x70u}, + {0x19u, 0x08u}, + {0x1Au, 0x07u}, + {0x1Bu, 0x10u}, + {0x1Cu, 0xAAu}, + {0x1Eu, 0x55u}, + {0x21u, 0x14u}, + {0x23u, 0x0Au}, + {0x27u, 0x10u}, + {0x28u, 0x44u}, + {0x29u, 0x12u}, + {0x2Au, 0x88u}, + {0x2Bu, 0x04u}, + {0x31u, 0x1Eu}, + {0x32u, 0xF0u}, + {0x34u, 0x0Fu}, + {0x35u, 0x01u}, + {0x37u, 0x20u}, + {0x3Fu, 0x40u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Fu, 0x01u}, + {0x80u, 0x55u}, {0x81u, 0x0Du}, - {0x84u, 0xD2u}, - {0x85u, 0x22u}, - {0x86u, 0x04u}, - {0x87u, 0x18u}, - {0x88u, 0x31u}, + {0x82u, 0xAAu}, + {0x85u, 0x0Du}, + {0x86u, 0xFFu}, {0x89u, 0x11u}, - {0x8Au, 0x0Eu}, + {0x8Au, 0xFFu}, {0x8Bu, 0x22u}, - {0x8Du, 0x60u}, - {0x90u, 0x29u}, - {0x91u, 0x02u}, - {0x92u, 0x16u}, - {0x93u, 0x0Du}, - {0x94u, 0x17u}, - {0x95u, 0x0Du}, - {0x96u, 0x28u}, - {0x98u, 0x22u}, - {0x99u, 0x0Du}, - {0x9Au, 0x10u}, - {0x9Du, 0x0Du}, - {0x9Eu, 0x80u}, - {0xA0u, 0x06u}, + {0x8Du, 0x0Du}, + {0x8Eu, 0xFFu}, + {0x90u, 0xFFu}, + {0x95u, 0x22u}, + {0x97u, 0x18u}, + {0x99u, 0x60u}, + {0x9Cu, 0x69u}, + {0x9Du, 0x02u}, + {0x9Eu, 0x96u}, + {0x9Fu, 0x0Du}, {0xA1u, 0x0Du}, - {0xA2u, 0xD0u}, - {0xA4u, 0xD0u}, - {0xA6u, 0x06u}, - {0xA8u, 0x04u}, - {0xACu, 0xD6u}, + {0xA4u, 0x33u}, + {0xA5u, 0x0Du}, + {0xA6u, 0xCCu}, + {0xAAu, 0xFFu}, + {0xACu, 0x0Fu}, {0xADu, 0x12u}, + {0xAEu, 0xF0u}, {0xAFu, 0x44u}, + {0xB0u, 0xFFu}, + {0xB5u, 0x70u}, + {0xB7u, 0x0Fu}, + {0xB8u, 0x80u}, + {0xB9u, 0x20u}, + {0xBAu, 0x02u}, + {0xBBu, 0x80u}, + {0xBEu, 0x40u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x01u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x01u, 0x80u}, + {0x02u, 0x80u}, + {0x03u, 0x18u}, + {0x04u, 0x22u}, + {0x05u, 0x04u}, + {0x08u, 0x80u}, + {0x0Bu, 0x80u}, + {0x0Eu, 0x26u}, + {0x10u, 0x02u}, + {0x12u, 0x18u}, + {0x17u, 0x10u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x02u}, + {0x1Eu, 0x24u}, + {0x1Fu, 0x04u}, + {0x22u, 0x50u}, + {0x24u, 0x01u}, + {0x25u, 0x10u}, + {0x26u, 0x02u}, + {0x28u, 0x41u}, + {0x2Bu, 0x20u}, + {0x2Cu, 0x22u}, + {0x2Fu, 0x4Au}, + {0x32u, 0x54u}, + {0x36u, 0x02u}, + {0x37u, 0x10u}, + {0x39u, 0x65u}, + {0x3Cu, 0x04u}, + {0x3Du, 0x80u}, + {0x58u, 0x04u}, + {0x59u, 0x12u}, + {0x5Bu, 0x40u}, + {0x60u, 0x04u}, + {0x61u, 0x01u}, + {0x62u, 0x50u}, + {0x63u, 0x10u}, + {0x80u, 0x80u}, + {0x81u, 0x02u}, + {0x83u, 0x50u}, + {0x85u, 0x60u}, + {0x86u, 0x04u}, + {0x8Bu, 0x01u}, + {0x8Cu, 0x40u}, + {0x8Eu, 0x10u}, + {0x91u, 0x10u}, + {0x96u, 0x40u}, + {0x97u, 0x1Cu}, + {0x98u, 0x04u}, + {0x99u, 0xD0u}, + {0x9Cu, 0x08u}, + {0x9Du, 0x01u}, + {0x9Eu, 0x40u}, + {0x9Fu, 0x19u}, + {0xA2u, 0x8Cu}, + {0xA4u, 0x80u}, + {0xA5u, 0x1Cu}, + {0xA6u, 0x01u}, + {0xA7u, 0x01u}, + {0xA9u, 0x40u}, + {0xABu, 0x40u}, + {0xACu, 0x20u}, + {0xB1u, 0x20u}, + {0xB7u, 0x02u}, + {0xC0u, 0x7Fu}, + {0xC2u, 0xE9u}, + {0xC4u, 0x47u}, + {0xCAu, 0xEBu}, + {0xCCu, 0xAEu}, + {0xCEu, 0x5Fu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, + {0xE0u, 0x81u}, + {0xE2u, 0x40u}, + {0xE4u, 0x20u}, + {0xE6u, 0x15u}, + {0xEAu, 0x20u}, + {0xEEu, 0x01u}, + {0x03u, 0xFFu}, + {0x06u, 0xFFu}, + {0x0Au, 0xFFu}, + {0x0Du, 0x0Fu}, + {0x0Eu, 0xFFu}, + {0x0Fu, 0xF0u}, + {0x11u, 0xFFu}, + {0x16u, 0xFFu}, + {0x17u, 0xFFu}, + {0x18u, 0x0Fu}, + {0x1Au, 0xF0u}, + {0x1Bu, 0xFFu}, + {0x20u, 0x33u}, + {0x21u, 0x96u}, + {0x22u, 0xCCu}, + {0x23u, 0x69u}, + {0x24u, 0x55u}, + {0x26u, 0xAAu}, + {0x27u, 0xFFu}, + {0x28u, 0x69u}, + {0x29u, 0x55u}, + {0x2Au, 0x96u}, + {0x2Bu, 0xAAu}, + {0x2Cu, 0xFFu}, + {0x2Du, 0x33u}, + {0x2Fu, 0xCCu}, + {0x34u, 0xFFu}, + {0x37u, 0xFFu}, + {0x3Au, 0x20u}, + {0x3Bu, 0x80u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x83u, 0x02u}, + {0x87u, 0x80u}, + {0x89u, 0x30u}, + {0x8Bu, 0x01u}, + {0x8Du, 0x30u}, + {0x8Eu, 0x03u}, + {0x90u, 0x03u}, + {0x91u, 0x06u}, + {0x92u, 0x0Cu}, + {0x93u, 0x08u}, + {0x94u, 0x05u}, + {0x95u, 0x10u}, + {0x96u, 0x0Au}, + {0x97u, 0x22u}, + {0x99u, 0x02u}, + {0x9Au, 0x02u}, + {0x9Bu, 0x0Cu}, + {0x9Cu, 0x06u}, + {0x9Du, 0x04u}, + {0x9Eu, 0x09u}, + {0x9Fu, 0x0Au}, + {0xA0u, 0x01u}, + {0xA1u, 0x04u}, + {0xA3u, 0x0Au}, + {0xA5u, 0x20u}, + {0xA7u, 0x10u}, + {0xA8u, 0x07u}, + {0xAAu, 0x08u}, + {0xABu, 0x40u}, + {0xADu, 0x40u}, + {0xAFu, 0x80u}, {0xB0u, 0x0Fu}, - {0xB1u, 0x0Fu}, - {0xB2u, 0x80u}, - {0xB4u, 0x30u}, - {0xB6u, 0x40u}, - {0xB7u, 0x70u}, + {0xB1u, 0x01u}, + {0xB3u, 0x30u}, + {0xB5u, 0x0Eu}, + {0xB7u, 0xC0u}, + {0xBAu, 0x02u}, + {0xBBu, 0x28u}, + {0xBFu, 0x40u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x01u, 0x80u}, + {0x02u, 0x08u}, + {0x03u, 0x10u}, + {0x05u, 0x80u}, + {0x09u, 0x08u}, + {0x0Au, 0x04u}, + {0x0Du, 0x08u}, + {0x0Eu, 0x82u}, + {0x0Fu, 0x24u}, + {0x10u, 0x01u}, + {0x12u, 0x40u}, + {0x13u, 0x18u}, + {0x17u, 0x11u}, + {0x19u, 0x20u}, + {0x1Au, 0x04u}, + {0x1Eu, 0x80u}, + {0x21u, 0x40u}, + {0x24u, 0x48u}, + {0x26u, 0x2Cu}, + {0x27u, 0x02u}, + {0x28u, 0x08u}, + {0x29u, 0x01u}, + {0x2Bu, 0x11u}, + {0x2Cu, 0xA0u}, + {0x2Eu, 0x40u}, + {0x2Fu, 0x04u}, + {0x30u, 0x01u}, + {0x32u, 0x08u}, + {0x33u, 0x10u}, + {0x34u, 0x01u}, + {0x36u, 0x29u}, + {0x37u, 0x80u}, + {0x39u, 0x80u}, + {0x3Bu, 0x01u}, + {0x3Cu, 0x40u}, + {0x3Du, 0x28u}, + {0x3Fu, 0x01u}, + {0x4Cu, 0x04u}, + {0x4Du, 0x10u}, + {0x5Bu, 0x40u}, + {0x5Du, 0x40u}, + {0x61u, 0x40u}, + {0x62u, 0x80u}, + {0x65u, 0x80u}, + {0x67u, 0x01u}, + {0x81u, 0x40u}, + {0x86u, 0x40u}, + {0x88u, 0x04u}, + {0x89u, 0x08u}, + {0x8Bu, 0x80u}, + {0x8Du, 0x10u}, + {0xC0u, 0x87u}, + {0xC2u, 0xF6u}, + {0xC4u, 0x5Fu}, + {0xCAu, 0xFFu}, + {0xCCu, 0xF7u}, + {0xCEu, 0xF9u}, + {0xD6u, 0x18u}, + {0xD8u, 0x18u}, + {0xE2u, 0x10u}, + {0x86u, 0x04u}, + {0x8Au, 0x10u}, + {0x96u, 0x04u}, + {0x9Eu, 0x10u}, + {0xA8u, 0xC0u}, + {0xB3u, 0x30u}, + {0xB6u, 0x44u}, + {0xE2u, 0x06u}, + {0xE6u, 0x01u}, + {0xE8u, 0x01u}, + {0xEEu, 0x01u}, + {0x80u, 0x40u}, + {0x84u, 0x01u}, + {0x90u, 0x80u}, + {0x94u, 0x40u}, + {0x96u, 0x44u}, + {0x97u, 0x10u}, + {0x9Cu, 0x81u}, + {0x9Eu, 0x10u}, + {0xA6u, 0x04u}, + {0xA7u, 0x20u}, + {0xA8u, 0x04u}, + {0xE2u, 0x02u}, + {0xE6u, 0x04u}, + {0xEAu, 0x06u}, + {0xEEu, 0x08u}, + {0x01u, 0xFFu}, + {0x05u, 0x30u}, + {0x06u, 0x80u}, + {0x07u, 0xC0u}, + {0x09u, 0x50u}, + {0x0Bu, 0xA0u}, + {0x0Eu, 0x08u}, + {0x0Fu, 0xFFu}, + {0x11u, 0x05u}, + {0x13u, 0x0Au}, + {0x14u, 0x99u}, + {0x16u, 0x22u}, + {0x19u, 0x03u}, + {0x1Au, 0x07u}, + {0x1Bu, 0x0Cu}, + {0x1Du, 0x0Fu}, + {0x1Eu, 0x70u}, + {0x1Fu, 0xF0u}, + {0x20u, 0xAAu}, + {0x22u, 0x55u}, + {0x25u, 0x06u}, + {0x27u, 0x09u}, + {0x28u, 0x44u}, + {0x2Au, 0x88u}, + {0x2Bu, 0xFFu}, + {0x2Du, 0x60u}, + {0x2Fu, 0x90u}, + {0x33u, 0xFFu}, + {0x34u, 0x0Fu}, + {0x36u, 0xF0u}, + {0x3Fu, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Cu, 0x01u}, + {0x5Fu, 0x01u}, + {0x80u, 0x36u}, + {0x84u, 0x07u}, + {0x85u, 0x11u}, + {0x86u, 0x08u}, + {0x87u, 0x62u}, + {0x88u, 0x32u}, + {0x89u, 0x58u}, + {0x8Au, 0x04u}, + {0x8Bu, 0x23u}, + {0x8Cu, 0x06u}, + {0x8Du, 0x34u}, + {0x8Eu, 0x30u}, + {0x8Fu, 0x43u}, + {0x90u, 0x09u}, + {0x92u, 0x06u}, + {0x94u, 0x01u}, + {0x95u, 0x40u}, + {0x96u, 0x0Eu}, + {0x97u, 0x30u}, + {0x98u, 0x04u}, + {0x9Bu, 0x0Cu}, + {0x9Cu, 0x02u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x36u}, + {0xA3u, 0x82u}, + {0xA8u, 0x30u}, + {0xAAu, 0x06u}, + {0xAEu, 0x20u}, + {0xB0u, 0x0Fu}, + {0xB3u, 0x70u}, + {0xB4u, 0x20u}, + {0xB5u, 0x0Fu}, + {0xB6u, 0x10u}, + {0xB7u, 0x80u}, {0xB8u, 0x02u}, - {0xB9u, 0x80u}, - {0xBAu, 0x20u}, - {0xBBu, 0x02u}, - {0xBEu, 0x44u}, - {0xD4u, 0x40u}, + {0xBBu, 0x08u}, + {0xBEu, 0x50u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x24u}, + {0x01u, 0x41u}, + {0x04u, 0x08u}, + {0x06u, 0x02u}, + {0x0Au, 0x82u}, + {0x0Bu, 0x18u}, + {0x0Du, 0x08u}, + {0x0Eu, 0x0Au}, + {0x10u, 0x08u}, + {0x12u, 0x01u}, + {0x13u, 0x02u}, + {0x14u, 0x40u}, + {0x17u, 0x10u}, + {0x18u, 0x40u}, + {0x19u, 0x40u}, + {0x1Au, 0x81u}, + {0x1Bu, 0x10u}, + {0x1Eu, 0x0Au}, + {0x1Fu, 0x10u}, + {0x22u, 0x98u}, + {0x24u, 0x20u}, + {0x29u, 0x01u}, + {0x2Eu, 0x14u}, + {0x2Fu, 0x02u}, + {0x32u, 0x98u}, + {0x36u, 0x11u}, + {0x37u, 0x40u}, + {0x38u, 0x44u}, + {0x3Bu, 0x10u}, + {0x3Cu, 0x02u}, + {0x3Du, 0x08u}, + {0x3Eu, 0xA0u}, + {0x58u, 0x16u}, + {0x59u, 0x80u}, + {0x60u, 0xA8u}, + {0x63u, 0x02u}, + {0x69u, 0x80u}, + {0x6Au, 0x40u}, + {0x81u, 0x80u}, + {0x82u, 0x10u}, + {0x87u, 0x01u}, + {0x90u, 0x0Cu}, + {0x91u, 0x61u}, + {0x92u, 0x06u}, + {0x93u, 0x9Eu}, + {0x94u, 0x60u}, + {0x96u, 0xC0u}, + {0x98u, 0x52u}, + {0x99u, 0x21u}, + {0x9Au, 0x93u}, + {0x9Bu, 0x12u}, + {0x9Cu, 0xA8u}, + {0x9Du, 0x40u}, + {0xA0u, 0x98u}, + {0xA1u, 0x08u}, + {0xA2u, 0x10u}, + {0xA5u, 0x04u}, + {0xA6u, 0x0Au}, + {0xA7u, 0x01u}, + {0xA8u, 0x10u}, + {0xC0u, 0xAFu}, + {0xC2u, 0xEFu}, + {0xC4u, 0x5Bu}, + {0xCAu, 0x71u}, + {0xCCu, 0xBEu}, + {0xCEu, 0xFEu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, + {0xE2u, 0x04u}, + {0xEAu, 0x02u}, + {0xEEu, 0x08u}, + {0x02u, 0x07u}, + {0x04u, 0x04u}, + {0x06u, 0x08u}, + {0x09u, 0x01u}, + {0x0Bu, 0x12u}, + {0x0Du, 0x08u}, + {0x0Fu, 0x84u}, + {0x10u, 0x0Au}, + {0x12u, 0x05u}, + {0x14u, 0x09u}, + {0x16u, 0x02u}, + {0x1Du, 0x53u}, + {0x1Fu, 0xACu}, + {0x21u, 0x02u}, + {0x22u, 0x08u}, + {0x23u, 0x41u}, + {0x2Du, 0x04u}, + {0x2Fu, 0x28u}, + {0x30u, 0x0Fu}, + {0x31u, 0xC0u}, + {0x33u, 0x30u}, + {0x37u, 0x0Fu}, + {0x3Fu, 0x45u}, + {0x54u, 0x40u}, + {0x56u, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x01u}, + {0x5Fu, 0x01u}, + {0x81u, 0xFFu}, + {0x82u, 0x10u}, + {0x85u, 0x30u}, + {0x86u, 0x01u}, + {0x87u, 0xC0u}, + {0x8Cu, 0x80u}, + {0x8Du, 0x90u}, + {0x8Eu, 0x05u}, + {0x8Fu, 0x60u}, + {0x91u, 0x05u}, + {0x93u, 0x0Au}, + {0x94u, 0x06u}, + {0x95u, 0x50u}, + {0x96u, 0x80u}, + {0x97u, 0xA0u}, + {0x99u, 0x03u}, + {0x9Au, 0x08u}, + {0x9Bu, 0x0Cu}, + {0x9Du, 0x0Fu}, + {0x9Eu, 0x20u}, + {0x9Fu, 0xF0u}, + {0xA5u, 0x09u}, + {0xA6u, 0x40u}, + {0xA7u, 0x06u}, + {0xA9u, 0xFFu}, + {0xAAu, 0x83u}, + {0xACu, 0x28u}, + {0xAEu, 0x50u}, + {0xAFu, 0xFFu}, + {0xB0u, 0x80u}, + {0xB2u, 0x07u}, + {0xB4u, 0x60u}, + {0xB6u, 0x18u}, + {0xB7u, 0xFFu}, + {0xBEu, 0x51u}, + {0xBFu, 0x40u}, + {0xD4u, 0x09u}, {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, - {0x01u, 0x28u}, - {0x03u, 0x02u}, - {0x04u, 0x20u}, - {0x07u, 0x50u}, - {0x08u, 0x08u}, - {0x09u, 0x20u}, - {0x0Au, 0x61u}, - {0x0Du, 0x02u}, - {0x0Eu, 0x28u}, - {0x0Fu, 0x03u}, - {0x10u, 0x60u}, - {0x15u, 0x01u}, - {0x16u, 0x0Au}, - {0x17u, 0x05u}, - {0x1Au, 0x28u}, - {0x1Bu, 0x02u}, - {0x1Cu, 0x40u}, - {0x1Du, 0x16u}, - {0x1Eu, 0x0Au}, - {0x1Fu, 0x01u}, - {0x21u, 0x08u}, - {0x22u, 0x21u}, - {0x25u, 0x40u}, - {0x26u, 0x02u}, - {0x29u, 0x02u}, - {0x2Du, 0x01u}, - {0x2Fu, 0x01u}, - {0x30u, 0x08u}, - {0x36u, 0x02u}, - {0x37u, 0x54u}, - {0x3Au, 0x04u}, - {0x3Du, 0xA8u}, - {0x3Eu, 0x02u}, - {0x5Cu, 0x02u}, - {0x5Eu, 0x02u}, - {0x64u, 0x80u}, - {0x65u, 0x04u}, - {0x66u, 0x20u}, - {0x67u, 0x01u}, - {0x6Du, 0x40u}, - {0x6Fu, 0x28u}, - {0x80u, 0x80u}, - {0x8Au, 0x04u}, - {0x8Fu, 0x08u}, - {0x92u, 0x41u}, - {0x93u, 0x4Cu}, - {0x94u, 0x04u}, - {0x95u, 0x90u}, - {0x96u, 0x82u}, - {0x98u, 0x10u}, - {0x99u, 0x2Au}, - {0x9Au, 0x05u}, - {0x9Cu, 0x24u}, - {0x9Du, 0x41u}, - {0x9Fu, 0x28u}, - {0xA0u, 0x61u}, - {0xA2u, 0x80u}, - {0xA5u, 0x08u}, - {0xA6u, 0x20u}, - {0xA7u, 0x20u}, - {0xAAu, 0x04u}, - {0xB5u, 0x02u}, - {0xB7u, 0x48u}, - {0xC0u, 0x77u}, - {0xC2u, 0xFFu}, - {0xC4u, 0xFCu}, - {0xCAu, 0x91u}, - {0xCCu, 0xF2u}, - {0xCEu, 0xF2u}, - {0xD8u, 0xF0u}, - {0xE2u, 0x18u}, - {0xEAu, 0x01u}, - {0xEEu, 0x04u}, - {0x00u, 0xFFu}, - {0x04u, 0x50u}, - {0x05u, 0x05u}, - {0x06u, 0xA0u}, - {0x07u, 0x0Au}, - {0x08u, 0x30u}, - {0x09u, 0x06u}, - {0x0Au, 0xC0u}, - {0x0Bu, 0x09u}, - {0x0Cu, 0x90u}, - {0x0Du, 0x03u}, - {0x0Eu, 0x60u}, - {0x0Fu, 0x0Cu}, - {0x11u, 0xFFu}, - {0x14u, 0xFFu}, - {0x15u, 0x30u}, - {0x17u, 0xC0u}, - {0x18u, 0x05u}, - {0x1Au, 0x0Au}, - {0x1Bu, 0xFFu}, - {0x1Du, 0x60u}, - {0x1Fu, 0x90u}, - {0x20u, 0x03u}, - {0x21u, 0x0Fu}, - {0x22u, 0x0Cu}, - {0x23u, 0xF0u}, - {0x24u, 0x09u}, - {0x26u, 0x06u}, - {0x27u, 0xFFu}, - {0x29u, 0x50u}, - {0x2Au, 0xFFu}, - {0x2Bu, 0xA0u}, - {0x2Cu, 0x0Fu}, - {0x2Eu, 0xF0u}, - {0x36u, 0xFFu}, - {0x37u, 0xFFu}, - {0x3Eu, 0x40u}, - {0x3Fu, 0x40u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Fu, 0x01u}, - {0x81u, 0x09u}, - {0x83u, 0x24u}, - {0x84u, 0x09u}, - {0x86u, 0x12u}, - {0x87u, 0x46u}, - {0x8Bu, 0x08u}, - {0x8Du, 0x40u}, - {0x8Eu, 0x06u}, - {0x8Fu, 0x80u}, - {0x90u, 0x09u}, - {0x92u, 0x24u}, - {0x96u, 0x80u}, - {0x9Au, 0x70u}, - {0x9Bu, 0x30u}, - {0xA2u, 0x09u}, - {0xA3u, 0x01u}, - {0xA5u, 0x09u}, - {0xA6u, 0x01u}, - {0xA7u, 0x12u}, - {0xAAu, 0x08u}, - {0xABu, 0x09u}, - {0xACu, 0x40u}, - {0xAEu, 0x80u}, - {0xAFu, 0x80u}, - {0xB0u, 0x07u}, - {0xB1u, 0xC0u}, - {0xB2u, 0xC0u}, - {0xB3u, 0x07u}, - {0xB4u, 0x38u}, - {0xB5u, 0x38u}, - {0xBEu, 0x04u}, - {0xBFu, 0x01u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x99u}, - {0xDFu, 0x01u}, - {0x00u, 0x40u}, - {0x01u, 0x08u}, - {0x02u, 0x01u}, - {0x05u, 0x41u}, - {0x06u, 0x20u}, - {0x07u, 0x08u}, - {0x08u, 0x14u}, - {0x0Au, 0x44u}, - {0x0Eu, 0x20u}, - {0x0Fu, 0x04u}, - {0x11u, 0x46u}, - {0x13u, 0x10u}, - {0x15u, 0x88u}, - {0x16u, 0x88u}, - {0x18u, 0x60u}, - {0x1Au, 0x04u}, - {0x1Cu, 0x02u}, - {0x20u, 0x20u}, - {0x21u, 0x24u}, - {0x23u, 0x84u}, - {0x26u, 0x80u}, - {0x28u, 0x80u}, - {0x29u, 0x68u}, - {0x2Du, 0x10u}, - {0x2Eu, 0x28u}, - {0x2Fu, 0x60u}, - {0x31u, 0x20u}, - {0x34u, 0x20u}, - {0x35u, 0x41u}, - {0x36u, 0x10u}, - {0x37u, 0x08u}, - {0x39u, 0xCAu}, - {0x3Bu, 0xA8u}, - {0x3Cu, 0x60u}, - {0x3Eu, 0x80u}, - {0x3Fu, 0x04u}, - {0x59u, 0x04u}, - {0x5Au, 0x20u}, - {0x5Bu, 0x41u}, - {0x63u, 0x01u}, - {0x78u, 0x08u}, - {0x7Au, 0x20u}, - {0x83u, 0xA0u}, - {0x8Cu, 0x10u}, - {0x8Eu, 0x10u}, - {0x8Fu, 0x80u}, - {0x91u, 0x06u}, - {0x92u, 0x41u}, - {0x93u, 0x71u}, - {0x94u, 0x04u}, - {0x96u, 0x82u}, - {0x98u, 0x80u}, - {0x99u, 0x2Cu}, - {0x9Bu, 0x01u}, - {0x9Cu, 0x08u}, - {0x9Fu, 0x20u}, - {0xA0u, 0x60u}, - {0xA1u, 0x01u}, - {0xA3u, 0x88u}, - {0xA5u, 0x08u}, - {0xA7u, 0x20u}, - {0xABu, 0x02u}, - {0xAEu, 0x40u}, - {0xB4u, 0x40u}, - {0xB5u, 0x21u}, - {0xC0u, 0xF5u}, - {0xC2u, 0x6Eu}, - {0xC4u, 0xFFu}, - {0xCAu, 0xEFu}, - {0xCCu, 0xF4u}, - {0xCEu, 0x7Fu}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x08u}, - {0xE0u, 0x01u}, - {0xEAu, 0x0Cu}, - {0xEEu, 0x10u}, - {0x01u, 0x5Bu}, - {0x03u, 0x24u}, - {0x04u, 0x01u}, - {0x08u, 0x08u}, - {0x09u, 0x58u}, - {0x0Au, 0x12u}, - {0x0Bu, 0xA4u}, - {0x0Cu, 0x40u}, - {0x11u, 0x02u}, - {0x14u, 0x0Bu}, - {0x15u, 0x0Cu}, - {0x16u, 0x24u}, - {0x17u, 0x40u}, - {0x1Bu, 0x01u}, - {0x1Eu, 0x3Fu}, - {0x20u, 0x80u}, - {0x23u, 0x1Fu}, - {0x26u, 0x20u}, - {0x29u, 0x40u}, - {0x2Bu, 0xB7u}, - {0x2Cu, 0x34u}, - {0x2Du, 0x03u}, - {0x2Eu, 0x0Bu}, - {0x2Fu, 0x0Cu}, - {0x30u, 0x80u}, - {0x31u, 0x1Fu}, - {0x32u, 0x07u}, - {0x33u, 0x80u}, - {0x34u, 0x38u}, - {0x35u, 0x20u}, - {0x36u, 0x40u}, - {0x37u, 0x40u}, - {0x3Eu, 0x41u}, - {0x3Fu, 0x54u}, - {0x40u, 0x64u}, - {0x41u, 0x03u}, - {0x42u, 0x20u}, - {0x45u, 0xDCu}, - {0x46u, 0x2Fu}, - {0x47u, 0x0Eu}, - {0x48u, 0x1Fu}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Fu, 0x2Cu}, - {0x56u, 0x01u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Au, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x99u}, - {0x5Du, 0x09u}, - {0x5Fu, 0x01u}, - {0x62u, 0xC0u}, - {0x66u, 0x80u}, - {0x68u, 0x40u}, - {0x69u, 0x40u}, - {0x6Eu, 0x08u}, - {0x01u, 0x20u}, - {0x03u, 0x22u}, - {0x0Au, 0x10u}, - {0x0Bu, 0x02u}, - {0x11u, 0x01u}, - {0x12u, 0x22u}, - {0x18u, 0x60u}, - {0x19u, 0x78u}, - {0x1Au, 0x10u}, - {0x21u, 0x11u}, - {0x22u, 0x06u}, - {0x23u, 0x01u}, - {0x29u, 0x12u}, - {0x2Au, 0x40u}, - {0x31u, 0x05u}, - {0x33u, 0x21u}, - {0x38u, 0x20u}, - {0x39u, 0x02u}, - {0x41u, 0x11u}, - {0x42u, 0x50u}, - {0x49u, 0x15u}, - {0x50u, 0x48u}, - {0x52u, 0x20u}, - {0x53u, 0x88u}, - {0x58u, 0x08u}, - {0x5Au, 0x82u}, - {0x5Bu, 0x20u}, - {0x5Cu, 0x80u}, - {0x5Du, 0x40u}, - {0x60u, 0x44u}, - {0x61u, 0x48u}, - {0x68u, 0x40u}, - {0x69u, 0x44u}, - {0x6Au, 0x20u}, - {0x70u, 0x20u}, - {0x72u, 0x01u}, - {0x73u, 0x50u}, - {0x7Eu, 0x10u}, - {0x7Fu, 0x10u}, - {0x80u, 0x08u}, - {0x89u, 0x01u}, - {0x8Au, 0x04u}, - {0x8Du, 0x02u}, - {0x8Fu, 0x01u}, - {0xC0u, 0x07u}, - {0xC2u, 0x05u}, - {0xC4u, 0x0Du}, - {0xCAu, 0x0Du}, - {0xCCu, 0x07u}, - {0xCEu, 0x05u}, - {0xD0u, 0x07u}, - {0xD2u, 0x04u}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x0Fu}, - {0xE0u, 0x40u}, - {0xE2u, 0x80u}, - {0xE6u, 0x01u}, - {0xECu, 0x40u}, - {0xEEu, 0x02u}, - {0xE2u, 0x20u}, - {0xEEu, 0x08u}, - {0x00u, 0xC0u}, - {0x01u, 0x64u}, - {0x02u, 0x02u}, - {0x06u, 0x9Fu}, - {0x07u, 0xF5u}, - {0x08u, 0x80u}, - {0x09u, 0x07u}, - {0x0Bu, 0x90u}, - {0x0Cu, 0xC0u}, - {0x0Du, 0x83u}, - {0x0Eu, 0x01u}, - {0x0Fu, 0x70u}, - {0x11u, 0x64u}, - {0x12u, 0xFFu}, - {0x14u, 0x1Fu}, - {0x16u, 0x20u}, - {0x17u, 0x64u}, - {0x18u, 0x7Fu}, - {0x19u, 0x24u}, - {0x1Au, 0x80u}, - {0x1Du, 0x64u}, - {0x1Eu, 0x60u}, - {0x20u, 0x90u}, - {0x21u, 0x08u}, - {0x22u, 0x40u}, - {0x24u, 0xC0u}, - {0x25u, 0x24u}, - {0x26u, 0x08u}, - {0x27u, 0x40u}, - {0x28u, 0xC0u}, - {0x29u, 0x40u}, - {0x2Au, 0x04u}, - {0x2Bu, 0x02u}, - {0x2Du, 0x08u}, - {0x30u, 0xFFu}, - {0x31u, 0x80u}, - {0x33u, 0x07u}, - {0x35u, 0x71u}, - {0x37u, 0x08u}, - {0x39u, 0x80u}, - {0x3Bu, 0x0Cu}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x01u}, - {0x54u, 0x09u}, - {0x56u, 0x04u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Fu, 0x01u}, - {0x86u, 0x01u}, - {0x90u, 0x04u}, - {0x92u, 0x43u}, - {0x94u, 0x88u}, - {0x95u, 0x50u}, - {0x96u, 0x03u}, - {0x97u, 0xA0u}, - {0x99u, 0x60u}, - {0x9Au, 0xECu}, - {0x9Bu, 0x90u}, - {0x9Cu, 0xE0u}, - {0x9Du, 0x0Fu}, - {0x9Fu, 0xF0u}, - {0xA1u, 0x03u}, - {0xA3u, 0x0Cu}, - {0xA5u, 0x05u}, - {0xA6u, 0x12u}, - {0xA7u, 0x0Au}, - {0xA8u, 0x21u}, - {0xA9u, 0x06u}, - {0xAAu, 0x02u}, - {0xABu, 0x09u}, - {0xADu, 0x30u}, - {0xAFu, 0xC0u}, - {0xB2u, 0x10u}, - {0xB3u, 0xFFu}, - {0xB4u, 0x0Fu}, - {0xB6u, 0xE0u}, - {0xBEu, 0x40u}, - {0xBFu, 0x04u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDFu, 0x01u}, - {0x01u, 0x08u}, - {0x05u, 0x10u}, - {0x06u, 0x12u}, - {0x07u, 0x40u}, - {0x09u, 0x46u}, - {0x0Au, 0x04u}, - {0x0Du, 0x82u}, - {0x0Eu, 0x28u}, - {0x11u, 0x20u}, - {0x12u, 0x10u}, - {0x16u, 0x08u}, - {0x17u, 0x15u}, - {0x19u, 0x08u}, - {0x1Au, 0x06u}, - {0x1Eu, 0x40u}, - {0x22u, 0x08u}, - {0x24u, 0x20u}, - {0x25u, 0x94u}, - {0x26u, 0x14u}, - {0x27u, 0x88u}, - {0x28u, 0x18u}, - {0x29u, 0x02u}, - {0x2Au, 0x80u}, - {0x2Du, 0x20u}, - {0x2Eu, 0x48u}, - {0x2Fu, 0x88u}, - {0x31u, 0x28u}, - {0x32u, 0x40u}, - {0x35u, 0x10u}, - {0x37u, 0x45u}, - {0x3Cu, 0x40u}, - {0x3Du, 0x28u}, - {0x3Eu, 0x02u}, - {0x5Du, 0x24u}, - {0x5Eu, 0x02u}, - {0x5Fu, 0x80u}, - {0x67u, 0x42u}, - {0x69u, 0x80u}, - {0x6Au, 0x80u}, - {0x78u, 0x20u}, - {0x7Au, 0x08u}, - {0x8Bu, 0x40u}, - {0x8Cu, 0x04u}, - {0x90u, 0x40u}, - {0x91u, 0x04u}, - {0x92u, 0x08u}, - {0x93u, 0x0Eu}, - {0x94u, 0x28u}, - {0x95u, 0x99u}, - {0x98u, 0x19u}, - {0x99u, 0x12u}, - {0x9Au, 0x12u}, - {0x9Bu, 0x55u}, - {0x9Cu, 0x20u}, - {0x9Du, 0xC1u}, - {0xA1u, 0x42u}, - {0xA2u, 0x01u}, - {0xA3u, 0x3Au}, - {0xA4u, 0x10u}, - {0xA5u, 0x3Cu}, - {0xA6u, 0x12u}, - {0xA8u, 0x01u}, - {0xC0u, 0xF4u}, - {0xC2u, 0xFFu}, - {0xC4u, 0x76u}, - {0xCAu, 0xFFu}, - {0xCCu, 0xFEu}, - {0xCEu, 0xF0u}, - {0xD6u, 0xF0u}, - {0xD8u, 0x90u}, - {0xE2u, 0x20u}, - {0xEEu, 0x0Cu}, - {0x02u, 0x40u}, - {0x05u, 0x30u}, - {0x07u, 0xC0u}, - {0x09u, 0x50u}, - {0x0Bu, 0xA0u}, - {0x0Cu, 0x01u}, - {0x0Eu, 0x12u}, - {0x10u, 0x53u}, - {0x12u, 0xACu}, - {0x13u, 0xFFu}, - {0x15u, 0xFFu}, - {0x18u, 0x02u}, - {0x1Au, 0x01u}, - {0x1Bu, 0xFFu}, - {0x1Cu, 0x08u}, - {0x1Du, 0x0Fu}, - {0x1Eu, 0x04u}, - {0x1Fu, 0xF0u}, - {0x20u, 0x04u}, - {0x21u, 0x60u}, - {0x22u, 0x28u}, - {0x23u, 0x90u}, - {0x25u, 0x05u}, - {0x27u, 0x0Au}, - {0x29u, 0x06u}, - {0x2Bu, 0x09u}, - {0x2Du, 0x03u}, - {0x2Eu, 0x80u}, - {0x2Fu, 0x0Cu}, - {0x30u, 0x0Fu}, - {0x32u, 0x30u}, - {0x33u, 0xFFu}, - {0x34u, 0xC0u}, - {0x3Eu, 0x15u}, - {0x3Fu, 0x04u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Fu, 0x01u}, - {0x80u, 0x01u}, - {0x85u, 0x05u}, - {0x86u, 0x40u}, - {0x87u, 0x0Au}, - {0x88u, 0x01u}, - {0x89u, 0x50u}, - {0x8Bu, 0xA0u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x0Fu}, - {0x8Fu, 0xF0u}, - {0x90u, 0x08u}, - {0x92u, 0x61u}, - {0x93u, 0xFFu}, - {0x94u, 0x10u}, - {0x97u, 0xFFu}, - {0x98u, 0xA2u}, - {0x99u, 0x30u}, - {0x9Au, 0x08u}, - {0x9Bu, 0xC0u}, - {0x9Cu, 0x04u}, - {0xA0u, 0x01u}, - {0xA1u, 0x90u}, - {0xA3u, 0x60u}, - {0xA4u, 0x07u}, - {0xA6u, 0xD8u}, - {0xA7u, 0xFFu}, - {0xA8u, 0x01u}, - {0xA9u, 0x09u}, - {0xABu, 0x06u}, - {0xADu, 0x03u}, - {0xAFu, 0x0Cu}, - {0xB1u, 0xFFu}, - {0xB2u, 0xE0u}, - {0xB6u, 0x3Fu}, - {0xB8u, 0x80u}, - {0xBEu, 0x40u}, - {0xBFu, 0x01u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDFu, 0x01u}, {0x01u, 0x02u}, - {0x03u, 0x02u}, - {0x05u, 0x14u}, - {0x06u, 0x02u}, - {0x07u, 0x40u}, - {0x0Au, 0xCAu}, - {0x0Du, 0x82u}, - {0x0Eu, 0x08u}, - {0x0Fu, 0x20u}, - {0x13u, 0x42u}, - {0x17u, 0x19u}, - {0x18u, 0x04u}, - {0x19u, 0x01u}, - {0x1Au, 0x10u}, + {0x03u, 0x10u}, + {0x04u, 0x42u}, + {0x05u, 0x04u}, + {0x09u, 0x08u}, + {0x0Bu, 0x80u}, + {0x0Eu, 0x06u}, + {0x0Fu, 0x10u}, + {0x10u, 0x80u}, + {0x15u, 0xA0u}, + {0x16u, 0x20u}, + {0x17u, 0x44u}, + {0x19u, 0x02u}, + {0x1Cu, 0x01u}, {0x1Du, 0x04u}, - {0x1Fu, 0x80u}, - {0x20u, 0x20u}, - {0x26u, 0x02u}, - {0x28u, 0x41u}, - {0x29u, 0x20u}, - {0x2Au, 0x08u}, - {0x2Cu, 0x41u}, - {0x2Du, 0x20u}, - {0x2Fu, 0x64u}, - {0x31u, 0x01u}, - {0x32u, 0x48u}, - {0x33u, 0x20u}, - {0x35u, 0x01u}, - {0x36u, 0x08u}, - {0x37u, 0x20u}, - {0x39u, 0x18u}, - {0x3Du, 0x10u}, - {0x3Eu, 0x48u}, - {0x3Fu, 0x04u}, - {0x48u, 0x01u}, - {0x49u, 0x40u}, - {0x4Bu, 0x80u}, - {0x68u, 0x01u}, - {0x69u, 0x19u}, - {0x6Au, 0x02u}, - {0x6Bu, 0x20u}, - {0x71u, 0x28u}, - {0x72u, 0x80u}, - {0x73u, 0x42u}, - {0x81u, 0x04u}, - {0x82u, 0x10u}, - {0x8Cu, 0x04u}, - {0x92u, 0x88u}, - {0x93u, 0x0Cu}, - {0x94u, 0x0Cu}, - {0x95u, 0x19u}, - {0x98u, 0x01u}, - {0x99u, 0x12u}, - {0x9Au, 0x02u}, - {0x9Bu, 0x59u}, - {0x9Du, 0x41u}, - {0x9Eu, 0x80u}, - {0xA1u, 0x82u}, - {0xA2u, 0x0Cu}, - {0xA3u, 0x32u}, - {0xA4u, 0x10u}, - {0xA5u, 0x28u}, + {0x1Eu, 0x48u}, + {0x20u, 0x82u}, + {0x22u, 0x04u}, + {0x27u, 0x01u}, + {0x29u, 0x42u}, + {0x2Eu, 0x94u}, + {0x33u, 0x40u}, + {0x36u, 0x11u}, + {0x37u, 0x44u}, + {0x38u, 0x80u}, + {0x3Bu, 0x20u}, + {0x3Cu, 0x02u}, + {0x3Du, 0x88u}, + {0x44u, 0x02u}, + {0x46u, 0x01u}, + {0x5Du, 0x20u}, + {0x5Eu, 0x41u}, + {0x5Fu, 0x04u}, + {0x60u, 0x02u}, + {0x62u, 0x12u}, + {0x63u, 0x20u}, + {0x65u, 0x01u}, + {0x67u, 0x02u}, + {0x6Cu, 0x41u}, + {0x6Du, 0x88u}, + {0x6Fu, 0x06u}, + {0x74u, 0x08u}, + {0x75u, 0x40u}, + {0x77u, 0x88u}, + {0x80u, 0x01u}, + {0x81u, 0x05u}, + {0x82u, 0x04u}, + {0x86u, 0x04u}, + {0x87u, 0x80u}, + {0x88u, 0x08u}, + {0x90u, 0x40u}, + {0x91u, 0xA0u}, + {0x92u, 0x15u}, + {0x93u, 0xB6u}, + {0x94u, 0x02u}, + {0x99u, 0x20u}, + {0x9Au, 0x91u}, + {0x9Bu, 0x10u}, + {0x9Eu, 0x20u}, + {0x9Fu, 0x49u}, + {0xA0u, 0x80u}, + {0xA1u, 0x08u}, + {0xA2u, 0x11u}, + {0xA3u, 0x10u}, + {0xA4u, 0x41u}, + {0xA5u, 0x04u}, {0xA6u, 0x02u}, - {0xA7u, 0x80u}, - {0xAEu, 0x01u}, - {0xB5u, 0x80u}, - {0xC0u, 0xF9u}, - {0xC2u, 0xFBu}, - {0xC4u, 0x79u}, - {0xCAu, 0xFFu}, - {0xCCu, 0xEFu}, - {0xCEu, 0x76u}, + {0xA7u, 0x02u}, + {0xAAu, 0x11u}, + {0xACu, 0x04u}, + {0xB0u, 0x41u}, + {0xB2u, 0x20u}, + {0xB4u, 0x01u}, + {0xB7u, 0x08u}, + {0xC0u, 0xBCu}, + {0xC2u, 0xECu}, + {0xC4u, 0xE8u}, + {0xCAu, 0x79u}, + {0xCCu, 0xF8u}, + {0xCEu, 0xDCu}, + {0xD6u, 0xF0u}, + {0xD8u, 0x9Fu}, {0xE0u, 0x01u}, - {0xECu, 0x40u}, - {0x0Eu, 0x08u}, + {0xE4u, 0x0Cu}, + {0xE6u, 0x20u}, + {0xEAu, 0xC8u}, + {0xEEu, 0xC0u}, + {0x0Fu, 0x08u}, {0x12u, 0x08u}, {0x15u, 0x80u}, {0x17u, 0x04u}, {0x33u, 0x04u}, {0x36u, 0x88u}, - {0x39u, 0x80u}, - {0x3Bu, 0x01u}, - {0x3Eu, 0x88u}, - {0x41u, 0x80u}, - {0x60u, 0x20u}, - {0x83u, 0x01u}, - {0x8Bu, 0x20u}, - {0x8Eu, 0x04u}, + {0x39u, 0x81u}, + {0x3Cu, 0x01u}, + {0x3Du, 0x20u}, + {0x40u, 0x04u}, + {0x62u, 0x02u}, + {0x83u, 0x04u}, + {0x86u, 0x08u}, + {0x8Au, 0x02u}, {0xC2u, 0x80u}, {0xC4u, 0xE0u}, {0xCCu, 0xE0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, {0xD8u, 0x40u}, - {0xE2u, 0x80u}, - {0x32u, 0x04u}, - {0x33u, 0x80u}, + {0xE4u, 0x20u}, + {0xE6u, 0x40u}, + {0x33u, 0x81u}, {0x35u, 0x80u}, - {0x39u, 0x40u}, - {0x53u, 0x20u}, - {0x59u, 0x10u}, - {0x5Cu, 0x02u}, - {0x81u, 0x10u}, - {0x8Fu, 0x02u}, - {0x9Cu, 0x20u}, - {0x9Eu, 0x08u}, - {0xA3u, 0x20u}, - {0xA5u, 0x80u}, + {0x3Au, 0x10u}, + {0x50u, 0x08u}, + {0x56u, 0x08u}, + {0x63u, 0x20u}, + {0x85u, 0x01u}, + {0x88u, 0x08u}, + {0x8Du, 0x10u}, + {0x8Fu, 0x10u}, + {0x94u, 0x05u}, + {0x95u, 0x01u}, + {0x9Au, 0x08u}, + {0xA5u, 0x10u}, {0xA6u, 0x80u}, - {0xB6u, 0x80u}, {0xCCu, 0x70u}, {0xCEu, 0x10u}, - {0xD4u, 0xA0u}, - {0xD6u, 0x80u}, - {0xE6u, 0x20u}, + {0xD4u, 0x60u}, + {0xD8u, 0x40u}, + {0xE2u, 0x10u}, {0x12u, 0x80u}, - {0x5Bu, 0x02u}, - {0x82u, 0x08u}, + {0x5Bu, 0x08u}, {0x85u, 0x80u}, - {0x8Cu, 0x02u}, - {0x96u, 0x08u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x22u}, + {0x8Au, 0x10u}, + {0x8Cu, 0x01u}, + {0x94u, 0x05u}, {0x9Du, 0x80u}, - {0x9Eu, 0x08u}, - {0xA5u, 0x80u}, + {0x9Eu, 0x10u}, + {0x9Fu, 0x01u}, + {0xA2u, 0x10u}, {0xA6u, 0x80u}, {0xA7u, 0x80u}, - {0xA9u, 0x40u}, + {0xAEu, 0x10u}, {0xC4u, 0x10u}, {0xD6u, 0x40u}, {0xE2u, 0x10u}, - {0xE6u, 0x80u}, - {0xEEu, 0x20u}, - {0xA5u, 0x80u}, - {0xA7u, 0x80u}, - {0xAEu, 0x04u}, - {0xB4u, 0x20u}, {0xEEu, 0x10u}, - {0x00u, 0x20u}, - {0x09u, 0x40u}, - {0x0Fu, 0x08u}, - {0x12u, 0x80u}, - {0x17u, 0x08u}, - {0x5Bu, 0x02u}, - {0x66u, 0x40u}, - {0x8Bu, 0x40u}, + {0x8Au, 0x20u}, + {0x94u, 0x04u}, + {0x9Fu, 0x01u}, + {0xA2u, 0x10u}, + {0xA7u, 0x80u}, + {0xB3u, 0x08u}, + {0x01u, 0x20u}, + {0x08u, 0x20u}, + {0x0Eu, 0x01u}, + {0x13u, 0x02u}, + {0x14u, 0x80u}, + {0x58u, 0x01u}, + {0x60u, 0x10u}, + {0x8Au, 0x01u}, + {0x8Cu, 0x20u}, + {0x8Du, 0x20u}, {0xC0u, 0x02u}, {0xC2u, 0x03u}, {0xC4u, 0x0Cu}, - {0xD6u, 0x03u}, - {0xE6u, 0x01u}, - {0x0Bu, 0x80u}, - {0x0Du, 0x08u}, - {0x53u, 0x02u}, - {0x57u, 0x40u}, - {0x61u, 0x40u}, - {0x62u, 0x04u}, - {0x81u, 0x10u}, - {0x8Fu, 0x02u}, - {0x97u, 0x80u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x02u}, - {0xA1u, 0x40u}, - {0xA2u, 0x80u}, - {0xA3u, 0x04u}, - {0xABu, 0x08u}, - {0xACu, 0x10u}, - {0xC2u, 0x0Cu}, - {0xD4u, 0x03u}, {0xD6u, 0x02u}, {0xD8u, 0x02u}, - {0xE4u, 0x02u}, - {0x57u, 0x08u}, - {0x87u, 0x10u}, - {0x89u, 0x40u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x44u}, - {0x9Fu, 0x02u}, - {0xA1u, 0x50u}, - {0xA2u, 0x80u}, - {0xA6u, 0x04u}, - {0xA7u, 0x40u}, - {0xA9u, 0x08u}, - {0xAAu, 0x04u}, - {0xB7u, 0x04u}, - {0xD4u, 0x02u}, + {0xE2u, 0x0Au}, + {0xE6u, 0x01u}, + {0x04u, 0x04u}, + {0x0Au, 0x20u}, + {0x0Du, 0x01u}, + {0x52u, 0x02u}, + {0x56u, 0x80u}, + {0x63u, 0x02u}, + {0x65u, 0x40u}, + {0x82u, 0x98u}, + {0x8Bu, 0x01u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0x01u}, + {0xA8u, 0x80u}, + {0xB4u, 0x10u}, + {0xC0u, 0x04u}, + {0xC2u, 0x0Cu}, + {0xD4u, 0x03u}, + {0xD6u, 0x03u}, {0xE0u, 0x01u}, - {0xEAu, 0x02u}, - {0x08u, 0x08u}, - {0x0Bu, 0x08u}, - {0x0Eu, 0x08u}, - {0x0Fu, 0x10u}, - {0x82u, 0x02u}, - {0x87u, 0x02u}, - {0x89u, 0x10u}, - {0x8Au, 0x40u}, - {0x97u, 0x18u}, - {0x9Eu, 0x44u}, - {0x9Fu, 0x02u}, - {0xA1u, 0x10u}, - {0xA2u, 0x80u}, - {0xA6u, 0x04u}, - {0xA7u, 0x40u}, - {0xAFu, 0x04u}, - {0xB1u, 0x40u}, - {0xB7u, 0x08u}, - {0xC2u, 0x0Fu}, - {0xE2u, 0x01u}, - {0xE4u, 0x01u}, {0xE8u, 0x08u}, - {0xEEu, 0x04u}, - {0x89u, 0x80u}, - {0xA5u, 0x80u}, - {0xAFu, 0x80u}, + {0x54u, 0x10u}, + {0x87u, 0x10u}, + {0x8Au, 0x04u}, + {0x90u, 0x04u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x40u}, + {0x9Eu, 0x08u}, + {0xA0u, 0x10u}, + {0xAAu, 0x02u}, + {0xB0u, 0x10u}, + {0xB1u, 0x01u}, + {0xB7u, 0x02u}, + {0xD4u, 0x02u}, + {0xE6u, 0x04u}, + {0xEAu, 0x0Cu}, + {0xECu, 0x01u}, + {0x08u, 0x08u}, + {0x0Bu, 0x04u}, + {0x0Eu, 0x04u}, + {0x0Fu, 0x10u}, + {0x90u, 0x04u}, + {0x96u, 0x04u}, + {0x97u, 0x10u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x40u}, + {0x9Eu, 0x08u}, + {0xC2u, 0x0Fu}, + {0x94u, 0x04u}, + {0x9Eu, 0x20u}, + {0xA2u, 0x10u}, + {0xAFu, 0x81u}, + {0xEAu, 0x40u}, {0xEEu, 0x10u}, {0x06u, 0x20u}, - {0x57u, 0x08u}, - {0x5Fu, 0x40u}, - {0x83u, 0x08u}, - {0x93u, 0x40u}, + {0x5Bu, 0x40u}, + {0x5Eu, 0x20u}, + {0x80u, 0x04u}, + {0x83u, 0x40u}, + {0x94u, 0x04u}, {0x9Eu, 0x20u}, - {0xAFu, 0x40u}, - {0xB6u, 0x20u}, + {0xA2u, 0x10u}, {0xC0u, 0x20u}, - {0xD4u, 0x40u}, + {0xD4u, 0x80u}, {0xD6u, 0x20u}, + {0xE2u, 0x20u}, {0xE6u, 0x80u}, - {0xEEu, 0x40u}, - {0x8Fu, 0x40u}, - {0x95u, 0x10u}, - {0x9Au, 0x02u}, - {0x9Eu, 0x04u}, - {0xA1u, 0x10u}, - {0xA7u, 0x40u}, - {0xAAu, 0x80u}, + {0x80u, 0x04u}, + {0x90u, 0x04u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x40u}, + {0x9Eu, 0x08u}, {0xACu, 0x08u}, - {0xE4u, 0x02u}, - {0x01u, 0x10u}, - {0x04u, 0x10u}, - {0x55u, 0x10u}, - {0x56u, 0x02u}, - {0x82u, 0x04u}, - {0x8Cu, 0x10u}, - {0x95u, 0x10u}, - {0x9Au, 0x02u}, - {0x9Eu, 0x04u}, - {0xA1u, 0x10u}, + {0xAFu, 0x04u}, + {0x00u, 0x20u}, + {0x06u, 0x08u}, + {0x53u, 0x80u}, + {0x56u, 0x80u}, + {0x82u, 0x80u}, + {0x83u, 0x80u}, + {0x85u, 0x40u}, + {0x9Du, 0x40u}, + {0x9Eu, 0x08u}, + {0xA4u, 0x10u}, + {0xACu, 0x10u}, + {0xB0u, 0x01u}, {0xC0u, 0x03u}, - {0xD4u, 0x02u}, - {0xD6u, 0x04u}, - {0xE2u, 0x08u}, - {0x00u, 0x01u}, - {0x01u, 0x01u}, - {0x0Cu, 0x01u}, - {0x0Du, 0x01u}, - {0x0Fu, 0x01u}, - {0x10u, 0x01u}, - {0x1Cu, 0x01u}, + {0xD4u, 0x06u}, + {0xECu, 0x04u}, + {0x10u, 0x03u}, + {0x11u, 0x01u}, + {0x1Cu, 0x03u}, + {0x1Du, 0x01u}, {0x00u, 0xFDu}, {0x01u, 0xABu}, {0x02u, 0x08u}, @@ -1546,15 +1831,44 @@ void cyfitter_cfg(void) uint16 size; } CYPACKED_ATTR cfg_memset_t; + + CYPACKED typedef struct { + void CYFAR *dest; + const void CYCODE *src; + uint16 size; + } CYPACKED_ATTR cfg_memcpy_t; + static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT1_DR), 16u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 2176u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P4_ROUTE_BASE), 1792u}, {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, - {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, + {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, + }; + + /* UDB_0_2_0_CONFIG Address: CYDEV_UCFG_B0_P4_U1_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_0_2_0_CONFIG_VAL[] = { + 0x01u, 0x74u, 0x00u, 0x00u, 0x00u, 0x54u, 0x00u, 0x20u, 0x01u, 0x40u, 0x00u, 0x34u, 0x10u, 0x34u, 0x00u, 0x40u, + 0x08u, 0x94u, 0x21u, 0x40u, 0x07u, 0xC0u, 0x18u, 0x3Du, 0x22u, 0x47u, 0x08u, 0x88u, 0x01u, 0x83u, 0x00u, 0x78u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x00u, 0x02u, 0x01u, 0x74u, 0x00u, 0x00u, + 0x3Fu, 0xC0u, 0x00u, 0x07u, 0x00u, 0x39u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x0Eu, 0x00u, 0x00u, 0x01u, 0x00u, + 0x46u, 0x02u, 0x50u, 0x00u, 0x03u, 0xBEu, 0xF0u, 0xDCu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x28u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, + 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ + static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { + 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x00u, 0x03u, 0x00u, 0x03u, 0x01u}; + + static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { + /* dest, src, size */ + {(void CYFAR *)(CYDEV_UCFG_B0_P4_U1_BASE), BS_UDB_0_2_0_CONFIG_VAL, 128u}, + {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; uint8 CYDATA i; @@ -1566,6 +1880,16 @@ void cyfitter_cfg(void) CYMEMZERO(ms->address, (uint32)(ms->size)); } + /* Copy device configuration data into registers */ + for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) + { + const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; + void * CYDATA destPtr = mc->dest; + const void CYCODE * CYDATA srcPtr = mc->src; + uint16 CYDATA numBytes = mc->size; + CYCONFIGCPYCODE(destPtr, srcPtr, numBytes); + } + cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 1394c44..7655563 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -71,6 +71,20 @@ .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* SCSI_Parity_Error */ +.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK +.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST + /* USBFS_bus_reset */ .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 @@ -84,41 +98,32 @@ /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL /* SCSI_Out_Bits */ .set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB10_11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB10_11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB10_11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB10_11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB10_11_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB10_11_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB10_11_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB10_11_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 @@ -133,15 +138,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB10_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB10_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB10_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL /* USBFS_arb_int */ .set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -630,34 +635,34 @@ .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB08_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB08_ST -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB08_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB08_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB08_MSK -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB09_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB09_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB09_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB09_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB09_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB09_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB09_MSK +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -665,17 +670,11 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB11_MSK -.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB11_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB10_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB10_ST .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 @@ -685,28 +684,32 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB08_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB08_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB08_09_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB08_09_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB08_09_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB08_09_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB08_09_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB08_09_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB08_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB08_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB08_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB08_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB08_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB08_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB08_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB08_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB08_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB08_F1 -.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB11_MSK +.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB11_ST_CTL +.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB11_ST_CTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB11_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB09_10_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB09_10_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB09_10_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB09_10_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB09_10_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB09_10_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB09_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB09_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB09_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB09_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB09_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB09_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB09_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB09_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB09_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB09_F1 +.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL /* USBFS_dp_int */ .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -1184,21 +1187,21 @@ .set SD_Data_Clk__PM_STBY_MSK, 0x01 /* timer_clock */ -.set timer_clock__CFG0, CYREG_CLKDIST_DCFG1_CFG0 -.set timer_clock__CFG1, CYREG_CLKDIST_DCFG1_CFG1 -.set timer_clock__CFG2, CYREG_CLKDIST_DCFG1_CFG2 +.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0 +.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1 +.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2 .set timer_clock__CFG2_SRC_SEL_MASK, 0x07 -.set timer_clock__INDEX, 0x01 +.set timer_clock__INDEX, 0x02 .set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set timer_clock__PM_ACT_MSK, 0x02 +.set timer_clock__PM_ACT_MSK, 0x04 .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set timer_clock__PM_STBY_MSK, 0x02 +.set timer_clock__PM_STBY_MSK, 0x04 /* scsiTarget */ .set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__POS, 0 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 .set scsiTarget_StatusReg__2__MASK, 0x04 @@ -1208,54 +1211,54 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB13_MSK -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB13_ST -.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL -.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST -.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB14_MSK -.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL -.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL -.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL -.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB14_ST_CTL -.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB14_ST_CTL -.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB14_ST -.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL -.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK -.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK -.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL -.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB14_CTL -.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL -.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB14_CTL -.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL -.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL -.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB14_MSK -.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL -.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB14_15_A0 -.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB14_15_A1 -.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB14_15_D0 -.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB14_15_D1 -.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL -.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB14_15_F0 -.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB14_15_F1 -.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB14_A0_A1 -.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB14_A0 -.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB14_A1 -.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB14_D0_D1 -.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB14_D0 -.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB14_D1 -.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB14_ACTL -.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB14_F0_F1 -.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB14_F0 -.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB14_F1 -.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL -.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST +.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST +.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB11_MSK +.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL +.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL +.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB11_ST +.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK +.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB11_CTL +.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL +.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB11_CTL +.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL +.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB11_MSK +.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB11_12_A0 +.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB11_12_A1 +.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB11_12_D0 +.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB11_12_D1 +.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB11_12_F0 +.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB11_12_F1 +.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB11_A0_A1 +.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB11_A0 +.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB11_A1 +.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB11_D0_D1 +.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB11_D0 +.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB11_D1 +.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB11_F0_F1 +.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB11_F0 +.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB11_F1 +.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL /* USBFS_ep_0 */ .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -1493,6 +1496,17 @@ .set SCSI_ATN__SHIFT, 0 .set SCSI_ATN__SLW, CYREG_PRT2_SLW +/* SCSI_CLK */ +.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 +.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 +.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2 +.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07 +.set SCSI_CLK__INDEX, 0x01 +.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SCSI_CLK__PM_ACT_MSK, 0x02 +.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SCSI_CLK__PM_STBY_MSK, 0x02 + /* SCSI_Out */ .set SCSI_Out__0__AG, CYREG_PRT15_AG .set SCSI_Out__0__AMUX, CYREG_PRT15_AMUX diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 735ac61..02f5ce9 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -71,6 +71,20 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* SCSI_Parity_Error */ +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK +SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST + /* USBFS_bus_reset */ USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 @@ -84,41 +98,32 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL /* SCSI_Out_Bits */ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 @@ -133,15 +138,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL /* USBFS_arb_int */ USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -630,34 +635,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB09_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB09_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB09_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB09_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB09_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB09_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB09_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -665,17 +670,11 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -685,28 +684,32 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB08_09_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB08_09_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB08_09_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB08_09_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB08_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB08_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB08_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB08_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB08_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB08_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB08_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB08_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK +SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL /* USBFS_dp_int */ USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1184,21 +1187,21 @@ SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 SD_Data_Clk__PM_STBY_MSK EQU 0x01 /* timer_clock */ -timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 +timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 +timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2 timer_clock__CFG2_SRC_SEL_MASK EQU 0x07 -timer_clock__INDEX EQU 0x01 +timer_clock__INDEX EQU 0x02 timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -timer_clock__PM_ACT_MSK EQU 0x02 +timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -timer_clock__PM_STBY_MSK EQU 0x02 +timer_clock__PM_STBY_MSK EQU 0x04 /* scsiTarget */ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1208,54 +1211,54 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB14_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB14_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB14_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB14_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB14_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB14_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB14_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB14_15_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB14_15_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB14_15_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB14_15_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB14_15_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB14_15_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB14_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB14_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB14_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB14_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB14_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB14_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB14_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB14_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB14_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL /* USBFS_ep_0 */ USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1493,6 +1496,17 @@ SCSI_ATN__PS EQU CYREG_PRT2_PS SCSI_ATN__SHIFT EQU 0 SCSI_ATN__SLW EQU CYREG_PRT2_SLW +/* SCSI_CLK */ +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 + /* SCSI_Out */ SCSI_Out__0__AG EQU CYREG_PRT15_AG SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 8bb4857..a831aed 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -71,6 +71,20 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; SCSI_Parity_Error +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK +SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST + ; USBFS_bus_reset USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 @@ -84,41 +98,32 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL ; SCSI_Out_Bits SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 @@ -133,15 +138,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL ; USBFS_arb_int USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -630,34 +635,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SDCard_BSPIM -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB09_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB09_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB09_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB09_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB09_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB09_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB09_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -665,17 +670,11 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -685,28 +684,32 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB08_09_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB08_09_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB08_09_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB08_09_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB08_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB08_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB08_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB08_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB08_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB08_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB08_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB08_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK +SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL ; USBFS_dp_int USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1184,21 +1187,21 @@ SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 SD_Data_Clk__PM_STBY_MSK EQU 0x01 ; timer_clock -timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 +timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 +timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2 timer_clock__CFG2_SRC_SEL_MASK EQU 0x07 -timer_clock__INDEX EQU 0x01 +timer_clock__INDEX EQU 0x02 timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -timer_clock__PM_ACT_MSK EQU 0x02 +timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -timer_clock__PM_STBY_MSK EQU 0x02 +timer_clock__PM_STBY_MSK EQU 0x04 ; scsiTarget scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1208,54 +1211,54 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB14_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB14_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB14_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB14_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB14_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB14_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB14_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB14_15_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB14_15_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB14_15_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB14_15_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB14_15_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB14_15_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB14_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB14_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB14_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB14_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB14_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB14_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB14_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB14_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB14_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL ; USBFS_ep_0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1493,6 +1496,17 @@ SCSI_ATN__PS EQU CYREG_PRT2_PS SCSI_ATN__SHIFT EQU 0 SCSI_ATN__SLW EQU CYREG_PRT2_SLW +; SCSI_CLK +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 + ; SCSI_Out SCSI_Out__0__AG EQU CYREG_PRT15_AG SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c index e49d6c5..3ffe79e 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used)) const uint8 cy_meta_loadable[] = { 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x52u, 0x03u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index 0a2ad3e..0698be1 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -67,6 +68,7 @@ #include #include #include +#include #include #include #include diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml index 2a28481..5c51d5c 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml @@ -18,7 +18,7 @@ - + SCSI2SD.svd @@ -27,8 +27,8 @@ .\Generated_Source\PSoC5\Cm3Iar.icf - - + + ..\..\src\main.c ..\..\src\diagnostic.c ..\..\src\disk.c @@ -55,13 +55,13 @@ ..\..\src\config.h - - + + .\device.h - - + + .\Generated_Source\PSoC5\cyfitter_cfg.h .\Generated_Source\PSoC5\cyfitter_cfg.c .\Generated_Source\PSoC5\cybootloader.c @@ -199,47 +199,51 @@ .\Generated_Source\PSoC5\EXTLED_aliases.h .\Generated_Source\PSoC5\EXTLED.c .\Generated_Source\PSoC5\EXTLED.h + .\Generated_Source\PSoC5\SCSI_Parity_Error.c + .\Generated_Source\PSoC5\SCSI_Parity_Error.h + .\Generated_Source\PSoC5\SCSI_CLK.c + .\Generated_Source\PSoC5\SCSI_CLK.h .\Generated_Source\PSoC5\prebuild.bat .\Generated_Source\PSoC5\postbuild.bat .\Generated_Source\PSoC5\CyElfTool.exe .\Generated_Source\PSoC5\libelf.dll - - + + .\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a - - + + .\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a - - + + .\Generated_Source\PSoC5\IAR\CyComponentLibrary.a - + - + - + - + - + - + - + diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx index 8286b03..cf7982a 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,9 +1,18 @@ - - - + + + + + + + + + + + + @@ -84,21 +93,46 @@ - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -156,19 +190,15 @@ - - - - - + - + @@ -177,7 +207,7 @@ - + diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit index 6757f1f..41419c0 100644 Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj index ea111d5..27247b2 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -2085,6 +2085,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd index d623bde..79140a9 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd @@ -490,6 +490,182 @@ + + SCSI_Parity_Error + No description available + 0x40006462 + + 0 + 0x31 + registers + + + + SCSI_Parity_Error_STATUS_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + SCSI_Parity_Error_MASK_REG + No description available + 0x20 + 8 + read-write + 0 + 0 + + + SCSI_Parity_Error_STATUS_AUX_CTL_REG + No description available + 0x30 + 8 + read-write + 0 + 0 + + + FIFO0 + FIFO0 clear + 5 + 5 + read-write + + + ENABLED + Enable counter + 1 + + + DISABLED + Disable counter + 0 + + + + + INTRENBL + Enables or disables the Interrupt + 4 + 4 + read-write + + + ENABLED + Interrupt enabled + 1 + + + DISABLED + Interrupt disabled + 0 + + + + + FIFO1LEVEL + FIFO level + 3 + 3 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO0LEVEL + FIFO level + 2 + 2 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO1CLEAR + FIFO clear + 1 + 1 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + FIFO0CLEAR + FIFO clear + 0 + 0 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + + + + + SCSI_Out_Bits + No description available + 0x4000657B + + 0 + 0x1 + registers + + + + SCSI_Out_Bits_CONTROL_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + Debug_Timer No description available @@ -803,31 +979,10 @@ - - SCSI_Out_Bits - No description available - 0x4000657A - - 0 - 0x1 - registers - - - - SCSI_Out_Bits_CONTROL_REG - No description available - 0x0 - 8 - read-write - 0 - 0 - - - SCSI_CTL_PHASE No description available - 0x4000647B + 0x40006472 0 0x1 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index e9e55f2..64952de 100755 Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit index e5e6ce7..dedaf4e 100644 Binary files a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit and b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit differ