Macintosh-HW/SCSI2SD
1
0
Fork 0
mirror of https://github.com/fhgwright/SCSI2SD.git synced 2025-04-10 01:37:07 +00:00
Code Issues Projects Releases Wiki Activity

Invert logic of the nor flash HOLD pin

Browse Source
This commit is contained in:
Michael McMaster 2021-01-20 19:46:16 +10:00
parent ac604b2b0c
commit 846bde57dd
10 changed files with 2910 additions and 2880 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
software/SCSI2SD/src/flash.c
View File

@ -102,6 +102,7 @@ static void spiFlash_init(S2S_Device* dev)
CyDelayUs(1);
nNOR_CS_Write(0); // Select
CyDelayCycles(4); // Tiny delay
// JEDEC standard "Read Identification" command
// returns CFI information

291
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
View File

@ -450,8 +450,8 @@
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@ -459,9 +459,9 @@
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB04_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB04_ST
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
@ -485,8 +485,8 @@
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
@ -494,9 +494,9 @@
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
/* SD_SCK */
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE1
@ -567,34 +567,34 @@
#define NOR_SCK__SLW CYREG_PRT3_SLW
/* NOR_SPI */
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL
#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL
#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK
#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK
#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST
#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB04_CTL
#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB04_CTL
#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB04_MSK
#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB04_MSK
#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL
#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB04_ST
#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
#define NOR_SPI_BSPIM_RxStsReg__4__MASK 0x10u
#define NOR_SPI_BSPIM_RxStsReg__4__POS 4
#define NOR_SPI_BSPIM_RxStsReg__5__MASK 0x20u
@ -602,34 +602,34 @@
#define NOR_SPI_BSPIM_RxStsReg__6__MASK 0x40u
#define NOR_SPI_BSPIM_RxStsReg__6__POS 6
#define NOR_SPI_BSPIM_RxStsReg__MASK 0x70u
#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1
#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1
#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0
#define NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1
#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1
#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0
#define NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1
#define NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1
#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0
#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1
#define NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB11_MSK
#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB11_ST
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1
#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1
#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0
#define NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1
#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1
#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0
#define NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1
#define NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1
#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0
#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1
#define NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define NOR_SPI_BSPIM_TxStsReg__0__MASK 0x01u
#define NOR_SPI_BSPIM_TxStsReg__0__POS 0
#define NOR_SPI_BSPIM_TxStsReg__1__MASK 0x02u
#define NOR_SPI_BSPIM_TxStsReg__1__POS 1
#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
#define NOR_SPI_BSPIM_TxStsReg__2__MASK 0x04u
#define NOR_SPI_BSPIM_TxStsReg__2__POS 2
#define NOR_SPI_BSPIM_TxStsReg__3__MASK 0x08u
@ -637,9 +637,9 @@
#define NOR_SPI_BSPIM_TxStsReg__4__MASK 0x10u
#define NOR_SPI_BSPIM_TxStsReg__4__POS 4
#define NOR_SPI_BSPIM_TxStsReg__MASK 0x1Fu
#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK
#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST
#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB03_MSK
#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB03_ST
/* SCSI_In */
#define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1
@ -1760,15 +1760,15 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@ -1781,35 +1781,35 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB10_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB10_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB10_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB10_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB10_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB10_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
@ -2673,8 +2673,6 @@
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
@ -2682,13 +2680,13 @@
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK
#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL
#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK
#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB15_ST_CTL
#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB15_ST_CTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST
/* Debug_Timer */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -2803,6 +2801,8 @@
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@ -2810,67 +2810,58 @@
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB15_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB15_ST
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B1_UDB08_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B1_UDB08_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK
/* SCSI_Glitch_Ctl */
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB09_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB09_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB09_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB08_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB08_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U

3800
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
View File

File diff suppressed because it is too large Load Diff

291
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
View File

@ -450,8 +450,8 @@
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@ -459,9 +459,9 @@
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB04_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB04_ST
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
@ -485,8 +485,8 @@
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
@ -494,9 +494,9 @@
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
/* SD_SCK */
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE1
@ -567,34 +567,34 @@
.set NOR_SCK__SLW, CYREG_PRT3_SLW
/* NOR_SPI */
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL
.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL
.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK
.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK
.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST
.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB04_CTL
.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB04_CTL
.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB04_MSK
.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB04_MSK
.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL
.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB04_ST
.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
.set NOR_SPI_BSPIM_RxStsReg__4__MASK, 0x10
.set NOR_SPI_BSPIM_RxStsReg__4__POS, 4
.set NOR_SPI_BSPIM_RxStsReg__5__MASK, 0x20
@ -602,34 +602,34 @@
.set NOR_SPI_BSPIM_RxStsReg__6__MASK, 0x40
.set NOR_SPI_BSPIM_RxStsReg__6__POS, 6
.set NOR_SPI_BSPIM_RxStsReg__MASK, 0x70
.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1
.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1
.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0
.set NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1
.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1
.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0
.set NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1
.set NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1
.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0
.set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1
.set NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB11_MSK
.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB11_ST
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1
.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1
.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0
.set NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1
.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1
.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0
.set NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1
.set NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1
.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0
.set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1
.set NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set NOR_SPI_BSPIM_TxStsReg__0__MASK, 0x01
.set NOR_SPI_BSPIM_TxStsReg__0__POS, 0
.set NOR_SPI_BSPIM_TxStsReg__1__MASK, 0x02
.set NOR_SPI_BSPIM_TxStsReg__1__POS, 1
.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
.set NOR_SPI_BSPIM_TxStsReg__2__MASK, 0x04
.set NOR_SPI_BSPIM_TxStsReg__2__POS, 2
.set NOR_SPI_BSPIM_TxStsReg__3__MASK, 0x08
@ -637,9 +637,9 @@
.set NOR_SPI_BSPIM_TxStsReg__4__MASK, 0x10
.set NOR_SPI_BSPIM_TxStsReg__4__POS, 4
.set NOR_SPI_BSPIM_TxStsReg__MASK, 0x1F
.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK
.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB03_MSK
.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB03_ST
/* SCSI_In */
.set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1
@ -1760,15 +1760,15 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@ -1781,35 +1781,35 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB10_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB10_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB10_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB10_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB10_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX
.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE
@ -2673,8 +2673,6 @@
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
@ -2682,13 +2680,13 @@
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK
.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL
.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK
.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB15_ST_CTL
.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB15_ST_CTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST
/* Debug_Timer */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -2803,6 +2801,8 @@
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@ -2810,67 +2810,58 @@
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB15_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB15_ST
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B1_UDB08_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B1_UDB08_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK
/* SCSI_Glitch_Ctl */
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB09_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB09_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB09_MSK
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB08_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB08_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB12_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB12_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000

291
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
View File

@ -449,8 +449,8 @@ SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -458,9 +458,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -484,8 +484,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -493,9 +493,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
/* SD_SCK */
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
@ -566,34 +566,34 @@ NOR_SCK__SHIFT EQU 7
NOR_SCK__SLW EQU CYREG_PRT3_SLW
/* NOR_SPI */
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL
NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL
NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK
NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -601,34 +601,34 @@ NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5
NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40
NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6
NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70
NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0
NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1
NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0
NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1
NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1
NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK
NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0
NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1
NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0
NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1
NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1
NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01
NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0
NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02
NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04
NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2
NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -636,9 +636,9 @@ NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3
NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F
NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK
NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST
/* SCSI_In */
SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
@ -1759,15 +1759,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1780,35 +1780,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
@ -2672,8 +2672,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2681,13 +2679,13 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
/* Debug_Timer */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2802,6 +2800,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2809,67 +2809,58 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB15_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB15_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
/* SCSI_Glitch_Ctl */
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000

291
software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
View File

@ -449,8 +449,8 @@ SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -458,9 +458,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -484,8 +484,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -493,9 +493,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
; SD_SCK
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
@ -566,34 +566,34 @@ NOR_SCK__SHIFT EQU 7
NOR_SCK__SLW EQU CYREG_PRT3_SLW
; NOR_SPI
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL
NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL
NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK
NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -601,34 +601,34 @@ NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5
NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40
NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6
NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70
NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0
NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1
NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0
NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1
NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1
NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK
NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0
NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1
NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0
NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1
NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0
NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1
NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01
NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0
NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02
NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04
NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2
NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -636,9 +636,9 @@ NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3
NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F
NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK
NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST
; SCSI_In
SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
@ -1759,15 +1759,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1780,35 +1780,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
@ -2672,8 +2672,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2681,13 +2679,13 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
; Debug_Timer
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2802,6 +2800,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2809,67 +2809,58 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB15_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB15_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
; SCSI_Glitch_Ctl
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000

181
software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx
View File

@ -5,16 +5,16 @@
<block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006479" bitWidth="8" desc="" hidden="false" />
</block>
<block name="TERM_EN" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006568" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006588" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006598" bitWidth="8" desc="" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646C" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x4000648C" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649C" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
@ -46,9 +46,9 @@
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x4000646F" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x4000648F" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649F" bitWidth="8" desc="" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x40006568" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x40006588" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006598" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
@ -76,8 +76,20 @@
</register>
</block>
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="nNOR_HOLD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_SI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="nNOR_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="nNOR_HOLD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Em_EEPROM_Dynamic" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="nNOR_WP" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_9" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_SO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_SPI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -85,20 +97,8 @@
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
</block>
<block name="NOR_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Em_EEPROM_Dynamic" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="nNOR_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="nNOR_WP" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_Clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_SO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_Clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -109,7 +109,7 @@
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647F" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -117,71 +117,15 @@
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">
<field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." hidden="false" />
</register>
<register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">
<field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." hidden="false" />
<field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)" hidden="false">
<value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
<value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
</field>
<field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." hidden="false" />
<field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." hidden="false" />
<field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" hidden="false" />
<field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively." hidden="false">
<value name="Timer" value="0" desc="CMP and TC are output." />
<value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
</field>
<field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" hidden="false" />
</register>
<register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">
<field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" hidden="false" />
<field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled." hidden="false">
<value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
<value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
</field>
<field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." hidden="false" />
<field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." hidden="false" />
<field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." hidden="false" />
<field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." hidden="false" />
</register>
<register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">
<field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ" hidden="false">
<value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
<value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
<value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
<value name="Irq" value="11" desc="Timer runs until IRQ." />
</field>
<field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." hidden="false" />
<field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" hidden="false" />
<field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations" hidden="false">
<value name="Equal" value="0" desc="Compare Equal " />
<value name="Less than" value="1" desc="Compare Less Than " />
<value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
<value name="Greater" value="11" desc="Compare Greater Than ." />
<value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
</field>
<field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." hidden="false" />
</register>
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
</block>
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">
<block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -1040,7 +984,7 @@
<field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />
</register>
</block>
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -1048,12 +992,69 @@
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
</block>
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" hidden="false" />
</block>
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">
<field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." hidden="false" />
</register>
<register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">
<field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." hidden="false" />
<field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)" hidden="false">
<value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
<value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
</field>
<field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." hidden="false" />
<field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." hidden="false" />
<field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" hidden="false" />
<field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively." hidden="false">
<value name="Timer" value="0" desc="CMP and TC are output." />
<value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
</field>
<field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" hidden="false" />
</register>
<register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">
<field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" hidden="false" />
<field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled." hidden="false">
<value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
<value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
</field>
<field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." hidden="false" />
<field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." hidden="false" />
<field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." hidden="false" />
<field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." hidden="false" />
</register>
<register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">
<field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ" hidden="false">
<value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
<value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
<value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
<value name="Irq" value="11" desc="Timer runs until IRQ." />
</field>
<field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." hidden="false" />
<field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" hidden="false" />
<field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations" hidden="false">
<value name="Equal" value="0" desc="Compare Equal " />
<value name="Less than" value="1" desc="Compare Less Than " />
<value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
<value name="Greater" value="11" desc="Compare Greater Than ." />
<value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
</field>
<field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." hidden="false" />
</register>
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
</block>
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000657A" bitWidth="8" desc="" hidden="false" />
</block>
</blockRegMap>

BIN
software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit
View File

Binary file not shown.

644
software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.svd
View File

@ -19,7 +19,7 @@
<register>
<name>SCSI_Glitch_Ctl_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x4000647C</addressOffset>
<addressOffset>0x40006479</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
@ -40,7 +40,7 @@
<register>
<name>SCSI_Parity_Error_STATUS_REG</name>
<description>No description available</description>
<addressOffset>0x40006568</addressOffset>
<addressOffset>0x4000646C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
@ -49,7 +49,7 @@
<register>
<name>SCSI_Parity_Error_MASK_REG</name>
<description>No description available</description>
<addressOffset>0x40006588</addressOffset>
<addressOffset>0x4000648C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
@ -58,7 +58,7 @@
<register>
<name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
<addressOffset>0x40006598</addressOffset>
<addressOffset>0x4000649C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
@ -195,7 +195,7 @@
<register>
<name>SCSI_Filtered_STATUS_REG</name>
<description>No description available</description>
<addressOffset>0x4000646F</addressOffset>
<addressOffset>0x40006568</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
@ -204,7 +204,7 @@
<register>
<name>SCSI_Filtered_MASK_REG</name>
<description>No description available</description>
<addressOffset>0x4000648F</addressOffset>
<addressOffset>0x40006588</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
@ -213,7 +213,7 @@
<register>
<name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
<addressOffset>0x4000649F</addressOffset>
<addressOffset>0x40006598</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
@ -350,7 +350,7 @@
<register>
<name>SCSI_CTL_PHASE_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x4000647D</addressOffset>
<addressOffset>0x4000647F</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
@ -358,298 +358,6 @@
</register>
</registers>
</peripheral>
<peripheral>
<name>Debug_Timer</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>Debug_Timer_GLOBAL_ENABLE</name>
<description>PM.ACT.CFG</description>
<addressOffset>0x400043A3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>en_timer</name>
<description>Enable timer/counters.</description>
<lsb>0</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL</name>
<description>TMRx.CFG0</description>
<addressOffset>0x40004F00</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>EN</name>
<description>Enables timer/comparator.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>MODE</name>
<description>Mode. (0 = Timer; 1 = Comparator)</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Timer</name>
<description>Timer mode. CNT/CMP register holds timer count value.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Comparator</name>
<description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONESHOT</name>
<description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>CMP_BUFF</name>
<description>Buffer compare register. Compare register updates only on timer terminal count.</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>INV</name>
<description>Invert sense of TIMEREN signal</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DB</name>
<description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Timer</name>
<description>CMP and TC are output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Deadband</name>
<description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEADBAND_PERIOD</name>
<description>Deadband Period</description>
<lsb>6</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL2</name>
<description>TMRx.CFG1</description>
<addressOffset>0x40004F01</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IRQ_SEL</name>
<description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>FTC</name>
<description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Disable_FTC</name>
<description>Disable the single cycle pulse, which signifies the timer is starting.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable_FTC</name>
<description>Enable the single cycle pulse, which signifies the timer is starting.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DCOR</name>
<description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>DBMODE</name>
<description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>CLK_BUS_EN_SEL</name>
<description>Digital Global Clock selection.</description>
<lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>BUS_CLK_SEL</name>
<description>Bus Clock selection.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL3_</name>
<description>TMRx.CFG2</description>
<addressOffset>0x40004F02</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>TMR_CFG</name>
<description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
<lsb>0</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Continuous</name>
<description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Pulsewidth</name>
<description>Timer runs from positive to negative edge of TIMEREN.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Period</name>
<description>Timer runs from positive to positive edge of TIMEREN.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>Irq</name>
<description>Timer runs until IRQ.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COD</name>
<description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>ROD</name>
<description>Reset On Disable (ROD). Resets internal state of output logic</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>CMP_CFG</name>
<description>Comparator configurations</description>
<lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Equal</name>
<description>Compare Equal </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Less_than</name>
<description>Compare Less Than </description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Less_than_or_equal</name>
<description>Compare Less Than or Equal .</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>Greater</name>
<description>Compare Greater Than .</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>Greater_than_or_equal</name>
<description>Compare Greater Than or Equal </description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HW_EN</name>
<description>When set Timer Enable controls counting.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_PERIOD</name>
<description>TMRx.PER0 - Assigned Period</description>
<addressOffset>0x40004F04</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>Debug_Timer_COUNTER</name>
<description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
<addressOffset>0x40004F06</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>USBFS</name>
<description>USBFS</description>
@ -2888,27 +2596,6 @@
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Out_Bits_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x40006473</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
@ -2922,7 +2609,320 @@
<register>
<name>SCSI_Out_Ctl_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x40006471</addressOffset>
<addressOffset>0x40006478</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>Debug_Timer</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>Debug_Timer_GLOBAL_ENABLE</name>
<description>PM.ACT.CFG</description>
<addressOffset>0x400043A3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>en_timer</name>
<description>Enable timer/counters.</description>
<lsb>0</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL</name>
<description>TMRx.CFG0</description>
<addressOffset>0x40004F00</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>EN</name>
<description>Enables timer/comparator.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>MODE</name>
<description>Mode. (0 = Timer; 1 = Comparator)</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Timer</name>
<description>Timer mode. CNT/CMP register holds timer count value.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Comparator</name>
<description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONESHOT</name>
<description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>CMP_BUFF</name>
<description>Buffer compare register. Compare register updates only on timer terminal count.</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>INV</name>
<description>Invert sense of TIMEREN signal</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
<name>DB</name>
<description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Timer</name>
<description>CMP and TC are output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Deadband</name>
<description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEADBAND_PERIOD</name>
<description>Deadband Period</description>
<lsb>6</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL2</name>
<description>TMRx.CFG1</description>
<addressOffset>0x40004F01</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>IRQ_SEL</name>
<description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
<name>FTC</name>
<description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Disable_FTC</name>
<description>Disable the single cycle pulse, which signifies the timer is starting.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable_FTC</name>
<description>Enable the single cycle pulse, which signifies the timer is starting.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DCOR</name>
<description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>DBMODE</name>
<description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>CLK_BUS_EN_SEL</name>
<description>Digital Global Clock selection.</description>
<lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
<name>BUS_CLK_SEL</name>
<description>Bus Clock selection.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_CONTROL3_</name>
<description>TMRx.CFG2</description>
<addressOffset>0x40004F02</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>TMR_CFG</name>
<description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
<lsb>0</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Continuous</name>
<description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Pulsewidth</name>
<description>Timer runs from positive to negative edge of TIMEREN.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Period</name>
<description>Timer runs from positive to positive edge of TIMEREN.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>Irq</name>
<description>Timer runs until IRQ.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COD</name>
<description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
<name>ROD</name>
<description>Reset On Disable (ROD). Resets internal state of output logic</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
<name>CMP_CFG</name>
<description>Comparator configurations</description>
<lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Equal</name>
<description>Compare Equal </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Less_than</name>
<description>Compare Less Than </description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Less_than_or_equal</name>
<description>Compare Less Than or Equal .</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>Greater</name>
<description>Compare Greater Than .</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>Greater_than_or_equal</name>
<description>Compare Greater Than or Equal </description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HW_EN</name>
<description>When set Timer Enable controls counting.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>Debug_Timer_PERIOD</name>
<description>TMRx.PER0 - Assigned Period</description>
<addressOffset>0x40004F04</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>Debug_Timer_COUNTER</name>
<description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
<addressOffset>0x40004F06</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Out_Bits_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x4000657A</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>

BIN
software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
View File

Binary file not shown.