mirror of
https://github.com/fhgwright/SCSI2SD.git
synced 2024-12-28 19:32:39 +00:00
Adding configurable geometry support to firmware.
Fix for scsi2sd-util crashes on exit.
This commit is contained in:
Michael McMaster
parent
6c7ac0966f
commit
94cc9e77bc
18
readme.txt
18
readme.txt
@ -35,10 +35,11 @@ Micro SD Card Interface
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USB Interface (firmware updates and config)
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USB 2.0 micro-B
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Power
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5V via standard molex drive connector.
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5V via standard molex drive connector
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USB or self-powered using the SCSI host termination power. (v5 only)
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Dimensions
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10cm x 10cm x 1.5cm
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Mounting holes to suit standard 2.5" - 3.5" drive bracket.
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10cm x 5cm x 1.5cm (v5)
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10cm x 10cm x 1.5cm (v3, v4)
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Performance
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@ -95,6 +96,17 @@ Compatibility
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Device-type modifier: 0x4c
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Applix 1616
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IMS MM/1
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NeXTcube + NeXTSTEP 3.3
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NeXTStation
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Modified geometry settings are required to avoid "cylinder group too large" errors while formatting.
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(To simulate Quantum Fireball 1050S)
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512 bytesPerSector
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139 sectorsPerTrack
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4 tracksPerCylinder
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4135 cylinder per volume
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1 spare sector per cylinder
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2051459 usable sectors on volume
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Samplers
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@ -32,7 +32,7 @@
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#include <string.h>
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static const uint16_t FIRMWARE_VERSION = 0x0424;
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static const uint16_t FIRMWARE_VERSION = 0x0430;
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// 1 flash row
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static const uint8_t DEFAULT_CONFIG[256] =
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@ -99,11 +99,15 @@ void scsiReceiveDiagnostic()
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uint64 fromByteAddr =
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scsiByteAddress(
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scsiDev.target->liveCfg.bytesPerSector,
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scsiDev.target->cfg->headsPerCylinder,
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scsiDev.target->cfg->sectorsPerTrack,
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suppliedFmt,
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&scsiDev.data[6]);
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scsiSaveByteAddress(
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scsiDev.target->liveCfg.bytesPerSector,
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scsiDev.target->cfg->headsPerCylinder,
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scsiDev.target->cfg->sectorsPerTrack,
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translateFmt,
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fromByteAddr,
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&scsiDev.data[6]);
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@ -46,36 +46,49 @@ uint32_t SCSISector2SD(
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// Standard mapping according to ECMA-107 and ISO/IEC 9293:1994
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// Sector always starts at 1. There is no 0 sector.
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uint64 CHS2LBA(uint32 c, uint8 h, uint32 s)
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uint64_t CHS2LBA(
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uint32_t c,
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uint8_t h,
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uint32_t s,
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uint16_t headsPerCylinder,
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uint16_t sectorsPerTrack)
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{
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return (
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(((uint64)c) * SCSI_HEADS_PER_CYLINDER + h) *
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(uint64) SCSI_SECTORS_PER_TRACK
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(((uint64_t)c) * headsPerCylinder + h) *
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(uint64_t) sectorsPerTrack
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) + (s - 1);
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}
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void LBA2CHS(uint32 lba, uint32* c, uint8* h, uint32* s)
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void LBA2CHS(
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uint32_t lba,
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uint32_t* c,
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uint8_t* h,
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uint32_t* s,
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uint16_t headsPerCylinder,
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uint16_t sectorsPerTrack)
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{
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*c = lba / (SCSI_SECTORS_PER_TRACK * SCSI_HEADS_PER_CYLINDER);
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*h = (lba / SCSI_SECTORS_PER_TRACK) % SCSI_HEADS_PER_CYLINDER;
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*s = (lba % SCSI_SECTORS_PER_TRACK) + 1;
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*c = lba / (((uint32_t) sectorsPerTrack) * headsPerCylinder);
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*h = (lba / sectorsPerTrack) % headsPerCylinder;
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*s = (lba % sectorsPerTrack) + 1;
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}
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uint64 scsiByteAddress(
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uint64_t scsiByteAddress(
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uint16_t bytesPerSector,
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uint16_t headsPerCylinder,
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uint16_t sectorsPerTrack,
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int format,
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const uint8* addr)
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const uint8_t* addr)
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{
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uint64 result;
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uint64_t result;
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switch (format)
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{
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case ADDRESS_BLOCK:
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{
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uint32 lba =
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(((uint32) addr[0]) << 24) +
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(((uint32) addr[1]) << 16) +
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(((uint32) addr[2]) << 8) +
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uint32_t lba =
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(((uint32_t) addr[0]) << 24) +
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(((uint32_t) addr[1]) << 16) +
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(((uint32_t) addr[2]) << 8) +
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addr[3];
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result = (uint64_t) bytesPerSector * lba;
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@ -83,38 +96,39 @@ uint64 scsiByteAddress(
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case ADDRESS_PHYSICAL_BYTE:
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{
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uint32 cyl =
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(((uint32) addr[0]) << 16) +
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(((uint32) addr[1]) << 8) +
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uint32_t cyl =
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(((uint32_t) addr[0]) << 16) +
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(((uint32_t) addr[1]) << 8) +
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addr[2];
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uint8 head = addr[3];
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uint8_t head = addr[3];
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uint32 bytes =
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(((uint32) addr[4]) << 24) +
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(((uint32) addr[5]) << 16) +
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(((uint32) addr[6]) << 8) +
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uint32_t bytes =
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(((uint32_t) addr[4]) << 24) +
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(((uint32_t) addr[5]) << 16) +
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(((uint32_t) addr[6]) << 8) +
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addr[7];
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result = CHS2LBA(cyl, head, 1) * (uint64_t) bytesPerSector + bytes;
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result = CHS2LBA(cyl, head, 1, headsPerCylinder, sectorsPerTrack) *
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(uint64_t) bytesPerSector + bytes;
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} break;
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case ADDRESS_PHYSICAL_SECTOR:
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{
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uint32 cyl =
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(((uint32) addr[0]) << 16) +
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(((uint32) addr[1]) << 8) +
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(((uint32_t) addr[0]) << 16) +
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(((uint32_t) addr[1]) << 8) +
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addr[2];
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uint8 head = scsiDev.data[3];
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uint32 sector =
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(((uint32) addr[4]) << 24) +
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(((uint32) addr[5]) << 16) +
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(((uint32) addr[6]) << 8) +
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(((uint32_t) addr[4]) << 24) +
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(((uint32_t) addr[5]) << 16) +
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(((uint32_t) addr[6]) << 8) +
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addr[7];
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result = CHS2LBA(cyl, head, sector) * (uint64_t) bytesPerSector;
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result = CHS2LBA(cyl, head, sector, headsPerCylinder, sectorsPerTrack) * (uint64_t) bytesPerSector;
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} break;
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default:
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@ -127,12 +141,14 @@ uint64 scsiByteAddress(
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void scsiSaveByteAddress(
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uint16_t bytesPerSector,
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uint16_t headsPerCylinder,
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uint16_t sectorsPerTrack,
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int format,
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uint64 byteAddr,
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uint8* buf)
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uint64_t byteAddr,
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uint8_t* buf)
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{
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uint32 lba = byteAddr / bytesPerSector;
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uint32 byteOffset = byteAddr % bytesPerSector;
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uint32_t lba = byteAddr / bytesPerSector;
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uint32_t byteOffset = byteAddr % bytesPerSector;
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switch (format)
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{
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@ -151,12 +167,12 @@ void scsiSaveByteAddress(
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case ADDRESS_PHYSICAL_BYTE:
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{
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uint32 cyl;
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uint8 head;
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uint32 sector;
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uint32 bytes;
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uint32_t cyl;
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uint8_t head;
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uint32_t sector;
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uint32_t bytes;
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LBA2CHS(lba, &cyl, &head, §or);
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LBA2CHS(lba, &cyl, &head, §or, headsPerCylinder, sectorsPerTrack);
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bytes = sector * bytesPerSector + byteOffset;
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@ -174,11 +190,11 @@ void scsiSaveByteAddress(
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case ADDRESS_PHYSICAL_SECTOR:
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{
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uint32 cyl;
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uint8 head;
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uint32 sector;
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uint32_t cyl;
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uint8_t head;
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uint32_t sector;
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LBA2CHS(lba, &cyl, &head, §or);
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LBA2CHS(lba, &cyl, &head, §or, headsPerCylinder, sectorsPerTrack);
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buf[0] = cyl >> 16;
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buf[1] = cyl >> 8;
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@ -22,12 +22,6 @@
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#include "config.h"
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#include "sd.h"
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// Max allowed by legacy IBM-PC Bios (6 bits)
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#define SCSI_SECTORS_PER_TRACK 63
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// MS-DOS up to 7.10 will crash on 256 heads.
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#define SCSI_HEADS_PER_CYLINDER 255
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typedef enum
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{
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ADDRESS_BLOCK = 0,
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@ -50,16 +44,36 @@ uint32_t SCSISector2SD(
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uint16_t bytesPerSector,
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uint32_t scsiSector);
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uint64 CHS2LBA(uint32 c, uint8 h, uint32 s);
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void LBA2CHS(uint32 lba, uint32* c, uint8* h, uint32* s);
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uint64_t CHS2LBA(
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uint32_t c,
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uint8_t h,
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uint32_t s,
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uint16_t headsPerCylinder,
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uint16_t sectorsPerTrack);
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void LBA2CHS(
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uint32_t lba,
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uint32_t* c,
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uint8_t* h,
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uint32_t* s,
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uint16_t headsPerCylinder,
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uint16_t sectorsPerTrack);
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// Convert an address in the given SCSI_ADDRESS_FORMAT to
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// a linear byte address.
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// addr must be >= 8 bytes.
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uint64 scsiByteAddress(
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uint16_t bytesPerSector, int format, const uint8* addr);
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uint64_t scsiByteAddress(
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uint16_t bytesPerSector,
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uint16_t headsPerCylinder,
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uint16_t sectorsPerTrack,
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int format,
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const uint8_t* addr);
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void scsiSaveByteAddress(
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uint16_t bytesPerSector, int format, uint64 byteAddr, uint8* buf);
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uint16_t bytesPerSector,
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uint16_t headsPerCylinder,
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uint16_t sectorsPerTrack,
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int format,
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uint64_t byteAddr,
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uint8_t* buf);
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#endif
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@ -97,7 +97,7 @@ static const uint8 FormatDevicePage[] =
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0x00, 0x00, // No alternate sectors
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0x00, 0x00, // No alternate tracks
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0x00, 0x00, // No alternate tracks per lun
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0x00, SCSI_SECTORS_PER_TRACK, // Sectors per track
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0x00, 0x00, // Sectors per track, configurable
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0xFF, 0xFF, // Data bytes per physical sector. Configurable.
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0x00, 0x01, // Interleave
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0x00, 0x00, // Track skew factor
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@ -111,7 +111,7 @@ static const uint8 RigidDiskDriveGeometry[] =
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0x04, // Page code
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0x16, // Page length
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0xFF, 0xFF, 0xFF, // Number of cylinders
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SCSI_HEADS_PER_CYLINDER, // Number of heads
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0x00, // Number of heads (replaced by configured value)
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0xFF, 0xFF, 0xFF, // Starting cylinder-write precompensation
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0xFF, 0xFF, 0xFF, // Starting cylinder-reduced write current
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0x00, 0x1, // Drive step rate (units of 100ns)
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@ -128,7 +128,7 @@ static const uint8 RigidDiskDriveGeometry_SCSI1[] =
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0x04, // Page code
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0x12, // Page length
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0xFF, 0xFF, 0xFF, // Number of cylinders
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SCSI_HEADS_PER_CYLINDER, // Number of heads
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0x00, // Number of heads (replaced by configured value)
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0xFF, 0xFF, 0xFF, // Starting cylinder-write precompensation
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0xFF, 0xFF, 0xFF, // Starting cylinder-reduced write current
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0x00, 0x1, // Drive step rate (units of 100ns)
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@ -311,6 +311,10 @@ static void doModeSense(
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pageIn(pc, idx, FormatDevicePage, sizeof(FormatDevicePage));
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if (pc != 0x01)
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{
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uint16_t sectorsPerTrack = scsiDev.target->cfg->sectorsPerTrack;
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scsiDev.data[idx+10] = sectorsPerTrack >> 8;
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scsiDev.data[idx+11] = sectorsPerTrack & 0xFF;
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// Fill out the configured bytes-per-sector
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uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector;
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scsiDev.data[idx+12] = bytesPerSector >> 8;
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@ -351,7 +355,9 @@ static void doModeSense(
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scsiDev.target->cfg->scsiSectors),
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&cyl,
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&head,
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§or);
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§or,
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scsiDev.target->cfg->headsPerCylinder,
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scsiDev.target->cfg->sectorsPerTrack);
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scsiDev.data[idx+2] = cyl >> 16;
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scsiDev.data[idx+3] = cyl >> 8;
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@ -359,6 +365,8 @@ static void doModeSense(
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memcpy(&scsiDev.data[idx+6], &scsiDev.data[idx+2], 3);
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memcpy(&scsiDev.data[idx+9], &scsiDev.data[idx+2], 3);
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scsiDev.data[idx+5] = scsiDev.target->cfg->headsPerCylinder;
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}
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if ((scsiDev.compatMode >= COMPAT_SCSI2))
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@ -207,40 +207,40 @@
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/* USBFS_ep_1 */
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#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_ep_1__INTC_MASK 0x40u
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#define USBFS_ep_1__INTC_NUMBER 6u
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#define USBFS_ep_1__INTC_MASK 0x80u
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#define USBFS_ep_1__INTC_NUMBER 7u
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#define USBFS_ep_1__INTC_PRIOR_NUM 7u
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#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6
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#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7
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#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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/* USBFS_ep_2 */
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#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_ep_2__INTC_MASK 0x80u
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#define USBFS_ep_2__INTC_NUMBER 7u
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#define USBFS_ep_2__INTC_MASK 0x100u
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#define USBFS_ep_2__INTC_NUMBER 8u
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#define USBFS_ep_2__INTC_PRIOR_NUM 7u
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#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7
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#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8
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#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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/* USBFS_ep_3 */
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#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_ep_3__INTC_MASK 0x100u
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#define USBFS_ep_3__INTC_NUMBER 8u
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#define USBFS_ep_3__INTC_MASK 0x200u
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#define USBFS_ep_3__INTC_NUMBER 9u
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#define USBFS_ep_3__INTC_PRIOR_NUM 7u
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#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8
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#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9
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#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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/* USBFS_ep_4 */
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#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_ep_4__INTC_MASK 0x200u
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#define USBFS_ep_4__INTC_NUMBER 9u
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#define USBFS_ep_4__INTC_MASK 0x400u
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#define USBFS_ep_4__INTC_NUMBER 10u
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#define USBFS_ep_4__INTC_PRIOR_NUM 7u
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#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9
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#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10
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#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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@ -381,34 +381,34 @@
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#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
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/* SDCard_BSPIM */
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
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||||
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL
|
||||
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK
|
||||
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
|
||||
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK
|
||||
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
|
||||
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
|
||||
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
|
||||
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
|
||||
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
|
||||
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
|
||||
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
|
||||
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
|
||||
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
|
||||
#define SDCard_BSPIM_RxStsReg__4__POS 4
|
||||
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
|
||||
@ -416,9 +416,9 @@
|
||||
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
|
||||
#define SDCard_BSPIM_RxStsReg__6__POS 6
|
||||
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
|
||||
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST
|
||||
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
|
||||
@ -436,12 +436,14 @@
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
|
||||
#define SDCard_BSPIM_TxStsReg__0__POS 0
|
||||
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
|
||||
#define SDCard_BSPIM_TxStsReg__1__POS 1
|
||||
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
|
||||
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
|
||||
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
|
||||
#define SDCard_BSPIM_TxStsReg__2__POS 2
|
||||
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
|
||||
@ -449,9 +451,9 @@
|
||||
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
|
||||
#define SDCard_BSPIM_TxStsReg__4__POS 4
|
||||
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
|
||||
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK
|
||||
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST
|
||||
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
|
||||
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
|
||||
|
||||
/* SD_SCK */
|
||||
#define SD_SCK__0__MASK 0x04u
|
||||
@ -1875,15 +1877,15 @@
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
|
||||
@ -1896,37 +1898,37 @@
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
|
||||
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
|
||||
|
||||
/* SCSI_Out_Ctl */
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
|
||||
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
|
||||
|
||||
/* SCSI_Out_DBx */
|
||||
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
|
||||
@ -2377,10 +2379,10 @@
|
||||
/* SD_RX_DMA_COMPLETE */
|
||||
#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
||||
#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
||||
#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u
|
||||
#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u
|
||||
#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u
|
||||
#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u
|
||||
#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
|
||||
#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
|
||||
#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
|
||||
#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
||||
#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -2399,10 +2401,10 @@
|
||||
/* SD_TX_DMA_COMPLETE */
|
||||
#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
||||
#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
||||
#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u
|
||||
#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u
|
||||
#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u
|
||||
#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u
|
||||
#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
|
||||
#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
|
||||
#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6
|
||||
#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
||||
#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -2804,10 +2806,10 @@
|
||||
/* SCSI_TX_DMA_COMPLETE */
|
||||
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
||||
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
||||
#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u
|
||||
#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u
|
||||
#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u
|
||||
#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u
|
||||
#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
|
||||
#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3
|
||||
#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
|
||||
#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
||||
#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -2843,13 +2845,23 @@
|
||||
#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
||||
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
||||
|
||||
/* SCSI_SEL_ISR */
|
||||
#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
||||
#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
||||
#define SCSI_SEL_ISR__INTC_MASK 0x08u
|
||||
#define SCSI_SEL_ISR__INTC_NUMBER 3u
|
||||
#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u
|
||||
#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3
|
||||
#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
||||
#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
||||
|
||||
/* SCSI_Filtered */
|
||||
#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u
|
||||
#define SCSI_Filtered_sts_sts_reg__0__POS 0
|
||||
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
|
||||
#define SCSI_Filtered_sts_sts_reg__1__POS 1
|
||||
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
|
||||
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST
|
||||
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
|
||||
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
|
||||
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
|
||||
#define SCSI_Filtered_sts_sts_reg__2__POS 2
|
||||
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
|
||||
@ -2857,9 +2869,13 @@
|
||||
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
|
||||
#define SCSI_Filtered_sts_sts_reg__4__POS 4
|
||||
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
|
||||
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB13_MSK
|
||||
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL
|
||||
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB13_ST
|
||||
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK
|
||||
#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
|
||||
#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
|
||||
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
|
||||
#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
|
||||
#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
|
||||
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST
|
||||
|
||||
/* SCSI_CTL_PHASE */
|
||||
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
|
||||
@ -2890,12 +2906,12 @@
|
||||
/* SCSI_Parity_Error */
|
||||
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
|
||||
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
|
||||
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
|
||||
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
|
||||
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
|
||||
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
|
||||
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
|
||||
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK
|
||||
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
|
||||
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST
|
||||
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK
|
||||
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
|
||||
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST
|
||||
|
||||
/* Miscellaneous */
|
||||
#define BCLK__BUS_CLK__HZ 50000000U
|
||||
@ -2976,7 +2992,7 @@
|
||||
#define CYDEV_ECC_ENABLE 0
|
||||
#define CYDEV_HEAP_SIZE 0x0400
|
||||
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
|
||||
#define CYDEV_INTR_RISING 0x0000003Eu
|
||||
#define CYDEV_INTR_RISING 0x0000007Eu
|
||||
#define CYDEV_PROJ_TYPE 2
|
||||
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
|
||||
#define CYDEV_PROJ_TYPE_LOADABLE 2
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -207,40 +207,40 @@
|
||||
/* USBFS_ep_1 */
|
||||
.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
|
||||
.set USBFS_ep_1__INTC_MASK, 0x40
|
||||
.set USBFS_ep_1__INTC_NUMBER, 6
|
||||
.set USBFS_ep_1__INTC_MASK, 0x80
|
||||
.set USBFS_ep_1__INTC_NUMBER, 7
|
||||
.set USBFS_ep_1__INTC_PRIOR_NUM, 7
|
||||
.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
|
||||
.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
|
||||
.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
|
||||
.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
|
||||
|
||||
/* USBFS_ep_2 */
|
||||
.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
|
||||
.set USBFS_ep_2__INTC_MASK, 0x80
|
||||
.set USBFS_ep_2__INTC_NUMBER, 7
|
||||
.set USBFS_ep_2__INTC_MASK, 0x100
|
||||
.set USBFS_ep_2__INTC_NUMBER, 8
|
||||
.set USBFS_ep_2__INTC_PRIOR_NUM, 7
|
||||
.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
|
||||
.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
|
||||
.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
|
||||
.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
|
||||
|
||||
/* USBFS_ep_3 */
|
||||
.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
|
||||
.set USBFS_ep_3__INTC_MASK, 0x100
|
||||
.set USBFS_ep_3__INTC_NUMBER, 8
|
||||
.set USBFS_ep_3__INTC_MASK, 0x200
|
||||
.set USBFS_ep_3__INTC_NUMBER, 9
|
||||
.set USBFS_ep_3__INTC_PRIOR_NUM, 7
|
||||
.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
|
||||
.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
|
||||
.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
|
||||
.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
|
||||
|
||||
/* USBFS_ep_4 */
|
||||
.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
|
||||
.set USBFS_ep_4__INTC_MASK, 0x200
|
||||
.set USBFS_ep_4__INTC_NUMBER, 9
|
||||
.set USBFS_ep_4__INTC_MASK, 0x400
|
||||
.set USBFS_ep_4__INTC_NUMBER, 10
|
||||
.set USBFS_ep_4__INTC_PRIOR_NUM, 7
|
||||
.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
|
||||
.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10
|
||||
.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
|
||||
.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -381,34 +381,34 @@
|
||||
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
|
||||
|
||||
/* SDCard_BSPIM */
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
|
||||
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL
|
||||
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL
|
||||
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK
|
||||
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
|
||||
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
|
||||
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
|
||||
.set SDCard_BSPIM_RxStsReg__4__POS, 4
|
||||
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
|
||||
@ -416,9 +416,9 @@
|
||||
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
|
||||
.set SDCard_BSPIM_RxStsReg__6__POS, 6
|
||||
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
|
||||
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
|
||||
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
|
||||
@ -436,12 +436,14 @@
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
|
||||
.set SDCard_BSPIM_TxStsReg__0__POS, 0
|
||||
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
|
||||
.set SDCard_BSPIM_TxStsReg__1__POS, 1
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
|
||||
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
|
||||
.set SDCard_BSPIM_TxStsReg__2__POS, 2
|
||||
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
|
||||
@ -449,9 +451,9 @@
|
||||
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
|
||||
.set SDCard_BSPIM_TxStsReg__4__POS, 4
|
||||
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
|
||||
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB05_MSK
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB05_ST
|
||||
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
|
||||
|
||||
/* SD_SCK */
|
||||
.set SD_SCK__0__MASK, 0x04
|
||||
@ -1875,15 +1877,15 @@
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
|
||||
@ -1896,37 +1898,37 @@
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
|
||||
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
|
||||
|
||||
/* SCSI_Out_Ctl */
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
|
||||
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
|
||||
|
||||
/* SCSI_Out_DBx */
|
||||
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
|
||||
@ -2377,10 +2379,10 @@
|
||||
/* SD_RX_DMA_COMPLETE */
|
||||
.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
|
||||
.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10
|
||||
.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4
|
||||
.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20
|
||||
.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5
|
||||
.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
|
||||
.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
|
||||
.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
|
||||
.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
|
||||
.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -2399,10 +2401,10 @@
|
||||
/* SD_TX_DMA_COMPLETE */
|
||||
.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
|
||||
.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20
|
||||
.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5
|
||||
.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40
|
||||
.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6
|
||||
.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
|
||||
.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
|
||||
.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
|
||||
.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
|
||||
.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -2804,10 +2806,10 @@
|
||||
/* SCSI_TX_DMA_COMPLETE */
|
||||
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
|
||||
.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08
|
||||
.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3
|
||||
.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10
|
||||
.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4
|
||||
.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
|
||||
.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
|
||||
.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
|
||||
.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
|
||||
.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -2843,13 +2845,23 @@
|
||||
.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
|
||||
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
|
||||
|
||||
/* SCSI_SEL_ISR */
|
||||
.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
|
||||
.set SCSI_SEL_ISR__INTC_MASK, 0x08
|
||||
.set SCSI_SEL_ISR__INTC_NUMBER, 3
|
||||
.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7
|
||||
.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
|
||||
.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
|
||||
.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
|
||||
|
||||
/* SCSI_Filtered */
|
||||
.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01
|
||||
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
|
||||
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
|
||||
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
|
||||
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
|
||||
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST
|
||||
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
|
||||
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
|
||||
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
|
||||
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
|
||||
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
|
||||
@ -2857,9 +2869,13 @@
|
||||
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
|
||||
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
|
||||
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
|
||||
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB13_MSK
|
||||
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
|
||||
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB13_ST
|
||||
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK
|
||||
.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
|
||||
.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
|
||||
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
|
||||
.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
|
||||
.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
|
||||
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST
|
||||
|
||||
/* SCSI_CTL_PHASE */
|
||||
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
|
||||
@ -2890,12 +2906,12 @@
|
||||
/* SCSI_Parity_Error */
|
||||
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
|
||||
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
|
||||
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
|
||||
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
|
||||
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
|
||||
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
|
||||
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
|
||||
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK
|
||||
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
|
||||
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST
|
||||
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK
|
||||
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
|
||||
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST
|
||||
|
||||
/* Miscellaneous */
|
||||
.set BCLK__BUS_CLK__HZ, 50000000
|
||||
@ -2975,7 +2991,7 @@
|
||||
.set CYDEV_ECC_ENABLE, 0
|
||||
.set CYDEV_HEAP_SIZE, 0x0400
|
||||
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1
|
||||
.set CYDEV_INTR_RISING, 0x0000003E
|
||||
.set CYDEV_INTR_RISING, 0x0000007E
|
||||
.set CYDEV_PROJ_TYPE, 2
|
||||
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
|
||||
.set CYDEV_PROJ_TYPE_LOADABLE, 2
|
||||
|
||||
@ -207,40 +207,40 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
/* USBFS_ep_1 */
|
||||
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
USBFS_ep_1__INTC_MASK EQU 0x40
|
||||
USBFS_ep_1__INTC_NUMBER EQU 6
|
||||
USBFS_ep_1__INTC_MASK EQU 0x80
|
||||
USBFS_ep_1__INTC_NUMBER EQU 7
|
||||
USBFS_ep_1__INTC_PRIOR_NUM EQU 7
|
||||
USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
|
||||
USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
|
||||
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
/* USBFS_ep_2 */
|
||||
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
USBFS_ep_2__INTC_MASK EQU 0x80
|
||||
USBFS_ep_2__INTC_NUMBER EQU 7
|
||||
USBFS_ep_2__INTC_MASK EQU 0x100
|
||||
USBFS_ep_2__INTC_NUMBER EQU 8
|
||||
USBFS_ep_2__INTC_PRIOR_NUM EQU 7
|
||||
USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
|
||||
USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
|
||||
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
/* USBFS_ep_3 */
|
||||
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
USBFS_ep_3__INTC_MASK EQU 0x100
|
||||
USBFS_ep_3__INTC_NUMBER EQU 8
|
||||
USBFS_ep_3__INTC_MASK EQU 0x200
|
||||
USBFS_ep_3__INTC_NUMBER EQU 9
|
||||
USBFS_ep_3__INTC_PRIOR_NUM EQU 7
|
||||
USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
|
||||
USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
|
||||
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
/* USBFS_ep_4 */
|
||||
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
USBFS_ep_4__INTC_MASK EQU 0x200
|
||||
USBFS_ep_4__INTC_NUMBER EQU 9
|
||||
USBFS_ep_4__INTC_MASK EQU 0x400
|
||||
USBFS_ep_4__INTC_NUMBER EQU 10
|
||||
USBFS_ep_4__INTC_PRIOR_NUM EQU 7
|
||||
USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
|
||||
USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
|
||||
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -381,34 +381,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
|
||||
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
|
||||
|
||||
/* SDCard_BSPIM */
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_RxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
|
||||
@ -416,9 +416,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
|
||||
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
|
||||
SDCard_BSPIM_RxStsReg__6__POS EQU 6
|
||||
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
|
||||
@ -436,12 +436,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
|
||||
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
|
||||
SDCard_BSPIM_TxStsReg__0__POS EQU 0
|
||||
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
|
||||
SDCard_BSPIM_TxStsReg__1__POS EQU 1
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
|
||||
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
|
||||
SDCard_BSPIM_TxStsReg__2__POS EQU 2
|
||||
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
|
||||
@ -449,9 +451,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
|
||||
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_TxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
|
||||
|
||||
/* SD_SCK */
|
||||
SD_SCK__0__MASK EQU 0x04
|
||||
@ -1875,15 +1877,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
|
||||
@ -1896,37 +1898,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
|
||||
|
||||
/* SCSI_Out_Ctl */
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
|
||||
|
||||
/* SCSI_Out_DBx */
|
||||
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
|
||||
@ -2377,10 +2379,10 @@ SD_RX_DMA__TERMOUT1_SEL EQU 0
|
||||
/* SD_RX_DMA_COMPLETE */
|
||||
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
|
||||
SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
|
||||
SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20
|
||||
SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5
|
||||
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
|
||||
SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
|
||||
SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
|
||||
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -2399,10 +2401,10 @@ SD_TX_DMA__TERMOUT1_SEL EQU 0
|
||||
/* SD_TX_DMA_COMPLETE */
|
||||
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
|
||||
SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
|
||||
SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40
|
||||
SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6
|
||||
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
|
||||
SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
|
||||
SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
|
||||
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -2804,10 +2806,10 @@ SCSI_TX_DMA__TERMOUT1_SEL EQU 0
|
||||
/* SCSI_TX_DMA_COMPLETE */
|
||||
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
|
||||
SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
|
||||
SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
|
||||
SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
|
||||
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
|
||||
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
|
||||
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
|
||||
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -2843,13 +2845,23 @@ SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
|
||||
SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
/* SCSI_SEL_ISR */
|
||||
SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
SCSI_SEL_ISR__INTC_MASK EQU 0x08
|
||||
SCSI_SEL_ISR__INTC_NUMBER EQU 3
|
||||
SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7
|
||||
SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
|
||||
SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
/* SCSI_Filtered */
|
||||
SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
|
||||
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
|
||||
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
|
||||
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
|
||||
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
|
||||
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
|
||||
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
|
||||
@ -2857,9 +2869,13 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
|
||||
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
|
||||
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
|
||||
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
|
||||
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST
|
||||
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
|
||||
SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
|
||||
|
||||
/* SCSI_CTL_PHASE */
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
@ -2890,12 +2906,12 @@ SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
|
||||
/* SCSI_Parity_Error */
|
||||
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
|
||||
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST
|
||||
|
||||
/* Miscellaneous */
|
||||
BCLK__BUS_CLK__HZ EQU 50000000
|
||||
@ -2975,7 +2991,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
|
||||
CYDEV_ECC_ENABLE EQU 0
|
||||
CYDEV_HEAP_SIZE EQU 0x0400
|
||||
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
|
||||
CYDEV_INTR_RISING EQU 0x0000003E
|
||||
CYDEV_INTR_RISING EQU 0x0000007E
|
||||
CYDEV_PROJ_TYPE EQU 2
|
||||
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
|
||||
CYDEV_PROJ_TYPE_LOADABLE EQU 2
|
||||
|
||||
@ -207,40 +207,40 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
; USBFS_ep_1
|
||||
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
USBFS_ep_1__INTC_MASK EQU 0x40
|
||||
USBFS_ep_1__INTC_NUMBER EQU 6
|
||||
USBFS_ep_1__INTC_MASK EQU 0x80
|
||||
USBFS_ep_1__INTC_NUMBER EQU 7
|
||||
USBFS_ep_1__INTC_PRIOR_NUM EQU 7
|
||||
USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
|
||||
USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
|
||||
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
; USBFS_ep_2
|
||||
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
USBFS_ep_2__INTC_MASK EQU 0x80
|
||||
USBFS_ep_2__INTC_NUMBER EQU 7
|
||||
USBFS_ep_2__INTC_MASK EQU 0x100
|
||||
USBFS_ep_2__INTC_NUMBER EQU 8
|
||||
USBFS_ep_2__INTC_PRIOR_NUM EQU 7
|
||||
USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
|
||||
USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
|
||||
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
; USBFS_ep_3
|
||||
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
USBFS_ep_3__INTC_MASK EQU 0x100
|
||||
USBFS_ep_3__INTC_NUMBER EQU 8
|
||||
USBFS_ep_3__INTC_MASK EQU 0x200
|
||||
USBFS_ep_3__INTC_NUMBER EQU 9
|
||||
USBFS_ep_3__INTC_PRIOR_NUM EQU 7
|
||||
USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
|
||||
USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
|
||||
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
; USBFS_ep_4
|
||||
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
USBFS_ep_4__INTC_MASK EQU 0x200
|
||||
USBFS_ep_4__INTC_NUMBER EQU 9
|
||||
USBFS_ep_4__INTC_MASK EQU 0x400
|
||||
USBFS_ep_4__INTC_NUMBER EQU 10
|
||||
USBFS_ep_4__INTC_PRIOR_NUM EQU 7
|
||||
USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
|
||||
USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
|
||||
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -381,34 +381,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
|
||||
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
|
||||
|
||||
; SDCard_BSPIM
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
|
||||
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
|
||||
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
|
||||
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
|
||||
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
|
||||
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_RxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
|
||||
@ -416,9 +416,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
|
||||
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
|
||||
SDCard_BSPIM_RxStsReg__6__POS EQU 6
|
||||
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
|
||||
@ -436,12 +436,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
|
||||
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
|
||||
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
|
||||
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
|
||||
SDCard_BSPIM_TxStsReg__0__POS EQU 0
|
||||
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
|
||||
SDCard_BSPIM_TxStsReg__1__POS EQU 1
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
|
||||
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
|
||||
SDCard_BSPIM_TxStsReg__2__POS EQU 2
|
||||
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
|
||||
@ -449,9 +451,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
|
||||
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_TxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
|
||||
|
||||
; SD_SCK
|
||||
SD_SCK__0__MASK EQU 0x04
|
||||
@ -1875,15 +1877,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
|
||||
@ -1896,37 +1898,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
|
||||
|
||||
; SCSI_Out_Ctl
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
|
||||
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
|
||||
|
||||
; SCSI_Out_DBx
|
||||
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
|
||||
@ -2377,10 +2379,10 @@ SD_RX_DMA__TERMOUT1_SEL EQU 0
|
||||
; SD_RX_DMA_COMPLETE
|
||||
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
|
||||
SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
|
||||
SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20
|
||||
SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5
|
||||
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
|
||||
SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
|
||||
SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
|
||||
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -2399,10 +2401,10 @@ SD_TX_DMA__TERMOUT1_SEL EQU 0
|
||||
; SD_TX_DMA_COMPLETE
|
||||
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
|
||||
SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
|
||||
SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40
|
||||
SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6
|
||||
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
|
||||
SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
|
||||
SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
|
||||
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -2804,10 +2806,10 @@ SCSI_TX_DMA__TERMOUT1_SEL EQU 0
|
||||
; SCSI_TX_DMA_COMPLETE
|
||||
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
|
||||
SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
|
||||
SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
|
||||
SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
|
||||
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
|
||||
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
|
||||
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
|
||||
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
@ -2843,13 +2845,23 @@ SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
|
||||
SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
; SCSI_SEL_ISR
|
||||
SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
SCSI_SEL_ISR__INTC_MASK EQU 0x08
|
||||
SCSI_SEL_ISR__INTC_NUMBER EQU 3
|
||||
SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7
|
||||
SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
|
||||
SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
; SCSI_Filtered
|
||||
SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
|
||||
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
|
||||
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
|
||||
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
|
||||
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
|
||||
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
|
||||
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
|
||||
@ -2857,9 +2869,13 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
|
||||
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
|
||||
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
|
||||
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
|
||||
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST
|
||||
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
|
||||
SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
|
||||
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
|
||||
|
||||
; SCSI_CTL_PHASE
|
||||
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
@ -2890,12 +2906,12 @@ SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
|
||||
; SCSI_Parity_Error
|
||||
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
|
||||
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
|
||||
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
|
||||
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST
|
||||
|
||||
; Miscellaneous
|
||||
BCLK__BUS_CLK__HZ EQU 50000000
|
||||
@ -2975,7 +2991,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
|
||||
CYDEV_ECC_ENABLE EQU 0
|
||||
CYDEV_HEAP_SIZE EQU 0x0400
|
||||
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
|
||||
CYDEV_INTR_RISING EQU 0x0000003E
|
||||
CYDEV_INTR_RISING EQU 0x0000007E
|
||||
CYDEV_PROJ_TYPE EQU 2
|
||||
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
|
||||
CYDEV_PROJ_TYPE_LOADABLE EQU 2
|
||||
|
||||
@ -69,6 +69,7 @@
|
||||
#include <SCSI_RX_DMA_COMPLETE.h>
|
||||
#include <SCSI_Parity_Error.h>
|
||||
#include <SCSI_Filtered.h>
|
||||
#include <SCSI_SEL_ISR.h>
|
||||
#include <USBFS_Dm_aliases.h>
|
||||
#include <USBFS_Dm.h>
|
||||
#include <USBFS_Dp_aliases.h>
|
||||
|
||||
@ -1,18 +1,11 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
|
||||
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />
|
||||
</block>
|
||||
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />
|
||||
</block>
|
||||
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
@ -71,20 +64,24 @@
|
||||
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
|
||||
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
|
||||
</block>
|
||||
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" />
|
||||
</block>
|
||||
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<register name="SCSI_Filtered_STATUS_REG" address="0x4000646D" bitWidth="8" desc="" />
|
||||
<register name="SCSI_Filtered_MASK_REG" address="0x4000648D" bitWidth="8" desc="" />
|
||||
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649D" bitWidth="8" desc="">
|
||||
<register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" />
|
||||
<register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" />
|
||||
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="">
|
||||
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
|
||||
<value name="ENABLED" value="1" desc="Enable counter" />
|
||||
<value name="DISABLED" value="0" desc="Disable counter" />
|
||||
@ -112,9 +109,9 @@
|
||||
</register>
|
||||
</block>
|
||||
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" />
|
||||
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" />
|
||||
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="">
|
||||
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006466" bitWidth="8" desc="" />
|
||||
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006486" bitWidth="8" desc="" />
|
||||
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006496" bitWidth="8" desc="">
|
||||
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
|
||||
<value name="ENABLED" value="1" desc="Enable counter" />
|
||||
<value name="DISABLED" value="0" desc="Disable counter" />
|
||||
@ -141,23 +138,28 @@
|
||||
</field>
|
||||
</register>
|
||||
</block>
|
||||
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />
|
||||
</block>
|
||||
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />
|
||||
</block>
|
||||
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
@ -165,6 +167,9 @@
|
||||
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
</block>
|
||||
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
|
||||
<block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
@ -261,11 +266,10 @@
|
||||
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
|
||||
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
|
||||
</block>
|
||||
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
</blockRegMap>
|
||||
Binary file not shown.
@ -3124,6 +3124,36 @@
|
||||
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
|
||||
<filters />
|
||||
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
|
||||
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
|
||||
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_SEL_ISR" persistent="">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
|
||||
<dependencies>
|
||||
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_SEL_ISR.c" persistent=".\Generated_Source\PSoC5\SCSI_SEL_ISR.c">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="ARM_C_FILE" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
|
||||
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_SEL_ISR.h" persistent=".\Generated_Source\PSoC5\SCSI_SEL_ISR.h">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="NONE" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
|
||||
</dependencies>
|
||||
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
|
||||
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
|
||||
<filters />
|
||||
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
|
||||
</dependencies>
|
||||
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
|
||||
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
|
||||
@ -3718,6 +3748,15 @@
|
||||
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@Command Line@Command Line" v="" />
|
||||
</name>
|
||||
</platform>
|
||||
<platform>
|
||||
<name v="e9305a93-d091-4da5-bdc7-2813049dcdbf">
|
||||
<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
|
||||
<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Assembly@Command Line@Command Line" v="-s+ -M<> -w+ -r -DNDEBUG --fpu None" />
|
||||
<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@C/C++@Command Line@Command Line" v="-D NDEBUG --debug --endian=little -e --fpu=None --no_wrap_diagnostics" />
|
||||
<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
|
||||
<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Linker@Command Line@Command Line" v="--semihosting --entry __iar_program_start --vfe" />
|
||||
</name>
|
||||
</platform>
|
||||
</platforms>
|
||||
<project_current_platform v="c9323d49-d323-40b8-9b59-cc008d68a989" />
|
||||
<project_current_processor v="CortexM3" />
|
||||
|
||||
@ -6,48 +6,6 @@
|
||||
<addressUnitBits>8</addressUnitBits>
|
||||
<width>32</width>
|
||||
<peripherals>
|
||||
<peripheral>
|
||||
<name>SCSI_Out_Bits</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x4000647B</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>SCSI_Out_Bits_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_Out_Ctl</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x40006478</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>SCSI_Out_Ctl_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>Debug_Timer</name>
|
||||
<description>No description available</description>
|
||||
@ -340,10 +298,31 @@
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_Out_Ctl</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x40006474</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>SCSI_Out_Ctl_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_Filtered</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x4000646D</baseAddress>
|
||||
<baseAddress>0x40006468</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
@ -498,7 +477,7 @@
|
||||
<peripheral>
|
||||
<name>SCSI_Parity_Error</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x40006465</baseAddress>
|
||||
<baseAddress>0x40006466</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
@ -650,6 +629,27 @@
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_Out_Bits</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x40006478</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x0</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>SCSI_Out_Bits_CONTROL_REG</name>
|
||||
<description>No description available</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>SCSI_CTL_PHASE</name>
|
||||
<description>No description available</description>
|
||||
|
||||
Binary file not shown.
@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used))
|
||||
const uint8 cy_meta_loadable[] = {
|
||||
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
|
||||
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
|
||||
0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x24u, 0x04u,
|
||||
0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x30u, 0x04u,
|
||||
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
|
||||
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
|
||||
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@ -781,8 +781,10 @@ private:
|
||||
|
||||
if (!myInitialConfig)
|
||||
{
|
||||
/* This doesn't work properly, and causes crashes.
|
||||
wxCommandEvent loadEvent(wxEVT_NULL, ID_BtnLoad);
|
||||
GetEventHandler()->AddPendingEvent(loadEvent);
|
||||
*/
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user