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Adding minimum command timer.
This commit is contained in:
Michael McMaster
parent
325e6cf2f1
commit
9dab0bcac4
754
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.c
Executable file
754
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.c
Executable file
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@ -0,0 +1,754 @@
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/*******************************************************************************
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* File Name: SCSI_CMD_TIMER.c
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* Version 2.50
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*
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* Description:
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* The Timer component consists of a 8, 16, 24 or 32-bit timer with
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* a selectable period between 2 and 2^Width - 1. The timer may free run
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* or be used as a capture timer as well. The capture can be initiated
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* by a positive or negative edge signal as well as via software.
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* A trigger input can be programmed to enable the timer on rising edge
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* falling edge, either edge or continous run.
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* Interrupts may be generated due to a terminal count condition
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* or a capture event.
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*
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* Note:
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*
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********************************************************************************
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* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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********************************************************************************/
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#include "SCSI_CMD_TIMER.h"
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uint8 SCSI_CMD_TIMER_initVar = 0u;
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/*******************************************************************************
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* Function Name: SCSI_CMD_TIMER_Init
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********************************************************************************
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*
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* Summary:
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* Initialize to the schematic state
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*
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* Parameters:
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* void
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*
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* Return:
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* void
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*
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*******************************************************************************/
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void SCSI_CMD_TIMER_Init(void)
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{
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#if(!SCSI_CMD_TIMER_UsingFixedFunction)
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/* Interrupt State Backup for Critical Region*/
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uint8 SCSI_CMD_TIMER_interruptState;
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#endif /* Interrupt state back up for Fixed Function only */
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#if (SCSI_CMD_TIMER_UsingFixedFunction)
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/* Clear all bits but the enable bit (if it's already set) for Timer operation */
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SCSI_CMD_TIMER_CONTROL &= SCSI_CMD_TIMER_CTRL_ENABLE;
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/* Clear the mode bits for continuous run mode */
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#if (CY_PSOC5A)
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SCSI_CMD_TIMER_CONTROL2 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_MODE_MASK));
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#endif /* Clear bits in CONTROL2 only in PSOC5A */
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#if (CY_PSOC3 || CY_PSOC5LP)
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SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_MODE_MASK));
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#endif /* CONTROL3 register exists only in PSoC3 OR PSoC5LP */
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/* Check if One Shot mode is enabled i.e. RunMode !=0*/
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#if (SCSI_CMD_TIMER_RunModeUsed != 0x0u)
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/* Set 3rd bit of Control register to enable one shot mode */
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SCSI_CMD_TIMER_CONTROL |= 0x04u;
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#endif /* One Shot enabled only when RunModeUsed is not Continuous*/
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#if (SCSI_CMD_TIMER_RunModeUsed == 2)
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#if (CY_PSOC5A)
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/* Set last 2 bits of control2 register if one shot(halt on
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interrupt) is enabled*/
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SCSI_CMD_TIMER_CONTROL2 |= 0x03u;
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#endif /* Set One-Shot Halt on Interrupt bit in CONTROL2 for PSoC5A */
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#if (CY_PSOC3 || CY_PSOC5LP)
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/* Set last 2 bits of control3 register if one shot(halt on
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interrupt) is enabled*/
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SCSI_CMD_TIMER_CONTROL3 |= 0x03u;
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#endif /* Set One-Shot Halt on Interrupt bit in CONTROL3 for PSoC3 or PSoC5LP */
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#endif /* Remove section if One Shot Halt on Interrupt is not enabled */
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#if (SCSI_CMD_TIMER_UsingHWEnable != 0)
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#if (CY_PSOC5A)
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/* Set the default Run Mode of the Timer to Continuous */
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SCSI_CMD_TIMER_CONTROL2 |= SCSI_CMD_TIMER_CTRL_MODE_PULSEWIDTH;
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#endif /* Set Continuous Run Mode in CONTROL2 for PSoC5A */
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#if (CY_PSOC3 || CY_PSOC5LP)
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/* Clear and Set ROD and COD bits of CFG2 register */
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SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_RCOD_MASK));
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SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_RCOD;
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/* Clear and Enable the HW enable bit in CFG2 register */
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SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_ENBL_MASK));
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SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_ENBL;
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/* Set the default Run Mode of the Timer to Continuous */
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SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_MODE_CONTINUOUS;
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#endif /* Set Continuous Run Mode in CONTROL3 for PSoC3ES3 or PSoC5A */
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#endif /* Configure Run Mode with hardware enable */
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/* Clear and Set SYNCTC and SYNCCMP bits of RT1 register */
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SCSI_CMD_TIMER_RT1 &= ((uint8)(~SCSI_CMD_TIMER_RT1_MASK));
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SCSI_CMD_TIMER_RT1 |= SCSI_CMD_TIMER_SYNC;
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/*Enable DSI Sync all all inputs of the Timer*/
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SCSI_CMD_TIMER_RT1 &= ((uint8)(~SCSI_CMD_TIMER_SYNCDSI_MASK));
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SCSI_CMD_TIMER_RT1 |= SCSI_CMD_TIMER_SYNCDSI_EN;
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/* Set the IRQ to use the status register interrupts */
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SCSI_CMD_TIMER_CONTROL2 |= SCSI_CMD_TIMER_CTRL2_IRQ_SEL;
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#endif /* Configuring registers of fixed function implementation */
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/* Set Initial values from Configuration */
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SCSI_CMD_TIMER_WritePeriod(SCSI_CMD_TIMER_INIT_PERIOD);
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SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_INIT_PERIOD);
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#if (SCSI_CMD_TIMER_UsingHWCaptureCounter)/* Capture counter is enabled */
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SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL |= SCSI_CMD_TIMER_CNTR_ENABLE;
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SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_INIT_CAPTURE_COUNT);
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#endif /* Configure capture counter value */
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#if (!SCSI_CMD_TIMER_UsingFixedFunction)
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#if (SCSI_CMD_TIMER_SoftwareCaptureMode)
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SCSI_CMD_TIMER_SetCaptureMode(SCSI_CMD_TIMER_INIT_CAPTURE_MODE);
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#endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */
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#if (SCSI_CMD_TIMER_SoftwareTriggerMode)
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if (0u == (SCSI_CMD_TIMER_CONTROL & SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE))
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{
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SCSI_CMD_TIMER_SetTriggerMode(SCSI_CMD_TIMER_INIT_TRIGGER_MODE);
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}
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#endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */
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/* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
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/* Enter Critical Region*/
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SCSI_CMD_TIMER_interruptState = CyEnterCriticalSection();
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/* Use the interrupt output of the status register for IRQ output */
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SCSI_CMD_TIMER_STATUS_AUX_CTRL |= SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK;
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/* Exit Critical Region*/
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CyExitCriticalSection(SCSI_CMD_TIMER_interruptState);
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#if (SCSI_CMD_TIMER_EnableTriggerMode)
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SCSI_CMD_TIMER_EnableTrigger();
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#endif /* Set Trigger enable bit for UDB implementation in the control register*/
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#if (SCSI_CMD_TIMER_InterruptOnCaptureCount)
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#if (!SCSI_CMD_TIMER_ControlRegRemoved)
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SCSI_CMD_TIMER_SetInterruptCount(SCSI_CMD_TIMER_INIT_INT_CAPTURE_COUNT);
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#endif /* Set interrupt count in control register if control register is not removed */
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#endif /*Set interrupt count in UDB implementation if interrupt count feature is checked.*/
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SCSI_CMD_TIMER_ClearFIFO();
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#endif /* Configure additional features of UDB implementation */
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SCSI_CMD_TIMER_SetInterruptMode(SCSI_CMD_TIMER_INIT_INTERRUPT_MODE);
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}
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/*******************************************************************************
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* Function Name: SCSI_CMD_TIMER_Enable
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********************************************************************************
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*
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* Summary:
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* Enable the Timer
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*
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* Parameters:
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* void
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*
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* Return:
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* void
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*
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*******************************************************************************/
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void SCSI_CMD_TIMER_Enable(void)
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{
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/* Globally Enable the Fixed Function Block chosen */
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#if (SCSI_CMD_TIMER_UsingFixedFunction)
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SCSI_CMD_TIMER_GLOBAL_ENABLE |= SCSI_CMD_TIMER_BLOCK_EN_MASK;
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SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE |= SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK;
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#endif /* Set Enable bit for enabling Fixed function timer*/
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/* Remove assignment if control register is removed */
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#if (!SCSI_CMD_TIMER_ControlRegRemoved || SCSI_CMD_TIMER_UsingFixedFunction)
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SCSI_CMD_TIMER_CONTROL |= SCSI_CMD_TIMER_CTRL_ENABLE;
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#endif /* Remove assignment if control register is removed */
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}
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/*******************************************************************************
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* Function Name: SCSI_CMD_TIMER_Start
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********************************************************************************
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*
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* Summary:
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* The start function initializes the timer with the default values, the
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* enables the timerto begin counting. It does not enable interrupts,
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* the EnableInt command should be called if interrupt generation is required.
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*
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* Parameters:
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* void
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*
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* Return:
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* void
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*
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* Global variables:
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* SCSI_CMD_TIMER_initVar: Is modified when this function is called for the
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* first time. Is used to ensure that initialization happens only once.
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*
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*******************************************************************************/
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void SCSI_CMD_TIMER_Start(void)
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{
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if(SCSI_CMD_TIMER_initVar == 0u)
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{
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SCSI_CMD_TIMER_Init();
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SCSI_CMD_TIMER_initVar = 1u; /* Clear this bit for Initialization */
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}
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/* Enable the Timer */
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SCSI_CMD_TIMER_Enable();
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}
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/*******************************************************************************
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* Function Name: SCSI_CMD_TIMER_Stop
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********************************************************************************
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*
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* Summary:
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* The stop function halts the timer, but does not change any modes or disable
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* interrupts.
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*
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* Parameters:
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* void
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*
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* Return:
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* void
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*
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* Side Effects: If the Enable mode is set to Hardware only then this function
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* has no effect on the operation of the timer.
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*
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*******************************************************************************/
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void SCSI_CMD_TIMER_Stop(void)
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{
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/* Disable Timer */
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#if(!SCSI_CMD_TIMER_ControlRegRemoved || SCSI_CMD_TIMER_UsingFixedFunction)
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SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_ENABLE));
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#endif /* Remove assignment if control register is removed */
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/* Globally disable the Fixed Function Block chosen */
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#if (SCSI_CMD_TIMER_UsingFixedFunction)
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SCSI_CMD_TIMER_GLOBAL_ENABLE &= ((uint8)(~SCSI_CMD_TIMER_BLOCK_EN_MASK));
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SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE &= ((uint8)(~SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK));
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#endif /* Disable global enable for the Timer Fixed function block to stop the Timer*/
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}
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/*******************************************************************************
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* Function Name: SCSI_CMD_TIMER_SetInterruptMode
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********************************************************************************
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*
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* Summary:
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* This function selects which of the interrupt inputs may cause an interrupt.
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* The twosources are caputure and terminal. One, both or neither may
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* be selected.
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*
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* Parameters:
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* interruptMode: This parameter is used to enable interrups on either/or
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* terminal count or capture.
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*
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* Return:
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* void
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*
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*******************************************************************************/
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void SCSI_CMD_TIMER_SetInterruptMode(uint8 interruptMode)
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{
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SCSI_CMD_TIMER_STATUS_MASK = interruptMode;
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}
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/*******************************************************************************
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* Function Name: SCSI_CMD_TIMER_SoftwareCapture
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********************************************************************************
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*
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* Summary:
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* This function forces a capture independent of the capture signal.
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*
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* Parameters:
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* void
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*
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* Return:
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* void
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*
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* Side Effects:
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* An existing hardware capture could be overwritten.
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*
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*******************************************************************************/
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void SCSI_CMD_TIMER_SoftwareCapture(void)
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{
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/* Generate a software capture by reading the counter register */
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(void)SCSI_CMD_TIMER_COUNTER_LSB;
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/* Capture Data is now in the FIFO */
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}
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/*******************************************************************************
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* Function Name: SCSI_CMD_TIMER_ReadStatusRegister
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********************************************************************************
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*
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* Summary:
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* Reads the status register and returns it's state. This function should use
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* defined types for the bit-field information as the bits in this register may
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* be permuteable.
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*
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* Parameters:
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* void
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*
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* Return:
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* The contents of the status register
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*
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* Side Effects:
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* Status register bits may be clear on read.
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*
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*******************************************************************************/
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uint8 SCSI_CMD_TIMER_ReadStatusRegister(void)
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{
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return (SCSI_CMD_TIMER_STATUS);
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}
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#if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove API if control register is removed */
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/*******************************************************************************
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* Function Name: SCSI_CMD_TIMER_ReadControlRegister
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********************************************************************************
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*
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* Summary:
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* Reads the control register and returns it's value.
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*
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* Parameters:
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* void
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*
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* Return:
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* The contents of the control register
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*
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*******************************************************************************/
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uint8 SCSI_CMD_TIMER_ReadControlRegister(void)
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{
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return ((uint8)SCSI_CMD_TIMER_CONTROL);
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}
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/*******************************************************************************
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* Function Name: SCSI_CMD_TIMER_WriteControlRegister
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********************************************************************************
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*
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* Summary:
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* Sets the bit-field of the control register.
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*
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* Parameters:
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* control: The contents of the control register
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*
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* Return:
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*
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*******************************************************************************/
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void SCSI_CMD_TIMER_WriteControlRegister(uint8 control)
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{
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SCSI_CMD_TIMER_CONTROL = control;
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}
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#endif /* Remove API if control register is removed */
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/*******************************************************************************
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* Function Name: SCSI_CMD_TIMER_ReadPeriod
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********************************************************************************
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*
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* Summary:
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* This function returns the current value of the Period.
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*
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* Parameters:
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* void
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*
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* Return:
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* The present value of the counter.
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*
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*******************************************************************************/
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uint16 SCSI_CMD_TIMER_ReadPeriod(void)
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{
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#if(SCSI_CMD_TIMER_UsingFixedFunction)
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return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR));
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#else
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return (CY_GET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR));
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#endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
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}
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/*******************************************************************************
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* Function Name: SCSI_CMD_TIMER_WritePeriod
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********************************************************************************
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*
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* Summary:
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* This function is used to change the period of the counter. The new period
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* will be loaded the next time terminal count is detected.
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*
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* Parameters:
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* period: This value may be between 1 and (2^Resolution)-1. A value of 0 will
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* result in the counter remaining at zero.
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*
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* Return:
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* void
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*
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*******************************************************************************/
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void SCSI_CMD_TIMER_WritePeriod(uint16 period)
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{
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#if(SCSI_CMD_TIMER_UsingFixedFunction)
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uint16 period_temp = (uint16)period;
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CY_SET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR, period_temp);
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#else
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CY_SET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR, period);
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#endif /*Write Period value with appropriate resolution suffix depending on UDB or fixed function implementation */
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}
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/*******************************************************************************
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* Function Name: SCSI_CMD_TIMER_ReadCapture
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********************************************************************************
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*
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* Summary:
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* This function returns the last value captured.
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*
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* Parameters:
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* void
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*
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* Return:
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* Present Capture value.
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*
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*******************************************************************************/
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uint16 SCSI_CMD_TIMER_ReadCapture(void)
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{
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#if(SCSI_CMD_TIMER_UsingFixedFunction)
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return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
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#else
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return (CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
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#endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
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}
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/*******************************************************************************
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* Function Name: SCSI_CMD_TIMER_WriteCounter
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********************************************************************************
|
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*
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* Summary:
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* This funtion is used to set the counter to a specific value
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*
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* Parameters:
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* counter: New counter value.
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*
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* Return:
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* void
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*
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*******************************************************************************/
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void SCSI_CMD_TIMER_WriteCounter(uint16 counter) \
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{
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#if(SCSI_CMD_TIMER_UsingFixedFunction)
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/* This functionality is removed until a FixedFunction HW update to
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* allow this register to be written
|
||||
*/
|
||||
CY_SET_REG16(SCSI_CMD_TIMER_COUNTER_LSB_PTR, (uint16)counter);
|
||||
|
||||
#else
|
||||
CY_SET_REG16(SCSI_CMD_TIMER_COUNTER_LSB_PTR, counter);
|
||||
#endif /* Set Write Counter only for the UDB implementation (Write Counter not available in fixed function Timer */
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ReadCounter
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* This function returns the current counter value.
|
||||
*
|
||||
* Parameters:
|
||||
* void
|
||||
*
|
||||
* Return:
|
||||
* Present compare value.
|
||||
*
|
||||
*******************************************************************************/
|
||||
uint16 SCSI_CMD_TIMER_ReadCounter(void)
|
||||
{
|
||||
|
||||
/* Force capture by reading Accumulator */
|
||||
/* Must first do a software capture to be able to read the counter */
|
||||
/* It is up to the user code to make sure there isn't already captured data in the FIFO */
|
||||
(void)SCSI_CMD_TIMER_COUNTER_LSB;
|
||||
|
||||
/* Read the data from the FIFO (or capture register for Fixed Function)*/
|
||||
#if(SCSI_CMD_TIMER_UsingFixedFunction)
|
||||
return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
|
||||
#else
|
||||
return (CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
|
||||
#endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
|
||||
}
|
||||
|
||||
|
||||
#if(!SCSI_CMD_TIMER_UsingFixedFunction) /* UDB Specific Functions */
|
||||
|
||||
/*******************************************************************************
|
||||
* The functions below this point are only available using the UDB
|
||||
* implementation. If a feature is selected, then the API is enabled.
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#if (SCSI_CMD_TIMER_SoftwareCaptureMode)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_SetCaptureMode
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* This function sets the capture mode to either rising or falling edge.
|
||||
*
|
||||
* Parameters:
|
||||
* captureMode: This parameter sets the capture mode of the UDB capture feature
|
||||
* The parameter values are defined using the
|
||||
* #define SCSI_CMD_TIMER__B_TIMER__CM_NONE 0
|
||||
#define SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE 1
|
||||
#define SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE 2
|
||||
#define SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE 3
|
||||
#define SCSI_CMD_TIMER__B_TIMER__CM_SOFTWARE 4
|
||||
identifiers
|
||||
* The following are the possible values of the parameter
|
||||
* SCSI_CMD_TIMER__B_TIMER__CM_NONE - Set Capture mode to None
|
||||
* SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE - Rising edge of Capture input
|
||||
* SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input
|
||||
* SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE - Either edge of Capture input
|
||||
*
|
||||
* Return:
|
||||
* void
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_SetCaptureMode(uint8 captureMode)
|
||||
{
|
||||
/* This must only set to two bits of the control register associated */
|
||||
captureMode = ((uint8)((uint8)captureMode << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT));
|
||||
captureMode &= (SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK);
|
||||
|
||||
/* Clear the Current Setting */
|
||||
SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK));
|
||||
|
||||
/* Write The New Setting */
|
||||
SCSI_CMD_TIMER_CONTROL |= captureMode;
|
||||
}
|
||||
#endif /* Remove API if Capture Mode is not Software Controlled */
|
||||
|
||||
|
||||
#if (SCSI_CMD_TIMER_SoftwareTriggerMode)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_SetTriggerMode
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* This function sets the trigger input mode
|
||||
*
|
||||
* Parameters:
|
||||
* triggerMode: Pass one of the pre-defined Trigger Modes (except Software)
|
||||
#define SCSI_CMD_TIMER__B_TIMER__TM_NONE 0x00u
|
||||
#define SCSI_CMD_TIMER__B_TIMER__TM_RISINGEDGE 0x04u
|
||||
#define SCSI_CMD_TIMER__B_TIMER__TM_FALLINGEDGE 0x08u
|
||||
#define SCSI_CMD_TIMER__B_TIMER__TM_EITHEREDGE 0x0Cu
|
||||
#define SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE 0x10u
|
||||
*
|
||||
* Return:
|
||||
* void
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_SetTriggerMode(uint8 triggerMode)
|
||||
{
|
||||
/* This must only set to two bits of the control register associated */
|
||||
triggerMode &= SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK;
|
||||
|
||||
/* Clear the Current Setting */
|
||||
SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK));
|
||||
|
||||
/* Write The New Setting */
|
||||
SCSI_CMD_TIMER_CONTROL |= (triggerMode | SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE);
|
||||
|
||||
}
|
||||
#endif /* Remove API if Trigger Mode is not Software Controlled */
|
||||
|
||||
#if (SCSI_CMD_TIMER_EnableTriggerMode)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_EnableTrigger
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Sets the control bit enabling Hardware Trigger mode
|
||||
*
|
||||
* Parameters:
|
||||
* void
|
||||
*
|
||||
* Return:
|
||||
* void
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_EnableTrigger(void)
|
||||
{
|
||||
#if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove assignment if control register is removed */
|
||||
SCSI_CMD_TIMER_CONTROL |= SCSI_CMD_TIMER_CTRL_TRIG_EN;
|
||||
#endif /* Remove code section if control register is not used */
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_DisableTrigger
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Clears the control bit enabling Hardware Trigger mode
|
||||
*
|
||||
* Parameters:
|
||||
* void
|
||||
*
|
||||
* Return:
|
||||
* void
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_DisableTrigger(void)
|
||||
{
|
||||
#if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove assignment if control register is removed */
|
||||
SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_TRIG_EN));
|
||||
#endif /* Remove code section if control register is not used */
|
||||
}
|
||||
#endif /* Remove API is Trigger Mode is set to None */
|
||||
|
||||
|
||||
#if(SCSI_CMD_TIMER_InterruptOnCaptureCount)
|
||||
#if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove API if control register is removed */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_SetInterruptCount
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* This function sets the capture count before an interrupt is triggered.
|
||||
*
|
||||
* Parameters:
|
||||
* interruptCount: A value between 0 and 3 is valid. If the value is 0, then
|
||||
* an interrupt will occur each time a capture occurs.
|
||||
* A value of 1 to 3 will cause the interrupt
|
||||
* to delay by the same number of captures.
|
||||
*
|
||||
* Return:
|
||||
* void
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_SetInterruptCount(uint8 interruptCount)
|
||||
{
|
||||
/* This must only set to two bits of the control register associated */
|
||||
interruptCount &= SCSI_CMD_TIMER_CTRL_INTCNT_MASK;
|
||||
|
||||
/* Clear the Current Setting */
|
||||
SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_INTCNT_MASK));
|
||||
/* Write The New Setting */
|
||||
SCSI_CMD_TIMER_CONTROL |= interruptCount;
|
||||
}
|
||||
#endif /* Remove API if control register is removed */
|
||||
#endif /* SCSI_CMD_TIMER_InterruptOnCaptureCount */
|
||||
|
||||
|
||||
#if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_SetCaptureCount
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* This function sets the capture count
|
||||
*
|
||||
* Parameters:
|
||||
* captureCount: A value between 2 and 127 inclusive is valid. A value of 1
|
||||
* to 127 will cause the interrupt to delay by the same number of
|
||||
* captures.
|
||||
*
|
||||
* Return:
|
||||
* void
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_SetCaptureCount(uint8 captureCount)
|
||||
{
|
||||
SCSI_CMD_TIMER_CAP_COUNT = captureCount;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ReadCaptureCount
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* This function reads the capture count setting
|
||||
*
|
||||
* Parameters:
|
||||
* void
|
||||
*
|
||||
* Return:
|
||||
* Returns the Capture Count Setting
|
||||
*
|
||||
*******************************************************************************/
|
||||
uint8 SCSI_CMD_TIMER_ReadCaptureCount(void)
|
||||
{
|
||||
return ((uint8)SCSI_CMD_TIMER_CAP_COUNT);
|
||||
}
|
||||
#endif /* SCSI_CMD_TIMER_UsingHWCaptureCounter */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ClearFIFO
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* This function clears all capture data from the capture FIFO
|
||||
*
|
||||
* Parameters:
|
||||
* void
|
||||
*
|
||||
* Return:
|
||||
* void
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_ClearFIFO(void)
|
||||
{
|
||||
while(0u != (SCSI_CMD_TIMER_ReadStatusRegister() & SCSI_CMD_TIMER_STATUS_FIFONEMP))
|
||||
{
|
||||
(void)SCSI_CMD_TIMER_ReadCapture();
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* UDB Specific Functions */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
439
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.h
Executable file
439
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.h
Executable file
|
|
@ -0,0 +1,439 @@
|
|||
/*******************************************************************************
|
||||
* File Name: SCSI_CMD_TIMER.h
|
||||
* Version 2.50
|
||||
*
|
||||
* Description:
|
||||
* Contains the function prototypes and constants available to the timer
|
||||
* user module.
|
||||
*
|
||||
* Note:
|
||||
* None
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
********************************************************************************/
|
||||
|
||||
#if !defined(CY_Timer_v2_30_SCSI_CMD_TIMER_H)
|
||||
#define CY_Timer_v2_30_SCSI_CMD_TIMER_H
|
||||
|
||||
#include "cytypes.h"
|
||||
#include "cyfitter.h"
|
||||
#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */
|
||||
|
||||
extern uint8 SCSI_CMD_TIMER_initVar;
|
||||
|
||||
/* Check to see if required defines such as CY_PSOC5LP are available */
|
||||
/* They are defined starting with cy_boot v3.0 */
|
||||
#if !defined (CY_PSOC5LP)
|
||||
#error Component Timer_v2_50 requires cy_boot v3.0 or later
|
||||
#endif /* (CY_ PSOC5LP) */
|
||||
|
||||
|
||||
/**************************************
|
||||
* Parameter Defaults
|
||||
**************************************/
|
||||
|
||||
#define SCSI_CMD_TIMER_Resolution 16u
|
||||
#define SCSI_CMD_TIMER_UsingFixedFunction 1u
|
||||
#define SCSI_CMD_TIMER_UsingHWCaptureCounter 0u
|
||||
#define SCSI_CMD_TIMER_SoftwareCaptureMode 0u
|
||||
#define SCSI_CMD_TIMER_SoftwareTriggerMode 0u
|
||||
#define SCSI_CMD_TIMER_UsingHWEnable 0u
|
||||
#define SCSI_CMD_TIMER_EnableTriggerMode 0u
|
||||
#define SCSI_CMD_TIMER_InterruptOnCaptureCount 0u
|
||||
#define SCSI_CMD_TIMER_RunModeUsed 1u
|
||||
#define SCSI_CMD_TIMER_ControlRegRemoved 0u
|
||||
|
||||
|
||||
/***************************************
|
||||
* Type defines
|
||||
***************************************/
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* Sleep Wakeup Backup structure for Timer Component
|
||||
*************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
uint8 TimerEnableState;
|
||||
#if(!SCSI_CMD_TIMER_UsingFixedFunction)
|
||||
#if (CY_UDB_V0)
|
||||
uint16 TimerUdb; /* Timer internal counter value */
|
||||
uint16 TimerPeriod; /* Timer Period value */
|
||||
uint8 InterruptMaskValue; /* Timer Compare Value */
|
||||
#if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
|
||||
uint8 TimerCaptureCounter; /* Timer Capture Counter Value */
|
||||
#endif /* variable declaration for backing up Capture Counter value*/
|
||||
#endif /* variables for non retention registers in CY_UDB_V0 */
|
||||
|
||||
#if (CY_UDB_V1)
|
||||
uint16 TimerUdb;
|
||||
uint8 InterruptMaskValue;
|
||||
#if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
|
||||
uint8 TimerCaptureCounter;
|
||||
#endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
|
||||
#endif /* (CY_UDB_V1) */
|
||||
|
||||
#if (!SCSI_CMD_TIMER_ControlRegRemoved)
|
||||
uint8 TimerControlRegister;
|
||||
#endif /* variable declaration for backing up enable state of the Timer */
|
||||
#endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */
|
||||
}SCSI_CMD_TIMER_backupStruct;
|
||||
|
||||
|
||||
/***************************************
|
||||
* Function Prototypes
|
||||
***************************************/
|
||||
|
||||
void SCSI_CMD_TIMER_Start(void) ;
|
||||
void SCSI_CMD_TIMER_Stop(void) ;
|
||||
|
||||
void SCSI_CMD_TIMER_SetInterruptMode(uint8 interruptMode) ;
|
||||
uint8 SCSI_CMD_TIMER_ReadStatusRegister(void) ;
|
||||
/* Deprecated function. Do not use this in future. Retained for backward compatibility */
|
||||
#define SCSI_CMD_TIMER_GetInterruptSource() SCSI_CMD_TIMER_ReadStatusRegister()
|
||||
|
||||
#if(!SCSI_CMD_TIMER_ControlRegRemoved)
|
||||
uint8 SCSI_CMD_TIMER_ReadControlRegister(void) ;
|
||||
void SCSI_CMD_TIMER_WriteControlRegister(uint8 control) \
|
||||
;
|
||||
#endif /* (!SCSI_CMD_TIMER_ControlRegRemoved) */
|
||||
|
||||
uint16 SCSI_CMD_TIMER_ReadPeriod(void) ;
|
||||
void SCSI_CMD_TIMER_WritePeriod(uint16 period) \
|
||||
;
|
||||
uint16 SCSI_CMD_TIMER_ReadCounter(void) ;
|
||||
void SCSI_CMD_TIMER_WriteCounter(uint16 counter) \
|
||||
;
|
||||
uint16 SCSI_CMD_TIMER_ReadCapture(void) ;
|
||||
void SCSI_CMD_TIMER_SoftwareCapture(void) ;
|
||||
|
||||
|
||||
#if(!SCSI_CMD_TIMER_UsingFixedFunction) /* UDB Prototypes */
|
||||
#if (SCSI_CMD_TIMER_SoftwareCaptureMode)
|
||||
void SCSI_CMD_TIMER_SetCaptureMode(uint8 captureMode) ;
|
||||
#endif /* (!SCSI_CMD_TIMER_UsingFixedFunction) */
|
||||
|
||||
#if (SCSI_CMD_TIMER_SoftwareTriggerMode)
|
||||
void SCSI_CMD_TIMER_SetTriggerMode(uint8 triggerMode) ;
|
||||
#endif /* (SCSI_CMD_TIMER_SoftwareTriggerMode) */
|
||||
#if (SCSI_CMD_TIMER_EnableTriggerMode)
|
||||
void SCSI_CMD_TIMER_EnableTrigger(void) ;
|
||||
void SCSI_CMD_TIMER_DisableTrigger(void) ;
|
||||
#endif /* (SCSI_CMD_TIMER_EnableTriggerMode) */
|
||||
|
||||
#if(SCSI_CMD_TIMER_InterruptOnCaptureCount)
|
||||
#if(!SCSI_CMD_TIMER_ControlRegRemoved)
|
||||
void SCSI_CMD_TIMER_SetInterruptCount(uint8 interruptCount) \
|
||||
;
|
||||
#endif /* (!SCSI_CMD_TIMER_ControlRegRemoved) */
|
||||
#endif /* (SCSI_CMD_TIMER_InterruptOnCaptureCount) */
|
||||
|
||||
#if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
|
||||
void SCSI_CMD_TIMER_SetCaptureCount(uint8 captureCount) \
|
||||
;
|
||||
uint8 SCSI_CMD_TIMER_ReadCaptureCount(void) ;
|
||||
#endif /* (SCSI_CMD_TIMER_UsingHWCaptureCounter) */
|
||||
|
||||
void SCSI_CMD_TIMER_ClearFIFO(void) ;
|
||||
#endif /* UDB Prototypes */
|
||||
|
||||
/* Sleep Retention APIs */
|
||||
void SCSI_CMD_TIMER_Init(void) ;
|
||||
void SCSI_CMD_TIMER_Enable(void) ;
|
||||
void SCSI_CMD_TIMER_SaveConfig(void) ;
|
||||
void SCSI_CMD_TIMER_RestoreConfig(void) ;
|
||||
void SCSI_CMD_TIMER_Sleep(void) ;
|
||||
void SCSI_CMD_TIMER_Wakeup(void) ;
|
||||
|
||||
|
||||
/***************************************
|
||||
* Enumerated Types and Parameters
|
||||
***************************************/
|
||||
|
||||
/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */
|
||||
#define SCSI_CMD_TIMER__B_TIMER__CM_NONE 0
|
||||
#define SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE 1
|
||||
#define SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE 2
|
||||
#define SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE 3
|
||||
#define SCSI_CMD_TIMER__B_TIMER__CM_SOFTWARE 4
|
||||
|
||||
|
||||
|
||||
/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */
|
||||
#define SCSI_CMD_TIMER__B_TIMER__TM_NONE 0x00u
|
||||
#define SCSI_CMD_TIMER__B_TIMER__TM_RISINGEDGE 0x04u
|
||||
#define SCSI_CMD_TIMER__B_TIMER__TM_FALLINGEDGE 0x08u
|
||||
#define SCSI_CMD_TIMER__B_TIMER__TM_EITHEREDGE 0x0Cu
|
||||
#define SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE 0x10u
|
||||
|
||||
|
||||
/***************************************
|
||||
* Initialial Parameter Constants
|
||||
***************************************/
|
||||
|
||||
#define SCSI_CMD_TIMER_INIT_PERIOD 1199u
|
||||
#define SCSI_CMD_TIMER_INIT_CAPTURE_MODE ((uint8)((uint8)0u << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT))
|
||||
#define SCSI_CMD_TIMER_INIT_TRIGGER_MODE ((uint8)((uint8)0u << SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT))
|
||||
#if (SCSI_CMD_TIMER_UsingFixedFunction)
|
||||
#define SCSI_CMD_TIMER_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT)) | \
|
||||
((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT)))
|
||||
#else
|
||||
#define SCSI_CMD_TIMER_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT)) | \
|
||||
((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT)) | \
|
||||
((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK_SHIFT)))
|
||||
#endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
|
||||
#define SCSI_CMD_TIMER_INIT_CAPTURE_COUNT (2u)
|
||||
#define SCSI_CMD_TIMER_INIT_INT_CAPTURE_COUNT ((uint8)((uint8)(1u - 1u) << SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT))
|
||||
|
||||
|
||||
/***************************************
|
||||
* Registers
|
||||
***************************************/
|
||||
|
||||
#if (SCSI_CMD_TIMER_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */
|
||||
|
||||
|
||||
/***************************************
|
||||
* Fixed Function Registers
|
||||
***************************************/
|
||||
|
||||
#define SCSI_CMD_TIMER_STATUS (*(reg8 *) SCSI_CMD_TIMER_TimerHW__SR0 )
|
||||
/* In Fixed Function Block Status and Mask are the same register */
|
||||
#define SCSI_CMD_TIMER_STATUS_MASK (*(reg8 *) SCSI_CMD_TIMER_TimerHW__SR0 )
|
||||
#define SCSI_CMD_TIMER_CONTROL (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG0)
|
||||
#define SCSI_CMD_TIMER_CONTROL2 (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG1)
|
||||
#define SCSI_CMD_TIMER_CONTROL2_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerHW__CFG1)
|
||||
#define SCSI_CMD_TIMER_RT1 (*(reg8 *) SCSI_CMD_TIMER_TimerHW__RT1)
|
||||
#define SCSI_CMD_TIMER_RT1_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerHW__RT1)
|
||||
|
||||
#if (CY_PSOC3 || CY_PSOC5LP)
|
||||
#define SCSI_CMD_TIMER_CONTROL3 (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG2)
|
||||
#define SCSI_CMD_TIMER_CONTROL3_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerHW__CFG2)
|
||||
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
|
||||
#define SCSI_CMD_TIMER_GLOBAL_ENABLE (*(reg8 *) SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG)
|
||||
#define SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE (*(reg8 *) SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG)
|
||||
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerHW__CAP0 )
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerHW__CAP0 )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerHW__PER0 )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerHW__PER0 )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerHW__CNT_CMP0 )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerHW__CNT_CMP0 )
|
||||
|
||||
|
||||
/***************************************
|
||||
* Register Constants
|
||||
***************************************/
|
||||
|
||||
/* Fixed Function Block Chosen */
|
||||
#define SCSI_CMD_TIMER_BLOCK_EN_MASK SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK
|
||||
#define SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK
|
||||
|
||||
/* Control Register Bit Locations */
|
||||
/* Interrupt Count - Not valid for Fixed Function Block */
|
||||
#define SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT 0x00u
|
||||
/* Trigger Polarity - Not valid for Fixed Function Block */
|
||||
#define SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT 0x00u
|
||||
/* Trigger Enable - Not valid for Fixed Function Block */
|
||||
#define SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT 0x00u
|
||||
/* Capture Polarity - Not valid for Fixed Function Block */
|
||||
#define SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT 0x00u
|
||||
/* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */
|
||||
#define SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT 0x00u
|
||||
|
||||
/* Control Register Bit Masks */
|
||||
#define SCSI_CMD_TIMER_CTRL_ENABLE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT))
|
||||
|
||||
/* Control2 Register Bit Masks */
|
||||
/* As defined in Register Map, Part of the TMRX_CFG1 register */
|
||||
#define SCSI_CMD_TIMER_CTRL2_IRQ_SEL_SHIFT 0x00u
|
||||
#define SCSI_CMD_TIMER_CTRL2_IRQ_SEL ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL2_IRQ_SEL_SHIFT))
|
||||
|
||||
#if (CY_PSOC5A)
|
||||
/* Use CFG1 Mode bits to set run mode */
|
||||
/* As defined by Verilog Implementation */
|
||||
#define SCSI_CMD_TIMER_CTRL_MODE_SHIFT 0x01u
|
||||
#define SCSI_CMD_TIMER_CTRL_MODE_MASK ((uint8)((uint8)0x07u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT))
|
||||
#endif /* (CY_PSOC5A) */
|
||||
#if (CY_PSOC3 || CY_PSOC5LP)
|
||||
/* Control3 Register Bit Locations */
|
||||
#define SCSI_CMD_TIMER_CTRL_RCOD_SHIFT 0x02u
|
||||
#define SCSI_CMD_TIMER_CTRL_ENBL_SHIFT 0x00u
|
||||
#define SCSI_CMD_TIMER_CTRL_MODE_SHIFT 0x00u
|
||||
|
||||
/* Control3 Register Bit Masks */
|
||||
#define SCSI_CMD_TIMER_CTRL_RCOD_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */
|
||||
#define SCSI_CMD_TIMER_CTRL_ENBL_MASK ((uint8)((uint8)0x80u << SCSI_CMD_TIMER_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */
|
||||
#define SCSI_CMD_TIMER_CTRL_MODE_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT)) /* Run mode bit mask */
|
||||
|
||||
#define SCSI_CMD_TIMER_CTRL_RCOD ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_RCOD_SHIFT))
|
||||
#define SCSI_CMD_TIMER_CTRL_ENBL ((uint8)((uint8)0x80u << SCSI_CMD_TIMER_CTRL_ENBL_SHIFT))
|
||||
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
|
||||
|
||||
/*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */
|
||||
#define SCSI_CMD_TIMER_RT1_SHIFT 0x04u
|
||||
/* Sync TC and CMP bit masks */
|
||||
#define SCSI_CMD_TIMER_RT1_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_RT1_SHIFT))
|
||||
#define SCSI_CMD_TIMER_SYNC ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_RT1_SHIFT))
|
||||
#define SCSI_CMD_TIMER_SYNCDSI_SHIFT 0x00u
|
||||
/* Sync all DSI inputs with Mask */
|
||||
#define SCSI_CMD_TIMER_SYNCDSI_MASK ((uint8)((uint8)0x0Fu << SCSI_CMD_TIMER_SYNCDSI_SHIFT))
|
||||
/* Sync all DSI inputs */
|
||||
#define SCSI_CMD_TIMER_SYNCDSI_EN ((uint8)((uint8)0x0Fu << SCSI_CMD_TIMER_SYNCDSI_SHIFT))
|
||||
|
||||
#define SCSI_CMD_TIMER_CTRL_MODE_PULSEWIDTH ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT))
|
||||
#define SCSI_CMD_TIMER_CTRL_MODE_PERIOD ((uint8)((uint8)0x02u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT))
|
||||
#define SCSI_CMD_TIMER_CTRL_MODE_CONTINUOUS ((uint8)((uint8)0x00u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT))
|
||||
|
||||
/* Status Register Bit Locations */
|
||||
/* As defined in Register Map, part of TMRX_SR0 register */
|
||||
#define SCSI_CMD_TIMER_STATUS_TC_SHIFT 0x07u
|
||||
/* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
|
||||
#define SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT 0x06u
|
||||
/* As defined in Register Map, part of TMRX_SR0 register */
|
||||
#define SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT (SCSI_CMD_TIMER_STATUS_TC_SHIFT - 0x04u)
|
||||
/* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
|
||||
#define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT (SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT - 0x04u)
|
||||
|
||||
/* Status Register Bit Masks */
|
||||
#define SCSI_CMD_TIMER_STATUS_TC ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT))
|
||||
#define SCSI_CMD_TIMER_STATUS_CAPTURE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT))
|
||||
/* Interrupt Enable Bit-Mask for interrupt on TC */
|
||||
#define SCSI_CMD_TIMER_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT))
|
||||
/* Interrupt Enable Bit-Mask for interrupt on Capture */
|
||||
#define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT))
|
||||
|
||||
#else /* UDB Registers and Register Constants */
|
||||
|
||||
|
||||
/***************************************
|
||||
* UDB Registers
|
||||
***************************************/
|
||||
|
||||
#define SCSI_CMD_TIMER_STATUS (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__STATUS_REG )
|
||||
#define SCSI_CMD_TIMER_STATUS_MASK (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__MASK_REG)
|
||||
#define SCSI_CMD_TIMER_STATUS_AUX_CTRL (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG)
|
||||
#define SCSI_CMD_TIMER_CONTROL (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG )
|
||||
|
||||
#if(SCSI_CMD_TIMER_Resolution <= 8u) /* 8-bit Timer */
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
|
||||
#elif(SCSI_CMD_TIMER_Resolution <= 16u) /* 8-bit Timer */
|
||||
#if(CY_PSOC3) /* 8-bit addres space */
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
|
||||
#else /* 16-bit address space */
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
|
||||
#endif /* CY_PSOC3 */
|
||||
#elif(SCSI_CMD_TIMER_Resolution <= 24u)/* 24-bit Timer */
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
|
||||
#else /* 32-bit Timer */
|
||||
#if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
|
||||
#else /* 32-bit address space */
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
|
||||
#define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
|
||||
#define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
|
||||
#define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
|
||||
#endif /* CY_PSOC3 || CY_PSOC5 */
|
||||
#endif
|
||||
|
||||
#if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
|
||||
#define SCSI_CMD_TIMER_CAP_COUNT (*(reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__PERIOD_REG )
|
||||
#define SCSI_CMD_TIMER_CAP_COUNT_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__PERIOD_REG )
|
||||
#define SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL (*(reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
|
||||
#define SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
|
||||
#endif /* (SCSI_CMD_TIMER_UsingHWCaptureCounter) */
|
||||
|
||||
|
||||
/***************************************
|
||||
* Register Constants
|
||||
***************************************/
|
||||
|
||||
/* Control Register Bit Locations */
|
||||
#define SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT 0x00u /* As defined by Verilog Implementation */
|
||||
#define SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT 0x02u /* As defined by Verilog Implementation */
|
||||
#define SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT 0x04u /* As defined by Verilog Implementation */
|
||||
#define SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT 0x05u /* As defined by Verilog Implementation */
|
||||
#define SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT 0x07u /* As defined by Verilog Implementation */
|
||||
|
||||
/* Control Register Bit Masks */
|
||||
#define SCSI_CMD_TIMER_CTRL_INTCNT_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT))
|
||||
#define SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT))
|
||||
#define SCSI_CMD_TIMER_CTRL_TRIG_EN ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT))
|
||||
#define SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT))
|
||||
#define SCSI_CMD_TIMER_CTRL_ENABLE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT))
|
||||
|
||||
/* Bit Counter (7-bit) Control Register Bit Definitions */
|
||||
/* As defined by the Register map for the AUX Control Register */
|
||||
#define SCSI_CMD_TIMER_CNTR_ENABLE 0x20u
|
||||
|
||||
/* Status Register Bit Locations */
|
||||
#define SCSI_CMD_TIMER_STATUS_TC_SHIFT 0x00u /* As defined by Verilog Implementation */
|
||||
#define SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT 0x01u /* As defined by Verilog Implementation */
|
||||
#define SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT SCSI_CMD_TIMER_STATUS_TC_SHIFT
|
||||
#define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT
|
||||
#define SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT 0x02u /* As defined by Verilog Implementation */
|
||||
#define SCSI_CMD_TIMER_STATUS_FIFONEMP_SHIFT 0x03u /* As defined by Verilog Implementation */
|
||||
#define SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK_SHIFT SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT
|
||||
|
||||
/* Status Register Bit Masks */
|
||||
/* Sticky TC Event Bit-Mask */
|
||||
#define SCSI_CMD_TIMER_STATUS_TC ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT))
|
||||
/* Sticky Capture Event Bit-Mask */
|
||||
#define SCSI_CMD_TIMER_STATUS_CAPTURE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT))
|
||||
/* Interrupt Enable Bit-Mask */
|
||||
#define SCSI_CMD_TIMER_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT))
|
||||
/* Interrupt Enable Bit-Mask */
|
||||
#define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT))
|
||||
/* NOT-Sticky FIFO Full Bit-Mask */
|
||||
#define SCSI_CMD_TIMER_STATUS_FIFOFULL ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT))
|
||||
/* NOT-Sticky FIFO Not Empty Bit-Mask */
|
||||
#define SCSI_CMD_TIMER_STATUS_FIFONEMP ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFONEMP_SHIFT))
|
||||
/* Interrupt Enable Bit-Mask */
|
||||
#define SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT))
|
||||
|
||||
#define SCSI_CMD_TIMER_STATUS_ACTL_INT_EN 0x10u /* As defined for the ACTL Register */
|
||||
|
||||
/* Datapath Auxillary Control Register definitions */
|
||||
#define SCSI_CMD_TIMER_AUX_CTRL_FIFO0_CLR 0x01u /* As defined by Register map */
|
||||
#define SCSI_CMD_TIMER_AUX_CTRL_FIFO1_CLR 0x02u /* As defined by Register map */
|
||||
#define SCSI_CMD_TIMER_AUX_CTRL_FIFO0_LVL 0x04u /* As defined by Register map */
|
||||
#define SCSI_CMD_TIMER_AUX_CTRL_FIFO1_LVL 0x08u /* As defined by Register map */
|
||||
#define SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK 0x10u /* As defined for the ACTL Register */
|
||||
|
||||
#endif /* Implementation Specific Registers and Register Constants */
|
||||
|
||||
#endif /* CY_Timer_v2_30_SCSI_CMD_TIMER_H */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
356
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.c
Executable file
356
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.c
Executable file
|
|
@ -0,0 +1,356 @@
|
|||
/*******************************************************************************
|
||||
* File Name: SCSI_CMD_TIMER_ISR.c
|
||||
* Version 1.70
|
||||
*
|
||||
* Description:
|
||||
* API for controlling the state of an interrupt.
|
||||
*
|
||||
*
|
||||
* Note:
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#include <cydevice_trm.h>
|
||||
#include <CyLib.h>
|
||||
#include <SCSI_CMD_TIMER_ISR.h>
|
||||
|
||||
#if !defined(SCSI_CMD_TIMER_ISR__REMOVED) /* Check for removal by optimization */
|
||||
|
||||
/*******************************************************************************
|
||||
* Place your includes, defines and code here
|
||||
********************************************************************************/
|
||||
/* `#START SCSI_CMD_TIMER_ISR_intc` */
|
||||
|
||||
/* `#END` */
|
||||
|
||||
#ifndef CYINT_IRQ_BASE
|
||||
#define CYINT_IRQ_BASE 16
|
||||
#endif /* CYINT_IRQ_BASE */
|
||||
#ifndef CYINT_VECT_TABLE
|
||||
#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
|
||||
#endif /* CYINT_VECT_TABLE */
|
||||
|
||||
/* Declared in startup, used to set unused interrupts to. */
|
||||
CY_ISR_PROTO(IntDefaultHandler);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ISR_Start
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Set up the interrupt and enable it.
|
||||
*
|
||||
* Parameters:
|
||||
* None
|
||||
*
|
||||
* Return:
|
||||
* None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_ISR_Start(void)
|
||||
{
|
||||
/* For all we know the interrupt is active. */
|
||||
SCSI_CMD_TIMER_ISR_Disable();
|
||||
|
||||
/* Set the ISR to point to the SCSI_CMD_TIMER_ISR Interrupt. */
|
||||
SCSI_CMD_TIMER_ISR_SetVector(&SCSI_CMD_TIMER_ISR_Interrupt);
|
||||
|
||||
/* Set the priority. */
|
||||
SCSI_CMD_TIMER_ISR_SetPriority((uint8)SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER);
|
||||
|
||||
/* Enable it. */
|
||||
SCSI_CMD_TIMER_ISR_Enable();
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ISR_StartEx
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Set up the interrupt and enable it.
|
||||
*
|
||||
* Parameters:
|
||||
* address: Address of the ISR to set in the interrupt vector table.
|
||||
*
|
||||
* Return:
|
||||
* None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_ISR_StartEx(cyisraddress address)
|
||||
{
|
||||
/* For all we know the interrupt is active. */
|
||||
SCSI_CMD_TIMER_ISR_Disable();
|
||||
|
||||
/* Set the ISR to point to the SCSI_CMD_TIMER_ISR Interrupt. */
|
||||
SCSI_CMD_TIMER_ISR_SetVector(address);
|
||||
|
||||
/* Set the priority. */
|
||||
SCSI_CMD_TIMER_ISR_SetPriority((uint8)SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER);
|
||||
|
||||
/* Enable it. */
|
||||
SCSI_CMD_TIMER_ISR_Enable();
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ISR_Stop
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Disables and removes the interrupt.
|
||||
*
|
||||
* Parameters:
|
||||
*
|
||||
* Return:
|
||||
* None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_ISR_Stop(void)
|
||||
{
|
||||
/* Disable this interrupt. */
|
||||
SCSI_CMD_TIMER_ISR_Disable();
|
||||
|
||||
/* Set the ISR to point to the passive one. */
|
||||
SCSI_CMD_TIMER_ISR_SetVector(&IntDefaultHandler);
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ISR_Interrupt
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* The default Interrupt Service Routine for SCSI_CMD_TIMER_ISR.
|
||||
*
|
||||
* Add custom code between the coments to keep the next version of this file
|
||||
* from over writting your code.
|
||||
*
|
||||
* Parameters:
|
||||
*
|
||||
* Return:
|
||||
* None
|
||||
*
|
||||
*******************************************************************************/
|
||||
CY_ISR(SCSI_CMD_TIMER_ISR_Interrupt)
|
||||
{
|
||||
/* Place your Interrupt code here. */
|
||||
/* `#START SCSI_CMD_TIMER_ISR_Interrupt` */
|
||||
|
||||
/* `#END` */
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ISR_SetVector
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Change the ISR vector for the Interrupt. Note calling SCSI_CMD_TIMER_ISR_Start
|
||||
* will override any effect this method would have had. To set the vector
|
||||
* before the component has been started use SCSI_CMD_TIMER_ISR_StartEx instead.
|
||||
*
|
||||
* Parameters:
|
||||
* address: Address of the ISR to set in the interrupt vector table.
|
||||
*
|
||||
* Return:
|
||||
* None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_ISR_SetVector(cyisraddress address)
|
||||
{
|
||||
cyisraddress * ramVectorTable;
|
||||
|
||||
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
|
||||
|
||||
ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_CMD_TIMER_ISR__INTC_NUMBER] = address;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ISR_GetVector
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Gets the "address" of the current ISR vector for the Interrupt.
|
||||
*
|
||||
* Parameters:
|
||||
* None
|
||||
*
|
||||
* Return:
|
||||
* Address of the ISR in the interrupt vector table.
|
||||
*
|
||||
*******************************************************************************/
|
||||
cyisraddress SCSI_CMD_TIMER_ISR_GetVector(void)
|
||||
{
|
||||
cyisraddress * ramVectorTable;
|
||||
|
||||
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
|
||||
|
||||
return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_CMD_TIMER_ISR__INTC_NUMBER];
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ISR_SetPriority
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Sets the Priority of the Interrupt. Note calling SCSI_CMD_TIMER_ISR_Start
|
||||
* or SCSI_CMD_TIMER_ISR_StartEx will override any effect this method
|
||||
* would have had. This method should only be called after
|
||||
* SCSI_CMD_TIMER_ISR_Start or SCSI_CMD_TIMER_ISR_StartEx has been called. To set
|
||||
* the initial priority for the component use the cydwr file in the tool.
|
||||
*
|
||||
* Parameters:
|
||||
* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
|
||||
*
|
||||
* Return:
|
||||
* None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_ISR_SetPriority(uint8 priority)
|
||||
{
|
||||
*SCSI_CMD_TIMER_ISR_INTC_PRIOR = priority << 5;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ISR_GetPriority
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Gets the Priority of the Interrupt.
|
||||
*
|
||||
* Parameters:
|
||||
* None
|
||||
*
|
||||
* Return:
|
||||
* Priority of the interrupt. 0 - 7, 0 being the highest.
|
||||
*
|
||||
*******************************************************************************/
|
||||
uint8 SCSI_CMD_TIMER_ISR_GetPriority(void)
|
||||
{
|
||||
uint8 priority;
|
||||
|
||||
|
||||
priority = *SCSI_CMD_TIMER_ISR_INTC_PRIOR >> 5;
|
||||
|
||||
return priority;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ISR_Enable
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Enables the interrupt.
|
||||
*
|
||||
* Parameters:
|
||||
* None
|
||||
*
|
||||
* Return:
|
||||
* None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_ISR_Enable(void)
|
||||
{
|
||||
/* Enable the general interrupt. */
|
||||
*SCSI_CMD_TIMER_ISR_INTC_SET_EN = SCSI_CMD_TIMER_ISR__INTC_MASK;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ISR_GetState
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Gets the state (enabled, disabled) of the Interrupt.
|
||||
*
|
||||
* Parameters:
|
||||
* None
|
||||
*
|
||||
* Return:
|
||||
* 1 if enabled, 0 if disabled.
|
||||
*
|
||||
*******************************************************************************/
|
||||
uint8 SCSI_CMD_TIMER_ISR_GetState(void)
|
||||
{
|
||||
/* Get the state of the general interrupt. */
|
||||
return ((*SCSI_CMD_TIMER_ISR_INTC_SET_EN & (uint32)SCSI_CMD_TIMER_ISR__INTC_MASK) != 0u) ? 1u:0u;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ISR_Disable
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Disables the Interrupt.
|
||||
*
|
||||
* Parameters:
|
||||
* None
|
||||
*
|
||||
* Return:
|
||||
* None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_ISR_Disable(void)
|
||||
{
|
||||
/* Disable the general interrupt. */
|
||||
*SCSI_CMD_TIMER_ISR_INTC_CLR_EN = SCSI_CMD_TIMER_ISR__INTC_MASK;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ISR_SetPending
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Causes the Interrupt to enter the pending state, a software method of
|
||||
* generating the interrupt.
|
||||
*
|
||||
* Parameters:
|
||||
* None
|
||||
*
|
||||
* Return:
|
||||
* None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_ISR_SetPending(void)
|
||||
{
|
||||
*SCSI_CMD_TIMER_ISR_INTC_SET_PD = SCSI_CMD_TIMER_ISR__INTC_MASK;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_ISR_ClearPending
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Clears a pending interrupt.
|
||||
*
|
||||
* Parameters:
|
||||
* None
|
||||
*
|
||||
* Return:
|
||||
* None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_ISR_ClearPending(void)
|
||||
{
|
||||
*SCSI_CMD_TIMER_ISR_INTC_CLR_PD = SCSI_CMD_TIMER_ISR__INTC_MASK;
|
||||
}
|
||||
|
||||
#endif /* End check for removal by optimization */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
70
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.h
Executable file
70
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.h
Executable file
|
|
@ -0,0 +1,70 @@
|
|||
/*******************************************************************************
|
||||
* File Name: SCSI_CMD_TIMER_ISR.h
|
||||
* Version 1.70
|
||||
*
|
||||
* Description:
|
||||
* Provides the function definitions for the Interrupt Controller.
|
||||
*
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
#if !defined(CY_ISR_SCSI_CMD_TIMER_ISR_H)
|
||||
#define CY_ISR_SCSI_CMD_TIMER_ISR_H
|
||||
|
||||
|
||||
#include <cytypes.h>
|
||||
#include <cyfitter.h>
|
||||
|
||||
/* Interrupt Controller API. */
|
||||
void SCSI_CMD_TIMER_ISR_Start(void);
|
||||
void SCSI_CMD_TIMER_ISR_StartEx(cyisraddress address);
|
||||
void SCSI_CMD_TIMER_ISR_Stop(void);
|
||||
|
||||
CY_ISR_PROTO(SCSI_CMD_TIMER_ISR_Interrupt);
|
||||
|
||||
void SCSI_CMD_TIMER_ISR_SetVector(cyisraddress address);
|
||||
cyisraddress SCSI_CMD_TIMER_ISR_GetVector(void);
|
||||
|
||||
void SCSI_CMD_TIMER_ISR_SetPriority(uint8 priority);
|
||||
uint8 SCSI_CMD_TIMER_ISR_GetPriority(void);
|
||||
|
||||
void SCSI_CMD_TIMER_ISR_Enable(void);
|
||||
uint8 SCSI_CMD_TIMER_ISR_GetState(void);
|
||||
void SCSI_CMD_TIMER_ISR_Disable(void);
|
||||
|
||||
void SCSI_CMD_TIMER_ISR_SetPending(void);
|
||||
void SCSI_CMD_TIMER_ISR_ClearPending(void);
|
||||
|
||||
|
||||
/* Interrupt Controller Constants */
|
||||
|
||||
/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_CMD_TIMER_ISR ISR. */
|
||||
#define SCSI_CMD_TIMER_ISR_INTC_VECTOR ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_VECT)
|
||||
|
||||
/* Address of the SCSI_CMD_TIMER_ISR ISR priority. */
|
||||
#define SCSI_CMD_TIMER_ISR_INTC_PRIOR ((reg8 *) SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG)
|
||||
|
||||
/* Priority of the SCSI_CMD_TIMER_ISR interrupt. */
|
||||
#define SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM
|
||||
|
||||
/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_CMD_TIMER_ISR interrupt. */
|
||||
#define SCSI_CMD_TIMER_ISR_INTC_SET_EN ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG)
|
||||
|
||||
/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_CMD_TIMER_ISR interrupt. */
|
||||
#define SCSI_CMD_TIMER_ISR_INTC_CLR_EN ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG)
|
||||
|
||||
/* Address of the INTC.SET_PD[x] register to set the SCSI_CMD_TIMER_ISR interrupt state to pending. */
|
||||
#define SCSI_CMD_TIMER_ISR_INTC_SET_PD ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG)
|
||||
|
||||
/* Address of the INTC.CLR_PD[x] register to clear the SCSI_CMD_TIMER_ISR interrupt. */
|
||||
#define SCSI_CMD_TIMER_ISR_INTC_CLR_PD ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG)
|
||||
|
||||
|
||||
#endif /* CY_ISR_SCSI_CMD_TIMER_ISR_H */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
194
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_PM.c
Executable file
194
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_PM.c
Executable file
|
|
@ -0,0 +1,194 @@
|
|||
/*******************************************************************************
|
||||
* File Name: SCSI_CMD_TIMER_PM.c
|
||||
* Version 2.50
|
||||
*
|
||||
* Description:
|
||||
* This file provides the power management source code to API for the
|
||||
* Timer.
|
||||
*
|
||||
* Note:
|
||||
* None
|
||||
*
|
||||
*******************************************************************************
|
||||
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
********************************************************************************/
|
||||
|
||||
#include "SCSI_CMD_TIMER.h"
|
||||
static SCSI_CMD_TIMER_backupStruct SCSI_CMD_TIMER_backup;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_SaveConfig
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Save the current user configuration
|
||||
*
|
||||
* Parameters:
|
||||
* void
|
||||
*
|
||||
* Return:
|
||||
* void
|
||||
*
|
||||
* Global variables:
|
||||
* SCSI_CMD_TIMER_backup: Variables of this global structure are modified to
|
||||
* store the values of non retention configuration registers when Sleep() API is
|
||||
* called.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_SaveConfig(void)
|
||||
{
|
||||
#if (!SCSI_CMD_TIMER_UsingFixedFunction)
|
||||
/* Backup the UDB non-rentention registers for CY_UDB_V0 */
|
||||
#if (CY_UDB_V0)
|
||||
SCSI_CMD_TIMER_backup.TimerUdb = SCSI_CMD_TIMER_ReadCounter();
|
||||
SCSI_CMD_TIMER_backup.TimerPeriod = SCSI_CMD_TIMER_ReadPeriod();
|
||||
SCSI_CMD_TIMER_backup.InterruptMaskValue = SCSI_CMD_TIMER_STATUS_MASK;
|
||||
#if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
|
||||
SCSI_CMD_TIMER_backup.TimerCaptureCounter = SCSI_CMD_TIMER_ReadCaptureCount();
|
||||
#endif /* Backup the UDB non-rentention register capture counter for CY_UDB_V0 */
|
||||
#endif /* Backup the UDB non-rentention registers for CY_UDB_V0 */
|
||||
|
||||
#if (CY_UDB_V1)
|
||||
SCSI_CMD_TIMER_backup.TimerUdb = SCSI_CMD_TIMER_ReadCounter();
|
||||
SCSI_CMD_TIMER_backup.InterruptMaskValue = SCSI_CMD_TIMER_STATUS_MASK;
|
||||
#if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
|
||||
SCSI_CMD_TIMER_backup.TimerCaptureCounter = SCSI_CMD_TIMER_ReadCaptureCount();
|
||||
#endif /* Back Up capture counter register */
|
||||
#endif /* Backup non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
|
||||
|
||||
#if(!SCSI_CMD_TIMER_ControlRegRemoved)
|
||||
SCSI_CMD_TIMER_backup.TimerControlRegister = SCSI_CMD_TIMER_ReadControlRegister();
|
||||
#endif /* Backup the enable state of the Timer component */
|
||||
#endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_RestoreConfig
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Restores the current user configuration.
|
||||
*
|
||||
* Parameters:
|
||||
* void
|
||||
*
|
||||
* Return:
|
||||
* void
|
||||
*
|
||||
* Global variables:
|
||||
* SCSI_CMD_TIMER_backup: Variables of this global structure are used to
|
||||
* restore the values of non retention registers on wakeup from sleep mode.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_RestoreConfig(void)
|
||||
{
|
||||
#if (!SCSI_CMD_TIMER_UsingFixedFunction)
|
||||
/* Restore the UDB non-rentention registers for CY_UDB_V0 */
|
||||
#if (CY_UDB_V0)
|
||||
/* Interrupt State Backup for Critical Region*/
|
||||
uint8 SCSI_CMD_TIMER_interruptState;
|
||||
|
||||
SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_backup.TimerUdb);
|
||||
SCSI_CMD_TIMER_WritePeriod(SCSI_CMD_TIMER_backup.TimerPeriod);
|
||||
/* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
|
||||
/* Enter Critical Region*/
|
||||
SCSI_CMD_TIMER_interruptState = CyEnterCriticalSection();
|
||||
/* Use the interrupt output of the status register for IRQ output */
|
||||
SCSI_CMD_TIMER_STATUS_AUX_CTRL |= SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK;
|
||||
/* Exit Critical Region*/
|
||||
CyExitCriticalSection(SCSI_CMD_TIMER_interruptState);
|
||||
SCSI_CMD_TIMER_STATUS_MASK =SCSI_CMD_TIMER_backup.InterruptMaskValue;
|
||||
#if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
|
||||
SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_backup.TimerCaptureCounter);
|
||||
#endif /* Restore the UDB non-rentention register capture counter for CY_UDB_V0 */
|
||||
#endif /* Restore the UDB non-rentention registers for CY_UDB_V0 */
|
||||
|
||||
#if (CY_UDB_V1)
|
||||
SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_backup.TimerUdb);
|
||||
SCSI_CMD_TIMER_STATUS_MASK =SCSI_CMD_TIMER_backup.InterruptMaskValue;
|
||||
#if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
|
||||
SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_backup.TimerCaptureCounter);
|
||||
#endif /* Restore Capture counter register*/
|
||||
#endif /* Restore up non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
|
||||
|
||||
#if(!SCSI_CMD_TIMER_ControlRegRemoved)
|
||||
SCSI_CMD_TIMER_WriteControlRegister(SCSI_CMD_TIMER_backup.TimerControlRegister);
|
||||
#endif /* Restore the enable state of the Timer component */
|
||||
#endif /* Restore non retention registers in the UDB implementation only */
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_Sleep
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Stop and Save the user configuration
|
||||
*
|
||||
* Parameters:
|
||||
* void
|
||||
*
|
||||
* Return:
|
||||
* void
|
||||
*
|
||||
* Global variables:
|
||||
* SCSI_CMD_TIMER_backup.TimerEnableState: Is modified depending on the
|
||||
* enable state of the block before entering sleep mode.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_Sleep(void)
|
||||
{
|
||||
#if(!SCSI_CMD_TIMER_ControlRegRemoved)
|
||||
/* Save Counter's enable state */
|
||||
if(SCSI_CMD_TIMER_CTRL_ENABLE == (SCSI_CMD_TIMER_CONTROL & SCSI_CMD_TIMER_CTRL_ENABLE))
|
||||
{
|
||||
/* Timer is enabled */
|
||||
SCSI_CMD_TIMER_backup.TimerEnableState = 1u;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Timer is disabled */
|
||||
SCSI_CMD_TIMER_backup.TimerEnableState = 0u;
|
||||
}
|
||||
#endif /* Back up enable state from the Timer control register */
|
||||
SCSI_CMD_TIMER_Stop();
|
||||
SCSI_CMD_TIMER_SaveConfig();
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SCSI_CMD_TIMER_Wakeup
|
||||
********************************************************************************
|
||||
*
|
||||
* Summary:
|
||||
* Restores and enables the user configuration
|
||||
*
|
||||
* Parameters:
|
||||
* void
|
||||
*
|
||||
* Return:
|
||||
* void
|
||||
*
|
||||
* Global variables:
|
||||
* SCSI_CMD_TIMER_backup.enableState: Is used to restore the enable state of
|
||||
* block on wakeup from sleep mode.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SCSI_CMD_TIMER_Wakeup(void)
|
||||
{
|
||||
SCSI_CMD_TIMER_RestoreConfig();
|
||||
#if(!SCSI_CMD_TIMER_ControlRegRemoved)
|
||||
if(SCSI_CMD_TIMER_backup.TimerEnableState == 1u)
|
||||
{ /* Enable Timer's operation */
|
||||
SCSI_CMD_TIMER_Enable();
|
||||
} /* Do nothing if Timer was disabled before */
|
||||
#endif /* Remove this code section if Control register is removed */
|
||||
}
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -3,6 +3,34 @@
|
|||
#include <cydevice.h>
|
||||
#include <cydevice_trm.h>
|
||||
|
||||
/* SCSI_CMD_TIMER_TimerHW */
|
||||
#define SCSI_CMD_TIMER_TimerHW__CAP0 CYREG_TMR0_CAP0
|
||||
#define SCSI_CMD_TIMER_TimerHW__CAP1 CYREG_TMR0_CAP1
|
||||
#define SCSI_CMD_TIMER_TimerHW__CFG0 CYREG_TMR0_CFG0
|
||||
#define SCSI_CMD_TIMER_TimerHW__CFG1 CYREG_TMR0_CFG1
|
||||
#define SCSI_CMD_TIMER_TimerHW__CFG2 CYREG_TMR0_CFG2
|
||||
#define SCSI_CMD_TIMER_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0
|
||||
#define SCSI_CMD_TIMER_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1
|
||||
#define SCSI_CMD_TIMER_TimerHW__PER0 CYREG_TMR0_PER0
|
||||
#define SCSI_CMD_TIMER_TimerHW__PER1 CYREG_TMR0_PER1
|
||||
#define SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3
|
||||
#define SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK 0x01u
|
||||
#define SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3
|
||||
#define SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK 0x01u
|
||||
#define SCSI_CMD_TIMER_TimerHW__RT0 CYREG_TMR0_RT0
|
||||
#define SCSI_CMD_TIMER_TimerHW__RT1 CYREG_TMR0_RT1
|
||||
#define SCSI_CMD_TIMER_TimerHW__SR0 CYREG_TMR0_SR0
|
||||
|
||||
/* SCSI_CMD_TIMER_ISR */
|
||||
#define SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
||||
#define SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
||||
#define SCSI_CMD_TIMER_ISR__INTC_MASK 0x01u
|
||||
#define SCSI_CMD_TIMER_ISR__INTC_NUMBER 0u
|
||||
#define SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM 7u
|
||||
#define SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_0
|
||||
#define SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
||||
#define SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
||||
|
||||
/* USBFS_bus_reset */
|
||||
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
||||
#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
||||
|
|
@ -504,8 +532,8 @@
|
|||
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
|
||||
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK
|
||||
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
|
||||
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
|
||||
#define SDCard_BSPIM_RxStsReg__4__POS 4
|
||||
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
|
||||
|
|
@ -513,13 +541,13 @@
|
|||
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
|
||||
#define SDCard_BSPIM_RxStsReg__6__POS 6
|
||||
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
|
||||
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST
|
||||
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
|
||||
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST
|
||||
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
|
||||
#define SDCard_BSPIM_TxStsReg__0__POS 0
|
||||
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
|
||||
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
|
||||
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
|
||||
#define SDCard_BSPIM_TxStsReg__1__POS 1
|
||||
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
|
||||
|
|
@ -529,9 +557,9 @@
|
|||
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
|
||||
#define SDCard_BSPIM_TxStsReg__4__POS 4
|
||||
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
|
||||
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK
|
||||
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST
|
||||
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK
|
||||
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
|
||||
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1
|
||||
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0
|
||||
|
|
@ -565,24 +593,24 @@
|
|||
/* SCSI_CTL_IO */
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
|
||||
#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
|
||||
|
||||
/* SCSI_In_DBx */
|
||||
#define SCSI_In_DBx__0__AG CYREG_PRT12_AG
|
||||
|
|
@ -1041,8 +1069,8 @@
|
|||
/* scsiTarget */
|
||||
#define scsiTarget_StatusReg__0__MASK 0x01u
|
||||
#define scsiTarget_StatusReg__0__POS 0
|
||||
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
|
||||
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST
|
||||
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
|
||||
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
|
||||
#define scsiTarget_StatusReg__1__MASK 0x02u
|
||||
#define scsiTarget_StatusReg__1__POS 1
|
||||
#define scsiTarget_StatusReg__2__MASK 0x04u
|
||||
|
|
@ -1050,76 +1078,80 @@
|
|||
#define scsiTarget_StatusReg__3__MASK 0x08u
|
||||
#define scsiTarget_StatusReg__3__POS 3
|
||||
#define scsiTarget_StatusReg__MASK 0x0Fu
|
||||
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB14_MSK
|
||||
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL
|
||||
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB14_ST
|
||||
#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
|
||||
#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST
|
||||
#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB13_MSK
|
||||
#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
|
||||
#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
|
||||
#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL
|
||||
#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB13_ST_CTL
|
||||
#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB13_ST_CTL
|
||||
#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB13_ST
|
||||
#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
|
||||
#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
|
||||
#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
|
||||
#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
|
||||
#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
|
||||
#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
|
||||
#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
|
||||
#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
|
||||
#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
|
||||
#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
|
||||
#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB13_CTL
|
||||
#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
|
||||
#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB13_CTL
|
||||
#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
|
||||
#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
|
||||
#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB13_MSK
|
||||
#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
|
||||
#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB13_14_A0
|
||||
#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB13_14_A1
|
||||
#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB13_14_D0
|
||||
#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB13_14_D1
|
||||
#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
|
||||
#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB13_14_F0
|
||||
#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB13_14_F1
|
||||
#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB13_A0_A1
|
||||
#define scsiTarget_datapath__A0_REG CYREG_B0_UDB13_A0
|
||||
#define scsiTarget_datapath__A1_REG CYREG_B0_UDB13_A1
|
||||
#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB13_D0_D1
|
||||
#define scsiTarget_datapath__D0_REG CYREG_B0_UDB13_D0
|
||||
#define scsiTarget_datapath__D1_REG CYREG_B0_UDB13_D1
|
||||
#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB13_ACTL
|
||||
#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB13_F0_F1
|
||||
#define scsiTarget_datapath__F0_REG CYREG_B0_UDB13_F0
|
||||
#define scsiTarget_datapath__F1_REG CYREG_B0_UDB13_F1
|
||||
#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
|
||||
#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
|
||||
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK
|
||||
#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
|
||||
#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
|
||||
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
|
||||
#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL
|
||||
#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL
|
||||
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST
|
||||
#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
|
||||
#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
|
||||
#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK
|
||||
#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
|
||||
#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL
|
||||
#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL
|
||||
#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST
|
||||
#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
|
||||
#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
|
||||
#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
|
||||
#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
|
||||
#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
|
||||
#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
|
||||
#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
|
||||
#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
|
||||
#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
|
||||
#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
|
||||
#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL
|
||||
#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
|
||||
#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL
|
||||
#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
|
||||
#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK
|
||||
#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0
|
||||
#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1
|
||||
#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0
|
||||
#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1
|
||||
#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
|
||||
#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0
|
||||
#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1
|
||||
#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1
|
||||
#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0
|
||||
#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1
|
||||
#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1
|
||||
#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0
|
||||
#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1
|
||||
#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL
|
||||
#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1
|
||||
#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0
|
||||
#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1
|
||||
#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
|
||||
|
||||
/* SD_Clk_Ctl */
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
|
||||
#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
|
||||
|
||||
/* USBFS_ep_0 */
|
||||
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
||||
|
|
@ -1134,20 +1166,20 @@
|
|||
/* USBFS_ep_1 */
|
||||
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
||||
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
||||
#define USBFS_ep_1__INTC_MASK 0x01u
|
||||
#define USBFS_ep_1__INTC_NUMBER 0u
|
||||
#define USBFS_ep_1__INTC_MASK 0x02u
|
||||
#define USBFS_ep_1__INTC_NUMBER 1u
|
||||
#define USBFS_ep_1__INTC_PRIOR_NUM 7u
|
||||
#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0
|
||||
#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_1
|
||||
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
||||
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
||||
|
||||
/* USBFS_ep_2 */
|
||||
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
||||
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
||||
#define USBFS_ep_2__INTC_MASK 0x02u
|
||||
#define USBFS_ep_2__INTC_NUMBER 1u
|
||||
#define USBFS_ep_2__INTC_MASK 0x04u
|
||||
#define USBFS_ep_2__INTC_NUMBER 2u
|
||||
#define USBFS_ep_2__INTC_PRIOR_NUM 7u
|
||||
#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1
|
||||
#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_2
|
||||
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
||||
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
||||
|
||||
|
|
@ -2722,7 +2754,7 @@
|
|||
#define CYDEV_ECC_ENABLE 0
|
||||
#define CYDEV_HEAP_SIZE 0x1000
|
||||
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
|
||||
#define CYDEV_INTR_RISING 0x00000000u
|
||||
#define CYDEV_INTR_RISING 0x00000001u
|
||||
#define CYDEV_PROJ_TYPE 2
|
||||
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
|
||||
#define CYDEV_PROJ_TYPE_LOADABLE 2
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -3,6 +3,34 @@
|
|||
.include "cydevicegnu.inc"
|
||||
.include "cydevicegnu_trm.inc"
|
||||
|
||||
/* SCSI_CMD_TIMER_TimerHW */
|
||||
.set SCSI_CMD_TIMER_TimerHW__CAP0, CYREG_TMR0_CAP0
|
||||
.set SCSI_CMD_TIMER_TimerHW__CAP1, CYREG_TMR0_CAP1
|
||||
.set SCSI_CMD_TIMER_TimerHW__CFG0, CYREG_TMR0_CFG0
|
||||
.set SCSI_CMD_TIMER_TimerHW__CFG1, CYREG_TMR0_CFG1
|
||||
.set SCSI_CMD_TIMER_TimerHW__CFG2, CYREG_TMR0_CFG2
|
||||
.set SCSI_CMD_TIMER_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0
|
||||
.set SCSI_CMD_TIMER_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1
|
||||
.set SCSI_CMD_TIMER_TimerHW__PER0, CYREG_TMR0_PER0
|
||||
.set SCSI_CMD_TIMER_TimerHW__PER1, CYREG_TMR0_PER1
|
||||
.set SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3
|
||||
.set SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK, 0x01
|
||||
.set SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3
|
||||
.set SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK, 0x01
|
||||
.set SCSI_CMD_TIMER_TimerHW__RT0, CYREG_TMR0_RT0
|
||||
.set SCSI_CMD_TIMER_TimerHW__RT1, CYREG_TMR0_RT1
|
||||
.set SCSI_CMD_TIMER_TimerHW__SR0, CYREG_TMR0_SR0
|
||||
|
||||
/* SCSI_CMD_TIMER_ISR */
|
||||
.set SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
.set SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
|
||||
.set SCSI_CMD_TIMER_ISR__INTC_MASK, 0x01
|
||||
.set SCSI_CMD_TIMER_ISR__INTC_NUMBER, 0
|
||||
.set SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM, 7
|
||||
.set SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
|
||||
.set SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
|
||||
.set SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
|
||||
|
||||
/* USBFS_bus_reset */
|
||||
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
|
||||
|
|
@ -504,8 +532,8 @@
|
|||
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK
|
||||
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
|
||||
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
|
||||
.set SDCard_BSPIM_RxStsReg__4__POS, 4
|
||||
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
|
||||
|
|
@ -513,13 +541,13 @@
|
|||
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
|
||||
.set SDCard_BSPIM_RxStsReg__6__POS, 6
|
||||
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
|
||||
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
|
||||
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
|
||||
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
|
||||
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
|
||||
.set SDCard_BSPIM_TxStsReg__0__POS, 0
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
|
||||
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
|
||||
.set SDCard_BSPIM_TxStsReg__1__POS, 1
|
||||
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
|
||||
|
|
@ -529,9 +557,9 @@
|
|||
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
|
||||
.set SDCard_BSPIM_TxStsReg__4__POS, 4
|
||||
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
|
||||
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
|
||||
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
|
||||
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1
|
||||
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0
|
||||
|
|
@ -565,24 +593,24 @@
|
|||
/* SCSI_CTL_IO */
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
|
||||
.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
|
||||
|
||||
/* SCSI_In_DBx */
|
||||
.set SCSI_In_DBx__0__AG, CYREG_PRT12_AG
|
||||
|
|
@ -1041,8 +1069,8 @@
|
|||
/* scsiTarget */
|
||||
.set scsiTarget_StatusReg__0__MASK, 0x01
|
||||
.set scsiTarget_StatusReg__0__POS, 0
|
||||
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
|
||||
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST
|
||||
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
|
||||
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
|
||||
.set scsiTarget_StatusReg__1__MASK, 0x02
|
||||
.set scsiTarget_StatusReg__1__POS, 1
|
||||
.set scsiTarget_StatusReg__2__MASK, 0x04
|
||||
|
|
@ -1050,76 +1078,80 @@
|
|||
.set scsiTarget_StatusReg__3__MASK, 0x08
|
||||
.set scsiTarget_StatusReg__3__POS, 3
|
||||
.set scsiTarget_StatusReg__MASK, 0x0F
|
||||
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB14_MSK
|
||||
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
|
||||
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB14_ST
|
||||
.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
|
||||
.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST
|
||||
.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB13_MSK
|
||||
.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
|
||||
.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
|
||||
.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
|
||||
.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB13_ST_CTL
|
||||
.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB13_ST_CTL
|
||||
.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB13_ST
|
||||
.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
|
||||
.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
|
||||
.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
|
||||
.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
|
||||
.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
|
||||
.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
|
||||
.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
|
||||
.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
|
||||
.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
|
||||
.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
|
||||
.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB13_CTL
|
||||
.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
|
||||
.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB13_CTL
|
||||
.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
|
||||
.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
|
||||
.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB13_MSK
|
||||
.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
|
||||
.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB13_14_A0
|
||||
.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB13_14_A1
|
||||
.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB13_14_D0
|
||||
.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB13_14_D1
|
||||
.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
|
||||
.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB13_14_F0
|
||||
.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB13_14_F1
|
||||
.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB13_A0_A1
|
||||
.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB13_A0
|
||||
.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB13_A1
|
||||
.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB13_D0_D1
|
||||
.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB13_D0
|
||||
.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB13_D1
|
||||
.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
|
||||
.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB13_F0_F1
|
||||
.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB13_F0
|
||||
.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB13_F1
|
||||
.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
|
||||
.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
|
||||
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK
|
||||
.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
|
||||
.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
|
||||
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
|
||||
.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL
|
||||
.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL
|
||||
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST
|
||||
.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
|
||||
.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
|
||||
.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK
|
||||
.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
|
||||
.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL
|
||||
.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL
|
||||
.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST
|
||||
.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
|
||||
.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
|
||||
.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
|
||||
.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
|
||||
.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL
|
||||
.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
|
||||
.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL
|
||||
.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
|
||||
.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK
|
||||
.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0
|
||||
.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1
|
||||
.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0
|
||||
.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1
|
||||
.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
|
||||
.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0
|
||||
.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1
|
||||
.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1
|
||||
.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0
|
||||
.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1
|
||||
.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1
|
||||
.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0
|
||||
.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1
|
||||
.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
|
||||
.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1
|
||||
.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0
|
||||
.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1
|
||||
.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
|
||||
|
||||
/* SD_Clk_Ctl */
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
|
||||
.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
|
||||
|
||||
/* USBFS_ep_0 */
|
||||
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
|
|
@ -1134,20 +1166,20 @@
|
|||
/* USBFS_ep_1 */
|
||||
.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
|
||||
.set USBFS_ep_1__INTC_MASK, 0x01
|
||||
.set USBFS_ep_1__INTC_NUMBER, 0
|
||||
.set USBFS_ep_1__INTC_MASK, 0x02
|
||||
.set USBFS_ep_1__INTC_NUMBER, 1
|
||||
.set USBFS_ep_1__INTC_PRIOR_NUM, 7
|
||||
.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
|
||||
.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
|
||||
.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
|
||||
.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
|
||||
|
||||
/* USBFS_ep_2 */
|
||||
.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
|
||||
.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
|
||||
.set USBFS_ep_2__INTC_MASK, 0x02
|
||||
.set USBFS_ep_2__INTC_NUMBER, 1
|
||||
.set USBFS_ep_2__INTC_MASK, 0x04
|
||||
.set USBFS_ep_2__INTC_NUMBER, 2
|
||||
.set USBFS_ep_2__INTC_PRIOR_NUM, 7
|
||||
.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
|
||||
.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
|
||||
.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
|
||||
.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
|
||||
|
||||
|
|
@ -2722,7 +2754,7 @@
|
|||
.set CYDEV_ECC_ENABLE, 0
|
||||
.set CYDEV_HEAP_SIZE, 0x1000
|
||||
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1
|
||||
.set CYDEV_INTR_RISING, 0x00000000
|
||||
.set CYDEV_INTR_RISING, 0x00000001
|
||||
.set CYDEV_PROJ_TYPE, 2
|
||||
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
|
||||
.set CYDEV_PROJ_TYPE_LOADABLE, 2
|
||||
|
|
|
|||
|
|
@ -3,6 +3,34 @@
|
|||
INCLUDE cydeviceiar.inc
|
||||
INCLUDE cydeviceiar_trm.inc
|
||||
|
||||
/* SCSI_CMD_TIMER_TimerHW */
|
||||
SCSI_CMD_TIMER_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
|
||||
SCSI_CMD_TIMER_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
|
||||
SCSI_CMD_TIMER_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
|
||||
SCSI_CMD_TIMER_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
|
||||
SCSI_CMD_TIMER_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
|
||||
SCSI_CMD_TIMER_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
|
||||
SCSI_CMD_TIMER_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
|
||||
SCSI_CMD_TIMER_TimerHW__PER0 EQU CYREG_TMR0_PER0
|
||||
SCSI_CMD_TIMER_TimerHW__PER1 EQU CYREG_TMR0_PER1
|
||||
SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
|
||||
SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK EQU 0x01
|
||||
SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
|
||||
SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK EQU 0x01
|
||||
SCSI_CMD_TIMER_TimerHW__RT0 EQU CYREG_TMR0_RT0
|
||||
SCSI_CMD_TIMER_TimerHW__RT1 EQU CYREG_TMR0_RT1
|
||||
SCSI_CMD_TIMER_TimerHW__SR0 EQU CYREG_TMR0_SR0
|
||||
|
||||
/* SCSI_CMD_TIMER_ISR */
|
||||
SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
SCSI_CMD_TIMER_ISR__INTC_MASK EQU 0x01
|
||||
SCSI_CMD_TIMER_ISR__INTC_NUMBER EQU 0
|
||||
SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM EQU 7
|
||||
SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
|
||||
SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
/* USBFS_bus_reset */
|
||||
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
|
|
@ -504,8 +532,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
|||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
|
||||
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_RxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
|
||||
|
|
@ -513,13 +541,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
|
|||
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
|
||||
SDCard_BSPIM_RxStsReg__6__POS EQU 6
|
||||
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
|
||||
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
|
||||
SDCard_BSPIM_TxStsReg__0__POS EQU 0
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
|
||||
SDCard_BSPIM_TxStsReg__1__POS EQU 1
|
||||
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
|
||||
|
|
@ -529,9 +557,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
|
|||
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_TxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
|
||||
|
|
@ -565,24 +593,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
|||
/* SCSI_CTL_IO */
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
|
||||
|
||||
/* SCSI_In_DBx */
|
||||
SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG
|
||||
|
|
@ -1041,8 +1069,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02
|
|||
/* scsiTarget */
|
||||
scsiTarget_StatusReg__0__MASK EQU 0x01
|
||||
scsiTarget_StatusReg__0__POS EQU 0
|
||||
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
|
||||
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST
|
||||
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
|
||||
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
|
||||
scsiTarget_StatusReg__1__MASK EQU 0x02
|
||||
scsiTarget_StatusReg__1__POS EQU 1
|
||||
scsiTarget_StatusReg__2__MASK EQU 0x04
|
||||
|
|
@ -1050,76 +1078,80 @@ scsiTarget_StatusReg__2__POS EQU 2
|
|||
scsiTarget_StatusReg__3__MASK EQU 0x08
|
||||
scsiTarget_StatusReg__3__POS EQU 3
|
||||
scsiTarget_StatusReg__MASK EQU 0x0F
|
||||
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK
|
||||
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
|
||||
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST
|
||||
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
|
||||
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK
|
||||
scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST
|
||||
scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL
|
||||
scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL
|
||||
scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK
|
||||
scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0
|
||||
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1
|
||||
scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0
|
||||
scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1
|
||||
scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0
|
||||
scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1
|
||||
scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1
|
||||
scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0
|
||||
scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1
|
||||
scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1
|
||||
scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0
|
||||
scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1
|
||||
scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1
|
||||
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0
|
||||
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1
|
||||
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
|
||||
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
|
||||
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
|
||||
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
|
||||
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK
|
||||
scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
|
||||
scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST
|
||||
scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
|
||||
scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL
|
||||
scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL
|
||||
scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK
|
||||
scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0
|
||||
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1
|
||||
scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0
|
||||
scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1
|
||||
scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0
|
||||
scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1
|
||||
scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1
|
||||
scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0
|
||||
scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1
|
||||
scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1
|
||||
scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0
|
||||
scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1
|
||||
scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
|
||||
scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1
|
||||
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0
|
||||
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1
|
||||
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
|
||||
/* SD_Clk_Ctl */
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
|
||||
/* USBFS_ep_0 */
|
||||
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
|
|
@ -1134,20 +1166,20 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
|||
/* USBFS_ep_1 */
|
||||
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
USBFS_ep_1__INTC_MASK EQU 0x01
|
||||
USBFS_ep_1__INTC_NUMBER EQU 0
|
||||
USBFS_ep_1__INTC_MASK EQU 0x02
|
||||
USBFS_ep_1__INTC_NUMBER EQU 1
|
||||
USBFS_ep_1__INTC_PRIOR_NUM EQU 7
|
||||
USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
|
||||
USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
|
||||
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
/* USBFS_ep_2 */
|
||||
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
USBFS_ep_2__INTC_MASK EQU 0x02
|
||||
USBFS_ep_2__INTC_NUMBER EQU 1
|
||||
USBFS_ep_2__INTC_MASK EQU 0x04
|
||||
USBFS_ep_2__INTC_NUMBER EQU 2
|
||||
USBFS_ep_2__INTC_PRIOR_NUM EQU 7
|
||||
USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
|
||||
USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
|
||||
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
|
|
@ -2722,7 +2754,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
|
|||
CYDEV_ECC_ENABLE EQU 0
|
||||
CYDEV_HEAP_SIZE EQU 0x1000
|
||||
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
|
||||
CYDEV_INTR_RISING EQU 0x00000000
|
||||
CYDEV_INTR_RISING EQU 0x00000001
|
||||
CYDEV_PROJ_TYPE EQU 2
|
||||
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
|
||||
CYDEV_PROJ_TYPE_LOADABLE EQU 2
|
||||
|
|
|
|||
|
|
@ -3,6 +3,34 @@ INCLUDED_CYFITTERRV_INC EQU 1
|
|||
GET cydevicerv.inc
|
||||
GET cydevicerv_trm.inc
|
||||
|
||||
; SCSI_CMD_TIMER_TimerHW
|
||||
SCSI_CMD_TIMER_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
|
||||
SCSI_CMD_TIMER_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
|
||||
SCSI_CMD_TIMER_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
|
||||
SCSI_CMD_TIMER_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
|
||||
SCSI_CMD_TIMER_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
|
||||
SCSI_CMD_TIMER_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
|
||||
SCSI_CMD_TIMER_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
|
||||
SCSI_CMD_TIMER_TimerHW__PER0 EQU CYREG_TMR0_PER0
|
||||
SCSI_CMD_TIMER_TimerHW__PER1 EQU CYREG_TMR0_PER1
|
||||
SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
|
||||
SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK EQU 0x01
|
||||
SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
|
||||
SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK EQU 0x01
|
||||
SCSI_CMD_TIMER_TimerHW__RT0 EQU CYREG_TMR0_RT0
|
||||
SCSI_CMD_TIMER_TimerHW__RT1 EQU CYREG_TMR0_RT1
|
||||
SCSI_CMD_TIMER_TimerHW__SR0 EQU CYREG_TMR0_SR0
|
||||
|
||||
; SCSI_CMD_TIMER_ISR
|
||||
SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
SCSI_CMD_TIMER_ISR__INTC_MASK EQU 0x01
|
||||
SCSI_CMD_TIMER_ISR__INTC_NUMBER EQU 0
|
||||
SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM EQU 7
|
||||
SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
|
||||
SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
; USBFS_bus_reset
|
||||
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
|
|
@ -504,8 +532,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
|
|||
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
|
||||
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
|
||||
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_RxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
|
||||
|
|
@ -513,13 +541,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
|
|||
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
|
||||
SDCard_BSPIM_RxStsReg__6__POS EQU 6
|
||||
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
|
||||
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
|
||||
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
|
||||
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
|
||||
SDCard_BSPIM_TxStsReg__0__POS EQU 0
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
|
||||
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
|
||||
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
|
||||
SDCard_BSPIM_TxStsReg__1__POS EQU 1
|
||||
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
|
||||
|
|
@ -529,9 +557,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
|
|||
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
|
||||
SDCard_BSPIM_TxStsReg__4__POS EQU 4
|
||||
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
|
||||
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
|
||||
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
|
||||
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
|
||||
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
|
||||
|
|
@ -565,24 +593,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
|||
; SCSI_CTL_IO
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
|
||||
SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
|
||||
|
||||
; SCSI_In_DBx
|
||||
SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG
|
||||
|
|
@ -1041,8 +1069,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02
|
|||
; scsiTarget
|
||||
scsiTarget_StatusReg__0__MASK EQU 0x01
|
||||
scsiTarget_StatusReg__0__POS EQU 0
|
||||
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
|
||||
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST
|
||||
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
|
||||
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
|
||||
scsiTarget_StatusReg__1__MASK EQU 0x02
|
||||
scsiTarget_StatusReg__1__POS EQU 1
|
||||
scsiTarget_StatusReg__2__MASK EQU 0x04
|
||||
|
|
@ -1050,76 +1078,80 @@ scsiTarget_StatusReg__2__POS EQU 2
|
|||
scsiTarget_StatusReg__3__MASK EQU 0x08
|
||||
scsiTarget_StatusReg__3__POS EQU 3
|
||||
scsiTarget_StatusReg__MASK EQU 0x0F
|
||||
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK
|
||||
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
|
||||
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST
|
||||
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
|
||||
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK
|
||||
scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST
|
||||
scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
|
||||
scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
|
||||
scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL
|
||||
scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL
|
||||
scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
|
||||
scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK
|
||||
scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0
|
||||
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1
|
||||
scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0
|
||||
scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1
|
||||
scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
|
||||
scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0
|
||||
scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1
|
||||
scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1
|
||||
scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0
|
||||
scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1
|
||||
scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1
|
||||
scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0
|
||||
scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1
|
||||
scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
|
||||
scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1
|
||||
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0
|
||||
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1
|
||||
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
|
||||
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
|
||||
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
|
||||
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
|
||||
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
|
||||
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK
|
||||
scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
|
||||
scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST
|
||||
scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
|
||||
scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
|
||||
scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
|
||||
scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL
|
||||
scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL
|
||||
scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
|
||||
scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK
|
||||
scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0
|
||||
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1
|
||||
scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0
|
||||
scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1
|
||||
scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
|
||||
scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0
|
||||
scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1
|
||||
scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1
|
||||
scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0
|
||||
scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1
|
||||
scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1
|
||||
scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0
|
||||
scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1
|
||||
scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
|
||||
scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1
|
||||
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0
|
||||
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1
|
||||
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
|
||||
|
||||
; SD_Clk_Ctl
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
|
||||
SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
|
||||
|
||||
; USBFS_ep_0
|
||||
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
|
|
@ -1134,20 +1166,20 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
|||
; USBFS_ep_1
|
||||
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
USBFS_ep_1__INTC_MASK EQU 0x01
|
||||
USBFS_ep_1__INTC_NUMBER EQU 0
|
||||
USBFS_ep_1__INTC_MASK EQU 0x02
|
||||
USBFS_ep_1__INTC_NUMBER EQU 1
|
||||
USBFS_ep_1__INTC_PRIOR_NUM EQU 7
|
||||
USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
|
||||
USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
|
||||
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
; USBFS_ep_2
|
||||
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
|
||||
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
|
||||
USBFS_ep_2__INTC_MASK EQU 0x02
|
||||
USBFS_ep_2__INTC_NUMBER EQU 1
|
||||
USBFS_ep_2__INTC_MASK EQU 0x04
|
||||
USBFS_ep_2__INTC_NUMBER EQU 2
|
||||
USBFS_ep_2__INTC_PRIOR_NUM EQU 7
|
||||
USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
|
||||
USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
|
||||
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
|
||||
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
|
||||
|
||||
|
|
@ -2722,7 +2754,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
|
|||
CYDEV_ECC_ENABLE EQU 0
|
||||
CYDEV_HEAP_SIZE EQU 0x1000
|
||||
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
|
||||
CYDEV_INTR_RISING EQU 0x00000000
|
||||
CYDEV_INTR_RISING EQU 0x00000001
|
||||
CYDEV_PROJ_TYPE EQU 2
|
||||
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
|
||||
CYDEV_PROJ_TYPE_LOADABLE EQU 2
|
||||
|
|
|
|||
|
|
@ -58,6 +58,8 @@
|
|||
#include <USBFS_midi.h>
|
||||
#include <USBFS_pvt.h>
|
||||
#include <Bootloadable_1.h>
|
||||
#include <SCSI_CMD_TIMER.h>
|
||||
#include <SCSI_CMD_TIMER_ISR.h>
|
||||
#include <USBFS_Dm_aliases.h>
|
||||
#include <USBFS_Dm.h>
|
||||
#include <USBFS_Dp_aliases.h>
|
||||
|
|
|
|||
|
|
@ -1,12 +1,79 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
|
||||
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
</block>
|
||||
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_CMD_TIMER_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_CMD_TIMER" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<register name="SCSI_CMD_TIMER_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">
|
||||
<field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />
|
||||
</register>
|
||||
<register name="SCSI_CMD_TIMER_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">
|
||||
<field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />
|
||||
<field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">
|
||||
<value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
|
||||
<value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
|
||||
</field>
|
||||
<field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />
|
||||
<field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />
|
||||
<field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />
|
||||
<field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">
|
||||
<value name="Timer" value="0" desc="CMP and TC are output." />
|
||||
<value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
|
||||
</field>
|
||||
<field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />
|
||||
</register>
|
||||
<register name="SCSI_CMD_TIMER_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">
|
||||
<field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />
|
||||
<field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">
|
||||
<value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
|
||||
<value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
|
||||
</field>
|
||||
<field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />
|
||||
<field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />
|
||||
<field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />
|
||||
<field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />
|
||||
</register>
|
||||
<register name="SCSI_CMD_TIMER_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">
|
||||
<field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">
|
||||
<value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
|
||||
<value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
|
||||
<value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
|
||||
<value name="Irq" value="11" desc="Timer runs until IRQ." />
|
||||
</field>
|
||||
<field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />
|
||||
<field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />
|
||||
<field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">
|
||||
<value name="Equal" value="0" desc="Compare Equal " />
|
||||
<value name="Less than" value="1" desc="Compare Less Than " />
|
||||
<value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
|
||||
<value name="Greater" value="11" desc="Compare Greater Than ." />
|
||||
<value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
|
||||
</field>
|
||||
<field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />
|
||||
</register>
|
||||
<register name="SCSI_CMD_TIMER_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
|
||||
<register name="SCSI_CMD_TIMER_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
|
||||
</block>
|
||||
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
|
||||
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
|
|
@ -87,31 +154,24 @@
|
|||
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
|
||||
</block>
|
||||
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
</block>
|
||||
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_Init_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<register name="SD_Clk_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />
|
||||
<register name="SD_Clk_Ctl_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />
|
||||
</block>
|
||||
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
<block name="SCSI_CTL_IO" BASE="0x0" SIZE="0x0" desc="" visible="true">
|
||||
<register name="SCSI_CTL_IO_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />
|
||||
<register name="SCSI_CTL_IO_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />
|
||||
</block>
|
||||
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
|
||||
</blockRegMap>
|
||||
Binary file not shown.
|
|
@ -2318,6 +2318,75 @@
|
|||
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
|
||||
<filters />
|
||||
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
|
||||
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
|
||||
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CMD_TIMER" persistent="">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
|
||||
<dependencies>
|
||||
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CMD_TIMER.c" persistent=".\Generated_Source\PSoC5\SCSI_CMD_TIMER.c">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="ARM_C_FILE" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
|
||||
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CMD_TIMER.h" persistent=".\Generated_Source\PSoC5\SCSI_CMD_TIMER.h">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="NONE" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
|
||||
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CMD_TIMER_PM.c" persistent=".\Generated_Source\PSoC5\SCSI_CMD_TIMER_PM.c">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="ARM_C_FILE" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
|
||||
</dependencies>
|
||||
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
|
||||
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
|
||||
<filters />
|
||||
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
|
||||
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
|
||||
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CMD_TIMER_ISR" persistent="">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
|
||||
<dependencies>
|
||||
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CMD_TIMER_ISR.c" persistent=".\Generated_Source\PSoC5\SCSI_CMD_TIMER_ISR.c">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="ARM_C_FILE" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
|
||||
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
|
||||
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
|
||||
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CMD_TIMER_ISR.h" persistent=".\Generated_Source\PSoC5\SCSI_CMD_TIMER_ISR.h">
|
||||
<Hidden v="False" />
|
||||
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
|
||||
<build_action v="NONE" />
|
||||
<PropertyDeltas />
|
||||
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
|
||||
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
|
||||
</dependencies>
|
||||
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
|
||||
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
|
||||
<filters />
|
||||
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
|
||||
</dependencies>
|
||||
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
|
||||
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
|
||||
|
|
|
|||
|
|
@ -6,6 +6,298 @@
|
|||
<addressUnitBits>8</addressUnitBits>
|
||||
<width>32</width>
|
||||
<peripherals>
|
||||
<peripheral>
|
||||
<name>SCSI_CMD_TIMER</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x400043A3</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0xB64</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>SCSI_CMD_TIMER_GLOBAL_ENABLE</name>
|
||||
<description>PM.ACT.CFG</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>en_timer</name>
|
||||
<description>Enable timer/counters.</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SCSI_CMD_TIMER_CONTROL</name>
|
||||
<description>TMRx.CFG0</description>
|
||||
<addressOffset>0xB5D</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>EN</name>
|
||||
<description>Enables timer/comparator.</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>0</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>MODE</name>
|
||||
<description>Mode. (0 = Timer; 1 = Comparator)</description>
|
||||
<lsb>1</lsb>
|
||||
<msb>1</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Timer</name>
|
||||
<description>Timer mode. CNT/CMP register holds timer count value.</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Comparator</name>
|
||||
<description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>ONESHOT</name>
|
||||
<description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
|
||||
<lsb>2</lsb>
|
||||
<msb>2</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>CMP_BUFF</name>
|
||||
<description>Buffer compare register. Compare register updates only on timer terminal count.</description>
|
||||
<lsb>3</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>INV</name>
|
||||
<description>Invert sense of TIMEREN signal</description>
|
||||
<lsb>4</lsb>
|
||||
<msb>4</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>DB</name>
|
||||
<description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
|
||||
<lsb>5</lsb>
|
||||
<msb>5</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Timer</name>
|
||||
<description>CMP and TC are output.</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Deadband</name>
|
||||
<description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>DEADBAND_PERIOD</name>
|
||||
<description>Deadband Period</description>
|
||||
<lsb>6</lsb>
|
||||
<msb>7</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SCSI_CMD_TIMER_CONTROL2</name>
|
||||
<description>TMRx.CFG1</description>
|
||||
<addressOffset>0xB5E</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>IRQ_SEL</name>
|
||||
<description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>0</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>FTC</name>
|
||||
<description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
|
||||
<lsb>1</lsb>
|
||||
<msb>1</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Disable_FTC</name>
|
||||
<description>Disable the single cycle pulse, which signifies the timer is starting.</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Enable_FTC</name>
|
||||
<description>Enable the single cycle pulse, which signifies the timer is starting.</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>DCOR</name>
|
||||
<description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
|
||||
<lsb>2</lsb>
|
||||
<msb>2</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>DBMODE</name>
|
||||
<description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
|
||||
<lsb>3</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>CLK_BUS_EN_SEL</name>
|
||||
<description>Digital Global Clock selection.</description>
|
||||
<lsb>4</lsb>
|
||||
<msb>6</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>BUS_CLK_SEL</name>
|
||||
<description>Bus Clock selection.</description>
|
||||
<lsb>7</lsb>
|
||||
<msb>7</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SCSI_CMD_TIMER_CONTROL3_</name>
|
||||
<description>TMRx.CFG2</description>
|
||||
<addressOffset>0xB5F</addressOffset>
|
||||
<size>8</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
<fields>
|
||||
<field>
|
||||
<name>TMR_CFG</name>
|
||||
<description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>1</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Continuous</name>
|
||||
<description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Pulsewidth</name>
|
||||
<description>Timer runs from positive to negative edge of TIMEREN.</description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Period</name>
|
||||
<description>Timer runs from positive to positive edge of TIMEREN.</description>
|
||||
<value>2</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Irq</name>
|
||||
<description>Timer runs until IRQ.</description>
|
||||
<value>3</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>COD</name>
|
||||
<description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
|
||||
<lsb>2</lsb>
|
||||
<msb>2</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>ROD</name>
|
||||
<description>Reset On Disable (ROD). Resets internal state of output logic</description>
|
||||
<lsb>3</lsb>
|
||||
<msb>3</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
<field>
|
||||
<name>CMP_CFG</name>
|
||||
<description>Comparator configurations</description>
|
||||
<lsb>4</lsb>
|
||||
<msb>6</msb>
|
||||
<access>read-write</access>
|
||||
<enumeratedValues>
|
||||
<enumeratedValue>
|
||||
<name>Equal</name>
|
||||
<description>Compare Equal </description>
|
||||
<value>0</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Less_than</name>
|
||||
<description>Compare Less Than </description>
|
||||
<value>1</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Less_than_or_equal</name>
|
||||
<description>Compare Less Than or Equal .</description>
|
||||
<value>2</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Greater</name>
|
||||
<description>Compare Greater Than .</description>
|
||||
<value>3</value>
|
||||
</enumeratedValue>
|
||||
<enumeratedValue>
|
||||
<name>Greater_than_or_equal</name>
|
||||
<description>Compare Greater Than or Equal </description>
|
||||
<value>4</value>
|
||||
</enumeratedValue>
|
||||
</enumeratedValues>
|
||||
</field>
|
||||
<field>
|
||||
<name>HW_EN</name>
|
||||
<description>When set Timer Enable controls counting.</description>
|
||||
<lsb>7</lsb>
|
||||
<msb>7</msb>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SCSI_CMD_TIMER_PERIOD</name>
|
||||
<description>TMRx.PER0 - Assigned Period</description>
|
||||
<addressOffset>0xB61</addressOffset>
|
||||
<size>16</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
<register>
|
||||
<name>SCSI_CMD_TIMER_COUNTER</name>
|
||||
<description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
|
||||
<addressOffset>0xB63</addressOffset>
|
||||
<size>16</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0</resetValue>
|
||||
<resetMask>0</resetMask>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>USBFS</name>
|
||||
<description>USBFS</description>
|
||||
|
|
@ -493,7 +785,7 @@
|
|||
<peripheral>
|
||||
<name>SD_Clk_Ctl</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x4000647A</baseAddress>
|
||||
<baseAddress>0x4000647C</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x1</size>
|
||||
|
|
@ -514,7 +806,7 @@
|
|||
<peripheral>
|
||||
<name>SCSI_CTL_IO</name>
|
||||
<description>No description available</description>
|
||||
<baseAddress>0x4000647B</baseAddress>
|
||||
<baseAddress>0x40006471</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x1</size>
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -46,18 +46,23 @@ static void process_Command(void);
|
|||
|
||||
static void doReserveRelease(void);
|
||||
|
||||
static uint8_t CmdTimerComplete = 0;
|
||||
CY_ISR(CommandTimerISR)
|
||||
{
|
||||
CmdTimerComplete = 1;
|
||||
}
|
||||
|
||||
static void enter_BusFree()
|
||||
{
|
||||
// TODO MPC3000 testing.
|
||||
// Spin until the 10us timer has stopped.
|
||||
// Required for Akai MPC3000, and possibly other broken controllers.
|
||||
// 1,2us: Cannot see SCSI device.
|
||||
// 5us: Can see SCSI device, format fails
|
||||
// 10us: Format succeeds.
|
||||
// 25us: Format fails.
|
||||
CyDelayUs(10);
|
||||
|
||||
|
||||
|
||||
|
||||
while (!CmdTimerComplete) {}
|
||||
SCSI_CMD_TIMER_Stop();
|
||||
|
||||
SCSI_ClearPin(SCSI_Out_BSY);
|
||||
// We now have a Bus Clear Delay of 800ns to release remaining signals.
|
||||
SCSI_ClearPin(SCSI_Out_MSG);
|
||||
|
|
@ -406,6 +411,8 @@ static void scsiReset()
|
|||
scsiDev.sense.code = NO_SENSE;
|
||||
scsiDev.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION;
|
||||
scsiDiskReset();
|
||||
|
||||
SCSI_CMD_TIMER_Stop();
|
||||
|
||||
// Sleep to allow the bus to settle down a bit.
|
||||
// We must be ready again within the "Reset to selection time" of
|
||||
|
|
@ -461,6 +468,11 @@ static void process_SelectionPhase()
|
|||
// for our BSY response, which is actually a very generous 250ms)
|
||||
SCSI_SetPin(SCSI_Out_BSY);
|
||||
ledOn();
|
||||
|
||||
// Used in enter_BusFree() to ensure each command takes at least 10us.
|
||||
// as required by some old SCSI controllers (MPC3000).
|
||||
CmdTimerComplete = 0;
|
||||
SCSI_CMD_TIMER_Enable();
|
||||
|
||||
#ifdef MM_DEBUG
|
||||
scsiDev.selCount++;
|
||||
|
|
@ -759,6 +771,9 @@ void scsiPoll(void)
|
|||
|
||||
void scsiInit()
|
||||
{
|
||||
SCSI_CMD_TIMER_Init(); // config but don't start the timeout counter
|
||||
SCSI_CMD_TIMER_ISR_StartEx(CommandTimerISR); // setup timer interrupt sub-routine
|
||||
|
||||
scsiDev.scsiIdMask = 1 << (config->scsiId);
|
||||
|
||||
scsiDev.atnFlag = 0;
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
// Set this to true to log SCSI commands and status information via
|
||||
// USB HID packets. The can be captured and viewed in wireshark.
|
||||
// For windows users, capture using USBPcap http://desowin.org/usbpcap/
|
||||
#define MM_DEBUG 0
|
||||
#define MM_DEBUG 1
|
||||
|
||||
#include "geometry.h"
|
||||
#include "sense.h"
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user